mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Revision 174:b96e65c34a4d, committed 2017-10-02
- Comitter:
- AnnaBridge
- Date:
- Mon Oct 02 15:33:19 2017 +0100
- Parent:
- 173:e131a1973e81
- Child:
- 175:af195413fb11
- Commit message:
- This updates the lib to the mbed lib v 152
Changed in this revision
--- a/cmsis/TARGET_CORTEX_M/cmsis_compiler.h Fri Sep 15 14:59:18 2017 +0100
+++ b/cmsis/TARGET_CORTEX_M/cmsis_compiler.h Mon Oct 02 15:33:19 2017 +0100
@@ -78,6 +78,14 @@
#ifndef __ARM_ARCH_7EM__
#define __ARM_ARCH_7EM__ 1
#endif
+ #elif (__CORE__ == __ARM8M_BASELINE__)
+ #ifndef __ARM_ARCH_8M_BASE__
+ #define __ARM_ARCH_8M_BASE__ 1
+ #endif
+ #elif (__CORE__ == __ARM8M_MAINLINE__)
+ #ifndef __ARM_ARCH_8M_MAIN__
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #endif
#endif
// IAR version 7.8.1 and earlier do not include __ALIGNED
--- a/drivers/CAN.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/CAN.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -18,16 +18,15 @@
#if DEVICE_CAN
#include "cmsis.h"
+#include "platform/mbed_sleep.h"
namespace mbed {
-static void donothing() {}
-
CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
// No lock needed in constructor
for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
- _irq[i] = callback(donothing);
+ _irq[i] = NULL;
}
can_init(&_can, rd, td);
@@ -38,7 +37,7 @@
// No lock needed in constructor
for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
- _irq[i].attach(donothing);
+ _irq[i] = NULL;
}
can_init_freq(&_can, rd, td, hz);
@@ -115,10 +114,18 @@
void CAN::attach(Callback<void()> func, IrqType type) {
lock();
if (func) {
+ // lock deep sleep only the first time
+ if (!_irq[(CanIrqType)type]) {
+ sleep_manager_lock_deep_sleep();
+ }
_irq[(CanIrqType)type] = func;
can_irq_set(&_can, (CanIrqType)type, 1);
} else {
- _irq[(CanIrqType)type] = callback(donothing);
+ // unlock deep sleep only the first time
+ if (_irq[(CanIrqType)type]) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _irq[(CanIrqType)type] = NULL;
can_irq_set(&_can, (CanIrqType)type, 0);
}
unlock();
@@ -126,7 +133,9 @@
void CAN::_irq_handler(uint32_t id, CanIrqType type) {
CAN *handler = (CAN*)id;
- handler->_irq[type].call();
+ if (handler->_irq[type]) {
+ handler->_irq[type].call();
+ }
}
void CAN::lock() {
--- a/drivers/CAN.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/CAN.h Mon Oct 02 15:33:19 2017 +0100
@@ -235,7 +235,9 @@
/** Attach a function to call whenever a CAN frame received interrupt is
* generated.
- *
+ *
+ * This function locks the deep sleep while a callback is attached
+ *
* @param func A pointer to a void function, or 0 to set as none
* @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
*/
--- a/drivers/FlashIAP.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/FlashIAP.h Mon Oct 02 15:33:19 2017 +0100
@@ -112,6 +112,7 @@
/** Get the program page size
*
+ * The page size defines the writable page size
* @return Size of a program page in bytes
*/
uint32_t get_page_size() const;
--- a/drivers/I2C.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/I2C.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -17,6 +17,10 @@
#if DEVICE_I2C
+#if DEVICE_I2C_ASYNCH
+#include "platform/mbed_sleep.h"
+#endif
+
namespace mbed {
I2C *I2C::_owner = NULL;
@@ -129,6 +133,7 @@
unlock();
return -1; // transaction ongoing
}
+ sleep_manager_lock_deep_sleep();
aquire();
_callback = callback;
@@ -143,6 +148,7 @@
{
lock();
i2c_abort_asynch(&_i2c);
+ sleep_manager_unlock_deep_sleep();
unlock();
}
@@ -152,6 +158,9 @@
if (_callback && event) {
_callback.call(event);
}
+ if (event) {
+ sleep_manager_unlock_deep_sleep();
+ }
}
--- a/drivers/I2C.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/I2C.h Mon Oct 02 15:33:19 2017 +0100
@@ -159,6 +159,8 @@
/** Start non-blocking I2C transfer.
*
+ * This function locks the deep sleep until any event has occured
+ *
* @param address 8/10 bit I2c slave address
* @param tx_buffer The TX buffer with data to be transfered
* @param tx_length The length of TX buffer in bytes
--- a/drivers/SPI.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/SPI.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -16,6 +16,10 @@
#include "drivers/SPI.h"
#include "platform/mbed_critical.h"
+#if DEVICE_SPI_ASYNCH
+#include "platform/mbed_sleep.h"
+#endif
+
#if DEVICE_SPI
namespace mbed {
@@ -136,6 +140,7 @@
void SPI::abort_transfer()
{
spi_abort_asynch(&_spi);
+ sleep_manager_unlock_deep_sleep();
#if TRANSACTION_QUEUE_SIZE_SPI
dequeue_transaction();
#endif
@@ -195,6 +200,7 @@
void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
{
+ sleep_manager_lock_deep_sleep();
_acquire();
_callback = callback;
_irq.callback(&SPI::irq_handler_asynch);
@@ -224,6 +230,7 @@
{
int event = spi_irq_handler_asynch(&_spi);
if (_callback && (event & SPI_EVENT_ALL)) {
+ sleep_manager_unlock_deep_sleep();
_callback.call(event & SPI_EVENT_ALL);
}
#if TRANSACTION_QUEUE_SIZE_SPI
--- a/drivers/SPI.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/SPI.h Mon Oct 02 15:33:19 2017 +0100
@@ -156,6 +156,8 @@
/** Start non-blocking SPI transfer using 8bit buffers.
*
+ * This function locks the deep sleep until any event has occured
+ *
* @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
* the default SPI value is sent
* @param tx_length The length of TX buffer in bytes
--- a/drivers/SerialBase.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/SerialBase.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -16,23 +16,23 @@
#include "drivers/SerialBase.h"
#include "platform/mbed_wait_api.h"
#include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
#if DEVICE_SERIAL
namespace mbed {
-static void donothing() {};
-
SerialBase::SerialBase(PinName tx, PinName rx, int baud) :
#if DEVICE_SERIAL_ASYNCH
_thunk_irq(this), _tx_usage(DMA_USAGE_NEVER),
- _rx_usage(DMA_USAGE_NEVER),
+ _rx_usage(DMA_USAGE_NEVER), _tx_callback(NULL),
+ _rx_callback(NULL),
#endif
_serial(), _baud(baud) {
// No lock needed in the constructor
for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
- _irq[i] = donothing;
+ _irq[i] = NULL;
}
serial_init(&_serial, tx, rx);
@@ -73,10 +73,18 @@
// Disable interrupts when attaching interrupt handler
core_util_critical_section_enter();
if (func) {
+ // lock deep sleep only the first time
+ if (!_irq[type]) {
+ sleep_manager_lock_deep_sleep();
+ }
_irq[type] = func;
serial_irq_set(&_serial, (SerialIrq)type, 1);
} else {
- _irq[type] = donothing;
+ // unlock deep sleep only the first time
+ if (_irq[type]) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _irq[type] = NULL;
serial_irq_set(&_serial, (SerialIrq)type, 0);
}
core_util_critical_section_exit();
@@ -85,7 +93,9 @@
void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
SerialBase *handler = (SerialBase*)id;
- handler->_irq[irq_type]();
+ if (handler->_irq[irq_type]) {
+ handler->_irq[irq_type]();
+ }
}
int SerialBase::_base_getc() {
@@ -173,16 +183,27 @@
_tx_callback = callback;
_thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+ sleep_manager_lock_deep_sleep();
serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage);
}
void SerialBase::abort_write(void)
{
+ // rx might still be active
+ if (_rx_callback) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _tx_callback = NULL;
serial_tx_abort_asynch(&_serial);
}
void SerialBase::abort_read(void)
{
+ // tx might still be active
+ if (_tx_callback) {
+ sleep_manager_unlock_deep_sleep();
+ }
+ _rx_callback = NULL;
serial_rx_abort_asynch(&_serial);
}
@@ -228,6 +249,7 @@
{
_rx_callback = callback;
_thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+ sleep_manager_lock_deep_sleep();
serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage);
}
@@ -235,14 +257,22 @@
{
int event = serial_irq_handler_asynch(&_serial);
int rx_event = event & SERIAL_EVENT_RX_MASK;
+ bool unlock_deepsleep = false;
+
if (_rx_callback && rx_event) {
+ unlock_deepsleep = true;
_rx_callback.call(rx_event);
}
int tx_event = event & SERIAL_EVENT_TX_MASK;
if (_tx_callback && tx_event) {
+ unlock_deepsleep = true;
_tx_callback.call(tx_event);
}
+ // unlock if tx or rx events are generated
+ if (unlock_deepsleep) {
+ sleep_manager_unlock_deep_sleep();
+ }
}
#endif
--- a/drivers/SerialBase.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/SerialBase.h Mon Oct 02 15:33:19 2017 +0100
@@ -167,6 +167,8 @@
/** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
*
+ * This function locks the deep sleep until any event has occured
+ *
* @param buffer The buffer where received data will be stored
* @param length The buffer length in bytes
* @param callback The event callback function
@@ -176,6 +178,8 @@
/** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
*
+ * This function locks the deep sleep until any event has occured
+ *
* @param buffer The buffer where received data will be stored
* @param length The buffer length in bytes
* @param callback The event callback function
@@ -189,6 +193,8 @@
/** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
*
+ * This function locks the deep sleep until any event has occured
+ *
* @param buffer The buffer where received data will be stored
* @param length The buffer length in bytes
* @param callback The event callback function
@@ -199,6 +205,8 @@
/** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
*
+ * This function locks the deep sleep until any event has occured
+ *
* @param buffer The buffer where received data will be stored
* @param length The buffer length in bytes
* @param callback The event callback function
@@ -241,10 +249,10 @@
#if DEVICE_SERIAL_ASYNCH
CThunk<SerialBase> _thunk_irq;
+ DMAUsage _tx_usage;
+ DMAUsage _rx_usage;
event_callback_t _tx_callback;
event_callback_t _rx_callback;
- DMAUsage _tx_usage;
- DMAUsage _rx_usage;
#endif
serial_t _serial;
--- a/drivers/Ticker.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/Ticker.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -25,6 +25,10 @@
void Ticker::detach() {
core_util_critical_section_enter();
remove();
+ // unlocked only if we were attached (we locked it)
+ if (_function) {
+ sleep_manager_unlock_deep_sleep();
+ }
_function = 0;
core_util_critical_section_exit();
}
@@ -39,7 +43,9 @@
void Ticker::handler() {
insert_absolute(event.timestamp + _delay);
- _function();
+ if (_function) {
+ _function();
+ }
}
} // namespace mbed
--- a/drivers/Ticker.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/Ticker.h Mon Oct 02 15:33:19 2017 +0100
@@ -20,6 +20,7 @@
#include "platform/Callback.h"
#include "platform/mbed_toolchain.h"
#include "platform/NonCopyable.h"
+#include "platform/mbed_sleep.h"
namespace mbed {
/** \addtogroup drivers */
@@ -63,10 +64,10 @@
class Ticker : public TimerEvent, private NonCopyable<Ticker> {
public:
- Ticker() : TimerEvent() {
+ Ticker() : TimerEvent(), _function(0) {
}
- Ticker(const ticker_data_t *data) : TimerEvent(data) {
+ Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0) {
data->interface->init();
}
@@ -102,6 +103,10 @@
* @param t the time between calls in micro-seconds
*/
void attach_us(Callback<void()> func, us_timestamp_t t) {
+ // lock only for the initial callback setup
+ if (!_function) {
+ sleep_manager_lock_deep_sleep();
+ }
_function = func;
setup(t);
}
--- a/drivers/Timeout.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/Timeout.h Mon Oct 02 15:33:19 2017 +0100
@@ -18,6 +18,7 @@
#include "drivers/Ticker.h"
#include "platform/NonCopyable.h"
+#include "platform/mbed_sleep.h"
namespace mbed {
/** \addtogroup drivers */
--- a/drivers/Timer.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/Timer.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -31,6 +31,7 @@
void Timer::start() {
core_util_critical_section_enter();
if (!_running) {
+ sleep_manager_lock_deep_sleep();
_start = ticker_read_us(_ticker_data);
_running = 1;
}
@@ -40,6 +41,9 @@
void Timer::stop() {
core_util_critical_section_enter();
_time += slicetime();
+ if (_running) {
+ sleep_manager_unlock_deep_sleep();
+ }
_running = 0;
core_util_critical_section_exit();
}
--- a/drivers/Timer.h Fri Sep 15 14:59:18 2017 +0100
+++ b/drivers/Timer.h Mon Oct 02 15:33:19 2017 +0100
@@ -19,6 +19,7 @@
#include "platform/platform.h"
#include "hal/ticker_api.h"
#include "platform/NonCopyable.h"
+#include "platform/mbed_sleep.h"
namespace mbed {
/** \addtogroup drivers */
--- a/hal/flash_api.h Fri Sep 15 14:59:18 2017 +0100 +++ b/hal/flash_api.h Mon Oct 02 15:33:19 2017 +0100 @@ -75,9 +75,9 @@ */ int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size); -/** Program one page starting at defined address +/** Program pages starting at defined address * - * The page should be at page boundary, should not cross multiple sectors. + * The pages should not cross multiple sectors. * This function does not do any check for address alignments or if size is aligned to a page size. * @param obj The flash object * @param address The sector starting address @@ -97,6 +97,7 @@ /** Get page size * + * The page size defines the writable page size * @param obj The flash object * @return The size of a page */
--- a/hal/lp_ticker_api.h Fri Sep 15 14:59:18 2017 +0100 +++ b/hal/lp_ticker_api.h Mon Oct 02 15:33:19 2017 +0100 @@ -74,6 +74,12 @@ */ void lp_ticker_clear_interrupt(void); +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + */ +void lp_ticker_fire_interrupt(void); + /**@}*/ #ifdef __cplusplus
--- a/hal/mbed_lp_ticker_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/hal/mbed_lp_ticker_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -25,6 +25,7 @@
.disable_interrupt = lp_ticker_disable_interrupt,
.clear_interrupt = lp_ticker_clear_interrupt,
.set_interrupt = lp_ticker_set_interrupt,
+ .fire_interrupt = lp_ticker_fire_interrupt,
};
static const ticker_data_t lp_data = {
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_sleep_manager.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_sleep.h"
+#include "mbed_critical.h"
+#include "sleep_api.h"
+#include "mbed_error.h"
+#include <limits.h>
+
+#if DEVICE_SLEEP
+
+// deep sleep locking counter. A target is allowed to deep sleep if counter == 0
+static uint16_t deep_sleep_lock = 0U;
+
+void sleep_manager_lock_deep_sleep(void)
+{
+ core_util_critical_section_enter();
+ if (deep_sleep_lock == USHRT_MAX) {
+ core_util_critical_section_exit();
+ error("Deep sleep lock would overflow (> USHRT_MAX)");
+ }
+ core_util_atomic_incr_u16(&deep_sleep_lock, 1);
+ core_util_critical_section_exit();
+}
+
+void sleep_manager_unlock_deep_sleep(void)
+{
+ core_util_critical_section_enter();
+ if (deep_sleep_lock == 0) {
+ core_util_critical_section_exit();
+ error("Deep sleep lock would underflow (< 0)");
+ }
+ core_util_atomic_decr_u16(&deep_sleep_lock, 1);
+ core_util_critical_section_exit();
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+ return deep_sleep_lock == 0 ? true : false;
+}
+
+void sleep_manager_sleep_auto(void)
+{
+ core_util_critical_section_enter();
+// debug profile should keep debuggers attached, no deep sleep allowed
+#ifdef MBED_DEBUG
+ hal_sleep();
+#else
+ if (sleep_manager_can_deep_sleep()) {
+ hal_deepsleep();
+ } else {
+ hal_sleep();
+ }
+#endif
+ core_util_critical_section_exit();
+}
+
+#else
+
+// locking is valid only if DEVICE_SLEEP is defined
+// we provide empty implementation
+
+void sleep_manager_lock_deep_sleep(void)
+{
+
+}
+
+void sleep_manager_unlock_deep_sleep(void)
+{
+
+}
+
+bool sleep_manager_can_deep_sleep(void)
+{
+ // no sleep implemented
+ return false;
+}
+
+#endif
--- a/hal/mbed_ticker_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/hal/mbed_ticker_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -117,14 +117,23 @@
// if the event at the head of the queue is in the past then schedule
// it immediately.
- if (next_event_timestamp < present) {
- relative_timeout = 0;
+ if (next_event_timestamp <= present) {
+ ticker->interface->fire_interrupt();
+ return;
} else if ((next_event_timestamp - present) < MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA) {
relative_timeout = next_event_timestamp - present;
}
}
- ticker->interface->set_interrupt(ticker->queue->present_time + relative_timeout);
+ us_timestamp_t new_match_time = ticker->queue->present_time + relative_timeout;
+ ticker->interface->set_interrupt(new_match_time);
+ // there could be a delay, reread the time, check if it was set in the past
+ // As result, if it is already in the past, we fire it immediately
+ update_present_time(ticker);
+ us_timestamp_t present = ticker->queue->present_time;
+ if (present >= new_match_time) {
+ ticker->interface->fire_interrupt();
+ }
}
void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
--- a/hal/mbed_us_ticker_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/hal/mbed_us_ticker_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -23,6 +23,7 @@
.disable_interrupt = us_ticker_disable_interrupt,
.clear_interrupt = us_ticker_clear_interrupt,
.set_interrupt = us_ticker_set_interrupt,
+ .fire_interrupt = us_ticker_fire_interrupt,
};
static const ticker_data_t us_data = {
--- a/hal/ticker_api.h Fri Sep 15 14:59:18 2017 +0100
+++ b/hal/ticker_api.h Mon Oct 02 15:33:19 2017 +0100
@@ -60,6 +60,7 @@
void (*disable_interrupt)(void); /**< Disable interrupt function */
void (*clear_interrupt)(void); /**< Clear interrupt function */
void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+ void (*fire_interrupt)(void); /**< Fire interrupt right-away */
} ticker_interface_t;
/** Ticker's event queue structure
--- a/hal/us_ticker_api.h Fri Sep 15 14:59:18 2017 +0100 +++ b/hal/us_ticker_api.h Mon Oct 02 15:33:19 2017 +0100 @@ -72,6 +72,12 @@ */ void us_ticker_clear_interrupt(void); +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + */ +void us_ticker_fire_interrupt(void); + /**@}*/ #ifdef __cplusplus
--- a/mbed.h Fri Sep 15 14:59:18 2017 +0100 +++ b/mbed.h Mon Oct 02 15:33:19 2017 +0100 @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 151 +#define MBED_LIBRARY_VERSION 152 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 -#define MBED_MINOR_VERSION 5 -#define MBED_PATCH_VERSION 7 +#define MBED_MINOR_VERSION 6 +#define MBED_PATCH_VERSION 1 #else // mbed 2 @@ -107,6 +107,8 @@ #include "platform/FileSystemHandle.h" #include "platform/FileHandle.h" #include "platform/DirHandle.h" +#include "platform/CriticalSectionLock.h" +#include "platform/DeepSleepLock.h" // mbed Non-hardware components #include "platform/Callback.h"
--- a/platform/CThunk.h Fri Sep 15 14:59:18 2017 +0100 +++ b/platform/CThunk.h Mon Oct 02 15:33:19 2017 +0100 @@ -37,7 +37,8 @@ #define CTHUNK_ADDRESS 1 #define CTHUNK_VARIABLES volatile uint32_t code[2] -#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7) || defined(__CORTEX_A9)) +#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7) || defined(__CORTEX_A9) \ + || defined(__CORTEX_M23) || defined(__CORTEX_M33)) /** * CTHUNK disassembly for Cortex-M3/M4/M7/A9 (thumb2): * * adr r0, #4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/CriticalSectionLock.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,71 @@
+/*
+ * PackageLicenseDeclared: Apache-2.0
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CRITICALSECTIONLOCK_H
+#define MBED_CRITICALSECTIONLOCK_H
+
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+/** RAII object for disabling, then restoring, interrupt state
+ * Usage:
+ * @code
+ *
+ * void f() {
+ * // some code here
+ * {
+ * CriticalSectionLock lock;
+ * // Code in this block will run with interrupts disabled
+ * }
+ * // interrupts will be restored to their previous state
+ * }
+ * @endcode
+ */
+class CriticalSectionLock {
+public:
+ CriticalSectionLock()
+ {
+ core_util_critical_section_enter();
+ }
+
+ ~CriticalSectionLock()
+ {
+ core_util_critical_section_exit();
+ }
+
+ /** Mark the start of a critical section
+ *
+ */
+ void lock()
+ {
+ core_util_critical_section_enter();
+ }
+
+ /** Mark the end of a critical section
+ *
+ */
+ void unlock()
+ {
+ core_util_critical_section_exit();
+ }
+};
+
+
+} // namespace mbed
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/DeepSleepLock.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEEPSLEEPLOCK_H
+#define MBED_DEEPSLEEPLOCK_H
+
+#include "platform/mbed_sleep.h"
+
+namespace mbed {
+
+
+/** RAII object for disabling, then restoring the deep sleep mode
+ * Usage:
+ * @code
+ *
+ * void f() {
+ * // some code here
+ * {
+ * DeepSleepLock lock;
+ * // Code in this block will run with the deep sleep mode locked
+ * }
+ * // deep sleep mode will be restored to their previous state
+ * }
+ * @endcode
+ */
+class DeepSleepLock {
+public:
+ DeepSleepLock()
+ {
+ sleep_manager_lock_deep_sleep();
+ }
+
+ ~DeepSleepLock()
+ {
+ sleep_manager_unlock_deep_sleep();
+ }
+
+ /** Mark the start of a locked deep sleep section
+ */
+ void lock()
+ {
+ sleep_manager_lock_deep_sleep();
+ }
+
+ /** Mark the end of a locked deep sleep section
+ */
+ void unlock()
+ {
+ sleep_manager_unlock_deep_sleep();
+ }
+};
+
+}
+
+#endif
--- a/platform/mbed_alloc_wrappers.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/platform/mbed_alloc_wrappers.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -207,26 +207,46 @@
/******************************************************************************/
-/* ARMCC memory allocation wrappers */
+/* ARMCC / IAR memory allocation wrappers */
/******************************************************************************/
-#elif defined(TOOLCHAIN_ARM) // #if defined(TOOLCHAIN_GCC)
+#elif defined(TOOLCHAIN_ARM) || defined(__ICCARM__)
+
+#if defined(TOOLCHAIN_ARM)
+#define SUPER_MALLOC $Super$$malloc
+#define SUB_MALLOC $Sub$$malloc
+#define SUPER_REALLOC $Super$$realloc
+#define SUB_REALLOC $Sub$$realloc
+#define SUPER_CALLOC $Super$$calloc
+#define SUB_CALLOC $Sub$$calloc
+#define SUPER_FREE $Super$$free
+#define SUB_FREE $Sub$$free
+#elif defined(__ICCARM__)
+#define SUPER_MALLOC $Super$$__iar_dlmalloc
+#define SUB_MALLOC $Sub$$__iar_dlmalloc
+#define SUPER_REALLOC $Super$$__iar_dlrealloc
+#define SUB_REALLOC $Sub$$__iar_dlrealloc
+#define SUPER_CALLOC $Super$$__iar_dlcalloc
+#define SUB_CALLOC $Sub$$__iar_dlcalloc
+#define SUPER_FREE $Super$$__iar_dlfree
+#define SUB_FREE $Sub$$__iar_dlfree
+#endif
/* Enable hooking of memory function only if tracing is also enabled */
#if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
extern "C" {
- void *$Super$$malloc(size_t size);
- void *$Super$$realloc(void *ptr, size_t size);
- void *$Super$$calloc(size_t nmemb, size_t size);
- void $Super$$free(void *ptr);
+ void *SUPER_MALLOC(size_t size);
+ void *SUPER_REALLOC(void *ptr, size_t size);
+ void *SUPER_CALLOC(size_t nmemb, size_t size);
+ void SUPER_FREE(void *ptr);
}
-extern "C" void* $Sub$$malloc(size_t size) {
+extern "C" void* SUB_MALLOC(size_t size) {
void *ptr = NULL;
#ifdef MBED_HEAP_STATS_ENABLED
malloc_stats_mutex->lock();
- alloc_info_t *alloc_info = (alloc_info_t*)$Super$$malloc(size + sizeof(alloc_info_t));
+ alloc_info_t *alloc_info = (alloc_info_t*)SUPER_MALLOC(size + sizeof(alloc_info_t));
if (alloc_info != NULL) {
alloc_info->size = size;
ptr = (void*)(alloc_info + 1);
@@ -241,7 +261,7 @@
}
malloc_stats_mutex->unlock();
#else // #ifdef MBED_HEAP_STATS_ENABLED
- ptr = $Super$$malloc(size);
+ ptr = SUPER_MALLOC(size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
#ifdef MBED_MEM_TRACING_ENABLED
mem_trace_mutex->lock();
@@ -251,7 +271,7 @@
return ptr;
}
-extern "C" void* $Sub$$realloc(void *ptr, size_t size) {
+extern "C" void* SUB_REALLOC(void *ptr, size_t size) {
void *new_ptr = NULL;
#ifdef MBED_HEAP_STATS_ENABLED
// Note - no lock needed since malloc and free are thread safe
@@ -276,7 +296,7 @@
free(ptr);
}
#else // #ifdef MBED_HEAP_STATS_ENABLED
- new_ptr = $Super$$realloc(ptr, size);
+ new_ptr = SUPER_REALLOC(ptr, size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
#ifdef MBED_MEM_TRACING_ENABLED
mem_trace_mutex->lock();
@@ -286,7 +306,7 @@
return new_ptr;
}
-extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) {
+extern "C" void *SUB_CALLOC(size_t nmemb, size_t size) {
void *ptr = NULL;
#ifdef MBED_HEAP_STATS_ENABLED
// Note - no lock needed since malloc is thread safe
@@ -295,7 +315,7 @@
memset(ptr, 0, nmemb * size);
}
#else // #ifdef MBED_HEAP_STATS_ENABLED
- ptr = $Super$$calloc(nmemb, size);
+ ptr = SUPER_CALLOC(nmemb, size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
#ifdef MBED_MEM_TRACING_ENABLED
mem_trace_mutex->lock();
@@ -305,7 +325,7 @@
return ptr;
}
-extern "C" void $Sub$$free(void *ptr) {
+extern "C" void SUB_FREE(void *ptr) {
#ifdef MBED_HEAP_STATS_ENABLED
malloc_stats_mutex->lock();
alloc_info_t *alloc_info = NULL;
@@ -314,10 +334,10 @@
heap_stats.current_size -= alloc_info->size;
heap_stats.alloc_cnt -= 1;
}
- $Super$$free((void*)alloc_info);
+ SUPER_FREE((void*)alloc_info);
malloc_stats_mutex->unlock();
#else // #ifdef MBED_HEAP_STATS_ENABLED
- $Super$$free(ptr);
+ SUPER_FREE(ptr);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
#ifdef MBED_MEM_TRACING_ENABLED
mem_trace_mutex->lock();
@@ -332,15 +352,14 @@
/* Allocation wrappers for other toolchains are not supported yet */
/******************************************************************************/
-#else // #if defined(TOOLCHAIN_GCC)
+#else
#ifdef MBED_MEM_TRACING_ENABLED
-#warning Memory tracing is not supported with the current toolchain.
+#error Memory tracing is not supported with the current toolchain.
#endif
#ifdef MBED_HEAP_STATS_ENABLED
-#warning Heap statistics are not supported with the current toolchain.
+#error Heap statistics are not supported with the current toolchain.
#endif
#endif // #if defined(TOOLCHAIN_GCC)
-
--- a/platform/mbed_board.c Fri Sep 15 14:59:18 2017 +0100
+++ b/platform/mbed_board.c Mon Oct 02 15:33:19 2017 +0100
@@ -30,39 +30,22 @@
#if !defined (NRF51_H) && !defined(TARGET_EFM32)
core_util_critical_section_enter();
#endif
-#if (DEVICE_ERROR_RED == 1)
- gpio_t led_red; gpio_init_out(&led_red, LED_RED);
-#elif (DEVICE_ERROR_PATTERN == 1)
- gpio_t led_1; gpio_init_out(&led_1, LED1);
- gpio_t led_2; gpio_init_out(&led_2, LED2);
- gpio_t led_3; gpio_init_out(&led_3, LED3);
- gpio_t led_4; gpio_init_out(&led_4, LED4);
-#endif
+ gpio_t led_err; gpio_init_out(&led_err, LED1);
while (1) {
-#if (DEVICE_ERROR_RED == 1)
- gpio_write(&led_red, 1);
-
-#elif (DEVICE_ERROR_PATTERN == 1)
- gpio_write(&led_1, 1);
- gpio_write(&led_2, 0);
- gpio_write(&led_3, 0);
- gpio_write(&led_4, 1);
-#endif
-
- wait_ms(150);
+ for (int i = 0; i < 4; ++i) {
+ gpio_write(&led_err, 1);
+ wait_ms(150);
+ gpio_write(&led_err, 0);
+ wait_ms(150);
+ }
-#if (DEVICE_ERROR_RED == 1)
- gpio_write(&led_red, 0);
-
-#elif (DEVICE_ERROR_PATTERN == 1)
- gpio_write(&led_1, 0);
- gpio_write(&led_2, 1);
- gpio_write(&led_3, 1);
- gpio_write(&led_4, 0);
-#endif
-
- wait_ms(150);
+ for (int i = 0; i < 4; ++i) {
+ gpio_write(&led_err, 1);
+ wait_ms(400);
+ gpio_write(&led_err, 0);
+ wait_ms(400);
+ }
}
}
--- a/platform/mbed_retarget.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/platform/mbed_retarget.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -34,7 +34,12 @@
#include "platform/mbed_retarget.h"
#if defined(__ARMCC_VERSION)
+# if __ARMCC_VERSION >= 6010050
+# include <arm_compat.h>
+# endif
# include <rt_sys.h>
+# include <rt_misc.h>
+# include <stdint.h>
# define PREFIX(x) _sys##x
# define OPEN_MAX _SYS_OPEN
# ifdef __MICROLIB
@@ -334,6 +339,16 @@
#endif
}
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+extern "C" void PREFIX(_exit)(int return_code) {
+ while(1) {}
+}
+
+extern "C" void _ttywrch(int ch) {
+ serial_putc(&stdio_uart, ch);
+}
+#endif
+
#if defined(__ICCARM__)
extern "C" size_t __read (int fh, unsigned char *buffer, size_t length) {
#else
@@ -497,6 +512,26 @@
}
return size;
}
+
+extern "C" char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern "C" MBED_WEAK __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+extern "C" __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ return _mbed_user_setup_stackheap(R0, R1, R2, R3);
+}
+
#endif
@@ -843,7 +878,7 @@
}
int mbed_getc(std::FILE *_file){
-#if defined (__ICCARM__)
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ < 8000000)
/*This is only valid for unbuffered streams*/
int res = std::fgetc(_file);
if (res>=0){
@@ -858,7 +893,7 @@
}
char* mbed_gets(char*s, int size, std::FILE *_file){
-#if defined (__ICCARM__)
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ < 8000000)
/*This is only valid for unbuffered streams*/
char *str = fgets(s,size,_file);
if (str!=NULL){
@@ -884,6 +919,9 @@
extern "C" WEAK void __iar_file_Mtxdst(__iar_Rmtx *mutex) {}
extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {}
extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {}
+#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
+extern "C" WEAK void *__aeabi_read_tp (void) { return NULL ;}
+#endif
#elif defined(__CC_ARM)
// Do nothing
#elif defined (__GNUC__)
--- a/platform/mbed_retarget.h Fri Sep 15 14:59:18 2017 +0100 +++ b/platform/mbed_retarget.h Mon Oct 02 15:33:19 2017 +0100 @@ -120,6 +120,9 @@ #undef EXDEV #define EXDEV 18 /* Cross-device link */ +#undef ENODEV +#define ENODEV 19 + #undef EINVAL #define EINVAL 22 /* Invalid argument */
--- a/platform/mbed_sdk_boot.c Fri Sep 15 14:59:18 2017 +0100 +++ b/platform/mbed_sdk_boot.c Mon Oct 02 15:33:19 2017 +0100 @@ -67,7 +67,7 @@ /* Toolchain specific main code */ -#if defined (__CC_ARM) +#if defined (__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 5010060)) int $Super$$main(void);
--- a/platform/mbed_semihost_api.h Fri Sep 15 14:59:18 2017 +0100
+++ b/platform/mbed_semihost_api.h Mon Oct 02 15:33:19 2017 +0100
@@ -28,7 +28,7 @@
#if DEVICE_SEMIHOST
-#ifndef __CC_ARM
+#if !defined(__CC_ARM) && !defined(__ARMCC_VERSION)
#if defined(__ICCARM__)
static inline int __semihost(int reason, const void *arg) {
--- a/platform/mbed_sleep.h Fri Sep 15 14:59:18 2017 +0100
+++ b/platform/mbed_sleep.h Mon Oct 02 15:33:19 2017 +0100
@@ -20,11 +20,87 @@
#define MBED_SLEEP_H
#include "sleep_api.h"
+#include "mbed_toolchain.h"
+#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
+/** Sleep manager API
+ * The sleep manager provides API to automatically select sleep mode.
+ *
+ * There are two sleep modes:
+ * - sleep
+ * - deepsleep
+ *
+ * Use locking/unlocking deepsleep for drivers that depend on features that
+ * are not allowed (=disabled) during the deepsleep. For instance, high frequency
+ * clocks.
+ *
+ * Example:
+ * @code
+ *
+ * void driver::handler()
+ * {
+ * if (_sensor.get_event()) {
+ * // any event - we are finished, unlock the deepsleep
+ * sleep_manager_unlock_deep_sleep();
+ * _callback();
+ * }
+ * }
+ *
+ * int driver::measure(event_t event, callback_t& callback)
+ * {
+ * _callback = callback;
+ * sleep_manager_lock_deep_sleep();
+ * // start async transaction, we are waiting for an event
+ * return _sensor.start(event, callback);
+ * }
+ * @endcode
+ */
+
+/** Lock the deep sleep mode
+ *
+ * This locks the automatic deep mode selection.
+ * sleep_manager_sleep_auto() will ignore deepsleep mode if
+ * this function is invoked at least once (the internal counter is non-zero)
+ *
+ * Use this locking mechanism for interrupt driven API that are
+ * running in the background and deepsleep could affect their functionality
+ *
+ * The lock is a counter, can be locked up to USHRT_MAX
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_lock_deep_sleep(void);
+
+/** Unlock the deep sleep mode
+ *
+ * Use unlocking in pair with sleep_manager_lock_deep_sleep().
+ *
+ * The lock is a counter, should be equally unlocked as locked
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_unlock_deep_sleep(void);
+
+/** Get the status of deep sleep allowance for a target
+ *
+ * @return true if a target can go to deepsleep, false otherwise
+ */
+bool sleep_manager_can_deep_sleep(void);
+
+/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based
+ * on the deepsleep locking counter
+ *
+ * This function is IRQ and thread safe
+ *
+ * @note
+ * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
+ * to be active for debug modes.
+ *
+ */
+void sleep_manager_sleep_auto(void);
+
/** Send the microcontroller to sleep
*
* @note This function can be a noop if not implemented by the platform.
@@ -46,11 +122,9 @@
__INLINE static void sleep(void)
{
#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
-#ifndef MBED_DEBUG
#if DEVICE_SLEEP
- hal_sleep();
+ sleep_manager_sleep_auto();
#endif /* DEVICE_SLEEP */
-#endif /* MBED_DEBUG */
#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
}
@@ -60,7 +134,7 @@
* @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
* @note This function will be a noop while uVisor is in use.
*
- * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * This processor is setup ready for deep sleep, and sent to sleep. This mode
* has the same sleep features as sleep plus it powers down peripherals and clocks. All state
* is still maintained.
*
@@ -71,14 +145,14 @@
* Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
* able to access the LocalFileSystem
*/
+
+MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
__INLINE static void deepsleep(void)
{
#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
-#ifndef MBED_DEBUG
#if DEVICE_SLEEP
- hal_deepsleep();
+ sleep_manager_sleep_auto();
#endif /* DEVICE_SLEEP */
-#endif /* MBED_DEBUG */
#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
}
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,43 +0,0 @@
-/*
- * PackageLicenseDeclared: Apache-2.0
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
- #include <rt_misc.h>
- #include <stdint.h>
-
-/* Get RW_IRAM1 from scatter definition */
- extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
- extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t beetle_zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t beetle_sp_limit = __current_sp();
-
- /* beetle_zi_limit has to be 8-byte aligned */
- beetle_zi_limit = (beetle_zi_limit + 7) & ~0x7;
-
- struct __initial_stackheap r;
- r.heap_base = beetle_zi_limit;
- r.heap_limit = beetle_sp_limit;
- return r;
- }
-
- #ifdef __cplusplus
- }
- #endif
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -115,27 +115,24 @@
*/
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- int32_t delta = 0;
-
/* Verify if lp_ticker has been not Initialized */
if (lp_ticker_initialized == 0)
lp_ticker_init();
/* Calculate the delta */
- delta = (int32_t)(timestamp - lp_ticker_read());
- /* Check if the event was in the past */
- if (delta <= 0) {
- /* This event was in the past */
- DualTimer_SetInterrupt_1(DUALTIMER0, 0,
- DUALTIMER_COUNT_32 | DUALTIMER_ONESHOT);
- return;
- }
+ uint32_t delta = timestamp - lp_ticker_read();
/* Enable interrupt on SingleTimer1 */
DualTimer_SetInterrupt_1(DUALTIMER0, delta,
DUALTIMER_COUNT_32 | DUALTIMER_ONESHOT);
}
+void lp_ticker_fire_interrupt(void)
+{
+ uint32_t lp_ticker_irqn = DualTimer_GetIRQn(DUALTIMER0);
+ NVIC_SetPendingIRQ((IRQn_Type)lp_ticker_irqn);
+}
+
/**
* Disable low power ticker interrupt
*/
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -91,20 +91,17 @@
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
- int32_t delta = 0;
-
if (!us_ticker_inited)
us_ticker_init();
- delta = (int32_t)(timestamp - us_ticker_read());
- /* Check if the event was in the past */
- if (delta <= 0) {
- /* This event was in the past */
- Timer_SetInterrupt(TIMER0, 0);
- return;
- }
+
+ uint32_t delta = timestamp - us_ticker_read();
+ Timer_SetInterrupt(TIMER0, delta);
+}
- /* If the event was not in the past enable interrupt */
- Timer_SetInterrupt(TIMER0, delta);
+void us_ticker_fire_interrupt(void)
+{
+ uint32_t us_ticker_irqn1 = Timer_GetIRQn(TIMER1);
+ NVIC_SetPendingIRQ((IRQn_Type)us_ticker_irqn1);
}
void us_ticker_disable_interrupt(void) {
--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,43 +0,0 @@
-/*
- * PackageLicenseDeclared: Apache-2.0
- * Copyright (c) 2009-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
- #include <rt_misc.h>
- #include <stdint.h>
-
-/* Get RW_IRAM1 from scatter definition */
- extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
- extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- /* beetle_zi_limit has to be 8-byte aligned */
- zi_limit = (zi_limit + 7) & ~0x7;
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
- }
-
- #ifdef __cplusplus
- }
- #endif
--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -108,22 +108,23 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int32_t delta = 0;
+ uint32_t delta = 0;
if (!us_ticker_drv_data.inited) {
us_ticker_init();
}
- delta = (int32_t)(timestamp - us_ticker_read());
+ delta = timestamp - us_ticker_read();
+
+ /* If the event was not in the past enable interrupt */
+ Timer_SetInterrupt(TIMER0, delta);
- /* Check if the event was in the past */
- if (delta <= 0) {
- /* This event was in the past */
- Timer_SetInterrupt(TIMER0, 0);
- } else {
- /* If the event was not in the past enable interrupt */
- Timer_SetInterrupt(TIMER0, delta);
- }
+}
+
+void us_ticker_fire_interrupt(void)
+{
+ uint32_t us_ticker_irqn1 = Timer_GetIRQn(TIMER1);
+ NVIC_SetPendingIRQ((IRQn_Type)us_ticker_irqn1);
}
void us_ticker_disable_interrupt(void)
--- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -69,6 +69,11 @@
US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER1->TimerControl &= 0xDF;
--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -51,15 +51,10 @@
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
-int delta = 0;
if (!us_ticker_inited)
us_ticker_init();
- delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past:
- us_ticker_irq_handler();
- return;
- }
+
+ uint32_t delta = timestamp - us_ticker_read();
// enable interrupt
US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
@@ -67,6 +62,12 @@
US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER1->TimerControl &= 0xDF;
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -86,15 +86,10 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t cur_time;
- int32_t delta;
+ uint32_t delta;
cur_time = lp_ticker_read();
- delta = (int32_t)((uint32_t)timestamp - cur_time);
- if (delta < 0) {
- /* Event already occurred in past */
- lp_ticker_irq_handler();
- return;
- }
+ delta = timestamp - cur_time;
uint16_t interruptat=0;
@@ -120,6 +115,11 @@
tc_start(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(TICKER_COUNTER_IRQn2);
+}
+
void lp_ticker_disable_interrupt(void)
{
tc_stop(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -170,6 +170,11 @@
tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(TICKER_COUNTER_IRQn1);
+}
+
void us_ticker_disable_interrupt(void)
{
tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -138,13 +138,7 @@
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
- int delta = (int)((uint32_t)timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past:
- us_ticker_irq_handler();
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
//Calculate how much falls outside the 32-bit after multiplying with clk_mhz
//We shift twice 16-bit to keep everything within the 32-bit variable
us_ticker_int_counter = (uint32_t)(delta >> 16);
@@ -159,3 +153,8 @@
ticker_set(us_ticker_int_remainder);
}
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT_TICKER_IRQ);
+}
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -70,15 +70,14 @@
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
- int delta = (int)((uint32_t)timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past:
- us_ticker_irq_handler();
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT->CHANNEL[3].TCTRL = 0;
PIT->CHANNEL[3].LDVAL = delta;
PIT->CHANNEL[3].TCTRL = PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK | PIT_TCTRL_CHN_MASK;
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT3_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -185,13 +185,7 @@
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
- int delta = (int)((uint32_t)timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past. Force it into the very near
- // future instead.
- delta = 1;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
us_ticker_int_counter = (uint32_t)(delta >> 16);
us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
if (us_ticker_int_counter > 0) {
@@ -202,3 +196,13 @@
us_ticker_int_remainder = 0;
}
}
+
+void us_ticker_fire_interrupt(void)
+{
+#if defined(TARGET_KL43Z)
+ NVIC_SetPendingIRQ(LPTMR0_IRQn);
+#else
+ NVIC_SetPendingIRQ(LPTimer_IRQn);
+
+#endif
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -73,16 +73,7 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(PIT3_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
@@ -90,3 +81,8 @@
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT3_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -32,7 +32,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,161 +0,0 @@
-/*
-* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
-#ifndef CPU_QN908X
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- SYSCON->STARTERSET[index] = 1u << intNumber;
- EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- DisableIRQ(interrupt); /* also disable interrupt at NVIC */
- SYSCON->STARTERCLR[index] = 1u << intNumber;
-}
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-#else
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- /* SYSCON->STARTERSET[index] = 1u << intNumber; */
- EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- DisableIRQ(interrupt); /* also disable interrupt at NVIC */
- /* SYSCON->STARTERCLR[index] = 1u << intNumber; */
-}
-#endif /*CPU_QN908X */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -73,16 +73,7 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(PIT3_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
@@ -90,3 +81,8 @@
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT3_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -82,18 +82,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(LPTMR0_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
LPTMR_StopTimer(LPTMR0);
LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta);
LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
LPTMR_StartTimer(LPTMR0);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(LPTMR0_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -82,18 +82,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(LPTMR0_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
LPTMR_StopTimer(LPTMR0);
LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta);
LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
LPTMR_StartTimer(LPTMR0);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(LPTMR0_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -73,16 +73,7 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(PIT0_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
@@ -90,3 +81,9 @@
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT0_IRQn);
+}
+
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct Mon Oct 02 15:33:19 2017 +0100 @@ -51,14 +51,22 @@ #define __ram_vector_table_size__ 0x00000000 #endif -#define m_interrupts_start 0x00000000 +#if !defined(MBED_APP_START) + #define MBED_APP_START 0 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x80000 +#endif + +#define m_interrupts_start MBED_APP_START #define m_interrupts_size 0x00000400 -#define m_flash_config_start 0x00000400 +#define m_flash_config_start MBED_APP_START + 0x400 #define m_flash_config_size 0x00000010 -#define m_text_start 0x00000410 -#define m_text_size 0x0007FBF0 +#define m_text_start MBED_APP_START + 0x410 +#define m_text_size MBED_APP_SIZE - 0x410 #define m_interrupts_ram_start 0x1FFF8000 #define m_interrupts_ram_size __ram_vector_table_size__
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld Mon Oct 02 15:33:19 2017 +0100
@@ -58,6 +58,14 @@
* heap and the page heap in uVisor applications. */
__heap_size__ = 0x4000;
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x80000
+#endif
+
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
@@ -65,9 +73,9 @@
/* Specify the memory areas */
MEMORY
{
- m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
- m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
- m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0
+ m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x400
+ m_flash_config (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10
+ m_text (RX) : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410
m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000
m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf Mon Oct 02 15:33:19 2017 +0100
@@ -48,17 +48,25 @@
define symbol __stack_size__=0x2000;
define symbol __heap_size__=0x4000;
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = 0;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = 0x80000;
+}
+
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
-define symbol m_interrupts_start = 0x00000000;
-define symbol m_interrupts_end = 0x000003FF;
+define symbol m_interrupts_start = MBED_APP_START;
+define symbol m_interrupts_end = MBED_APP_START + 0x3FF;
-define symbol m_flash_config_start = 0x00000400;
-define symbol m_flash_config_end = 0x0000040F;
+define symbol m_flash_config_start = MBED_APP_START + 0x400;
+define symbol m_flash_config_end = MBED_APP_START + 0x40F;
-define symbol m_text_start = 0x00000410;
-define symbol m_text_end = 0x0007FFFF;
+define symbol m_text_start = MBED_APP_START + 0x410;
+define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol m_interrupts_ram_start = 0x1FFF8000;
define symbol m_interrupts_ram_end = 0x1FFF8000 + __ram_vector_table_offset__;
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -73,16 +73,7 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(PIT3_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
@@ -90,3 +81,8 @@
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT3_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -32,7 +32,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -77,18 +77,14 @@
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(LPTMR0_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
LPTMR_StopTimer(LPTMR0);
LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta);
LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
LPTMR_StartTimer(LPTMR0);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(LPTMR0_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -73,16 +73,7 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(PIT3_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
@@ -90,3 +81,8 @@
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT3_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2017 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -32,7 +32,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,179 +0,0 @@
-/*
- * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __BKPT(0);
- }
-}
-#elif(defined(__REDLIB__))
-
-#if SDK_DEBUGCONSOLE
-void __assertion_failed(char *_Expr)
-{
- PRINTF("%s\n", _Expr);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif
-
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __BKPT(0);
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif /* This was not needed for mbed */
-
-#ifndef __GIC_PRIO_BITS
-uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t ret;
- uint32_t irqMaskValue;
-
- irqMaskValue = DisableGlobalIRQ();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- ret = __VECTOR_RAM[irq + 16];
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- EnableGlobalIRQ(irqMaskValue);
-
- return ret;
-}
-#endif
-
-#ifndef CPU_QN908X
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- SYSCON->STARTERSET[index] = 1u << intNumber;
- EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- DisableIRQ(interrupt); /* also disable interrupt at NVIC */
- SYSCON->STARTERCLR[index] = 1u << intNumber;
-}
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-#else
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- /* SYSCON->STARTERSET[index] = 1u << intNumber; */
- EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- DisableIRQ(interrupt); /* also disable interrupt at NVIC */
- /* SYSCON->STARTERCLR[index] = 1u << intNumber; */
-}
-#endif /*CPU_QN908X */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.h Mon Oct 02 15:33:19 2017 +0100 @@ -305,7 +305,7 @@ * @param irqHandler IRQ handler address * @return The old IRQ handler address */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) /*!
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -73,16 +73,7 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(PIT3_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
@@ -90,3 +81,8 @@
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT3_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -31,7 +31,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$VECTOR_RAM$$Base[]; #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,161 +0,0 @@
-/*
-* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
- extern uint32_t Image$$VECTOR_ROM$$Base[];
- extern uint32_t Image$$VECTOR_RAM$$Base[];
- extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
- extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
- extern uint32_t __VECTOR_TABLE[];
- extern uint32_t __VECTOR_RAM[];
- extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
- uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
- uint32_t n;
- uint32_t interrupts_disabled;
-
- interrupts_disabled = __get_PRIMASK();
- __disable_irq();
- if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
- {
- /* Copy the vector table from ROM to RAM */
- for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
- {
- __VECTOR_RAM[n] = __VECTOR_TABLE[n];
- }
- /* Point the VTOR to the position of vector table */
- SCB->VTOR = (uint32_t)__VECTOR_RAM;
- }
-
- /* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[irq + 16] = irqHandler;
-
- if (!interrupts_disabled) {
- __enable_irq();
- }
-}
-#ifndef CPU_QN908X
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- SYSCON->STARTERSET[index] = 1u << intNumber;
- EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- DisableIRQ(interrupt); /* also disable interrupt at NVIC */
- SYSCON->STARTERCLR[index] = 1u << intNumber;
-}
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-#else
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- /* SYSCON->STARTERSET[index] = 1u << intNumber; */
- EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- DisableIRQ(interrupt); /* also disable interrupt at NVIC */
- /* SYSCON->STARTERCLR[index] = 1u << intNumber; */
-}
-#endif /*CPU_QN908X */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -73,16 +73,7 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- int delta = (int)(timestamp - us_ticker_read());
- if (delta <= 0) {
- // This event was in the past.
- // Set the interrupt as pending, but don't process it here.
- // This prevents a recurive loop under heavy load
- // which can lead to a stack overflow.
- NVIC_SetPendingIRQ(PIT3_IRQn);
- return;
- }
-
+ uint32_t delta = timestamp - us_ticker_read();
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
@@ -90,3 +81,8 @@
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(PIT3_IRQn);
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -163,6 +163,11 @@
}
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(LPTMR0_IRQn);
+}
+
/** Disable low power ticker interrupt
*
*/
@@ -180,4 +185,5 @@
RTC->TAR = 0; /* Write clears the IRQ flag */
LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
}
+
#endif /* DEVICE_LOWPOWERTIMER */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/fsl_common.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,135 @@
+/*
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_common.h"
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ extern uint32_t Image$$VECTOR_ROM$$Base[];
+ extern uint32_t Image$$VECTOR_RAM$$Base[];
+ extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+ uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+ uint32_t n;
+ uint32_t interrupts_disabled;
+
+ interrupts_disabled = __get_PRIMASK();
+ __disable_irq();
+ if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+ {
+ /* Copy the vector table from ROM to RAM */
+ for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+ {
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+ }
+ /* Point the VTOR to the position of vector table */
+ SCB->VTOR = (uint32_t)__VECTOR_RAM;
+ }
+
+ /* make sure the __VECTOR_RAM is noncachable */
+ __VECTOR_RAM[irq + 16] = irqHandler;
+
+ if (!interrupts_disabled) {
+ __enable_irq();
+ }
+}
+#ifndef CPU_QN908X
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t index = 0;
+ uint32_t intNumber = (uint32_t)interrupt;
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ SYSCON->STARTERSET[index] = 1u << intNumber;
+ EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t index = 0;
+ uint32_t intNumber = (uint32_t)interrupt;
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+ SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+#else
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t index = 0;
+ uint32_t intNumber = (uint32_t)interrupt;
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ /* SYSCON->STARTERSET[index] = 1u << intNumber; */
+ EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t index = 0;
+ uint32_t intNumber = (uint32_t)interrupt;
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+ /* SYSCON->STARTERCLR[index] = 1u << intNumber; */
+}
+#endif /*CPU_QN908X */
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32600/rtc_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/rtc_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -229,6 +229,11 @@
MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(RTC0_IRQn);
+}
+
//******************************************************************************
inline void lp_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32600/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -234,6 +234,11 @@
US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TIMER_IRQn);
+}
+
//******************************************************************************
void us_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32610/rtc_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/rtc_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -229,6 +229,11 @@
MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(RTC0_IRQn);
+}
+
//******************************************************************************
inline void lp_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32610/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -234,6 +234,11 @@
US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TIMER_IRQn);
+}
+
//******************************************************************************
void us_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,58 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
-{
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -281,6 +281,11 @@
while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(RTC0_IRQn);
+}
+
//******************************************************************************
inline void lp_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -265,6 +265,11 @@
US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TIMER_IRQn);
+}
+
//******************************************************************************
void us_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32625/rtc_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/rtc_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -234,6 +234,11 @@
while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(RTC0_IRQn);
+}
+
//******************************************************************************
inline void lp_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -228,6 +228,11 @@
TMR32_Start(US_TIMER);
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TIMER_IRQn);
+}
+
//******************************************************************************
void us_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -234,6 +234,11 @@
while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(RTC0_IRQn);
+}
+
//******************************************************************************
inline void lp_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -228,6 +228,11 @@
TMR32_Start(US_TIMER);
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TIMER_IRQn);
+}
+
//******************************************************************************
void us_ticker_disable_interrupt(void)
{
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -285,6 +285,11 @@
}
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(RTC1_IRQn);
+}
+
void us_ticker_disable_interrupt(void)
{
if (us_ticker_callbackPending) {
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct Mon Oct 02 15:33:19 2017 +0100
@@ -19,7 +19,7 @@
.ANY (+RO)
}
RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section
- *(noinit)
+ *(*noinit)
}
RW_IRAM1 0x20002FB8 0x00005048 {
.ANY (+RW +ZI)
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct Mon Oct 02 15:33:19 2017 +0100
@@ -19,7 +19,7 @@
.ANY (+RO)
}
RW_IRAM0 0x20002000 UNINIT 0x000000c0 { ;no init section
- *(noinit)
+ *(*noinit)
}
RW_IRAM1 0x200020C0 0x00001F40 {
.ANY (+RW +ZI)
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct Mon Oct 02 15:33:19 2017 +0100
@@ -19,7 +19,7 @@
.ANY (+RO)
}
RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section
- *(noinit)
+ *(*noinit)
}
RW_IRAM1 0x20002FB8 0x00001048 {
.ANY (+RW +ZI)
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct Mon Oct 02 15:33:19 2017 +0100
@@ -19,7 +19,7 @@
.ANY (+RO)
}
RW_IRAM0 0x20002EF8 UNINIT 0x000000D8 { ;no init section
- *(noinit)
+ *(*noinit)
}
RW_IRAM1 0x20002FD0 0x0000D030 {
.ANY (+RW +ZI)
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct Mon Oct 02 15:33:19 2017 +0100
@@ -5,7 +5,7 @@
.ANY (+RO)
}
RW_IRAM0 0x20003288 UNINIT 0x000000F8 { ;no init section
- *(noinit)
+ *(*noinit)
}
RW_IRAM1 0x20003380 0x0003cc80 {
.ANY (+RW +ZI)
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/delay/nrf_delay.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/delay/nrf_delay.h Mon Oct 02 15:33:19 2017 +0100
@@ -164,7 +164,7 @@
{
register uint32_t delay __ASM ("r0") = number_of_us;
__ASM volatile (
-#ifdef NRF51
+#if defined(NRF51) && !defined(__ARMCC_VERSION)
".syntax unified\n"
#endif
"1:\n"
@@ -230,7 +230,7 @@
" NOP\n"
#endif
" BNE 1b\n"
-#ifdef NRF51
+#if defined(NRF51) && !defined(__ARMCC_VERSION)
".syntax divided\n"
#endif
: "+r" (delay));
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/experimental_section_vars/section_vars.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/experimental_section_vars/section_vars.h Mon Oct 02 15:33:19 2017 +0100
@@ -63,7 +63,7 @@
*
* @param[in] section_name Name of the section to register.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
// Not required by this compiler.
#define NRF_SECTION_VARS_REGISTER_SECTION(section_name)
@@ -88,7 +88,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_START_SYMBOL(section_name) section_name ## $$Base
@@ -109,7 +109,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_END_SYMBOL(section_name) section_name ## $$Limit
@@ -130,7 +130,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_LENGTH(section_name) \
((uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name))
@@ -152,7 +152,7 @@
*
* param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_START_ADDR(section_name) (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name)
@@ -171,7 +171,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_END_ADDR(section_name) (uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name)
@@ -193,7 +193,7 @@
* @param[in] type_name Name of the type stored in the section.
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_REGISTER_SYMBOLS(type_name, section_name) \
extern type_name * NRF_SECTION_VARS_START_SYMBOL(section_name); \
@@ -229,7 +229,7 @@
* @param[in] section_name Name of the section.
* @param[in] type_def Datatype of the variable to place in the given section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_ADD(section_name, type_def) \
static type_def __attribute__ ((section(#section_name))) __attribute__((used))
@@ -259,7 +259,7 @@
* @param[in] type_name Type name of item in section.
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_GET(i, type_name, section_name) \
(type_name*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(type_name))
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler.c Mon Oct 02 15:33:19 2017 +0100
@@ -441,7 +441,7 @@
uint32_t sd_check_ram_start(uint32_t sd_req_ram_start)
{
#if (defined(S130) || defined(S132) || defined(S332))
-#if defined ( __CC_ARM )
+#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$RW_IRAM1$$Base;
const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base;
#elif defined ( __ICCARM__ )
@@ -474,7 +474,7 @@
uint32_t err_code;
uint32_t app_ram_base;
-#if defined ( __CC_ARM )
+#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$RW_IRAM1$$Base;
const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base;
#elif defined ( __ICCARM__ )
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/experimental_section_vars/section_vars.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/experimental_section_vars/section_vars.h Mon Oct 02 15:33:19 2017 +0100
@@ -72,7 +72,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_START_SYMBOL(section_name) section_name ## $$Base
@@ -93,7 +93,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_END_SYMBOL(section_name) section_name ## $$Limit
@@ -115,7 +115,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_LENGTH(section_name) \
((uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name))
@@ -137,7 +137,7 @@
*
* param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_START_ADDR(section_name) (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name)
@@ -156,7 +156,7 @@
*
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_END_ADDR(section_name) (uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name)
@@ -180,7 +180,7 @@
*
* @warning The data type must be word aligned to prevent padding.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_CREATE_SECTION(section_name, data_type) \
extern data_type * NRF_SECTION_VARS_START_SYMBOL(section_name); \
@@ -216,7 +216,7 @@
* @param[in] section_name Name of the section.
* @param[in] section_var The variable to register in the given section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_REGISTER_VAR(section_name, section_var) \
static section_var __attribute__ ((section(#section_name))) __attribute__((used))
@@ -246,7 +246,7 @@
* @param[in] data_type Data type of the variable.
* @param[in] section_name Name of the section.
*/
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define NRF_SECTION_VARS_GET(i, data_type, section_name) \
(data_type*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(data_type))
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.c Mon Oct 02 15:33:19 2017 +0100
@@ -522,7 +522,7 @@
uint32_t err_code;
uint32_t app_ram_base;
-#if defined ( __CC_ARM )
+#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$RW_IRAM1$$Base;
const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base;
#elif defined ( __ICCARM__ )
--- a/targets/TARGET_NORDIC/TARGET_NRF5/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -35,6 +35,14 @@
LP_TICKER_CC_CHANNEL, LP_TICKER_INT_MASK);
}
+void lp_ticker_fire_interrupt(void)
+{
+ uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
+
+ nrf_rtc_cc_set(COMMON_RTC_INSTANCE, LP_TICKER_CC_CHANNEL, RTC_WRAP(closest_safe_compare));
+ nrf_rtc_event_enable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK);
+}
+
void lp_ticker_disable_interrupt(void)
{
nrf_rtc_event_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK);
--- a/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c Mon Oct 02 15:33:19 2017 +0100
@@ -42,8 +42,8 @@
#include "nrf_sdm.h"
#include "section_vars.h"
-#if defined(__CC_ARM)
- __attribute__ ((section("noinit"),zero_init))
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ __attribute__ ((section(".bss.noinit"),zero_init))
uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
#elif defined(__GNUC__)
__attribute__ ((section(".noinit")))
--- a/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -271,6 +271,14 @@
US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK);
}
+void us_ticker_fire_interrupt(void)
+{
+ uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
+
+ nrf_rtc_cc_set(COMMON_RTC_INSTANCE, US_TICKER_CC_CHANNEL, RTC_WRAP(closest_safe_compare));
+ nrf_rtc_event_enable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
+}
+
void us_ticker_disable_interrupt(void)
{
nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
@@ -291,24 +299,6 @@
#define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1)
-/**
- * The value previously set in the capture compare register of channel 1
- */
-static uint32_t previous_tick_cc_value = 0;
-
-/* The Period of RTC oscillator, unit [1/RTC1_CONFIG_FREQUENCY] */
-static uint32_t os_rtc_period;
-
-/* Variable for frozen RTC1 counter value. It is used when system timer is disabled. */
-static uint32_t frozen_sub_tick = 0;
-
-
-#ifdef MBED_CONF_RTOS_PRESENT
- #include "rtx_os.h" //import osRtxInfo, SysTick_Handler()
-
- static inline void clear_tick_interrupt();
-#endif
-
#ifndef RTC1_CONFIG_FREQUENCY
#define RTC1_CONFIG_FREQUENCY 32678 // [Hz]
#endif
@@ -317,210 +307,15 @@
void COMMON_RTC_IRQ_HANDLER(void)
{
- if(nrf_rtc_event_pending(COMMON_RTC_INSTANCE, OS_TICK_EVENT)) {
-#ifdef MBED_CONF_RTOS_PRESENT
- clear_tick_interrupt();
- // Trigger the SysTick_Handler just after exit form RTC Handler.
- NVIC_SetPendingIRQ(SWI3_IRQn);
-
- nrf_gpio_pin_set(11);
-#endif
- } else {
+ if(!nrf_rtc_event_pending(COMMON_RTC_INSTANCE, OS_TICK_EVENT)) {
common_rtc_irq_handler();
}
}
-
-#ifdef MBED_CONF_RTOS_PRESENT
-/**
- * Return the next number of clock cycle needed for the next tick.
- * @note This function has been carefully optimized for a systick occurring every 1000us.
- */
-static uint32_t get_next_tick_cc_delta()
-{
- uint32_t delta = 0;
-
- if (osRtxConfig.tick_freq != 1000) {
- // In RTX, by default SYSTICK is is used.
- // A tick event is generated every os_trv + 1 clock cycles of the system timer.
- delta = os_rtc_period;
- } else {
- // If the clockrate is set to 1000us then 1000 tick should happen every second.
- // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
- // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
- // generated in 32000 clock cycle instead of 32768 clock cycles.
- // As a result, if a user schedule an OS timer to start in 100s, the timer will start
- // instead after 97.656s
- // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
- // clock cycles.
- // The strategy is simple, for 1000 ticks:
- // * 768 ticks will occur 33 clock cycles after the previous tick
- // * 232 ticks will occur 32 clock cycles after the previous tick
- // By default every delta is equal to 33.
- // Every five ticks (20%, 200 delta in one second), the delta is equal to 32
- // The remaining (32) deltas equal to 32 are distributed using primes numbers.
- static uint32_t counter = 0;
- if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
- delta = 32;
- } else {
- delta = 33;
- }
- ++counter;
- if (counter == 1000) {
- counter = 0;
- }
- }
- return delta;
-}
-
-static inline void clear_tick_interrupt()
+IRQn_Type mbed_get_m0_tick_irqn()
{
- nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
- nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
-}
-
-/**
- * Indicate if a value is included in a range which can be wrapped.
- * @param begin start of the range
- * @param end end of the range
- * @param val value to check
- * @return true if the value is included in the range and false otherwise.
- */
-static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val)
-{
- // regular case, begin < end
- // return true if begin <= val < end
- if (begin < end) {
- if (begin <= val && val < end) {
- return true;
- } else {
- return false;
- }
- } else {
- // In this case end < begin because it has wrap around the limits
- // return false if end < val < begin
- if (end < val && val < begin) {
- return false;
- } else {
- return true;
- }
- }
-
-}
-
-/**
- * Register the next tick.
- */
-static void register_next_tick()
-{
- previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
- uint32_t delta = get_next_tick_cc_delta();
- uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
-
- // Disable irq directly for few cycles,
- // Validation of the new CC value against the COUNTER,
- // Setting the new CC value and enabling CC IRQ should be an atomic operation
- // Otherwise, there is a possibility to set an invalid CC value because
- // the RTC1 keeps running.
- // This code is very short 20-38 cycles in the worst case, it shouldn't
- // disturb softdevice.
- __disable_irq();
- uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
-
- // If an overflow occur, set the next tick in COUNTER + delta clock cycles
- if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) {
- new_compare_value = current_counter + delta;
- }
- nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
- // Enable generation of the compare event for the value set above (this
- // event will trigger the interrupt).
- nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
- __enable_irq();
+ return SWI3_IRQn;
}
-/**
- * Initialize alternative hardware timer as RTX kernel timer
- * This function is directly called by RTX.
- * @note this function shouldn't be called directly.
- * @return IRQ number of the alternative hardware timer
- */
-int32_t osRtxSysTimerSetup(void)
-{
- common_rtc_init();
-
- os_rtc_period = (RTC1_CONFIG_FREQUENCY) / osRtxConfig.tick_freq;
-
- return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE);
-}
-
-// Start SysTickt timer emulation
-void osRtxSysTimerEnable(void)
-{
- nrf_rtc_int_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
-
- uint32_t current_cnt = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
- nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, current_cnt);
- register_next_tick();
-
- NVIC_SetVector(SWI3_IRQn, (uint32_t)SysTick_Handler);
- NVIC_SetPriority(SWI3_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Emulated Systick Interrupt */
- NVIC_EnableIRQ(SWI3_IRQn);
-}
-
-// Stop SysTickt timer emulation
-void osRtxSysTimerDisable(void)
-{
- nrf_rtc_int_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
-
- // RTC1 is free runing. osRtxSysTimerGetCount will return proper frozen value
- // thanks to geting frozen value instead of RTC1 counter value
- frozen_sub_tick = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
-}
-
-
-
-/**
- * Acknowledge the tick interrupt.
- * This function is called by the function OS_Tick_Handler of RTX.
- * @note this function shouldn't be called directly.
- */
-void osRtxSysTimerAckIRQ(void)
-{
- register_next_tick();
-}
-
-// provide a free running incremental value over the entire 32-bit range
-uint32_t osRtxSysTimerGetCount(void)
-{
- uint32_t current_cnt;
- uint32_t sub_tick;
-
- if (nrf_rtc_int_is_enabled(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK)) {
- // system timer is enabled
- current_cnt = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
-
- if (current_cnt >= previous_tick_cc_value) {
- //0 prev current MAX
- //|------|---------|------------|---->
- sub_tick = current_cnt - previous_tick_cc_value;
- } else {
- //0 current prev MAX
- //|------|---------|------------|---->
- sub_tick = MAX_RTC_COUNTER_VAL - previous_tick_cc_value + current_cnt;
- }
- } else { // system timer is disabled
- sub_tick = frozen_sub_tick;
- }
-
- return (os_rtc_period * osRtxInfo.kernel.tick) + sub_tick;
-}
-
-// Timer Tick frequency
-uint32_t osRtxSysTimerGetFreq (void) {
- return RTC1_CONFIG_FREQUENCY;
-}
-
-#endif // #ifdef MBED_CONF_RTOS_PRESENT
-
#endif // defined(TARGET_MCU_NRF51822)
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -9,13 +9,17 @@
extern "C" {
#endif
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
struct __initial_stackheap r;
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -9,13 +9,17 @@
extern "C" {
#endif
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
struct __initial_stackheap r;
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis.h Mon Oct 02 15:33:19 2017 +0100 @@ -21,7 +21,7 @@ #include "cmsis_nvic.h" // Support linker-generated symbol as start of relocated vector table. -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; #elif defined(__ICCARM__)
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -19,7 +19,7 @@ #define NVIC_NUM_VECTORS (16 + 64) -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) #elif defined(__ICCARM__) # pragma section = "IRAMVEC"
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c Mon Oct 02 15:33:19 2017 +0100
@@ -47,7 +47,7 @@
/* Initialize segments */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern void __main(void);
#elif defined(__ICCARM__)
@@ -152,7 +152,7 @@
WEAK_ALIAS_FUNC(TK_IRQHandler, Default_Handler) // 63:
/* Vector table */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__attribute__ ((section("RESET")))
const uint32_t __vector_handlers[] = {
#elif defined(__ICCARM__)
@@ -164,7 +164,7 @@
#endif
/* Configure Initial Stack Pointer, using linker-generated symbols */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
(uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
#elif defined(__ICCARM__)
//(uint32_t) __sfe("CSTACK"),
@@ -279,7 +279,7 @@
/* Enable register write-protection function */
SYS_LockReg();
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__main();
#elif defined(__ICCARM__)
--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -145,31 +145,23 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t now = lp_ticker_read();
+ uint32_t delta = timestamp - lp_ticker_read();
wakeup_tick = timestamp;
TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+ lp_ticker_arm_cd();
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+ cd_major_minor_clks = cd_minor_clks = 0;
/**
- * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
- * Conditions in which delta is negative:
- * 1. Wrap around
- * 2. Newly scheduled alarm is behind now
- */
- //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
- int delta = (int) (timestamp - now);
- if (delta > 0) {
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
- }
- else {
- cd_major_minor_clks = cd_minor_clks = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
- }
+ * This event was in the past. Set the interrupt as pending, but don't process it here.
+ * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+ */
+ NVIC_SetPendingIRQ(timer3_modinit.irq_n);
}
void lp_ticker_disable_interrupt(void)
--- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -150,19 +150,19 @@
{
TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- int delta = (int) (timestamp - us_ticker_read());
- if (delta > 0) {
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
- }
- else {
- cd_major_minor_us = cd_minor_us = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
- }
+ uint32_t delta = timestamp - us_ticker_read();
+ cd_major_minor_us = delta * US_PER_TICK;
+ us_ticker_arm_cd();
+}
+
+void us_ticker_fire_interrupt(void)
+{
+ cd_major_minor_us = cd_minor_us = 0;
+ /**
+ * This event was in the past. Set the interrupt as pending, but don't process it here.
+ * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+ */
+ NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
}
static void tmr0_vec(void)
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -9,13 +9,17 @@
extern "C" {
#endif
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
struct __initial_stackheap r;
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -9,13 +9,17 @@
extern "C" {
#endif
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
struct __initial_stackheap r;
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/cmsis.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/cmsis.h Mon Oct 02 15:33:19 2017 +0100 @@ -21,7 +21,7 @@ #include "cmsis_nvic.h" // Support linker-generated symbol as start of relocated vector table. -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; #elif defined(__ICCARM__)
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -23,7 +23,7 @@ #define NVIC_USER_IRQ_NUMBER 96 #define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) #elif defined(__ICCARM__) # pragma section = "IRAMVEC"
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/startup_M480.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/startup_M480.c Mon Oct 02 15:33:19 2017 +0100
@@ -50,7 +50,7 @@
/* Initialize segments */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern void __main(void);
#elif defined(__ICCARM__)
@@ -190,7 +190,7 @@
WEAK_ALIAS_FUNC(ETMC_IRQHandler, Default_Handler) // 95:
/* Vector table */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__attribute__ ((section("RESET")))
const uint32_t __vector_handlers[] = {
#elif defined(__ICCARM__)
@@ -201,7 +201,7 @@
const uint32_t __vector_handlers[] = {
#endif
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
(uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
#elif defined(__ICCARM__)
(uint32_t) &CSTACK$$Limit,
@@ -339,7 +339,7 @@
* C/C++ runtime initialization
*/
-#if defined (__CC_ARM)
+#if defined(__CC_ARM)
__asm static void Reset_Handler(void)
{
@@ -406,7 +406,7 @@
/* Enable register write-protection function */
SYS_LockReg();
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
Reset_Handler_Cascade((void *) &Image$$ARM_LIB_STACK$$ZI$$Limit, (void *) Reset_Handler_2);
#elif defined(__ICCARM__)
Reset_Handler_Cascade((void *) &CSTACK$$Limit, (void *) Reset_Handler_2);
@@ -429,7 +429,7 @@
uvisor_init();
#endif
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__main();
#elif defined(__ICCARM__)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PeripheralNames.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,134 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name
+// which encodes module base address and module index/subindex.
+#define NU_MODSUBINDEX_Pos 0
+#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos)
+#define NU_MODINDEX_Pos 24
+#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos)
+
+#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos))
+#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk))
+#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos)
+#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos)
+
+#if 0
+typedef enum {
+ GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0),
+ GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0),
+ GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0),
+ GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0),
+ GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0),
+ GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0)
+} GPIOName;
+#endif
+
+typedef enum {
+ ADC_0_0 = (int) NU_MODNAME(ADC_BASE, 0, 0),
+ ADC_0_1 = (int) NU_MODNAME(ADC_BASE, 0, 1),
+ ADC_0_2 = (int) NU_MODNAME(ADC_BASE, 0, 2),
+ ADC_0_3 = (int) NU_MODNAME(ADC_BASE, 0, 3),
+ ADC_0_4 = (int) NU_MODNAME(ADC_BASE, 0, 4),
+ ADC_0_5 = (int) NU_MODNAME(ADC_BASE, 0, 5),
+ ADC_0_6 = (int) NU_MODNAME(ADC_BASE, 0, 6),
+ ADC_0_7 = (int) NU_MODNAME(ADC_BASE, 0, 7),
+ ADC_0_8 = (int) NU_MODNAME(ADC_BASE, 0, 8),
+ ADC_0_9 = (int) NU_MODNAME(ADC_BASE, 0, 9),
+ ADC_0_10 = (int) NU_MODNAME(ADC_BASE, 0, 10),
+ ADC_0_11 = (int) NU_MODNAME(ADC_BASE, 0, 11),
+} ADCName;
+
+typedef enum {
+ UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
+ UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
+ // NOTE: board-specific
+ STDIO_UART = UART_0
+} UARTName;
+
+typedef enum {
+ SPI_0_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
+ SPI_0_1 = (int) NU_MODNAME(SPI0_BASE, 0, 1),
+ SPI_1_0 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
+ SPI_1_1 = (int) NU_MODNAME(SPI1_BASE, 1, 1),
+ SPI_2_0 = (int) NU_MODNAME(SPI2_BASE, 2, 0),
+ SPI_2_1 = (int) NU_MODNAME(SPI2_BASE, 2, 1),
+
+ SPI_0 = SPI_0_0,
+ SPI_1 = SPI_1_0,
+ SPI_2 = SPI_2_0
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0),
+ I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0)
+} I2CName;
+
+typedef enum {
+ PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0, 0),
+ PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 0, 1),
+ PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 0, 2),
+ PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 0, 3),
+
+ PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 1, 0),
+ PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1, 1),
+ PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 1, 2),
+ PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 1, 3),
+} PWMName;
+
+typedef enum {
+ TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0, 0),
+ TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 0, 0),
+ TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 0, 0),
+ TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 0, 0),
+} TIMERName;
+
+typedef enum {
+ RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0)
+} RTCName;
+
+typedef enum {
+ DMAGCR_0 = (int) NU_MODNAME(PDMAGCR_BASE, 0, 0)
+} DMAGCR_Name;
+
+typedef enum {
+ DMA_0_0 = (int) NU_MODNAME(VDMA_BASE, 0, 0),
+ DMA_1_0 = (int) NU_MODNAME(PDMA1_BASE, 1, 0),
+ DMA_2_0 = (int) NU_MODNAME(PDMA2_BASE, 2, 0),
+ DMA_3_0 = (int) NU_MODNAME(PDMA3_BASE, 3, 0),
+ DMA_4_0 = (int) NU_MODNAME(PDMA4_BASE, 4, 0),
+ DMA_5_0 = (int) NU_MODNAME(PDMA5_BASE, 5, 0),
+ DMA_6_0 = (int) NU_MODNAME(PDMA6_BASE, 6, 0),
+} DMAName;
+
+typedef enum {
+ I2S_0 = (int) NU_MODNAME(I2S_BASE, 0, 0),
+} I2SName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PeripheralPins.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,190 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_0_0, SYS_PA_L_MFP_PA0_MFP_ADC_CH0},
+ {PA_1, ADC_0_1, SYS_PA_L_MFP_PA1_MFP_ADC_CH1},
+ {PA_2, ADC_0_2, SYS_PA_L_MFP_PA2_MFP_ADC_CH2},
+ {PA_3, ADC_0_3, SYS_PA_L_MFP_PA3_MFP_ADC_CH3},
+ {PA_4, ADC_0_4, SYS_PA_L_MFP_PA4_MFP_ADC_CH4},
+ {PA_5, ADC_0_5, SYS_PA_L_MFP_PA5_MFP_ADC_CH5},
+ {PA_6, ADC_0_6, SYS_PA_L_MFP_PA6_MFP_ADC_CH6},
+ {PA_7, ADC_0_7, SYS_PA_L_MFP_PA7_MFP_ADC_CH7},
+ {PD_0, ADC_0_8, SYS_PD_L_MFP_PD0_MFP_ADC_CH8},
+ {PD_1, ADC_0_9, SYS_PD_L_MFP_PD1_MFP_ADC_CH9},
+ {PD_2, ADC_0_10, SYS_PD_L_MFP_PD2_MFP_ADC_CH10},
+ {PD_3, ADC_0_11, SYS_PD_L_MFP_PD3_MFP_ADC_CH11},
+
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PA_8, I2C_0, SYS_PA_H_MFP_PA8_MFP_I2C0_SDA},
+ {PA_10, I2C_1, SYS_PA_H_MFP_PA10_MFP_I2C1_SDA},
+ {PA_12, I2C_0, SYS_PA_H_MFP_PA12_MFP_I2C0_SDA},
+ {PA_4, I2C_0, SYS_PA_L_MFP_PA4_MFP_I2C0_SDA},
+ {PC_8, I2C_1, SYS_PC_H_MFP_PC8_MFP_I2C1_SDA},
+ {PC_12, I2C_0, SYS_PC_H_MFP_PC12_MFP_I2C0_SDA},
+ {PF_4, I2C_0, SYS_PF_L_MFP_PF4_MFP_I2C0_SDA},
+
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_5, I2C_0, SYS_PA_L_MFP_PA5_MFP_I2C0_SCL},
+ {PA_9, I2C_0, SYS_PA_H_MFP_PA9_MFP_I2C0_SCL},
+ {PA_11, I2C_1, SYS_PA_H_MFP_PA11_MFP_I2C1_SCL},
+ {PA_13, I2C_0, SYS_PA_H_MFP_PA13_MFP_I2C0_SCL},
+ {PC_9, I2C_1, SYS_PC_H_MFP_PC9_MFP_I2C1_SCL},
+ {PC_13, I2C_0, SYS_PC_H_MFP_PC13_MFP_I2C0_SCL},
+ {PF_5, I2C_0, SYS_PF_L_MFP_PF5_MFP_I2C0_SCL},
+
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+ {PA_6, PWM_0_3, SYS_PA_L_MFP_PA6_MFP_PWM0_CH3},
+ {PA_7, PWM_0_2, SYS_PA_L_MFP_PA7_MFP_PWM0_CH2},
+ {PA_12, PWM_0_0, SYS_PA_H_MFP_PA12_MFP_PWM0_CH0},
+ {PA_13, PWM_0_1, SYS_PA_H_MFP_PA13_MFP_PWM0_CH1},
+ {PA_14, PWM_0_2, SYS_PA_H_MFP_PA14_MFP_PWM0_CH2},
+ {PA_15, PWM_0_3, SYS_PA_H_MFP_PA15_MFP_PWM0_CH3},
+ {PB_11, PWM_1_0, SYS_PB_H_MFP_PB11_MFP_PWM1_CH0},
+ {PC_6, PWM_0_0, SYS_PC_L_MFP_PC6_MFP_PWM0_CH0},
+ {PC_7, PWM_0_1, SYS_PC_L_MFP_PC7_MFP_PWM0_CH1},
+ {PC_12, PWM_1_0, SYS_PC_H_MFP_PC12_MFP_PWM1_CH0},
+ {PC_13, PWM_1_1, SYS_PC_H_MFP_PC13_MFP_PWM1_CH1},
+ {PC_14, PWM_1_3, SYS_PC_H_MFP_PC14_MFP_PWM1_CH3},
+ {PC_15, PWM_1_2, SYS_PC_H_MFP_PC15_MFP_PWM1_CH2},
+ {PE_0, PWM_1_2, SYS_PE_L_MFP_PE0_MFP_PWM1_CH2},
+ {PE_1, PWM_1_3, SYS_PE_L_MFP_PE1_MFP_PWM1_CH3},
+ {PE_5, PWM_1_1, SYS_PE_L_MFP_PE5_MFP_PWM1_CH1},
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_3, UART_1, SYS_PA_L_MFP_PA3_MFP_UART1_TX},
+ {PA_15, UART_0, SYS_PA_H_MFP_PA15_MFP_UART0_TX},
+ {PB_1, UART_0, SYS_PB_L_MFP_PB1_MFP_UART0_TX},
+ {PB_5, UART_1, SYS_PB_L_MFP_PB5_MFP_UART1_TX},
+ {PC_11, UART_1, SYS_PC_H_MFP_PC11_MFP_UART1_TX},
+ {PD_1, UART_1, SYS_PD_L_MFP_PD1_MFP_UART1_TX},
+ {PE_10, UART_1, SYS_PE_H_MFP_PE10_MFP_UART1_TX},
+
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_2, UART_1, SYS_PA_L_MFP_PA2_MFP_UART1_RX},
+ {PA_14, UART_0, SYS_PA_H_MFP_PA14_MFP_UART0_RX},
+ {PB_0, UART_0, SYS_PB_L_MFP_PB0_MFP_UART0_RX},
+ {PB_4, UART_1, SYS_PB_L_MFP_PB4_MFP_UART1_RX},
+ {PC_10, UART_1, SYS_PC_H_MFP_PC10_MFP_UART1_RX},
+ {PD_0, UART_1, SYS_PD_L_MFP_PD0_MFP_UART1_RX},
+ {PE_9, UART_1, SYS_PE_H_MFP_PE9_MFP_UART1_RX},
+
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ {PB_2, UART_0, SYS_PB_L_MFP_PB2_MFP_UART0_RTS},
+ {PB_6, UART_1, SYS_PB_L_MFP_PB6_MFP_UART1_RTS},
+ {PD_2, UART_1, SYS_PD_L_MFP_PD2_MFP_UART1_RTS},
+ {PE_11, UART_1, SYS_PE_H_MFP_PE11_MFP_UART1_RTS},
+
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PB_3, UART_0, SYS_PB_L_MFP_PB3_MFP_UART0_CTS},
+ {PB_7, UART_1, SYS_PB_L_MFP_PB7_MFP_UART1_CTS},
+ {PD_3, UART_1, SYS_PD_L_MFP_PD3_MFP_UART1_CTS},
+ {PE_12, UART_1, SYS_PE_H_MFP_PE12_MFP_UART1_CTS},
+
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_11, SPI_2, SYS_PA_H_MFP_PA11_MFP_SPI2_MOSI0},
+ {PB_0, SPI_1, SYS_PB_L_MFP_PB0_MFP_SPI1_MOSI0},
+ {PB_7, SPI_2, SYS_PB_L_MFP_PB7_MFP_SPI2_MOSI0},
+ {PB_10, SPI_0, SYS_PB_H_MFP_PB10_MFP_SPI0_MOSI0},
+ {PC_3, SPI_0, SYS_PC_L_MFP_PC3_MFP_SPI0_MOSI0},
+ {PC_5, SPI_0, SYS_PC_L_MFP_PC5_MFP_SPI0_MOSI1},
+ {PC_11, SPI_1, SYS_PC_H_MFP_PC11_MFP_SPI1_MOSI0},
+ {PC_13, SPI_1, SYS_PC_H_MFP_PC13_MFP_SPI1_MOSI1},
+ {PD_3, SPI_2, SYS_PD_L_MFP_PD3_MFP_SPI2_MOSI0},
+ {PD_5, SPI_2, SYS_PD_L_MFP_PD5_MFP_SPI2_MOSI1},
+ {PE_4, SPI_0, SYS_PE_L_MFP_PE4_MFP_SPI0_MOSI0},
+
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_10, SPI_2, SYS_PA_H_MFP_PA10_MFP_SPI2_MISO0},
+ {PB_1, SPI_1, SYS_PB_L_MFP_PB1_MFP_SPI1_MISO0},
+ {PB_6, SPI_2, SYS_PB_L_MFP_PB6_MFP_SPI2_MISO0},
+ {PB_11, SPI_0, SYS_PB_H_MFP_PB11_MFP_SPI0_MISO0},
+ {PC_2, SPI_0, SYS_PC_L_MFP_PC2_MFP_SPI0_MISO0},
+ {PC_4, SPI_0, SYS_PC_L_MFP_PC4_MFP_SPI0_MISO1},
+ {PC_10, SPI_1, SYS_PC_H_MFP_PC10_MFP_SPI1_MISO0},
+ {PC_12, SPI_1, SYS_PC_H_MFP_PC12_MFP_SPI1_MISO1},
+ {PD_2, SPI_2, SYS_PD_L_MFP_PD2_MFP_SPI2_MISO0},
+ {PD_4, SPI_2, SYS_PD_L_MFP_PD4_MFP_SPI2_MISO1},
+ {PE_3, SPI_0, SYS_PE_L_MFP_PE3_MFP_SPI0_MISO0},
+
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_9, SPI_2, SYS_PA_H_MFP_PA9_MFP_SPI2_SCLK},
+ {PB_2, SPI_1, SYS_PB_L_MFP_PB2_MFP_SPI1_SCLK},
+ {PB_5, SPI_2, SYS_PB_L_MFP_PB5_MFP_SPI2_SCLK},
+ {PC_1, SPI_0, SYS_PC_L_MFP_PC1_MFP_SPI0_SCLK},
+ {PC_9, SPI_1, SYS_PC_H_MFP_PC9_MFP_SPI1_SCLK},
+ {PD_1, SPI_2, SYS_PD_L_MFP_PD1_MFP_SPI2_SCLK},
+ {PE_2, SPI_0, SYS_PE_L_MFP_PE2_MFP_SPI0_SCLK},
+
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_8, SPI_2, SYS_PA_H_MFP_PA8_MFP_SPI2_SS0},
+ {PB_3, SPI_1, SYS_PB_L_MFP_PB3_MFP_SPI1_SS0},
+ {PB_4, SPI_2, SYS_PB_L_MFP_PB4_MFP_SPI2_SS0},
+ {PB_9, SPI_1, SYS_PB_H_MFP_PB9_MFP_SPI1_SS1},
+ {PB_10, SPI_0, SYS_PB_H_MFP_PB10_MFP_SPI0_SS1},
+ {PB_14, SPI_2, SYS_PB_H_MFP_PB14_MFP_SPI2_SS1},
+ {PC_0, SPI_0, SYS_PC_L_MFP_PC0_MFP_SPI0_SS0},
+ {PC_8, SPI_1, SYS_PC_H_MFP_PC8_MFP_SPI1_SS0},
+ {PD_0, SPI_2, SYS_PD_L_MFP_PD0_MFP_SPI2_SS0},
+ {PE_1, SPI_0, SYS_PE_L_MFP_PE1_MFP_SPI0_SS0},
+
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PeripheralPins.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if 0
+//*** GPIO ***
+
+extern const PinMap PinMap_GPIO[];
+#endif
+
+//*** ADC ***
+
+extern const PinMap PinMap_ADC[];
+
+//*** I2C ***
+
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+//*** PWM ***
+
+extern const PinMap PinMap_PWM[];
+
+//*** SERIAL ***
+
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_RTS[];
+extern const PinMap PinMap_UART_CTS[];
+
+//*** SPI ***
+
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,130 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NU_PININDEX_Pos 0
+#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos)
+#define NU_PINPORT_Pos 8
+#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos)
+#define NU_PIN_MODINDEX_Pos 12
+#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos)
+#define NU_PIN_BIND_Pos 16
+#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos)
+
+#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos)
+#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos)
+#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos)
+#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos)
+#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos))
+#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)
+#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
+
+#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
+#define NU_MFP_POS(pin) ((pin % 8) * 4)
+#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
+
+// LEGACY
+#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME)
+#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME)
+#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME)
+#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN))
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PullNone = 0,
+ PullDown,
+ PullUp,
+
+ PushPull,
+ OpenDrain,
+ Quasi,
+
+ PullDefault = PullUp,
+} PinMode;
+
+typedef enum {
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ // Generic naming
+ PA_0 = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
+ PB_0 = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
+ PC_0 = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14, PC_15,
+ PD_0 = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14, PD_15,
+ PE_0 = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15,
+ PF_0 = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5,
+
+ // Arduino UNO naming
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_2,
+ A3 = PA_3,
+ A4 = PA_4,
+ A5 = PA_5,
+
+ D0 = PB_4,
+ D1 = PB_5,
+ D2 = PA_12,
+ D3 = PA_13,
+ D4 = PA_14,
+ D5 = PA_15,
+ D6 = PC_12,
+ D7 = PC_13,
+ D8 = PE_0,
+ D9 = PE_1,
+ D10 = PC_0,
+ D11 = PC_3,
+ D12 = PC_2,
+ D13 = PC_1,
+ D14 = PC_8,
+ D15 = PC_9,
+
+ // NOTE: other board-specific naming
+ // UART naming
+ USBTX = PB_1,
+ USBRX = PB_0,
+ STDIO_UART_TX = USBTX,
+ STDIO_UART_RX = USBRX,
+ // LED naming
+ LED1 = PE_11,
+ LED2 = PE_10,
+ LED3 = PE_9,
+ LED4 = LED1,
+ LED_RED = LED3,
+ LED_GREEN = LED1,
+ LED_YELLOW = LED2,
+ // Button naming
+ SW2 = PE_5,
+ SW3 = PE_6,
+
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MBED_PINNAMES_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PortNames.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4,
+ PortF = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/device.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/mbed_overrides.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+
+void mbed_sdk_init(void)
+{
+ // NOTE: Support singleton semantics to be called from other init functions
+ static int inited = 0;
+ if (inited) {
+ return;
+ }
+ inited = 1;
+
+ /*---------------------------------------------------------------------------------------------------------*/
+ /* Init System Clock */
+ /*---------------------------------------------------------------------------------------------------------*/
+ /* Unlock protected registers */
+ SYS_UnlockReg();
+
+ /* Enable HIRC clock (internal OSC 12MHz) */
+ CLK_EnableXtalRC(CLK_PWRCTL_HIRC_EN_Msk);
+ /* Enable HXT clock (external XTAL 12MHz) */
+ CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);
+ /* Enable LIRC clock (OSC 10KHz) for lp_ticker */
+ CLK_EnableXtalRC(CLK_PWRCTL_LIRC_EN_Msk);
+ /* Enable LXT clock (XTAL 32KHz) for RTC */
+ CLK_EnableXtalRC(CLK_PWRCTL_LXT_EN_Msk);
+
+ /* Wait for HIRC clock ready */
+ CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk);
+ /* Wait for HXT clock ready */
+ CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk);
+ /* Wait for LIRC clock ready */
+ CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk);
+ /* Wait for LXT clock ready */
+ CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk);
+
+ /* Set HCLK source form HXT and HCLK source divide 1 */
+ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_HCLK_CLK_DIVIDER(1));
+
+ /* Set HCLK frequency 42MHz */
+ CLK_SetCoreClock(42000000);
+
+ /* Update System Core Clock */
+ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
+ SystemCoreClockUpdate();
+
+ /* Lock protected registers */
+ SYS_LockReg();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "dma_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ PinName pin;
+ uint32_t irq_handler;
+ uint32_t irq_id;
+ struct gpio_irq_s *next;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct serial_s {
+ UARTName uart;
+ PinName pin_tx;
+ PinName pin_rx;
+
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t parity;
+ uint32_t stopbits;
+
+ void (*vec)(void);
+ uint32_t irq_handler;
+ uint32_t irq_id;
+ uint32_t irq_en;
+ uint32_t ier_msk;
+ uint32_t async_en;
+
+ // Async transfer related fields
+ DMAUsage dma_usage_tx;
+ DMAUsage dma_usage_rx;
+ int dma_chn_id_tx;
+ int dma_chn_id_rx;
+ uint32_t event;
+ void (*irq_handler_tx_async)(void);
+ void (*irq_handler_rx_async)(void);
+};
+
+struct spi_s {
+ SPIName spi;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+
+ // Async transfer related fields
+ DMAUsage dma_usage;
+ int dma_chn_id_tx;
+ int dma_chn_id_rx;
+ uint32_t event;
+ uint32_t hdlr_async;
+};
+
+struct i2c_s {
+ I2CName i2c;
+ int slaveaddr_state;
+
+ uint32_t tran_ctrl;
+ char * tran_beg;
+ char * tran_pos;
+ char * tran_end;
+ int inten;
+
+ // Async transfer related fields
+ DMAUsage dma_usage;
+ uint32_t event;
+ int stop;
+ uint32_t address;
+ uint32_t hdlr_async;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ uint32_t period_us;
+ uint32_t pulsewidth_us;
+};
+
+struct sleep_s {
+ int powerdown;
+};
+#ifdef __cplusplus
+}
+#endif
+
+#include "gpio_object.h"
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/analogin_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "mbed_wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+
+static uint32_t adc_modinit_mask = 0;
+volatile int adc_busy_flag = 0;
+
+static const struct nu_modinit_s adc_modinit_tab[] = {
+ {ADC_0_0, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_1, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_2, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_3, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_4, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_5, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_6, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_7, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_8, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_9, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_10, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+ {ADC_0_11, ADC_MODULE, CLK_CLKSEL1_ADC_S_HIRC, CLK_ADC_CLK_DIVIDER(1), ADC_RST, ADC_IRQn, NULL},
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName) NC);
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((ADCName) modinit->modname == obj->adc);
+
+ ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
+ uint32_t chn = NU_MODSUBINDEX(obj->adc);
+
+ // Wait for ADC is not busy, due to all ADC channels share the same module
+ while (adc_busy_flag != 0) {
+ wait_us(100);
+ }
+ adc_busy_flag = 1;
+
+ // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
+ if (! adc_modinit_mask) {
+ // Reset this module if no channel enabled
+ SYS_ResetModule(modinit->rsetidx);
+
+ // Select clock source of paired channels
+ CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+ // Enable clock of paired channels
+ CLK_EnableModuleClock(modinit->clkidx);
+
+ // Set operation mode and enable channel N
+ ADC_Open(ADC, ADC_INPUT_MODE_SINGLE_END, ADC_OPERATION_MODE_SINGLE_CYCLE, 1 << chn);
+
+ // Set reference voltage to AVDD
+ ADC_SET_REF_VOLTAGE(ADC, ADC_REFSEL_POWER);
+
+ // Power on ADC
+ ADC_POWER_ON(ADC);
+ } else {
+ // Just enable channel N
+ adc_base->CHEN |= 1 << chn;
+ }
+
+ adc_modinit_mask |= 1 << chn;
+
+ adc_busy_flag = 0;
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_ADC);
+}
+
+void analogin_deinit(PinName pin)
+{
+ analogin_t obj;
+ obj.adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj.adc != (ADCName) NC);
+
+ const struct nu_modinit_s *modinit = get_modinit(obj.adc, adc_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((ADCName) modinit->modname == obj.adc);
+
+ ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj.adc);
+ uint32_t chn = NU_MODSUBINDEX(obj.adc);
+
+ // Wait for ADC is not busy, due to all ADC channels share the same module
+ while (adc_busy_flag != 0) {
+ wait_us(100);
+ }
+ adc_busy_flag = 1;
+
+ // Disable channel N
+ adc_base->CHEN &= ~(1 << chn);
+ adc_modinit_mask &= ~(1 << chn);
+
+ adc_busy_flag = 0;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
+ uint32_t chn = NU_MODSUBINDEX(obj->adc);
+
+ // Wait for ADC is not busy, due to all ADC channels share the same module
+ while (adc_busy_flag != 0) {
+ wait_us(100);
+ }
+ adc_busy_flag = 1;
+
+ // Start the A/D conversion
+ adc_base->CR |= ADC_CR_ADST_Msk;
+ // Wait for conversion finish
+ while (! ADC_GET_INT_FLAG(adc_base, ADC_ADF_INT) & ADC_ADF_INT) ;
+ ADC_CLR_INT_FLAG(ADC, ADC_ADF_INT);
+ uint16_t conv_res_12 = ADC_GET_CONVERSION_DATA(adc_base, chn);
+
+ adc_busy_flag = 0;
+
+ // Just 12 bits are effective. Convert to 16 bits.
+ // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
+ // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
+ uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8);
+
+ return conv_res_16;
+}
+
+float analogin_read(analogin_t *obj)
+{
+ uint16_t value = analogin_read_u16(obj);
+ return (float) value * (1.0f / (float) 0xFFFF);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,11923 @@
+/**************************************************************************//**
+ * @file Nano100Series.h
+ * @version V1.00
+ * $Revision: 79 $
+ * $Date: 15/06/22 5:34p $
+ * @brief Nano100 series peripheral access layer header file.
+ * This file contains all the peripheral register's definitions,
+ * bits definitions and memory mapping for NuMicro Nano100 series MCU.
+ *
+ * @note
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+/**
+ \mainpage NuMicro NANO100BN Driver Reference Guide
+ *
+ * <b>Introduction</b>
+ *
+ * This user manual describes the usage of Nano100BN Series MCU device driver
+ *
+ * <b>Disclaimer</b>
+ *
+ * The Software is furnished "AS IS", without warranty as to performance or results, and
+ * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+ * warranties, express, implied or otherwise, with regard to the Software, its use, or
+ * operation, including without limitation any and all warranties of merchantability, fitness
+ * for a particular purpose, and non-infringement of intellectual property rights.
+ *
+ * <b>Important Notice</b>
+ *
+ * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
+ * any malfunction or failure of which may cause loss of human life, bodily injury or severe
+ * property damage. Such applications are deemed, "Insecure Usage".
+ *
+ * Insecure usage includes, but is not limited to: equipment for surgical implementation,
+ * atomic energy control instruments, airplane or spaceship instruments, the control or
+ * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
+ * instruments, all types of safety devices, and other applications intended to support or
+ * sustain life.
+ *
+ * All Insecure Usage shall be made at customer's risk, and in the event that third parties
+ * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
+ * the damages and liabilities thus incurred by Nuvoton.
+ *
+ * Please note that all data and specifications are subject to change without notice. All the
+ * trademarks of products and companies mentioned in this datasheet belong to their respective
+ * owners.
+ *
+ * <b>Copyright Notice</b>
+ *
+ * Copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved.
+ */
+#ifndef __NANO100SERIES_H__
+#define __NANO100SERIES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NANO100_Definitions NANO100 Definitions
+ This file defines all structures and symbols for Nano100:
+ - interrupt numbers
+ - registers and bit fields
+ - peripheral base address
+ - peripheral ID
+ - Peripheral definitions
+ @{
+*/
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup NANO100_CMSIS Device CMSIS Definitions
+ Configuration of the Cortex-M0 Processor and Core Peripherals
+ @{
+*/
+
+/**
+ * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
+ */
+typedef enum IRQn {
+ /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
+
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+ /****** Nano100 specific Interrupt Numbers ***********************************************/
+ BOD_IRQn = 0, /*!< Brownout low voltage detected interrupt */
+ WDT_IRQn = 1, /*!< Watch Dog Timer interrupt */
+ EINT0_IRQn = 2, /*!< External signal interrupt from PB.14 pin */
+ EINT1_IRQn = 3, /*!< External signal interrupt from PB.15 pin */
+ GPABC_IRQn = 4, /*!< External signal interrupt from PA[15:0]/PB[13:0]/PC[15:0] */
+ GPDEF_IRQn = 5, /*!< External interrupt from PD[15:0]/PE[15:0]/PF[15:0] */
+ PWM0_IRQn = 6, /*!< PWM 0 interrupt */
+ PWM1_IRQn = 7, /*!< PWM 1 interrupt */
+ TMR0_IRQn = 8, /*!< Timer 0 interrupt */
+ TMR1_IRQn = 9, /*!< Timer 1 interrupt */
+ TMR2_IRQn = 10, /*!< Timer 2 interrupt */
+ TMR3_IRQn = 11, /*!< Timer 3 interrupt */
+ UART0_IRQn = 12, /*!< UART0 interrupt */
+ UART1_IRQn = 13, /*!< UART1 interrupt */
+ SPI0_IRQn = 14, /*!< SPI0 interrupt */
+ SPI1_IRQn = 15, /*!< SPI1 interrupt */
+ SPI2_IRQn = 16, /*!< SPI2 interrupt */
+ HIRC_IRQn = 17, /*!< HIRC interrupt */
+ I2C0_IRQn = 18, /*!< I2C0 interrupt */
+ I2C1_IRQn = 19, /*!< I2C1 interrupt */
+ SC2_IRQn = 20, /*!< Smart Card 2 interrupt */
+ SC0_IRQn = 21, /*!< Smart Card 0 interrupt */
+ SC1_IRQn = 22, /*!< Smart Card 1 interrupt */
+ USBD_IRQn = 23, /*!< USB FS Device interrupt */
+ LCD_IRQn = 25, /*!< LCD interrupt */
+ PDMA_IRQn = 26, /*!< PDMA interrupt */
+ I2S_IRQn = 27, /*!< I2S interrupt */
+ PDWU_IRQn = 28, /*!< Power Down Wake up interrupt */
+ ADC_IRQn = 29, /*!< ADC interrupt */
+ DAC_IRQn = 30, /*!< DAC interrupt */
+ RTC_IRQn = 31 /*!< Real time clock interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __CM0_REV 0x0201 /*!< Core Revision r2p1 */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __FPU_PRESENT 0 /*!< FPU present or not */
+
+/*@}*/ /* end of group NANO100_CMSIS */
+
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_Nano100Series.h" /* Nano100 Series System include file */
+#include <stdint.h>
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+/** @addtogroup NANO100_Peripherals NANO100 Peripherals
+ NANO100 Device Specific Peripheral registers structures
+ @{
+*/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+/*---------------------- Analog to Digital Converter -------------------------*/
+/**
+ @addtogroup ADC Analog to Digital Converter(ADC)
+ Memory Mapped Structure for ADC Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * RESULT0, RESULT1.. RESULT17
+ * ===================================================================================================
+ * Offset: 0x00 ~0x44 A/D Data Register 0~17
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |RSLT |A/D Conversion Result
+ * | | |This field contains 12 bits conversion results.
+ * |[16] |VALID |Data Valid Flag
+ * | | |It is a mirror of VALID bit in ADC_RESULTx
+ * |[17] |OVERRUN |Over Run Flag
+ * | | |It is a mirror to OVERRUN bit in ADC_RESULTx
+ */
+ __I uint32_t RESULT[18];
+
+
+ /**
+ * CR
+ * ===================================================================================================
+ * Offset: 0x48 A/D Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADEN |A/D Converter Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |Before starting A/D conversion, this bit should be set to 1.
+ * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
+ * |[1] |ADIE |A/D Interrupt Enable
+ * | | |0 = A/D interrupt function Disabled.
+ * | | |1 = A/D interrupt function Enabled.
+ * | | |A/D conversion end interrupt request is generated if ADIE bit is set to 1.
+ * |[3:2] |ADMD |A/D Converter Operation Mode
+ * | | |00 = Single conversion
+ * | | |01 = Reserved
+ * | | |10 = Single-cycle scan
+ * | | |11 = Continuous scan
+ * |[5:4] |TRGS |Hardware Trigger Source
+ * | | |This field must keep 00
+ * | | |Software should disable TRGE and ADST before change TRGS.
+ * | | |In hardware trigger mode, the ADST bit is set by the external trigger from STADC, However software has the highest priority to set or cleared ADST bit at any time.
+ * |[7:6] |TRGCOND |External Trigger Condition
+ * | | |These two bits decide external pin STADC trigger event is level or edge.
+ * | | |The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
+ * | | |00 = Low level
+ * | | |01 = High level
+ * | | |10 = Falling edge
+ * | | |11 = Rising edge
+ * |[8] |TRGE |External Trigger Enable
+ * | | |Enable or disable triggering of A/D conversion by external STADC pin.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[9] |PTEN |PDMA Transfer Enable
+ * | | |0 = PDMA data transfer Disabled.
+ * | | |1 = PDMA data transfer in ADC_RESULT 0~17 Enabled.
+ * | | |When A/D conversion is completed, the converted data is loaded into ADC_RESULT 0~10, software can enable this bit to generate a PDMA data transfer request.
+ * | | |When PTEN=1, software must set ADIE=0 to disable interrupt.
+ * | | |PDMA can access ADC_RESULT 0-17 registers by block or single transfer mode.
+ * |[10] |DIFF |Differential Mode Selection
+ * | | |0 = ADC is operated in single-ended mode.
+ * | | |1 = ADC is operated in differential mode.
+ * | | |The A/D analog input ADC_CH0/ADC_CH1 consists of a differential pair.
+ * | | |So as ADC_CH2/ADC_CH3, ADC_CH4/ADC_CH5, ADC_CH6/ADC_CH7, ADC_CH8/ADC_CH9 and ADC_CH10/ADC_CH11.
+ * | | |The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus).
+ * | | |Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus is the analog input; Vminus is the inverted analog input.
+ * | | |In differential input mode, only the even number of the two corresponding channels needs to be enabled in CHEN (ADCHER[11:0]).
+ * | | |The conversion result will be placed to the corresponding data register of the enabled channel.
+ * | | |Note: Calibration should calibrated each time when switching between single-ended and differential mode
+ * |[11] |ADST |A/D Conversion Start
+ * | | |0 = Conversion stopped and A/D converter enter idle state.
+ * | | |1 = Conversion starts.
+ * | | |ADST bit can be set to 1 from two sources: software write and external pin STADC.
+ * | | |ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels.
+ * | | |In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.
+ * | | |Note: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again.
+ * |[13:12] |TMSEL |Select A/D Enable Time-Out Source
+ * | | |00 = TMR0
+ * | | |01 = TMR1
+ * | | |10 = TMR2
+ * | | |11 = TMR3
+ * |[15] |TMTRGMOD |Timer Event Trigger ADC Conversion
+ * | | |0 = This function Disabled.
+ * | | |1 = ADC Enabled by TIMER OUT event. Setting TMSEL to select timer event from timer0~3
+ * |[17:16] |REFSEL |Reference Voltage Source Selection
+ * | | |00 = Reserved
+ * | | |01 = Select Int_VREF as reference voltage
+ * | | |10 = Select VREF as reference voltage
+ * | | |11 = Reserved
+ * |[19:18] |RESSEL |Resolution Selection
+ * | | |00 = 6 bits
+ * | | |01 = 8 bits
+ * | | |10 = 10 bits
+ * | | |11 = 12 bits
+ * |[31:24] |TMPDMACNT |PDMA Count
+ * | | |When each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting
+ * | | |Note: The total amount of PDMA transferring data should be set in PDMA byte count register.
+ * | | |When PDMA finish is set, ADC will not be enabled and start transfer even though the timer event occurred.
+ */
+ __IO uint32_t CR;
+
+ /**
+ * CHEN
+ * ===================================================================================================
+ * Offset: 0x4C A/D Channel Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHEN0 |Analog Input Channel 0 Enable (Convert Input Voltage From PA.0 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |If more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored.
+ * |[1] |CHEN1 |Analog Input Channel 1 Enable(Convert Input Voltage From PA.1 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2] |CHEN2 |Analog Input Channel 2 Enable (Convert Input Voltage From PA.2 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[3] |CHEN3 |Analog Input Channel 3 Enable(Convert Input Voltage From PA.3 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[4] |CHEN4 |Analog Input Channel 4 Enable (Convert Input Voltage From PA.4 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[5] |CHEN5 |Analog Input Channel 5 Enable (Convert Input Voltage From PA.5 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[6] |CHEN6 |Analog Input Channel 6 Enable (Convert Input Voltage From PA.6 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[7] |CHEN7 |Analog Input Channel 7 Enable (Convert Input Voltage From PA.7 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[8] |CHEN8 |Analog Input Channel 8 Enable For DAC0 (Convert Input Voltage From PD.0 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[9] |CHEN9 |Analog Input Channel 9 Enable For DAC1 (Convert Input Voltage From PD.1 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[10] |CHEN10 |Analog Input Channel 10 Enable (Convert Input Voltage From PD.2 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[11] |CHEN11 |Analog Input Channel 11 Enable(Convert Input Voltage From PD.3 )
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[12] |CHEN12 |Analog Input Channel 12 Enable (Convert DAC0 Output Voltage)
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[13] |CHEN13 |Analog Input Channel 13 Enable (Convert DAC1 Output Voltage)
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[14] |CHEN14 |Analog Input Channel 14 Enable (Convert VTEMP)
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[15] |CHEN15 |Analog Input Channel 15 Enable (Convert Int_VREF)
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[16] |CHEN16 |Analog Input Channel 16 Enable (Convert AVDD)
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[17] |CHEN17 |Analog Input Channel 17 Enable (Convert AVSS)
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ */
+ __IO uint32_t CHEN;
+
+ /**
+ * CMPR0
+ * ===================================================================================================
+ * Offset: 0x50 A/D Compare Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CMPEN |Compare Enable
+ * | | |0 = Compare Disabled.
+ * | | |1 = Compare Enabled.
+ * | | |Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
+ * | | |When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
+ * |[1] |CMPIE |Compare Interrupt Enable
+ * | | |0 = Compare function interrupt Disabled.
+ * | | |1 = Compare function interrupt Enabled.
+ * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
+ * |[2] |CMPCOND |Compare Condition
+ * | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
+ * | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
+ * | | |Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
+ * |[7:3] |CMPCH |Compare Channel Selection
+ * | | |This field selects the channel whose conversion result is selected to be compared.
+ * |[11:8] |CMPMATCNT |Compare Match Count
+ * | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
+ * | | |When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
+ * |[27:16] |CMPD |Comparison Data
+ * | | |The 12 bits data is used to compare with conversion result of specified channel.
+ * | | |Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
+ */
+ __IO uint32_t CMPR0;
+
+ /**
+ * CMPR1
+ * ===================================================================================================
+ * Offset: 0x54 A/D Compare Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CMPEN |Compare Enable
+ * | | |0 = Compare Disabled.
+ * | | |1 = Compare Enabled.
+ * | | |Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
+ * | | |When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
+ * |[1] |CMPIE |Compare Interrupt Enable
+ * | | |0 = Compare function interrupt Disabled.
+ * | | |1 = Compare function interrupt Enabled.
+ * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
+ * |[2] |CMPCOND |Compare Condition
+ * | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
+ * | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
+ * | | |Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
+ * |[7:3] |CMPCH |Compare Channel Selection
+ * | | |This field selects the channel whose conversion result is selected to be compared.
+ * |[11:8] |CMPMATCNT |Compare Match Count
+ * | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
+ * | | |When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
+ * |[27:16] |CMPD |Comparison Data
+ * | | |The 12 bits data is used to compare with conversion result of specified channel.
+ * | | |Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
+ */
+ __IO uint32_t CMPR1;
+
+ /**
+ * SR
+ * ===================================================================================================
+ * Offset: 0x58 A/D Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADF |A/D Conversion End Flag
+ * | | |A status flag that indicates the end of A/D conversion.
+ * | | |ADF is set to 1 at these two conditions:
+ * | | |When A/D conversion ends in single mode
+ * | | |When A/D conversion ends on all specified channels in scan mode.
+ * | | |This flag can be cleared by writing 1 to it.
+ * |[1] |CMPF0 |Compare Flag
+ * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
+ * | | |And it is cleared by writing 1 to self.
+ * | | |0 = Conversion result in ADC_RESULTx does not meet ADCMPR0setting.
+ * | | |1 = Conversion result in ADC_RESULTx meets ADCMPR0setting.
+ * | | |This flag can be cleared by writing 1 to it.
+ * | | |Note: When this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0
+ * |[2] |CMPF1 |Compare Flag
+ * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
+ * | | |And it is cleared by writing 1 to self.
+ * | | |0 = Conversion result in ADC_RESULTx does not meet ADCMPR1 setting.
+ * | | |1 = Conversion result in ADC_RESULTx meets ADCMPR1 setting.
+ * | | |This flag can be cleared by writing 1 to it.
+ * | | |Note: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1
+ * |[3] |BUSY |BUSY/IDLE
+ * | | |0 = A/D converter is in idle state.
+ * | | |1 = A/D converter is busy at conversion.
+ * | | |This bit is a mirror of ADST bit in ADCR. That is to say if ADST = 1,then BUSY is 1 and vice versa.
+ * | | |It is read only.
+ * |[8:4] |CHANNEL |Current Conversion Channel
+ * | | |This filed reflects current conversion channel when BUSY=1.
+ * | | |When BUSY=0, it shows the next channel to be converted.
+ * | | |It is read only.
+ * |[16] |INITRDY |ADC Power-Up Sequence Completed
+ * | | |0 = ADC not powered up after system reset.
+ * | | |1 = ADC has been powered up since the last system reset.
+ * | | |Note: This bit will be set after system reset occurred and automatically cleared by power-up event.
+ */
+ __IO uint32_t SR;
+ uint32_t RESERVE0[1];
+
+
+ /**
+ * PDMA
+ * ===================================================================================================
+ * Offset: 0x60 A/D PDMA current transfer data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |AD_PDMA |ADC PDMA Current Transfer Data Register
+ * | | |When PDMA transferring, read this register can monitor current PDMA transfer data.
+ * | | |This is a read only register.
+ */
+ __I uint32_t PDMA;
+
+ /**
+ * PWRCTL
+ * ===================================================================================================
+ * Offset: 0x64 ADC Power Management Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWUPRDY |ADC Power-Up Sequence Completed And Ready For Conversion
+ * | | |0 = ADC is not ready for conversion; may be in power down state or in the progress of power up.
+ * | | |1 = ADC is ready for conversion.
+ * |[1] |PWDCALEN |Power Up Calibration Function Enable
+ * | | |1 = Power up with calibration.
+ * | | |0 = Power up without calibration.
+ * | | |Note: This bit work together with CALFBKSEL set 1
+ * |[3:2] |PWDMOD |Power-Down Mode
+ * | | |00 = Power down
+ * | | |01 = Reserved
+ * | | |10 = Standby mode
+ * | | |11 = Reserved
+ * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in powe down and power up
+ */
+ __IO uint32_t PWRCTL;
+
+ /**
+ * CALCTL
+ * ===================================================================================================
+ * Offset: 0x68 ADC Calibration Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CALEN |Calibration Function Enable
+ * | | |Enable this bit to turn on the calibration function block.
+ * | | |0 = Disable
+ * | | |1 = Enabled.
+ * |[1] |CALSTART |Calibration Functional Block Start
+ * | | |0 = Stops calibration functional block.
+ * | | |1 = Starts calibration functional block.
+ * | | |Note: This bit is set by SW and clear by HW; don't write 1 to this bit while CALEN = 0.
+ * |[2] |CALDONE |Calibrate Functional Block Complete
+ * | | |0 = Not yet.
+ * | | |1 = Selected functional block complete.
+ * |[3] |CALSEL |Select Calibration Functional Block
+ * | | |0 = Load calibration functional block.
+ * | | |1 = Calibration functional block.
+ */
+ __IO uint32_t CALCTL;
+
+ /**
+ * CALWORD
+ * ===================================================================================================
+ * Offset: 0x6C A/D calibration load word register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |CALWORD |Calibration Word Register
+ * | | |Write to this register with the previous calibration word before load calibration action
+ * | | |Read this register after calibration done
+ * | | |Note: The calibration block contains two parts "CALIBRATION" and "LOAD CALIBRATION"; if the calibration block is config as "CALIBRATION"; then this register represent the result of calibration when calibration is completed; if config as "LOAD CALIBRATION" ; config this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC;while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
+ */
+ __IO uint32_t CALWORD;
+
+ /**
+ * SMPLCNT0
+ * ===================================================================================================
+ * Offset: 0x70 ADC Channel Sampling Time Counter Register Group 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CH0SAMPCNT|Channel 0 Sampling Counter
+ * | | |0000 = 0 ADC clock
+ * | | |0001 = 1 ADC clock
+ * | | |0010 = 2 ADC clocks
+ * | | |0011 = 4 ADC clocks
+ * | | |0100 = 8 ADC clocks
+ * | | |0101 = 16 ADC clocks
+ * | | |0110 = 32 ADC clocks
+ * | | |0111 = 64 ADC clocks
+ * | | |1000 = 128 ADC clocks
+ * | | |1001 = 256 ADC clocks
+ * | | |1010 = 512 ADC clocks
+ * | | |Others = 1024 ADC clocks
+ * |[7:4] |CH1SAMPCNT|Channel 1 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[11:8] |CH2SAMPCNT|Channel 2 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[15:12] |CH3SAMPCNT|Channel 3 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[19:16] |CH4SAMPCNT|Channel 4 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[23:20] |CH5SAMPCNT|Channel 5 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[27:24] |CH6SAMPCNT|Channel 6 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[31:28] |CH7SAMPCNT|Channel 7 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ */
+ __IO uint32_t SMPLCNT0;
+
+ /**
+ * SMPLCNT1
+ * ===================================================================================================
+ * Offset: 0x74 ADC Channel Sampling Time Counter Register Group 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CH8SAMPCNT|Channel 8 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[7:4] |CH9SAMPCNT|Channel 9 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[11:8] |CH10SAMPCNT|Channel 10 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[15:12] |CH11SAMPCNT|Channel 11 Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ * |[19:16] |INTCHSAMPCNT|Internal Channel (VTEMP, AVDD, AVSS, Int_VREF, DAC0, DAC1) Sampling Counter
+ * | | |The same as Channel 0 sampling counter table.
+ */
+ __IO uint32_t SMPLCNT1;
+
+} ADC_T;
+
+/**
+ @addtogroup ADC_CONST ADC Bit Field Definition
+ Constant Definitions for ADC Controller
+@{ */
+#define ADC_RESULT_RSLT_Pos (0) /*!< ADC_T::RESULT: RSLT Position */
+#define ADC_RESULT_RSLT_Msk (0xffful << ADC_RESULT_RSLT_Pos) /*!< ADC_T::RESULT: RSLT Mask */
+
+#define ADC_RESULT_VALID_Pos (16) /*!< ADC_T::RESULT: VALID Position */
+#define ADC_RESULT_VALID_Msk (0x1ul << ADC_RESULT_VALID_Pos) /*!< ADC_T::RESULT: VALID Mask */
+
+#define ADC_RESULT_OVERRUN_Pos (17) /*!< ADC_T::RESULT: OVERRUN Position */
+#define ADC_RESULT_OVERRUN_Msk (0x1ul << ADC_RESULT_OVERRUN_Pos) /*!< ADC_T::RESULT: OVERRUN Mask */
+
+#define ADC_CR_ADEN_Pos (0) /*!< ADC_T::CR: ADEN Position */
+#define ADC_CR_ADEN_Msk (0x1ul << ADC_CR_ADEN_Pos) /*!< ADC_T::CR: ADEN Mask */
+
+#define ADC_CR_ADIE_Pos (1) /*!< ADC_T::CR: ADIE Position */
+#define ADC_CR_ADIE_Msk (0x1ul << ADC_CR_ADIE_Pos) /*!< ADC_T::CR: ADIE Mask */
+
+#define ADC_CR_ADMD_Pos (2) /*!< ADC_T::CR: ADMD Position */
+#define ADC_CR_ADMD_Msk (0x3ul << ADC_CR_ADMD_Pos) /*!< ADC_T::CR: ADMD Mask */
+
+#define ADC_CR_TRGS_Pos (4) /*!< ADC_T::CR: TRGS Position */
+#define ADC_CR_TRGS_Msk (0x3ul << ADC_CR_TRGS_Pos) /*!< ADC_T::CR: TRGS Mask */
+
+#define ADC_CR_TRGCOND_Pos (6) /*!< ADC_T::CR: TRGCOND Position */
+#define ADC_CR_TRGCOND_Msk (0x3ul << ADC_CR_TRGCOND_Pos) /*!< ADC_T::CR: TRGCOND Mask */
+
+#define ADC_CR_TRGE_Pos (8) /*!< ADC_T::CR: TRGE Position */
+#define ADC_CR_TRGE_Msk (0x1ul << ADC_CR_TRGE_Pos) /*!< ADC_T::CR: TRGE Mask */
+
+#define ADC_CR_PTEN_Pos (9) /*!< ADC_T::CR: PTEN Position */
+#define ADC_CR_PTEN_Msk (0x1ul << ADC_CR_PTEN_Pos) /*!< ADC_T::CR: PTEN Mask */
+
+#define ADC_CR_DIFF_Pos (10) /*!< ADC_T::CR: DIFF Position */
+#define ADC_CR_DIFF_Msk (0x1ul << ADC_CR_DIFF_Pos) /*!< ADC_T::CR: DIFF Mask */
+
+#define ADC_CR_ADST_Pos (11) /*!< ADC_T::CR: ADST Position */
+#define ADC_CR_ADST_Msk (0x1ul << ADC_CR_ADST_Pos) /*!< ADC_T::CR: ADST Mask */
+
+#define ADC_CR_TMSEL_Pos (12) /*!< ADC_T::CR: TMSEL Position */
+#define ADC_CR_TMSEL_Msk (0x3ul << ADC_CR_TMSEL_Pos) /*!< ADC_T::CR: TMSEL Mask */
+
+#define ADC_CR_TMTRGMOD_Pos (15) /*!< ADC_T::CR: TMTRGMOD Position */
+#define ADC_CR_TMTRGMOD_Msk (0x1ul << ADC_CR_TMTRGMOD_Pos) /*!< ADC_T::CR: TMTRGMOD Mask */
+
+#define ADC_CR_REFSEL_Pos (16) /*!< ADC_T::CR: REFSEL Position */
+#define ADC_CR_REFSEL_Msk (0x3ul << ADC_CR_REFSEL_Pos) /*!< ADC_T::CR: REFSEL Mask */
+
+#define ADC_CR_RESSEL_Pos (18) /*!< ADC_T::CR: RESSEL Position */
+#define ADC_CR_RESSEL_Msk (0x3ul << ADC_CR_RESSEL_Pos) /*!< ADC_T::CR: RESSEL Mask */
+
+#define ADC_CR_TMPDMACNT_Pos (24) /*!< ADC_T::CR: TMPDMACNT Position */
+#define ADC_CR_TMPDMACNT_Msk (0xfful << ADC_CR_TMPDMACNT_Pos) /*!< ADC_T::CR: TMPDMACNT Mask */
+
+#define ADC_CHEN_CHEN0_Pos (0) /*!< ADC_T::CHEN: CHEN0 Position */
+#define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos) /*!< ADC_T::CHEN: CHEN0 Mask */
+
+#define ADC_CMPR_CMPEN_Pos (0) /*!< ADC_T::CMPR: CMPEN Position */
+#define ADC_CMPR_CMPEN_Msk (0x1ul << ADC_CMPR_CMPEN_Pos) /*!< ADC_T::CMPR: CMPEN Mask */
+
+#define ADC_CMPR_CMPIE_Pos (1) /*!< ADC_T::CMPR: CMPIE Position */
+#define ADC_CMPR_CMPIE_Msk (0x1ul << ADC_CMPR_CMPIE_Pos) /*!< ADC_T::CMPR: CMPIE Mask */
+
+#define ADC_CMPR_CMPCOND_Pos (2) /*!< ADC_T::CMPR: CMPCOND Position */
+#define ADC_CMPR_CMPCOND_Msk (0x1ul << ADC_CMPR_CMPCOND_Pos) /*!< ADC_T::CMPR: CMPCOND Mask */
+
+#define ADC_CMPR_CMPCH_Pos (3) /*!< ADC_T::CMPR: CMPCH Position */
+#define ADC_CMPR_CMPCH_Msk (0x1ful << ADC_CMPR_CMPCH_Pos) /*!< ADC_T::CMPR: CMPCH Mask */
+
+#define ADC_CMPR_CMPMATCNT_Pos (8) /*!< ADC_T::CMPR: CMPMATCNT Position */
+#define ADC_CMPR_CMPMATCNT_Msk (0xful << ADC_CMPR_CMPMATCNT_Pos) /*!< ADC_T::CMPR: CMPMATCNT Mask */
+
+#define ADC_CMPR_CMPD_Pos (16) /*!< ADC_T::CMPR: CMPD Position */
+#define ADC_CMPR_CMPD_Msk (0xffful << ADC_CMPR_CMPD_Pos) /*!< ADC_T::CMPR: CMPD Mask */
+
+#define ADC_SR_ADF_Pos (0) /*!< ADC_T::SR: ADF Position */
+#define ADC_SR_ADF_Msk (0x1ul << ADC_SR_ADF_Pos) /*!< ADC_T::SR: ADF Mask */
+
+#define ADC_SR_CMPF0_Pos (1) /*!< ADC_T::SR: CMPF0 Position */
+#define ADC_SR_CMPF0_Msk (0x1ul << ADC_SR_CMPF0_Pos) /*!< ADC_T::SR: CMPF0 Mask */
+
+#define ADC_SR_CMPF1_Pos (2) /*!< ADC_T::SR: CMPF1 Position */
+#define ADC_SR_CMPF1_Msk (0x1ul << ADC_SR_CMPF1_Pos) /*!< ADC_T::SR: CMPF1 Mask */
+
+#define ADC_SR_BUSY_Pos (3) /*!< ADC_T::SR: BUSY Position */
+#define ADC_SR_BUSY_Msk (0x1ul << ADC_SR_BUSY_Pos) /*!< ADC_T::SR: BUSY Mask */
+
+#define ADC_SR_CHANNEL_Pos (4) /*!< ADC_T::SR: CHANNEL Position */
+#define ADC_SR_CHANNEL_Msk (0x1ful << ADC_SR_CHANNEL_Pos) /*!< ADC_T::SR: CHANNEL Mask */
+
+#define ADC_SR_INITRDY_Pos (16) /*!< ADC_T::SR: INITRDY Position */
+#define ADC_SR_INITRDY_Msk (0x1ul << ADC_SR_INITRDY_Pos) /*!< ADC_T::SR: INITRDY Mask */
+
+#define ADC_PDMA_AD_PDMA_Pos (0) /*!< ADC_T::PDMA: AD_PDMA Position */
+#define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos) /*!< ADC_T::PDMA: AD_PDMA Mask */
+
+#define ADC_PWRCTL_PWUPRDY_Pos (0) /*!< ADC_T::PWRCTL: PWUPRDY Position */
+#define ADC_PWRCTL_PWUPRDY_Msk (0x1ul << ADC_PWRCTL_PWUPRDY_Pos) /*!< ADC_T::PWRCTL: PWUPRDY Mask */
+
+#define ADC_PWRCTL_PWDCALEN_Pos (1) /*!< ADC_T::PWRCTL: PWDCALEN Position */
+#define ADC_PWRCTL_PWDCALEN_Msk (0x1ul << ADC_PWRCTL_PWDCALEN_Pos) /*!< ADC_T::PWRCTL: PWDCALEN Mask */
+
+#define ADC_PWRCTL_PWDMOD_Pos (2) /*!< ADC_T::PWRCTL: PWDMOD Position */
+#define ADC_PWRCTL_PWDMOD_Msk (0x3ul << ADC_PWRCTL_PWDMOD_Pos) /*!< ADC_T::PWRCTL: PWDMOD Mask */
+
+#define ADC_CALCTL_CALEN_Pos (0) /*!< ADC_T::CALCTL: CALEN Position */
+#define ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos) /*!< ADC_T::CALCTL: CALEN Mask */
+
+#define ADC_CALCTL_CALSTART_Pos (1) /*!< ADC_T::CALCTL: CALSTART Position */
+#define ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos) /*!< ADC_T::CALCTL: CALSTART Mask */
+
+#define ADC_CALCTL_CALDONE_Pos (2) /*!< ADC_T::CALCTL: CALDONE Position */
+#define ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos) /*!< ADC_T::CALCTL: CALDONE Mask */
+
+#define ADC_CALCTL_CALSEL_Pos (3) /*!< ADC_T::CALCTL: CALSEL Position */
+#define ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos) /*!< ADC_T::CALCTL: CALSEL Mask */
+
+#define ADC_CALWORD_CALWORD_Pos (0) /*!< ADC_T::CALWORD: CALWORD Position */
+#define ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos) /*!< ADC_T::CALWORD: CALWORD Mask */
+
+#define ADC_SMPLCNT0_CH0SAMPCNT_Pos (0) /*!< ADC_T::SMPLCNT0: CH0SAMPCNT Position */
+#define ADC_SMPLCNT0_CH0SAMPCNT_Msk (0xful << ADC_SMPLCNT0_CH0SAMPCNT_Pos) /*!< ADC_T::SMPLCNT0: CH0SAMPCNT Mask */
+
+#define ADC_SMPLCNT1_CH8SAMPCNT_Pos (0) /*!< ADC_T::SMPLCNT1: CH8SAMPCNT Position */
+#define ADC_SMPLCNT1_CH8SAMPCNT_Msk (0xful << ADC_SMPLCNT1_CH8SAMPCNT_Pos) /*!< ADC_T::SMPLCNT1: CH8SAMPCNT Mask */
+
+#define ADC_SMPLCNT1_INTCHSAMPCNT_Pos (16) /*!< ADC_T::SMPLCNT1: INTCHSAMPCNT Position */
+#define ADC_SMPLCNT1_INTCHSAMPCNT_Msk (0xful << ADC_SMPLCNT1_INTCHSAMPCNT_Pos) /*!< ADC_T::SMPLCNT1: INTCHSAMPCNT Mask */
+
+/**@}*/ /* ADC_CONST */
+/**@}*/ /* end of ADC register group */
+
+
+/*---------------------- System Clock Controller -------------------------*/
+/**
+ @addtogroup CLK System Clock Controller(CLK)
+ Memory Mapped Structure for CLK Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * PWRCTL
+ * ===================================================================================================
+ * Offset: 0x00 System Power Down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXT_EN |HXT Control
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |The bit default value is set by flash controller user configuration register config0 [26].
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |HXT is disabled by default.
+ * |[1] |LXT_EN |LXT Control
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |LXT is disabled by default.
+ * |[2] |HIRC_EN |HIRC Control
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |HIRC is enabled by default.
+ * |[3] |LIRC_EN |LIRC Control
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |LIRC is enabled by default.
+ * |[4] |WK_DLY |Wake-Up Delay Counter Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |When chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.
+ * | | |0 = Delay clock cycle Disabled.
+ * | | |1 = Delay clock cycle Enabled.
+ * |[5] |PD_WK_IE |Power-Down Mode Wake-Up Interrupt Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |PD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high.
+ * |[6] |PD_EN |Chip Power-Down Mode Enable Bit
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active
+ * | | |When chip wakes up from Power-down mode, this bit will be auto cleared.
+ * | | |When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode.
+ * | | |When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection.
+ * | | |Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC.
+ * | | |In Power-down mode, flash macro power is ON.
+ * | | |0 = Chip operated in Normal mode.
+ * | | |1 = Chip power down Enabled.
+ * |[8] |HXT_SELXT |HXT SELXT
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = High frequency crystal loop back path Disabled. It is used for external oscillator.
+ * | | |1 = High frequency crystal loop back path Enabled. It is used for external crystal.
+ * |[9] |HXT_GAIN |HXT Gain Control Bit
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Gain control is used to enlarge the gain of crystal to make sure crystal wok normally.
+ * | | |If gain control is enabled, crystal will consume more power than gain control off.
+ * | | |0 = Gain control Disabled. It means HXT gain is always high.
+ * | | |For 16MHz to 24MHz crystal.
+ * | | |1 = Gain control Enabled. HXT gain will be high lasting 2ms then low. This is for power saving.
+ * | | |For 4MHz to 16MHz crystal.
+ * |[10] |LXT_SCNT |LXT Stable Time Control
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Delay 4096 LXT before LXT output.
+ * | | |1 = Delay 8192 LXT before LXT output.
+ * |[12:11] |HXT_HF_ST |HXT Frequency Selection
+ * | | |Set this bit to meet HXT frequency selection (Recommended)
+ * | | |00 = HXT frequency is from 4 MHz to 12 MHz.
+ * | | |01 = HXT frequency is from 12 MHz to 16 MHz.
+ * | | |10 = HXT frequency is from 16 MHz to 24 MHz.
+ * | | |11 = Reserved.
+ */
+ __IO uint32_t PWRCTL;
+
+ /**
+ * AHBCLK
+ * ===================================================================================================
+ * Offset: 0x04 AHB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GPIO_EN |GPIO Controller Clock Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[1] |DMA_EN |DMA Controller Clock Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2] |ISP_EN |Flash ISP Controller Clock Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[3] |EBI_EN |EBI Controller Clock Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[4] |SRAM_EN |SRAM Controller Clock Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[5] |TICK_EN |System Tick Clock Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ */
+ __IO uint32_t AHBCLK;
+
+ /**
+ * APBCLK
+ * ===================================================================================================
+ * Offset: 0x08 APB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WDT_EN |Watchdog Timer Clock Enable Control
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[1] |RTC_EN |Real-Time-Clock Clock Enable Control
+ * | | |This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2] |TMR0_EN |Timer0 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[3] |TMR1_EN |Timer1 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[4] |TMR2_EN |Timer2 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[5] |TMR3_EN |Timer3 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[6] |FDIV_EN |Frequency Divider Output Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[7] |SC2_EN |SmartCard 2 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[8] |I2C0_EN |I2C0 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[9] |I2C1_EN |I2C1 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[12] |SPI0_EN |SPI0 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[13] |SPI1_EN |SPI1 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[14] |SPI2_EN |SPI2 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[16] |UART0_EN |UART0 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[17] |UART1_EN |UART1 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[20] |PWM0_CH01_EN|PWM0 Channel 0 And Channel 1Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[21] |PWM0_CH23_EN|PWM0 Channel 2 And Channel 3 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[22] |PWM1_CH01_EN|PWM1 Channel 0 And Channel 1 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[23] |PWM1_CH23_EN|PWM1 Channel 2 And Channel 3 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[25] |DAC_EN |12-Bit DAC Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[26] |LCD_EN |LCD Controller Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[27] |USBD_EN |USB FS Device Controller Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[28] |ADC_EN |Analog-Digital-Converter (ADC) Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[29] |I2S_EN |I2S Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[30] |SC0_EN |SmartCard 0 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[31] |SC1_EN |SmartCard 1 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ */
+ __IO uint32_t APBCLK;
+
+ /**
+ * CLKSTATUS
+ * ===================================================================================================
+ * Offset: 0x0C Clock status monitor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXT_STB |HXT Clock Source Stable Flag
+ * | | |0 = HXT clock is not stable or not enable.
+ * | | |1 = HXT clock is stable.
+ * |[1] |LXT_STB |LXT Clock Source Stable Flag
+ * | | |0 = LXT clock is not stable or not enable.
+ * | | |1 = LXT clock is stable.
+ * |[2] |PLL_STB |PLL Clock Source Stable Flag
+ * | | |0 = PLL clock is not stable or not enable.
+ * | | |1 = PLL clock is stable.
+ * |[3] |LIRC_STB |LIRC Clock Source Stable Flag
+ * | | |0 = LIRC clock is not stable or not enable.
+ * | | |1 = LIRC clock is stable.
+ * |[4] |HIRC_STB |HIRC Clock Source Stable Flag
+ * | | |0 = HIRC clock is not stable or not enable.
+ * | | |1 = HIRC clock is stable.
+ * |[7] |CLK_SW_FAIL|Clock Switch Fail Flag
+ * | | |0 = Clock switch success.
+ * | | |1 = Clock switch fail.
+ * | | |This bit will be set when target switch Clock Source is not stable. This bit is write 1 clear
+ */
+ __I uint32_t CLKSTATUS;
+
+ /**
+ * CLKSEL0
+ * ===================================================================================================
+ * Offset: 0x10 Clock Source Select Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |HCLK_S |HCLK Clock Source Selection
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Note:
+ * | | |Before Clock Source switches, the related clock sources (pre-select and new-select) must be turn on
+ * | | |The 3-bit default value is reloaded with the value of CFOSC (Config0[26:24]) in user configuration register in Flash controller by any reset.
+ * | | |Therefore the default value is either 000b or 111b.
+ * | | |000 = HXT
+ * | | |001 = LXT
+ * | | |010 = PLL Clock
+ * | | |011 = LIRC
+ * | | |111 = HIRC
+ * | | |Others = Reserved
+ */
+ __IO uint32_t CLKSEL0;
+
+ /**
+ * CLKSEL1
+ * ===================================================================================================
+ * Offset: 0x14 Clock Source Select Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |UART_S |UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection)
+ * | | |00 = HXT
+ * | | |01 = LXT
+ * | | |10 = PLL Clock
+ * | | |11 = HIRC
+ * |[3:2] |ADC_S |ADC Clock Source Selection
+ * | | |00 = HXT
+ * | | |01 = LXT
+ * | | |10 = PLL Clock
+ * | | |11 = HIRC
+ * |[5:4] |PWM0_CH01_S|PWM0 Channel 0 And Channel 1 Clock Source Selection
+ * | | |PWM0 channel 0 and channel 1 use the same Engine clock source, both of them with the same prescaler
+ * | | |00 = HXT
+ * | | |01 = LXT
+ * | | |10 = HCLK
+ * | | |11 = HIRC
+ * |[7:6] |PWM0_CH23_S|PWM0 Channel 2 And Channel 3 Clock Source Selection
+ * | | |PWM0 channel 2 and channel 3 use the same Engine clock source, both of them with the same prescaler
+ * | | |00 = HXT
+ * | | |01 = LXT
+ * | | |10 = HCLK
+ * | | |11 = HIRC
+ * |[10:8] |TMR0_S |Timer0 Clock Source Selection
+ * | | |000 = HXT
+ * | | |001 = LXT
+ * | | |010 = LIRC
+ * | | |011 = External Pin
+ * | | |111 = HIRC
+ * | | |Others = Reserved
+ * |[14:12] |TMR1_S |Timer1 Clock Source Selection
+ * | | |000 = HXT
+ * | | |001 = LXT
+ * | | |010 = LIRC
+ * | | |011 = External Pin
+ * | | |111 = HIRC
+ * | | |Others = Reserved
+ * |[18] |LCD_S |LCD Clock Source Selection
+ * | | |0 = Clock Source from LXT.
+ * | | |1 = Reserved.
+ */
+ __IO uint32_t CLKSEL1;
+
+ /**
+ * CLKSEL2
+ * ===================================================================================================
+ * Offset: 0x18 Clock Source Select Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:2] |FRQDIV_S |Clock Divider Clock Source Selection
+ * | | |00 = HXT
+ * | | |01 = LXT
+ * | | |10 = HCLK
+ * | | |11 = HIRC
+ * |[5:4] |PWM1_CH01_S|PWM1 Channel 0 And Channel 1 Clock Source Selection
+ * | | |PWM1 channel 0 and channel 1 use the same Engine clock source, both of them with the same pre-scale
+ * | | |00 = HXT
+ * | | |01 = LXT
+ * | | |10 = HCLK
+ * | | |11 = HIRC
+ * |[7:6] |PWM1_CH23_S|PWM1 Channel 2 And Channel 2 Clock Source Selection
+ * | | |PWM1 channel 2 and channel 3 use the same Engine clock source, both of them with the same pre-scale
+ * | | |00 = HXT
+ * | | |01 = LXT
+ * | | |10 = HCLK
+ * | | |11 = HIRC
+ * |[10:8] |TMR2_S |Timer2 Clock Source Selection
+ * | | |000 = HXT
+ * | | |001 = LXT
+ * | | |010 = LIRC
+ * | | |011 = External Pin
+ * | | |111 = HIRC
+ * | | |Others = Reserved
+ * |[14:12] |TMR3_S |Timer3 Clock Source Selection
+ * | | |000 = HXT
+ * | | |001 = LXT
+ * | | |010 = LIRC
+ * | | |011 = External Pin
+ * | | |111 = HIRC
+ * | | |Others = Reserved
+ * |[17:16] |I2S_S |I2S Clock Source Selection
+ * | | |00 = HXT
+ * | | |01 = PLL Clock
+ * | | |10 = HIRC
+ * | | |11 = HIRC
+ * |[19:18] |SC_S |SC Clock Source Selection
+ * | | |00 = HXT
+ * | | |01 = PLL Clock
+ * | | |10 = HIRC
+ * | | |11 = HIRC
+ * | | |Note: SC0,SC1 and SC2 use the same Clock Source selection but they have different clock divider number.
+ * |[20] |SPI0_S |SPI0 Clock Source Selection
+ * | | |0 = PLL.
+ * | | |1 = HCLK.
+ * |[21] |SPI1_S |SPI1 Clock Source Selection
+ * | | |0 = PLL.
+ * | | |1 = HCLK.
+ * |[22] |SPI2_S |SPI2 Clock Source Selection
+ * | | |0 = PLL.
+ * | | |1 = HCLK.
+ */
+ __IO uint32_t CLKSEL2;
+
+ /**
+ * CLKDIV0
+ * ===================================================================================================
+ * Offset: 0x1C Clock Divider Number Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |HCLK_N |HCLK Clock Divide Number From HCLK Clock Source
+ * | | |The HCLK clock frequency = (HCLK Clock Source frequency) / (HCLK_N + 1).
+ * |[7:4] |USB_N |USB Clock Divide Number From PLL Clock
+ * | | |The USB clock frequency = (PLL frequency ) / (USB_N + 1).
+ * |[11:8] |UART_N |UART Clock Divide Number From UART Clock Source
+ * | | |The UART clock frequency = (UART Clock Source frequency ) / (UART_N + 1).
+ * |[15:12] |I2S_N |I2S Clock Divide Number From I2S Clock Source
+ * | | |The I2S clock frequency = (I2S Clock Source frequency ) / (I2S_N + 1).
+ * |[23:16] |ADC_N |ADC Clock Divide Number From ADC Clock Source
+ * | | |The ADC clock frequency = (ADC Clock Source frequency ) / (ADC_N + 1).
+ * |[31:28] |SC0_N |SC 0 Clock Divide Number From SC 0 Clock Source
+ * | | |The SC 0 clock frequency = (SC0 Clock Source frequency ) / (SC0_N + 1).
+ */
+ __IO uint32_t CLKDIV0;
+
+ /**
+ * CLKDIV1
+ * ===================================================================================================
+ * Offset: 0x20 Clock Divider Number Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SC1_N |SC 1 Clock Divide Number From SC 1 Clock Source
+ * | | |The SC 1 clock frequency = (SC 1 Clock Source frequency ) / (SC1_N + 1).
+ * |[7:4] |SC2_N |SC 2 Clock Divide Number From SC2 Clock Source
+ * | | |The SC 2 clock frequency = (SC 2 Clock Source frequency ) / (SC2_N + 1).
+ */
+ __IO uint32_t CLKDIV1;
+
+ /**
+ * PLLCTL
+ * ===================================================================================================
+ * Offset: 0x24 PLL Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |FB_DV |PLL Feedback Divider Control Pins
+ * | | |Refer to the formulas below the table.
+ * | | |The range of FB_DV is from 0 to 63.
+ * |[9:8] |IN_DV |PLL Input Divider Control Pins
+ * | | |Refer to the formulas below the table.
+ * |[12] |OUT_DV |PLL Output Divider Control Pins
+ * | | |Refer to the formulas below the table. This bit MUST be 0 for PLL output low deviation.
+ * |[16] |PD |Power-Down Mode
+ * | | |If set the PD_EN bit "1" in PWR_CTL register, the PLL will enter Power-down mode too
+ * | | |0 = PLL is in normal mode.
+ * | | |1 = PLL is in power-down mode (default).
+ * |[17] |PLL_SRC |PLL Source Clock Select
+ * | | |0 = PLL source clock from HXT.
+ * | | |1 = PLL source clock from HIRC.
+ */
+ __IO uint32_t PLLCTL;
+
+ /**
+ * FRQDIV
+ * ===================================================================================================
+ * Offset: 0x28 Frequency Divider Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |FSEL |Divider Output Frequency Selection Bits
+ * | | |The formula of output frequency is
+ * | | |Fout = Fin/2^(N+1),.
+ * | | |Where Fin is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
+ * |[4] |FDIV_EN |Frequency Divider Enable Bit
+ * | | |0 = Frequency Divider Disabled.
+ * | | |1 = Frequency Divider Enabled.
+ */
+ __IO uint32_t FRQDIV;
+
+ /**
+ * MCLKO
+ * ===================================================================================================
+ * Offset: 0x2C Module Clock Output Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |MCLK_SEL |Module Clock Output Source Selection (PC.0)
+ * | | |000000 = ISP_CLK
+ * | | |000001 = HIRC
+ * | | |000010 = HXT
+ * | | |000011 = LXT
+ * | | |000100 = LIRC
+ * | | |000101 = PLL output
+ * | | |000110 = PLL input
+ * | | |000111 = System Tick
+ * | | |001000 = HCLK clock
+ * | | |001010 = PCLK clock
+ * | | |100000 = TMR0_CLK
+ * | | |100001 = TMR1_CLK
+ * | | |100010 = UART0_CLK
+ * | | |100011 = USB_CLK
+ * | | |100100 = ADC_CLK
+ * | | |100101 = WDT_CLK
+ * | | |100110 = PWM0_CH01_CLK
+ * | | |100111 = PWM0_CH32_CLK
+ * | | |101001 = LCD_CLK
+ * | | |111000 = TMR2_CLK
+ * | | |111001 = TMR3_CLK
+ * | | |111010 = UART1_CLK
+ * | | |111011 = PWM1_CH01_CLK
+ * | | |111100 = PWM1_CH23_CLK
+ * | | |111101 = I²S_CLK
+ * | | |111110 = SC0_CLK
+ * | | |111111 = SC1_CLK
+ * |[7] |MCLK_EN |Module Clock Output Enable
+ * | | |User can get the module clock output from PC.0 pin via choosing the clock source in the MCLK_SEL bit field and then setting MCLK_EN bit to 1.
+ * | | |0 = Module clock output Disabled.
+ * | | |1 = Module clock output Enabled.
+ * | | |Note: If this bit is enabled, PC.0 will be configured to module clock output and the setting of PC0_MFP will be ineffective
+ */
+ __IO uint32_t MCLKO;
+
+ /**
+ * WK_INTSTS
+ * ===================================================================================================
+ * Offset: 0x30 Wake-up interrupt status
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PD_WK_IS |Wake-Up Interrupt Status In Chip Power-Down Mode
+ * | | |This bit indicates that some event resumes chip from Power-down mode
+ * | | |The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.
+ * | | |Write 1 to clear this bit.
+ */
+ __IO uint32_t WK_INTSTS;
+
+} CLK_T;
+
+/**
+ @addtogroup CLK_CONST CLK Bit Field Definition
+ Constant Definitions for CLK Controller
+@{ */
+
+#define CLK_PWRCTL_HXT_EN_Pos (0) /*!< CLK_T::PWRCTL: HXT_EN Position */
+#define CLK_PWRCTL_HXT_EN_Msk (0x1ul << CLK_PWRCTL_HXT_EN_Pos) /*!< CLK_T::PWRCTL: HXT_EN Mask */
+
+#define CLK_PWRCTL_LXT_EN_Pos (1) /*!< CLK_T::PWRCTL: LXT_EN Position */
+#define CLK_PWRCTL_LXT_EN_Msk (0x1ul << CLK_PWRCTL_LXT_EN_Pos) /*!< CLK_T::PWRCTL: LXT_EN Mask */
+
+#define CLK_PWRCTL_HIRC_EN_Pos (2) /*!< CLK_T::PWRCTL: HIRC_EN Position */
+#define CLK_PWRCTL_HIRC_EN_Msk (0x1ul << CLK_PWRCTL_HIRC_EN_Pos) /*!< CLK_T::PWRCTL: HIRC_EN Mask */
+
+#define CLK_PWRCTL_LIRC_EN_Pos (3) /*!< CLK_T::PWRCTL: LIRC_EN Position */
+#define CLK_PWRCTL_LIRC_EN_Msk (0x1ul << CLK_PWRCTL_LIRC_EN_Pos) /*!< CLK_T::PWRCTL: LIRC_EN Mask */
+
+#define CLK_PWRCTL_WK_DLY_Pos (4) /*!< CLK_T::PWRCTL: WK_DLY Position */
+#define CLK_PWRCTL_WK_DLY_Msk (0x1ul << CLK_PWRCTL_WK_DLY_Pos) /*!< CLK_T::PWRCTL: WK_DLY Mask */
+
+#define CLK_PWRCTL_PD_WK_IE_Pos (5) /*!< CLK_T::PWRCTL: PD_WK_IE Position */
+#define CLK_PWRCTL_PD_WK_IE_Msk (0x1ul << CLK_PWRCTL_PD_WK_IE_Pos) /*!< CLK_T::PWRCTL: PD_WK_IE Mask */
+
+#define CLK_PWRCTL_PD_EN_Pos (6) /*!< CLK_T::PWRCTL: PD_EN Position */
+#define CLK_PWRCTL_PD_EN_Msk (0x1ul << CLK_PWRCTL_PD_EN_Pos) /*!< CLK_T::PWRCTL: PD_EN Mask */
+
+#define CLK_PWRCTL_HXT_SELXT_Pos (8) /*!< CLK_T::PWRCTL: HXT_SELXT Position */
+#define CLK_PWRCTL_HXT_SELXT_Msk (0x1ul << CLK_PWRCTL_HXT_SELXT_Pos) /*!< CLK_T::PWRCTL: HXT_SELXT Mask */
+
+#define CLK_PWRCTL_HXT_GAIN_Pos (9) /*!< CLK_T::PWRCTL: HXT_GAIN Position */
+#define CLK_PWRCTL_HXT_GAIN_Msk (0x1ul << CLK_PWRCTL_HXT_GAIN_Pos) /*!< CLK_T::PWRCTL: HXT_GAIN Mask */
+
+#define CLK_PWRCTL_LXT_SCNT_Pos (10) /*!< CLK_T::PWRCTL: LXT_SCNT Position */
+#define CLK_PWRCTL_LXT_SCNT_Msk (0x1ul << CLK_PWRCTL_LXT_SCNT_Pos) /*!< CLK_T::PWRCTL: LXT_SCNT Mask */
+
+#define CLK_PWRCTL_HXT_HF_ST_Pos (11) /*!< CLK_T::PWRCTL: HXT_HF_ST Position */
+#define CLK_PWRCTL_HXT_HF_ST_Msk (0x3ul << CLK_PWRCTL_HXT_HF_ST_Pos) /*!< CLK_T::PWRCTL: HXT_HF_ST Mask */
+
+#define CLK_AHBCLK_GPIO_EN_Pos (0) /*!< CLK_T::AHBCLK: GPIO_EN Position */
+#define CLK_AHBCLK_GPIO_EN_Msk (0x1ul << CLK_AHBCLK_GPIO_EN_Pos) /*!< CLK_T::AHBCLK: GPIO_EN Mask */
+
+#define CLK_AHBCLK_DMA_EN_Pos (1) /*!< CLK_T::AHBCLK: DMA_EN Position */
+#define CLK_AHBCLK_DMA_EN_Msk (0x1ul << CLK_AHBCLK_DMA_EN_Pos) /*!< CLK_T::AHBCLK: DMA_EN Mask */
+
+#define CLK_AHBCLK_ISP_EN_Pos (2) /*!< CLK_T::AHBCLK: ISP_EN Position */
+#define CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos) /*!< CLK_T::AHBCLK: ISP_EN Mask */
+
+#define CLK_AHBCLK_EBI_EN_Pos (3) /*!< CLK_T::AHBCLK: EBI_EN Position */
+#define CLK_AHBCLK_EBI_EN_Msk (0x1ul << CLK_AHBCLK_EBI_EN_Pos) /*!< CLK_T::AHBCLK: EBI_EN Mask */
+
+#define CLK_AHBCLK_SRAM_EN_Pos (4) /*!< CLK_T::AHBCLK: SRAM_EN Position */
+#define CLK_AHBCLK_SRAM_EN_Msk (0x1ul << CLK_AHBCLK_SRAM_EN_Pos) /*!< CLK_T::AHBCLK: SRAM_EN Mask */
+
+#define CLK_AHBCLK_TICK_EN_Pos (5) /*!< CLK_T::AHBCLK: TICK_EN Position */
+#define CLK_AHBCLK_TICK_EN_Msk (0x1ul << CLK_AHBCLK_TICK_EN_Pos) /*!< CLK_T::AHBCLK: TICK_EN Mask */
+
+#define CLK_APBCLK_WDT_EN_Pos (0) /*!< CLK_T::APBCLK: WDT_EN Position */
+#define CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos) /*!< CLK_T::APBCLK: WDT_EN Mask */
+
+#define CLK_APBCLK_RTC_EN_Pos (1) /*!< CLK_T::APBCLK: RTC_EN Position */
+#define CLK_APBCLK_RTC_EN_Msk (0x1ul << CLK_APBCLK_RTC_EN_Pos) /*!< CLK_T::APBCLK: RTC_EN Mask */
+
+#define CLK_APBCLK_TMR0_EN_Pos (2) /*!< CLK_T::APBCLK: TMR0_EN Position */
+#define CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos) /*!< CLK_T::APBCLK: TMR0_EN Mask */
+
+#define CLK_APBCLK_TMR1_EN_Pos (3) /*!< CLK_T::APBCLK: TMR1_EN Position */
+#define CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos) /*!< CLK_T::APBCLK: TMR1_EN Mask */
+
+#define CLK_APBCLK_TMR2_EN_Pos (4) /*!< CLK_T::APBCLK: TMR2_EN Position */
+#define CLK_APBCLK_TMR2_EN_Msk (0x1ul << CLK_APBCLK_TMR2_EN_Pos) /*!< CLK_T::APBCLK: TMR2_EN Mask */
+
+#define CLK_APBCLK_TMR3_EN_Pos (5) /*!< CLK_T::APBCLK: TMR3_EN Position */
+#define CLK_APBCLK_TMR3_EN_Msk (0x1ul << CLK_APBCLK_TMR3_EN_Pos) /*!< CLK_T::APBCLK: TMR3_EN Mask */
+
+#define CLK_APBCLK_FDIV_EN_Pos (6) /*!< CLK_T::APBCLK: FDIV_EN Position */
+#define CLK_APBCLK_FDIV_EN_Msk (0x1ul << CLK_APBCLK_FDIV_EN_Pos) /*!< CLK_T::APBCLK: FDIV_EN Mask */
+
+#define CLK_APBCLK_SC2_EN_Pos (7) /*!< CLK_T::APBCLK: SC2_EN Position */
+#define CLK_APBCLK_SC2_EN_Msk (0x1ul << CLK_APBCLK_SC2_EN_Pos) /*!< CLK_T::APBCLK: SC2_EN Mask */
+
+#define CLK_APBCLK_I2C0_EN_Pos (8) /*!< CLK_T::APBCLK: I2C0_EN Position */
+#define CLK_APBCLK_I2C0_EN_Msk (0x1ul << CLK_APBCLK_I2C0_EN_Pos) /*!< CLK_T::APBCLK: I2C0_EN Mask */
+
+#define CLK_APBCLK_I2C1_EN_Pos (9) /*!< CLK_T::APBCLK: I2C1_EN Position */
+#define CLK_APBCLK_I2C1_EN_Msk (0x1ul << CLK_APBCLK_I2C1_EN_Pos) /*!< CLK_T::APBCLK: I2C1_EN Mask */
+
+#define CLK_APBCLK_SPI0_EN_Pos (12) /*!< CLK_T::APBCLK: SPI0_EN Position */
+#define CLK_APBCLK_SPI0_EN_Msk (0x1ul << CLK_APBCLK_SPI0_EN_Pos) /*!< CLK_T::APBCLK: SPI0_EN Mask */
+
+#define CLK_APBCLK_SPI1_EN_Pos (13) /*!< CLK_T::APBCLK: SPI1_EN Position */
+#define CLK_APBCLK_SPI1_EN_Msk (0x1ul << CLK_APBCLK_SPI1_EN_Pos) /*!< CLK_T::APBCLK: SPI1_EN Mask */
+
+#define CLK_APBCLK_SPI2_EN_Pos (14) /*!< CLK_T::APBCLK: SPI2_EN Position */
+#define CLK_APBCLK_SPI2_EN_Msk (0x1ul << CLK_APBCLK_SPI2_EN_Pos) /*!< CLK_T::APBCLK: SPI2_EN Mask */
+
+#define CLK_APBCLK_UART0_EN_Pos (16) /*!< CLK_T::APBCLK: UART0_EN Position */
+#define CLK_APBCLK_UART0_EN_Msk (0x1ul << CLK_APBCLK_UART0_EN_Pos) /*!< CLK_T::APBCLK: UART0_EN Mask */
+
+#define CLK_APBCLK_UART1_EN_Pos (17) /*!< CLK_T::APBCLK: UART1_EN Position */
+#define CLK_APBCLK_UART1_EN_Msk (0x1ul << CLK_APBCLK_UART1_EN_Pos) /*!< CLK_T::APBCLK: UART1_EN Mask */
+
+#define CLK_APBCLK_PWM0_CH01_EN_Pos (20) /*!< CLK_T::APBCLK: PWM0_CH01_EN Position */
+#define CLK_APBCLK_PWM0_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH01_EN_Pos) /*!< CLK_T::APBCLK: PWM0_CH01_EN Mask */
+
+#define CLK_APBCLK_PWM0_CH23_EN_Pos (21) /*!< CLK_T::APBCLK: PWM0_CH23_EN Position */
+#define CLK_APBCLK_PWM0_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH23_EN_Pos) /*!< CLK_T::APBCLK: PWM0_CH23_EN Mask */
+
+#define CLK_APBCLK_PWM1_CH01_EN_Pos (22) /*!< CLK_T::APBCLK: PWM1_CH01_EN Position */
+#define CLK_APBCLK_PWM1_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH01_EN_Pos) /*!< CLK_T::APBCLK: PWM1_CH01_EN Mask */
+
+#define CLK_APBCLK_PWM1_CH23_EN_Pos (23) /*!< CLK_T::APBCLK: PWM1_CH23_EN Position */
+#define CLK_APBCLK_PWM1_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH23_EN_Pos) /*!< CLK_T::APBCLK: PWM1_CH23_EN Mask */
+
+#define CLK_APBCLK_DAC_EN_Pos (25) /*!< CLK_T::APBCLK: DAC_EN Position */
+#define CLK_APBCLK_DAC_EN_Msk (0x1ul << CLK_APBCLK_DAC_EN_Pos) /*!< CLK_T::APBCLK: DAC_EN Mask */
+
+#define CLK_APBCLK_LCD_EN_Pos (26) /*!< CLK_T::APBCLK: LCD_EN Position */
+#define CLK_APBCLK_LCD_EN_Msk (0x1ul << CLK_APBCLK_LCD_EN_Pos) /*!< CLK_T::APBCLK: LCD_EN Mask */
+
+#define CLK_APBCLK_USBD_EN_Pos (27) /*!< CLK_T::APBCLK: USBD_EN Position */
+#define CLK_APBCLK_USBD_EN_Msk (0x1ul << CLK_APBCLK_USBD_EN_Pos) /*!< CLK_T::APBCLK: USBD_EN Mask */
+
+#define CLK_APBCLK_ADC_EN_Pos (28) /*!< CLK_T::APBCLK: ADC_EN Position */
+#define CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos) /*!< CLK_T::APBCLK: ADC_EN Mask */
+
+#define CLK_APBCLK_I2S_EN_Pos (29) /*!< CLK_T::APBCLK: I2S_EN Position */
+#define CLK_APBCLK_I2S_EN_Msk (0x1ul << CLK_APBCLK_I2S_EN_Pos) /*!< CLK_T::APBCLK: I2S_EN Mask */
+
+#define CLK_APBCLK_SC0_EN_Pos (30) /*!< CLK_T::APBCLK: SC0_EN Position */
+#define CLK_APBCLK_SC0_EN_Msk (0x1ul << CLK_APBCLK_SC0_EN_Pos) /*!< CLK_T::APBCLK: SC0_EN Mask */
+
+#define CLK_APBCLK_SC1_EN_Pos (31) /*!< CLK_T::APBCLK: SC1_EN Position */
+#define CLK_APBCLK_SC1_EN_Msk (0x1ul << CLK_APBCLK_SC1_EN_Pos) /*!< CLK_T::APBCLK: SC1_EN Mask */
+
+#define CLK_CLKSTATUS_HXT_STB_Pos (0) /*!< CLK_T::CLKSTATUS: HXT_STB Position */
+#define CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos) /*!< CLK_T::CLKSTATUS: HXT_STB Mask */
+
+#define CLK_CLKSTATUS_LXT_STB_Pos (1) /*!< CLK_T::CLKSTATUS: LXT_STB Position */
+#define CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos) /*!< CLK_T::CLKSTATUS: LXT_STB Mask */
+
+#define CLK_CLKSTATUS_PLL_STB_Pos (2) /*!< CLK_T::CLKSTATUS: PLL_STB Position */
+#define CLK_CLKSTATUS_PLL_STB_Msk (0x1ul << CLK_CLKSTATUS_PLL_STB_Pos) /*!< CLK_T::CLKSTATUS: PLL_STB Mask */
+
+#define CLK_CLKSTATUS_LIRC_STB_Pos (3) /*!< CLK_T::CLKSTATUS: LIRC_STB Position */
+#define CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos) /*!< CLK_T::CLKSTATUS: LIRC_STB Mask */
+
+#define CLK_CLKSTATUS_HIRC_STB_Pos (4) /*!< CLK_T::CLKSTATUS: HIRC_STB Position */
+#define CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos) /*!< CLK_T::CLKSTATUS: HIRC_STB Mask */
+
+#define CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7) /*!< CLK_T::CLKSTATUS: CLK_SW_FAIL Position */
+#define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) /*!< CLK_T::CLKSTATUS: CLK_SW_FAIL Mask */
+
+#define CLK_CLKSEL0_HCLK_S_Pos (0) /*!< CLK_T::CLKSEL0: HCLK_S Position */
+#define CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos) /*!< CLK_T::CLKSEL0: HCLK_S Mask */
+
+#define CLK_CLKSEL1_UART_S_Pos (0) /*!< CLK_T::CLKSEL1: UART_S Position */
+#define CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos) /*!< CLK_T::CLKSEL1: UART_S Mask */
+
+#define CLK_CLKSEL1_ADC_S_Pos (2) /*!< CLK_T::CLKSEL1: ADC_S Position */
+#define CLK_CLKSEL1_ADC_S_Msk (0x3ul << CLK_CLKSEL1_ADC_S_Pos) /*!< CLK_T::CLKSEL1: ADC_S Mask */
+
+#define CLK_CLKSEL1_PWM0_CH01_S_Pos (4) /*!< CLK_T::CLKSEL1: PWM0_CH01_S Position */
+#define CLK_CLKSEL1_PWM0_CH01_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!< CLK_T::CLKSEL1: PWM0_CH01_S Mask */
+
+#define CLK_CLKSEL1_PWM0_CH23_S_Pos (6) /*!< CLK_T::CLKSEL1: PWM0_CH23_S Position */
+#define CLK_CLKSEL1_PWM0_CH23_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!< CLK_T::CLKSEL1: PWM0_CH23_S Mask */
+
+#define CLK_CLKSEL1_TMR0_S_Pos (8) /*!< CLK_T::CLKSEL1: TMR0_S Position */
+#define CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos) /*!< CLK_T::CLKSEL1: TMR0_S Mask */
+
+#define CLK_CLKSEL1_TMR1_S_Pos (12) /*!< CLK_T::CLKSEL1: TMR1_S Position */
+#define CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos) /*!< CLK_T::CLKSEL1: TMR1_S Mask */
+
+#define CLK_CLKSEL1_LCD_S_Pos (18) /*!< CLK_T::CLKSEL1: LCD_S Position */
+#define CLK_CLKSEL1_LCD_S_Msk (0x1ul << CLK_CLKSEL1_LCD_S_Pos) /*!< CLK_T::CLKSEL1: LCD_S Mask */
+
+#define CLK_CLKSEL2_FRQDIV_S_Pos (2) /*!< CLK_T::CLKSEL2: FRQDIV_S Position */
+#define CLK_CLKSEL2_FRQDIV_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV_S_Pos) /*!< CLK_T::CLKSEL2: FRQDIV_S Mask */
+
+#define CLK_CLKSEL2_PWM1_CH01_S_Pos (4) /*!< CLK_T::CLKSEL2: PWM1_CH01_S Position */
+#define CLK_CLKSEL2_PWM1_CH01_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!< CLK_T::CLKSEL2: PWM1_CH01_S Mask */
+
+#define CLK_CLKSEL2_PWM1_CH23_S_Pos (6) /*!< CLK_T::CLKSEL2: PWM1_CH23_S Position */
+#define CLK_CLKSEL2_PWM1_CH23_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!< CLK_T::CLKSEL2: PWM1_CH23_S Mask */
+
+#define CLK_CLKSEL2_TMR2_S_Pos (8) /*!< CLK_T::CLKSEL2: TMR2_S Position */
+#define CLK_CLKSEL2_TMR2_S_Msk (0x7ul << CLK_CLKSEL2_TMR2_S_Pos) /*!< CLK_T::CLKSEL2: TMR2_S Mask */
+
+#define CLK_CLKSEL2_TMR3_S_Pos (12) /*!< CLK_T::CLKSEL2: TMR3_S Position */
+#define CLK_CLKSEL2_TMR3_S_Msk (0x7ul << CLK_CLKSEL2_TMR3_S_Pos) /*!< CLK_T::CLKSEL2: TMR3_S Mask */
+
+#define CLK_CLKSEL2_I2S_S_Pos (16) /*!< CLK_T::CLKSEL2: I2S_S Position */
+#define CLK_CLKSEL2_I2S_S_Msk (0x3ul << CLK_CLKSEL2_I2S_S_Pos) /*!< CLK_T::CLKSEL2: I2S_S Mask */
+
+#define CLK_CLKSEL2_SC_S_Pos (18) /*!< CLK_T::CLKSEL2: SC_S Position */
+#define CLK_CLKSEL2_SC_S_Msk (0x3ul << CLK_CLKSEL2_SC_S_Pos) /*!< CLK_T::CLKSEL2: SC_S Mask */
+
+#define CLK_CLKSEL2_SPI0_S_Pos (20) /*!< CLK_T::CLKSEL2: SPI0_S Position */
+#define CLK_CLKSEL2_SPI0_S_Msk (0x1ul << CLK_CLKSEL2_SPI0_S_Pos) /*!< CLK_T::CLKSEL2: SPI0_S Mask */
+
+#define CLK_CLKSEL2_SPI1_S_Pos (21) /*!< CLK_T::CLKSEL2: SPI1_S Position */
+#define CLK_CLKSEL2_SPI1_S_Msk (0x1ul << CLK_CLKSEL2_SPI1_S_Pos) /*!< CLK_T::CLKSEL2: SPI1_S Mask */
+
+#define CLK_CLKSEL2_SPI2_S_Pos (22) /*!< CLK_T::CLKSEL2: SPI2_S Position */
+#define CLK_CLKSEL2_SPI2_S_Msk (0x1ul << CLK_CLKSEL2_SPI2_S_Pos) /*!< CLK_T::CLKSEL2: SPI2_S Mask */
+
+#define CLK_CLKDIV0_HCLK_N_Pos (0) /*!< CLK_T::CLKDIV0: HCLK_N Position */
+#define CLK_CLKDIV0_HCLK_N_Msk (0xful << CLK_CLKDIV0_HCLK_N_Pos) /*!< CLK_T::CLKDIV0: HCLK_N Mask */
+
+#define CLK_CLKDIV0_USB_N_Pos (4) /*!< CLK_T::CLKDIV0: USB_N Position */
+#define CLK_CLKDIV0_USB_N_Msk (0xful << CLK_CLKDIV0_USB_N_Pos) /*!< CLK_T::CLKDIV0: USB_N Mask */
+
+#define CLK_CLKDIV0_UART_N_Pos (8) /*!< CLK_T::CLKDIV0: UART_N Position */
+#define CLK_CLKDIV0_UART_N_Msk (0xful << CLK_CLKDIV0_UART_N_Pos) /*!< CLK_T::CLKDIV0: UART_N Mask */
+
+#define CLK_CLKDIV0_I2S_N_Pos (12) /*!< CLK_T::CLKDIV0: I2S_N Position */
+#define CLK_CLKDIV0_I2S_N_Msk (0xful << CLK_CLKDIV0_I2S_N_Pos) /*!< CLK_T::CLKDIV0: I2S_N Mask */
+
+#define CLK_CLKDIV0_ADC_N_Pos (16) /*!< CLK_T::CLKDIV0: ADC_N Position */
+#define CLK_CLKDIV0_ADC_N_Msk (0xfful << CLK_CLKDIV0_ADC_N_Pos) /*!< CLK_T::CLKDIV0: ADC_N Mask */
+
+#define CLK_CLKDIV0_SC0_N_Pos (28) /*!< CLK_T::CLKDIV0: SC0_N Position */
+#define CLK_CLKDIV0_SC0_N_Msk (0xful << CLK_CLKDIV0_SC0_N_Pos) /*!< CLK_T::CLKDIV0: SC0_N Mask */
+
+#define CLK_CLKDIV1_SC1_N_Pos (0) /*!< CLK_T::CLKDIV1: SC1_N Position */
+#define CLK_CLKDIV1_SC1_N_Msk (0xful << CLK_CLKDIV1_SC1_N_Pos) /*!< CLK_T::CLKDIV1: SC1_N Mask */
+
+#define CLK_CLKDIV1_SC2_N_Pos (4) /*!< CLK_T::CLKDIV1: SC2_N Position */
+#define CLK_CLKDIV1_SC2_N_Msk (0xful << CLK_CLKDIV1_SC2_N_Pos) /*!< CLK_T::CLKDIV1: SC2_N Mask */
+
+#define CLK_PLLCTL_FB_DV_Pos (0) /*!< CLK_T::PLLCTL: FB_DV Position */
+#define CLK_PLLCTL_FB_DV_Msk (0x3ful << CLK_PLLCTL_FB_DV_Pos) /*!< CLK_T::PLLCTL: FB_DV Mask */
+
+#define CLK_PLLCTL_IN_DV_Pos (8) /*!< CLK_T::PLLCTL: IN_DV Position */
+#define CLK_PLLCTL_IN_DV_Msk (0x3ul << CLK_PLLCTL_IN_DV_Pos) /*!< CLK_T::PLLCTL: IN_DV Mask */
+
+#define CLK_PLLCTL_OUT_DV_Pos (12) /*!< CLK_T::PLLCTL: OUT_DV Position */
+#define CLK_PLLCTL_OUT_DV_Msk (0x1ul << CLK_PLLCTL_OUT_DV_Pos) /*!< CLK_T::PLLCTL: OUT_DV Mask */
+
+#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
+#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
+
+#define CLK_PLLCTL_PLL_SRC_Pos (17) /*!< CLK_T::PLLCTL: PLL_SRC Position */
+#define CLK_PLLCTL_PLL_SRC_Msk (0x1ul << CLK_PLLCTL_PLL_SRC_Pos) /*!< CLK_T::PLLCTL: PLL_SRC Mask */
+
+#define CLK_FRQDIV_FSEL_Pos (0) /*!< CLK_T::FRQDIV: FSEL Position */
+#define CLK_FRQDIV_FSEL_Msk (0xful << CLK_FRQDIV_FSEL_Pos) /*!< CLK_T::FRQDIV: FSEL Mask */
+
+#define CLK_FRQDIV_FDIV_EN_Pos (4) /*!< CLK_T::FRQDIV: FDIV_EN Position */
+#define CLK_FRQDIV_FDIV_EN_Msk (0x1ul << CLK_FRQDIV_FDIV_EN_Pos) /*!< CLK_T::FRQDIV: FDIV_EN Mask */
+
+#define CLK_MCLKO_MCLK_SEL_Pos (0) /*!< CLK_T::MCLKO: MCLK_SEL Position */
+#define CLK_MCLKO_MCLK_SEL_Msk (0x3ful << CLK_MCLKO_MCLK_SEL_Pos) /*!< CLK_T::MCLKO: MCLK_SEL Mask */
+
+#define CLK_MCLKO_MCLK_EN_Pos (7) /*!< CLK_T::MCLKO: MCLK_EN Position */
+#define CLK_MCLKO_MCLK_EN_Msk (0x1ul << CLK_MCLKO_MCLK_EN_Pos) /*!< CLK_T::MCLKO: MCLK_EN Mask */
+
+#define CLK_WK_INTSTS_PD_WK_IS_Pos (0) /*!< CLK_T::WK_INTSTS: PD_WK_IS Position */
+#define CLK_WK_INTSTS_PD_WK_IS_Msk (0x1ul << CLK_WK_INTSTS_PD_WK_IS_Pos) /*!< CLK_T::WK_INTSTS: PD_WK_IS Mask */
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+
+
+/*---------------------- Digital to Analog Converter -------------------------*/
+/**
+ @addtogroup DAC Digital to Analog Converter(DAC)
+ Memory Mapped Structure for DAC Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * CTL0
+ * ===================================================================================================
+ * Offset: 0x00 DAC0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DACEN |DAC Enable
+ * | | |0 = Power down DAC.
+ * | | |1 = Power on DAC.
+ * | | |Note: When DAC is powered on, DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle
+ * |[1] |DACIE |DAC Interrupt Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[6:4] |DACLSEL |DAC Load Selection
+ * | | |Select the load trigger for the DAC latch.
+ * | | |000 = DAC latch loads when DACx_DAT written
+ * | | |001 = PDMA ACK
+ * | | |010 = Rising edge of TMR0
+ * | | |011 = Rising edge of TMR1
+ * | | |100 = Rising edge of TMR2
+ * | | |101 = Rising edge of TMR3
+ * | | |Others = Reserved
+ * |[21:8] |DACPWONSTBCNT|DACPWONSTBCNT
+ * | | |DAC need 6 us to be stable after DAC is power on from power down state.
+ * | | |This field controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement.
+ */
+ __IO uint32_t CTL0;
+
+ /**
+ * DATA0
+ * ===================================================================================================
+ * Offset: 0x04 DAC0 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DACData |DAC data
+ */
+ __IO uint32_t DATA0;
+
+ /**
+ * STS0
+ * ===================================================================================================
+ * Offset: 0x08 DAC0 Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DACIFG |DAC Interrupt Flag
+ * | | |0 = No interrupt pending.
+ * | | |1 = Interrupt pending.
+ * | | |Note: This bit is read only.
+ * |[1] |DACSTFG |DAC Start Flag
+ * | | |0 = DAC is not start yet.
+ * | | |1 = DAC has been started.
+ * | | |Note: this bit is read only.
+ * |[2] |BUSY |BUSY Bit
+ * | | |0 = DAC is not busy.
+ * | | |1 = DAC is busy.
+ */
+ __IO uint32_t STS0;
+ uint32_t RESERVE0[1];
+
+
+ /**
+ * CTL1
+ * ===================================================================================================
+ * Offset: 0x10 DAC1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DACEN |DAC Enable
+ * | | |0 = Power down DAC.
+ * | | |1 = Power on DAC.
+ * | | |Note: When DAC is powered on, DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle
+ * |[1] |DACIE |DAC Interrupt Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[6:4] |DACLSEL |DAC Load Selection
+ * | | |Select the load trigger for the DAC latch.
+ * | | |000 = DAC latch loads when DACx_DAT written
+ * | | |001 = PDMA ACK
+ * | | |010 = Rising edge of TMR0
+ * | | |011 = Rising edge of TMR1
+ * | | |100 = Rising edge of TMR2
+ * | | |101 = Rising edge of TMR3
+ * | | |Others = Reserved
+ * |[21:8] |DACPWONSTBCNT|DACPWONSTBCNT
+ * | | |DAC need 6 us to be stable after DAC is power on from power down state.
+ * | | |This field controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement.
+ */
+ __IO uint32_t CTL1;
+
+ /**
+ * DATA1
+ * ===================================================================================================
+ * Offset: 0x14 DAC1 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DACData |DAC data
+ */
+ __IO uint32_t DATA1;
+
+ /**
+ * STS1
+ * ===================================================================================================
+ * Offset: 0x18 DAC1 Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DACIFG |DAC Interrupt Flag
+ * | | |0 = No interrupt pending.
+ * | | |1 = Interrupt pending.
+ * | | |Note: This bit is read only.
+ * |[1] |DACSTFG |DAC Start Flag
+ * | | |0 = DAC is not start yet.
+ * | | |1 = DAC has been started.
+ * | | |Note: this bit is read only.
+ * |[2] |BUSY |BUSY Bit
+ * | | |0 = DAC is not busy.
+ * | | |1 = DAC is busy.
+ */
+ __IO uint32_t STS1;
+ uint32_t RESERVE1[1];
+
+
+ /**
+ * COMCTL
+ * ===================================================================================================
+ * Offset: 0x20 DAC01 Common Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |WAITDACCONV|Wait DAC Conversion Complete
+ * | | |The DAC needs at least 2 us to settle down every time when each data deliver to DAC, which means user cannot update each DACx_data register faster than 2 us; otherwise data will lost.
+ * | | |Setting this register can adjust the time interval in PCLK unit between each DACx_data into DAC in order to meet the 2 us requirement.
+ * |[8] |DAC01GRP |Group DAC0 And DAC1
+ * | | |0 = Not grouped.
+ * | | |1 = Grouped.
+ * |[10:9] |REFSEL |Reference Voltage Selection
+ * | | |00 = AVDD
+ * | | |01 = Internal reference voltage
+ * | | |10 = External reference voltage
+ * | | |11= Reserved
+ */
+ __IO uint32_t COMCTL;
+
+} DAC_T;
+
+/**
+ @addtogroup DAC_CONST DAC Bit Field Definition
+ Constant Definitions for DAC Controller
+@{ */
+
+#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
+#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
+
+#define DAC_CTL_DACIE_Pos (1) /*!< DAC_T::CTL: DACIE Position */
+#define DAC_CTL_DACIE_Msk (0x1ul << DAC_CTL_DACIE_Pos) /*!< DAC_T::CTL: DACIE Mask */
+
+#define DAC_CTL_DACLSEL_Pos (4) /*!< DAC_T::CTL: DACLSEL Position */
+#define DAC_CTL_DACLSEL_Msk (0x7ul << DAC_CTL_DACLSEL_Pos) /*!< DAC_T::CTL: DACLSEL Mask */
+
+#define DAC_CTL_DACPWONSTBCNT_Pos (8) /*!< DAC_T::CTL: DACPWONSTBCNT Position */
+#define DAC_CTL_DACPWONSTBCNT_Msk (0x3ffful << DAC_CTL_DACPWONSTBCNT_Pos) /*!< DAC_T::CTL: DACPWONSTBCNT Mask */
+
+#define DAC_DATA_DACData_Pos (0) /*!< DAC_T::DATA: DACData Position */
+#define DAC_DATA_DACData_Msk (0xffful << DAC_DATA_DACData_Pos) /*!< DAC_T::DATA: DACData Mask */
+
+#define DAC_STS_DACIFG_Pos (0) /*!< DAC_T::STS: DACIFG Position */
+#define DAC_STS_DACIFG_Msk (0x1ul << DAC_STS_DACIFG_Pos) /*!< DAC_T::STS: DACIFG Mask */
+
+#define DAC_STS_DACSTFG_Pos (1) /*!< DAC_T::STS: DACSTFG Position */
+#define DAC_STS_DACSTFG_Msk (0x1ul << DAC_STS_DACSTFG_Pos) /*!< DAC_T::STS: DACSTFG Mask */
+
+#define DAC_STS_BUSY_Pos (2) /*!< DAC_T::STS: BUSY Position */
+#define DAC_STS_BUSY_Msk (0x1ul << DAC_STS_BUSY_Pos) /*!< DAC_T::STS: BUSY Mask */
+
+#define DAC_COMCTL_WAITDACCONV_Pos (0) /*!< DAC_T::COMCTL: WAITDACCONV Position */
+#define DAC_COMCTL_WAITDACCONV_Msk (0xfful << DAC_COMCTL_WAITDACCONV_Pos) /*!< DAC_T::COMCTL: WAITDACCONV Mask */
+
+#define DAC_COMCTL_DAC01GRP_Pos (8) /*!< DAC_T::COMCTL: DAC01GRP Position */
+#define DAC_COMCTL_DAC01GRP_Msk (0x1ul << DAC_COMCTL_DAC01GRP_Pos) /*!< DAC_T::COMCTL: DAC01GRP Mask */
+
+#define DAC_COMCTL_REFSEL_Pos (9) /*!< DAC_T::COMCTL: REFSEL Position */
+#define DAC_COMCTL_REFSEL_Msk (0x3ul << DAC_COMCTL_REFSEL_Pos) /*!< DAC_T::COMCTL: REFSEL Mask */
+
+/**@}*/ /* DAC_CONST */
+/**@}*/ /* end of DAC register group */
+
+
+/*---------------------- External Bus Interface Controller -------------------------*/
+/**
+ @addtogroup EBI External Bus Interface Controller(EBI)
+ Memory Mapped Structure for EBI Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * EBICON
+ * ===================================================================================================
+ * Offset: 0x00 External Bus Interface General Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ExtEN |EBI Enable
+ * | | |This bit is the functional enable bit for EBI.
+ * | | |0 = EBI function is disabled.
+ * | | |1 = EBI function is enabled.
+ * |[1] |ExtBW16 |EBI Data Width 16-Bit
+ * | | |This bit defines if the data bus is 8-bit or 16-bit.
+ * | | |0 = EBI data width is 8-bit.
+ * | | |1 = EBI data width is 16-bit.
+ * |[10:8] |MCLKDIV |External Output Clock Divider
+ * | | |The frequency of EBI output clock is controlled by MCLKDIV as shown in the following table.
+ * | | |000 = HCLK/1.
+ * | | |001 = HCLK/2.
+ * | | |010 = HCLK/4.
+ * | | |011 = HCLK/8.
+ * | | |100 = HCLK/16.
+ * | | |101 = HCLK/32.
+ * | | |110 = Default.
+ * | | |111 = Default.
+ * | | |Notice: Default value of output clock is HCLK/1
+ * |[11] |MCLKEN |External Clock Enable
+ * | | |This bit control if EBI generates the clock to external device.
+ * | | |If external device is a synchronous device, it's necessary to set this bit high to enable EBI generating clock to external device.
+ * | | |If the external device is an asynchronous device, keep this bit low is recommended to save power consumption.
+ * | | |0 = EBI Disabled to generate clock to external device.
+ * | | |1 = EBI Enabled to generate clock to external device.
+ * |[18:16] |ExttALE |Expand Time Of ALE
+ * | | |The ALE width (tALE) to latch the address can be controlled by ExttALE.
+ * | | |tALE = (ExttALE+1)*MCLK.
+ */
+ __IO uint32_t EBICON;
+
+ /**
+ * EXTIME
+ * ===================================================================================================
+ * Offset: 0x04 External Bus Interface Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |ExttACC |EBI Data Access Time
+ * | | |ExttACC define data access time (tACC).
+ * | | |tACC = (ExttACC +1) * MCLK.
+ * |[10:8] |ExttAHD |EBI Data Access Hold Time
+ * | | |ExttAHD define data access hold time (tAHD).
+ * | | |tAHD = (ExttAHD +1) * MCLK.
+ * |[15:12] |ExtIW2X |Idle State Cycle After Write
+ * | | |When write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.
+ * | | |Idle state cycle = (ExtIW2X*MCLK).
+ * |[19:16] |ExtIR2W |Idle State Cycle Between Read-Write
+ * | | |When read action is finish and next action is going to write, idle state is inserted and nCS return to high if ExtIR2W is not zero.
+ * | | |Idle state cycle = (ExtIR2W*MCLK).
+ * |[27:24] |ExtIR2R |Idle State Cycle Between Read-Read
+ * | | |When read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.
+ * | | |Idle state cycle = (ExtIR2R*MCLK).
+ */
+ __IO uint32_t EXTIME;
+
+} EBI_T;
+
+/**
+ @addtogroup EBI_CONST EBI Bit Field Definition
+ Constant Definitions for EBI Controller
+@{ */
+
+#define EBI_EBICON_ExtEN_Pos (0) /*!< EBI_T::EBICON: ExtEN Position */
+#define EBI_EBICON_ExtEN_Msk (0x1ul << EBI_EBICON_ExtEN_Pos) /*!< EBI_T::EBICON: ExtEN Mask */
+
+#define EBI_EBICON_ExtBW16_Pos (1) /*!< EBI_T::EBICON: ExtBW16 Position */
+#define EBI_EBICON_ExtBW16_Msk (0x1ul << EBI_EBICON_ExtBW16_Pos) /*!< EBI_T::EBICON: ExtBW16 Mask */
+
+#define EBI_EBICON_MCLKDIV_Pos (8) /*!< EBI_T::EBICON: MCLKDIV Position */
+#define EBI_EBICON_MCLKDIV_Msk (0x7ul << EBI_EBICON_MCLKDIV_Pos) /*!< EBI_T::EBICON: MCLKDIV Mask */
+
+#define EBI_EBICON_MCLKEN_Pos (11) /*!< EBI_T::EBICON: MCLKEN Position */
+#define EBI_EBICON_MCLKEN_Msk (0x1ul << EBI_EBICON_MCLKEN_Pos) /*!< EBI_T::EBICON: MCLKEN Mask */
+
+#define EBI_EBICON_ExttALE_Pos (16) /*!< EBI_T::EBICON: ExttALE Position */
+#define EBI_EBICON_ExttALE_Msk (0x7ul << EBI_EBICON_ExttALE_Pos) /*!< EBI_T::EBICON: ExttALE Mask */
+
+#define EBI_EXTIME_ExttACC_Pos (0) /*!< EBI_T::EXTIME: ExttACC Position */
+#define EBI_EXTIME_ExttACC_Msk (0x1ful << EBI_EXTIME_ExttACC_Pos) /*!< EBI_T::EXTIME: ExttACC Mask */
+
+#define EBI_EXTIME_ExttAHD_Pos (8) /*!< EBI_T::EXTIME: ExttAHD Position */
+#define EBI_EXTIME_ExttAHD_Msk (0x7ul << EBI_EXTIME_ExttAHD_Pos) /*!< EBI_T::EXTIME: ExttAHD Mask */
+
+#define EBI_EXTIME_ExtIW2X_Pos (12) /*!< EBI_T::EXTIME: ExtIW2X Position */
+#define EBI_EXTIME_ExtIW2X_Msk (0xful << EBI_EXTIME_ExtIW2X_Pos) /*!< EBI_T::EXTIME: ExtIW2X Mask */
+
+#define EBI_EXTIME_ExtIR2W_Pos (16) /*!< EBI_T::EXTIME: ExtIR2W Position */
+#define EBI_EXTIME_ExtIR2W_Msk (0xful << EBI_EXTIME_ExtIR2W_Pos) /*!< EBI_T::EXTIME: ExtIR2W Mask */
+
+#define EBI_EXTIME_ExtIR2R_Pos (24) /*!< EBI_T::EXTIME: ExtIR2R Position */
+#define EBI_EXTIME_ExtIR2R_Msk (0xful << EBI_EXTIME_ExtIR2R_Pos) /*!< EBI_T::EXTIME: ExtIR2R Mask */
+
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* end of EBI register group */
+
+
+/*---------------------- Flash Memory Controller -------------------------*/
+/**
+ @addtogroup FMC Flash Memory Controller(FMC)
+ Memory Mapped Structure for FMC Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * ISPCON
+ * ===================================================================================================
+ * Offset: 0x00 ISP Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPEN |ISP Enable (Write-Protection Bit)
+ * | | |ISP function enable bit. Set this bit to enable ISP function.
+ * | | |0 = ISP function Disabled.
+ * | | |1 = ISP function Enabled.
+ * |[1] |BS |Boot Select (Write-Protection Bit)
+ * | | |Set/clear this bit to select next booting from LDROM/APROM, respectively.
+ * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
+ * | | |This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset.
+ * | | |0 = boot from APROM.
+ * | | |1 = boot from LDROM.
+ * |[3] |APUEN |APROM Update Enable (Write-Protection Bit)
+ * | | |APROM update enable bit.
+ * | | |0 = APROM can not be updated.
+ * | | |1 = APROM can be updated when the MCU runs in APROM.
+ * |[4] |CFGUEN |Enable Config-Bits Update By ISP (Write-Protection Bit)
+ * | | |0 = Disabling ISP can update config-bits.
+ * | | |1 = Enabling ISP can update config-bits.
+ * |[5] |LDUEN |LDROM Update Enable (Write-Protection Bit)
+ * | | |LDROM update enable bit.
+ * | | |0 = LDROM cannot be updated.
+ * | | |1 = LDROM can be updated when the chip runs in APROM.
+ * |[6] |ISPFF |ISP Fail Flag (Write-Protection Bit)
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself
+ * | | |(2) LDROM writes to itself
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0
+ * | | |(4) Destination address is illegal, such as over an available range
+ * | | |Write 1 to clear.
+ */
+ __IO uint32_t ISPCON;
+
+ /**
+ * ISPADR
+ * ===================================================================================================
+ * Offset: 0x04 ISP Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPADR |ISP Address
+ * | | |This chip supports word program only.
+ * | | |ISPADR[1:0] must be kept 00b for ISP operation, and ISPADR[8:0] must be kept 0_0000_0000b for Vector Page Re-map Command.
+ */
+ __IO uint32_t ISPADR;
+
+ /**
+ * ISPDAT
+ * ===================================================================================================
+ * Offset: 0x08 ISP Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT |ISP Data
+ * | | |Write data to this register before ISP program operation
+ * | | |Read data from this register after ISP read operation
+ */
+ __IO uint32_t ISPDAT;
+
+ /**
+ * ISPCMD
+ * ===================================================================================================
+ * Offset: 0x0C ISP Command Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |FCTRL |ISP Command
+ * | | |The ISP command table is shown as follows.
+ * |[4] |FCEN |ISP Command
+ * | | |The ISP command table is shown as follows.
+ * |[5] |FOEN |ISP Command
+ * | | |The ISP command table is shown as follows.
+ */
+ __IO uint32_t ISPCMD;
+
+ /**
+ * ISPTRG
+ * ===================================================================================================
+ * Offset: 0x10 ISP Trigger Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPGO |ISP Start Trigger
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP is progressing.
+ */
+ __IO uint32_t ISPTRG;
+
+ /**
+ * DFBADR
+ * ===================================================================================================
+ * Offset: 0x14 Data Flash Base Address
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DFBA |Data Flash Base Address
+ * | | |This register indicates data flash start address. It is a read only register.
+ * | | |The data flash start address is defined by user.
+ * | | |Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
+ */
+ __I uint32_t DFBADR;
+ uint32_t RESERVE0[10];
+
+
+ /**
+ * ISPSTA
+ * ===================================================================================================
+ * Offset: 0x40 ISP Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPBUSY |ISP BUSY
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP operation is busy.
+ * | | |Read Only
+ * |[2:1] |CBS |Config Boot Selection Status
+ * |[6] |ISPFF |ISP Fail Flag
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself.
+ * | | |(2) LDROM writes to itself.
+ * | | |(3) CONFIG is erased/programmed when the MCU is running in APROM.
+ * | | |(4) Destination address is illegal, such as over an available range.
+ * | | |Write 1 to clear.
+ */
+ __IO uint32_t ISPSTA;
+
+} FMC_T;
+
+/**
+ @addtogroup FMC_CONST FMC Bit Field Definition
+ Constant Definitions for FMC Controller
+@{ */
+
+#define FMC_ISPCON_ISPEN_Pos (0) /*!< FMC_T::ISPCON: ISPEN Position */
+#define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos) /*!< FMC_T::ISPCON: ISPEN Mask */
+
+#define FMC_ISPCON_BS_Pos (1) /*!< FMC_T::ISPCON: BS Position */
+#define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos) /*!< FMC_T::ISPCON: BS Mask */
+
+#define FMC_ISPCON_APUEN_Pos (3) /*!< FMC_T::ISPCON: APUEN Position */
+#define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos) /*!< FMC_T::ISPCON: APUEN Mask */
+
+#define FMC_ISPCON_CFGUEN_Pos (4) /*!< FMC_T::ISPCON: CFGUEN Position */
+#define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos) /*!< FMC_T::ISPCON: CFGUEN Mask */
+
+#define FMC_ISPCON_LDUEN_Pos (5) /*!< FMC_T::ISPCON: LDUEN Position */
+#define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos) /*!< FMC_T::ISPCON: LDUEN Mask */
+
+#define FMC_ISPCON_ISPFF_Pos (6) /*!< FMC_T::ISPCON: ISPFF Position */
+#define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos) /*!< FMC_T::ISPCON: ISPFF Mask */
+
+#define FMC_ISPADR_ISPADR_Pos (0) /*!< FMC_T::ISPADR: ISPADR Position */
+#define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos) /*!< FMC_T::ISPADR: ISPADR Mask */
+
+#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
+#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
+
+#define FMC_ISPCMD_FCTRL_Pos (0) /*!< FMC_T::ISPCMD: FCTRL Position */
+#define FMC_ISPCMD_FCTRL_Msk (0xful << FMC_ISPCMD_FCTRL_Pos) /*!< FMC_T::ISPCMD: FCTRL Mask */
+
+#define FMC_ISPCMD_FCEN_Pos (4) /*!< FMC_T::ISPCMD: FCEN Position */
+#define FMC_ISPCMD_FCEN_Msk (0x1ul << FMC_ISPCMD_FCEN_Pos) /*!< FMC_T::ISPCMD: FCEN Mask */
+
+#define FMC_ISPCMD_FOEN_Pos (5) /*!< FMC_T::ISPCMD: FOEN Position */
+#define FMC_ISPCMD_FOEN_Msk (0x1ul << FMC_ISPCMD_FOEN_Pos) /*!< FMC_T::ISPCMD: FOEN Mask */
+
+#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
+#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
+
+#define FMC_DFBADR_DFBA_Pos (0) /*!< FMC_T::DFBADR: DFBA Position */
+#define FMC_DFBADR_DFBA_Msk (0xfffffffful << FMC_DFBADR_DFBA_Pos) /*!< FMC_T::DFBADR: DFBA Mask */
+
+#define FMC_ISPSTA_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTA: ISPBUSY Position */
+#define FMC_ISPSTA_ISPBUSY_Msk (0x1ul << FMC_ISPSTA_ISPBUSY_Pos) /*!< FMC_T::ISPSTA: ISPBUSY Mask */
+
+#define FMC_ISPSTA_CBS_Pos (1) /*!< FMC_T::ISPSTA: CBS Position */
+#define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos) /*!< FMC_T::ISPSTA: CBS Mask */
+
+#define FMC_ISPSTA_ISPFF_Pos (6) /*!< FMC_T::ISPSTA: ISPFF Position */
+#define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos) /*!< FMC_T::ISPSTA: ISPFF Mask */
+
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* end of FMC register group */
+
+
+/*---------------------- System Global Control Registers -------------------------*/
+/**
+ @addtogroup System Global Control Registers(SYS)
+ Memory Mapped Structure for SYS Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * PDID
+ * ===================================================================================================
+ * Offset: 0x00 Part Device Identification number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDID |Part Device ID
+ * | | |This register reflects device part number code.
+ * | | |Software can read this register to identify which device is used.
+ */
+ __I uint32_t PDID;
+
+ /**
+ * RST_SRC
+ * ===================================================================================================
+ * Offset: 0x04 System Reset Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RSTS_POR |The RSTS_POR Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Module Or Bit CHIP_RST (IPRSTC1[0]) To Indicate The Previous Reset Source
+ * | | |0 = No reset from POR or CHIP_RST.
+ * | | |1 = Power-on Reset (POR) or CHIP_RST had issued the reset signal to reset the system.
+ * | | |This bit is cleared by writing 1 to itself.
+ * |[1] |RSTS_PAD |The RSTS_PAD Flag Is Set By The "Reset Signal" From The /RESET Pin To Indicate The Previous Reset Source
+ * | | |0 = No reset from /RESET pin.
+ * | | |1 = The /RESET pin had issued the reset signal to reset the system.
+ * | | |This bit is cleared by writing 1 to itself.
+ * |[2] |RSTS_WDT |The RSTS_WDT Flag Is Set By The "Reset Signal" From The Watchdog Timer Module To Indicate The Previous Reset Source
+ * | | |0 = No reset from Watchdog Timer.
+ * | | |1 = The Watchdog Timer module had issued the reset signal to reset the system.
+ * | | |This bit is cleared by writing 1 to itself.
+ * |[4] |RSTS_BOD |The RSTS_BOD Flag Is Set By The "Reset Signal" From The Brown-Out-Detected Module To Indicate The Previous Reset Source
+ * | | |0 = No reset from BOD.
+ * | | |1 = Brown-out-Detected module had issued the reset signal to reset the system.
+ * | | |This bit is cleared by writing 1 to itself.
+ * |[5] |RSTS_SYS |The RSTS_SYS Flag Is Set By The "Reset Signal" From The Cortex_M0 Kernel To Indicate The Previous Reset Source
+ * | | |0 = No reset from Cortex_M0.
+ * | | |1 = Cortex_M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel.
+ * | | |This bit is cleared by writing 1 to itself.
+ * |[7] |RSTS_CPU |The RSTS_CPU Flag Is Set By Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) "1" To Rest Cortex-M0 CPU Kernel And Flash Memory Controller (FMC)
+ * | | |0 = No reset from CPU.
+ * | | |1 = Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1.
+ * | | |This bit is cleared by writing 1 to itself.
+ */
+ __IO uint32_t RST_SRC;
+
+ /**
+ * IPRST_CTL1
+ * ===================================================================================================
+ * Offset: 0x08 IP Reset Control Resister1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHIP_RST |CHIP One Shot Reset
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Setting this bit will reset the whole chip, including CPU kernel and all peripherals like power-on reset and this bit will automatically return to "0" after the 2 clock cycles.
+ * | | |The chip setting from flash will be also reloaded when chip one shot reset.
+ * | | |0 = Normal.
+ * | | |1 = Reset CHIP.
+ * | | |Note: In the following conditions, chip setting from flash will be reloaded.
+ * | | |Power-on Reset
+ * | | |Brown-out-Detected Reset
+ * | | |Low level on the /RESET pin
+ * | | |Set IPRST_CTL1[CHIP_RST]
+ * |[1] |CPU_RST |CPU Kernel One Shot Reset
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to "0" after the 2 clock cycles
+ * | | |0 = Normal.
+ * | | |1 = Reset CPU.
+ * |[2] |DMA_RST |DMA Controller Reset
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Set this bit "1" will generate a reset signal to the DMA.
+ * | | |SW needs to set this bit to low to release reset signal.
+ * | | |0 = Normal operation.
+ * | | |1 = DMA IP reset.
+ * |[3] |EBI_RST |EBI Controller Reset
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Set this bit "1" will generate a reset signal to the EBI.
+ * | | |SW needs to set this bit to low to release reset signal.
+ * | | |0 = Normal operation.
+ * | | |1 = EBI IP reset.
+ */
+ __IO uint32_t IPRST_CTL1;
+
+ /**
+ * IPRST_CTL2
+ * ===================================================================================================
+ * Offset: 0x0C IP Reset Control Resister2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |GPIO_RST |GPIO Controller Reset
+ * | | |0 = GPIO normal operation.
+ * | | |1 = GPIO reset.
+ * |[2] |TMR0_RST |Timer0 Controller Reset
+ * | | |0 = Timer0 normal operation.
+ * | | |1 = Timer0 reset.
+ * |[3] |TMR1_RST |Timer1 Controller Reset
+ * | | |0 = Timer1 normal operation.
+ * | | |1 = Timer1 block reset.
+ * |[4] |TMR2_RST |Timer2 Controller Reset
+ * | | |0 = Timer2 normal operation.
+ * | | |1 = Timer2 block reset.
+ * |[5] |TMR3_RST |Timer3 Controller Reset
+ * | | |0 = Timer3 normal operation.
+ * | | |1 = Timer3 block reset.
+ * |[7] |SC2_RST |SmartCard 2 Controller Reset
+ * | | |0 = SmartCard 2 block normal operation.
+ * | | |1 = SmartCard 2 block reset.
+ * |[8] |I2C0_RST |I2C0 Controller Reset
+ * | | |0 = I2C0 normal operation.
+ * | | |1 = I2C0 block reset.
+ * |[9] |I2C1_RST |I2C1 Controller Reset
+ * | | |0 = I2C1 block normal operation.
+ * | | |1 = I2C1 block reset.
+ * |[12] |SPI0_RST |SPI0 Controller Reset
+ * | | |0 = SPI0 block normal operation.
+ * | | |1 = SPI0 block reset.
+ * |[13] |SPI1_RST |SPI1 Controller Reset
+ * | | |0 = SPI1 normal operation.
+ * | | |1 = SPI1 block reset.
+ * |[14] |SPI2_RST |SPI2 Controller Reset
+ * | | |0 = SPI2 normal operation.
+ * | | |1 = SPI2 block reset.
+ * |[16] |UART0_RST |UART0 Controller Reset
+ * | | |0 = UART0 normal operation.
+ * | | |1 = UART0 block reset.
+ * |[17] |UART1_RST |UART1 Controller Reset
+ * | | |0 = UART1 normal operation.
+ * | | |1 = UART1 block reset.
+ * |[20] |PWM0_RST |PWM0 Controller Reset
+ * | | |0 = PWM0 block normal operation.
+ * | | |1 = PWM0 block reset.
+ * |[21] |PWM1_RST |PWM1 Controller Reset
+ * | | |0 = PWM1 block normal operation.
+ * | | |1 = PWM1 block reset.
+ * |[25] |DAC_RST |DAC Controller Reset
+ * | | |0 = DAC block normal operation.
+ * | | |1 = DAC block reset.
+ * |[26] |LCD_RST |LCD Controller Reset
+ * | | |0 = LCD block normal operation.
+ * | | |1 = LCD block reset.
+ * |[27] |USBD_RST |USB Device Controller Reset
+ * | | |0 = USB block normal operation.
+ * | | |1 = USB block reset.
+ * |[28] |ADC_RST |ADC Controller Reset
+ * | | |0 = ADC block normal operation.
+ * | | |1 = ADC block reset.
+ * |[29] |I2S_RST |I2S Controller Reset
+ * | | |0 = I2S block normal operation.
+ * | | |1 = I2S block reset.
+ * |[30] |SC0_RST |SmartCard 0 Controller Reset
+ * | | |0 = SmartCard block normal operation.
+ * | | |1 = SmartCard block reset.
+ * |[31] |SC1_RST |SmartCard1 Controller Reset
+ * | | |0 = SmartCard block normal operation.
+ * | | |1 = SmartCard block reset.
+ */
+ __IO uint32_t IPRST_CTL2;
+ uint32_t RESERVE0[4];
+
+
+ /**
+ * TEMPCTL
+ * ===================================================================================================
+ * Offset: 0x20 Temperature Sensor Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VTEMP_EN |Temperature Sensor Enable
+ * | | |0 = Temperature sensor function Disabled (default).
+ * | | |1 = Temperature sensor function Enabled.
+ */
+ __IO uint32_t TEMPCTL;
+ uint32_t RESERVE1[3];
+
+
+ /**
+ * PA_L_MFP
+ * ===================================================================================================
+ * Offset: 0x30 Port A low byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PA0_MFP |PA.0 Pin Function Selection
+ * | | |001 = ADC input channel 0
+ * | | |100 = SmartCard 2 card detect
+ * | | |Others = GPIOA[0]
+ * |[6:4] |PA1_MFP |PA.1 Pin Function Selection
+ * | | |001 = ADC input channel 1
+ * | | |010 = EBI AD[12]
+ * | | |Others = GPIOA[1]
+ * |[10:8] |PA2_MFP |PA.2 Pin Function Selection
+ * | | |001 = ADC input channel 2
+ * | | |010 = EBI AD[11]
+ * | | |101 = UART1_RXD
+ * | | |Others = GPIOA[2]
+ * |[14:12] |PA3_MFP |PA.3 Pin Function Selection
+ * | | |001 = ADC input channel 3
+ * | | |010 = EBI AD[10]
+ * | | |101 = UART1_TXD
+ * | | |Others = GPIOA[3]
+ * |[18:16] |PA4_MFP |PA.4 Pin Function Selection
+ * | | |001 = ADC input channel 4
+ * | | |010 = EBI AD[9]
+ * | | |100 = SmartCard 2 power
+ * | | |101 = I2C0 SDA
+ * | | |111 = LCD SEG 39
+ * | | |Others = GPIOA[4]
+ * |[22:20] |PA5_MFP |PA.5 Pin Function Selection
+ * | | |001 = ADC input channel 5
+ * | | |010 = EBI AD[8]
+ * | | |100 = SmartCard2 RST
+ * | | |101 = I2C0 SCL
+ * | | |111 = LCD SEG 38
+ * | | |Others = GPIOA[5]
+ * |[26:24] |PA6_MFP |PA.6 Pin Function Selection
+ * | | |001 = ADC input channel 6
+ * | | |010 = EBI AD[7]
+ * | | |011 = Timer 3 Capture event
+ * | | |100 = SmartCard 2 clock
+ * | | |101 = PWM0 Channel 3
+ * | | |111 = LCD SEG 37
+ * | | |Others = GPIOA[6]
+ * |[30:28] |PA7_MFP |PA.7 Pin Function Selection
+ * | | |001 = ADC input channel 7
+ * | | |010 = EBI AD[6]
+ * | | |011 = Timer 2 capture event
+ * | | |100 = SmartCard 2 data pin
+ * | | |101 = PWM0 Channel 2
+ * | | |111 = LCD SEG 36
+ * | | |Others = GPIOA[7]
+ */
+ __IO uint32_t PA_L_MFP;
+
+ /**
+ * PA_H_MFP
+ * ===================================================================================================
+ * Offset: 0x34 Port A high byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PA8_MFP |PA.8 Pin Function Selection
+ * | | |001 = I2C0 SDA
+ * | | |011 = SmartCard0 clock
+ * | | |100 = SPI2 1st slave select pin
+ * | | |111 = LCD SEG 20
+ * | | |Others = GPIOA[8]
+ * |[6:4] |PA9_MFP |PA.9 Pin Function Selection
+ * | | |001 = I2C0 SCL
+ * | | |011 = SmartCard0 DATA
+ * | | |100 = SPI2 SCLK
+ * | | |111 = LCD SEG 21
+ * | | |Others = GPIOA[9]
+ * |[10:8] |PA10_MFP |PA.10 Pin Function Selection
+ * | | |001 = I2C1 SDA
+ * | | |010 = EBI nWR
+ * | | |011 = SmartCard0 Power
+ * | | |100 = SPI2 MISO0
+ * | | |111 = LCD SEG 22
+ * | | |Others = GPIOA[10]
+ * |[14:12] |PA11_MFP |PA.11 Pin Function Selection
+ * | | |001 = I2C1 SCL
+ * | | |010 = EBI nRE
+ * | | |011 = SmartCard0 RST
+ * | | |100 = SPI2 MOSI0
+ * | | |111 = LCD SEG 23
+ * | | |Others = GPIOA[11]
+ * |[18:16] |PA12_MFP |PA.12 Pin Function Selection
+ * | | |001 = PWM0 Channel 0
+ * | | |010 = EBI AD[13]
+ * | | |011 = Timer0 capture event
+ * | | |101 = I2C0 SDA
+ * | | |Others = GPIOA[12]
+ * |[22:20] |PA13_MFP |PA.13 Pin Function Selection
+ * | | |001 = PWM0 Channel 1
+ * | | |010 = EBI AD[14]
+ * | | |011 = Timer1 capture event
+ * | | |101 = I2C0 SCL
+ * | | |Others = GPIOA[13]
+ * |[26:24] |PA14_MFP |PA.14 Pin Function Selection
+ * | | |001 = PWM0 Channel 2
+ * | | |010 = EBI AD[15]
+ * | | |011 = Timer2 capture event
+ * | | |110 = UART0 RX
+ * | | |Others = GPIOA[14]
+ * |[30:28] |PA15_MFP |PA.15 Pin Function Selection
+ * | | |001 = PWM0 Channel 3
+ * | | |010 = I2S MCLK
+ * | | |011 = Timer3 capture event
+ * | | |100 = SmartCard 0 power
+ * | | |110 = UART0 TX
+ * | | |Others = GPIOA[15]
+ */
+ __IO uint32_t PA_H_MFP;
+
+ /**
+ * PB_L_MFP
+ * ===================================================================================================
+ * Offset: 0x38 Port B low byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PB0_MFP |PB.0 Pin Function Selection
+ * | | |001 = UART0 RX
+ * | | |011 = SPI1 MOSI0
+ * | | |111 = LCD SEG 7
+ * | | |Others = GPIOB[0]
+ * |[6:4] |PB1_MFP |PB.1 Pin Function Selection
+ * | | |001 = UART0 TX
+ * | | |011 = SPI1 MISO0
+ * | | |111 = LCD SEG 6
+ * | | |Others = GPIOB[1]
+ * |[10:8] |PB2_MFP |PB.2 Pin Function Selection
+ * | | |001 = UART0 RTSn
+ * | | |010 = EBI nWRL
+ * | | |011 = SPI1 SCLK
+ * | | |111 = LCD SEG 5
+ * | | |Others = GPIOB[2]
+ * |[14:12] |PB3_MFP |PB.3 Pin Function Selection
+ * | | |001 = UART0 CTSn
+ * | | |010 = EBI nWRH
+ * | | |011 = SPI1 1st slave select pin
+ * | | |111 = LCD SEG 4
+ * | | |Others = GPIOB[3]
+ * |[18:16] |PB4_MFP |PB.4 Pin Function Selection
+ * | | |001 = UART1 RX
+ * | | |011 = SmartCard0 card detection
+ * | | |100 = SPI2 1st slave select pin
+ * | | |111 = LCD SEG 13
+ * | | |Others = GPIOB[4]
+ * |[22:20] |PB5_MFP |PB.5 Pin Function Selection
+ * | | |001 = UART1 TX
+ * | | |011 = SmartCard0 RST
+ * | | |100 = SPI2 SCLK
+ * | | |111 = LCD SEG 12
+ * | | |Others = GPIOB[5]
+ * |[26:24] |PB6_MFP |PB.6 Pin Function Selection
+ * | | |001 = UART1 RTSn
+ * | | |010 = EBI ALE
+ * | | |100 = SPI2 MISO0
+ * | | |111 = LCD SEG 11
+ * | | |Others = GPIOB[6]
+ * |[30:28] |PB7_MFP |PB.7 Pin Function Selection
+ * | | |001 = UART1 CTSn
+ * | | |010 = EBI nCS
+ * | | |100 = SPI2 MOSI0
+ * | | |111 = LCD SEG 10
+ * | | |Others = GPIOB[7]
+ */
+ __IO uint32_t PB_L_MFP;
+
+ /**
+ * PB_H_MFP
+ * ===================================================================================================
+ * Offset: 0x3C Port B high byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PB8_MFP |PB.8 Pin Function Selection
+ * | | |001 = ADC external trigger
+ * | | |010 = Timer0 external event input or Timer0 toggle output
+ * | | |011 = External interrupt 0
+ * | | |100 = SmartCard 2 power
+ * | | |111 = LCD SEG 30
+ * | | |Others = GPIOB[8]
+ * |[6:4] |PB9_MFP |PB.9 Pin Function Selection
+ * | | |001 = SPI1 2nd slave select pin
+ * | | |010 = Timer1 external event input or Timer1 toggle output
+ * | | |100 = SmartCard 2 RST
+ * | | |101 = External interrupt 0
+ * | | |111 = LCD V1
+ * | | |Others = GPIOB[9]
+ * |[10:8] |PB10_MFP |PB.10 Pin Function Selection
+ * | | |001 = SPI0 2nd slave select pin
+ * | | |010 = Timer2 external event input or Timer2 toggle output
+ * | | |100 = SmartCard 2 clock
+ * | | |101 = SPI0 MOSI0
+ * | | |111 = LCD V2
+ * | | |Others = GPIOB[10]
+ * |[14:12] |PB11_MFP |PB.11 Pin Function Selection
+ * | | |001 = PWM1 Channel 0
+ * | | |010 = Timer3 external event input or Timer3 toggle output
+ * | | |100 = SmartCard 2 DATA
+ * | | |101 = SPI0 MISO0
+ * | | |111 = LCD V3
+ * | | |Others = GPIOB[11]
+ * |[18:16] |PB12_MFP |PB.12 Pin Function Selection
+ * | | |010 = EBI AD[0]
+ * | | |100 = FRQDIV_CLK
+ * | | |111 = LCD SEG 24
+ * | | |Others = GPIOB[12]
+ * |[22:20] |PB13_MFP |PB.13 Pin Function Selection
+ * | | |010 = EBI AD[1]
+ * | | |111 = LCD SEG 25
+ * | | |Others = GPIOB[13]
+ * |[26:24] |PB14_MFP |PB.14 Pin Function Selection
+ * | | |001 = External interrupt 0
+ * | | |011 = SmartCard 2 card detect
+ * | | |100 = SPI2 2nd slave select pin
+ * | | |111 = LCD SEG 26
+ * | | |Others = GPIOB[14]
+ * |[30:28] |PB15_MFP |PB.15 Pin Function Selection
+ * | | |001 = External interrupt 1
+ * | | |011 = Snooper pin
+ * | | |100 = SmartCard1 card detect
+ * | | |111 = LCD SEG 31
+ * | | |Others = GPIOB[15]
+ */
+ __IO uint32_t PB_H_MFP;
+
+ /**
+ * PC_L_MFP
+ * ===================================================================================================
+ * Offset: 0x40 Port C low byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PC0_MFP |PC.0 Pin Function Selection
+ * | | |001 = SPI0 1st slave select pin
+ * | | |010 = I2S WS
+ * | | |100 = SmartCard1 clock
+ * | | |111 = LCD DH1
+ * | | |Others = GPIOC[0]
+ * |[6:4] |PC1_MFP |PC.1 Pin Function Selection
+ * | | |001 = SPI0 SCLK
+ * | | |010 = I2S BCLK
+ * | | |100 = SmartCard1 DATA
+ * | | |111 = LCD DH2
+ * | | |Others = GPIOC[1]
+ * |[10:8] |PC2_MFP |PC.2 Pin Function Selection
+ * | | |001 = SPI0 MISO0
+ * | | |010 = I2S Din
+ * | | |100 = SmartCard1 Power
+ * | | |111 = LCD COM 0
+ * | | |Others = GPIOC[2]
+ * |[14:12] |PC3_MFP |PC.3 Pin Function Selection
+ * | | |001 = SPI0 MOSI1
+ * | | |010 = I2S Dout
+ * | | |100 = SmartCard1 RST
+ * | | |111 = LCD COM 1
+ * | | |Others = GPIOC[3]
+ * |[18:16] |PC4_MFP |PC.4 Pin Function Selection
+ * | | |001 = SPI0 MISO1
+ * | | |111 = LCD COM 2
+ * | | |Others = GPIOC[4]
+ * |[22:20] |PC5_MFP |PC.5 Pin Function Selection
+ * | | |001 = SPI0 MOSI1
+ * | | |111 = LCD COM 3
+ * | | |Others = GPIOC[5]
+ * |[26:24] |PC6_MFP |PC.6 Pin Function Selection
+ * | | |001 = DA out0
+ * | | |010 = EBI AD[4]
+ * | | |011 = Timer0 capture event
+ * | | |100 = SmartCard1 card detection
+ * | | |101 = PWM0 Channel 0
+ * | | |Others = GPIOC[6]
+ * |[30:28] |PC7_MFP |PC.7 Pin Function Selection
+ * | | |001 = DA out1
+ * | | |010 = EBI AD[5]
+ * | | |011 = Timer1 capture event
+ * | | |101 = PWM0 Channel 1
+ * | | |Others = GPIOC[7]
+ */
+ __IO uint32_t PC_L_MFP;
+
+ /**
+ * PC_H_MFP
+ * ===================================================================================================
+ * Offset: 0x44 Port C high byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PC8_MFP |PC.8 Pin Function Selection
+ * | | |001 = SPI1 1st slave select pin
+ * | | |010 = EBI MCLK
+ * | | |101 = I2C1 SDA
+ * | | |Others = GPIOC[8]
+ * |[6:4] |PC9_MFP |PC.9 Pin Function Selection
+ * | | |001 = SPI1 SCLK
+ * | | |101 = I2C1 SCL
+ * | | |Others = GPIOC[9]
+ * |[10:8] |PC10_MFP |PC.10 Pin Function Selection
+ * | | |001 = SPI1 MISO0
+ * | | |101 = UART1 RX
+ * | | |Others = GPIOC[10]
+ * |[14:12] |PC11_MFP |PC.11 Pin Function Selection
+ * | | |001 = SPI1 MOSI0
+ * | | |101 = UART1 TX
+ * | | |Others = GPIOC[11]
+ * |[18:16] |PC12_MFP |PC.12 Pin Function Selection
+ * | | |001 = SPI1 MISO1
+ * | | |010 = PWM1 Channel 0
+ * | | |101 = External interrupt 0
+ * | | |110 = I2C0 SDA
+ * | | |Others = GPIOC[12]
+ * |[22:20] |PC13_MFP |PC.13 Pin Function Selection
+ * | | |001 = SPI1 MOSI1
+ * | | |010 = PWM1 Channel 1
+ * | | |100 = Snooper pin
+ * | | |101 = External interrupt 1
+ * | | |110 = I2C0 SCL
+ * | | |Others = GPIOC[13]
+ * |[26:24] |PC14_MFP |PC.14 Pin Function Selection
+ * | | |010 = EBI AD[2]
+ * | | |100 = PWM1 Channel 3
+ * | | |111 = LCD SEG 32
+ * | | |Others = GPIOC[14]
+ * |[30:28] |PC15_MFP |PC.15 Pin Function Selection
+ * | | |010 = EBI AD[3]
+ * | | |011 = Timer0 capture event
+ * | | |100 = PWM1 Channel 2
+ * | | |111 = LCD SEG 33
+ * | | |Others = GPIOC[15]
+ */
+ __IO uint32_t PC_H_MFP;
+
+ /**
+ * PD_L_MFP
+ * ===================================================================================================
+ * Offset: 0x48 Port D low byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PD0_MFP |PD.0 Pin Function Selection
+ * | | |001 = UART1 RX
+ * | | |011 = SPI2 1st slave select pin
+ * | | |100 = SmartCard1 clock
+ * | | |101 = ADC input channel8
+ * | | |Others = GPIOD[0]
+ * |[6:4] |PD1_MFP |PD.1 Pin Function Selection
+ * | | |001 = UART1 TX
+ * | | |011 = SPI2 SCLK
+ * | | |100 = SmartCard1 DATA
+ * | | |101 = ADC input channel9
+ * | | |Others = GPIOD[1]
+ * |[10:8] |PD2_MFP |PD.2 Pin Function Selection
+ * | | |001 = UART1 RTSn
+ * | | |010 = I2S WS
+ * | | |011 = SPI2 MISO0
+ * | | |100 = SmartCard1 power
+ * | | |101 = ADC input channel10
+ * | | |Others = GPIOD[2]
+ * |[14:12] |PD3_MFP |PD.3 Pin Function Selection
+ * | | |001 = UART1 CTSn
+ * | | |010 = I2S BCLK
+ * | | |011 = SPI2 MOSI0
+ * | | |100 = SmartCard1 reset
+ * | | |101 = ADC input channel11
+ * | | |Others = GPIOD[3]
+ * |[18:16] |PD4_MFP |PD.4 Pin Function Selection
+ * | | |010 = I2S Din
+ * | | |011 = SPI2 MISO1
+ * | | |100 = SmartCard1 card detection
+ * | | |111 = LCD SEG 35
+ * | | |Others = GPIOD[4]
+ * |[22:20] |PD5_MFP |PD.5 Pin Function Selection
+ * | | |010 = I2S Dout
+ * | | |011 = SPI2 MOSI1
+ * | | |111 = LCD SEG 34
+ * | | |Others = GPIOD[5]
+ * |[26:24] |PD6_MFP |PD.6 Pin Function Selection
+ * | | |111 = LCD SEG 3
+ * | | |Others = GPIOD[6]
+ * |[30:28] |PD7_MFP |PD.7 Pin Function Selection
+ * | | |111 = LCD SEG 2
+ * | | |Others = GPIOD[7]
+ */
+ __IO uint32_t PD_L_MFP;
+
+ /**
+ * PD_H_MFP
+ * ===================================================================================================
+ * Offset: 0x4C Port D high byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PD8_MFP |PD.8 Pin Function Selection
+ * | | |111 = LCD SEG 19
+ * | | |Others = GPIOD[8]
+ * |[6:4] |PD9_MFP |PD.9 Pin Function Selection
+ * | | |111 = LCD SEG 18
+ * | | |Others = GPIOD[9]
+ * |[10:8] |PD10_MFP |PD.10 Pin Function Selection
+ * | | |111 = LCD SEG 17
+ * | | |Others = GPIOD[10]
+ * |[14:12] |PD11_MFP |PD.11 Pin Function Selection
+ * | | |111 = LCD SEG 16
+ * | | |Others = GPIOD[11]
+ * |[18:16] |PD12_MFP |PD.12 Pin Function Selection
+ * | | |111 = LCD SEG 15
+ * | | |Others = GPIOD[12]
+ * |[22:20] |PD13_MFP |PD.13 Pin Function Selection
+ * | | |111 = LCD SEG 14
+ * | | |Others = GPIOD[13]
+ * |[26:24] |PD14_MFP |PD.14 Pin Function Selection
+ * | | |111 = LCD SEG 1
+ * | | |Others = GPIOD[14]
+ * |[30:28] |PD15_MFP |PD.15 Pin Function Selection
+ * | | |111 = LCD SEG 0
+ * | | |Others = GPIOD[15]
+ */
+ __IO uint32_t PD_H_MFP;
+
+ /**
+ * PE_L_MFP
+ * ===================================================================================================
+ * Offset: 0x50 Port E low byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PE0_MFP |PE.0 Pin Function Selection
+ * | | |001 = PWM1 Channel 2
+ * | | |010 = I2S MCLK
+ * | | |Others = GPIOE[0]
+ * |[6:4] |PE1_MFP |PE.1 Pin Function Selection
+ * | | |001 = PWM1 Channel 3
+ * | | |110 = SPI0 1st slave select pin
+ * | | |Others = GPIOE[1]
+ * |[10:8] |PE2_MFP |PE.2 Pin Function Selection
+ * | | |110 = SPI0 SCLK
+ * | | |Others = GPIOE[2]
+ * |[14:12] |PE3_MFP |PE.3 Pin Function Selection
+ * | | |110 = SPI0 MISO0
+ * | | |Others = GPIOE[3]
+ * |[18:16] |PE4_MFP |PE.4 Pin Function Selection
+ * | | |110 = SPI0 MOSI0
+ * | | |Others = GPIOE[4]
+ * |[22:20] |PE5_MFP |PE.5 Pin Function Selection
+ * | | |001 = PWM1 Channel 1
+ * | | |Others = GPIOE[5]
+ * |[26:24] |PE6_MFP |PE.6 Pin Function Selection
+ * | | |GPIOE[6]
+ * |[30:28] |PE7_MFP |PE.7 Pin Function Selection
+ * | | |111 = LCD SEG 8
+ * | | |Others = GPIOE[7]
+ */
+ __IO uint32_t PE_L_MFP;
+
+ /**
+ * PE_H_MFP
+ * ===================================================================================================
+ * Offset: 0x54 Port E high byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PE8_MFP |PE.8 Pin Function Selection
+ * | | |111 = LCD SEG 9
+ * | | |Others = GPIOE[8]
+ * |[6:4] |PE9_MFP |PE.9 Pin Function Selection
+ * | | |111 = UART1 RX
+ * | | |Others = GPIOE[9]
+ * |[10:8] |PE10_MFP |PE.10 Pin Function Selection
+ * | | |111 = UART1 TX
+ * | | |Others = GPIOE[10]
+ * |[14:12] |PE11_MFP |PE.11 Pin Function Selection
+ * | | |111 = UART1 RTSn
+ * | | |Others = GPIOE[11]
+ * |[18:16] |PE12_MFP |PE.12 Pin Function Selection
+ * | | |111 = UART1 CTSn
+ * | | |Others = GPIOE[12]
+ * |[22:20] |PE13_MFP |PE.13 Pin Function Selection
+ * | | |111 = LCD SEG 27
+ * | | |Others = GPIOE[13]
+ * |[26:24] |PE14_MFP |PE.14 Pin Function Selection
+ * | | |111 = LCD SEG 28
+ * | | |Others = GPIOE[14]
+ * |[30:28] |PE15_MFP |PE.15 Pin Function Selection
+ * | | |111 = LCD SEG 2
+ * | | |Others = GPIOE[15]
+ */
+ __IO uint32_t PE_H_MFP;
+
+ /**
+ * PF_L_MFP
+ * ===================================================================================================
+ * Offset: 0x58 Port F low byte multiple function control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PF0_MFP |PF.0 Pin Function Selection
+ * | | |101 = External interrupt 0
+ * | | |111 = ICE DATA
+ * | | |Others = GPIOF[1]
+ * |[6:4] |PF1_MFP |PF.1 Pin Function Selection
+ * | | |100 = FRQDIV_CLK
+ * | | |101 = External interrupt 1
+ * | | |111 = ICE CLOCK
+ * | | |Others = GPIOF[1]
+ * |[10:8] |PF2_MFP |PF.2 Pin Function Selection
+ * | | |111 = HXT OUT
+ * | | |Others = GPIOF[2]
+ * |[14:12] |PF3_MFP |PF.3 Pin Function Selection
+ * | | |111 = HXT IN
+ * | | |Others = GPIOF[3]
+ * |[18:16] |PF4_MFP |PF.4 Pin Function Selection
+ * | | |001 = I2C0 SDA
+ * | | |Others = GPIOF[4]
+ * |[22:20] |PF5_MFP |PF.5 Pin Function Selection
+ * | | |001 = I2C0 SCL
+ * | | |Others = GPIOF[5]
+ */
+ __IO uint32_t PF_L_MFP;
+ uint32_t RESERVE2[1];
+
+
+ /**
+ * PORCTL
+ * ===================================================================================================
+ * Offset: 0x60 Power-On-Reset Controller Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |POR_DIS_CODE|Power-On Reset Enable Control
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
+ * | | |If setting the POR_DIS_CODE to 0x5AA5, the POR reset function will be disabled and the POR function will be active again when POR_DIS_CODE is set to another value or POR_DIS_CODE is reset by chip other reset functions, including: /RESET, Watchdog Timer reset, BOD reset, ICE reset command and the software-chip reset function.
+ */
+ __IO uint32_t PORCTL;
+
+ /**
+ * BODCTL
+ * ===================================================================================================
+ * Offset: 0x64 Brown-out Detector Controller Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BOD17_EN |Brown-Out Detector 1.7V Function Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |The default value is set by flash controller user configuration register config0 bit[20:19]
+ * | | |Users can disable BOD17_EN but it takes effective (disabled) only in Power-down mode.
+ * | | |Once existing Power-down mode, BOD17 will be enabled by HW automatically.
+ * | | |When CPU reads this bit, CPU will read whether BOD17 function enabled or not.
+ * | | |In other words,CPU will always read high.
+ * | | |0 = Brown-out Detector 1.7V function Disabled.
+ * | | |1 = Brown-out Detector 1.7V function Enabled.
+ * |[1] |BOD20_EN |Brown-Out Detector 2.0 V Function Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Brown-out Detector 2.0 V function Disabled.
+ * | | |1 = Brown-out Detector 2.0 V function Enabled.
+ * | | |BOD20_EN is default on.
+ * | | |If SW disables it, Brown-out Detector 2.0 V function is not disabled until chip enters power-down mode.
+ * | | |If system is not in power-down mode, BOD20_EN will be enabled by hardware automatically.
+ * |[2] |BOD25_EN |Brown-Out Detector 2.5 V Function Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Brown-out Detector 2.5 V function Disabled.
+ * | | |1 = Brown-out Detector 2.5 V function Enabled.
+ * |[4] |BOD17_RST_EN|BOD 1.7 V Reset Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Reset does not issue when BOD17 occurs.
+ * | | |1 = Reset issues when BOD17 occurs.
+ * | | |The default value is set by flash controller user configuration register config0 bit[20:19]
+ * | | |BOD17_RST_EN can be controlled (enable or disable) only when BOD17_EN is high.
+ * |[5] |BOD20_RST_EN|BOD 2.0 V Reset Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Reset does not issue when BOD20 occurs.
+ * | | |1 = Reset issues when BOD20 occurs.
+ * | | |The default value is set by flash controller user configuration register config0 bit[20:19]
+ * |[6] |BOD25_RST_EN|BOD 2.5 V Reset Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Reset does not issue when BOD25 occurs.
+ * | | |1 = Reset issues when BOD25 occurs.
+ * | | |The default value is set by flash controller user configuration register config0 bit[20:19]
+ * |[8] |BOD17_INT_EN|BOD 1.7 V Interrupt Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Interrupt does not issue when BOD17 occurs.
+ * | | |1 = Interrupt issues when BOD17 occurs.
+ * |[9] |BOD20_INT_EN|BOD 2.0 V Interrupt Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Interrupt does not issue when BOD20 occurs.
+ * | | |1 = Interrupt issues when BOD20 occurs.
+ * |[10] |BOD25_INT_EN|BOD 2.5 V Interrupt Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Interrupt does not issue when BOD25 occurs.
+ * | | |1 = Interrupt issues when BOD25 occurs.
+ */
+ __IO uint32_t BODCTL;
+
+ /**
+ * BODSTS
+ * ===================================================================================================
+ * Offset: 0x68 Brown-out Detector Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BOD_INT |Brown-Out Detector Interrupt Status
+ * | | |1 = When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage and Brown-out interrupt is enabled, this bit will be set to 1.
+ * | | |0 = Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled.
+ * | | |This bit is cleared by writing 1 to itself.
+ * |[1] |BOD17_drop|Brown-Out Detector Lower Than 1.7V Status
+ * | | |Setting BOD17_drop high means once the detected voltage is lower than target detected voltage setting (1.7V).
+ * | | |Software can write 1 to clear BOD17_drop.
+ * |[2] |BOD20_drop|Brown-Out Detector Lower Than 2.0V Status
+ * | | |Setting BOD20_drop high means once the detected voltage is lower than target detected voltage setting (2.0V).
+ * | | |Software can write 1 to clear BOD20_drop.
+ * |[3] |BOD25_drop|Brown-Out Detector Lower Than 2.5V Status
+ * | | |Setting BOD25_drop high means once the detected voltage is lower than target detected voltage setting (2.5V).
+ * | | |Software can write 1 to clear BOD25_drop.
+ * |[4] |BOD17_rise|Brown-Out Detector Higher Than 1.7V Status
+ * | | |Setting BOD17_rise high means once the detected voltage is higher than target detected voltage setting (1.7V).
+ * | | |Software can write 1 to clear BOD17_rise.
+ * |[5] |BOD20_rise|Brown-Out Detector Higher Than 2.0V Status
+ * | | |Setting BOD20_rise high means once the detected voltage is higher than target detected voltage setting (2.0V).
+ * | | |Software can write 1 to clear BOD20_rise.
+ * |[6] |BOD25_rise|Brown-Out Detector Higher Than 2.5V Status
+ * | | |Setting BOD25_rise high means once the detected voltage is higher than target detected voltage setting (2.5V).
+ * | | |Software can write 1 to clear BOD25_rise.
+ */
+ __IO uint32_t BODSTS;
+
+ /**
+ * Int_VREFCTL
+ * ===================================================================================================
+ * Offset: 0x6C Voltage reference Control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BGP_EN |Band-Gap Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Band-gap is the reference voltage of internal reference voltage.
+ * | | |User must enable band-gap if want to enable internal 1.8V or 2.5V reference voltage.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[1] |REG_EN |Regulator Enable
+ * | | |Enable internal 1.8V or 2.5V reference voltage.
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2] |SEL25 |Regulator Output Voltage Selection
+ * | | |Select internal reference voltage level.
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = 1.8V.
+ * | | |1 = 2.5V.
+ * |[3] |EXT_MODE |Regulator External Mode
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Users can output regulator output voltage in VREF pin if EXT_MODE is high.
+ * | | |0 = No connection with external VREF pin.
+ * | | |1 = Connect to external VREF pin.
+ * | | |Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable.
+ */
+ __IO uint32_t Int_VREFCTL;
+ uint32_t RESERVE3[4];
+
+
+ /**
+ * IRCTRIMCTL
+ * ===================================================================================================
+ * Offset: 0x80 HIRC Trim Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |TRIM_SEL |Trim Frequency Selection
+ * | | |This field indicates the target frequency of HIRC auto trim.
+ * | | |If no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled.
+ * | | |During auto trim operation, if 32.768 kHz clock error detected or trim retry limitation count reached, this field will be cleared to 00 automatically.
+ * | | |00 = Disable HIRC auto trim function
+ * | | |01 = Enable HIRC auto trim function and trim HIRC to 11.0592 MHz
+ * | | |10 = Enable HIRC auto trim function and trim HIRC to 12 MHz
+ * | | |11 = Enable HIRC auto trim function and trim HIRC to 12.288 MHz
+ * |[5:4] |TRIM_LOOP |Trim Calculation Loop
+ * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
+ * | | |For example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
+ * | | |00 = 4 32.768 kHz clock
+ * | | |01 = 8 32.768 kHz clock
+ * | | |10 = 16 32.768 kHz clock
+ * | | |11 = 32 32.768 kHz clock
+ * |[7:6] |TRIM_RETRY_CNT|Trim Value Update Limitation Count
+ * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+ * | | |Once the HIRC locked, the internal trim value update counter will be reset.
+ * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00.
+ * | | |00 = Trim retry count limitation is 64
+ * | | |01 = Trim retry count limitation is 128
+ * | | |10 = Trim retry count limitation is 256
+ * | | |11 = Trim retry count limitation is 512
+ * |[8] |ERR_STOP |Trim Stop When 32.768 KHz Error Detected
+ * | | |This bit is used to control if stop the HIRC trim operation when 32.768 kHz clock error is detected.
+ * | | |If set this bit high and 32.768 kHz clock error detected, the status 32K_ERR_INT would be set high and HIRC trim operation was stopped.
+ * | | |If this bit is low and 32.768 kHz clock error detected, the status 23K_ERR_INT would be set high and HIRC trim operation is continuously.
+ * | | |0 = Continue the HIRC trim operation even if 32.768 kHz clock error detected.
+ * | | |1 = Stop the HIRC trim operation if 32.768 kHz clock error detected.
+ */
+ __IO uint32_t IRCTRIMCTL;
+
+ /**
+ * IRCTRIMIEN
+ * ===================================================================================================
+ * Offset: 0x84 HIRC Trim Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TRIM_FAIL_IEN|Trim Failure Interrupt Enable
+ * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL.
+ * | | |If this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * | | |0 = TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU.
+ * | | |1 = TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU.
+ * |[2] |32K_ERR_IEN|32.768 KHz Clock Error Interrupt Enable
+ * | | |This bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation.
+ * | | |If this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.
+ * | | |0 = 32K_ERR_INT status Disabled to trigger an interrupt to CPU.
+ * | | |1 = 32K_ERR_INT status Enabled to trigger an interrupt to CPU.
+ */
+ __IO uint32_t IRCTRIMIEN;
+
+ /**
+ * IRCTRIMINT
+ * ===================================================================================================
+ * Offset: 0x88 HIRC Trim Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FREQ_LOCK |HIRC Frequency Lock Status
+ * | | |This bit indicates the HIRC frequency lock.
+ * | | |This is a status bit and doesn't trigger any interrupt.
+ * |[1] |TRIM_FAIL_INT|Trim Failure Interrupt Status
+ * | | |This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock.
+ * | | |Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.
+ * | | |If this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * | | |Write 1 to clear this to zero.
+ * | | |0 = Trim value update limitation count doesn't reach.
+ * | | |1 = Trim value update limitation count reached and HIRC frequency still doesn't lock.
+ * |[2] |32K_ERR_INT|32.768 KHz Clock Error Interrupt Status
+ * | | |This bit indicates that 32.768 kHz clock frequency is inaccuracy.
+ * | | |Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.
+ * | | |If this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.
+ * | | |Write 1 to clear this to zero.
+ * | | |0 = 32.768 kHz clock frequency is accuracy.
+ * | | |1 = 32.768 kHz clock frequency is inaccuracy.
+ */
+ __IO uint32_t IRCTRIMINT;
+ uint32_t RESERVE4[29];
+
+
+ /**
+ * RegLockAddr
+ * ===================================================================================================
+ * Offset: 0x100 Register Lock Key address
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RegUnLock |Register unlock bit
+ * | | |0 = Protected register are Locked. Any write to the target register is ignored.
+ * | | |1 = Protected registers are Unlocked.
+ */
+ __IO uint32_t RegLockAddr;
+
+} SYS_T;
+
+/**
+ @addtogroup SYS_CONST SYS Bit Field Definition
+ Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
+#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
+
+#define SYS_RST_SRC_RSTS_POR_Pos (0) /*!< SYS_T::RST_SRC: RSTS_POR Position */
+#define SYS_RST_SRC_RSTS_POR_Msk (0x1ul << SYS_RST_SRC_RSTS_POR_Pos) /*!< SYS_T::RST_SRC: RSTS_POR Mask */
+
+#define SYS_RST_SRC_RSTS_PAD_Pos (1) /*!< SYS_T::RST_SRC: RSTS_PAD Position */
+#define SYS_RST_SRC_RSTS_PAD_Msk (0x1ul << SYS_RST_SRC_RSTS_PAD_Pos) /*!< SYS_T::RST_SRC: RSTS_PAD Mask */
+
+#define SYS_RST_SRC_RSTS_WDT_Pos (2) /*!< SYS_T::RST_SRC: RSTS_WDT Position */
+#define SYS_RST_SRC_RSTS_WDT_Msk (0x1ul << SYS_RST_SRC_RSTS_WDT_Pos) /*!< SYS_T::RST_SRC: RSTS_WDT Mask */
+
+#define SYS_RST_SRC_RSTS_BOD_Pos (4) /*!< SYS_T::RST_SRC: RSTS_BOD Position */
+#define SYS_RST_SRC_RSTS_BOD_Msk (0x1ul << SYS_RST_SRC_RSTS_BOD_Pos) /*!< SYS_T::RST_SRC: RSTS_BOD Mask */
+
+#define SYS_RST_SRC_RSTS_SYS_Pos (5) /*!< SYS_T::RST_SRC: RSTS_SYS_T::Position */
+#define SYS_RST_SRC_RSTS_SYS_Msk (0x1ul << SYS_RST_SRC_RSTS_SYS_Pos) /*!< SYS_T::RST_SRC: RSTS_SYS_T::Mask */
+
+#define SYS_RST_SRC_RSTS_CPU_Pos (7) /*!< SYS_T::RST_SRC: RSTS_CPU Position */
+#define SYS_RST_SRC_RSTS_CPU_Msk (0x1ul << SYS_RST_SRC_RSTS_CPU_Pos) /*!< SYS_T::RST_SRC: RSTS_CPU Mask */
+
+#define SYS_IPRST_CTL1_CHIP_RST_Pos (0) /*!< SYS_T::IPRST_CTL1: CHIP_RST Position */
+#define SYS_IPRST_CTL1_CHIP_RST_Msk (0x1ul << SYS_IPRST_CTL1_CHIP_RST_Pos) /*!< SYS_T::IPRST_CTL1: CHIP_RST Mask */
+
+#define SYS_IPRST_CTL1_CPU_RST_Pos (1) /*!< SYS_T::IPRST_CTL1: CPU_RST Position */
+#define SYS_IPRST_CTL1_CPU_RST_Msk (0x1ul << SYS_IPRST_CTL1_CPU_RST_Pos) /*!< SYS_T::IPRST_CTL1: CPU_RST Mask */
+
+#define SYS_IPRST_CTL1_DMA_RST_Pos (2) /*!< SYS_T::IPRST_CTL1: DMA_RST Position */
+#define SYS_IPRST_CTL1_DMA_RST_Msk (0x1ul << SYS_IPRST_CTL1_DMA_RST_Pos) /*!< SYS_T::IPRST_CTL1: DMA_RST Mask */
+
+#define SYS_IPRST_CTL1_EBI_RST_Pos (3) /*!< SYS_T::IPRST_CTL1: EBI_RST Position */
+#define SYS_IPRST_CTL1_EBI_RST_Msk (0x1ul << SYS_IPRST_CTL1_EBI_RST_Pos) /*!< SYS_T::IPRST_CTL1: EBI_RST Mask */
+
+#define SYS_IPRST_CTL2_GPIO_RST_Pos (1) /*!< SYS_T::IPRST_CTL2: GPIO_RST Position */
+#define SYS_IPRST_CTL2_GPIO_RST_Msk (0x1ul << SYS_IPRST_CTL2_GPIO_RST_Pos) /*!< SYS_T::IPRST_CTL2: GPIO_RST Mask */
+
+#define SYS_IPRST_CTL2_TMR0_RST_Pos (2) /*!< SYS_T::IPRST_CTL2: TMR0_RST Position */
+#define SYS_IPRST_CTL2_TMR0_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR0_RST_Pos) /*!< SYS_T::IPRST_CTL2: TMR0_RST Mask */
+
+#define SYS_IPRST_CTL2_TMR1_RST_Pos (3) /*!< SYS_T::IPRST_CTL2: TMR1_RST Position */
+#define SYS_IPRST_CTL2_TMR1_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR1_RST_Pos) /*!< SYS_T::IPRST_CTL2: TMR1_RST Mask */
+
+#define SYS_IPRST_CTL2_TMR2_RST_Pos (4) /*!< SYS_T::IPRST_CTL2: TMR2_RST Position */
+#define SYS_IPRST_CTL2_TMR2_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR2_RST_Pos) /*!< SYS_T::IPRST_CTL2: TMR2_RST Mask */
+
+#define SYS_IPRST_CTL2_TMR3_RST_Pos (5) /*!< SYS_T::IPRST_CTL2: TMR3_RST Position */
+#define SYS_IPRST_CTL2_TMR3_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR3_RST_Pos) /*!< SYS_T::IPRST_CTL2: TMR3_RST Mask */
+
+#define SYS_IPRST_CTL2_SC2_RST_Pos (7) /*!< SYS_T::IPRST_CTL2: SC2_RST Position */
+#define SYS_IPRST_CTL2_SC2_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC2_RST_Pos) /*!< SYS_T::IPRST_CTL2: SC2_RST Mask */
+
+#define SYS_IPRST_CTL2_I2C0_RST_Pos (8) /*!< SYS_T::IPRST_CTL2: I2C0_RST Position */
+#define SYS_IPRST_CTL2_I2C0_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C0_RST_Pos) /*!< SYS_T::IPRST_CTL2: I2C0_RST Mask */
+
+#define SYS_IPRST_CTL2_I2C1_RST_Pos (9) /*!< SYS_T::IPRST_CTL2: I2C1_RST Position */
+#define SYS_IPRST_CTL2_I2C1_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C1_RST_Pos) /*!< SYS_T::IPRST_CTL2: I2C1_RST Mask */
+
+#define SYS_IPRST_CTL2_SPI0_RST_Pos (12) /*!< SYS_T::IPRST_CTL2: SPI0_RST Position */
+#define SYS_IPRST_CTL2_SPI0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI0_RST_Pos) /*!< SYS_T::IPRST_CTL2: SPI0_RST Mask */
+
+#define SYS_IPRST_CTL2_SPI1_RST_Pos (13) /*!< SYS_T::IPRST_CTL2: SPI1_RST Position */
+#define SYS_IPRST_CTL2_SPI1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI1_RST_Pos) /*!< SYS_T::IPRST_CTL2: SPI1_RST Mask */
+
+#define SYS_IPRST_CTL2_SPI2_RST_Pos (14) /*!< SYS_T::IPRST_CTL2: SPI2_RST Position */
+#define SYS_IPRST_CTL2_SPI2_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI2_RST_Pos) /*!< SYS_T::IPRST_CTL2: SPI2_RST Mask */
+
+#define SYS_IPRST_CTL2_UART0_RST_Pos (16) /*!< SYS_T::IPRST_CTL2: UART0_RST Position */
+#define SYS_IPRST_CTL2_UART0_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART0_RST_Pos) /*!< SYS_T::IPRST_CTL2: UART0_RST Mask */
+
+#define SYS_IPRST_CTL2_UART1_RST_Pos (17) /*!< SYS_T::IPRST_CTL2: UART1_RST Position */
+#define SYS_IPRST_CTL2_UART1_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART1_RST_Pos) /*!< SYS_T::IPRST_CTL2: UART1_RST Mask */
+
+#define SYS_IPRST_CTL2_PWM0_RST_Pos (20) /*!< SYS_T::IPRST_CTL2: PWM0_RST Position */
+#define SYS_IPRST_CTL2_PWM0_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM0_RST_Pos) /*!< SYS_T::IPRST_CTL2: PWM0_RST Mask */
+
+#define SYS_IPRST_CTL2_PWM1_RST_Pos (21) /*!< SYS_T::IPRST_CTL2: PWM1_RST Position */
+#define SYS_IPRST_CTL2_PWM1_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM1_RST_Pos) /*!< SYS_T::IPRST_CTL2: PWM1_RST Mask */
+
+#define SYS_IPRST_CTL2_DAC_RST_Pos (25) /*!< SYS_T::IPRST_CTL2: DAC_RST Position */
+#define SYS_IPRST_CTL2_DAC_RST_Msk (0x1ul << SYS_IPRST_CTL2_DAC_RST_Pos) /*!< SYS_T::IPRST_CTL2: DAC_RST Mask */
+
+#define SYS_IPRST_CTL2_LCD_RST_Pos (26) /*!< SYS_T::IPRST_CTL2: LCD_RST Position */
+#define SYS_IPRST_CTL2_LCD_RST_Msk (0x1ul << SYS_IPRST_CTL2_LCD_RST_Pos) /*!< SYS_T::IPRST_CTL2: LCD_RST Mask */
+
+#define SYS_IPRST_CTL2_USBD_RST_Pos (27) /*!< SYS_T::IPRST_CTL2: USBD_RST Position */
+#define SYS_IPRST_CTL2_USBD_RST_Msk (0x1ul << SYS_IPRST_CTL2_USBD_RST_Pos) /*!< SYS_T::IPRST_CTL2: USBD_RST Mask */
+
+#define SYS_IPRST_CTL2_ADC_RST_Pos (28) /*!< SYS_T::IPRST_CTL2: ADC_RST Position */
+#define SYS_IPRST_CTL2_ADC_RST_Msk (0x1ul << SYS_IPRST_CTL2_ADC_RST_Pos) /*!< SYS_T::IPRST_CTL2: ADC_RST Mask */
+
+#define SYS_IPRST_CTL2_I2S_RST_Pos (29) /*!< SYS_T::IPRST_CTL2: I2S_RST Position */
+#define SYS_IPRST_CTL2_I2S_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2S_RST_Pos) /*!< SYS_T::IPRST_CTL2: I2S_RST Mask */
+
+#define SYS_IPRST_CTL2_SC0_RST_Pos (30) /*!< SYS_T::IPRST_CTL2: SC0_RST Position */
+#define SYS_IPRST_CTL2_SC0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC0_RST_Pos) /*!< SYS_T::IPRST_CTL2: SC0_RST Mask */
+
+#define SYS_IPRST_CTL2_SC1_RST_Pos (31) /*!< SYS_T::IPRST_CTL2: SC1_RST Position */
+#define SYS_IPRST_CTL2_SC1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC1_RST_Pos) /*!< SYS_T::IPRST_CTL2: SC1_RST Mask */
+
+#define SYS_TEMPCTL_VTEMP_EN_Pos (0) /*!< SYS_T::TEMPCTL: VTEMP_EN Position */
+#define SYS_TEMPCTL_VTEMP_EN_Msk (0x1ul << SYS_TEMPCTL_VTEMP_EN_Pos) /*!< SYS_T::TEMPCTL: VTEMP_EN Mask */
+
+#define SYS_PA_L_MFP_PA0_MFP_Pos (0) /*!< SYS_T::PA_L_MFP: PA0_MFP Position */
+#define SYS_PA_L_MFP_PA0_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA0_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA0_MFP Mask */
+
+#define SYS_PA_L_MFP_PA1_MFP_Pos (4) /*!< SYS_T::PA_L_MFP: PA1_MFP Position */
+#define SYS_PA_L_MFP_PA1_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA1_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA1_MFP Mask */
+
+#define SYS_PA_L_MFP_PA2_MFP_Pos (8) /*!< SYS_T::PA_L_MFP: PA2_MFP Position */
+#define SYS_PA_L_MFP_PA2_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA2_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA2_MFP Mask */
+
+#define SYS_PA_L_MFP_PA3_MFP_Pos (12) /*!< SYS_T::PA_L_MFP: PA3_MFP Position */
+#define SYS_PA_L_MFP_PA3_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA3_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA3_MFP Mask */
+
+#define SYS_PA_L_MFP_PA4_MFP_Pos (16) /*!< SYS_T::PA_L_MFP: PA4_MFP Position */
+#define SYS_PA_L_MFP_PA4_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA4_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA4_MFP Mask */
+
+#define SYS_PA_L_MFP_PA5_MFP_Pos (20) /*!< SYS_T::PA_L_MFP: PA5_MFP Position */
+#define SYS_PA_L_MFP_PA5_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA5_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA5_MFP Mask */
+
+#define SYS_PA_L_MFP_PA6_MFP_Pos (24) /*!< SYS_T::PA_L_MFP: PA6_MFP Position */
+#define SYS_PA_L_MFP_PA6_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA6_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA6_MFP Mask */
+
+#define SYS_PA_L_MFP_PA7_MFP_Pos (28) /*!< SYS_T::PA_L_MFP: PA7_MFP Position */
+#define SYS_PA_L_MFP_PA7_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA7_MFP_Pos) /*!< SYS_T::PA_L_MFP: PA7_MFP Mask */
+
+#define SYS_PA_H_MFP_PA8_MFP_Pos (0) /*!< SYS_T::PA_H_MFP: PA8_MFP Position */
+#define SYS_PA_H_MFP_PA8_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA8_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA8_MFP Mask */
+
+#define SYS_PA_H_MFP_PA9_MFP_Pos (4) /*!< SYS_T::PA_H_MFP: PA9_MFP Position */
+#define SYS_PA_H_MFP_PA9_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA9_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA9_MFP Mask */
+
+#define SYS_PA_H_MFP_PA10_MFP_Pos (8) /*!< SYS_T::PA_H_MFP: PA10_MFP Position */
+#define SYS_PA_H_MFP_PA10_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA10_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA10_MFP Mask */
+
+#define SYS_PA_H_MFP_PA11_MFP_Pos (12) /*!< SYS_T::PA_H_MFP: PA11_MFP Position */
+#define SYS_PA_H_MFP_PA11_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA11_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA11_MFP Mask */
+
+#define SYS_PA_H_MFP_PA12_MFP_Pos (16) /*!< SYS_T::PA_H_MFP: PA12_MFP Position */
+#define SYS_PA_H_MFP_PA12_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA12_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA12_MFP Mask */
+
+#define SYS_PA_H_MFP_PA13_MFP_Pos (20) /*!< SYS_T::PA_H_MFP: PA13_MFP Position */
+#define SYS_PA_H_MFP_PA13_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA13_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA13_MFP Mask */
+
+#define SYS_PA_H_MFP_PA14_MFP_Pos (24) /*!< SYS_T::PA_H_MFP: PA14_MFP Position */
+#define SYS_PA_H_MFP_PA14_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA14_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA14_MFP Mask */
+
+#define SYS_PA_H_MFP_PA15_MFP_Pos (28) /*!< SYS_T::PA_H_MFP: PA15_MFP Position */
+#define SYS_PA_H_MFP_PA15_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA15_MFP_Pos) /*!< SYS_T::PA_H_MFP: PA15_MFP Mask */
+
+#define SYS_PB_L_MFP_PB0_MFP_Pos (0) /*!< SYS_T::PB_L_MFP: PB0_MFP Position */
+#define SYS_PB_L_MFP_PB0_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB0_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB0_MFP Mask */
+
+#define SYS_PB_L_MFP_PB1_MFP_Pos (4) /*!< SYS_T::PB_L_MFP: PB1_MFP Position */
+#define SYS_PB_L_MFP_PB1_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB1_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB1_MFP Mask */
+
+#define SYS_PB_L_MFP_PB2_MFP_Pos (8) /*!< SYS_T::PB_L_MFP: PB2_MFP Position */
+#define SYS_PB_L_MFP_PB2_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB2_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB2_MFP Mask */
+
+#define SYS_PB_L_MFP_PB3_MFP_Pos (12) /*!< SYS_T::PB_L_MFP: PB3_MFP Position */
+#define SYS_PB_L_MFP_PB3_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB3_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB3_MFP Mask */
+
+#define SYS_PB_L_MFP_PB4_MFP_Pos (16) /*!< SYS_T::PB_L_MFP: PB4_MFP Position */
+#define SYS_PB_L_MFP_PB4_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB4_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB4_MFP Mask */
+
+#define SYS_PB_L_MFP_PB5_MFP_Pos (20) /*!< SYS_T::PB_L_MFP: PB5_MFP Position */
+#define SYS_PB_L_MFP_PB5_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB5_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB5_MFP Mask */
+
+#define SYS_PB_L_MFP_PB6_MFP_Pos (24) /*!< SYS_T::PB_L_MFP: PB6_MFP Position */
+#define SYS_PB_L_MFP_PB6_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB6_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB6_MFP Mask */
+
+#define SYS_PB_L_MFP_PB7_MFP_Pos (28) /*!< SYS_T::PB_L_MFP: PB7_MFP Position */
+#define SYS_PB_L_MFP_PB7_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB7_MFP_Pos) /*!< SYS_T::PB_L_MFP: PB7_MFP Mask */
+
+#define SYS_PB_H_MFP_PB8_MFP_Pos (0) /*!< SYS_T::PB_H_MFP: PB8_MFP Position */
+#define SYS_PB_H_MFP_PB8_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB8_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB8_MFP Mask */
+
+#define SYS_PB_H_MFP_PB9_MFP_Pos (4) /*!< SYS_T::PB_H_MFP: PB9_MFP Position */
+#define SYS_PB_H_MFP_PB9_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB9_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB9_MFP Mask */
+
+#define SYS_PB_H_MFP_PB10_MFP_Pos (8) /*!< SYS_T::PB_H_MFP: PB10_MFP Position */
+#define SYS_PB_H_MFP_PB10_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB10_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB10_MFP Mask */
+
+#define SYS_PB_H_MFP_PB11_MFP_Pos (12) /*!< SYS_T::PB_H_MFP: PB11_MFP Position */
+#define SYS_PB_H_MFP_PB11_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB11_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB11_MFP Mask */
+
+#define SYS_PB_H_MFP_PB12_MFP_Pos (16) /*!< SYS_T::PB_H_MFP: PB12_MFP Position */
+#define SYS_PB_H_MFP_PB12_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB12_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB12_MFP Mask */
+
+#define SYS_PB_H_MFP_PB13_MFP_Pos (20) /*!< SYS_T::PB_H_MFP: PB13_MFP Position */
+#define SYS_PB_H_MFP_PB13_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB13_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB13_MFP Mask */
+
+#define SYS_PB_H_MFP_PB14_MFP_Pos (24) /*!< SYS_T::PB_H_MFP: PB14_MFP Position */
+#define SYS_PB_H_MFP_PB14_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB14_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB14_MFP Mask */
+
+#define SYS_PB_H_MFP_PB15_MFP_Pos (28) /*!< SYS_T::PB_H_MFP: PB15_MFP Position */
+#define SYS_PB_H_MFP_PB15_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB15_MFP_Pos) /*!< SYS_T::PB_H_MFP: PB15_MFP Mask */
+
+#define SYS_PC_L_MFP_PC0_MFP_Pos (0) /*!< SYS_T::PC_L_MFP: PC0_MFP Position */
+#define SYS_PC_L_MFP_PC0_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC0_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC0_MFP Mask */
+
+#define SYS_PC_L_MFP_PC1_MFP_Pos (4) /*!< SYS_T::PC_L_MFP: PC1_MFP Position */
+#define SYS_PC_L_MFP_PC1_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC1_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC1_MFP Mask */
+
+#define SYS_PC_L_MFP_PC2_MFP_Pos (8) /*!< SYS_T::PC_L_MFP: PC2_MFP Position */
+#define SYS_PC_L_MFP_PC2_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC2_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC2_MFP Mask */
+
+#define SYS_PC_L_MFP_PC3_MFP_Pos (12) /*!< SYS_T::PC_L_MFP: PC3_MFP Position */
+#define SYS_PC_L_MFP_PC3_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC3_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC3_MFP Mask */
+
+#define SYS_PC_L_MFP_PC4_MFP_Pos (16) /*!< SYS_T::PC_L_MFP: PC4_MFP Position */
+#define SYS_PC_L_MFP_PC4_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC4_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC4_MFP Mask */
+
+#define SYS_PC_L_MFP_PC5_MFP_Pos (20) /*!< SYS_T::PC_L_MFP: PC5_MFP Position */
+#define SYS_PC_L_MFP_PC5_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC5_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC5_MFP Mask */
+
+#define SYS_PC_L_MFP_PC6_MFP_Pos (24) /*!< SYS_T::PC_L_MFP: PC6_MFP Position */
+#define SYS_PC_L_MFP_PC6_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC6_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC6_MFP Mask */
+
+#define SYS_PC_L_MFP_PC7_MFP_Pos (28) /*!< SYS_T::PC_L_MFP: PC7_MFP Position */
+#define SYS_PC_L_MFP_PC7_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC7_MFP_Pos) /*!< SYS_T::PC_L_MFP: PC7_MFP Mask */
+
+#define SYS_PC_H_MFP_PC8_MFP_Pos (0) /*!< SYS_T::PC_H_MFP: PC8_MFP Position */
+#define SYS_PC_H_MFP_PC8_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC8_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC8_MFP Mask */
+
+#define SYS_PC_H_MFP_PC9_MFP_Pos (4) /*!< SYS_T::PC_H_MFP: PC9_MFP Position */
+#define SYS_PC_H_MFP_PC9_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC9_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC9_MFP Mask */
+
+#define SYS_PC_H_MFP_PC10_MFP_Pos (8) /*!< SYS_T::PC_H_MFP: PC10_MFP Position */
+#define SYS_PC_H_MFP_PC10_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC10_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC10_MFP Mask */
+
+#define SYS_PC_H_MFP_PC11_MFP_Pos (12) /*!< SYS_T::PC_H_MFP: PC11_MFP Position */
+#define SYS_PC_H_MFP_PC11_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC11_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC11_MFP Mask */
+
+#define SYS_PC_H_MFP_PC12_MFP_Pos (16) /*!< SYS_T::PC_H_MFP: PC12_MFP Position */
+#define SYS_PC_H_MFP_PC12_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC12_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC12_MFP Mask */
+
+#define SYS_PC_H_MFP_PC13_MFP_Pos (20) /*!< SYS_T::PC_H_MFP: PC13_MFP Position */
+#define SYS_PC_H_MFP_PC13_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC13_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC13_MFP Mask */
+
+#define SYS_PC_H_MFP_PC14_MFP_Pos (24) /*!< SYS_T::PC_H_MFP: PC14_MFP Position */
+#define SYS_PC_H_MFP_PC14_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC14_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC14_MFP Mask */
+
+#define SYS_PC_H_MFP_PC15_MFP_Pos (28) /*!< SYS_T::PC_H_MFP: PC15_MFP Position */
+#define SYS_PC_H_MFP_PC15_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC15_MFP_Pos) /*!< SYS_T::PC_H_MFP: PC15_MFP Mask */
+
+#define SYS_PD_L_MFP_PD0_MFP_Pos (0) /*!< SYS_T::PD_L_MFP: PD0_MFP Position */
+#define SYS_PD_L_MFP_PD0_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD0_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD0_MFP Mask */
+
+#define SYS_PD_L_MFP_PD1_MFP_Pos (4) /*!< SYS_T::PD_L_MFP: PD1_MFP Position */
+#define SYS_PD_L_MFP_PD1_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD1_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD1_MFP Mask */
+
+#define SYS_PD_L_MFP_PD2_MFP_Pos (8) /*!< SYS_T::PD_L_MFP: PD2_MFP Position */
+#define SYS_PD_L_MFP_PD2_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD2_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD2_MFP Mask */
+
+#define SYS_PD_L_MFP_PD3_MFP_Pos (12) /*!< SYS_T::PD_L_MFP: PD3_MFP Position */
+#define SYS_PD_L_MFP_PD3_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD3_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD3_MFP Mask */
+
+#define SYS_PD_L_MFP_PD4_MFP_Pos (16) /*!< SYS_T::PD_L_MFP: PD4_MFP Position */
+#define SYS_PD_L_MFP_PD4_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD4_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD4_MFP Mask */
+
+#define SYS_PD_L_MFP_PD5_MFP_Pos (20) /*!< SYS_T::PD_L_MFP: PD5_MFP Position */
+#define SYS_PD_L_MFP_PD5_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD5_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD5_MFP Mask */
+
+#define SYS_PD_L_MFP_PD6_MFP_Pos (24) /*!< SYS_T::PD_L_MFP: PD6_MFP Position */
+#define SYS_PD_L_MFP_PD6_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD6_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD6_MFP Mask */
+
+#define SYS_PD_L_MFP_PD7_MFP_Pos (28) /*!< SYS_T::PD_L_MFP: PD7_MFP Position */
+#define SYS_PD_L_MFP_PD7_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD7_MFP_Pos) /*!< SYS_T::PD_L_MFP: PD7_MFP Mask */
+
+#define SYS_PD_H_MFP_PD8_MFP_Pos (0) /*!< SYS_T::PD_H_MFP: PD8_MFP Position */
+#define SYS_PD_H_MFP_PD8_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD8_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD8_MFP Mask */
+
+#define SYS_PD_H_MFP_PD9_MFP_Pos (4) /*!< SYS_T::PD_H_MFP: PD9_MFP Position */
+#define SYS_PD_H_MFP_PD9_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD9_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD9_MFP Mask */
+
+#define SYS_PD_H_MFP_PD10_MFP_Pos (8) /*!< SYS_T::PD_H_MFP: PD10_MFP Position */
+#define SYS_PD_H_MFP_PD10_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD10_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD10_MFP Mask */
+
+#define SYS_PD_H_MFP_PD11_MFP_Pos (12) /*!< SYS_T::PD_H_MFP: PD11_MFP Position */
+#define SYS_PD_H_MFP_PD11_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD11_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD11_MFP Mask */
+
+#define SYS_PD_H_MFP_PD12_MFP_Pos (16) /*!< SYS_T::PD_H_MFP: PD12_MFP Position */
+#define SYS_PD_H_MFP_PD12_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD12_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD12_MFP Mask */
+
+#define SYS_PD_H_MFP_PD13_MFP_Pos (20) /*!< SYS_T::PD_H_MFP: PD13_MFP Position */
+#define SYS_PD_H_MFP_PD13_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD13_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD13_MFP Mask */
+
+#define SYS_PD_H_MFP_PD14_MFP_Pos (24) /*!< SYS_T::PD_H_MFP: PD14_MFP Position */
+#define SYS_PD_H_MFP_PD14_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD14_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD14_MFP Mask */
+
+#define SYS_PD_H_MFP_PD15_MFP_Pos (28) /*!< SYS_T::PD_H_MFP: PD15_MFP Position */
+#define SYS_PD_H_MFP_PD15_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD15_MFP_Pos) /*!< SYS_T::PD_H_MFP: PD15_MFP Mask */
+
+#define SYS_PE_L_MFP_PE0_MFP_Pos (0) /*!< SYS_T::PE_L_MFP: PE0_MFP Position */
+#define SYS_PE_L_MFP_PE0_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE0_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE0_MFP Mask */
+
+#define SYS_PE_L_MFP_PE1_MFP_Pos (4) /*!< SYS_T::PE_L_MFP: PE1_MFP Position */
+#define SYS_PE_L_MFP_PE1_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE1_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE1_MFP Mask */
+
+#define SYS_PE_L_MFP_PE2_MFP_Pos (8) /*!< SYS_T::PE_L_MFP: PE2_MFP Position */
+#define SYS_PE_L_MFP_PE2_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE2_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE2_MFP Mask */
+
+#define SYS_PE_L_MFP_PE3_MFP_Pos (12) /*!< SYS_T::PE_L_MFP: PE3_MFP Position */
+#define SYS_PE_L_MFP_PE3_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE3_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE3_MFP Mask */
+
+#define SYS_PE_L_MFP_PE4_MFP_Pos (16) /*!< SYS_T::PE_L_MFP: PE4_MFP Position */
+#define SYS_PE_L_MFP_PE4_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE4_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE4_MFP Mask */
+
+#define SYS_PE_L_MFP_PE5_MFP_Pos (20) /*!< SYS_T::PE_L_MFP: PE5_MFP Position */
+#define SYS_PE_L_MFP_PE5_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE5_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE5_MFP Mask */
+
+#define SYS_PE_L_MFP_PE6_MFP_Pos (24) /*!< SYS_T::PE_L_MFP: PE6_MFP Position */
+#define SYS_PE_L_MFP_PE6_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE6_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE6_MFP Mask */
+
+#define SYS_PE_L_MFP_PE7_MFP_Pos (28) /*!< SYS_T::PE_L_MFP: PE7_MFP Position */
+#define SYS_PE_L_MFP_PE7_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE7_MFP_Pos) /*!< SYS_T::PE_L_MFP: PE7_MFP Mask */
+
+#define SYS_PE_H_MFP_PE8_MFP_Pos (0) /*!< SYS_T::PE_H_MFP: PE8_MFP Position */
+#define SYS_PE_H_MFP_PE8_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE8_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE8_MFP Mask */
+
+#define SYS_PE_H_MFP_PE9_MFP_Pos (4) /*!< SYS_T::PE_H_MFP: PE9_MFP Position */
+#define SYS_PE_H_MFP_PE9_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE9_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE9_MFP Mask */
+
+#define SYS_PE_H_MFP_PE10_MFP_Pos (8) /*!< SYS_T::PE_H_MFP: PE10_MFP Position */
+#define SYS_PE_H_MFP_PE10_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE10_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE10_MFP Mask */
+
+#define SYS_PE_H_MFP_PE11_MFP_Pos (12) /*!< SYS_T::PE_H_MFP: PE11_MFP Position */
+#define SYS_PE_H_MFP_PE11_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE11_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE11_MFP Mask */
+
+#define SYS_PE_H_MFP_PE12_MFP_Pos (16) /*!< SYS_T::PE_H_MFP: PE12_MFP Position */
+#define SYS_PE_H_MFP_PE12_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE12_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE12_MFP Mask */
+
+#define SYS_PE_H_MFP_PE13_MFP_Pos (20) /*!< SYS_T::PE_H_MFP: PE13_MFP Position */
+#define SYS_PE_H_MFP_PE13_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE13_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE13_MFP Mask */
+
+#define SYS_PE_H_MFP_PE14_MFP_Pos (24) /*!< SYS_T::PE_H_MFP: PE14_MFP Position */
+#define SYS_PE_H_MFP_PE14_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE14_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE14_MFP Mask */
+
+#define SYS_PE_H_MFP_PE15_MFP_Pos (28) /*!< SYS_T::PE_H_MFP: PE15_MFP Position */
+#define SYS_PE_H_MFP_PE15_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE15_MFP_Pos) /*!< SYS_T::PE_H_MFP: PE15_MFP Mask */
+
+#define SYS_PF_L_MFP_PF0_MFP_Pos (0) /*!< SYS_T::PF_L_MFP: PF0_MFP Position */
+#define SYS_PF_L_MFP_PF0_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF0_MFP_Pos) /*!< SYS_T::PF_L_MFP: PF0_MFP Mask */
+
+#define SYS_PF_L_MFP_PF1_MFP_Pos (4) /*!< SYS_T::PF_L_MFP: PF1_MFP Position */
+#define SYS_PF_L_MFP_PF1_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF1_MFP_Pos) /*!< SYS_T::PF_L_MFP: PF1_MFP Mask */
+
+#define SYS_PF_L_MFP_PF2_MFP_Pos (8) /*!< SYS_T::PF_L_MFP: PF2_MFP Position */
+#define SYS_PF_L_MFP_PF2_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF2_MFP_Pos) /*!< SYS_T::PF_L_MFP: PF2_MFP Mask */
+
+#define SYS_PF_L_MFP_PF3_MFP_Pos (12) /*!< SYS_T::PF_L_MFP: PF3_MFP Position */
+#define SYS_PF_L_MFP_PF3_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF3_MFP_Pos) /*!< SYS_T::PF_L_MFP: PF3_MFP Mask */
+
+#define SYS_PF_L_MFP_PF4_MFP_Pos (16) /*!< SYS_T::PF_L_MFP: PF4_MFP Position */
+#define SYS_PF_L_MFP_PF4_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF4_MFP_Pos) /*!< SYS_T::PF_L_MFP: PF4_MFP Mask */
+
+#define SYS_PF_L_MFP_PF5_MFP_Pos (20) /*!< SYS_T::PF_L_MFP: PF5_MFP Position */
+#define SYS_PF_L_MFP_PF5_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF5_MFP_Pos) /*!< SYS_T::PF_L_MFP: PF5_MFP Mask */
+
+#define SYS_PORCTL_POR_DIS_CODE_Pos (0) /*!< SYS_T::PORCTL: POR_DIS_CODE Position */
+#define SYS_PORCTL_POR_DIS_CODE_Msk (0xfffful << SYS_PORCTL_POR_DIS_CODE_Pos) /*!< SYS_T::PORCTL: POR_DIS_CODE Mask */
+
+#define SYS_BODCTL_BOD17_EN_Pos (0) /*!< SYS_T::BODCTL: BOD17_EN Position */
+#define SYS_BODCTL_BOD17_EN_Msk (0x1ul << SYS_BODCTL_BOD17_EN_Pos) /*!< SYS_T::BODCTL: BOD17_EN Mask */
+
+#define SYS_BODCTL_BOD20_EN_Pos (1) /*!< SYS_T::BODCTL: BOD20_EN Position */
+#define SYS_BODCTL_BOD20_EN_Msk (0x1ul << SYS_BODCTL_BOD20_EN_Pos) /*!< SYS_T::BODCTL: BOD20_EN Mask */
+
+#define SYS_BODCTL_BOD25_EN_Pos (2) /*!< SYS_T::BODCTL: BOD25_EN Position */
+#define SYS_BODCTL_BOD25_EN_Msk (0x1ul << SYS_BODCTL_BOD25_EN_Pos) /*!< SYS_T::BODCTL: BOD25_EN Mask */
+
+#define SYS_BODCTL_BOD17_RST_EN_Pos (4) /*!< SYS_T::BODCTL: BOD17_RST_EN Position */
+#define SYS_BODCTL_BOD17_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD17_RST_EN_Pos) /*!< SYS_T::BODCTL: BOD17_RST_EN Mask */
+
+#define SYS_BODCTL_BOD20_RST_EN_Pos (5) /*!< SYS_T::BODCTL: BOD20_RST_EN Position */
+#define SYS_BODCTL_BOD20_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD20_RST_EN_Pos) /*!< SYS_T::BODCTL: BOD20_RST_EN Mask */
+
+#define SYS_BODCTL_BOD25_RST_EN_Pos (6) /*!< SYS_T::BODCTL: BOD25_RST_EN Position */
+#define SYS_BODCTL_BOD25_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD25_RST_EN_Pos) /*!< SYS_T::BODCTL: BOD25_RST_EN Mask */
+
+#define SYS_BODCTL_BOD17_INT_EN_Pos (8) /*!< SYS_T::BODCTL: BOD17_INT_EN Position */
+#define SYS_BODCTL_BOD17_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD17_INT_EN_Pos) /*!< SYS_T::BODCTL: BOD17_INT_EN Mask */
+
+#define SYS_BODCTL_BOD20_INT_EN_Pos (9) /*!< SYS_T::BODCTL: BOD20_INT_EN Position */
+#define SYS_BODCTL_BOD20_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD20_INT_EN_Pos) /*!< SYS_T::BODCTL: BOD20_INT_EN Mask */
+
+#define SYS_BODCTL_BOD25_INT_EN_Pos (10) /*!< SYS_T::BODCTL: BOD25_INT_EN Position */
+#define SYS_BODCTL_BOD25_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD25_INT_EN_Pos) /*!< SYS_T::BODCTL: BOD25_INT_EN Mask */
+
+#define SYS_BODSTS_BOD_INT_Pos (0) /*!< SYS_T::BODSTS: BOD_INT Position */
+#define SYS_BODSTS_BOD_INT_Msk (0x1ul << SYS_BODSTS_BOD_INT_Pos) /*!< SYS_T::BODSTS: BOD_INT Mask */
+
+#define SYS_BODSTS_BOD17_drop_Pos (1) /*!< SYS_T::BODSTS: BOD17_drop Position */
+#define SYS_BODSTS_BOD17_drop_Msk (0x1ul << SYS_BODSTS_BOD17_drop_Pos) /*!< SYS_T::BODSTS: BOD17_drop Mask */
+
+#define SYS_BODSTS_BOD20_drop_Pos (2) /*!< SYS_T::BODSTS: BOD20_drop Position */
+#define SYS_BODSTS_BOD20_drop_Msk (0x1ul << SYS_BODSTS_BOD20_drop_Pos) /*!< SYS_T::BODSTS: BOD20_drop Mask */
+
+#define SYS_BODSTS_BOD25_drop_Pos (3) /*!< SYS_T::BODSTS: BOD25_drop Position */
+#define SYS_BODSTS_BOD25_drop_Msk (0x1ul << SYS_BODSTS_BOD25_drop_Pos) /*!< SYS_T::BODSTS: BOD25_drop Mask */
+
+#define SYS_BODSTS_BOD17_rise_Pos (4) /*!< SYS_T::BODSTS: BOD17_rise Position */
+#define SYS_BODSTS_BOD17_rise_Msk (0x1ul << SYS_BODSTS_BOD17_rise_Pos) /*!< SYS_T::BODSTS: BOD17_rise Mask */
+
+#define SYS_BODSTS_BOD20_rise_Pos (5) /*!< SYS_T::BODSTS: BOD20_rise Position */
+#define SYS_BODSTS_BOD20_rise_Msk (0x1ul << SYS_BODSTS_BOD20_rise_Pos) /*!< SYS_T::BODSTS: BOD20_rise Mask */
+
+#define SYS_BODSTS_BOD25_rise_Pos (6) /*!< SYS_T::BODSTS: BOD25_rise Position */
+#define SYS_BODSTS_BOD25_rise_Msk (0x1ul << SYS_BODSTS_BOD25_rise_Pos) /*!< SYS_T::BODSTS: BOD25_rise Mask */
+
+#define SYS_VREFCTL_BGP_EN_Pos (0) /*!< SYS_T::VREFCTL: BGP_EN Position */
+#define SYS_VREFCTL_BGP_EN_Msk (0x1ul << SYS_VREFCTL_BGP_EN_Pos) /*!< SYS_T::VREFCTL: BGP_EN Mask */
+
+#define SYS_VREFCTL_REG_EN_Pos (1) /*!< SYS_T::VREFCTL: REG_EN Position */
+#define SYS_VREFCTL_REG_EN_Msk (0x1ul << SYS_VREFCTL_REG_EN_Pos) /*!< SYS_T::VREFCTL: REG_EN Mask */
+
+#define SYS_VREFCTL_SEL25_Pos (2) /*!< SYS_T::VREFCTL: SEL25 Position */
+#define SYS_VREFCTL_SEL25_Msk (0x1ul << SYS_VREFCTL_SEL25_Pos) /*!< SYS_T::VREFCTL: SEL25 Mask */
+
+#define SYS_VREFCTL_EXT_MODE_Pos (3) /*!< SYS_T::VREFCTL: EXT_MODE Position */
+#define SYS_VREFCTL_EXT_MODE_Msk (0x1ul << SYS_VREFCTL_EXT_MODE_Pos) /*!< SYS_T::VREFCTL: EXT_MODE Mask */
+
+#define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0) /*!< SYS_T::IRCTRIMCTL: TRIM_SEL Position */
+#define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!< SYS_T::IRCTRIMCTL: TRIM_SEL Mask */
+
+#define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4) /*!< SYS_T::IRCTRIMCTL: TRIM_LOOP Position */
+#define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!< SYS_T::IRCTRIMCTL: TRIM_LOOP Mask */
+
+#define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos (6) /*!< SYS_T::IRCTRIMCTL: TRIM_RETRY_CNT Position*/
+#define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!< SYS_T::IRCTRIMCTL: TRIM_RETRY_CNT Mask */
+
+#define SYS_IRCTRIMCTL_ERR_STOP_Pos (8) /*!< SYS_T::IRCTRIMCTL: ERR_STOP Position */
+#define SYS_IRCTRIMCTL_ERR_STOP_Msk (0x1ul << SYS_IRCTRIMCTL_ERR_STOP_Pos) /*!< SYS_T::IRCTRIMCTL: ERR_STOP Mask */
+
+#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1) /*!< SYS_T::IRCTRIMIEN: TRIM_FAIL_IEN Position */
+#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos) /*!< SYS_T::IRCTRIMIEN: TRIM_FAIL_IEN Mask */
+
+#define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2) /*!< SYS_T::IRCTRIMIEN: 32K_ERR_IEN Position */
+#define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos) /*!< SYS_T::IRCTRIMIEN: 32K_ERR_IEN Mask */
+
+#define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0) /*!< SYS_T::IRCTRIMINT: FREQ_LOCK Position */
+#define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos) /*!< SYS_T::IRCTRIMINT: FREQ_LOCK Mask */
+
+#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1) /*!< SYS_T::IRCTRIMINT: TRIM_FAIL_INT Position */
+#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos) /*!< SYS_T::IRCTRIMINT: TRIM_FAIL_INT Mask */
+
+#define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2) /*!< SYS_T::IRCTRIMINT: 32K_ERR_INT Position */
+#define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos) /*!< SYS_T::IRCTRIMINT: 32K_ERR_INT Mask */
+
+#define SYS_RegLockAddr_RegUnLock_Pos (0) /*!< SYS_T::RegLockAddr: RegUnLock Position */
+#define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) /*!< SYS_T::RegLockAddr: RegUnLock Mask */
+
+/**@}*/ /* SYS_CONST */
+/**@}*/ /* end of SYS register group */
+
+
+/*---------------------- General Purpose Input/Output Controller -------------------------*/
+/**
+ @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+ Memory Mapped Structure for GPIO Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * PMD
+ * ===================================================================================================
+ * Offset: 0x00 GPIO Port Pin I/O Mode Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |PMD0 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[3:2] |PMD1 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[5:4] |PMD2 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[7:6] |PMD3 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[9:8] |PMD4 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[11:10] |PMD5 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[13:12] |PMD6 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[15:14] |PMD7 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[17:16] |PMD8 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[19:18] |PMD9 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[21:20] |PMD10 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[23:22] |PMD11 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[25:24] |PMD12 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[27:26] |PMD13 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[29:28] |PMD14 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ * |[31:30] |PMD15 |GPIO Port [X] Pin [N] Mode Control
+ * | | |Determine the I/O type of GPIO port [x] pin [n]
+ * | | |00 = GPIO port [x] pin [n] is in INPUT mode.
+ * | | |01 = GPIO port [x] pin [n] is in OUTPUT mode.
+ * | | |10 = GPIO port [x] pin [n] is in Open-Drain mode.
+ * | | |11 = Reserved.
+ * | | |Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
+ */
+ __IO uint32_t PMD;
+
+ /**
+ * OFFD
+ * ===================================================================================================
+ * Offset: 0x04 GPIO Port Pin OFF Digital Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |OFFD |GPIO Port [X] Pin [N] Digital Input Path Disable
+ * | | |Determine if the digital input path of GPIO port [x] pin [n] is disabled.
+ * | | |0 = Digital input path of GPIO port [x] pin [n] Enabled.
+ * | | |1 = Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low).
+ * | | |Note: For GPIOF_OFFD, bits [31:22] are reserved.
+ */
+ __IO uint32_t OFFD;
+
+ /**
+ * DOUT
+ * ===================================================================================================
+ * Offset: 0x08 GPIO Port Data Output Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DOUT |GPIO Port [X] Pin [N] Output Value
+ * | | |Each of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode
+ * | | |0 = GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set.
+ * | | |1 = GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set.
+ * | | |Note: For GPIOF_DOUT, bits [15:6] are reserved.
+ */
+ __IO uint32_t DOUT;
+
+ /**
+ * DMASK
+ * ===================================================================================================
+ * Offset: 0x0C GPIO Port Data Output Write Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DMASK |GPIO Port [X] Pin [N] Data Output Write Mask
+ * | | |These bits are used to protect the corresponding register of GPIOx_DOUT bit [n].
+ * | | |When set the DMASK[n] to "1", the corresponding DOUT[n] bit is protected.
+ * | | |The write signal is masked, write data to the protect bit is ignored.
+ * | | |0 = The corresponding GPIO_DOUT bit [n] can be updated.
+ * | | |1 = The corresponding GPIO_DOUT bit [n] is protected.
+ * | | |Note: For GPIOF_DMASK, bits [15:6] are reserved.
+ * | | |Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT.
+ * | | |If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
+ */
+ __IO uint32_t DMASK;
+
+ /**
+ * PIN
+ * ===================================================================================================
+ * Offset: 0x10 GPIO Port Pin Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PIN |GPIO Port [X] Pin [N] Value
+ * | | |The value read from each of these bit reflects the actual status of the respective GPI/O pin
+ * | | |Note: For GPIOF_PIN, bits [15:6] are reserved.
+ */
+ __I uint32_t PIN;
+
+ /**
+ * DBEN
+ * ===================================================================================================
+ * Offset: 0x14 GPIO Port De-bounce Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DBEN |GPIO Port [X] Pin [N] Input Signal De-Bounce Enable
+ * | | |DBEN[n] used to enable the de-bounce function for each corresponding bit.
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
+ * | | |DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt
+ * | | |0 = The GPIO port [x] Pin [n] input signal de-bounce function is disabled.
+ * | | |1 = The GPIO port [x] Pin [n] input signal de-bounce function is enabled.
+ * | | |The de-bounce function is valid for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note: For GPIOF_DBEN, bits [15:6] are reserved.
+ */
+ __IO uint32_t DBEN;
+
+ /**
+ * IMD
+ * ===================================================================================================
+ * Offset: 0x18 GPIO Port Interrupt Mode Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IMD |GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control
+ * | | |IMD[n] used to control the interrupt is by level trigger or by edge trigger.
+ * | | |If the interrupt is by edge trigger, the trigger source is control de-bounce.
+ * | | |If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt.
+ * | | |0 = Edge trigger interrupt.
+ * | | |1 = Level trigger interrupt.
+ * | | |If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER.
+ * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note: For GPIOF_IMD, bits [15:6] are reserved.
+ */
+ __IO uint32_t IMD;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x1C GPIO Port Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FIER0 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[1] |FIER1 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[2] |FIER2 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[3] |FIER3 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[4] |FIER4 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[5] |FIER5 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[6] |FIER6 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[7] |FIER7 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[8] |FIER8 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[9] |FIER9 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[10] |FIER10 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[11] |FIER11 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[12] |FIER12 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[13] |FIER13 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[14] |FIER14 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[15] |FIER15 |GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low
+ * | | |FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the FIER[n] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.
+ * | | |1 = PIN[n] state low-level or high-to-low change interrupt Enabled.
+ * | | |0 = PIN[n] state low-level or high-to-low change interrupt Disabled.
+ * | | |Note: For GPIOF_IER, bits [15:6] are reserved.
+ * |[16] |RIER0 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[17] |RIER1 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[18] |RIER2 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[19] |RIER3 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[20] |RIER4 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[21] |RIER5 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[22] |RIER6 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[23] |RIER7 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[24] |RIER8 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[25] |RIER9 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[26] |RIER10 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[27] |RIER11 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[28] |RIER12 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[29] |RIER13 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[30] |RIER14 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ * |[31] |RIER15 |GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High
+ * | | |RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x].
+ * | | |Set bit "1" also enable the pin wake-up function.
+ * | | |When set the RIER[x] bit "1":
+ * | | |If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt.
+ * | | |If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt.
+ * | | |1 = PIN[x] level-high or low-to-high interrupt Enabled.
+ * | | |0 = PIN[x] level-high or low-to-high interrupt Disabled.
+ * | | |Note: For GPIOF_IE, bits [31:22] are reserved.
+ */
+ __IO uint32_t IER;
+
+ /**
+ * ISRC
+ * ===================================================================================================
+ * Offset: 0x20 GPIO Port Interrupt Trigger Source Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |ISRC |GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator
+ * | | |Read :
+ * | | |1 = Port x[n] generate an interrupt.
+ * | | |0 = No interrupt at Port x[n].
+ * | | |Write:
+ * | | |1 = Clear the correspond pending interrupt.
+ * | | |0 = No action.
+ * | | |Note: For GPIOF_ISRC, bits [15:6] are reserved.
+ */
+ __IO uint32_t ISRC;
+
+ /**
+ * PUEN
+ * ===================================================================================================
+ * Offset: 0x24 GPIO Port
+ Pull-Up Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PUEN |GPIO Port [X] Pin [N] Pull-Up Enable Register
+ * | | |Read :
+ * | | |1 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled.
+ * | | |0 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled.
+ * | | |Note: For GPIOF_PUEN, bits [15:6] are reserved.
+ */
+ __IO uint32_t PUEN;
+
+} GPIO_T;
+
+
+typedef struct {
+ /**
+ * DBNCECON
+ * ===================================================================================================
+ * Offset: 0x180 De-bounce Cycle Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PUEN |De-Bounce Sampling Cycle Selection
+ * | | |0000 = Sample interrupt input once per 1 clock.
+ * | | |0001 = Sample interrupt input once per 2 clock.
+ * | | |0010 = Sample interrupt input once per 4 clock.
+ * | | |0011 = Sample interrupt input once per 8 clock.
+ * | | |0100 = Sample interrupt input once per 16 clock.
+ * | | |0101 = Sample interrupt input once per 32 clock.
+ * | | |0110 = Sample interrupt input once per 64 clock.
+ * | | |0111 = Sample interrupt input once per 128 clock.
+ * | | |1000 = Sample interrupt input once per 256 clock.
+ * | | |1001 = Sample interrupt input once per 512 clock.
+ * | | |1010 = Sample interrupt input once per 1024 clock.
+ * | | |1011 = Sample interrupt input once per 2048 clock.
+ * | | |1100 = Sample interrupt input once per 4096 clock.
+ * | | |1101 = Sample interrupt input once per 8192 clock.
+ * | | |1110 = Sample interrupt input once per 16384 clock.
+ * | | |1111 = Sample interrupt input once per 32768 clock.
+ * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
+ * | | |0 = De-bounce counter Clock Source is the HCLK.
+ * | | |1 = De-bounce counter Clock Source is the internal 10 kHz clock.
+ * |[5] |DBCLK_ON |De-Bounce Clock Enable
+ * | | |This bit controls if the de-bounce clock is enabled.
+ * | | |However, if GPI/O pin's interrupt is enabled, the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is.
+ * | | |If CPU is in sleep mode, this bit didn't take effect.
+ * | | |And only the GPI/O pin with interrupt enable could get de-bounce clock.
+ * | | |0 = De-bounce clock Disabled.
+ * | | |1 = De-bounce clock Enabled.
+ */
+ __IO uint32_t DBNCECON;
+} GP_DB_T;
+
+/**
+ @addtogroup GPIO_CONST GPIO Bit Field Definition
+ Constant Definitions for GPIO Controller
+@{ */
+
+#define GP_PMD_PMD0_Pos (0) /*!< GPIO_T::PMD: PMD0 Position */
+#define GP_PMD_PMD0_Msk (0x3ul << GP_PMD_PMD0_Pos) /*!< GPIO_T::PMD: PMD0 Mask */
+
+#define GP_PMD_PMD1_Pos (2) /*!< GPIO_T::PMD: PMD1 Position */
+#define GP_PMD_PMD1_Msk (0x3ul << GP_PMD_PMD1_Pos) /*!< GPIO_T::PMD: PMD1 Mask */
+
+#define GP_PMD_PMD2_Pos (4) /*!< GPIO_T::PMD: PMD2 Position */
+#define GP_PMD_PMD2_Msk (0x3ul << GP_PMD_PMD2_Pos) /*!< GPIO_T::PMD: PMD2 Mask */
+
+#define GP_PMD_PMD3_Pos (6) /*!< GPIO_T::PMD: PMD3 Position */
+#define GP_PMD_PMD3_Msk (0x3ul << GP_PMD_PMD3_Pos) /*!< GPIO_T::PMD: PMD3 Mask */
+
+#define GP_PMD_PMD4_Pos (8) /*!< GPIO_T::PMD: PMD4 Position */
+#define GP_PMD_PMD4_Msk (0x3ul << GP_PMD_PMD4_Pos) /*!< GPIO_T::PMD: PMD4 Mask */
+
+#define GP_PMD_PMD5_Pos (10) /*!< GPIO_T::PMD: PMD5 Position */
+#define GP_PMD_PMD5_Msk (0x3ul << GP_PMD_PMD5_Pos) /*!< GPIO_T::PMD: PMD5 Mask */
+
+#define GP_PMD_PMD6_Pos (12) /*!< GPIO_T::PMD: PMD6 Position */
+#define GP_PMD_PMD6_Msk (0x3ul << GP_PMD_PMD6_Pos) /*!< GPIO_T::PMD: PMD6 Mask */
+
+#define GP_PMD_PMD7_Pos (14) /*!< GPIO_T::PMD: PMD7 Position */
+#define GP_PMD_PMD7_Msk (0x3ul << GP_PMD_PMD7_Pos) /*!< GPIO_T::PMD: PMD7 Mask */
+
+#define GP_PMD_PMD8_Pos (16) /*!< GPIO_T::PMD: PMD8 Position */
+#define GP_PMD_PMD8_Msk (0x3ul << GP_PMD_PMD8_Pos) /*!< GPIO_T::PMD: PMD8 Mask */
+
+#define GP_PMD_PMD9_Pos (18) /*!< GPIO_T::PMD: PMD9 Position */
+#define GP_PMD_PMD9_Msk (0x3ul << GP_PMD_PMD9_Pos) /*!< GPIO_T::PMD: PMD9 Mask */
+
+#define GP_PMD_PMD10_Pos (20) /*!< GPIO_T::PMD: PMD10 Position */
+#define GP_PMD_PMD10_Msk (0x3ul << GP_PMD_PMD10_Pos) /*!< GPIO_T::PMD: PMD10 Mask */
+
+#define GP_PMD_PMD11_Pos (22) /*!< GPIO_T::PMD: PMD11 Position */
+#define GP_PMD_PMD11_Msk (0x3ul << GP_PMD_PMD11_Pos) /*!< GPIO_T::PMD: PMD11 Mask */
+
+#define GP_PMD_PMD12_Pos (24) /*!< GPIO_T::PMD: PMD12 Position */
+#define GP_PMD_PMD12_Msk (0x3ul << GP_PMD_PMD12_Pos) /*!< GPIO_T::PMD: PMD12 Mask */
+
+#define GP_PMD_PMD13_Pos (26) /*!< GPIO_T::PMD: PMD13 Position */
+#define GP_PMD_PMD13_Msk (0x3ul << GP_PMD_PMD13_Pos) /*!< GPIO_T::PMD: PMD13 Mask */
+
+#define GP_PMD_PMD14_Pos (28) /*!< GPIO_T::PMD: PMD14 Position */
+#define GP_PMD_PMD14_Msk (0x3ul << GP_PMD_PMD14_Pos) /*!< GPIO_T::PMD: PMD14 Mask */
+
+#define GP_PMD_PMD15_Pos (30) /*!< GPIO_T::PMD: PMD15 Position */
+#define GP_PMD_PMD15_Msk (0x3ul << GP_PMD_PMD15_Pos) /*!< GPIO_T::PMD: PMD15 Mask */
+
+#define GP_OFFD_OFFD_Pos (16) /*!< GPIO_T::OFFD: OFFD Position */
+#define GP_OFFD_OFFD_Msk (0xfffful << GP_OFFD_OFFD_Pos) /*!< GPIO_T::OFFD: OFFD Mask */
+
+#define GP_DOUT_DOUT_Pos (0) /*!< GPIO_T::DOUT: DOUT Position */
+#define GP_DOUT_DOUT_Msk (0xfffful << GP_DOUT_DOUT_Pos) /*!< GPIO_T::DOUT: DOUT Mask */
+
+#define GP_DMASK_DMASK_Pos (0) /*!< GPIO_T::DMASK: DMASK Position */
+#define GP_DMASK_DMASK_Msk (0xfffful << GP_DMASK_DMASK_Pos) /*!< GPIO_T::DMASK: DMASK Mask */
+
+#define GP_PIN_PIN_Pos (0) /*!< GPIO_T::PIN: PIN Position */
+#define GP_PIN_PIN_Msk (0xfffful << GP_PIN_PIN_Pos) /*!< GPIO_T::PIN: PIN Mask */
+
+#define GP_DBEN_DBEN_Pos (0) /*!< GPIO_T::DBEN: DBEN Position */
+#define GP_DBEN_DBEN_Msk (0xfffful << GP_DBEN_DBEN_Pos) /*!< GPIO_T::DBEN: DBEN Mask */
+
+#define GP_IMD_IMD_Pos (0) /*!< GPIO_T::IMD: IMD Position */
+#define GP_IMD_IMD_Msk (0xfffful << GP_IMD_IMD_Pos) /*!< GPIO_T::IMD: IMD Mask */
+
+#define GP_IER_FIER0_Pos (0) /*!< GPIO_T::IER: FIER0 Position */
+#define GP_IER_FIER0_Msk (0x1ul << GP_IER_FIER0_Pos) /*!< GPIO_T::IER: FIER0 Mask */
+
+#define GP_IER_FIER1_Pos (1) /*!< GPIO_T::IER: FIER1 Position */
+#define GP_IER_FIER1_Msk (0x1ul << GP_IER_FIER1_Pos) /*!< GPIO_T::IER: FIER1 Mask */
+
+#define GP_IER_FIER2_Pos (2) /*!< GPIO_T::IER: FIER2 Position */
+#define GP_IER_FIER2_Msk (0x1ul << GP_IER_FIER2_Pos) /*!< GPIO_T::IER: FIER2 Mask */
+
+#define GP_IER_FIER3_Pos (3) /*!< GPIO_T::IER: FIER3 Position */
+#define GP_IER_FIER3_Msk (0x1ul << GP_IER_FIER3_Pos) /*!< GPIO_T::IER: FIER3 Mask */
+
+#define GP_IER_FIER4_Pos (4) /*!< GPIO_T::IER: FIER4 Position */
+#define GP_IER_FIER4_Msk (0x1ul << GP_IER_FIER4_Pos) /*!< GPIO_T::IER: FIER4 Mask */
+
+#define GP_IER_FIER5_Pos (5) /*!< GPIO_T::IER: FIER5 Position */
+#define GP_IER_FIER5_Msk (0x1ul << GP_IER_FIER5_Pos) /*!< GPIO_T::IER: FIER5 Mask */
+
+#define GP_IER_FIER6_Pos (6) /*!< GPIO_T::IER: FIER6 Position */
+#define GP_IER_FIER6_Msk (0x1ul << GP_IER_FIER6_Pos) /*!< GPIO_T::IER: FIER6 Mask */
+
+#define GP_IER_FIER7_Pos (7) /*!< GPIO_T::IER: FIER7 Position */
+#define GP_IER_FIER7_Msk (0x1ul << GP_IER_FIER7_Pos) /*!< GPIO_T::IER: FIER7 Mask */
+
+#define GP_IER_FIER8_Pos (8) /*!< GPIO_T::IER: FIER8 Position */
+#define GP_IER_FIER8_Msk (0x1ul << GP_IER_FIER8_Pos) /*!< GPIO_T::IER: FIER8 Mask */
+
+#define GP_IER_FIER9_Pos (9) /*!< GPIO_T::IER: FIER9 Position */
+#define GP_IER_FIER9_Msk (0x1ul << GP_IER_FIER9_Pos) /*!< GPIO_T::IER: FIER9 Mask */
+
+#define GP_IER_FIER10_Pos (10) /*!< GPIO_T::IER: FIER10 Position */
+#define GP_IER_FIER10_Msk (0x1ul << GP_IER_FIER10_Pos) /*!< GPIO_T::IER: FIER10 Mask */
+
+#define GP_IER_FIER11_Pos (11) /*!< GPIO_T::IER: FIER11 Position */
+#define GP_IER_FIER11_Msk (0x1ul << GP_IER_FIER11_Pos) /*!< GPIO_T::IER: FIER11 Mask */
+
+#define GP_IER_FIER12_Pos (12) /*!< GPIO_T::IER: FIER12 Position */
+#define GP_IER_FIER12_Msk (0x1ul << GP_IER_FIER12_Pos) /*!< GPIO_T::IER: FIER12 Mask */
+
+#define GP_IER_FIER13_Pos (13) /*!< GPIO_T::IER: FIER13 Position */
+#define GP_IER_FIER13_Msk (0x1ul << GP_IER_FIER13_Pos) /*!< GPIO_T::IER: FIER13 Mask */
+
+#define GP_IER_FIER14_Pos (14) /*!< GPIO_T::IER: FIER14 Position */
+#define GP_IER_FIER14_Msk (0x1ul << GP_IER_FIER14_Pos) /*!< GPIO_T::IER: FIER14 Mask */
+
+#define GP_IER_FIER15_Pos (15) /*!< GPIO_T::IER: FIER15 Position */
+#define GP_IER_FIER15_Msk (0x1ul << GP_IER_FIER15_Pos) /*!< GPIO_T::IER: FIER15 Mask */
+
+#define GP_IER_RIER0_Pos (16) /*!< GPIO_T::IER: RIER0 Position */
+#define GP_IER_RIER0_Msk (0x1ul << GP_IER_RIER0_Pos) /*!< GPIO_T::IER: RIER0 Mask */
+
+#define GP_IER_RIER1_Pos (17) /*!< GPIO_T::IER: RIER1 Position */
+#define GP_IER_RIER1_Msk (0x1ul << GP_IER_RIER1_Pos) /*!< GPIO_T::IER: RIER1 Mask */
+
+#define GP_IER_RIER2_Pos (18) /*!< GPIO_T::IER: RIER2 Position */
+#define GP_IER_RIER2_Msk (0x1ul << GP_IER_RIER2_Pos) /*!< GPIO_T::IER: RIER2 Mask */
+
+#define GP_IER_RIER3_Pos (19) /*!< GPIO_T::IER: RIER3 Position */
+#define GP_IER_RIER3_Msk (0x1ul << GP_IER_RIER3_Pos) /*!< GPIO_T::IER: RIER3 Mask */
+
+#define GP_IER_RIER4_Pos (20) /*!< GPIO_T::IER: RIER4 Position */
+#define GP_IER_RIER4_Msk (0x1ul << GP_IER_RIER4_Pos) /*!< GPIO_T::IER: RIER4 Mask */
+
+#define GP_IER_RIER5_Pos (21) /*!< GPIO_T::IER: RIER5 Position */
+#define GP_IER_RIER5_Msk (0x1ul << GP_IER_RIER5_Pos) /*!< GPIO_T::IER: RIER5 Mask */
+
+#define GP_IER_RIER6_Pos (22) /*!< GPIO_T::IER: RIER6 Position */
+#define GP_IER_RIER6_Msk (0x1ul << GP_IER_RIER6_Pos) /*!< GPIO_T::IER: RIER6 Mask */
+
+#define GP_IER_RIER7_Pos (23) /*!< GPIO_T::IER: RIER7 Position */
+#define GP_IER_RIER7_Msk (0x1ul << GP_IER_RIER7_Pos) /*!< GPIO_T::IER: RIER7 Mask */
+
+#define GP_IER_RIER8_Pos (24) /*!< GPIO_T::IER: RIER8 Position */
+#define GP_IER_RIER8_Msk (0x1ul << GP_IER_RIER8_Pos) /*!< GPIO_T::IER: RIER8 Mask */
+
+#define GP_IER_RIER9_Pos (25) /*!< GPIO_T::IER: RIER9 Position */
+#define GP_IER_RIER9_Msk (0x1ul << GP_IER_RIER9_Pos) /*!< GPIO_T::IER: RIER9 Mask */
+
+#define GP_IER_RIER10_Pos (26) /*!< GPIO_T::IER: RIER10 Position */
+#define GP_IER_RIER10_Msk (0x1ul << GP_IER_RIER10_Pos) /*!< GPIO_T::IER: RIER10 Mask */
+
+#define GP_IER_RIER11_Pos (27) /*!< GPIO_T::IER: RIER11 Position */
+#define GP_IER_RIER11_Msk (0x1ul << GP_IER_RIER11_Pos) /*!< GPIO_T::IER: RIER11 Mask */
+
+#define GP_IER_RIER12_Pos (28) /*!< GPIO_T::IER: RIER12 Position */
+#define GP_IER_RIER12_Msk (0x1ul << GP_IER_RIER12_Pos) /*!< GPIO_T::IER: RIER12 Mask */
+
+#define GP_IER_RIER13_Pos (29) /*!< GPIO_T::IER: RIER13 Position */
+#define GP_IER_RIER13_Msk (0x1ul << GP_IER_RIER13_Pos) /*!< GPIO_T::IER: RIER13 Mask */
+
+#define GP_IER_RIER14_Pos (30) /*!< GPIO_T::IER: RIER14 Position */
+#define GP_IER_RIER14_Msk (0x1ul << GP_IER_RIER14_Pos) /*!< GPIO_T::IER: RIER14 Mask */
+
+#define GP_IER_RIER15_Pos (31) /*!< GPIO_T::IER: RIER15 Position */
+#define GP_IER_RIER15_Msk (0x1ul << GP_IER_RIER15_Pos) /*!< GPIO_T::IER: RIER15 Mask */
+
+#define GP_ISRC_ISRC_Pos (0) /*!< GPIO_T::ISRC: ISRC Position */
+#define GP_ISRC_ISRC_Msk (0xfffful << GP_ISRC_ISRC_Pos) /*!< GPIO_T::ISRC: ISRC Mask */
+
+#define GP_PUEN_PUEN_Pos (0) /*!< GPIO_T::PUEN: PUEN Position */
+#define GP_PUEN_PUEN_Msk (0xfffful << GP_PUEN_PUEN_Pos) /*!< GPIO_T::PUEN: PUEN Mask */
+/**@}*/ /* GPIO_CONST */
+
+/**
+ @addtogroup GP_DB_CONST GP_DB Bit Field Definition
+ Constant Definitions for GP_DB Controller
+@{ */
+#define GP_DBNCECON_DBCLKSEL_Pos (0) /*!< GP_DB_T::DBNCECON: DBCLKSEL Position */
+#define GP_DBNCECON_DBCLKSEL_Msk (0xful << GP_DBNCECON_DBCLKSEL_Pos) /*!< GP_DB_T::DBNCECON: DBCLKSEL Mask */
+
+#define GP_DBNCECON_DBCLKSRC_Pos (4) /*!< GP_DB_T::DBNCECON: DBCLKSRC Position */
+#define GP_DBNCECON_DBCLKSRC_Msk (0x1ul << GP_DBNCECON_DBCLKSRC_Pos) /*!< GP_DB_T::DBNCECON: DBCLKSRC Mask */
+
+#define GP_DBNCECON_DBCLK_ON_Pos (5) /*!< GP_DB_T::DBNCECON: DBCLK_ON Position */
+#define GP_DBNCECON_DBCLK_ON_Msk (0x1ul << GP_DBNCECON_DBCLK_ON_Pos) /*!< GP_DB_T::DBNCECON: DBCLK_ON Mask */
+
+
+/**@}*/ /* GP_DB_CONST */
+/**@}*/ /* end of GP register group */
+
+
+/*---------------------- Inter-IC Bus Controller -------------------------*/
+/**
+ @addtogroup I2C Inter-IC Bus Controller(I2C)
+ Memory Mapped Structure for I2C Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * CON
+ * ===================================================================================================
+ * Offset: 0x00 I2C Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IPEN |I2C Function Enable
+ * | | |When this bit is set to 1, the I2C serial function is enabled.
+ * | | |0 = I2C function Disabled.
+ * | | |1 = I2C function Enabled.
+ * |[1] |ACK |Assert Acknowledge Control Bit
+ * | | |0 =: When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse.
+ * | | |1 = When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when.
+ * | | |a. A slave is acknowledging the address sent from master
+ * | | |b. The receiver devices are acknowledging the data sent by transmitter.
+ * |[2] |STOP |I2C STOP Control Bit
+ * | | |In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.
+ * | | |In Slave mode, set this bit to 1 to reset the controller to the defined "not addressed" Slave mode.
+ * | | |This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
+ * | | |0 = Will be cleared by hardware automatically if a STOP condition is detected.
+ * | | |1 = Sends a STOP condition to bus in Master mode or reset the controller to "not addressed" in Slave mode.
+ * |[3] |START |I2C START Command
+ * | | |Setting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.
+ * | | |0 = After START or repeat START is active.
+ * | | |1 = Sends a START or repeat START condition to bus.
+ * |[4] |I2C_STS |I2C Status
+ * | | |When a new state is present in the I2CSTATUS register, this bit will be set automatically, and if the INTEN bit is set, the I2C interrupt is requested.
+ * | | |It must be cleared by software by writing one to this bit and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled.
+ * | | |0 = I2C's Status disabled and the I2C protocol function will go ahead.
+ * | | |1 = I2C's Status active.
+ * |[7] |INTEN |Interrupt Enable
+ * | | |0 = I2C interrupt Disabled.
+ * | | |1 = I2C interrupt Enabled.
+ */
+ __IO uint32_t CON;
+
+ /**
+ * INTSTS
+ * ===================================================================================================
+ * Offset: 0x04 I2C Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INTSTS |I2C STATUS's Interrupt Status
+ * | | |When a new state is present in the I2CSTATUS register, this bit will be set automatically, and if INTEN bit is set, the I2C interrupt is requested.
+ * | | |Software can write 1 to cleat this bit.
+ * |[1] |TIF |Time-Out Status
+ * | | |0 = No Time-out flag. Software can cleat this flag.
+ * | | |1 = Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set.
+ */
+ __IO uint32_t INTSTS;
+
+ /**
+ * STATUS
+ * ===================================================================================================
+ * Offset: 0x08 I2C Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |STATUS |I2C Status Register
+ * | | |This is a read only register.
+ * | | |The three least significant bits are always 0.
+ * | | |The five most significant bits contain the status code.
+ * | | |When each of these states is entered, a status interrupt and I2C_STS are requested (I2C_STS = 1 and STAINTSTS = 1).
+ * | | |A valid status code is present in STATUS one machine cycle after I2C_STS is set by hardware and is still present one machine cycle after I2C_STS has been reset by software.
+ * | | |In addition, states 00H stands for a 'Bus Error'.
+ * | | |A 'Bus Error' occurs when a START or STOP condition is present at an illegal position in the formation frame.
+ * | | |Example of illegal position: a data byte or an acknowledge bit is present during the serial transfer of an address byte.
+ * | | |To recover I2C from bus error, STOP should be set and I2C_STS should be cleared to enter not addressed Slave mode.
+ * | | |Then clear STOP to release the bus and to wait new communication.
+ * | | |I2C bus can not recognize stop condition during this action when bus error occurs.
+ */
+ __I uint32_t STATUS;
+
+ /**
+ * DIV
+ * ===================================================================================================
+ * Offset: 0x0C I2C clock divided Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CLK_DIV |I2C Clock Divider Control Register
+ * | | |The I2C clock rate bits: Data Baud Rate of I2C = PCLK /( 4 x ( CLK_DIV + 1)).
+ * | | |Note: the minimum value of CLK_DIV is 4.
+ */
+ __IO uint32_t DIV;
+
+ /**
+ * TOUT
+ * ===================================================================================================
+ * Offset: 0x10 I2C Time-out control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TOUTEN |Time-Out Counter Enable/Disable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |When set this bit to enable, the 14 bits time-out counter will start counting when STAINTSTS is cleared.
+ * | | |Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after STAINTSTS is cleared.
+ * |[1] |DIV4 |Time-Out Counter Input Clock Divider By 4
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |When this bit is set enabled, the Time-Out period is prolonging 4 times.
+ */
+ __IO uint32_t TOUT;
+
+ /**
+ * DATA
+ * ===================================================================================================
+ * Offset: 0x14 I2C DATA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DATA |I2C Data Register
+ * | | |The DATA contains a byte of serial data to be transmitted or a byte which has just been received.
+ * | | |The user can read from or write to this 8-bit I2CDATA register directly while it is not in the process of shifting a byte.
+ * | | |This occurs when the serial interrupt flag is set.
+ * | | |Data in DATA remains stable as long as I2C_STS bit is set.
+ * | | |While data is being shifted out, data on the bus is simultaneously being shifted in; The DATA always contains the last data byte present on the bus.
+ * | | |Thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in DATA.
+ * | | |DATA and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the device hardware and cannot be accessed by the user.
+ * | | |Serial data is shifted through the acknowledge bit into DATA on the rising edges of serial clock pulses on the SCL line.
+ * | | |When a byte has been shifted into DATA, the serial data is available in DATA, and the acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse.
+ */
+ __IO uint32_t DATA;
+
+ /**
+ * SADDR0
+ * ===================================================================================================
+ * Offset: 0x18 I2C Slave address Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GCALL |General Call Function
+ * | | |The I2C controller supports the "General Call" function.
+ * | | |If the GCALL bit is set, the controller will respond to General Call address (00H).
+ * | | |When GCALL bit is set, the controller is in Slave mode, it can receive the general call address by 00H after Master send general call address to the I2C bus, then it will follow status of GCALL mode.
+ * | | |If it is in Master mode, the ACK bit must be cleared when it will send general call address of 00H to I2C bus.
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[7:1] |SADDR |I2C Salve Address Register
+ * | | |The content of this register is irrelevant when the device is in Master mode.
+ * | | |In the Slave mode, the seven most significant bits must be loaded with the device's own address.
+ * | | |The device will react if either of the address is matched.
+ */
+ __IO uint32_t SADDR0;
+
+ /**
+ * SADDR1
+ * ===================================================================================================
+ * Offset: 0x1C I2C Slave address Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GCALL |General Call Function
+ * | | |The I2C controller supports the "General Call" function.
+ * | | |If the GCALL bit is set, the controller will respond to General Call address (00H).
+ * | | |When GCALL bit is set, the controller is in Slave mode, it can receive the general call address by 00H after Master send general call address to the I2C bus, then it will follow status of GCALL mode.
+ * | | |If it is in Master mode, the ACK bit must be cleared when it will send general call address of 00H to I2C bus.
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[7:1] |SADDR |I2C Salve Address Register
+ * | | |The content of this register is irrelevant when the device is in Master mode.
+ * | | |In the Slave mode, the seven most significant bits must be loaded with the device's own address.
+ * | | |The device will react if either of the address is matched.
+ */
+ __IO uint32_t SADDR1;
+ uint32_t RESERVE0[2];
+
+
+ /**
+ * SAMASK0
+ * ===================================================================================================
+ * Offset: 0x28 I2C Slave address Mask Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |SAMASK |I2C Slave Address Mask Register
+ * | | |0 = Mask disable (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask enable (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with two address mask registers.
+ * | | |When the bit in the address mask register is set to b'1, it means the received corresponding address bit is don't-care.
+ * | | |If the bit is set to b'0, that means the received corresponding register bit should be exact the same as address register.
+ */
+ __IO uint32_t SAMASK0;
+
+ /**
+ * SAMASK1
+ * ===================================================================================================
+ * Offset: 0x2C I2C Slave address Mask Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |SAMASK |I2C Slave Address Mask Register
+ * | | |0 = Mask disable (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask enable (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with two address mask registers.
+ * | | |When the bit in the address mask register is set to b'1, it means the received corresponding address bit is don't-care.
+ * | | |If the bit is set to b'0, that means the received corresponding register bit should be exact the same as address register.
+ */
+ __IO uint32_t SAMASK1;
+ uint32_t RESERVE1[4];
+
+
+ /**
+ * WKUPCON
+ * ===================================================================================================
+ * Offset: 0x40 I2C Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKUPEN |I2C Wake-Up Function Enable
+ * | | |0 = I2C wake-up function Disabled.
+ * | | |1 = I2C wake-up function Enabled.
+ */
+ __IO uint32_t WKUPCON;
+
+ /**
+ * WKUPSTS
+ * ===================================================================================================
+ * Offset: 0x44 I2C Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKUPIF |Wake-Up Interrupt Flag
+ * | | |0 = Wake-up flag inactive.
+ * | | |1 = Wake-up flag active.
+ * | | |Software can write 1 to clear this flag
+ */
+ __IO uint32_t WKUPSTS;
+
+} I2C_T;
+
+/**
+ @addtogroup I2C_CONST I2C Bit Field Definition
+ Constant Definitions for I2C Controller
+@{ */
+
+#define I2C_CON_IPEN_Pos (0) /*!< I2C_T::CON: IPEN Position */
+#define I2C_CON_IPEN_Msk (0x1ul << I2C_CON_IPEN_Pos) /*!< I2C_T::CON: IPEN Mask */
+
+#define I2C_CON_ACK_Pos (1) /*!< I2C_T::CON: ACK Position */
+#define I2C_CON_ACK_Msk (0x1ul << I2C_CON_ACK_Pos) /*!< I2C_T::CON: ACK Mask */
+
+#define I2C_CON_STOP_Pos (2) /*!< I2C_T::CON: STOP Position */
+#define I2C_CON_STOP_Msk (0x1ul << I2C_CON_STOP_Pos) /*!< I2C_T::CON: STOP Mask */
+
+#define I2C_CON_START_Pos (3) /*!< I2C_T::CON: START Position */
+#define I2C_CON_START_Msk (0x1ul << I2C_CON_START_Pos) /*!< I2C_T::CON: START Mask */
+
+#define I2C_CON_I2C_STS_Pos (4) /*!< I2C_T::CON: I2C_STS Position */
+#define I2C_CON_I2C_STS_Msk (0x1ul << I2C_CON_I2C_STS_Pos) /*!< I2C_T::CON: I2C_STS Mask */
+
+#define I2C_CON_INTEN_Pos (7) /*!< I2C_T::CON: INTEN Position */
+#define I2C_CON_INTEN_Msk (0x1ul << I2C_CON_INTEN_Pos) /*!< I2C_T::CON: INTEN Mask */
+
+#define I2C_INTSTS_INTSTS_Pos (0) /*!< I2C_T::INTSTS: INTSTS Position */
+#define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos) /*!< I2C_T::INTSTS: INTSTS Mask */
+
+#define I2C_INTSTS_TIF_Pos (1) /*!< I2C_T::INTSTS: TIF Position */
+#define I2C_INTSTS_TIF_Msk (0x1ul << I2C_INTSTS_TIF_Pos) /*!< I2C_T::INTSTS: TIF Mask */
+
+#define I2C_STATUS_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
+#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C_T::STATUS: STATUS Mask */
+
+#define I2C_DIV_CLK_DIV_Pos (0) /*!< I2C_T::DIV: CLK_DIV Position */
+#define I2C_DIV_CLK_DIV_Msk (0xfful << I2C_DIV_CLK_DIV_Pos) /*!< I2C_T::DIV: CLK_DIV Mask */
+
+#define I2C_TOUT_TOUTEN_Pos (0) /*!< I2C_T::TOUT: TOUTEN Position */
+#define I2C_TOUT_TOUTEN_Msk (0x1ul << I2C_TOUT_TOUTEN_Pos) /*!< I2C_T::TOUT: TOUTEN Mask */
+
+#define I2C_TOUT_DIV4_Pos (1) /*!< I2C_T::TOUT: DIV4 Position */
+#define I2C_TOUT_DIV4_Msk (0x1ul << I2C_TOUT_DIV4_Pos) /*!< I2C_T::TOUT: DIV4 Mask */
+
+#define I2C_DATA_DATA_Pos (0) /*!< I2C_T::DATA: DATA Position */
+#define I2C_DATA_DATA_Msk (0xfful << I2C_DATA_DATA_Pos) /*!< I2C_T::DATA: DATA Mask */
+
+#define I2C_SADDR0_GCALL_Pos (0) /*!< I2C_T::SADDR0: GCALL Position */
+#define I2C_SADDR0_GCALL_Msk (0x1ul << I2C_SADDR0_GCALL_Pos) /*!< I2C_T::SADDR0: GCALL Mask */
+
+#define I2C_SADDR0_SADDR_Pos (1) /*!< I2C_T::SADDR0: SADDR Position */
+#define I2C_SADDR0_SADDR_Msk (0x7ful << I2C_SADDR0_SADDR_Pos) /*!< I2C_T::SADDR0: SADDR Mask */
+
+#define I2C_SADDR1_GCALL_Pos (0) /*!< I2C_T::SADDR1: GCALL Position */
+#define I2C_SADDR1_GCALL_Msk (0x1ul << I2C_SADDR1_GCALL_Pos) /*!< I2C_T::SADDR1: GCALL Mask */
+
+#define I2C_SADDR1_SADDR_Pos (1) /*!< I2C_T::SADDR1: SADDR Position */
+#define I2C_SADDR1_SADDR_Msk (0x7ful << I2C_SADDR1_SADDR_Pos) /*!< I2C_T::SADDR1: SADDR Mask */
+
+#define I2C_SAMASK0_SAMASK_Pos (1) /*!< I2C_T::SAMASK0: SAMASK Position */
+#define I2C_SAMASK0_SAMASK_Msk (0x7ful << I2C_SAMASK0_SAMASK_Pos) /*!< I2C_T::SAMASK0: SAMASK Mask */
+
+#define I2C_SAMASK1_SAMASK_Pos (1) /*!< I2C_T::SAMASK1: SAMASK Position */
+#define I2C_SAMASK1_SAMASK_Msk (0x7ful << I2C_SAMASK1_SAMASK_Pos) /*!< I2C_T::SAMASK1: SAMASK Mask */
+
+#define I2C_WKUPCON_WKUPEN_Pos (0) /*!< I2C_T::WKUPCON: WKUPEN Position */
+#define I2C_WKUPCON_WKUPEN_Msk (0x1ul << I2C_WKUPCON_WKUPEN_Pos) /*!< I2C_T::WKUPCON: WKUPEN Mask */
+
+#define I2C_WKUPSTS_WKUPIF_Pos (0) /*!< I2C_T::WKUPSTS: WKUPIF Position */
+#define I2C_WKUPSTS_WKUPIF_Msk (0x1ul << I2C_WKUPSTS_WKUPIF_Pos) /*!< I2C_T::WKUPSTS: WKUPIF Mask */
+
+/**@}*/ /* I2C_CONST */
+/**@}*/ /* end of I2C register group */
+
+
+/*---------------------- I2S Interface Controller -------------------------*/
+/**
+ @addtogroup I2S I2S Interface Controller(I2S)
+ Memory Mapped Structure for I2S Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * CTRL
+ * ===================================================================================================
+ * Offset: 0x00 I2S Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |I2SEN |I2S Controller Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[1] |TXEN |Transmit Enable
+ * | | |0 = Data transmitting Disabled.
+ * | | |1 = Data transmitting Enabled.
+ * |[2] |RXEN |Receive Enable
+ * | | |0 = Data receiving Disabled.
+ * | | |1 = Data receiving Enabled.
+ * |[3] |MUTE |Transmitting Mute Enable
+ * | | |0 = Transmit data in buffer to channel.
+ * | | |1 = Transmit '0' to channel.
+ * |[5:4] |WORDWIDTH |Word Width
+ * | | |00 = Data is 8 bit.
+ * | | |01 = Data is 16 bit.
+ * | | |10 = Data is 24 bit.
+ * | | |11 = Data is 32 bit.
+ * |[6] |MONO |Monaural Data
+ * | | |0 = Data is stereo format.
+ * | | |1 = Data is monaural format and gets the right channel data from I2S bus when this mode is enabled.
+ * |[7] |FORMAT |Data Format
+ * | | |0 = I2S data format.
+ * | | |1 = MSB justified data format.
+ * |[8] |SLAVE |Slave Mode
+ * | | |I2S can operate as master or Slave mode.
+ * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and also outputs I2S_BCLK and I2S_LRCLK signals to the audio CODEC.
+ * | | |When act as Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from the outer audio CODEC chip.
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * |[11:9] |TXTH |Transmit FIFO Threshold Level
+ * | | |If remain data word (32 bits) in transmitting FIFO is the same or less than threshold level then TXTHF flag is set.
+ * | | |000 = 1 word data in transmitting FIFO.
+ * | | |001 = 2 word data in transmitting FIFO.
+ * | | |010 = 3 word data in transmitting FIFO.
+ * | | |011 = 4 word data in transmitting FIFO.
+ * | | |100 = 5 word data in transmitting FIFO.
+ * | | |101 = 6 word data in transmitting FIFO.
+ * | | |110 = 7 word data in transmitting FIFO.
+ * | | |111 = 8 word data in transmitting FIFO.
+ * |[14:12] |RXTH |Receiving FIFO Threshold Level
+ * | | |When received data word(s) in buffer is equal to or higher than threshold level, the RXTHF flag is set.
+ * | | |000 = 1 word data in receiving FIFO.
+ * | | |001 = 2 word data in receiving FIFO.
+ * | | |010 = 3 word data in receiving FIFO.
+ * | | |011 = 4 word data in receiving FIFO.
+ * | | |100 = 5 word data in receiving FIFO.
+ * | | |101 = 6 word data in receiving FIFO.
+ * | | |110 = 7 word data in receiving FIFO.
+ * | | |111 = 8 word data in receiving FIFO.
+ * |[15] |MCLKEN |Master Clock Enable
+ * | | |Enable master MCLK timing output to the external audio codec device.
+ * | | |The output frequency is according to MCLK_DIV[2:0] in the I2S_CLKDIV register.
+ * | | |0 = Master Clock Disabled.
+ * | | |1 = Master Clock Enabled.
+ * |[16] |RCHZCEN |Right Channel Zero Cross Detect Enable
+ * | | |If this bit is set to "1", when right channel data sign bit is changed or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to "1".
+ * | | |It works on transmitting mode only.
+ * | | |0 = Right channel zero cross detection Disabled.
+ * | | |1 = Right channel zero cross detection Enabled.
+ * |[17] |LCHZCEN |Left Channel Zero Cross Detect Enable
+ * | | |If this bit is set to "1", when left channel data sign bit is changed or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to "1".
+ * | | |It works on transmitting mode only.
+ * | | |0 = Left channel zero cross detection Disabled.
+ * | | |1 = Left channel zero cross detection Enabled.
+ * |[18] |CLR_TXFIFO|Clear Transmit FIFO
+ * | | |Write "1" to clear transmitting FIFO, internal pointer is reset to FIFO start point, TX_LEVEL[3:0] returns to zero and transmitting FIFO becomes empty but data in transmit FIFO is not changed.
+ * | | |This bit is cleared by hardware automatically, read it to return zero.
+ * |[19] |CLR_RXFIFO|Clear Receiving FIFO
+ * | | |Write "1" to clear receiving FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns to zero and receiving FIFO becomes empty.
+ * | | |This bit is cleared by hardware automatically, and read it return zero.
+ * |[20] |TXDMA |Enable Transmit DMA
+ * | | |When TX DMA is enabled, I2S requests PDMA to transfer data from memory to transmitting FIFO if FIFO is not full
+ * | | |0 = TX DMA Disabled.
+ * | | |1 = TX DMA Enabled.
+ * |[21] |RXDMA |Enable Receive DMA
+ * | | |When RX DMA is enabled, I2S requests PDMA to transfer data from receiving FIFO to memory if FIFO is not empty.
+ * | | |0 = RX DMA Disabled.
+ * | | |1 = RX DMA Enabled.
+ * |[23] |RXLCH |Receive Left Channel Enable
+ * | | |When monaural format is selected (MONO = 1), I2S will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
+ * | | |0 = Receives right channel data when monaural format is selected.
+ * | | |1 = Receives left channel data when monaural format is selected.
+ */
+ __IO uint32_t CTRL;
+
+ /**
+ * CLKDIV
+ * ===================================================================================================
+ * Offset: 0x04 I2S Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |MCLK_DIV |Master Clock Divider
+ * | | |If the external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio CODEC chip.
+ * | | |If MCLK_DIV is set to "0", MCLK is the same as external clock input.
+ * | | |For example, sampling rate is 48 kHz and the external crystal clock is 12.288 MHz, set MCLK_DIV=0.
+ * | | |MCLK = I2SCLK/(2x(MCLK_DIV)).
+ * |[15:8] |BCLK_DIV |Bit Clock Divider
+ * | | |If I2S is operated in Master mode, bit clock is provided by this chip.
+ * | | |Software can program these bits to generate sampling rate clock frequency.
+ * | | |BCLK = I2SCLK /(2x(BCLK_DIV + 1)).
+ */
+ __IO uint32_t CLKDIV;
+
+ /**
+ * INTEN
+ * ===================================================================================================
+ * Offset: 0x08 I2S Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXUDFIE |Receiving FIFO Underflow Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and receiving FIFO underflow flag is set to "1".
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[1] |RXOVFIE |Receiving FIFO Overflow Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and receiving FIFO overflow flag is set to "1"
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[2] |RXTHIE |Receiving FIFO Threshold Level Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and data words in receiving FIFO is less than RXTH[2:0].
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[8] |TXUDFIE |Transmitting FIFO Underflow Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and transmitting FIFO underflow flag is set to "1".
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[9] |TXOVFIE |Transmitting FIFO Overflow Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and transmitting FIFO overflow flag is set to "1"
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[10] |TXTHIE |Transmitting FIFO Threshold Level Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and data words in transmitting FIFO is less than TXTH[2:0].
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[11] |RZCIE |Right Channel Zero Cross Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and right channel is zero crossing.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[12] |LZCIE |Left Channel Zero Cross Interrupt Enable
+ * | | |Interrupt occurs if this bit is set to "1" and left channel is zero crossing.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ */
+ __IO uint32_t INTEN;
+
+ /**
+ * STATUS
+ * ===================================================================================================
+ * Offset: 0x0C I2S Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |I2SINT |I2S Interrupt Flag
+ * | | |0 = No I2S interrupt.
+ * | | |1 = I2S interrupt occurred.
+ * | | |It is wire-OR of I2STXINT and I2SRXINT bits.
+ * | | |This bit is read only.
+ * |[1] |I2SRXINT |I2S Receiving Interrupt
+ * | | |0 = No receiving interrupt occurred.
+ * | | |1 = Receiving interrupt occurred.
+ * | | |This bit is read only
+ * |[2] |I2STXINT |I2S Transmit Interrupt
+ * | | |0 = No transmit interrupt occurred.
+ * | | |1 = Transmit interrupt occurred.
+ * | | |This bit is read only
+ * |[3] |RIGHT |Right Channel
+ * | | |This bit indicates the current transmitting data is belong to right channel
+ * | | |0 = Left channel.
+ * | | |1 = Right channel.
+ * | | |This bit is read only
+ * |[8] |RXUDF |Receiving FIFO Underflow Flag
+ * | | |Read the receiving FIFO when it is empty, this bit set to "1" indicate underflow occur.
+ * | | |0 = No underflow occurred.
+ * | | |1 = Underflow occurred.
+ * | | |This bit is cleared by writing 1.
+ * |[9] |RXOVF |Receiving FIFO Overflow Flag
+ * | | |When the receiving FIFO is full and receiving hardware attempts to write data into receiving FIFO then this bit is set to "1".
+ * | | |Data in 1st buffer is overwritten.
+ * | | |0 = No overflow occurred.
+ * | | |1 = Overflow occurred.
+ * | | |This bit is cleared by writing 1.
+ * |[10] |RXTHF |Receiving FIFO Threshold Flag
+ * | | |When data word(s) in the receiving FIFO is equal to or higher than threshold value set in RXTH[2:0], the RXTHF bit becomes to "1".
+ * | | |It keeps at "1" till RX_LEVEL[3:0] less than RXTH[1:0] after software reads data from the RXFIFO register.
+ * | | |0 = Data word(s) in receiving FIFO is lower than threshold level.
+ * | | |1 = Data word(s) in receiving FIFO is equal to or higher than threshold level.
+ * | | |This bit is read only
+ * |[11] |RXFULL |Receiving FIFO Full
+ * | | |This bit reflect data word number in the receiving FIFO is 8
+ * | | |0 = Not full.
+ * | | |1 = Full.
+ * | | |This bit is read only
+ * |[12] |RXEMPTY |Receiving FIFO Empty
+ * | | |This bit reflect data word number in the receiving FIFO is zero
+ * | | |0 = Empty.
+ * | | |1 = Not empty.
+ * | | |This bit is read only.
+ * |[16] |TXUDF |Transmitting FIFO Underflow Flag
+ * | | |When the transmitting FIFO is empty and shift logic hardware read data from the data FIFO causes this set to "1".
+ * | | |0 = No underflow.
+ * | | |1 = Underflow.
+ * | | |This bit is cleared by writing 1.
+ * |[17] |TXOVF |Transmit FIFO Overflow Flag
+ * | | |Write data to the transmitting FIFO when it is full and this bit will set to "1"
+ * | | |0 = No overflow.
+ * | | |1 = Overflow.
+ * | | |This bit is cleared by writing 1.
+ * |[18] |TXTHF |Transmitting FIFO Threshold Flag
+ * | | |When data word(s) in the transmitting FIFO is equal to or lower than threshold value set in TXTH[2:0],the TXTHF bit becomes to "1".
+ * | | |It keeps at 1 till TX_LEVEL[3:0] is higher than TXTH[1:0] after software writes data into the TXFIFO register.
+ * | | |0 = Data word(s) in transmitting FIFO is higher than threshold level.
+ * | | |1 = Data word(s) in transmitting FIFO is equal to or lower than threshold level.
+ * | | |This bit is read only
+ * |[19] |TXFULL |Transmitting FIFO Full
+ * | | |This bit reflect data word number in the transmitting FIFO is 8
+ * | | |0 = Full.
+ * | | |1 = Not full.
+ * | | |This bit is read only
+ * |[20] |TXEMPTY |Transmitting FIFO Empty
+ * | | |This bit reflect data word number in the transmitting FIFO is zero
+ * | | |0 = Empty.
+ * | | |1 = Not empty.
+ * | | |This bit is read only.
+ * |[21] |TXBUSY |Transmitting Busy
+ * | | |This bit is cleared to 0 when all data in the transmitting FIFO and shift buffer is shifted out.
+ * | | |Set this bit to 1 when 1st data is loading to shift buffer.
+ * | | |0 = Transmit shift buffer is empty.
+ * | | |1 = Transmit shift buffer is busy.
+ * | | |This bit is read only.
+ * |[22] |RZCF |Right Channel Zero Cross Flag
+ * | | |It indicates the data sign of right channel next sample data is changed or all data bits are zero.
+ * | | |0 = No zero cross.
+ * | | |1 = Right channel zero cross is detected.
+ * | | |This bit is cleared by writing 1.
+ * |[23] |LZCF |Left Channel Zero Cross Flag
+ * | | |It indicates the next sample data sign bit of left channel is changed or all data bits are zero.
+ * | | |0 = No zero cross.
+ * | | |1 = Left channel zero cross is detected.
+ * | | |This bit is cleared by writing 1.
+ * |[27:24] |RX_LEVEL |Receive FIFO Level
+ * | | |These bits indicate the number of word(s) in the receiving FIFO
+ * |[31:28] |TX_LEVEL |Transmitting FIFO Level
+ * | | |These bits indicate the number of word(s) in the transmitting FIFO
+ */
+ __IO uint32_t STATUS;
+
+ /**
+ * TXFIFO
+ * ===================================================================================================
+ * Offset: 0x10 I2S Transmit FIFO Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TXFIFO |Transmitting FIFO Register
+ * | | |I2S contains 8 words (8x32-bit) data buffer for data transmitting.
+ * | | |Write data to this register in order to prepare data for transmitting.
+ * | | |The remaining word number is indicated by TX_LEVEL[3:0] in the I2S_STATUS register.
+ * | | |This register is write only.
+ */
+ __O uint32_t TXFIFO;
+
+ /**
+ * RXFIFO
+ * ===================================================================================================
+ * Offset: 0x14 I2S Receive FIFO Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RXFIFO |Receiving FIFO Register
+ * | | |I2S contains 8 words (8x32-bit) data buffer for data receiving.
+ * | | |Read this register to get data in FIFO.
+ * | | |The remaining data word number is indicated by RX_LEVEL[3:0] in the I2S_STATUS register.
+ * | | |This register is read only.
+ */
+ __I uint32_t RXFIFO;
+
+} I2S_T;
+
+/**
+ @addtogroup I2S_CONST I2S Bit Field Definition
+ Constant Definitions for I2S Controller
+@{ */
+
+#define I2S_CTRL_I2SEN_Pos (0) /*!< I2S_T::CTRL: I2SEN Position */
+#define I2S_CTRL_I2SEN_Msk (0x1ul << I2S_CTRL_I2SEN_Pos) /*!< I2S_T::CTRL: I2SEN Mask */
+
+#define I2S_CTRL_TXEN_Pos (1) /*!< I2S_T::CTRL: TXEN Position */
+#define I2S_CTRL_TXEN_Msk (0x1ul << I2S_CTRL_TXEN_Pos) /*!< I2S_T::CTRL: TXEN Mask */
+
+#define I2S_CTRL_RXEN_Pos (2) /*!< I2S_T::CTRL: RXEN Position */
+#define I2S_CTRL_RXEN_Msk (0x1ul << I2S_CTRL_RXEN_Pos) /*!< I2S_T::CTRL: RXEN Mask */
+
+#define I2S_CTRL_MUTE_Pos (3) /*!< I2S_T::CTRL: MUTE Position */
+#define I2S_CTRL_MUTE_Msk (0x1ul << I2S_CTRL_MUTE_Pos) /*!< I2S_T::CTRL: MUTE Mask */
+
+#define I2S_CTRL_WORDWIDTH_Pos (4) /*!< I2S_T::CTRL: WORDWIDTH Position */
+#define I2S_CTRL_WORDWIDTH_Msk (0x3ul << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S_T::CTRL: WORDWIDTH Mask */
+
+#define I2S_CTRL_MONO_Pos (6) /*!< I2S_T::CTRL: MONO Position */
+#define I2S_CTRL_MONO_Msk (0x1ul << I2S_CTRL_MONO_Pos) /*!< I2S_T::CTRL: MONO Mask */
+
+#define I2S_CTRL_FORMAT_Pos (7) /*!< I2S_T::CTRL: FORMAT Position */
+#define I2S_CTRL_FORMAT_Msk (0x1ul << I2S_CTRL_FORMAT_Pos) /*!< I2S_T::CTRL: FORMAT Mask */
+
+#define I2S_CTRL_SLAVE_Pos (8) /*!< I2S_T::CTRL: SLAVE Position */
+#define I2S_CTRL_SLAVE_Msk (0x1ul << I2S_CTRL_SLAVE_Pos) /*!< I2S_T::CTRL: SLAVE Mask */
+
+#define I2S_CTRL_TXTH_Pos (9) /*!< I2S_T::CTRL: TXTH Position */
+#define I2S_CTRL_TXTH_Msk (0x7ul << I2S_CTRL_TXTH_Pos) /*!< I2S_T::CTRL: TXTH Mask */
+
+#define I2S_CTRL_RXTH_Pos (12) /*!< I2S_T::CTRL: RXTH Position */
+#define I2S_CTRL_RXTH_Msk (0x7ul << I2S_CTRL_RXTH_Pos) /*!< I2S_T::CTRL: RXTH Mask */
+
+#define I2S_CTRL_MCLKEN_Pos (15) /*!< I2S_T::CTRL: MCLKEN Position */
+#define I2S_CTRL_MCLKEN_Msk (0x1ul << I2S_CTRL_MCLKEN_Pos) /*!< I2S_T::CTRL: MCLKEN Mask */
+
+#define I2S_CTRL_RCHZCEN_Pos (16) /*!< I2S_T::CTRL: RCHZCEN Position */
+#define I2S_CTRL_RCHZCEN_Msk (0x1ul << I2S_CTRL_RCHZCEN_Pos) /*!< I2S_T::CTRL: RCHZCEN Mask */
+
+#define I2S_CTRL_LCHZCEN_Pos (17) /*!< I2S_T::CTRL: LCHZCEN Position */
+#define I2S_CTRL_LCHZCEN_Msk (0x1ul << I2S_CTRL_LCHZCEN_Pos) /*!< I2S_T::CTRL: LCHZCEN Mask */
+
+#define I2S_CTRL_CLR_TXFIFO_Pos (18) /*!< I2S_T::CTRL: CLR_TXFIFO Position */
+#define I2S_CTRL_CLR_TXFIFO_Msk (0x1ul << I2S_CTRL_CLR_TXFIFO_Pos) /*!< I2S_T::CTRL: CLR_TXFIFO Mask */
+
+#define I2S_CTRL_CLR_RXFIFO_Pos (19) /*!< I2S_T::CTRL: CLR_RXFIFO Position */
+#define I2S_CTRL_CLR_RXFIFO_Msk (0x1ul << I2S_CTRL_CLR_RXFIFO_Pos) /*!< I2S_T::CTRL: CLR_RXFIFO Mask */
+
+#define I2S_CTRL_TXDMA_Pos (20) /*!< I2S_T::CTRL: TXDMA Position */
+#define I2S_CTRL_TXDMA_Msk (0x1ul << I2S_CTRL_TXDMA_Pos) /*!< I2S_T::CTRL: TXDMA Mask */
+
+#define I2S_CTRL_RXDMA_Pos (21) /*!< I2S_T::CTRL: RXDMA Position */
+#define I2S_CTRL_RXDMA_Msk (0x1ul << I2S_CTRL_RXDMA_Pos) /*!< I2S_T::CTRL: RXDMA Mask */
+
+#define I2S_CTRL_RXLCH_Pos (23) /*!< I2S_T::CTRL: RXLCH Position */
+#define I2S_CTRL_RXLCH_Msk (0x1ul << I2S_CTRL_RXLCH_Pos) /*!< I2S_T::CTRL: RXLCH Mask */
+
+#define I2S_CLKDIV_MCLK_DIV_Pos (0) /*!< I2S_T::CLKDIV: MCLK_DIV Position */
+#define I2S_CLKDIV_MCLK_DIV_Msk (0x7ul << I2S_CLKDIV_MCLK_DIV_Pos) /*!< I2S_T::CLKDIV: MCLK_DIV Mask */
+
+#define I2S_CLKDIV_BCLK_DIV_Pos (8) /*!< I2S_T::CLKDIV: BCLK_DIV Position */
+#define I2S_CLKDIV_BCLK_DIV_Msk (0xfful << I2S_CLKDIV_BCLK_DIV_Pos) /*!< I2S_T::CLKDIV: BCLK_DIV Mask */
+
+#define I2S_INTEN_RXUDFIE_Pos (0) /*!< I2S_T::INTEN: RXUDFIE Position */
+#define I2S_INTEN_RXUDFIE_Msk (0x1ul << I2S_INTEN_RXUDFIE_Pos) /*!< I2S_T::INTEN: RXUDFIE Mask */
+
+#define I2S_INTEN_RXOVFIE_Pos (1) /*!< I2S_T::INTEN: RXOVFIE Position */
+#define I2S_INTEN_RXOVFIE_Msk (0x1ul << I2S_INTEN_RXOVFIE_Pos) /*!< I2S_T::INTEN: RXOVFIE Mask */
+
+#define I2S_INTEN_RXTHIE_Pos (2) /*!< I2S_T::INTEN: RXTHIE Position */
+#define I2S_INTEN_RXTHIE_Msk (0x1ul << I2S_INTEN_RXTHIE_Pos) /*!< I2S_T::INTEN: RXTHIE Mask */
+
+#define I2S_INTEN_TXUDFIE_Pos (8) /*!< I2S_T::INTEN: TXUDFIE Position */
+#define I2S_INTEN_TXUDFIE_Msk (0x1ul << I2S_INTEN_TXUDFIE_Pos) /*!< I2S_T::INTEN: TXUDFIE Mask */
+
+#define I2S_INTEN_TXOVFIE_Pos (9) /*!< I2S_T::INTEN: TXOVFIE Position */
+#define I2S_INTEN_TXOVFIE_Msk (0x1ul << I2S_INTEN_TXOVFIE_Pos) /*!< I2S_T::INTEN: TXOVFIE Mask */
+
+#define I2S_INTEN_TXTHIE_Pos (10) /*!< I2S_T::INTEN: TXTHIE Position */
+#define I2S_INTEN_TXTHIE_Msk (0x1ul << I2S_INTEN_TXTHIE_Pos) /*!< I2S_T::INTEN: TXTHIE Mask */
+
+#define I2S_INTEN_RZCIE_Pos (11) /*!< I2S_T::INTEN: RZCIE Position */
+#define I2S_INTEN_RZCIE_Msk (0x1ul << I2S_INTEN_RZCIE_Pos) /*!< I2S_T::INTEN: RZCIE Mask */
+
+#define I2S_INTEN_LZCIE_Pos (12) /*!< I2S_T::INTEN: LZCIE Position */
+#define I2S_INTEN_LZCIE_Msk (0x1ul << I2S_INTEN_LZCIE_Pos) /*!< I2S_T::INTEN: LZCIE Mask */
+
+#define I2S_STATUS_I2SINT_Pos (0) /*!< I2S_T::STATUS: I2SINT Position */
+#define I2S_STATUS_I2SINT_Msk (0x1ul << I2S_STATUS_I2SINT_Pos) /*!< I2S_T::STATUS: I2SINT Mask */
+
+#define I2S_STATUS_I2SRXINT_Pos (1) /*!< I2S_T::STATUS: I2SRXINT Position */
+#define I2S_STATUS_I2SRXINT_Msk (0x1ul << I2S_STATUS_I2SRXINT_Pos) /*!< I2S_T::STATUS: I2SRXINT Mask */
+
+#define I2S_STATUS_I2STXINT_Pos (2) /*!< I2S_T::STATUS: I2STXINT Position */
+#define I2S_STATUS_I2STXINT_Msk (0x1ul << I2S_STATUS_I2STXINT_Pos) /*!< I2S_T::STATUS: I2STXINT Mask */
+
+#define I2S_STATUS_RIGHT_Pos (3) /*!< I2S_T::STATUS: RIGHT Position */
+#define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) /*!< I2S_T::STATUS: RIGHT Mask */
+
+#define I2S_STATUS_RXUDF_Pos (8) /*!< I2S_T::STATUS: RXUDF Position */
+#define I2S_STATUS_RXUDF_Msk (0x1ul << I2S_STATUS_RXUDF_Pos) /*!< I2S_T::STATUS: RXUDF Mask */
+
+#define I2S_STATUS_RXOVF_Pos (9) /*!< I2S_T::STATUS: RXOVF Position */
+#define I2S_STATUS_RXOVF_Msk (0x1ul << I2S_STATUS_RXOVF_Pos) /*!< I2S_T::STATUS: RXOVF Mask */
+
+#define I2S_STATUS_RXTHF_Pos (10) /*!< I2S_T::STATUS: RXTHF Position */
+#define I2S_STATUS_RXTHF_Msk (0x1ul << I2S_STATUS_RXTHF_Pos) /*!< I2S_T::STATUS: RXTHF Mask */
+
+#define I2S_STATUS_RXFULL_Pos (11) /*!< I2S_T::STATUS: RXFULL Position */
+#define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) /*!< I2S_T::STATUS: RXFULL Mask */
+
+#define I2S_STATUS_RXEMPTY_Pos (12) /*!< I2S_T::STATUS: RXEMPTY Position */
+#define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) /*!< I2S_T::STATUS: RXEMPTY Mask */
+
+#define I2S_STATUS_TXUDF_Pos (16) /*!< I2S_T::STATUS: TXUDF Position */
+#define I2S_STATUS_TXUDF_Msk (0x1ul << I2S_STATUS_TXUDF_Pos) /*!< I2S_T::STATUS: TXUDF Mask */
+
+#define I2S_STATUS_TXOVF_Pos (17) /*!< I2S_T::STATUS: TXOVF Position */
+#define I2S_STATUS_TXOVF_Msk (0x1ul << I2S_STATUS_TXOVF_Pos) /*!< I2S_T::STATUS: TXOVF Mask */
+
+#define I2S_STATUS_TXTHF_Pos (18) /*!< I2S_T::STATUS: TXTHF Position */
+#define I2S_STATUS_TXTHF_Msk (0x1ul << I2S_STATUS_TXTHF_Pos) /*!< I2S_T::STATUS: TXTHF Mask */
+
+#define I2S_STATUS_TXFULL_Pos (19) /*!< I2S_T::STATUS: TXFULL Position */
+#define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) /*!< I2S_T::STATUS: TXFULL Mask */
+
+#define I2S_STATUS_TXEMPTY_Pos (20) /*!< I2S_T::STATUS: TXEMPTY Position */
+#define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) /*!< I2S_T::STATUS: TXEMPTY Mask */
+
+#define I2S_STATUS_TXBUSY_Pos (21) /*!< I2S_T::STATUS: TXBUSY Position */
+#define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) /*!< I2S_T::STATUS: TXBUSY Mask */
+
+#define I2S_STATUS_RZCF_Pos (22) /*!< I2S_T::STATUS: RZCF Position */
+#define I2S_STATUS_RZCF_Msk (0x1ul << I2S_STATUS_RZCF_Pos) /*!< I2S_T::STATUS: RZCF Mask */
+
+#define I2S_STATUS_LZCF_Pos (23) /*!< I2S_T::STATUS: LZCF Position */
+#define I2S_STATUS_LZCF_Msk (0x1ul << I2S_STATUS_LZCF_Pos) /*!< I2S_T::STATUS: LZCF Mask */
+
+#define I2S_STATUS_RX_LEVEL_Pos (24) /*!< I2S_T::STATUS: RX_LEVEL Position */
+#define I2S_STATUS_RX_LEVEL_Msk (0xful << I2S_STATUS_RX_LEVEL_Pos) /*!< I2S_T::STATUS: RX_LEVEL Mask */
+
+#define I2S_STATUS_TX_LEVEL_Pos (28) /*!< I2S_T::STATUS: TX_LEVEL Position */
+#define I2S_STATUS_TX_LEVEL_Msk (0xful << I2S_STATUS_TX_LEVEL_Pos) /*!< I2S_T::STATUS: TX_LEVEL Mask */
+
+#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */
+#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */
+
+#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */
+#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */
+
+/**@}*/ /* I2S_CONST */
+/**@}*/ /* end of I2S register group */
+
+
+/*---------------------- Interrupt Controller -------------------------*/
+/**
+ @addtogroup INT Interrupt Controller (INTR)
+ Memory Mapped Structure for INT Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * IRQ0SRC ~ IRQ31SRC
+ * ===================================================================================================
+ * Offset: 0x00 ~0x7C IRQ0~IRQ31 Interrupt Source Identity
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |INT_SRC |Interrupt Source
+ * | | |Define the interrupt sources for interrupt event.
+ */
+ __I uint32_t IRQSRC[32];
+
+
+ /**
+ * NMI_SEL
+ * ===================================================================================================
+ * Offset: 0x80 NMI Source Interrupt Select Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |NMI_SEL |The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]
+ * | | |The NMI_SEL bit[4:0] used to select the NMI interrupt source
+ */
+ __IO uint32_t NMI_SEL;
+
+ /**
+ * MCU_IRQ
+ * ===================================================================================================
+ * Offset: 0x84 MCU IRQ Number Identity Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |MCU_IRQ |MCU IRQ Source Register
+ * | | |The IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core.
+ * | | |There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.
+ * | | |In Normal mode (control by NMI_SEL register bit [7] = 0) The MCU_IRQ collects all interrupts from each peripheral
+ * | | |and synchronizes them and then interrupts the Cortex-M0.
+ * | | |In Test mode, all the interrupts from peripheral are blocked, and the interrupts sent to
+ * | | |MCU are replaced by set the bit31~bit0.
+ * | | |When the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].
+ * | | |When the IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting IRQ[n] 0 has no effect.
+ */
+ __IO uint32_t MCU_IRQ;
+
+} INTR_T;
+
+/**
+ @addtogroup INT_CONST INT Bit Field Definition
+ Constant Definitions for INT Controller
+@{ */
+
+#define INTR_IRQSRC_INT_SRC_Pos (0) /*!< INTR_T::IRQSRC: INT_SRC Position */
+#define INTR_IRQSRC_INT_SRC_Msk (0xful << INTR_IRQ0SRC_INT_SRC_Pos) /*!< INTR_T::IRQSRC: INT_SRC Mask */
+
+#define INTR_NMI_SEL_NMISEL_Pos (0) /*!< INTR_T::NMI_SEL: NMISEL Position */
+#define INTR_NMI_SEL_NMISEL_Msk (0x1ful << INTR_NMI_SEL_NMISEL_Pos) /*!< INTR_T::NMI_SEL: NMISEL Mask */
+
+#define INTR_MCU_IRQ_MCU_IRQ_Pos (0) /*!< INTR_T::MCU_IRQ: MCU_IRQ Position */
+#define INTR_MCU_IRQ_MCU_IRQ_Msk (0xfffffffful << INTR_MCU_IRQ_MCU_IRQ_Pos) /*!< INTR_T::MCU_IRQ: MCU_IRQ Mask */
+
+/**@}*/ /* INTR_CONST */
+/**@}*/ /* end of INTR register group */
+
+
+/*---------------------- LCD Controller -------------------------*/
+/**
+ @addtogroup LCD LCD Controller(LCD)
+ Memory Mapped Structure for LCD Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x00 LCD Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EN |LCD Enable
+ * | | |0 = LCD controller operation Disabled.
+ * | | |1 = LCD controller operation Enabled.
+ * |[3:1] |MUX |Mux Select
+ * | | |000 = Static.
+ * | | |001 = 1/2 duty.
+ * | | |010 = 1/3 duty.
+ * | | |011 = 1/4 duty.
+ * | | |100 = 1/5 duty.
+ * | | |101 = 1/6 duty.
+ * | | |110 = Reserved.
+ * | | |111 = Reserved.
+ * | | |Note : User does not need to set PD_H_MFP bit field, but only to set the MUX bit field to switch LCD_SEG0 and LCD_SEG1 to LCD_COM4 and LCD_COM5 for Nano110 and Nano130 series.
+ * |[6:4] |FREQ |LCD Frequency Selection
+ * | | |000 = LCDCLK Divided by 32.
+ * | | |001 = LCDCLK Divided by 64.
+ * | | |010 = LCDCLK Divided by 96.
+ * | | |011 = LCDCLK Divided by 128.
+ * | | |100 = LCDCLK Divided by 192.
+ * | | |101 = LCDCLK Divided by 256.
+ * | | |110 = LCDCLK Divided by 384.
+ * | | |111 = LCDCLK Divided by 512.
+ * |[7] |BLINK |LCD Blinking Enable
+ * | | |0 = Blinking Disabled.
+ * | | |1 = Blinking Enabled.
+ * |[8] |PDDISP_EN |Power Down Display Enable
+ * | | |The LCD can be programmed to be displayed or not be displayed at power down state by PDDISP_EN setting.
+ * | | |0 = LCD display Disabled ( LCD is put out) at power down state.
+ * | | |1 = LCD display Enabled (LCD keeps the display) at power down state.
+ * |[9] |PDINT_EN |Power Down Interrupt Enable
+ * | | |If the power down request is triggered from system management, LCD controller will execute the frame completely to avoid the DC component.
+ * | | |When the frame is executed completely, the LCD power down interrupt signal is generated to inform system management that LCD controller is ready to enter power down state, if PDINT_EN is set to 1.
+ * | | |Otherwise, if PDINT_EN is set to 0, the LCD power down interrupt signal is blocked and the interrupt is disabled to send to system management.
+ * | | |0 = Power Down Interrupt Disabled.
+ * | | |1 = Power Down Interrupt Enabled.
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * DISPCTL
+ * ===================================================================================================
+ * Offset: 0x04 LCD Display Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CPUMP_EN |Charge Pump Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2:1] |BIAS_SEL |Bias Selection
+ * | | |00 = Static.
+ * | | |01 = 1/2 Bias.
+ * | | |10 = 1/3 Bias.
+ * | | |11 = Reserved.
+ * |[4] |IBRL_EN |Internal Bias Reference Ladder Enable
+ * | | |0 = Bias reference ladder Disabled.
+ * | | |1 = Bias reference ladder Enabled.
+ * |[6] |BV_SEL |Bias Voltage Type Selection
+ * | | |0 = C-Type bias mode. Bias voltage source from internal bias generator.
+ * | | |1 = R-Type bias mode. Bias voltage source from external bias generator.
+ * | | |Note: The external resistor ladder should be connected to the V1 pin, V2 pin, V3 pin and VSS.
+ * | | |The VLCD pin should also be connected to VDD.
+ * |[10:8] |CPUMP_VOL_SET|Charge Pump Voltage Selection
+ * | | |000 = 2.7V.
+ * | | |001 = 2.8V.
+ * | | |010 = 2.9V.
+ * | | |011 = 3.0V.
+ * | | |100 = 3.1V.
+ * | | |101 = 3.2V.
+ * | | |110 = 3.3V.
+ * | | |111 = 3.4V.
+ * |[13:11] |CPUMP_FREQ|Charge Pump Frequency Selection
+ * | | |000 = LCDCLK.
+ * | | |001 = LCDCLK/2.
+ * | | |010 = LCDCLK/4.
+ * | | |011 = LCDCLK/8.
+ * | | |100 = LCDCLK/16.
+ * | | |101 = LCDCLK/32.
+ * | | |110 = LCDCLK/64.
+ * | | |111 = LCDCLK/128.
+ */
+ __IO uint32_t DISPCTL;
+
+ /**
+ * MEM_0
+ * ===================================================================================================
+ * Offset: 0x08 LCD SEG3 ~ SEG0 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_0;
+
+ /**
+ * MEM_1
+ * ===================================================================================================
+ * Offset: 0x0C LCD SEG7 ~ SEG4 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_1;
+
+ /**
+ * MEM_2
+ * ===================================================================================================
+ * Offset: 0x10 LCD SEG11 ~ SEG8 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_2;
+
+ /**
+ * MEM_3
+ * ===================================================================================================
+ * Offset: 0x14 LCD SEG15 ~ SEG12 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_3;
+
+ /**
+ * MEM_4
+ * ===================================================================================================
+ * Offset: 0x18 LCD SEG19 ~ SEG16 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_4;
+
+ /**
+ * MEM_5
+ * ===================================================================================================
+ * Offset: 0x1C LCD SEG23 ~ SEG20 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_5;
+
+ /**
+ * MEM_6
+ * ===================================================================================================
+ * Offset: 0x20 LCD SEG27 ~ SEG24 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_6;
+
+ /**
+ * MEM_7
+ * ===================================================================================================
+ * Offset: 0x24 LCD SEG31 ~ SEG28 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_7;
+
+ /**
+ * MEM_8
+ * ===================================================================================================
+ * Offset: 0x28 LCD SEG35 ~ SEG32 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_8;
+
+ /**
+ * MEM_9
+ * ===================================================================================================
+ * Offset: 0x2C LCD SEG39 ~ SEG36 data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SEG_0_4x |SEG_0_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[14:8] |SEG_1_4x |SEG_1_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[21:16] |SEG_2_4x |SEG_2_4x DATA for COM(x= 0 ~ 9)
+ * | | |LCD display data
+ * |[29:24] |SEG_3_4x |SEG_3_4x DATA for COM (x = 0 ~ 9)
+ * | | |LCD display data
+ */
+ __IO uint32_t MEM_9;
+
+ /**
+ * FCR
+ * ===================================================================================================
+ * Offset: 0x30 LCD frame counter control register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FCEN |LCD Frame Counter Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[1] |FCINTEN |LCD Frame Counter Interrupt Enable
+ * | | |0 = Frame counter interrupt Disabled.
+ * | | |1 = Frame counter interrupt Enabled.
+ * |[3:2] |PRESCL |Frame Counter Pre-Scaler Value
+ * | | |00 = CLKframe/1.
+ * | | |01 = CLKframe/2.
+ * | | |10 = CLKframe/4.
+ * | | |11 = CLKframe/8.
+ * |[9:4] |FCV |Frame Counter Top Value
+ * | | |These 6 bits contain the top value of the Frame counter.
+ */
+ __IO uint32_t FCR;
+
+ /**
+ * FCSTS
+ * ===================================================================================================
+ * Offset: 0x34 LCD frame counter status
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FCSTS |LCD Frame Counter Status
+ * | | |0 = Frame counter value does not reach FCV (Frame Count TOP value).
+ * | | |1 = Frame counter value reaches FCV (Frame Count TOP value).
+ * | | |If the FCINTEN is s enabled, the frame counter overflow Interrupt is generated.
+ * |[1] |PDSTS |Power-Down Interrupt Status
+ * | | |0 = Inform system manager that LCD controller is not ready to enter power-down state until this bit becomes 1 if power down is set and one frame is not executed completely.
+ * | | |1 = Inform system manager that LCD controller is ready to enter power-down state if power down is set and one frame is executed completely
+ */
+ __IO uint32_t FCSTS;
+
+} LCD_T;
+
+/**
+ @addtogroup LCD_CONST LCD Bit Field Definition
+ Constant Definitions for LCD Controller
+@{ */
+
+#define LCD_CTL_EN_Pos (0) /*!< LCD_T::CTL: EN Position */
+#define LCD_CTL_EN_Msk (0x1ul << LCD_CTL_EN_Pos) /*!< LCD_T::CTL: EN Mask */
+
+#define LCD_CTL_MUX_Pos (1) /*!< LCD_T::CTL: MUX Position */
+#define LCD_CTL_MUX_Msk (0x7ul << LCD_CTL_MUX_Pos) /*!< LCD_T::CTL: MUX Mask */
+
+#define LCD_CTL_FREQ_Pos (4) /*!< LCD_T::CTL: FREQ Position */
+#define LCD_CTL_FREQ_Msk (0x7ul << LCD_CTL_FREQ_Pos) /*!< LCD_T::CTL: FREQ Mask */
+
+#define LCD_CTL_BLINK_Pos (7) /*!< LCD_T::CTL: BLINK Position */
+#define LCD_CTL_BLINK_Msk (0x1ul << LCD_CTL_BLINK_Pos) /*!< LCD_T::CTL: BLINK Mask */
+
+#define LCD_CTL_PDDISP_EN_Pos (8) /*!< LCD_T::CTL: PDDISP_EN Position */
+#define LCD_CTL_PDDISP_EN_Msk (0x1ul << LCD_CTL_PDDISP_EN_Pos) /*!< LCD_T::CTL: PDDISP_EN Mask */
+
+#define LCD_CTL_PDINT_EN_Pos (9) /*!< LCD_T::CTL: PDINT_EN Position */
+#define LCD_CTL_PDINT_EN_Msk (0x1ul << LCD_CTL_PDINT_EN_Pos) /*!< LCD_T::CTL: PDINT_EN Mask */
+
+#define LCD_DISPCTL_CPUMP_EN_Pos (0) /*!< LCD_T::DISPCTL: CPUMP_EN Position */
+#define LCD_DISPCTL_CPUMP_EN_Msk (0x1ul << LCD_DISPCTL_CPUMP_EN_Pos) /*!< LCD_T::DISPCTL: CPUMP_EN Mask */
+
+#define LCD_DISPCTL_BIAS_SEL_Pos (1) /*!< LCD_T::DISPCTL: BIAS_SEL Position */
+#define LCD_DISPCTL_BIAS_SEL_Msk (0x3ul << LCD_DISPCTL_BIAS_SEL_Pos) /*!< LCD_T::DISPCTL: BIAS_SEL Mask */
+
+#define LCD_DISPCTL_IBRL_EN_Pos (4) /*!< LCD_T::DISPCTL: IBRL_EN Position */
+#define LCD_DISPCTL_IBRL_EN_Msk (0x1ul << LCD_DISPCTL_IBRL_EN_Pos) /*!< LCD_T::DISPCTL: IBRL_EN Mask */
+
+#define LCD_DISPCTL_BV_SEL_Pos (6) /*!< LCD_T::DISPCTL: BV_SEL Position */
+#define LCD_DISPCTL_BV_SEL_Msk (0x1ul << LCD_DISPCTL_BV_SEL_Pos) /*!< LCD_T::DISPCTL: BV_SEL Mask */
+
+#define LCD_DISPCTL_CPUMP_VOL_SET_Pos (8) /*!< LCD_T::DISPCTL: CPUMP_VOL_SET Position */
+#define LCD_DISPCTL_CPUMP_VOL_SET_Msk (0x7ul << LCD_DISPCTL_CPUMP_VOL_SET_Pos) /*!< LCD_T::DISPCTL: CPUMP_VOL_SET Mask */
+
+#define LCD_DISPCTL_CPUMP_FREQ_Pos (11) /*!< LCD_T::DISPCTL: CPUMP_FREQ Position */
+#define LCD_DISPCTL_CPUMP_FREQ_Msk (0x7ul << LCD_DISPCTL_CPUMP_FREQ_Pos) /*!< LCD_T::DISPCTL: CPUMP_FREQ Mask */
+
+#define LCD_MEM_0_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_0: SEG_0_4x Position */
+#define LCD_MEM_0_SEG_0_4x_Msk (0x3ful << LCD_MEM_0_SEG_0_4x_Pos) /*!< LCD_T::MEM_0: SEG_0_4x Mask */
+
+#define LCD_MEM_0_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_0: SEG_1_4x Position */
+#define LCD_MEM_0_SEG_1_4x_Msk (0x7ful << LCD_MEM_0_SEG_1_4x_Pos) /*!< LCD_T::MEM_0: SEG_1_4x Mask */
+
+#define LCD_MEM_0_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_0: SEG_2_4x Position */
+#define LCD_MEM_0_SEG_2_4x_Msk (0x3ful << LCD_MEM_0_SEG_2_4x_Pos) /*!< LCD_T::MEM_0: SEG_2_4x Mask */
+
+#define LCD_MEM_0_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_0: SEG_3_4x Position */
+#define LCD_MEM_0_SEG_3_4x_Msk (0x3ful << LCD_MEM_0_SEG_3_4x_Pos) /*!< LCD_T::MEM_0: SEG_3_4x Mask */
+
+#define LCD_MEM_1_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_1: SEG_0_4x Position */
+#define LCD_MEM_1_SEG_0_4x_Msk (0x3ful << LCD_MEM_1_SEG_0_4x_Pos) /*!< LCD_T::MEM_1: SEG_0_4x Mask */
+
+#define LCD_MEM_1_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_1: SEG_1_4x Position */
+#define LCD_MEM_1_SEG_1_4x_Msk (0x7ful << LCD_MEM_1_SEG_1_4x_Pos) /*!< LCD_T::MEM_1: SEG_1_4x Mask */
+
+#define LCD_MEM_1_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_1: SEG_2_4x Position */
+#define LCD_MEM_1_SEG_2_4x_Msk (0x3ful << LCD_MEM_1_SEG_2_4x_Pos) /*!< LCD_T::MEM_1: SEG_2_4x Mask */
+
+#define LCD_MEM_1_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_1: SEG_3_4x Position */
+#define LCD_MEM_1_SEG_3_4x_Msk (0x3ful << LCD_MEM_1_SEG_3_4x_Pos) /*!< LCD_T::MEM_1: SEG_3_4x Mask */
+
+#define LCD_MEM_2_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_2: SEG_0_4x Position */
+#define LCD_MEM_2_SEG_0_4x_Msk (0x3ful << LCD_MEM_2_SEG_0_4x_Pos) /*!< LCD_T::MEM_2: SEG_0_4x Mask */
+
+#define LCD_MEM_2_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_2: SEG_1_4x Position */
+#define LCD_MEM_2_SEG_1_4x_Msk (0x7ful << LCD_MEM_2_SEG_1_4x_Pos) /*!< LCD_T::MEM_2: SEG_1_4x Mask */
+
+#define LCD_MEM_2_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_2: SEG_2_4x Position */
+#define LCD_MEM_2_SEG_2_4x_Msk (0x3ful << LCD_MEM_2_SEG_2_4x_Pos) /*!< LCD_T::MEM_2: SEG_2_4x Mask */
+
+#define LCD_MEM_2_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_2: SEG_3_4x Position */
+#define LCD_MEM_2_SEG_3_4x_Msk (0x3ful << LCD_MEM_2_SEG_3_4x_Pos) /*!< LCD_T::MEM_2: SEG_3_4x Mask */
+
+#define LCD_MEM_3_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_3: SEG_0_4x Position */
+#define LCD_MEM_3_SEG_0_4x_Msk (0x3ful << LCD_MEM_3_SEG_0_4x_Pos) /*!< LCD_T::MEM_3: SEG_0_4x Mask */
+
+#define LCD_MEM_3_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_3: SEG_1_4x Position */
+#define LCD_MEM_3_SEG_1_4x_Msk (0x7ful << LCD_MEM_3_SEG_1_4x_Pos) /*!< LCD_T::MEM_3: SEG_1_4x Mask */
+
+#define LCD_MEM_3_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_3: SEG_2_4x Position */
+#define LCD_MEM_3_SEG_2_4x_Msk (0x3ful << LCD_MEM_3_SEG_2_4x_Pos) /*!< LCD_T::MEM_3: SEG_2_4x Mask */
+
+#define LCD_MEM_3_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_3: SEG_3_4x Position */
+#define LCD_MEM_3_SEG_3_4x_Msk (0x3ful << LCD_MEM_3_SEG_3_4x_Pos) /*!< LCD_T::MEM_3: SEG_3_4x Mask */
+
+#define LCD_MEM_4_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_4: SEG_0_4x Position */
+#define LCD_MEM_4_SEG_0_4x_Msk (0x3ful << LCD_MEM_4_SEG_0_4x_Pos) /*!< LCD_T::MEM_4: SEG_0_4x Mask */
+
+#define LCD_MEM_4_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_4: SEG_1_4x Position */
+#define LCD_MEM_4_SEG_1_4x_Msk (0x7ful << LCD_MEM_4_SEG_1_4x_Pos) /*!< LCD_T::MEM_4: SEG_1_4x Mask */
+
+#define LCD_MEM_4_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_4: SEG_2_4x Position */
+#define LCD_MEM_4_SEG_2_4x_Msk (0x3ful << LCD_MEM_4_SEG_2_4x_Pos) /*!< LCD_T::MEM_4: SEG_2_4x Mask */
+
+#define LCD_MEM_4_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_4: SEG_3_4x Position */
+#define LCD_MEM_4_SEG_3_4x_Msk (0x3ful << LCD_MEM_4_SEG_3_4x_Pos) /*!< LCD_T::MEM_4: SEG_3_4x Mask */
+
+#define LCD_MEM_5_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_5: SEG_0_4x Position */
+#define LCD_MEM_5_SEG_0_4x_Msk (0x3ful << LCD_MEM_5_SEG_0_4x_Pos) /*!< LCD_T::MEM_5: SEG_0_4x Mask */
+
+#define LCD_MEM_5_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_5: SEG_1_4x Position */
+#define LCD_MEM_5_SEG_1_4x_Msk (0x7ful << LCD_MEM_5_SEG_1_4x_Pos) /*!< LCD_T::MEM_5: SEG_1_4x Mask */
+
+#define LCD_MEM_5_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_5: SEG_2_4x Position */
+#define LCD_MEM_5_SEG_2_4x_Msk (0x3ful << LCD_MEM_5_SEG_2_4x_Pos) /*!< LCD_T::MEM_5: SEG_2_4x Mask */
+
+#define LCD_MEM_5_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_5: SEG_3_4x Position */
+#define LCD_MEM_5_SEG_3_4x_Msk (0x3ful << LCD_MEM_5_SEG_3_4x_Pos) /*!< LCD_T::MEM_5: SEG_3_4x Mask */
+
+#define LCD_MEM_6_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_6: SEG_0_4x Position */
+#define LCD_MEM_6_SEG_0_4x_Msk (0x3ful << LCD_MEM_6_SEG_0_4x_Pos) /*!< LCD_T::MEM_6: SEG_0_4x Mask */
+
+#define LCD_MEM_6_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_6: SEG_1_4x Position */
+#define LCD_MEM_6_SEG_1_4x_Msk (0x7ful << LCD_MEM_6_SEG_1_4x_Pos) /*!< LCD_T::MEM_6: SEG_1_4x Mask */
+
+#define LCD_MEM_6_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_6: SEG_2_4x Position */
+#define LCD_MEM_6_SEG_2_4x_Msk (0x3ful << LCD_MEM_6_SEG_2_4x_Pos) /*!< LCD_T::MEM_6: SEG_2_4x Mask */
+
+#define LCD_MEM_6_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_6: SEG_3_4x Position */
+#define LCD_MEM_6_SEG_3_4x_Msk (0x3ful << LCD_MEM_6_SEG_3_4x_Pos) /*!< LCD_T::MEM_6: SEG_3_4x Mask */
+
+#define LCD_MEM_7_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_7: SEG_0_4x Position */
+#define LCD_MEM_7_SEG_0_4x_Msk (0x3ful << LCD_MEM_7_SEG_0_4x_Pos) /*!< LCD_T::MEM_7: SEG_0_4x Mask */
+
+#define LCD_MEM_7_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_7: SEG_1_4x Position */
+#define LCD_MEM_7_SEG_1_4x_Msk (0x7ful << LCD_MEM_7_SEG_1_4x_Pos) /*!< LCD_T::MEM_7: SEG_1_4x Mask */
+
+#define LCD_MEM_7_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_7: SEG_2_4x Position */
+#define LCD_MEM_7_SEG_2_4x_Msk (0x3ful << LCD_MEM_7_SEG_2_4x_Pos) /*!< LCD_T::MEM_7: SEG_2_4x Mask */
+
+#define LCD_MEM_7_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_7: SEG_3_4x Position */
+#define LCD_MEM_7_SEG_3_4x_Msk (0x3ful << LCD_MEM_7_SEG_3_4x_Pos) /*!< LCD_T::MEM_7: SEG_3_4x Mask */
+
+#define LCD_MEM_8_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_8: SEG_0_4x Position */
+#define LCD_MEM_8_SEG_0_4x_Msk (0x3ful << LCD_MEM_8_SEG_0_4x_Pos) /*!< LCD_T::MEM_8: SEG_0_4x Mask */
+
+#define LCD_MEM_8_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_8: SEG_1_4x Position */
+#define LCD_MEM_8_SEG_1_4x_Msk (0x7ful << LCD_MEM_8_SEG_1_4x_Pos) /*!< LCD_T::MEM_8: SEG_1_4x Mask */
+
+#define LCD_MEM_8_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_8: SEG_2_4x Position */
+#define LCD_MEM_8_SEG_2_4x_Msk (0x3ful << LCD_MEM_8_SEG_2_4x_Pos) /*!< LCD_T::MEM_8: SEG_2_4x Mask */
+
+#define LCD_MEM_8_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_8: SEG_3_4x Position */
+#define LCD_MEM_8_SEG_3_4x_Msk (0x3ful << LCD_MEM_8_SEG_3_4x_Pos) /*!< LCD_T::MEM_8: SEG_3_4x Mask */
+
+#define LCD_MEM_9_SEG_0_4x_Pos (0) /*!< LCD_T::MEM_9: SEG_0_4x Position */
+#define LCD_MEM_9_SEG_0_4x_Msk (0x3ful << LCD_MEM_9_SEG_0_4x_Pos) /*!< LCD_T::MEM_9: SEG_0_4x Mask */
+
+#define LCD_MEM_9_SEG_1_4x_Pos (8) /*!< LCD_T::MEM_9: SEG_1_4x Position */
+#define LCD_MEM_9_SEG_1_4x_Msk (0x7ful << LCD_MEM_9_SEG_1_4x_Pos) /*!< LCD_T::MEM_9: SEG_1_4x Mask */
+
+#define LCD_MEM_9_SEG_2_4x_Pos (16) /*!< LCD_T::MEM_9: SEG_2_4x Position */
+#define LCD_MEM_9_SEG_2_4x_Msk (0x3ful << LCD_MEM_9_SEG_2_4x_Pos) /*!< LCD_T::MEM_9: SEG_2_4x Mask */
+
+#define LCD_MEM_9_SEG_3_4x_Pos (24) /*!< LCD_T::MEM_9: SEG_3_4x Position */
+#define LCD_MEM_9_SEG_3_4x_Msk (0x3ful << LCD_MEM_9_SEG_3_4x_Pos) /*!< LCD_T::MEM_9: SEG_3_4x Mask */
+
+#define LCD_FCR_FCEN_Pos (0) /*!< LCD_T::FCR: FCEN Position */
+#define LCD_FCR_FCEN_Msk (0x1ul << LCD_FCR_FCEN_Pos) /*!< LCD_T::FCR: FCEN Mask */
+
+#define LCD_FCR_FCINTEN_Pos (1) /*!< LCD_T::FCR: FCINTEN Position */
+#define LCD_FCR_FCINTEN_Msk (0x1ul << LCD_FCR_FCINTEN_Pos) /*!< LCD_T::FCR: FCINTEN Mask */
+
+#define LCD_FCR_PRESCL_Pos (2) /*!< LCD_T::FCR: PRESCL Position */
+#define LCD_FCR_PRESCL_Msk (0x3ul << LCD_FCR_PRESCL_Pos) /*!< LCD_T::FCR: PRESCL Mask */
+
+#define LCD_FCR_FCV_Pos (4) /*!< LCD_T::FCR: FCV Position */
+#define LCD_FCR_FCV_Msk (0x3ful << LCD_FCR_FCV_Pos) /*!< LCD_T::FCR: FCV Mask */
+
+#define LCD_FCSTS_FCSTS_Pos (0) /*!< LCD_T::FCSTS: FCSTS Position */
+#define LCD_FCSTS_FCSTS_Msk (0x1ul << LCD_FCSTS_FCSTS_Pos) /*!< LCD_T::FCSTS: FCSTS Mask */
+
+#define LCD_FCSTS_PDSTS_Pos (1) /*!< LCD_T::FCSTS: PDSTS Position */
+#define LCD_FCSTS_PDSTS_Msk (0x1ul << LCD_FCSTS_PDSTS_Pos) /*!< LCD_T::FCSTS: PDSTS Mask */
+
+/**@}*/ /* LCD_CONST */
+/**@}*/ /* end of LCD register group */
+
+
+/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
+/**
+ @addtogroup DMA Direct Memory Access Controller(DMA)
+ Memory Mapped Structure for DMA Controller
+@{ */
+
+
+typedef struct {
+
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x00 DMA CRC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CRCCEN |CRC Channel Enable
+ * | | |Setting this bit to 1 enables CRC's operation.
+ * | | |When operating in CRC DMA mode (TRIG_EN = 1), if user clear this bit, the DMA operation will be continuous until all CRC DMA operation done, and the TRIG_EN bit will asserted until all CRC DMA operation done.
+ * | | |But in this case, the CRC_DMAISR [BLKD_IF] flag will inactive, user can read CRC result by reading CRC_CHECKSUM register when TRIG_EN = 0.
+ * | | |When operating in CRC DMA mode (TRIG_EN = 1), if user want to stop the transfer immediately, user can write 1 to CRC_RST bit to stop the transmission.
+ * |[1] |CRC_RST |CRC Engine Reset
+ * | | |0 = Writing 0 to this bit has no effect.
+ * | | |1 = Writing 1 to this bit will reset the internal CRC state machine and internal buffer.
+ * | | |The contents of control register will not be cleared.
+ * | | |This bit will be auto cleared after few clock cycles.
+ * | | |Note: When operating in CPU PIO mode, setting this bit will reload the initial seed value
+ * |[23] |TRIG_EN |Trigger Enable
+ * | | |0 = No effect.
+ * | | |1 = CRC DMA data read or write transfer Enabled.
+ * | | |Note1: If this bit assert that indicates the CRC engine operation in CRC DMA mode, so don't filled any data in CRC_WDATA register.
+ * | | |Note2: When CRC DMA transfer completed, this bit will be cleared automatically.
+ * | | |Note3: If the bus error occurs, all CRC DMA transfer will be stopped.
+ * | | |Software must reset all DMA channel, and then trigger again.
+ * |[24] |WDATA_RVS |Write Data Order Reverse
+ * | | |0 = No bit order reverse for CRC write data in.
+ * | | |1 = Bit order reverse for CRC write data in (per byre).
+ * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
+ * |[25] |CHECKSUM_RVS|Checksum Reverse
+ * | | |0 = No bit order reverse for CRC checksum.
+ * | | |1 = Bit order reverse for CRC checksum.
+ * | | |Note: If the checksum data is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
+ * |[26] |WDATA_COM |Write Data Complement
+ * | | |0 = No bit order reverse for CRC write data in.
+ * | | |1 = 1's complement for CRC write data in.
+ * |[27] |CHECKSUM_COM|Checksum Complement
+ * | | |0 = No bit order reverse for CRC checksum.
+ * | | |1 = 1's complement for CRC checksum.
+ * |[29:28] |CPU_WDLEN |CPU Write Data Length
+ * | | |When operating in CPU PIO mode (CRCCEN= 1, TRIG_EN = 0), this field indicates the write data length.
+ * | | |00 = The data length is 8-bit mode
+ * | | |01 = The data length is 16-bit mode
+ * | | |10 = The data length is 32-bit mode
+ * | | |11 = Reserved
+ * | | |Note1: This field is only used for CPU PIO mode.
+ * | | |Note2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0], and if the data length is 16 bit mode, the valid data is CRC_WDATA [15:0].
+ * |[31:30] |CRC_MODE |CRC Polynomial Mode
+ * | | |00 = CRC-CCITT Polynomial Mode
+ * | | |01 = CRC-8 Polynomial Mode
+ * | | |10 = CRC-16 Polynomial Mode
+ * | | |11 = CRC-32 Polynomial Mode
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * DMASAR
+ * ===================================================================================================
+ * Offset: 0x04 DMA CRC Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRC_DMASAR|CRC DMA Transfer Source Address Register
+ * | | |This field indicates a 32-bit source address of CRC DMA.
+ * | | |Note : The source address must be word alignment
+ */
+ __IO uint32_t DMASAR;
+ uint32_t RESERVE0[1];
+
+
+ /**
+ * DMABCR
+ * ===================================================================================================
+ * Offset: 0x0C DMA CRC Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRC_DMABCR|CRC DMA Transfer Byte Count Register
+ * | | |This field indicates a 16-bit transfer byte count number of CRC DMA
+ */
+ __IO uint32_t DMABCR;
+ uint32_t RESERVE1[1];
+
+
+ /**
+ * DMACSAR
+ * ===================================================================================================
+ * Offset: 0x14 DMA CRC Current Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRC_DMACSAR|CRC DMA Current Source Address Register (Read Only)
+ * | | |This field indicates the source address where the CRC DMA transfer is just occurring.
+ */
+ __I uint32_t DMACSAR;
+ uint32_t RESERVE2[1];
+
+
+ /**
+ * DMACBCR
+ * ===================================================================================================
+ * Offset: 0x1C DMA CRC Current Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRC_DMACBCR|CRC DMA Current Byte Count Register (Read Only)
+ * | | |This field indicates the current remained byte count of CRC_DMA.
+ * | | |Note: CRC_RST will clear this register value.
+ */
+ __I uint32_t DMACBCR;
+
+ /**
+ * DMAIER
+ * ===================================================================================================
+ * Offset: 0x20 DMA CRC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TABORT_IE |CRC DMA Read/Write Target Abort Interrupt Enable
+ * | | |0 = Target abort interrupt generation Disabled during CRC DMA transfer.
+ * | | |1 = Target abort interrupt generation Enabled during CRC DMA transfer.
+ * |[1] |BLKD_IE |CRC DMA Transfer Done Interrupt Enable
+ * | | |0 = Interrupt generator Disabled during CRC DMA transfer done.
+ * | | |1 = Interrupt generator Enabled during CRC DMA transfer done.
+ */
+ __IO uint32_t DMAIER;
+
+ /**
+ * DMAISR
+ * ===================================================================================================
+ * Offset: 0x24 DMA CRC Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TABORT_IF |CRC DMA Read/Write Target Abort Interrupt Flag
+ * | | |0 = No bus ERROR response received.
+ * | | |1 = Bus ERROR response received.
+ * | | |Software can write 1 to clear this bit to zero
+ * | | |Note: The CRC_DMAISR [TABORT_IF] indicate bus master received ERROR response or not.
+ * | | |If bus master received ERROR response, it means that target abort is happened.
+ * | | |DMA will stop transfer and respond this event to software then go to IDLE state.
+ * | | |When target abort occurred, software must reset DMA, and then transfer those data again.
+ * |[1] |BLKD_IF |Block Transfer Done Interrupt Flag
+ * | | |This bit indicates that CRC DMA has finished all transfer.
+ * | | |0 = Not finished yet.
+ * | | |1 = Done.
+ * | | |Software can write 1 to clear this bit to zero
+ */
+ __IO uint32_t DMAISR;
+ uint32_t RESERVE3[22];
+
+
+ /**
+ * WDATA
+ * ===================================================================================================
+ * Offset: 0x80 DMA CRC Write Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRC_WDATA |CRC Write Data Register
+ * | | |When operating in CPU PIO (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0) mode, software can write data to this field to perform CRC operation;.
+ * | | |When operating in CRC DMA mode (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0), this field will be used for DMA internal buffer.
+ * | | |Note1: When operating in CRC DMA mode, so don't filled any data in this field.
+ * | | |Note2:The CRC_CTL [WDATA_COM] and CRC_CTL [WDATA_RVS] bit setting will affected this field; For example, if WDATA_RVS = 1, if the write data in CRC_WDATA register is 0xAABBCCDD, the read data from CRC_WDATA register will be 0x55DD33BB
+ */
+ __IO uint32_t WDATA;
+
+ /**
+ * SEED
+ * ===================================================================================================
+ * Offset: 0x84 DMA CRC Seed Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRC_SEED |CRC Seed Register
+ * | | |This field indicates the CRC seed value.
+ */
+ __IO uint32_t SEED;
+
+ /**
+ * CHECKSUM
+ * ===================================================================================================
+ * Offset: 0x88 DMA CRC Check Sum Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRC_CHECKSUM|CRC Checksum Register
+ * | | |This field indicates the CRC checksum
+ */
+ __I uint32_t CHECKSUM;
+
+} DMA_CRC_T;
+
+
+typedef struct {
+
+
+ /**
+ * GCRCSR
+ * ===================================================================================================
+ * Offset: 0x00 DMA Global Control and Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8] |CLK0_EN |DMA Controller Channel 0 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[9] |CLK1_EN |DMA Controller Channel 1 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[10] |CLK2_EN |DMA Controller Channel 2 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[11] |CLK3_EN |DMA Controller Channel 3 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[12] |CLK4_EN |DMA Controller Channel 4 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[13] |CLK5_EN |DMA Controller Channel 5 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[14] |CLK6_EN |DMA Controller Channel 6 Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[24] |CRC_CLK_EN|CRC Controller Clock Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ */
+ __IO uint32_t GCRCSR;
+
+ /**
+ * DSSR0
+ * ===================================================================================================
+ * Offset: 0x04 DMA Service Selection Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[12:8] |CH1_SEL |Channel 1 Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 1.
+ * | | |Software can configure the peripheral by setting CH1_SEL.
+ * | | |00000 = Connect to SPI0_TX.
+ * | | |00001 = Connect to SPI1_TX.
+ * | | |00010 = Connect to UART0_TX.
+ * | | |00011 = Connect to UART1_TX.
+ * | | |00100 = Connect to USB_TX.
+ * | | |00101 = Connect to I2S_TX.
+ * | | |00110 = Connect to DAC0_TX.
+ * | | |00111 = Connect to DAC1_TX.
+ * | | |01000 = Connect to SPI2_TX.
+ * | | |01001 = Connect to TMR0.
+ * | | |01010 = Connect to TMR1.
+ * | | |01011 = Connect to TMR2.
+ * | | |01100 = Connect to TMR3.
+ * | | |10000 = Connect to SPI0_RX.
+ * | | |10001 = Connect to SPI1_RX.
+ * | | |10010 = Connect to UART0_RX.
+ * | | |10011 = Connect to UART1_RX.
+ * | | |10100 = Connect to USB_RX.
+ * | | |10101 = Connect to I2S_RX.
+ * | | |10110 = Connect to ADC.
+ * | | |11000 = Connect to SPI2_RX.
+ * | | |11001 = Connect to PWM0_CH0.
+ * | | |11010 = Connect to PWM0_CH2.
+ * | | |11011 = Connect to PWM1_CH0.
+ * | | |11100 = Connect to PWM1_CH2.
+ * |[20:16] |CH2_SEL |Channel 2 Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 2.
+ * | | |Software can configure the peripheral setting by CH2_SEL.
+ * | | |The channel configuration is the same as CH1_SEL field.
+ * | | |Please refer to the explanation of CH1_SEL.
+ * |[28:24] |CH3_SEL |Channel 3 Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 3.
+ * | | |Software can configure the peripheral setting by CH3_SEL.
+ * | | |The channel configuration is the same as CH1_SEL field.
+ * | | |Please refer to the explanation of CH1_SEL.
+ */
+ __IO uint32_t DSSR0;
+
+ /**
+ * DSSR1
+ * ===================================================================================================
+ * Offset: 0x08 DMA Service Selection Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |CH4_SEL |Channel 4 Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 4.
+ * | | |Software can configure the peripheral by setting CH4_SEL.
+ * | | |The channel configuration is the same as CH1_SEL field.
+ * | | |Please refer to the explanation of CH1_SEL.
+ * |[12:8] |CH5_SEL |Channel 5 Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 5.
+ * | | |Software can configure the peripheral setting by CH5_SEL.
+ * | | |The channel configuration is the same as CH1_SEL field.
+ * | | |Please refer to the explanation of CH1_SEL.
+ * |[20:16] |CH6_SEL |Channel 6 Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 6.
+ * | | |Software can configure the peripheral setting by CH6_SEL.
+ * | | |The channel configuration is the same as CH1_SEL field.
+ * | | |Please refer to the explanation of CH1_SEL.
+ */
+ __IO uint32_t DSSR1;
+
+ /**
+ * GCRISR
+ * ===================================================================================================
+ * Offset: 0x0C DMA Global Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INTR0 |Interrupt Pin Status Of Channel 0 (Read Only)
+ * | | |This bit is the Interrupt pin status of DMA channel0.
+ * | | |Note: This bit is read only
+ * |[1] |INTR1 |Interrupt Pin Status Of Channel 1 (Read Only)
+ * | | |This bit is the Interrupt pin status of DMA channel1.
+ * | | |Note: This bit is read only
+ * |[2] |INTR2 |Interrupt Pin Status Of Channel 2 (Read Only)
+ * | | |This bit is the Interrupt pin status of DMA channel2.
+ * | | |Note: This bit is read only
+ * |[3] |INTR3 |Interrupt Pin Status Of Channel 3 (Read Only)
+ * | | |This bit is the Interrupt pin status of DMA channel3.
+ * | | |Note: This bit is read only
+ * |[4] |INTR4 |Interrupt Pin Status Of Channel 4 (Read Only)
+ * | | |This bit is the Interrupt pin status of DMA channel4.
+ * | | |Note: This bit is read only
+ * |[5] |INTR5 |Interrupt Pin Status Of Channel 5 (Read Only)
+ * | | |This bit is the Interrupt pin status of DMA channel4.
+ * | | |Note: This bit is read only
+ * |[6] |INTR6 |Interrupt Pin Status Of Channel 6 (Read Only)
+ * | | |This bit is the Interrupt pin status of DMA channel4.
+ * | | |Note: This bit is read only
+ * |[16] |CRC_INTR |Interrupt Pin Status Of CRC Controller
+ * | | |This bit is the Interrupt status of CRC controller
+ * | | |Note: This bit is read only
+ */
+ __I uint32_t GCRISR;
+
+} DMA_GCR_T;
+
+
+typedef struct {
+ /**
+ * CSR
+ * ===================================================================================================
+ * Offset: 0x00 PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PDMACEN |PDMA Channel Enable
+ * | | |Setting this bit to "1" enables PDMA's operation.
+ * | | |If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
+ * | | |Note: SW_RST will clear this bit.
+ * |[1] |SW_RST |Software Engine Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the internal state machine and pointers.
+ * | | |The contents of control register will not be cleared.
+ * | | |This bit will be auto cleared after few clock cycles.
+ * |[3:2] |MODE_SEL |PDMA Mode Select
+ * | | |00 = Memory to Memory mode (Memory-to-Memory).
+ * | | |01 = IP to Memory mode (APB-to-Memory)
+ * | | |10 = Memory to IP mode (Memory-to-APB).
+ * | | |11 = Reserved.
+ * |[5:4] |SAD_SEL |Transfer Source Address Direction Selection
+ * | | |00 = Transfer Source address is incremented successively.
+ * | | |01 = Reserved.
+ * | | |10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations).
+ * | | |11 = Transfer Source address is wrap around (When the PDMA_CBCR is equal to zero, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically.
+ * | | |PDMA will start another transfer without software trigger until PDMA_EN disabled.
+ * | | |When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address).
+ * |[7:6] |DAD_SEL |Transfer Destination Address Direction Selection
+ * | | |00 = Transfer Destination address is incremented successively
+ * | | |01 = Reserved.
+ * | | |10 = Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
+ * | | |11 = Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to zero, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically.
+ * | | |PDMA will start another transfer without software trigger until PDMA_EN disabled.
+ * | | |When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address).
+ * |[12] |TO_EN |Time-Out Enable
+ * | | |This bit will enable PDMA internal counter. While this counter counts to zero, the TO_IS will be set.
+ * | | |0 = PDMA internal counter Disabled.
+ * | | |1 = PDMA internal counter Enabled.
+ * |[20:19] |APB_TWS |Peripheral Transfer Width Selection
+ * | | |00 = One word (32 bits) is transferred for every PDMA operation.
+ * | | |01 = One byte (8 bits) is transferred for every PDMA operation.
+ * | | |10 = One half-word (16 bits) is transferred for every PDMA operation.
+ * | | |11 = Reserved.
+ * | | |Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
+ * |[23] |TRIG_EN |TRIG_EN
+ * | | |0 = No effect.
+ * | | |1 = PDMA data read or write transfer Enabled.
+ * | | |Note1: When PDMA transfer completed, this bit will be cleared automatically.
+ * | | |Note2: If the bus error occurs, all PDMA transfer will be stopped.
+ * | | |Software must reset all PDMA channel, and then trig again.
+ */
+ __IO uint32_t CSR;
+
+ /**
+ * SAR
+ * ===================================================================================================
+ * Offset: 0x04 PDMA Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDMA_SAR |PDMA Transfer Source Address Register
+ * | | |This field indicates a 32-bit source address of PDMA.
+ * | | |Note: The source address must be word alignment.
+ */
+ __IO uint32_t SAR;
+
+ /**
+ * DAR
+ * ===================================================================================================
+ * Offset: 0x08 PDMA Destination Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDMA_DAR |PDMA Transfer Destination Address Register
+ * | | |This field indicates a 32-bit destination address of PDMA.
+ * | | |Note : The destination address must be word alignment
+ */
+ __IO uint32_t DAR;
+
+ /**
+ * BCR
+ * ===================================================================================================
+ * Offset: 0x0C PDMA Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PDMA_BCR |PDMA Transfer Byte Count Register
+ * | | |This field indicates a 16-bit transfer byte count of PDMA.
+ * | | |Note: In Memory-to-memory (PDMA_CSR [MODE_SEL] = 00) mode, the transfer byte count must be word alignment.
+ */
+ __IO uint32_t BCR;
+ uint32_t RESERVE0[1];
+
+
+ /**
+ * CSAR
+ * ===================================================================================================
+ * Offset: 0x14 PDMA Current Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDMA_CSAR |PDMA Current Source Address Register (Read Only)
+ * | | |This field indicates the source address where the PDMA transfer is just occurring.
+ */
+ __I uint32_t CSAR;
+
+ /**
+ * CDAR
+ * ===================================================================================================
+ * Offset: 0x18 PDMA Current Destination Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDMA_CDAR |PDMA Current Destination Address Register (Read Only)
+ * | | |This field indicates the destination address where the PDMA transfer is just occurring.
+ */
+ __I uint32_t CDAR;
+
+ /**
+ * CBCR
+ * ===================================================================================================
+ * Offset: 0x1C PDMA Current Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |PDMA_CBCR |PDMA Current Byte Count Register (Read Only)
+ * | | |This field indicates the current remained byte count of PDMA.
+ * | | |Note: These fields will be changed when PDMA finish data transfer (data transfer to destination address),
+ */
+ __I uint32_t CBCR;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x20 PDMA Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TABORT_IE |PDMA Read/Write Target Abort Interrupt Enable
+ * | | |0 = Target abort interrupt generation Disabled during PDMA transfer.
+ * | | |1 = Target abort interrupt generation Enabled during PDMA transfer.
+ * |[1] |TD_IE |PDMA Transfer Done Interrupt Enable
+ * | | |0 = Interrupt generator Disabled when PDMA transfer is done.
+ * | | |1 = Interrupt generator Enabled when PDMA transfer is done.
+ * |[5:2] |WRA_BCR_IE|Wrap Around Byte Count Interrupt Enable
+ * | | |0001 = Interrupt enable of PDMA_CBCR equals 0
+ * | | |0100 = Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR.
+ * |[6] |TO_IE |Time-Out Interrupt Enable
+ * | | |0 = Time-out interrupt Disabled.
+ * | | |1 = Time-out interrupt Enabled.
+ */
+ __IO uint32_t IER;
+
+ /**
+ * ISR
+ * ===================================================================================================
+ * Offset: 0x24 PDMA Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TABORT_IS |PDMA Read/Write Target Abort Interrupt Status Flag
+ * | | |0 = No bus ERROR response received.
+ * | | |1 = Bus ERROR response received.
+ * | | |Note1: This bit is cleared by writing "1" to itself.
+ * | | |Note2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened.
+ * | | |PDMA controller will stop transfer and respond this event to software then go to IDLE state.
+ * | | |When target abort occurred, software must reset PDMA controller, and then transfer those data again.
+ * |[1] |TD_IS |Transfer Done Interrupt Status Flag
+ * | | |This bit indicates that PDMA has finished all transfer.
+ * | | |0 = Not finished yet.
+ * | | |1 = Done.
+ * | | |Note: This bit is cleared by writing "1" to itself.
+ * |[5:2] |WRA_BCR_IS|Wrap Around Transfer Byte Count Interrupt Status Flag
+ * | | |WAR_)CR_IS [0] (xxx1) = PDMA_CBCR equal 0 flag.
+ * | | |WAR_BCR_IS [2] (x1xx) = PDMA_CBCR equal 1/2 PDMA_BCR flag.
+ * | | |Note: Each bit is cleared by writing "1" to itself.
+ * | | |This field is only valid in wrap around mode.
+ * | | |(PDMA_CSR[DAD_SEL] =11 or PDMA_CSR[SAD_SEL] =11).
+ * |[6] |TO_IS |Time-Out Interrupt Status Flag
+ * | | |This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.
+ * | | |0 = No time-out flag.
+ * | | |1 = Time-out flag.
+ * | | |Note: This bit is cleared by writing "1" to itself.
+ */
+ __IO uint32_t ISR;
+
+ /**
+ * TCR
+ * ===================================================================================================
+ * Offset: 0x28 PDMA Timer Counter Setting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PDMA_TCR |PDMA Timer Count Setting Register
+ * | | |Each PDMA channel contains an internal counter.
+ * | | |The internal counter loads the value of PDAM_TCR and starts counting down when setting PDMA_CSRx [TO_EN] register.
+ * | | |PDMA will request interrupt when this internal counter reaches zero and PDMA_IERx[TO_IE] is high.
+ * | | |This internal counter will reload and start counting when completing each peripheral request service.
+ */
+ __IO uint32_t TCR;
+
+} PDMA_T;
+
+
+
+typedef struct {
+
+
+ /**
+ * CSR
+ * ===================================================================================================
+ * Offset: 0x00 VDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VDMACEN |VDMA Channel Enable
+ * | | |Setting this bit to "1" enables VDMA's operation.
+ * | | |If this bit is cleared, VDMA will ignore all VDMA request and force Bus Master into IDLE state.
+ * | | |Note: SW_RST will clear this bit.
+ * |[1] |SW_RST |Software Engine Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the internal state machine and pointers.
+ * | | |The contents of control register will not be cleared.
+ * | | |This bit will be auto cleared after few clock cycles.
+ * |[10] |STRIDE_EN |Stride Mode Enable
+ * | | |0 = Stride transfer mode Disabled.
+ * | | |1 = Stride transfer mode Enabled.
+ * |[11] |DIR_SEL |Transfer Source/Destination Address Direction Select
+ * | | |0 = Transfer address is incremented successively.
+ * | | |1 = Transfer address is decremented successively.
+ * |[23] |TRIG_EN |TRIG_EN
+ * | | |0 = No effect.
+ * | | |1 = VDMA data read or write transfer Enabled.
+ * | | |Note1: When VDMA transfer is completed, this bit will be cleared automatically.
+ * | | |Note2: If the bus error occurs, all VDMA transfer will be stopped.
+ * | | |Software must reset all VDMA channel, and then trig again.
+ */
+ __IO uint32_t CSR;
+
+ /**
+ * SAR
+ * ===================================================================================================
+ * Offset: 0x04 VDMA Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |VDMA_SAR |VDMA Transfer Source Address Register
+ * | | |This field indicates a 32-bit source address of VDMA.
+ */
+ __IO uint32_t SAR;
+
+ /**
+ * DAR
+ * ===================================================================================================
+ * Offset: 0x08 VDMA Destination Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |VDMA_DAR |VDMA Transfer Destination Address Register
+ * | | |This field indicates a 32-bit destination address of VDMA.
+ */
+ __IO uint32_t DAR;
+
+ /**
+ * BCR
+ * ===================================================================================================
+ * Offset: 0x0C VDMA Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |VDMA_BCR |VDMA Transfer Byte Count Register
+ * | | |This field indicates a 16-bit transfer byte count of VDMA.
+ * | | |Note: In Stride Enable mode (VDMA_CSR [10] = "0"]), the transfer byte count (VDMA_BCR) must be an integer multiple of STBC (VDMA_SASOCR [31:16]).
+ */
+ __IO uint32_t BCR;
+ uint32_t RESERVE0[1];
+
+
+ /**
+ * CSAR
+ * ===================================================================================================
+ * Offset: 0x14 VDMA Current Source Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |VDMA_CSAR |VDMA Current Source Address Register (Read Only)
+ * | | |This field indicates the source address where the VDMA transfer is just occurring.
+ */
+ __I uint32_t CSAR;
+
+ /**
+ * CDAR
+ * ===================================================================================================
+ * Offset: 0x18 VDMA Current Destination Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |VDMA_CDAR |VDMA Current Destination Address Register (Read Only)
+ * | | |This field indicates the destination address where the VDMA transfer is just occurring.
+ */
+ __I uint32_t CDAR;
+
+ /**
+ * CBCR
+ * ===================================================================================================
+ * Offset: 0x1C VDMA Current Transfer Byte Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |VDMA_CBCR |VDMA Current Byte Count Register (Read Only)
+ * | | |This field indicates the current remained byte count of VDMA.
+ */
+ __I uint32_t CBCR;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x20 VDMA Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TABORT_IE |VDMA Read/Write Target Abort Interrupt Enable
+ * | | |0 = Disabled target abort interrupt generation during VDMA transfer.
+ * | | |1 = Enabled target abort interrupt generation during VDMA transfer.
+ * |[1] |TD_IE |VDMA Transfer Done Interrupt Enable
+ * | | |0 = Disabled interrupt generator during VDMA transfer done.
+ * | | |1 = Enabled interrupt generator during VDMA transfer done.
+ */
+ __IO uint32_t IER;
+
+ /**
+ * ISR
+ * ===================================================================================================
+ * Offset: 0x24 VDMA Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TABORT_IS |VDMA Read/Write Target Abort Interrupt Status Flag
+ * | | |0 = No bus ERROR response received.
+ * | | |1 = Bus ERROR response received.
+ * | | |Note1: This bit is cleared by writing "1" to itself.
+ * | | |Note2: The VDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened.
+ * | | |VDMA controller will stop transfer and respond this event to software then go to IDLE state.
+ * | | |When target abort occurred, software must reset VDMA controller, and then transfer those data again.
+ * |[1] |TD_IS |Transfer Done Interrupt Status Flag
+ * | | |This bit indicates that VDMA has finished all transfer.
+ * | | |0 = Not finished yet.
+ * | | |1 = Done.
+ * | | |Note: This bit is cleared by writing "1" to itself.
+ */
+ __IO uint32_t ISR;
+ uint32_t RESERVE1[1];
+
+
+ /**
+ * SASOCR
+ * ===================================================================================================
+ * Offset: 0x2C VDMA Source Address Stride Offset Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |SASTOBL |VDMA Source Address Stride Offset Byte Length
+ * | | |The 16-bit register defines the source address stride transfer offset count of each row.
+ * |[31:16] |STBC |VDMA Stride Transfer Byte Count
+ * | | |The 16-bit register defines the stride transfer byte count of each row.
+ */
+ __IO uint32_t SASOCR;
+
+ /**
+ * DASOCR
+ * ===================================================================================================
+ * Offset: 0x30 VDMA Destination Address Stride Offset Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DASTOBL |VDMA Destination Address Stride Offset Byte Length
+ * | | |The 16-bit register defines the destination address stride transfer offset count of each row.
+ */
+ __IO uint32_t DASOCR;
+
+} VDMA_T;
+
+
+/**
+ @addtogroup DMA_CRC_CONST DMA_CRC Bit Field Definition
+ Constant Definitions for DMA_CRC Controller
+@{ */
+
+#define DMA_CRC_CTL_CRCCEN_Pos (0) /*!< DMA_CRC_T::CTL: CRCCEN Position */
+#define DMA_CRC_CTL_CRCCEN_Msk (0x1ul << DMA_CRC_CTL_CRCCEN_Pos) /*!< DMA_CRC_T::CTL: CRCCEN Mask */
+
+#define DMA_CRC_CTL_CRC_RST_Pos (1) /*!< DMA_CRC_T::CTL: CRC_RST Position */
+#define DMA_CRC_CTL_CRC_RST_Msk (0x1ul << DMA_CRC_CTL_CRC_RST_Pos) /*!< DMA_CRC_T::CTL: CRC_RST Mask */
+
+#define DMA_CRC_CTL_TRIG_EN_Pos (23) /*!< DMA_CRC_T::CTL: TRIG_EN Position */
+#define DMA_CRC_CTL_TRIG_EN_Msk (0x1ul << DMA_CRC_CTL_TRIG_EN_Pos) /*!< DMA_CRC_T::CTL: TRIG_EN Mask */
+
+#define DMA_CRC_CTL_WDATA_RVS_Pos (24) /*!< DMA_CRC_T::CTL: WDATA_RVS Position */
+#define DMA_CRC_CTL_WDATA_RVS_Msk (0x1ul << DMA_CRC_CTL_WDATA_RVS_Pos) /*!< DMA_CRC_T::CTL: WDATA_RVS Mask */
+
+#define DMA_CRC_CTL_CHECKSUM_RVS_Pos (25) /*!< DMA_CRC_T::CTL: CHECKSUM_RVS Position */
+#define DMA_CRC_CTL_CHECKSUM_RVS_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_RVS_Pos) /*!< DMA_CRC_T::CTL: CHECKSUM_RVS Mask */
+
+#define DMA_CRC_CTL_WDATA_COM_Pos (26) /*!< DMA_CRC_T::CTL: WDATA_COM Position */
+#define DMA_CRC_CTL_WDATA_COM_Msk (0x1ul << DMA_CRC_CTL_WDATA_COM_Pos) /*!< DMA_CRC_T::CTL: WDATA_COM Mask */
+
+#define DMA_CRC_CTL_CHECKSUM_COM_Pos (27) /*!< DMA_CRC_T::CTL: CHECKSUM_COM Position */
+#define DMA_CRC_CTL_CHECKSUM_COM_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_COM_Pos) /*!< DMA_CRC_T::CTL: CHECKSUM_COM Mask */
+
+#define DMA_CRC_CTL_CPU_WDLEN_Pos (28) /*!< DMA_CRC_T::CTL: CPU_WDLEN Position */
+#define DMA_CRC_CTL_CPU_WDLEN_Msk (0x3ul << DMA_CRC_CTL_CPU_WDLEN_Pos) /*!< DMA_CRC_T::CTL: CPU_WDLEN Mask */
+
+#define DMA_CRC_CTL_CRC_MODE_Pos (30) /*!< DMA_CRC_T::CTL: CRC_MODE Position */
+#define DMA_CRC_CTL_CRC_MODE_Msk (0x3ul << DMA_CRC_CTL_CRC_MODE_Pos) /*!< DMA_CRC_T::CTL: CRC_MODE Mask */
+
+#define DMA_CRC_DMASAR_CRC_DMASAR_Pos (0) /*!< DMA_CRC_T::DMASAR: CRC_DMASAR Position */
+#define DMA_CRC_DMASAR_CRC_DMASAR_Msk (0xfffffffful << DMA_CRC_DMASAR_CRC_DMASAR_Pos) /*!< DMA_CRC_T::DMASAR: CRC_DMASAR Mask */
+
+#define DMA_CRC_DMABCR_CRC_DMABCR_Pos (0) /*!< DMA_CRC_T::DMABCR: CRC_DMABCR Position */
+#define DMA_CRC_DMABCR_CRC_DMABCR_Msk (0xfffful << DMA_CRC_DMABCR_CRC_DMABCR_Pos) /*!< DMA_CRC_T::DMABCR: CRC_DMABCR Mask */
+
+#define DMA_CRC_DMACSAR_CRC_DMACSAR_Pos (0) /*!< DMA_CRC_T::DMACSAR: CRC_DMACSAR Position */
+#define DMA_CRC_DMACSAR_CRC_DMACSAR_Msk (0xfffffffful << DMA_CRC_DMACSAR_CRC_DMACSAR_Pos) /*!< DMA_CRC_T::DMACSAR: CRC_DMACSAR Mask */
+
+#define DMA_CRC_DMACBCR_CRC_DMACBCR_Pos (0) /*!< DMA_CRC_T::DMACBCR: CRC_DMACBCR Position */
+#define DMA_CRC_DMACBCR_CRC_DMACBCR_Msk (0xfffful << DMA_CRC_DMACBCR_CRC_DMACBCR_Pos) /*!< DMA_CRC_T::DMACBCR: CRC_DMACBCR Mask */
+
+#define DMA_CRC_DMAIER_TABORT_IE_Pos (0) /*!< DMA_CRC_T::DMAIER: TABORT_IE Position */
+#define DMA_CRC_DMAIER_TABORT_IE_Msk (0x1ul << DMA_CRC_DMAIER_TABORT_IE_Pos) /*!< DMA_CRC_T::DMAIER: TABORT_IE Mask */
+
+#define DMA_CRC_DMAIER_BLKD_IE_Pos (1) /*!< DMA_CRC_T::DMAIER: BLKD_IE Position */
+#define DMA_CRC_DMAIER_BLKD_IE_Msk (0x1ul << DMA_CRC_DMAIER_BLKD_IE_Pos) /*!< DMA_CRC_T::DMAIER: BLKD_IE Mask */
+
+#define DMA_CRC_DMAISR_TABORT_IF_Pos (0) /*!< DMA_CRC_T::DMAISR: TABORT_IF Position */
+#define DMA_CRC_DMAISR_TABORT_IF_Msk (0x1ul << DMA_CRC_DMAISR_TABORT_IF_Pos) /*!< DMA_CRC_T::DMAISR: TABORT_IF Mask */
+
+#define DMA_CRC_DMAISR_BLKD_IF_Pos (1) /*!< DMA_CRC_T::DMAISR: BLKD_IF Position */
+#define DMA_CRC_DMAISR_BLKD_IF_Msk (0x1ul << DMA_CRC_DMAISR_BLKD_IF_Pos) /*!< DMA_CRC_T::DMAISR: BLKD_IF Mask */
+
+#define DMA_CRC_WDATA_CRC_WDATA_Pos (0) /*!< DMA_CRC_T::WDATA: CRC_WDATA Position */
+#define DMA_CRC_WDATA_CRC_WDATA_Msk (0xfffffffful << DMA_CRC_WDATA_CRC_WDATA_Pos) /*!< DMA_CRC_T::WDATA: CRC_WDATA Mask */
+
+#define DMA_CRC_SEED_CRC_SEED_Pos (0) /*!< DMA_CRC_T::SEED: CRC_SEED Position */
+#define DMA_CRC_SEED_CRC_SEED_Msk (0xfffffffful << DMA_CRC_SEED_CRC_SEED_Pos) /*!< DMA_CRC_T::SEED: CRC_SEED Mask */
+
+#define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos (0) /*!< DMA_CRC_T::CHECKSUM: CRC_CHECKSUM Position*/
+#define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos) /*!< DMA_CRC_T::CHECKSUM: CRC_CHECKSUM Mask */
+
+/**@}*/ /* DMA_CRC_CONST */
+
+
+/**
+ @addtogroup DMA_GCR_CONST DMA_GCR Bit Field Definition
+ Constant Definitions for DMA_GCR Controller
+@{ */
+
+#define DMA_GCR_GCRCSR_CLK0_EN_Pos (8) /*!< DMA_GCR_T::GCRCSR: CLK0_EN Position */
+#define DMA_GCR_GCRCSR_CLK0_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK0_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CLK0_EN Mask */
+
+#define DMA_GCR_GCRCSR_CLK1_EN_Pos (9) /*!< DMA_GCR_T::GCRCSR: CLK1_EN Position */
+#define DMA_GCR_GCRCSR_CLK1_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK1_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CLK1_EN Mask */
+
+#define DMA_GCR_GCRCSR_CLK2_EN_Pos (10) /*!< DMA_GCR_T::GCRCSR: CLK2_EN Position */
+#define DMA_GCR_GCRCSR_CLK2_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK2_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CLK2_EN Mask */
+
+#define DMA_GCR_GCRCSR_CLK3_EN_Pos (11) /*!< DMA_GCR_T::GCRCSR: CLK3_EN Position */
+#define DMA_GCR_GCRCSR_CLK3_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK3_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CLK3_EN Mask */
+
+#define DMA_GCR_GCRCSR_CLK4_EN_Pos (12) /*!< DMA_GCR_T::GCRCSR: CLK4_EN Position */
+#define DMA_GCR_GCRCSR_CLK4_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK4_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CLK4_EN Mask */
+
+#define DMA_GCR_GCRCSR_CLK5_EN_Pos (13) /*!< DMA_GCR_T::GCRCSR: CLK5_EN Position */
+#define DMA_GCR_GCRCSR_CLK5_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK5_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CLK5_EN Mask */
+
+#define DMA_GCR_GCRCSR_CLK6_EN_Pos (14) /*!< DMA_GCR_T::GCRCSR: CLK6_EN Position */
+#define DMA_GCR_GCRCSR_CLK6_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK6_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CLK6_EN Mask */
+
+#define DMA_GCR_GCRCSR_CRC_CLK_EN_Pos (24) /*!< DMA_GCR_T::GCRCSR: CRC_CLK_EN Position */
+#define DMA_GCR_GCRCSR_CRC_CLK_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CRC_CLK_EN_Pos) /*!< DMA_GCR_T::GCRCSR: CRC_CLK_EN Mask */
+
+#define DMA_GCR_DSSR0_CH1_SEL_Pos (8) /*!< DMA_GCR_T::DSSR0: CH1_SEL Position */
+#define DMA_GCR_DSSR0_CH1_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH1_SEL_Pos) /*!< DMA_GCR_T::DSSR0: CH1_SEL Mask */
+
+#define DMA_GCR_DSSR0_CH2_SEL_Pos (16) /*!< DMA_GCR_T::DSSR0: CH2_SEL Position */
+#define DMA_GCR_DSSR0_CH2_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH2_SEL_Pos) /*!< DMA_GCR_T::DSSR0: CH2_SEL Mask */
+
+#define DMA_GCR_DSSR0_CH3_SEL_Pos (24) /*!< DMA_GCR_T::DSSR0: CH3_SEL Position */
+#define DMA_GCR_DSSR0_CH3_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH3_SEL_Pos) /*!< DMA_GCR_T::DSSR0: CH3_SEL Mask */
+
+#define DMA_GCR_DSSR1_CH4_SEL_Pos (0) /*!< DMA_GCR_T::DSSR1: CH4_SEL Position */
+#define DMA_GCR_DSSR1_CH4_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH4_SEL_Pos) /*!< DMA_GCR_T::DSSR1: CH4_SEL Mask */
+
+#define DMA_GCR_DSSR1_CH5_SEL_Pos (8) /*!< DMA_GCR_T::DSSR1: CH5_SEL Position */
+#define DMA_GCR_DSSR1_CH5_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH5_SEL_Pos) /*!< DMA_GCR_T::DSSR1: CH5_SEL Mask */
+
+#define DMA_GCR_DSSR1_CH6_SEL_Pos (16) /*!< DMA_GCR_T::DSSR1: CH6_SEL Position */
+#define DMA_GCR_DSSR1_CH6_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH6_SEL_Pos) /*!< DMA_GCR_T::DSSR1: CH6_SEL Mask */
+
+#define DMA_GCR_GCRISR_INTR0_Pos (0) /*!< DMA_GCR_T::GCRISR: INTR0 Position */
+#define DMA_GCR_GCRISR_INTR0_Msk (0x1ul << DMA_GCR_GCRISR_INTR0_Pos) /*!< DMA_GCR_T::GCRISR: INTR0 Mask */
+
+#define DMA_GCR_GCRISR_INTR1_Pos (1) /*!< DMA_GCR_T::GCRISR: INTR1 Position */
+#define DMA_GCR_GCRISR_INTR1_Msk (0x1ul << DMA_GCR_GCRISR_INTR1_Pos) /*!< DMA_GCR_T::GCRISR: INTR1 Mask */
+
+#define DMA_GCR_GCRISR_INTR2_Pos (2) /*!< DMA_GCR_T::GCRISR: INTR2 Position */
+#define DMA_GCR_GCRISR_INTR2_Msk (0x1ul << DMA_GCR_GCRISR_INTR2_Pos) /*!< DMA_GCR_T::GCRISR: INTR2 Mask */
+
+#define DMA_GCR_GCRISR_INTR3_Pos (3) /*!< DMA_GCR_T::GCRISR: INTR3 Position */
+#define DMA_GCR_GCRISR_INTR3_Msk (0x1ul << DMA_GCR_GCRISR_INTR3_Pos) /*!< DMA_GCR_T::GCRISR: INTR3 Mask */
+
+#define DMA_GCR_GCRISR_INTR4_Pos (4) /*!< DMA_GCR_T::GCRISR: INTR4 Position */
+#define DMA_GCR_GCRISR_INTR4_Msk (0x1ul << DMA_GCR_GCRISR_INTR4_Pos) /*!< DMA_GCR_T::GCRISR: INTR4 Mask */
+
+#define DMA_GCR_GCRISR_INTR5_Pos (5) /*!< DMA_GCR_T::GCRISR: INTR5 Position */
+#define DMA_GCR_GCRISR_INTR5_Msk (0x1ul << DMA_GCR_GCRISR_INTR5_Pos) /*!< DMA_GCR_T::GCRISR: INTR5 Mask */
+
+#define DMA_GCR_GCRISR_INTR6_Pos (6) /*!< DMA_GCR_T::GCRISR: INTR6 Position */
+#define DMA_GCR_GCRISR_INTR6_Msk (0x1ul << DMA_GCR_GCRISR_INTR6_Pos) /*!< DMA_GCR_T::GCRISR: INTR6 Mask */
+
+#define DMA_GCR_GCRISR_CRC_INTR_Pos (16) /*!< DMA_GCR_T::GCRISR: CRC_INTR Position */
+#define DMA_GCR_GCRISR_CRC_INTR_Msk (0x1ul << DMA_GCR_GCRISR_CRC_INTR_Pos) /*!< DMA_GCR_T::GCRISR: CRC_INTR Mask */
+
+/**@}*/ /* DMA_GCR_CONST */
+
+
+/**
+ @addtogroup PDMA_CONST PDMA Bit Field Definition
+ Constant Definitions for PDMA Controller
+@{ */
+
+#define PDMA_CSR_PDMACEN_Pos (0) /*!< PDMA_T::CSR: PDMACEN Position */
+#define PDMA_CSR_PDMACEN_Msk (0x1ul << PDMA_CSR_PDMACEN_Pos) /*!< PDMA_T::CSR: PDMACEN Mask */
+
+#define PDMA_CSR_SW_RST_Pos (1) /*!< PDMA_T::CSR: SW_RST Position */
+#define PDMA_CSR_SW_RST_Msk (0x1ul << PDMA_CSR_SW_RST_Pos) /*!< PDMA_T::CSR: SW_RST Mask */
+
+#define PDMA_CSR_MODE_SEL_Pos (2) /*!< PDMA_T::CSR: MODE_SEL Position */
+#define PDMA_CSR_MODE_SEL_Msk (0x3ul << PDMA_CSR_MODE_SEL_Pos) /*!< PDMA_T::CSR: MODE_SEL Mask */
+
+#define PDMA_CSR_SAD_SEL_Pos (4) /*!< PDMA_T::CSR: SAD_SEL Position */
+#define PDMA_CSR_SAD_SEL_Msk (0x3ul << PDMA_CSR_SAD_SEL_Pos) /*!< PDMA_T::CSR: SAD_SEL Mask */
+
+#define PDMA_CSR_DAD_SEL_Pos (6) /*!< PDMA_T::CSR: DAD_SEL Position */
+#define PDMA_CSR_DAD_SEL_Msk (0x3ul << PDMA_CSR_DAD_SEL_Pos) /*!< PDMA_T::CSR: DAD_SEL Mask */
+
+#define PDMA_CSR_TO_EN_Pos (12) /*!< PDMA_T::CSR: TO_EN Position */
+#define PDMA_CSR_TO_EN_Msk (0x1ul << PDMA_CSR_TO_EN_Pos) /*!< PDMA_T::CSR: TO_EN Mask */
+
+#define PDMA_CSR_APB_TWS_Pos (19) /*!< PDMA_T::CSR: APB_TWS Position */
+#define PDMA_CSR_APB_TWS_Msk (0x3ul << PDMA_CSR_APB_TWS_Pos) /*!< PDMA_T::CSR: APB_TWS Mask */
+
+#define PDMA_CSR_TRIG_EN_Pos (23) /*!< PDMA_T::CSR: TRIG_EN Position */
+#define PDMA_CSR_TRIG_EN_Msk (0x1ul << PDMA_CSR_TRIG_EN_Pos) /*!< PDMA_T::CSR: TRIG_EN Mask */
+
+#define PDMA_SAR_PDMA_SAR_Pos (0) /*!< PDMA_T::SAR: PDMA_SAR Position */
+#define PDMA_SAR_PDMA_SAR_Msk (0xfffffffful << PDMA_SAR_PDMA_SAR_Pos) /*!< PDMA_T::SAR: PDMA_SAR Mask */
+
+#define PDMA_DAR_PDMA_DAR_Pos (0) /*!< PDMA_T::DAR: PDMA_DAR Position */
+#define PDMA_DAR_PDMA_DAR_Msk (0xfffffffful << PDMA_DAR_PDMA_DAR_Pos) /*!< PDMA_T::DAR: PDMA_DAR Mask */
+
+#define PDMA_BCR_PDMA_BCR_Pos (0) /*!< PDMA_T::BCR: PDMA_BCR Position */
+#define PDMA_BCR_PDMA_BCR_Msk (0xfffful << PDMA_BCR_PDMA_BCR_Pos) /*!< PDMA_T::BCR: PDMA_BCR Mask */
+
+#define PDMA_CSAR_PDMA_CSAR_Pos (0) /*!< PDMA_T::CSAR: PDMA_CSAR Position */
+#define PDMA_CSAR_PDMA_CSAR_Msk (0xfffffffful << PDMA_CSAR_PDMA_CSAR_Pos) /*!< PDMA_T::CSAR: PDMA_CSAR Mask */
+
+#define PDMA_CDAR_PDMA_CDAR_Pos (0) /*!< PDMA_T::CDAR: PDMA_CDAR Position */
+#define PDMA_CDAR_PDMA_CDAR_Msk (0xfffffffful << PDMA_CDAR_PDMA_CDAR_Pos) /*!< PDMA_T::CDAR: PDMA_CDAR Mask */
+
+#define PDMA_CBCR_PDMA_CBCR_Pos (0) /*!< PDMA_T::CBCR: PDMA_CBCR Position */
+#define PDMA_CBCR_PDMA_CBCR_Msk (0xfffffful << PDMA_CBCR_PDMA_CBCR_Pos) /*!< PDMA_T::CBCR: PDMA_CBCR Mask */
+
+#define PDMA_IER_TABORT_IE_Pos (0) /*!< PDMA_T::IER: TABORT_IE Position */
+#define PDMA_IER_TABORT_IE_Msk (0x1ul << PDMA_IER_TABORT_IE_Pos) /*!< PDMA_T::IER: TABORT_IE Mask */
+
+#define PDMA_IER_TD_IE_Pos (1) /*!< PDMA_T::IER: TD_IE Position */
+#define PDMA_IER_TD_IE_Msk (0x1ul << PDMA_IER_TD_IE_Pos) /*!< PDMA_T::IER: TD_IE Mask */
+
+#define PDMA_IER_WRA_BCR_IE_Pos (2) /*!< PDMA_T::IER: WRA_BCR_IE Position */
+#define PDMA_IER_WRA_BCR_IE_Msk (0xful << PDMA_IER_WRA_BCR_IE_Pos) /*!< PDMA_T::IER: WRA_BCR_IE Mask */
+
+#define PDMA_IER_TO_IE_Pos (6) /*!< PDMA_T::IER: TO_IE Position */
+#define PDMA_IER_TO_IE_Msk (0x1ul << PDMA_IER_TO_IE_Pos) /*!< PDMA_T::IER: TO_IE Mask */
+
+#define PDMA_ISR_TABORT_IS_Pos (0) /*!< PDMA_T::ISR: TABORT_IS Position */
+#define PDMA_ISR_TABORT_IS_Msk (0x1ul << PDMA_ISR_TABORT_IS_Pos) /*!< PDMA_T::ISR: TABORT_IS Mask */
+
+#define PDMA_ISR_TD_IS_Pos (1) /*!< PDMA_T::ISR: TD_IS Position */
+#define PDMA_ISR_TD_IS_Msk (0x1ul << PDMA_ISR_TD_IS_Pos) /*!< PDMA_T::ISR: TD_IS Mask */
+
+#define PDMA_ISR_WRA_BCR_IS_Pos (2) /*!< PDMA_T::ISR: WRA_BCR_IS Position */
+#define PDMA_ISR_WRA_BCR_IS_Msk (0xful << PDMA_ISR_WRA_BCR_IS_Pos) /*!< PDMA_T::ISR: WRA_BCR_IS Mask */
+
+#define PDMA_ISR_TO_IS_Pos (6) /*!< PDMA_T::ISR: TO_IS Position */
+#define PDMA_ISR_TO_IS_Msk (0x1ul << PDMA_ISR_TO_IS_Pos) /*!< PDMA_T::ISR: TO_IS Mask */
+
+#define PDMA_TCR_PDMA_TCR_Pos (0) /*!< PDMA_T::TCR: PDMA_TCR Position */
+#define PDMA_TCR_PDMA_TCR_Msk (0xfffful << PDMA_TCR_PDMA_TCR_Pos) /*!< PDMA_T::TCR: PDMA_TCR Mask */
+
+/**@}*/ /* PDMA_CONST */
+
+
+/**
+ @addtogroup VDMA_CONST VDMA Bit Field Definition
+ Constant Definitions for VDMA Controller
+@{ */
+
+#define VDMA_CSR_VDMACEN_Pos (0) /*!< VDMA_T::CSR: VDMACEN Position */
+#define VDMA_CSR_VDMACEN_Msk (0x1ul << VDMA_CSR_VDMACEN_Pos) /*!< VDMA_T::CSR: VDMACEN Mask */
+
+#define VDMA_CSR_SW_RST_Pos (1) /*!< VDMA_T::CSR: SW_RST Position */
+#define VDMA_CSR_SW_RST_Msk (0x1ul << VDMA_CSR_SW_RST_Pos) /*!< VDMA_T::CSR: SW_RST Mask */
+
+#define VDMA_CSR_STRIDE_EN_Pos (10) /*!< VDMA_T::CSR: STRIDE_EN Position */
+#define VDMA_CSR_STRIDE_EN_Msk (0x1ul << VDMA_CSR_STRIDE_EN_Pos) /*!< VDMA_T::CSR: STRIDE_EN Mask */
+
+#define VDMA_CSR_DIR_SEL_Pos (11) /*!< VDMA_T::CSR: DIR_SEL Position */
+#define VDMA_CSR_DIR_SEL_Msk (0x1ul << VDMA_CSR_DIR_SEL_Pos) /*!< VDMA_T::CSR: DIR_SEL Mask */
+
+#define VDMA_CSR_TRIG_EN_Pos (23) /*!< VDMA_T::CSR: TRIG_EN Position */
+#define VDMA_CSR_TRIG_EN_Msk (0x1ul << VDMA_CSR_TRIG_EN_Pos) /*!< VDMA_T::CSR: TRIG_EN Mask */
+
+#define VDMA_SAR_VDMA_SAR_Pos (0) /*!< VDMA_T::SAR: VDMA_SAR Position */
+#define VDMA_SAR_VDMA_SAR_Msk (0xfffffffful << VDMA_SAR_VDMA_SAR_Pos) /*!< VDMA_T::SAR: VDMA_SAR Mask */
+
+#define VDMA_DAR_VDMA_DAR_Pos (0) /*!< VDMA_T::DAR: VDMA_DAR Position */
+#define VDMA_DAR_VDMA_DAR_Msk (0xfffffffful << VDMA_DAR_VDMA_DAR_Pos) /*!< VDMA_T::DAR: VDMA_DAR Mask */
+
+#define VDMA_BCR_VDMA_BCR_Pos (0) /*!< VDMA_T::BCR: VDMA_BCR Position */
+#define VDMA_BCR_VDMA_BCR_Msk (0xfffful << VDMA_BCR_VDMA_BCR_Pos) /*!< VDMA_T::BCR: VDMA_BCR Mask */
+
+#define VDMA_CSAR_VDMA_CSAR_Pos (0) /*!< VDMA_T::CSAR: VDMA_CSAR Position */
+#define VDMA_CSAR_VDMA_CSAR_Msk (0xfffffffful << VDMA_CSAR_VDMA_CSAR_Pos) /*!< VDMA_T::CSAR: VDMA_CSAR Mask */
+
+#define VDMA_CDAR_VDMA_CDAR_Pos (0) /*!< VDMA_T::CDAR: VDMA_CDAR Position */
+#define VDMA_CDAR_VDMA_CDAR_Msk (0xfffffffful << VDMA_CDAR_VDMA_CDAR_Pos) /*!< VDMA_T::CDAR: VDMA_CDAR Mask */
+
+#define VDMA_CBCR_VDMA_CBCR_Pos (0) /*!< VDMA_T::CBCR: VDMA_CBCR Position */
+#define VDMA_CBCR_VDMA_CBCR_Msk (0xfffful << VDMA_CBCR_VDMA_CBCR_Pos) /*!< VDMA_T::CBCR: VDMA_CBCR Mask */
+
+#define VDMA_IER_TABORT_IE_Pos (0) /*!< VDMA_T::IER: TABORT_IE Position */
+#define VDMA_IER_TABORT_IE_Msk (0x1ul << VDMA_IER_TABORT_IE_Pos) /*!< VDMA_T::IER: TABORT_IE Mask */
+
+#define VDMA_IER_TD_IE_Pos (1) /*!< VDMA_T::IER: TD_IE Position */
+#define VDMA_IER_TD_IE_Msk (0x1ul << VDMA_IER_TD_IE_Pos) /*!< VDMA_T::IER: TD_IE Mask */
+
+#define VDMA_ISR_TABORT_IS_Pos (0) /*!< VDMA_T::ISR: TABORT_IS Position */
+#define VDMA_ISR_TABORT_IS_Msk (0x1ul << VDMA_ISR_TABORT_IS_Pos) /*!< VDMA_T::ISR: TABORT_IS Mask */
+
+#define VDMA_ISR_TD_IS_Pos (1) /*!< VDMA_T::ISR: TD_IS Position */
+#define VDMA_ISR_TD_IS_Msk (0x1ul << VDMA_ISR_TD_IS_Pos) /*!< VDMA_T::ISR: TD_IS Mask */
+
+#define VDMA_SASOCR_SASTOBL_Pos (0) /*!< VDMA_T::SASOCR: SASTOBL Position */
+#define VDMA_SASOCR_SASTOBL_Msk (0xfffful << VDMA_SASOCR_SASTOBL_Pos) /*!< VDMA_T::SASOCR: SASTOBL Mask */
+
+#define VDMA_SASOCR_STBC_Pos (16) /*!< VDMA_T::SASOCR: STBC Position */
+#define VDMA_SASOCR_STBC_Msk (0xfffful << VDMA_SASOCR_STBC_Pos) /*!< VDMA_T::SASOCR: STBC Mask */
+
+#define VDMA_DASOCR_DASTOBL_Pos (0) /*!< VDMA_T::DASOCR: DASTOBL Position */
+#define VDMA_DASOCR_DASTOBL_Msk (0xfffful << VDMA_DASOCR_DASTOBL_Pos) /*!< VDMA_T::DASOCR: DASTOBL Mask */
+
+/**@}*/ /* VDMA_CONST */
+
+/**@}*/ /* end of DMA register group */
+
+
+/*---------------------- Pulse Width Modulation Controller -------------------------*/
+/**
+ @addtogroup PWM Pulse Width Modulation Controller(PWM)
+ Memory Mapped Structure for PWM Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * PRES
+ * ===================================================================================================
+ * Offset: 0x00 PWM Prescaler Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CP01 |Clock Prescaler 0 For PWM Timer 0 & 1
+ * | | |Clock input is divided by (CP01 + 1) before it is fed to the counter 0 & 1
+ * | | |If CP01 =0, the prescaler 0 output clock will be stopped. So PWM counter 0 and 1 will be stopped also.
+ * |[15:8] |CP23 |Clock Prescaler 2 For PWM Timer 2 & 3
+ * | | |Clock input is divided by (CP23 + 1) before it is fed to the counter 2 & 3
+ * | | |If CP23=0, the prescaler 2 output clock will be stopped. So PWM counter2 and 3 will be stopped also.
+ * |[23:16] |DZ01 |Dead Zone Interval Register For CH0 And CH1 Pair
+ * | | |These 8 bits determine dead zone length.
+ * | | |The unit time of dead zone length is received from clock selector 0.
+ * |[31:24] |DZ23 |Dead Zone Interval Register For CH2 And CH3 Pair
+ * | | |These 8 bits determine dead zone length.
+ * | | |The unit time of dead zone length is received from clock selector 2.
+ */
+ __IO uint32_t PRES;
+
+ /**
+ * CLKSEL
+ * ===================================================================================================
+ * Offset: 0x04 PWM Clock Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |CLKSEL0 |Timer 0 Clock Source Selection
+ * | | |Select clock input for timer 0.
+ * | | |(Table is the same as CLKSEL3)
+ * |[6:4] |CLKSEL1 |Timer 1 Clock Source Selection
+ * | | |Select clock input for timer 1.
+ * | | |(Table is the same as CLKSEL3)
+ * |[10:8] |CLKSEL2 |Timer 2Clock Source Selection
+ * | | |Select clock input for timer 2.
+ * | | |(Table is the same as CLKSEL3)
+ * |[14:12] |CLKSEL3 |Timer 3 Clock Source Selection
+ * | | |Select clock input for timer 3.
+ * | | |000 = Input Clock Divided by 2.
+ * | | |001 = Input Clock Divided by 4.
+ * | | |010 = Input Clock Divided by 8.
+ * | | |011 = Input Clock Divided by 16.
+ * | | |100 = Input Clock Divided by 1.
+ */
+ __IO uint32_t CLKSEL;
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x08 PWM Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CH0EN |PWM-Timer 0 Enable/Disable Start Run
+ * | | |0 = PWM-Timer 0 Running Stopped.
+ * | | |1 = PWM-Timer 0 Start Run Enabled.
+ * |[2] |CH0INV |PWM-Timer 0 Output Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON.
+ * |[3] |CH0MOD |PWM-Timer 0 Continuous/One-Shot Mode
+ * | | |0 = One-Shot Mode.
+ * | | |1 = Continuous Mode.
+ * | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY0 to be cleared.
+ * |[4] |DZEN01 |Dead-Zone 0 Generator Enable/Disable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
+ * |[5] |DZEN23 |Dead-Zone 2 Generator Enable/Disable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair.
+ * |[8] |CH1EN |PWM-Timer 1 Enable/Disable Start Run
+ * | | |0 = PWM-Timer 1 Running Stopped.
+ * | | |1 = PWM-Timer 1 Start Run Enabled.
+ * |[10] |CH1INV |PWM-Timer 1 Output Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON.
+ * |[11] |CH1MOD |PWM-Timer 1 Continuous/One-Shot Mode
+ * | | |0 = One-Shot Mode.
+ * | | |1 = Continuous Mode.
+ * | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY1 to be cleared.
+ * |[16] |CH2EN |PWM-Timer 2 Enable/Disable Start Run
+ * | | |0 = PWM-Timer 2 Running Stopped.
+ * | | |1 = PWM-Timer 2 Start Run Enabled.
+ * |[18] |CH2INV |PWM-Timer 2 Output Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON.
+ * |[19] |CH2MOD |PWM-Timer 2 Continuous/One-Shot Mode
+ * | | |0 = One-Shot Mode.
+ * | | |1 = Continuous Mode.
+ * | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY2 be cleared.
+ * |[24] |CH3EN |PWM-Timer 3 Enable/Disable Start Run
+ * | | |0 = PWM-Timer 3 Running Stopped.
+ * | | |1 = PWM-Timer 3 Start Run Enabled.
+ * |[26] |CH3INV |PWM-Timer 3 Output Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON.
+ * |[27] |CH3MOD |PWM-Timer 3 Continuous/One-Shot Mode
+ * | | |0 = One-Shot Mode.
+ * | | |1 = Continuous Mode.
+ * | | |Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY3 to be cleared.
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * INTEN
+ * ===================================================================================================
+ * Offset: 0x0C PWM Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TMIE0 |PWM Timer 0 Interrupt Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[1] |TMIE1 |PWM Timer 1 Interrupt Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2] |TMIE2 |PWM Timer 2 Interrupt Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[3] |TMIE3 |PWM Timer 3 Interrupt Enable
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ */
+ __IO uint32_t INTEN;
+
+ /**
+ * INTSTS
+ * ===================================================================================================
+ * Offset: 0x10 PWM Interrupt Indication Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TMINT0 |PWM Timer 0 Interrupt Flag
+ * | | |Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it.
+ * |[1] |TMINT1 |PWM Timer 1 Interrupt Flag
+ * | | |Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it.
+ * |[2] |TMINT2 |PWM Timer 2 Interrupt Flag
+ * | | |Flag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it.
+ * |[3] |TMINT3 |PWM Timer 3 Interrupt Flag
+ * | | |Flag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it.
+ * |[4] |Duty0Syncflag|Duty0 Synchronize Flag
+ * | | |0 = Duty0 has been synchronized to ECLK domain.
+ * | | |1 = Duty0 is synchronizing to ECLK domain.
+ * | | |Note: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle
+ * |[5] |Duty1Syncflag|Duty1 Synchronize Flag
+ * | | |0 = Duty1 has been synchronized to ECLK domain.
+ * | | |1 = Duty1 is synchronizing to ECLK domain.
+ * | | |Note: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle
+ * |[6] |Duty2Syncflag|Duty2 Synchronize Flag
+ * | | |0 = Duty2 has been synchronized to ECLK domain.
+ * | | |1 = Duty2 is synchronizing to ECLK domain.
+ * | | |Note: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle
+ * |[7] |Duty3Syncflag|Duty3 Synchronize Flag
+ * | | |0 = Duty3 has been synchronized to ECLK domain.
+ * | | |1 = Duty3 is synchronizing to ECLK domain.
+ * | | |Note: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle
+ * |[8] |PresSyncFlag|Prescale Synchronize Flag
+ * | | |0 = Prescale has been synchronized to ECLK domain.
+ * | | |1 = Prescale is synchronizing to ECLK domain.
+ * | | |Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle
+ */
+ __IO uint32_t INTSTS;
+
+ /**
+ * OE
+ * ===================================================================================================
+ * Offset: 0x14 PWM Output Enable for PWM0~PWM3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CH0_OE |PWM CH0 Output Enable Register
+ * | | |0 = PWM CH0 output to pin Disabled.
+ * | | |1 = PWM CH0 output to pin Enabled.
+ * | | |Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
+ * |[1] |CH1_OE |PWM CH1 Output Enable Register
+ * | | |0 = PWM CH1 output to pin Disabled.
+ * | | |1 = PWM CH1 output to pin Enabled.
+ * | | |Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
+ * |[2] |CH2_OE |PWM CH2 Output Enable Register
+ * | | |0 = PWM CH2 output to pin Disabled.
+ * | | |1 = PWM CH2 output to pin Enabled.
+ * | | |Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
+ * |[3] |CH3_OE |PWM CH3 Output Enable Register
+ * | | |0 = PWM CH3 output to pin Disabled.
+ * | | |1 = PWM CH3 output to pin Enabled.
+ * | | |Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP)
+ */
+ __IO uint32_t OE;
+ uint32_t RESERVE0[1];
+
+
+ /**
+ * DUTY0
+ * ===================================================================================================
+ * Offset: 0x1C PWM Counter/Comparator Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CN |PWM Counter/Timer Loaded Value
+ * | | |CN determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note:
+ * | | |Any write to CN will take effect in next PWM cycle.
+ * |[31:16] |CM |PWM Comparator Register
+ * | | |CM determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note:
+ * | | |Any write to CM will take effect in next PWM cycle.
+ */
+ __IO uint32_t DUTY0;
+
+ /**
+ * DATA0
+ * ===================================================================================================
+ * Offset: 0x20 PWM Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PWMx_DATAy15_0|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 16-bit down count counter.
+ * |[30:16] |PWMx_DATAy30_16|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 32-bit down count counter
+ * | | |Notes:This will be valid only for the corresponding cascade enable .bit is set
+ * |[31] |sync |Indicate That CNR Value Is Sync To PWM Counter
+ * | | |0 = CNR value is sync to PWM counter.
+ * | | |1 = CNR value is not sync to PWM counter.
+ * | | |Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel
+ */
+ __I uint32_t DATA0;
+ uint32_t RESERVE1[1];
+
+
+ /**
+ * DUTY1
+ * ===================================================================================================
+ * Offset: 0x28 PWM Counter/Comparator Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CN |PWM Counter/Timer Loaded Value
+ * | | |CN determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note:
+ * | | |Any write to CN will take effect in next PWM cycle.
+ * |[31:16] |CM |PWM Comparator Register
+ * | | |CM determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note:
+ * | | |Any write to CM will take effect in next PWM cycle.
+ */
+ __IO uint32_t DUTY1;
+
+ /**
+ * DATA1
+ * ===================================================================================================
+ * Offset: 0x2C PWM Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PWMx_DATAy15_0|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 16-bit down count counter.
+ * |[30:16] |PWMx_DATAy30_16|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 32-bit down count counter
+ * | | |Notes:This will be valid only for the corresponding cascade enable .bit is set
+ * |[31] |sync |Indicate That CNR Value Is Sync To PWM Counter
+ * | | |0 = CNR value is sync to PWM counter.
+ * | | |1 = CNR value is not sync to PWM counter.
+ * | | |Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel
+ */
+ __I uint32_t DATA1;
+ uint32_t RESERVE2[1];
+
+
+ /**
+ * DUTY2
+ * ===================================================================================================
+ * Offset: 0x34 PWM Counter/Comparator Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CN |PWM Counter/Timer Loaded Value
+ * | | |CN determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note:
+ * | | |Any write to CN will take effect in next PWM cycle.
+ * |[31:16] |CM |PWM Comparator Register
+ * | | |CM determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note:
+ * | | |Any write to CM will take effect in next PWM cycle.
+ */
+ __IO uint32_t DUTY2;
+
+ /**
+ * DATA2
+ * ===================================================================================================
+ * Offset: 0x38 PWM Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PWMx_DATAy15_0|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 16-bit down count counter.
+ * |[30:16] |PWMx_DATAy30_16|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 32-bit down count counter
+ * | | |Notes:This will be valid only for the corresponding cascade enable .bit is set
+ * |[31] |sync |Indicate That CNR Value Is Sync To PWM Counter
+ * | | |0 = CNR value is sync to PWM counter.
+ * | | |1 = CNR value is not sync to PWM counter.
+ * | | |Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel
+ */
+ __I uint32_t DATA2;
+ uint32_t RESERVE3[1];
+
+
+ /**
+ * DUTY3
+ * ===================================================================================================
+ * Offset: 0x40 PWM Counter/Comparator Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CN |PWM Counter/Timer Loaded Value
+ * | | |CN determines the PWM period.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note: Any write to CN will take effect in next PWM cycle.
+ * |[31:16] |CM |PWM Comparator Register
+ * | | |CM determines the PWM duty.
+ * | | |PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel.
+ * | | |Duty ratio = (CM+1)/(CN+1).
+ * | | |CM >= CN: PWM output is always high.
+ * | | |CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit.
+ * | | |CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit.
+ * | | |(Unit = one PWM clock cycle).
+ * | | |Note: Any write to CM will take effect in next PWM cycle.
+ */
+ __IO uint32_t DUTY3;
+
+ /**
+ * DATA3
+ * ===================================================================================================
+ * Offset: 0x44 PWM Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PWMx_DATAy15_0|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 16-bit down count counter.
+ * |[30:16] |PWMx_DATAy30_16|PWM Data Register
+ * | | |User can monitor PWMx_DATAy to know the current value in 32-bit down count counter
+ * | | |Notes:This will be valid only for the corresponding cascade enable .bit is set
+ * |[31] |sync |Indicate That CNR Value Is Sync To PWM Counter
+ * | | |0 = CNR value is sync to PWM counter.
+ * | | |1 = CNR value is not sync to PWM counter.
+ * | | |Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel
+ */
+ __I uint32_t DATA3;
+ uint32_t RESERVE4[3];
+
+
+ /**
+ * CAPCTL
+ * ===================================================================================================
+ * Offset: 0x54 Capture Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INV0 |Channel 0 Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * |[1] |CAPCH0EN |Capture Channel 0 Transition Enable/Disable
+ * | | |0 = Capture function on channel 0 Disabled.
+ * | | |1 = Capture function on channel 0 Enabled.
+ * | | |When Enabled, Capture latched the PWM-timer value and saved to PWM_CRL0 (Rising latch) and PWM_CFL0 (Falling latch).
+ * | | |When Disabled, Capture does not update PWM_CRL0 and PWM_CFL0, and disable Channel 0 Interrupt.
+ * |[2] |CAPCH0PADEN|Capture Input Enable
+ * | | |0 = OFF.
+ * | | |1 = ON.
+ * |[3] |CH0PDMAEN |Channel 0 PDMA Enable
+ * | | |0 = Channel 0 PDMA function Disabled.
+ * | | |1 = Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory.
+ * |[5:4] |PDMACAPMOD0|Select CRL0 Or CFL0 For PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = CRL0.
+ * | | |10 = CFL0.
+ * | | |11 = Both CRL0 and CFL0.
+ * |[6] |CAPRELOADREN0|Reload CNR0 When CH0 Capture Rising Event Comes
+ * | | |0 = Rising capture reload for CH0 Disabled.
+ * | | |1 = Rising capture reload for CH0 Enabled.
+ * |[7] |CAPRELOADFEN0|Reload CNR0 When CH0 Capture Falling Event Comes
+ * | | |0 = Falling capture reload for CH0 Disabled.
+ * | | |1 = Falling capture reload for CH0 Enabled.
+ * |[8] |INV1 |Channel 1 Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * |[9] |CAPCH1EN |Capture Channel 1 Transition Enable/Disable
+ * | | |0 = Capture function on channel 1 Disabled.
+ * | | |1 = Capture function on channel 1 Enabled.
+ * | | |When Enabled, Capture latched the PMW-counter and saved to PWM_CRL1 (Rising latch) and PWM_CFL1 (Falling latch).
+ * | | |When Disabled, Capture does not update PWM_CRL1 and PWM_CFL1, and disable Channel 1 Interrupt.
+ * |[10] |CAPCH1PADEN|Capture Input Enable
+ * | | |0 = OFF.
+ * | | |1 = ON.
+ * |[12] |CH0RFORDER|Channel 0 capture order control
+ * | | |Set this bit to determine whether the PWM_CRL0 or PWM_CFL0 is the first captured data transferred to memory through PDMA when PDMACAPMOD0 =2'b11.
+ * | | |0 = PWM_CFL0 is the first captured data to memory.
+ * | | |1 = PWM_CRL0 is the first captured data to memory.
+ * |[13] |CH01CASK |Cascade channel 0 and channel 1 PWM timer for capturing usage
+ * |[14] |CAPRELOADREN1|Reload CNR1 When CH1 Capture Rising Event Comes
+ * | | |0 = Rising capture reload for CH1 Disabled.
+ * | | |1 = Rising capture reload for CH1 Enabled.
+ * |[15] |CAPRELOADFEN1|Reload CNR1 When CH1 Capture Falling Event Coming
+ * | | |0 = Capture falling reload for CH1 Disabled.
+ * | | |1 = Capture falling reload for CH1 Enabled.
+ * |[16] |INV2 |Channel 2 Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * |[17] |CAPCH2EN |Capture Channel 2 Transition Enable/Disable
+ * | | |0 = Capture function on channel 2 Disabled.
+ * | | |1 = Capture function on channel 2 Enabled.
+ * | | |When Enabled, Capture latched the PWM-timer value and saved to PWM_CRL2 (Rising latch) and PWM_CFL2 (Falling latch).
+ * | | |When Disabled, Capture does not update PWM_CRL2 and PWM_CFL2, and disable Channel 2 Interrupt.
+ * |[18] |CAPCH2PADEN|Capture Input Enable
+ * | | |0 = OFF.
+ * | | |1 = ON.
+ * |[19] |CH2PDMAEN |Channel 2 PDMA Enable
+ * | | |0 = Channel 2 PDMA function Disabled.
+ * | | |1 = Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory.
+ * |[21:20] |PDMACAPMOD2|Select CRL2 Or CFL2 For PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = CRL2.
+ * | | |10 = CFL2.
+ * | | |11 = Both CRL2 and CFL2.
+ * |[22] |CAPRELOADREN2|Reload CNR2 When CH2 Capture Rising Event Coming
+ * | | |0 = Rising capture reload for CH2 Disabled.
+ * | | |1 = Rising capture reload for CH2 Enabled.
+ * |[23] |CAPRELOADFEN2|Reload CNR2 When CH2 Capture Failing Event Coming
+ * | | |0 = Failing capture reload for CH2 Disabled.
+ * | | |1 = Failing capture reload for CH2 Enabled.
+ * |[24] |INV3 |Channel 3 Inverter ON/OFF
+ * | | |0 = Inverter OFF.
+ * | | |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
+ * |[25] |CAPCH3EN |Capture Channel 3 Transition Enable/Disable
+ * | | |0 = Capture function on channel 3 Disabled.
+ * | | |1 = Capture function on channel 3 Enabled.
+ * | | |When Enabled, Capture latched the PMW-timer and saved to PWM_CRL3 (Rising latch) and PWM_CFL3 (Falling latch).
+ * | | |When Disabled, Capture does not update PWM_CRL3 and PWM_CFL3, and disable Channel 3 Interrupt.
+ * |[26] |CAPCH3PADEN|Capture Input Enable
+ * | | |0 = OFF.
+ * | | |1 = ON.
+ * |[28] |CH2RFORDER|Channel 0 capture order control
+ * | | |Set this bit to determine whether the PWM_CRL2 or PWM_CFL2 is the first captured data transferred to memory through PDMA when PDMACAPMOD2 = 2'b11.
+ * | | |0 = PWM_CFL2 is the first captured data to memory.
+ * | | |1 = PWM_CRL2 is the first captured data to memory.
+ * |[29] |CH23CASK |Cascade channel 2 and channel 3 PWM counter for capturing usage
+ * |[30] |CAPRELOADREN3|Reload CNR3 When CH3 Rising Capture Event Comes
+ * | | |0 = Rising capture reload for CH3 Disabled.
+ * | | |1 = Rising capture reload for CH3 Enabled.
+ * |[31] |CAPRELOADFEN3|Reload CNR3 When CH3 Falling Capture Event Comes
+ * | | |0 = Falling capture reload for CH3 Disabled.
+ * | | |1 = Falling capture reload for CH3 Enabled.
+ */
+ __IO uint32_t CAPCTL;
+
+ /**
+ * CAPINTEN
+ * ===================================================================================================
+ * Offset: 0x58 Capture interrupt enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CRL_IE0 |Channel 0 Rising Latch Interrupt Enable ON/OFF
+ * | | |0 = Rising latch interrupt Disabled.
+ * | | |1 = Rising latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
+ * |[1] |CFL_IE0 |Channel 0 Falling Latch Interrupt Enable ON/OFF
+ * | | |0 = Falling latch interrupt Disabled.
+ * | | |1 = Falling latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
+ * |[8] |CRL_IE1 |Channel 1 Rising Latch Interrupt Enable
+ * | | |0 = Rising latch interrupt Disabled.
+ * | | |1 = Rising latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
+ * |[9] |CFL_IE1 |Channel 1 Falling Latch Interrupt Enable
+ * | | |0 = Falling latch interrupt Disabled.
+ * | | |1 = Falling latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
+ * |[16] |CRL_IE2 |Channel 2 Rising Latch Interrupt Enable ON/OFF
+ * | | |0 = Rising latch interrupt Disabled.
+ * | | |1 = Rising latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
+ * |[17] |CFL_IE2 |Channel 2 Falling Latch Interrupt Enable ON/OFF
+ * | | |0 = Falling latch interrupt Disabled.
+ * | | |1 = Falling latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
+ * |[24] |CRL_IE3 |Channel 3 Rising Latch Interrupt Enable ON/OFF
+ * | | |0 = Rising latch interrupt Disabled.
+ * | | |1 = Rising latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
+ * |[25] |CFL_IE3 |Channel 3 Falling Latch Interrupt Enable ON/OFF
+ * | | |0 = Falling latch interrupt Disabled.
+ * | | |1 = Falling latch interrupt Enabled.
+ * | | |When Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.
+ */
+ __IO uint32_t CAPINTEN;
+
+ /**
+ * CAPINTSTS
+ * ===================================================================================================
+ * Offset: 0x5C Capture Interrupt Indication Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPIF0 |Capture0 Interrupt Indication Flag
+ * | | |If channel 0 rising latch interrupt is enabled (CRL_IE0 =1), a rising transition occurs at input channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFL_IE0 =1).
+ * | | |This flag is cleared by software with a write 1 on it.
+ * |[1] |CRLI0 |PWM_CRL0 Latched Indicator Bit
+ * | | |When input channel 0 has a rising transition, PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[2] |CFLRI0 |PWM_CFL0 Latched Indicator Bit
+ * | | |When input channel 0 has a falling transition, PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[3] |CAPOVR0 |Capture Rising Flag Over Run For Channel 0
+ * | | |This flag indicate CRL0 update faster than software reading it when it is set
+ * | | |This bit will be cleared automatically when user clears CRLI0 bit 1 of PWM_CAPINTSTS.
+ * |[4] |CAPOVF0 |Capture Falling Flag Over Run For Channel 0
+ * | | |This flag indicate CFL0 update faster than software read it when it is set
+ * | | |This bit will be cleared automatically when user clear CFLI0 bit 2 of PWM_CAPINTSTS
+ * |[8] |CAPIF1 |Capture1 Interrupt Indication Flag
+ * | | |If channel 1 rising latch interrupt is enabled (CRL_IE1 =1), a rising transition occurs at input channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFL_IE1 =1).
+ * | | |This flag is cleared by software with a write 1 on it.
+ * |[9] |CRLI1 |PWM_CRL1 Latched Indicator Bit
+ * | | |When input channel 1 has a rising transition, PWM_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[10] |CFLI1 |PWM_CFL1 Latched Indicator Bit
+ * | | |When input channel 1 has a falling transition, PWM_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[11] |CAPOVR1 |Capture Rising Flag Over Run For Channel 1
+ * | | |This flag indicate CRL1 update faster than software reading it when it is set
+ * | | |This bit will be cleared automatically when user clear CRLI1 bit 9 of PWM_CAPINTSTS
+ * |[12] |CAPOVF1 |Capture Falling Flag Over Run For Channel 1
+ * | | |This flag indicate CFL1 update faster than software reading it when it is set
+ * | | |This bit will be cleared automatically when user clear CFLI1 bit 10 of PWM_CAPINTSTS
+ * |[16] |CAPIF2 |Capture2 Interrupt Indication Flag
+ * | | |If channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs at input channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt is enabled (CFL_IE2=1).
+ * | | |This flag is cleared by software with a write 1 on it.
+ * |[17] |CRLI2 |PWM_CRL2 Latched Indicator Bit
+ * | | |When input channel 2 has a rising transition, PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[18] |CFLI2 |PWM_CFL2 Latched Indicator Bit
+ * | | |When input channel 2 has a falling transition, PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[19] |CAPOVR2 |Capture Rising Flag Over Run For Channel 2
+ * | | |This flag indicate CRL2 update faster than software reading it when it is set
+ * | | |This bit will be cleared automatically when user clear CRLI2 bit 17 of PWM_CAPINTSTS
+ * |[20] |CAPOVF2 |Capture Falling Flag Over Run For Channel 2
+ * | | |This flag indicate CFL2 update faster than software reading it when it is set
+ * | | |This bit will be cleared automatically when user clear CFLI2 bit 18 of PWM_CAPINTSTS
+ * |[24] |CAPIF3 |Capture3 Interrupt Indication Flag
+ * | | |If channel 3 rising latch interrupt is enabled (CRL_IE3 =1), a rising transition occurs at input channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt is enabled (CFL_IE3=1).
+ * | | |This flag is cleared by software with a write 1 on it.
+ * |[25] |CRLI3 |PWM_CRL3 Latched Indicator Bit
+ * | | |When input channel 3 has a rising transition, PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[26] |CFLI3 |PWM_CFL3 Latched Indicator Bit
+ * | | |When input channel 3 has a falling transition, PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
+ * |[27] |CAPOVR3 |Capture Rising Flag Over Run For Channel 3
+ * | | |This flag indicate CRL3update faster than software reading it when it is set
+ * | | |This bit will be cleared automatically when user clear CRLI3 bit 25 of PWM_CAPINTSTS
+ * |[28] |CAPOVF3 |Capture Falling Flag Over Run For Channel 3
+ * | | |This flag indicate CFL3 update faster than software reading it when it is set
+ * | | |This bit will be cleared automatically when user clear CFLI3 bit 26 of PWM_CAPINTSTS
+ */
+ __IO uint32_t CAPINTSTS;
+
+ /**
+ * CRL0
+ * ===================================================================================================
+ * Offset: 0x60 Capture Rising Latch Register (Channel 0)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRL15_0 |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ * |[31:16] |CRL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit.
+ */
+ __I uint32_t CRL0;
+
+ /**
+ * CFL0
+ * ===================================================================================================
+ * Offset: 0x64 Capture Falling Latch Register (Channel 0)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFL15_0 |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 01/2/3 has Falling transition.
+ * |[31:16] |CFL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit.
+ */
+ __I uint32_t CFL0;
+
+ /**
+ * CRL1
+ * ===================================================================================================
+ * Offset: 0x68 Capture Rising Latch Register (Channel 1)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRL15_0 |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ * |[31:16] |CRL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit.
+ */
+ __I uint32_t CRL1;
+
+ /**
+ * CFL1
+ * ===================================================================================================
+ * Offset: 0x6C Capture Falling Latch Register (Channel 1)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFL15_0 |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 01/2/3 has Falling transition.
+ * |[31:16] |CFL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit.
+ */
+ __I uint32_t CFL1;
+
+ /**
+ * CRL2
+ * ===================================================================================================
+ * Offset: 0x70 Capture Rising Latch Register (Channel 2)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRL15_0 |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ * |[31:16] |CRL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit.
+ */
+ __I uint32_t CRL2;
+
+ /**
+ * CFL2
+ * ===================================================================================================
+ * Offset: 0x74 Capture Falling Latch Register (Channel 2)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFL15_0 |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 01/2/3 has Falling transition.
+ * |[31:16] |CFL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit.
+ */
+ __I uint32_t CFL2;
+
+ /**
+ * CRL3
+ * ===================================================================================================
+ * Offset: 0x78 Capture Rising Latch Register (Channel 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CRL15_0 |Capture Rising Latch Register
+ * | | |Latch the PWM counter when Channel 0/1/2/3 has rising transition.
+ * |[31:16] |CRL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit.
+ */
+ __I uint32_t CRL3;
+
+ /**
+ * CFL3
+ * ===================================================================================================
+ * Offset: 0x7C Capture Falling Latch Register (Channel 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CFL15_0 |Capture Falling Latch Register
+ * | | |Latch the PWM counter when Channel 01/2/3 has Falling transition.
+ * |[31:16] |CFL31_16 |Upper Half Word Of 32-Bit Capture Data When Cascade Enabled
+ * | | |When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit.
+ */
+ __I uint32_t CFL3;
+
+ /**
+ * PDMACH0
+ * ===================================================================================================
+ * Offset: 0x80 PDMA channel 0 captured data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Captureddata7_0|PDMACH0
+ * | | |When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0
+ * | | |When CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0
+ * |[15:8] |Captureddata15_8|PDMACH0
+ * | | |When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0
+ * | | |When CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0
+ * |[23:16] |Captureddata23_16|PDMACH0
+ * | | |When CH01CASK is disabled, this byte is 0
+ * | | |When CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0
+ * |[31:24] |Captureddata31_24|PDMACH0
+ * | | |When CH01CASK is disabled, this byte is 0
+ * | | |When CH01CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0
+ */
+ __I uint32_t PDMACH0;
+
+ /**
+ * PDMACH2
+ * ===================================================================================================
+ * Offset: 0x84 PDMA channel 2 captured data
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Captureddata7_0|PDMACH0
+ * | | |When CH23CASK is disabled, it is the capturing value(CFL2/CRL2) for channel 2
+ * | | |When CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2
+ * |[15:8] |Captureddata15_8|PDMACH0
+ * | | |When CH23CASK is disabled, it is the capturing value(CFL2/CRL2) for channel 2
+ * | | |When CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2
+ * |[23:16] |Captureddata23_16|PDMACH0
+ * | | |When CH23CASK is disabled, this byte is 0
+ * | | |When CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2
+ * |[31:24] |Captureddata31_24|PDMACH0
+ * | | |When CH23CASK is disabled, this byte is 0
+ * | | |When CH23CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 2
+ */
+ __I uint32_t PDMACH2;
+
+} PWM_T;
+
+/**
+ @addtogroup PWM_CONST PWM Bit Field Definition
+ Constant Definitions for PWM Controller
+@{ */
+
+#define PWM_PRES_CP01_Pos (0) /*!< PWM_T::PRES: CP01 Position */
+#define PWM_PRES_CP01_Msk (0xfful << PWM_PRES_CP01_Pos) /*!< PWM_T::PRES: CP01 Mask */
+
+#define PWM_PRES_CP23_Pos (8) /*!< PWM_T::PRES: CP23 Position */
+#define PWM_PRES_CP23_Msk (0xfful << PWM_PRES_CP23_Pos) /*!< PWM_T::PRES: CP23 Mask */
+
+#define PWM_PRES_DZ01_Pos (16) /*!< PWM_T::PRES: DZ01 Position */
+#define PWM_PRES_DZ01_Msk (0xfful << PWM_PRES_DZ01_Pos) /*!< PWM_T::PRES: DZ01 Mask */
+
+#define PWM_PRES_DZ23_Pos (24) /*!< PWM_T::PRES: DZ23 Position */
+#define PWM_PRES_DZ23_Msk (0xfful << PWM_PRES_DZ23_Pos) /*!< PWM_T::PRES: DZ23 Mask */
+
+#define PWM_CLKSEL_CLKSEL0_Pos (0) /*!< PWM_T::CLKSEL: CLKSEL0 Position */
+#define PWM_CLKSEL_CLKSEL0_Msk (0x7ul << PWM_CLKSEL_CLKSEL0_Pos) /*!< PWM_T::CLKSEL: CLKSEL0 Mask */
+
+#define PWM_CLKSEL_CLKSEL1_Pos (4) /*!< PWM_T::CLKSEL: CLKSEL1 Position */
+#define PWM_CLKSEL_CLKSEL1_Msk (0x7ul << PWM_CLKSEL_CLKSEL1_Pos) /*!< PWM_T::CLKSEL: CLKSEL1 Mask */
+
+#define PWM_CLKSEL_CLKSEL2_Pos (8) /*!< PWM_T::CLKSEL: CLKSEL2 Position */
+#define PWM_CLKSEL_CLKSEL2_Msk (0x7ul << PWM_CLKSEL_CLKSEL2_Pos) /*!< PWM_T::CLKSEL: CLKSEL2 Mask */
+
+#define PWM_CLKSEL_CLKSEL3_Pos (12) /*!< PWM_T::CLKSEL: CLKSEL3 Position */
+#define PWM_CLKSEL_CLKSEL3_Msk (0x7ul << PWM_CLKSEL_CLKSEL3_Pos) /*!< PWM_T::CLKSEL: CLKSEL3 Mask */
+
+#define PWM_CTL_CH0EN_Pos (0) /*!< PWM_T::CTL: CH0EN Position */
+#define PWM_CTL_CH0EN_Msk (0x1ul << PWM_CTL_CH0EN_Pos) /*!< PWM_T::CTL: CH0EN Mask */
+
+#define PWM_CTL_CH0INV_Pos (2) /*!< PWM_T::CTL: CH0INV Position */
+#define PWM_CTL_CH0INV_Msk (0x1ul << PWM_CTL_CH0INV_Pos) /*!< PWM_T::CTL: CH0INV Mask */
+
+#define PWM_CTL_CH0MOD_Pos (3) /*!< PWM_T::CTL: CH0MOD Position */
+#define PWM_CTL_CH0MOD_Msk (0x1ul << PWM_CTL_CH0MOD_Pos) /*!< PWM_T::CTL: CH0MOD Mask */
+
+#define PWM_CTL_DZEN01_Pos (4) /*!< PWM_T::CTL: DZEN01 Position */
+#define PWM_CTL_DZEN01_Msk (0x1ul << PWM_CTL_DZEN01_Pos) /*!< PWM_T::CTL: DZEN01 Mask */
+
+#define PWM_CTL_DZEN23_Pos (5) /*!< PWM_T::CTL: DZEN23 Position */
+#define PWM_CTL_DZEN23_Msk (0x1ul << PWM_CTL_DZEN23_Pos) /*!< PWM_T::CTL: DZEN23 Mask */
+
+#define PWM_CTL_CH1EN_Pos (8) /*!< PWM_T::CTL: CH1EN Position */
+#define PWM_CTL_CH1EN_Msk (0x1ul << PWM_CTL_CH1EN_Pos) /*!< PWM_T::CTL: CH1EN Mask */
+
+#define PWM_CTL_CH1INV_Pos (10) /*!< PWM_T::CTL: CH1INV Position */
+#define PWM_CTL_CH1INV_Msk (0x1ul << PWM_CTL_CH1INV_Pos) /*!< PWM_T::CTL: CH1INV Mask */
+
+#define PWM_CTL_CH1MOD_Pos (11) /*!< PWM_T::CTL: CH1MOD Position */
+#define PWM_CTL_CH1MOD_Msk (0x1ul << PWM_CTL_CH1MOD_Pos) /*!< PWM_T::CTL: CH1MOD Mask */
+
+#define PWM_CTL_CH2EN_Pos (16) /*!< PWM_T::CTL: CH2EN Position */
+#define PWM_CTL_CH2EN_Msk (0x1ul << PWM_CTL_CH2EN_Pos) /*!< PWM_T::CTL: CH2EN Mask */
+
+#define PWM_CTL_CH2INV_Pos (18) /*!< PWM_T::CTL: CH2INV Position */
+#define PWM_CTL_CH2INV_Msk (0x1ul << PWM_CTL_CH2INV_Pos) /*!< PWM_T::CTL: CH2INV Mask */
+
+#define PWM_CTL_CH2MOD_Pos (19) /*!< PWM_T::CTL: CH2MOD Position */
+#define PWM_CTL_CH2MOD_Msk (0x1ul << PWM_CTL_CH2MOD_Pos) /*!< PWM_T::CTL: CH2MOD Mask */
+
+#define PWM_CTL_CH3EN_Pos (24) /*!< PWM_T::CTL: CH3EN Position */
+#define PWM_CTL_CH3EN_Msk (0x1ul << PWM_CTL_CH3EN_Pos) /*!< PWM_T::CTL: CH3EN Mask */
+
+#define PWM_CTL_CH3INV_Pos (26) /*!< PWM_T::CTL: CH3INV Position */
+#define PWM_CTL_CH3INV_Msk (0x1ul << PWM_CTL_CH3INV_Pos) /*!< PWM_T::CTL: CH3INV Mask */
+
+#define PWM_CTL_CH3MOD_Pos (27) /*!< PWM_T::CTL: CH3MOD Position */
+#define PWM_CTL_CH3MOD_Msk (0x1ul << PWM_CTL_CH3MOD_Pos) /*!< PWM_T::CTL: CH3MOD Mask */
+
+#define PWM_INTEN_TMIE0_Pos (0) /*!< PWM_T::INTEN: TMIE0 Position */
+#define PWM_INTEN_TMIE0_Msk (0x1ul << PWM_INTEN_TMIE0_Pos) /*!< PWM_T::INTEN: TMIE0 Mask */
+
+#define PWM_INTEN_TMIE1_Pos (1) /*!< PWM_T::INTEN: TMIE1 Position */
+#define PWM_INTEN_TMIE1_Msk (0x1ul << PWM_INTEN_TMIE1_Pos) /*!< PWM_T::INTEN: TMIE1 Mask */
+
+#define PWM_INTEN_TMIE2_Pos (2) /*!< PWM_T::INTEN: TMIE2 Position */
+#define PWM_INTEN_TMIE2_Msk (0x1ul << PWM_INTEN_TMIE2_Pos) /*!< PWM_T::INTEN: TMIE2 Mask */
+
+#define PWM_INTEN_TMIE3_Pos (3) /*!< PWM_T::INTEN: TMIE3 Position */
+#define PWM_INTEN_TMIE3_Msk (0x1ul << PWM_INTEN_TMIE3_Pos) /*!< PWM_T::INTEN: TMIE3 Mask */
+
+#define PWM_INTSTS_TMINT0_Pos (0) /*!< PWM_T::INTSTS: TMINT0 Position */
+#define PWM_INTSTS_TMINT0_Msk (0x1ul << PWM_INTSTS_TMINT0_Pos) /*!< PWM_T::INTSTS: TMINT0 Mask */
+
+#define PWM_INTSTS_TMINT1_Pos (1) /*!< PWM_T::INTSTS: TMINT1 Position */
+#define PWM_INTSTS_TMINT1_Msk (0x1ul << PWM_INTSTS_TMINT1_Pos) /*!< PWM_T::INTSTS: TMINT1 Mask */
+
+#define PWM_INTSTS_TMINT2_Pos (2) /*!< PWM_T::INTSTS: TMINT2 Position */
+#define PWM_INTSTS_TMINT2_Msk (0x1ul << PWM_INTSTS_TMINT2_Pos) /*!< PWM_T::INTSTS: TMINT2 Mask */
+
+#define PWM_INTSTS_TMINT3_Pos (3) /*!< PWM_T::INTSTS: TMINT3 Position */
+#define PWM_INTSTS_TMINT3_Msk (0x1ul << PWM_INTSTS_TMINT3_Pos) /*!< PWM_T::INTSTS: TMINT3 Mask */
+
+#define PWM_INTSTS_DUTY0SYNC_Pos (4) /*!< PWM_T::INTSTS: DUTY0SYNC Position */
+#define PWM_INTSTS_DUTY0SYNC_Msk (0x1ul << PWM_INTSTS_DUTY0SYNC_Pos) /*!< PWM_T::INTSTS: DUTY0SYNC Mask */
+
+#define PWM_INTSTS_PRESSYNC_Pos (8) /*!< PWM_T::INTSTS: PRESSYNC Position */
+#define PWM_INTSTS_PRESSYNC_Msk (0x1ul << PWM_INTSTS_PRESSYNC_Pos) /*!< PWM_T::INTSTS: PRESSYNC Mask */
+
+#define PWM_OE_CH0_OE_Pos (0) /*!< PWM_T::OE: CH0_OE Position */
+#define PWM_OE_CH0_OE_Msk (0x1ul << PWM_OE_CH0_OE_Pos) /*!< PWM_T::OE: CH0_OE Mask */
+
+#define PWM_OE_CH1_OE_Pos (1) /*!< PWM_T::OE: CH1_OE Position */
+#define PWM_OE_CH1_OE_Msk (0x1ul << PWM_OE_CH1_OE_Pos) /*!< PWM_T::OE: CH1_OE Mask */
+
+#define PWM_OE_CH2_OE_Pos (2) /*!< PWM_T::OE: CH2_OE Position */
+#define PWM_OE_CH2_OE_Msk (0x1ul << PWM_OE_CH2_OE_Pos) /*!< PWM_T::OE: CH2_OE Mask */
+
+#define PWM_OE_CH3_OE_Pos (3) /*!< PWM_T::OE: CH3_OE Position */
+#define PWM_OE_CH3_OE_Msk (0x1ul << PWM_OE_CH3_OE_Pos) /*!< PWM_T::OE: CH3_OE Mask */
+
+#define PWM_DUTY_CN_Pos (0) /*!< PWM_T::DUTY0: CN Position */
+#define PWM_DUTY_CN_Msk (0xfffful << PWM_DUTY_CN_Pos) /*!< PWM_T::DUTY0: CN Mask */
+
+#define PWM_DUTY_CM_Pos (16) /*!< PWM_T::DUTY0: CM Position */
+#define PWM_DUTY_CM_Msk (0xfffful << PWM_DUTY_CM_Pos) /*!< PWM_T::DUTY0: CM Mask */
+
+#define PWM_DATA0_PWMx_DATAy15_0_Pos (0) /*!< PWM_T::DATA0: PWMx_DATAy15_0 Position */
+#define PWM_DATA0_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA0_PWMx_DATAy15_0_Pos) /*!< PWM_T::DATA0: PWMx_DATAy15_0 Mask */
+
+#define PWM_DATA0_PWMx_DATAy30_16_Pos (16) /*!< PWM_T::DATA0: PWMx_DATAy30_16 Position */
+#define PWM_DATA0_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA0_PWMx_DATAy30_16_Pos) /*!< PWM_T::DATA0: PWMx_DATAy30_16 Mask */
+
+#define PWM_DATA0_sync_Pos (31) /*!< PWM_T::DATA0: sync Position */
+#define PWM_DATA0_sync_Msk (0x1ul << PWM_DATA0_sync_Pos) /*!< PWM_T::DATA0: sync Mask */
+
+#define PWM_DUTY1_CN_Pos (0) /*!< PWM_T::DUTY1: CN Position */
+#define PWM_DUTY1_CN_Msk (0xfffful << PWM_DUTY1_CN_Pos) /*!< PWM_T::DUTY1: CN Mask */
+
+#define PWM_DUTY1_CM_Pos (16) /*!< PWM_T::DUTY1: CM Position */
+#define PWM_DUTY1_CM_Msk (0xfffful << PWM_DUTY1_CM_Pos) /*!< PWM_T::DUTY1: CM Mask */
+
+#define PWM_DATA1_PWMx_DATAy15_0_Pos (0) /*!< PWM_T::DATA1: PWMx_DATAy15_0 Position */
+#define PWM_DATA1_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA1_PWMx_DATAy15_0_Pos) /*!< PWM_T::DATA1: PWMx_DATAy15_0 Mask */
+
+#define PWM_DATA1_PWMx_DATAy30_16_Pos (16) /*!< PWM_T::DATA1: PWMx_DATAy30_16 Position */
+#define PWM_DATA1_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA1_PWMx_DATAy30_16_Pos) /*!< PWM_T::DATA1: PWMx_DATAy30_16 Mask */
+
+#define PWM_DATA1_sync_Pos (31) /*!< PWM_T::DATA1: sync Position */
+#define PWM_DATA1_sync_Msk (0x1ul << PWM_DATA1_sync_Pos) /*!< PWM_T::DATA1: sync Mask */
+
+#define PWM_DUTY2_CN_Pos (0) /*!< PWM_T::DUTY2: CN Position */
+#define PWM_DUTY2_CN_Msk (0xfffful << PWM_DUTY2_CN_Pos) /*!< PWM_T::DUTY2: CN Mask */
+
+#define PWM_DUTY2_CM_Pos (16) /*!< PWM_T::DUTY2: CM Position */
+#define PWM_DUTY2_CM_Msk (0xfffful << PWM_DUTY2_CM_Pos) /*!< PWM_T::DUTY2: CM Mask */
+
+#define PWM_DATA2_PWMx_DATAy15_0_Pos (0) /*!< PWM_T::DATA2: PWMx_DATAy15_0 Position */
+#define PWM_DATA2_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA2_PWMx_DATAy15_0_Pos) /*!< PWM_T::DATA2: PWMx_DATAy15_0 Mask */
+
+#define PWM_DATA2_PWMx_DATAy30_16_Pos (16) /*!< PWM_T::DATA2: PWMx_DATAy30_16 Position */
+#define PWM_DATA2_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA2_PWMx_DATAy30_16_Pos) /*!< PWM_T::DATA2: PWMx_DATAy30_16 Mask */
+
+#define PWM_DATA2_sync_Pos (31) /*!< PWM_T::DATA2: sync Position */
+#define PWM_DATA2_sync_Msk (0x1ul << PWM_DATA2_sync_Pos) /*!< PWM_T::DATA2: sync Mask */
+
+#define PWM_DUTY3_CN_Pos (0) /*!< PWM_T::DUTY3: CN Position */
+#define PWM_DUTY3_CN_Msk (0xfffful << PWM_DUTY3_CN_Pos) /*!< PWM_T::DUTY3: CN Mask */
+
+#define PWM_DUTY3_CM_Pos (16) /*!< PWM_T::DUTY3: CM Position */
+#define PWM_DUTY3_CM_Msk (0xfffful << PWM_DUTY3_CM_Pos) /*!< PWM_T::DUTY3: CM Mask */
+
+#define PWM_DATA3_PWMx_DATAy15_0_Pos (0) /*!< PWM_T::DATA3: PWMx_DATAy15_0 Position */
+#define PWM_DATA3_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA3_PWMx_DATAy15_0_Pos) /*!< PWM_T::DATA3: PWMx_DATAy15_0 Mask */
+
+#define PWM_DATA3_PWMx_DATAy30_16_Pos (16) /*!< PWM_T::DATA3: PWMx_DATAy30_16 Position */
+#define PWM_DATA3_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA3_PWMx_DATAy30_16_Pos) /*!< PWM_T::DATA3: PWMx_DATAy30_16 Mask */
+
+#define PWM_DATA3_sync_Pos (31) /*!< PWM_T::DATA3: sync Position */
+#define PWM_DATA3_sync_Msk (0x1ul << PWM_DATA3_sync_Pos) /*!< PWM_T::DATA3: sync Mask */
+
+#define PWM_CAPCTL_INV0_Pos (0) /*!< PWM_T::CAPCTL: INV0 Position */
+#define PWM_CAPCTL_INV0_Msk (0x1ul << PWM_CAPCTL_INV0_Pos) /*!< PWM_T::CAPCTL: INV0 Mask */
+
+#define PWM_CAPCTL_CAPCH0EN_Pos (1) /*!< PWM_T::CAPCTL: CAPCH0EN Position */
+#define PWM_CAPCTL_CAPCH0EN_Msk (0x1ul << PWM_CAPCTL_CAPCH0EN_Pos) /*!< PWM_T::CAPCTL: CAPCH0EN Mask */
+
+#define PWM_CAPCTL_CAPCH0PADEN_Pos (2) /*!< PWM_T::CAPCTL: CAPCH0PADEN Position */
+#define PWM_CAPCTL_CAPCH0PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH0PADEN_Pos) /*!< PWM_T::CAPCTL: CAPCH0PADEN Mask */
+
+#define PWM_CAPCTL_CH0PDMAEN_Pos (3) /*!< PWM_T::CAPCTL: CH0PDMAEN Position */
+#define PWM_CAPCTL_CH0PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH0PDMAEN_Pos) /*!< PWM_T::CAPCTL: CH0PDMAEN Mask */
+
+#define PWM_CAPCTL_PDMACAPMOD0_Pos (4) /*!< PWM_T::CAPCTL: PDMACAPMOD0 Position */
+#define PWM_CAPCTL_PDMACAPMOD0_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD0_Pos) /*!< PWM_T::CAPCTL: PDMACAPMOD0 Mask */
+
+#define PWM_CAPCTL_CAPRELOADREN0_Pos (6) /*!< PWM_T::CAPCTL: CAPRELOADREN0 Position */
+#define PWM_CAPCTL_CAPRELOADREN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN0_Pos) /*!< PWM_T::CAPCTL: CAPRELOADREN0 Mask */
+
+#define PWM_CAPCTL_CAPRELOADFEN0_Pos (7) /*!< PWM_T::CAPCTL: CAPRELOADFEN0 Position */
+#define PWM_CAPCTL_CAPRELOADFEN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN0_Pos) /*!< PWM_T::CAPCTL: CAPRELOADFEN0 Mask */
+
+#define PWM_CAPCTL_INV1_Pos (8) /*!< PWM_T::CAPCTL: INV1 Position */
+#define PWM_CAPCTL_INV1_Msk (0x1ul << PWM_CAPCTL_INV1_Pos) /*!< PWM_T::CAPCTL: INV1 Mask */
+
+#define PWM_CAPCTL_CAPCH1EN_Pos (9) /*!< PWM_T::CAPCTL: CAPCH1EN Position */
+#define PWM_CAPCTL_CAPCH1EN_Msk (0x1ul << PWM_CAPCTL_CAPCH1EN_Pos) /*!< PWM_T::CAPCTL: CAPCH1EN Mask */
+
+#define PWM_CAPCTL_CAPCH1PADEN_Pos (10) /*!< PWM_T::CAPCTL: CAPCH1PADEN Position */
+#define PWM_CAPCTL_CAPCH1PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH1PADEN_Pos) /*!< PWM_T::CAPCTL: CAPCH1PADEN Mask */
+
+#define PWM_CAPCTL_CH0RFORDER_Pos (12) /*!< PWM_T::CAPCTL: CH0RFORDER Position */
+#define PWM_CAPCTL_CH0RFORDER_Msk (0x1ul << PWM_CAPCTL_CH0RFORDER_Pos) /*!< PWM_T::CAPCTL: CH0RFORDER Mask */
+
+#define PWM_CAPCTL_CH01CASK_Pos (13) /*!< PWM_T::CAPCTL: CH01CASK Position */
+#define PWM_CAPCTL_CH01CASK_Msk (0x1ul << PWM_CAPCTL_CH01CASK_Pos) /*!< PWM_T::CAPCTL: CH01CASK Mask */
+
+#define PWM_CAPCTL_CAPRELOADREN1_Pos (14) /*!< PWM_T::CAPCTL: CAPRELOADREN1 Position */
+#define PWM_CAPCTL_CAPRELOADREN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN1_Pos) /*!< PWM_T::CAPCTL: CAPRELOADREN1 Mask */
+
+#define PWM_CAPCTL_CAPRELOADFEN1_Pos (15) /*!< PWM_T::CAPCTL: CAPRELOADFEN1 Position */
+#define PWM_CAPCTL_CAPRELOADFEN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN1_Pos) /*!< PWM_T::CAPCTL: CAPRELOADFEN1 Mask */
+
+#define PWM_CAPCTL_INV2_Pos (16) /*!< PWM_T::CAPCTL: INV2 Position */
+#define PWM_CAPCTL_INV2_Msk (0x1ul << PWM_CAPCTL_INV2_Pos) /*!< PWM_T::CAPCTL: INV2 Mask */
+
+#define PWM_CAPCTL_CAPCH2EN_Pos (17) /*!< PWM_T::CAPCTL: CAPCH2EN Position */
+#define PWM_CAPCTL_CAPCH2EN_Msk (0x1ul << PWM_CAPCTL_CAPCH2EN_Pos) /*!< PWM_T::CAPCTL: CAPCH2EN Mask */
+
+#define PWM_CAPCTL_CAPCH2PADEN_Pos (18) /*!< PWM_T::CAPCTL: CAPCH2PADEN Position */
+#define PWM_CAPCTL_CAPCH2PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH2PADEN_Pos) /*!< PWM_T::CAPCTL: CAPCH2PADEN Mask */
+
+#define PWM_CAPCTL_CH2PDMAEN_Pos (19) /*!< PWM_T::CAPCTL: CH2PDMAEN Position */
+#define PWM_CAPCTL_CH2PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH2PDMAEN_Pos) /*!< PWM_T::CAPCTL: CH2PDMAEN Mask */
+
+#define PWM_CAPCTL_PDMACAPMOD2_Pos (20) /*!< PWM_T::CAPCTL: PDMACAPMOD2 Position */
+#define PWM_CAPCTL_PDMACAPMOD2_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD2_Pos) /*!< PWM_T::CAPCTL: PDMACAPMOD2 Mask */
+
+#define PWM_CAPCTL_CAPRELOADREN2_Pos (22) /*!< PWM_T::CAPCTL: CAPRELOADREN2 Position */
+#define PWM_CAPCTL_CAPRELOADREN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN2_Pos) /*!< PWM_T::CAPCTL: CAPRELOADREN2 Mask */
+
+#define PWM_CAPCTL_CAPRELOADFEN2_Pos (23) /*!< PWM_T::CAPCTL: CAPRELOADFEN2 Position */
+#define PWM_CAPCTL_CAPRELOADFEN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN2_Pos) /*!< PWM_T::CAPCTL: CAPRELOADFEN2 Mask */
+
+#define PWM_CAPCTL_INV3_Pos (24) /*!< PWM_T::CAPCTL: INV3 Position */
+#define PWM_CAPCTL_INV3_Msk (0x1ul << PWM_CAPCTL_INV3_Pos) /*!< PWM_T::CAPCTL: INV3 Mask */
+
+#define PWM_CAPCTL_CAPCH3EN_Pos (25) /*!< PWM_T::CAPCTL: CAPCH3EN Position */
+#define PWM_CAPCTL_CAPCH3EN_Msk (0x1ul << PWM_CAPCTL_CAPCH3EN_Pos) /*!< PWM_T::CAPCTL: CAPCH3EN Mask */
+
+#define PWM_CAPCTL_CAPCH3PADEN_Pos (26) /*!< PWM_T::CAPCTL: CAPCH3PADEN Position */
+#define PWM_CAPCTL_CAPCH3PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH3PADEN_Pos) /*!< PWM_T::CAPCTL: CAPCH3PADEN Mask */
+
+#define PWM_CAPCTL_CH2RFORDER_Pos (28) /*!< PWM_T::CAPCTL: CH2RFORDER Position */
+#define PWM_CAPCTL_CH2RFORDER_Msk (0x1ul << PWM_CAPCTL_CH2RFORDER_Pos) /*!< PWM_T::CAPCTL: CH2RFORDER Mask */
+
+#define PWM_CAPCTL_CH23CASK_Pos (29) /*!< PWM_T::CAPCTL: CH23CASK Position */
+#define PWM_CAPCTL_CH23CASK_Msk (0x1ul << PWM_CAPCTL_CH23CASK_Pos) /*!< PWM_T::CAPCTL: CH23CASK Mask */
+
+#define PWM_CAPCTL_CAPRELOADREN3_Pos (30) /*!< PWM_T::CAPCTL: CAPRELOADREN3 Position */
+#define PWM_CAPCTL_CAPRELOADREN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN3_Pos) /*!< PWM_T::CAPCTL: CAPRELOADREN3 Mask */
+
+#define PWM_CAPCTL_CAPRELOADFEN3_Pos (31) /*!< PWM_T::CAPCTL: CAPRELOADFEN3 Position */
+#define PWM_CAPCTL_CAPRELOADFEN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN3_Pos) /*!< PWM_T::CAPCTL: CAPRELOADFEN3 Mask */
+
+#define PWM_CAPINTEN_CRL_IE0_Pos (0) /*!< PWM_T::CAPINTEN: CRL_IE0 Position */
+#define PWM_CAPINTEN_CRL_IE0_Msk (0x1ul << PWM_CAPINTEN_CRL_IE0_Pos) /*!< PWM_T::CAPINTEN: CRL_IE0 Mask */
+
+#define PWM_CAPINTEN_CFL_IE0_Pos (1) /*!< PWM_T::CAPINTEN: CFL_IE0 Position */
+#define PWM_CAPINTEN_CFL_IE0_Msk (0x1ul << PWM_CAPINTEN_CFL_IE0_Pos) /*!< PWM_T::CAPINTEN: CFL_IE0 Mask */
+
+#define PWM_CAPINTEN_CRL_IE1_Pos (8) /*!< PWM_T::CAPINTEN: CRL_IE1 Position */
+#define PWM_CAPINTEN_CRL_IE1_Msk (0x1ul << PWM_CAPINTEN_CRL_IE1_Pos) /*!< PWM_T::CAPINTEN: CRL_IE1 Mask */
+
+#define PWM_CAPINTEN_CFL_IE1_Pos (9) /*!< PWM_T::CAPINTEN: CFL_IE1 Position */
+#define PWM_CAPINTEN_CFL_IE1_Msk (0x1ul << PWM_CAPINTEN_CFL_IE1_Pos) /*!< PWM_T::CAPINTEN: CFL_IE1 Mask */
+
+#define PWM_CAPINTEN_CRL_IE2_Pos (16) /*!< PWM_T::CAPINTEN: CRL_IE2 Position */
+#define PWM_CAPINTEN_CRL_IE2_Msk (0x1ul << PWM_CAPINTEN_CRL_IE2_Pos) /*!< PWM_T::CAPINTEN: CRL_IE2 Mask */
+
+#define PWM_CAPINTEN_CFL_IE2_Pos (17) /*!< PWM_T::CAPINTEN: CFL_IE2 Position */
+#define PWM_CAPINTEN_CFL_IE2_Msk (0x1ul << PWM_CAPINTEN_CFL_IE2_Pos) /*!< PWM_T::CAPINTEN: CFL_IE2 Mask */
+
+#define PWM_CAPINTEN_CRL_IE3_Pos (24) /*!< PWM_T::CAPINTEN: CRL_IE3 Position */
+#define PWM_CAPINTEN_CRL_IE3_Msk (0x1ul << PWM_CAPINTEN_CRL_IE3_Pos) /*!< PWM_T::CAPINTEN: CRL_IE3 Mask */
+
+#define PWM_CAPINTEN_CFL_IE3_Pos (25) /*!< PWM_T::CAPINTEN: CFL_IE3 Position */
+#define PWM_CAPINTEN_CFL_IE3_Msk (0x1ul << PWM_CAPINTEN_CFL_IE3_Pos) /*!< PWM_T::CAPINTEN: CFL_IE3 Mask */
+
+#define PWM_CAPINTSTS_CAPIF0_Pos (0) /*!< PWM_T::CAPINTSTS: CAPIF0 Position */
+#define PWM_CAPINTSTS_CAPIF0_Msk (0x1ul << PWM_CAPINTSTS_CAPIF0_Pos) /*!< PWM_T::CAPINTSTS: CAPIF0 Mask */
+
+#define PWM_CAPINTSTS_CRLI0_Pos (1) /*!< PWM_T::CAPINTSTS: CRLI0 Position */
+#define PWM_CAPINTSTS_CRLI0_Msk (0x1ul << PWM_CAPINTSTS_CRLI0_Pos) /*!< PWM_T::CAPINTSTS: CRLI0 Mask */
+
+#define PWM_CAPINTSTS_CFLRI0_Pos (2) /*!< PWM_T::CAPINTSTS: CFLRI0 Position */
+#define PWM_CAPINTSTS_CFLRI0_Msk (0x1ul << PWM_CAPINTSTS_CFLRI0_Pos) /*!< PWM_T::CAPINTSTS: CFLRI0 Mask */
+
+#define PWM_CAPINTSTS_CAPOVR0_Pos (3) /*!< PWM_T::CAPINTSTS: CAPOVR0 Position */
+#define PWM_CAPINTSTS_CAPOVR0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR0_Pos) /*!< PWM_T::CAPINTSTS: CAPOVR0 Mask */
+
+#define PWM_CAPINTSTS_CAPOVF0_Pos (4) /*!< PWM_T::CAPINTSTS: CAPOVF0 Position */
+#define PWM_CAPINTSTS_CAPOVF0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF0_Pos) /*!< PWM_T::CAPINTSTS: CAPOVF0 Mask */
+
+#define PWM_CAPINTSTS_CAPIF1_Pos (8) /*!< PWM_T::CAPINTSTS: CAPIF1 Position */
+#define PWM_CAPINTSTS_CAPIF1_Msk (0x1ul << PWM_CAPINTSTS_CAPIF1_Pos) /*!< PWM_T::CAPINTSTS: CAPIF1 Mask */
+
+#define PWM_CAPINTSTS_CRLI1_Pos (9) /*!< PWM_T::CAPINTSTS: CRLI1 Position */
+#define PWM_CAPINTSTS_CRLI1_Msk (0x1ul << PWM_CAPINTSTS_CRLI1_Pos) /*!< PWM_T::CAPINTSTS: CRLI1 Mask */
+
+#define PWM_CAPINTSTS_CFLI1_Pos (10) /*!< PWM_T::CAPINTSTS: CFLI1 Position */
+#define PWM_CAPINTSTS_CFLI1_Msk (0x1ul << PWM_CAPINTSTS_CFLI1_Pos) /*!< PWM_T::CAPINTSTS: CFLI1 Mask */
+
+#define PWM_CAPINTSTS_CAPOVR1_Pos (11) /*!< PWM_T::CAPINTSTS: CAPOVR1 Position */
+#define PWM_CAPINTSTS_CAPOVR1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR1_Pos) /*!< PWM_T::CAPINTSTS: CAPOVR1 Mask */
+
+#define PWM_CAPINTSTS_CAPOVF1_Pos (12) /*!< PWM_T::CAPINTSTS: CAPOVF1 Position */
+#define PWM_CAPINTSTS_CAPOVF1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF1_Pos) /*!< PWM_T::CAPINTSTS: CAPOVF1 Mask */
+
+#define PWM_CAPINTSTS_CAPIF2_Pos (16) /*!< PWM_T::CAPINTSTS: CAPIF2 Position */
+#define PWM_CAPINTSTS_CAPIF2_Msk (0x1ul << PWM_CAPINTSTS_CAPIF2_Pos) /*!< PWM_T::CAPINTSTS: CAPIF2 Mask */
+
+#define PWM_CAPINTSTS_CRLI2_Pos (17) /*!< PWM_T::CAPINTSTS: CRLI2 Position */
+#define PWM_CAPINTSTS_CRLI2_Msk (0x1ul << PWM_CAPINTSTS_CRLI2_Pos) /*!< PWM_T::CAPINTSTS: CRLI2 Mask */
+
+#define PWM_CAPINTSTS_CFLI2_Pos (18) /*!< PWM_T::CAPINTSTS: CFLI2 Position */
+#define PWM_CAPINTSTS_CFLI2_Msk (0x1ul << PWM_CAPINTSTS_CFLI2_Pos) /*!< PWM_T::CAPINTSTS: CFLI2 Mask */
+
+#define PWM_CAPINTSTS_CAPOVR2_Pos (19) /*!< PWM_T::CAPINTSTS: CAPOVR2 Position */
+#define PWM_CAPINTSTS_CAPOVR2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR2_Pos) /*!< PWM_T::CAPINTSTS: CAPOVR2 Mask */
+
+#define PWM_CAPINTSTS_CAPOVF2_Pos (20) /*!< PWM_T::CAPINTSTS: CAPOVF2 Position */
+#define PWM_CAPINTSTS_CAPOVF2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF2_Pos) /*!< PWM_T::CAPINTSTS: CAPOVF2 Mask */
+
+#define PWM_CAPINTSTS_CAPIF3_Pos (24) /*!< PWM_T::CAPINTSTS: CAPIF3 Position */
+#define PWM_CAPINTSTS_CAPIF3_Msk (0x1ul << PWM_CAPINTSTS_CAPIF3_Pos) /*!< PWM_T::CAPINTSTS: CAPIF3 Mask */
+
+#define PWM_CAPINTSTS_CRLI3_Pos (25) /*!< PWM_T::CAPINTSTS: CRLI3 Position */
+#define PWM_CAPINTSTS_CRLI3_Msk (0x1ul << PWM_CAPINTSTS_CRLI3_Pos) /*!< PWM_T::CAPINTSTS: CRLI3 Mask */
+
+#define PWM_CAPINTSTS_CFLI3_Pos (26) /*!< PWM_T::CAPINTSTS: CFLI3 Position */
+#define PWM_CAPINTSTS_CFLI3_Msk (0x1ul << PWM_CAPINTSTS_CFLI3_Pos) /*!< PWM_T::CAPINTSTS: CFLI3 Mask */
+
+#define PWM_CAPINTSTS_CAPOVR3_Pos (27) /*!< PWM_T::CAPINTSTS: CAPOVR3 Position */
+#define PWM_CAPINTSTS_CAPOVR3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR3_Pos) /*!< PWM_T::CAPINTSTS: CAPOVR3 Mask */
+
+#define PWM_CAPINTSTS_CAPOVF3_Pos (28) /*!< PWM_T::CAPINTSTS: CAPOVF3 Position */
+#define PWM_CAPINTSTS_CAPOVF3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF3_Pos) /*!< PWM_T::CAPINTSTS: CAPOVF3 Mask */
+
+#define PWM_CRL0_CRL15_0_Pos (0) /*!< PWM_T::CRL0: CRL15_0 Position */
+#define PWM_CRL0_CRL15_0_Msk (0xfffful << PWM_CRL0_CRL15_0_Pos) /*!< PWM_T::CRL0: CRL15_0 Mask */
+
+#define PWM_CRL0_CRL31_16_Pos (16) /*!< PWM_T::CRL0: CRL31_16 Position */
+#define PWM_CRL0_CRL31_16_Msk (0xfffful << PWM_CRL0_CRL31_16_Pos) /*!< PWM_T::CRL0: CRL31_16 Mask */
+
+#define PWM_CFL0_CFL15_0_Pos (0) /*!< PWM_T::CFL0: CFL15_0 Position */
+#define PWM_CFL0_CFL15_0_Msk (0xfffful << PWM_CFL0_CFL15_0_Pos) /*!< PWM_T::CFL0: CFL15_0 Mask */
+
+#define PWM_CFL0_CFL31_16_Pos (16) /*!< PWM_T::CFL0: CFL31_16 Position */
+#define PWM_CFL0_CFL31_16_Msk (0xfffful << PWM_CFL0_CFL31_16_Pos) /*!< PWM_T::CFL0: CFL31_16 Mask */
+
+#define PWM_CRL1_CRL15_0_Pos (0) /*!< PWM_T::CRL1: CRL15_0 Position */
+#define PWM_CRL1_CRL15_0_Msk (0xfffful << PWM_CRL1_CRL15_0_Pos) /*!< PWM_T::CRL1: CRL15_0 Mask */
+
+#define PWM_CRL1_CRL31_16_Pos (16) /*!< PWM_T::CRL1: CRL31_16 Position */
+#define PWM_CRL1_CRL31_16_Msk (0xfffful << PWM_CRL1_CRL31_16_Pos) /*!< PWM_T::CRL1: CRL31_16 Mask */
+
+#define PWM_CFL1_CFL15_0_Pos (0) /*!< PWM_T::CFL1: CFL15_0 Position */
+#define PWM_CFL1_CFL15_0_Msk (0xfffful << PWM_CFL1_CFL15_0_Pos) /*!< PWM_T::CFL1: CFL15_0 Mask */
+
+#define PWM_CFL1_CFL31_16_Pos (16) /*!< PWM_T::CFL1: CFL31_16 Position */
+#define PWM_CFL1_CFL31_16_Msk (0xfffful << PWM_CFL1_CFL31_16_Pos) /*!< PWM_T::CFL1: CFL31_16 Mask */
+
+#define PWM_CRL2_CRL15_0_Pos (0) /*!< PWM_T::CRL2: CRL15_0 Position */
+#define PWM_CRL2_CRL15_0_Msk (0xfffful << PWM_CRL2_CRL15_0_Pos) /*!< PWM_T::CRL2: CRL15_0 Mask */
+
+#define PWM_CRL2_CRL31_16_Pos (16) /*!< PWM_T::CRL2: CRL31_16 Position */
+#define PWM_CRL2_CRL31_16_Msk (0xfffful << PWM_CRL2_CRL31_16_Pos) /*!< PWM_T::CRL2: CRL31_16 Mask */
+
+#define PWM_CFL2_CFL15_0_Pos (0) /*!< PWM_T::CFL2: CFL15_0 Position */
+#define PWM_CFL2_CFL15_0_Msk (0xfffful << PWM_CFL2_CFL15_0_Pos) /*!< PWM_T::CFL2: CFL15_0 Mask */
+
+#define PWM_CFL2_CFL31_16_Pos (16) /*!< PWM_T::CFL2: CFL31_16 Position */
+#define PWM_CFL2_CFL31_16_Msk (0xfffful << PWM_CFL2_CFL31_16_Pos) /*!< PWM_T::CFL2: CFL31_16 Mask */
+
+#define PWM_CRL3_CRL15_0_Pos (0) /*!< PWM_T::CRL3: CRL15_0 Position */
+#define PWM_CRL3_CRL15_0_Msk (0xfffful << PWM_CRL3_CRL15_0_Pos) /*!< PWM_T::CRL3: CRL15_0 Mask */
+
+#define PWM_CRL3_CRL31_16_Pos (16) /*!< PWM_T::CRL3: CRL31_16 Position */
+#define PWM_CRL3_CRL31_16_Msk (0xfffful << PWM_CRL3_CRL31_16_Pos) /*!< PWM_T::CRL3: CRL31_16 Mask */
+
+#define PWM_CFL3_CFL15_0_Pos (0) /*!< PWM_T::CFL3: CFL15_0 Position */
+#define PWM_CFL3_CFL15_0_Msk (0xfffful << PWM_CFL3_CFL15_0_Pos) /*!< PWM_T::CFL3: CFL15_0 Mask */
+
+#define PWM_CFL3_CFL31_16_Pos (16) /*!< PWM_T::CFL3: CFL31_16 Position */
+#define PWM_CFL3_CFL31_16_Msk (0xfffful << PWM_CFL3_CFL31_16_Pos) /*!< PWM_T::CFL3: CFL31_16 Mask */
+
+#define PWM_PDMACH0_Captureddata7_0_Pos (0) /*!< PWM_T::PDMACH0: Captureddata7_0 Position */
+#define PWM_PDMACH0_Captureddata7_0_Msk (0xfful << PWM_PDMACH0_Captureddata7_0_Pos) /*!< PWM_T::PDMACH0: Captureddata7_0 Mask */
+
+#define PWM_PDMACH0_Captureddata15_8_Pos (8) /*!< PWM_T::PDMACH0: Captureddata15_8 Position */
+#define PWM_PDMACH0_Captureddata15_8_Msk (0xfful << PWM_PDMACH0_Captureddata15_8_Pos) /*!< PWM_T::PDMACH0: Captureddata15_8 Mask */
+
+#define PWM_PDMACH0_Captureddata23_16_Pos (16) /*!< PWM_T::PDMACH0: Captureddata23_16 Position*/
+#define PWM_PDMACH0_Captureddata23_16_Msk (0xfful << PWM_PDMACH0_Captureddata23_16_Pos) /*!< PWM_T::PDMACH0: Captureddata23_16 Mask */
+
+#define PWM_PDMACH0_Captureddata31_24_Pos (24) /*!< PWM_T::PDMACH0: Captureddata31_24 Position*/
+#define PWM_PDMACH0_Captureddata31_24_Msk (0xfful << PWM_PDMACH0_Captureddata31_24_Pos) /*!< PWM_T::PDMACH0: Captureddata31_24 Mask */
+
+#define PWM_PDMACH2_Captureddata7_0_Pos (0) /*!< PWM_T::PDMACH2: Captureddata7_0 Position */
+#define PWM_PDMACH2_Captureddata7_0_Msk (0xfful << PWM_PDMACH2_Captureddata7_0_Pos) /*!< PWM_T::PDMACH2: Captureddata7_0 Mask */
+
+#define PWM_PDMACH2_Captureddata15_8_Pos (8) /*!< PWM_T::PDMACH2: Captureddata15_8 Position */
+#define PWM_PDMACH2_Captureddata15_8_Msk (0xfful << PWM_PDMACH2_Captureddata15_8_Pos) /*!< PWM_T::PDMACH2: Captureddata15_8 Mask */
+
+#define PWM_PDMACH2_Captureddata23_16_Pos (16) /*!< PWM_T::PDMACH2: Captureddata23_16 Position*/
+#define PWM_PDMACH2_Captureddata23_16_Msk (0xfful << PWM_PDMACH2_Captureddata23_16_Pos) /*!< PWM_T::PDMACH2: Captureddata23_16 Mask */
+
+#define PWM_PDMACH2_Captureddata31_24_Pos (24) /*!< PWM_T::PDMACH2: Captureddata31_24 Position*/
+#define PWM_PDMACH2_Captureddata31_24_Msk (0xfful << PWM_PDMACH2_Captureddata31_24_Pos) /*!< PWM_T::PDMACH2: Captureddata31_24 Mask */
+
+/**@}*/ /* PWM_CONST */
+/**@}*/ /* end of PWM register group */
+
+
+/*---------------------- Real Time Clock Controller -------------------------*/
+/**
+ @addtogroup RTC Real Time Clock Controller(RTC)
+ Memory Mapped Structure for RTC Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * INIR
+ * ===================================================================================================
+ * Offset: 0x00 RTC Initiation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACTIVE |RTC Active Status (Read Only)
+ * | | |0 = RTC is at reset state.
+ * | | |1 = RTC is at normal active state.
+ * |[31:1] |INIR |RTC Initiation (Write Only)
+ * | | |When RTC block is powered on, RTC is at reset state.
+ * | | |User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state.
+ * | | |Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
+ * | | |The INIR is a write-only field and read value will be always "0".
+ */
+ __IO uint32_t INIR;
+
+ /**
+ * AER
+ * ===================================================================================================
+ * Offset: 0x04 RTC Access Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |AER |RTC Register Access Enable Password (Write Only)
+ * | | |Enable RTC access after write 0xA965. Otherwise disable RTC access.
+ * |[16] |ENF |RTC Register Access Enable Flag (Read Only)
+ * | | |1 = RTC register read/write Enabled.
+ * | | |0 = RTC register read/write Disabled.
+ * | | |This bit will be set after AER[15:0] register is load a 0xA965, and be cleared automatically 512 RTC clocks or AER[15:0] is not 0xA965.
+ */
+ __IO uint32_t AER;
+
+ /**
+ * FCR
+ * ===================================================================================================
+ * Offset: 0x08 RTC Frequency Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |FRACTION |Fraction Part
+ * | | |Formula = (fraction part of detected value) x 64.
+ * | | |Note: Digit in FCR must be expressed as hexadecimal number.
+ * |[11:8] |INTEGER |Integer Part
+ * | | |0000 = 32761.
+ * | | |0001 = 32762.
+ * | | |0010 = 32763.
+ * | | |0011 = 32764.
+ * | | |0100 = 32765.
+ * | | |0101 = 32766.
+ * | | |0110 = 32767.
+ * | | |0111 = 32768.
+ * | | |1000 = 32769.
+ * | | |1001 = 32770.
+ * | | |1010 = 32771.
+ * | | |1011 = 32772.
+ * | | |1100 = 32773.
+ * | | |1101 = 32774.
+ * | | |1110 = 32775.
+ * | | |1111 = 32776.
+ */
+ __IO uint32_t FCR;
+
+ /**
+ * TLR
+ * ===================================================================================================
+ * Offset: 0x0C Time Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |1SEC |1 Sec Time Digit (0~9)
+ * |[6:4] |10SEC |10 Sec Time Digit (0~5)
+ * |[11:8] |1MIN |1 Min Time Digit (0~9)
+ * |[14:12] |10MIN |10 Min Time Digit (0~5)
+ * |[19:16] |1HR |1 Hour Time Digit (0~9)
+ * |[21:20] |10HR |10 Hour Time Digit (0~2)
+ */
+ __IO uint32_t TLR;
+
+ /**
+ * CLR
+ * ===================================================================================================
+ * Offset: 0x10 Calendar Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |1DAY |1 Day Calendar Digit (0~9)
+ * |[5:4] |10DAY |10 Day Calendar Digit (0~3)
+ * |[11:8] |1MON |1 Month Calendar Digit (0~9)
+ * |[12] |10MON |10 Month Calendar Digit (0~1)
+ * |[19:16] |1YEAR |1 Year Calendar Digit (0~9)
+ * |[23:20] |10YEAR |10 Year Calendar Digit (0~9)
+ */
+ __IO uint32_t CLR;
+
+ /**
+ * TSSR
+ * ===================================================================================================
+ * Offset: 0x14 Time Scale Selection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |24hr_12hr |24-Hour / 12-Hour Mode Selection
+ * | | |It indicates that TLR and TAR are in 24-hour mode or 12-hour mode
+ * | | |0 = select 12-hour time scale with AM and PM indication.
+ * | | |1 = select 24-hour time scale.
+ */
+ __IO uint32_t TSSR;
+
+ /**
+ * DWR
+ * ===================================================================================================
+ * Offset: 0x18 Day of the Week Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |DWR |Day Of The Week Register
+ * | | |000 = Sunday.
+ * | | |001 = Monday.
+ * | | |010 = Tuesday.
+ * | | |011 = Wednesday.
+ * | | |100 = Thursday.
+ * | | |101 = Friday.
+ * | | |110 = Saturday.
+ */
+ __IO uint32_t DWR;
+
+ /**
+ * TAR
+ * ===================================================================================================
+ * Offset: 0x1C Time Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |1SEC |1 Sec Time Digit of Alarm Setting (0~9)
+ * |[6:4] |10SEC |10 Sec Time Digit of Alarm Setting (0~5)
+ * |[11:8] |1MIN |1 Min Time Digit of Alarm Setting (0~9)
+ * |[14:12] |10MIN |10 Min Time Digit of Alarm Setting (0~5)
+ * |[19:16] |1HR |1 Hour Time Digit of Alarm Setting (0~9)
+ * |[21:20] |10HR |10 Hour Time Digit of Alarm Setting (0~2)
+ */
+ __IO uint32_t TAR;
+
+ /**
+ * CAR
+ * ===================================================================================================
+ * Offset: 0x20 Calendar Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |1DAY |1 Day Calendar Digit of Alarm Setting (0~9)
+ * |[5:4] |10DAY |10 Day Calendar Digit of Alarm Setting (0~3)
+ * |[11:8] |1MON |1 Month Calendar Digit of Alarm Setting (0~9)
+ * |[12] |10MON |10 Month Calendar Digit of Alarm Setting (0~1)
+ * |[19:16] |1YEAR |1 Year Calendar Digit of Alarm Setting (0~9)
+ * |[23:20] |10YEAR |10 Year Calendar Digit of Alarm Setting (0~9)
+ */
+ __IO uint32_t CAR;
+
+ /**
+ * LIR
+ * ===================================================================================================
+ * Offset: 0x24 Leap Year Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LIR |Leap Year Indication REGISTER (Read Only)
+ * | | |0 = This year is not a leap year.
+ * | | |1 = This year is leap year.
+ */
+ __I uint32_t LIR;
+
+ /**
+ * RIER
+ * ===================================================================================================
+ * Offset: 0x28 RTC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |AIER |Alarm Interrupt Enable
+ * | | |0 = RTC Alarm Interrupt is disabled.
+ * | | |1 = RTC Alarm Interrupt is enabled.
+ * |[1] |TIER |Time Tick Interrupt And Wake-Up By Tick Enable
+ * | | |0 = RTC Time Tick Interrupt is disabled.
+ * | | |1 = RTC Time Tick Interrupt is enabled.
+ * |[2] |SNOOPIER |Snooper Pin Event Detection Interrupt Enable
+ * | | |0 = Snooper Pin Event Detection Interrupt is disabled.
+ * | | |1 = Snooper Pin Event Detection Interrupt is enabled.
+ */
+ __IO uint32_t RIER;
+
+ /**
+ * RIIR
+ * ===================================================================================================
+ * Offset: 0x2C RTC Interrupt Indication Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |AIS |RTC Alarm Interrupt Status
+ * | | |RTC unit will set AIS to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR.
+ * | | |When this bit is set and AIER is also high, RTC will generate an interrupt to CPU.
+ * | | |This bit is cleared by writing "1" to it through software.
+ * | | |0 = RCT Alarm Interrupt condition never occurred.
+ * | | |1 = RTC Alarm Interrupt is requested if RIER.AIER=1.
+ * |[1] |TIS |RTC Time Tick Interrupt Status
+ * | | |RTC unit will set TIF to high periodically in the period selected by TTR[2:0].
+ * | | |When this bit is set and TIER is also high, RTC will generate an interrupt to CPU.
+ * | | |This bit is cleared by writing "1" to it through software.
+ * | | |0 = RCT Time Tick Interrupt condition never occurred.
+ * | | |1 = RTC Time Tick Interrupt is requested.
+ * |[2] |SNOOPIF |Snooper Pin Event Detection Interrupt Flag
+ * | | |When SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin, this flag will be set.
+ * | | |While this bit is set and SNOOPIER is also high, RTC will generate an interrupt to CPU.
+ * | | |Write "1" to clear this bit to "0".
+ * | | |0 = Snooper pin event defined by SNOOPEDGE never detected.
+ * | | |1 = Snooper pin event defined by SNOOPEDGE detected.
+ */
+ __IO uint32_t RIIR;
+
+ /**
+ * TTR
+ * ===================================================================================================
+ * Offset: 0x30 RTC Time Tick Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TTR |Time Tick Register
+ * | | |The RTC time tick period for Periodic Time Tick Interrupt request.
+ * | | |000 = 1 tick/second.
+ * | | |001 = 1/2 tick/second.
+ * | | |010 = 1/4 tick/second.
+ * | | |011 = 1/8 tick/second.
+ * | | |100 = 1/16 tick/second.
+ * | | |101 = 1/32 tick/second.
+ * | | |110 = 1/64 tick/second.
+ * | | |111 = 1/128 tick/second.
+ * | | |Note: This register can be read back after the RTC is active by AER.
+ * |[3] |TWKE |RTC Timer Wake-Up CPU Function Enable Bit
+ * | | |If TWKE is set before CPU enters power-down mode, when a RTC Time Tick, CPU will be wakened up by RTC unit.
+ * | | |0 = Time Tick wake-up CPU function Disabled.
+ * | | |1 = Wake-up function Enabled so that CPU can be waken up from Power-down mode by Time Tick.
+ * | | |Note: Tick timer setting follows the TTR description.
+ */
+ __IO uint32_t TTR;
+ uint32_t RESERVE0[2];
+
+
+ /**
+ * SPRCTL
+ * ===================================================================================================
+ * Offset: 0x3C RTC Spare Functional Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SNOOPEN |Snooper Pin Event Detection Enable
+ * | | |This bit enables the snooper pin event detection.
+ * | | |When this bit is set high and an event defined by SNOOPEDGE detected, the 20 spare registers will be cleared to "0" by hardware automatically.
+ * | | |And, the SNOOPIF will also be set.
+ * | | |In addition, RTC will also generate wake-up event to wake system up.
+ * | | |0 = Snooper pin event detection function Disabled.
+ * | | |1 = Snooper pin event detection function Enabled.
+ * |[1] |SNOOPEDGE |Snooper Active Edge Selection
+ * | | |This bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers.
+ * | | |0 = Rising edge of snooper pin generates snooper pin detected event.
+ * | | |1 = Falling edge of snooper pin generates snooper pin detected event.
+ * |[7] |SPRRDY |SPR Register Ready
+ * | | |This bit indicates if the registers SPR0 ~ SPR19 are ready to read.
+ * | | |After CPU writing registers SPR0 ~ SPR19, polling this bit to check if SP0 ~ SPR19 are updated done is necessary.
+ * | | |This it is read only and any write to this bit won't take any effect.
+ * | | |0 = SPR0 ~ SPR19 updating is in progress.
+ * | | |1 = SPR0 ~ SPR19 are updated done and ready to read.
+ */
+ __IO uint32_t SPRCTL;
+
+ /**
+ * SPR0 ~ 19
+ * ===================================================================================================
+ * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SPARE |SPARE
+ * | | |This field is used to store back-up information defined by software.
+ * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
+ */
+ __IO uint32_t SPR[20];
+
+} RTC_T;
+
+/**
+ @addtogroup RTC_CONST RTC Bit Field Definition
+ Constant Definitions for RTC Controller
+@{ */
+
+#define RTC_INIR_ACTIVE_Pos (0) /*!< RTC_T::INIR: ACTIVE Position */
+#define RTC_INIR_ACTIVE_Msk (0x1ul << RTC_INIR_ACTIVE_Pos) /*!< RTC_T::INIR: ACTIVE Mask */
+
+#define RTC_INIR_INIR_Pos (0) /*!< RTC_T::INIR: INIR Position */
+#define RTC_INIR_INIR_Msk (0xfffffffful << RTC_INIR_INIR_Pos) /*!< RTC_T::INIR: INIR Mask */
+
+#define RTC_AER_AER_Pos (0) /*!< RTC_T::AER: AER Position */
+#define RTC_AER_AER_Msk (0xfffful << RTC_AER_AER_Pos) /*!< RTC_T::AER: AER Mask */
+
+#define RTC_AER_ENF_Pos (16) /*!< RTC_T::AER: ENF Position */
+#define RTC_AER_ENF_Msk (0x1ul << RTC_AER_ENF_Pos) /*!< RTC_T::AER: ENF Mask */
+
+#define RTC_FCR_FRACTION_Pos (0) /*!< RTC_T::FCR: FRACTION Position */
+#define RTC_FCR_FRACTION_Msk (0x3ful << RTC_FCR_FRACTION_Pos) /*!< RTC_T::FCR: FRACTION Mask */
+
+#define RTC_FCR_INTEGER_Pos (8) /*!< RTC_T::FCR: INTEGER Position */
+#define RTC_FCR_INTEGER_Msk (0xful << RTC_FCR_INTEGER_Pos) /*!< RTC_T::FCR: INTEGER Mask */
+
+#define RTC_TLR_1SEC_Pos (0) /*!< RTC_T::TLR: 1SEC Position */
+#define RTC_TLR_1SEC_Msk (0xful << RTC_TLR_1SEC_Pos) /*!< RTC_T::TLR: 1SEC Mask */
+
+#define RTC_TLR_10SEC_Pos (4) /*!< RTC_T::TLR: 10SEC Position */
+#define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos) /*!< RTC_T::TLR: 10SEC Mask */
+
+#define RTC_TLR_1MIN_Pos (8) /*!< RTC_T::TLR: 1MIN Position */
+#define RTC_TLR_1MIN_Msk (0xful << RTC_TLR_1MIN_Pos) /*!< RTC_T::TLR: 1MIN Mask */
+
+#define RTC_TLR_10MIN_Pos (12) /*!< RTC_T::TLR: 10MIN Position */
+#define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos) /*!< RTC_T::TLR: 10MIN Mask */
+
+#define RTC_TLR_1HR_Pos (16) /*!< RTC_T::TLR: 1HR Position */
+#define RTC_TLR_1HR_Msk (0xful << RTC_TLR_1HR_Pos) /*!< RTC_T::TLR: 1HR Mask */
+
+#define RTC_TLR_10HR_Pos (20) /*!< RTC_T::TLR: 10HR Position */
+#define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos) /*!< RTC_T::TLR: 10HR Mask */
+
+#define RTC_CLR_1DAY_Pos (0) /*!< RTC_T::CLR: 1DAY Position */
+#define RTC_CLR_1DAY_Msk (0xful << RTC_CLR_1DAY_Pos) /*!< RTC_T::CLR: 1DAY Mask */
+
+#define RTC_CLR_10DAY_Pos (4) /*!< RTC_T::CLR: 10DAY Position */
+#define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos) /*!< RTC_T::CLR: 10DAY Mask */
+
+#define RTC_CLR_1MON_Pos (8) /*!< RTC_T::CLR: 1MON Position */
+#define RTC_CLR_1MON_Msk (0xful << RTC_CLR_1MON_Pos) /*!< RTC_T::CLR: 1MON Mask */
+
+#define RTC_CLR_10MON_Pos (12) /*!< RTC_T::CLR: 10MON Position */
+#define RTC_CLR_10MON_Msk (0x1ul << RTC_CLR_10MON_Pos) /*!< RTC_T::CLR: 10MON Mask */
+
+#define RTC_CLR_1YEAR_Pos (16) /*!< RTC_T::CLR: 1YEAR Position */
+#define RTC_CLR_1YEAR_Msk (0xful << RTC_CLR_1YEAR_Pos) /*!< RTC_T::CLR: 1YEAR Mask */
+
+#define RTC_CLR_10YEAR_Pos (20) /*!< RTC_T::CLR: 10YEAR Position */
+#define RTC_CLR_10YEAR_Msk (0xful << RTC_CLR_10YEAR_Pos) /*!< RTC_T::CLR: 10YEAR Mask */
+
+#define RTC_TSSR_24H_12H_Pos (0) /*!< RTC_T::TSSR: 24hr_12hr Position */
+#define RTC_TSSR_24H_12H_Msk (0x1ul << RTC_TSSR_24H_12H_Pos) /*!< RTC_T::TSSR: 24hr_12hr Mask */
+
+#define RTC_DWR_DWR_Pos (0) /*!< RTC_T::DWR: DWR Position */
+#define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos) /*!< RTC_T::DWR: DWR Mask */
+
+#define RTC_TAR_1SEC_Pos (0) /*!< RTC_T::TAR: 1SEC Position */
+#define RTC_TAR_1SEC_Msk (0xful << RTC_TAR_1SEC_Pos) /*!< RTC_T::TAR: 1SEC Mask */
+
+#define RTC_TAR_10SEC_Pos (4) /*!< RTC_T::TAR: 10SEC Position */
+#define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos) /*!< RTC_T::TAR: 10SEC Mask */
+
+#define RTC_TAR_1MIN_Pos (8) /*!< RTC_T::TAR: 1MIN Position */
+#define RTC_TAR_1MIN_Msk (0xful << RTC_TAR_1MIN_Pos) /*!< RTC_T::TAR: 1MIN Mask */
+
+#define RTC_TAR_10MIN_Pos (12) /*!< RTC_T::TAR: 10MIN Position */
+#define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos) /*!< RTC_T::TAR: 10MIN Mask */
+
+#define RTC_TAR_1HR_Pos (16) /*!< RTC_T::TAR: 1HR Position */
+#define RTC_TAR_1HR_Msk (0xful << RTC_TAR_1HR_Pos) /*!< RTC_T::TAR: 1HR Mask */
+
+#define RTC_TAR_10HR_Pos (20) /*!< RTC_T::TAR: 10HR Position */
+#define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos) /*!< RTC_T::TAR: 10HR Mask */
+
+#define RTC_CAR_1DAY_Pos (0) /*!< RTC_T::CAR: 1DAY Position */
+#define RTC_CAR_1DAY_Msk (0xful << RTC_CAR_1DAY_Pos) /*!< RTC_T::CAR: 1DAY Mask */
+
+#define RTC_CAR_10DAY_Pos (4) /*!< RTC_T::CAR: 10DAY Position */
+#define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos) /*!< RTC_T::CAR: 10DAY Mask */
+
+#define RTC_CAR_1MON_Pos (8) /*!< RTC_T::CAR: 1MON Position */
+#define RTC_CAR_1MON_Msk (0xful << RTC_CAR_1MON_Pos) /*!< RTC_T::CAR: 1MON Mask */
+
+#define RTC_CAR_10MON_Pos (12) /*!< RTC_T::CAR: 10MON Position */
+#define RTC_CAR_10MON_Msk (0x1ul << RTC_CAR_10MON_Pos) /*!< RTC_T::CAR: 10MON Mask */
+
+#define RTC_CAR_1YEAR_Pos (16) /*!< RTC_T::CAR: 1YEAR Position */
+#define RTC_CAR_1YEAR_Msk (0xful << RTC_CAR_1YEAR_Pos) /*!< RTC_T::CAR: 1YEAR Mask */
+
+#define RTC_CAR_10YEAR_Pos (20) /*!< RTC_T::CAR: 10YEAR Position */
+#define RTC_CAR_10YEAR_Msk (0xful << RTC_CAR_10YEAR_Pos) /*!< RTC_T::CAR: 10YEAR Mask */
+
+#define RTC_LIR_LIR_Pos (0) /*!< RTC_T::LIR: LIR Position */
+#define RTC_LIR_LIR_Msk (0x1ul << RTC_LIR_LIR_Pos) /*!< RTC_T::LIR: LIR Mask */
+
+#define RTC_RIER_AIER_Pos (0) /*!< RTC_T::RIER: AIER Position */
+#define RTC_RIER_AIER_Msk (0x1ul << RTC_RIER_AIER_Pos) /*!< RTC_T::RIER: AIER Mask */
+
+#define RTC_RIER_TIER_Pos (1) /*!< RTC_T::RIER: TIER Position */
+#define RTC_RIER_TIER_Msk (0x1ul << RTC_RIER_TIER_Pos) /*!< RTC_T::RIER: TIER Mask */
+
+#define RTC_RIER_SNOOPIER_Pos (2) /*!< RTC_T::RIER: SNOOPIER Position */
+#define RTC_RIER_SNOOPIER_Msk (0x1ul << RTC_RIER_SNOOPIER_Pos) /*!< RTC_T::RIER: SNOOPIER Mask */
+
+#define RTC_RIIR_AIF_Pos (0) /*!< RTC_T::RIIR: AIF Position */
+#define RTC_RIIR_AIF_Msk (0x1ul << RTC_RIIR_AIF_Pos) /*!< RTC_T::RIIR: AIF Mask */
+
+#define RTC_RIIR_TIF_Pos (1) /*!< RTC_T::RIIR: TIF Position */
+#define RTC_RIIR_TIF_Msk (0x1ul << RTC_RIIR_TIF_Pos) /*!< RTC_T::RIIR: TIF Mask */
+
+#define RTC_RIIR_SNOOPIF_Pos (2) /*!< RTC_T::RIIR: SNOOPIF Position */
+#define RTC_RIIR_SNOOPIF_Msk (0x1ul << RTC_RIIR_SNOOPIF_Pos) /*!< RTC_T::RIIR: SNOOPIF Mask */
+
+#define RTC_TTR_TTR_Pos (0) /*!< RTC_T::TTR: TTR Position */
+#define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos) /*!< RTC_T::TTR: TTR Mask */
+
+#define RTC_TTR_TWKE_Pos (3) /*!< RTC_T::TTR: TWKE Position */
+#define RTC_TTR_TWKE_Msk (0x1ul << RTC_TTR_TWKE_Pos) /*!< RTC_T::TTR: TWKE Mask */
+
+#define RTC_SPRCTL_SNOOPEN_Pos (0) /*!< RTC_T::SPRCTL: SNOOPEN Position */
+#define RTC_SPRCTL_SNOOPEN_Msk (0x1ul << RTC_SPRCTL_SNOOPEN_Pos) /*!< RTC_T::SPRCTL: SNOOPEN Mask */
+
+#define RTC_SPRCTL_SNOOPEDGE_Pos (1) /*!< RTC_T::SPRCTL: SNOOPEDGE Position */
+#define RTC_SPRCTL_SNOOPEDGE_Msk (0x1ul << RTC_SPRCTL_SNOOPEDGE_Pos) /*!< RTC_T::SPRCTL: SNOOPEDGE Mask */
+
+#define RTC_SPRCTL_SPRRDY_Pos (7) /*!< RTC_T::SPRCTL: SPRRDY Position */
+#define RTC_SPRCTL_SPRRDY_Msk (0x1ul << RTC_SPRCTL_SPRRDY_Pos) /*!< RTC_T::SPRCTL: SPRRDY Mask */
+
+#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */
+#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */
+
+#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */
+#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */
+
+#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */
+#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */
+
+#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */
+#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */
+
+#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */
+#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */
+
+#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */
+#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */
+
+#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */
+#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */
+
+#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */
+#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */
+
+#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */
+#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */
+
+#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */
+#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */
+
+#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */
+#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */
+
+#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */
+#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */
+
+#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */
+#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */
+
+#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */
+#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */
+
+#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */
+#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */
+
+#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */
+#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */
+
+#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */
+#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */
+
+#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */
+#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */
+
+#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */
+#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */
+
+#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */
+#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */
+
+/**@}*/ /* RTC_CONST */
+/**@}*/ /* end of RTC register group */
+
+
+/*---------------------- Smart Card Host Interface Controller -------------------------*/
+/**
+ @addtogroup SC Smart Card Host Interface Controller(SC)
+ Memory Mapped Structure for SC Controller
+@{ */
+
+typedef struct {
+
+
+ union {
+ /**
+ * RBR
+ * ===================================================================================================
+ * Offset: 0x00 SC Receive Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |RBR |Receiving Buffer
+ * | | |By reading this register, the SC Controller will return an 8-bit data received from RX pin (LSB first).
+ */
+ __I uint32_t RBR;
+ /**
+ * THR
+ * ===================================================================================================
+ * Offset: 0x00 SC Transmit Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |THR |Transmit Buffer
+ * | | |By writing to this register, the SC sends out an 8-bit data through the TX pin (LSB first).
+ */
+ __O uint32_t THR;
+ };
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x04 SC Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SC_CEN |SC Engine Enable
+ * | | |Set this bit to "1" to enable SC operation.
+ * | | |If this bit is cleared, SC will force all transition to IDLE state.
+ * |[1] |DIS_RX |RX Transition Disable
+ * | | |0 = Receiver Enabled.
+ * | | |1 = Receiver Disabled.
+ * |[2] |DIS_TX |TX Transition Disable
+ * | | |0 = Transceiver Enabled.
+ * | | |1 = Transceiver Disabled.
+ * |[3] |AUTO_CON_EN|Auto Convention Enable
+ * | | |0 = Auto-convention Disabled.
+ * | | |1 = Auto-convention Enabled.
+ * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL will be set to 00 automatically, otherwise if the TS is inverse convention, CON_SEL will be set to 11.
+ * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
+ * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the SC_CTL[CON_SEL] register automatically.
+ * | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR(if SC_IER [ACON_ERR_IE = "1"] to CPU.
+ * |[5:4] |CON_SEL |Convention Selection
+ * | | |00 = Direct convention.
+ * | | |01 = Reserved.
+ * | | |10 = Reserved.
+ * | | |11 = Inverse convention.
+ * | | |Note: If AUTO_CON_EN is enabled, this field must be ignored.
+ * |[7:6] |RX_FTRI_LEV|RX Buffer Trigger Level
+ * | | |When the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated).
+ * | | |00 = INTR_RDA Trigger Level 1 byte.
+ * | | |01 = INTR_RDA Trigger Level 2 bytes.
+ * | | |10 = INTR_RDA Trigger Level 3 bytes.
+ * | | |11 = Reserved.
+ * |[12:8] |BGT |Block Guard Time (BGT)
+ * | | |This field indicates the counter for block guard time.
+ * | | |According to ISO7816-3, in T=0 mode, software must fill 15 (real block guard time = 16) to this field and in T=1 mode software must fill 21 (real block guard time = 22) to it.
+ * | | |In TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data.
+ * | | |In RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing.
+ * | | |If the incoming data timing less than BGT, an interrupt will be generated.
+ * | | |Note: The real block guard time is BGT + 1.
+ * |[14:13] |TMR_SEL |Timer Selection
+ * | | |00 = Disable all internal timer function.
+ * | | |01 = Enable internal 24 bit timer.
+ * | | |Software can configure it by setting SC_TMR0 [23:0].
+ * | | |SC_TMR1 and SC_TMR2 will be ignored in this mode.
+ * | | |10 = Enable internal 24 bit timer and 8 bit internal timer.
+ * | | |Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1 [7:0].
+ * | | |SC_TMR2 will be ignored in this mode.
+ * | | |11 = Enable internal 24 bit timer and two 8 bit timers.
+ * | | |Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0].
+ * |[15] |SLEN |Stop Bit Length
+ * | | |This field indicates the length of stop bit.
+ * | | |0 = The stop bit length is 2 ETU.
+ * | | |1 = The stop bit length is 1 ETU.
+ * | | |Note: The default stop bit length is 2.
+ * |[18:16] |RX_ERETRY |RX Error Retry Register
+ * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred.
+ * | | |Note1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number.
+ * | | |Note2: This field can not be changed when RX_ERETRY_EN enabled.
+ * | | |The change flow is to disable RX_ETRTRY_EN first and then fill new retry value.
+ * |[19] |RX_ERETRY_EN|RX Error Retry Enable Register
+ * | | |This bit enables receiver retry function when parity error has occurred.
+ * | | |0 = RX error retry function Disabled.
+ * | | |1 = RX error retry function Enabled.
+ * | | |Note: User must fill RX_ERETRY value before enabling this bit.
+ * |[22:20] |TX_ERETRY |TX Error Retry Register
+ * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
+ * | | |Note1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.
+ * | | |Note2: This field can not be changed when TX_ERETRY_EN enabled.
+ * | | |The change flow is to disable TX_ETRTRY_EN first and then fill new retry value.
+ * |[23] |TX_ERETRY_EN|TX Error Retry Enable Register
+ * | | |This bit enables transmitter retry function when parity error has occurred.
+ * | | |0 = TX error retry function Disabled.
+ * | | |1 = TX error retry function Enabled.
+ * | | |Note: User must fill TX_ERETRY value before enabling this bit.
+ * |[25:24] |CD_DEB_SEL|Card Detect De-Bounce Select Register
+ * | | |This field indicates the card detect de-bounce selection.
+ * | | |This field indicates the card detect de-bounce selection.
+ * | | |00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks.
+ * | | |01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks.
+ * | | |10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks.
+ * | | |11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks.
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * ALTCTL
+ * ===================================================================================================
+ * Offset: 0x08 SC Alternate Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TX_RST |TX Software Reset
+ * | | |When TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the TX internal state machine and pointers.
+ * | | |Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
+ * |[1] |RX_RST |RX Software Reset
+ * | | |When RX_RST is set, all the bytes in the receiver buffer and RX internal state machine will be cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the RX internal state machine and pointers.
+ * | | |Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
+ * |[2] |DACT_EN |Deactivation Sequence Generator Enable
+ * | | |This bit enables SC controller to initiate the card by deactivation sequence
+ * | | |0 = No effect.
+ * | | |1 = Deactivation sequence generator Enabled.
+ * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1".
+ * | | |Note2: This field will be cleared by TX_RST and RX_RST.
+ * | | |So don't fill this bit, TX_RST, and RX_RST at the same time.
+ * | | |Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
+ * |[3] |ACT_EN |Activation Sequence Generator Enable
+ * | | |This bit enables SC controller to initiate the card by activation sequence
+ * | | |0 = No effect.
+ * | | |1 = Activation sequence generator Enabled.
+ * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_IS [INIT_IS] will be set to "1".
+ * | | |Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
+ * | | |Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
+ * |[4] |WARST_EN |Warm Reset Sequence Generator Enable
+ * | | |This bit enables SC controller to initiate the card by warm reset sequence
+ * | | |0 = No effect.
+ * | | |1 = Warm reset sequence generator Enabled.
+ * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1".
+ * | | |Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
+ * | | |Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
+ * |[5] |TMR0_SEN |Internal Timer0 Start Enable
+ * | | |This bit enables Timer0 to start counting.
+ * | | |Software can fill "0" to stop it and set "1" to reload and count.
+ * | | |0 = Stops counting.
+ * | | |1 = Starts counting.
+ * | | |Note1: This field is used for internal 24 bit timer when SC_CTL [TMR_SEL] = 01.
+ * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMR0 [26] = "0"), this bit will be auto-cleared by hardware.
+ * | | |Note3: This field will be cleared by TX_RST and RX_RST.
+ * | | |So don't fill this bit, TX_RST and RX_RST at the same time.
+ * | | |Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
+ * |[6] |TMR1_SEN |Internal Timer1 Start Enable
+ * | | |This bit enables Timer "1" to start counting.
+ * | | |Software can fill 0 to stop it and set "1" to reload and count.
+ * | | |0 = Stops counting.
+ * | | |1 = Starts counting.
+ * | | |Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] = 01 or 10.
+ * | | |Don't filled TMR1_SEN when SC_CTL [TMR_SEL] = 00 or 11.
+ * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMR1 [26] = "0"), this bit will be auto-cleared by hardware.
+ * | | |Note3: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
+ * | | |Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
+ * |[7] |TMR2_SEN |Internal Timer2 Start Enable
+ * | | |This bit enables Timer2 to start counting.
+ * | | |Software can fill "0" to stop it and set "1" to reload and count.
+ * | | |0 = Stops counting.
+ * | | |1 = Starts counting.
+ * | | |Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] == 11.
+ * | | |Don't filled TMR2_SEN when SC_CTL [TMR_SEL] == 00 or 01 or 10.
+ * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMR2 [26] = "0"), this bit will be auto-cleared by hardware.
+ * | | |Note3: This field will be cleared by TX_RST and RX_RST.
+ * | | |So don't fill this bit, TX_RST, and RX_RST at the same time.
+ * | | |Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
+ * |[9:8] |INIT_SEL |Initial Timing Selection
+ * | | |This field indicates the timing of hardware initial state (activation or warm-reset or deactivation).
+ * |[12] |RX_BGT_EN |Receiver Block Guard Time Function Enable
+ * | | |0 = Receiver block guard time function Disabled.
+ * | | |1 = Receiver block guard time function Enabled.
+ * |[13] |TMR0_ATV |Internal Timer0 Active State (Read Only)
+ * | | |This bit indicates the timer counter status of timer0.
+ * | | |0 = Timer0 is not active.
+ * | | |1 = Timer0 is active.
+ * |[14] |TMR1_ATV |Internal Timer1 Active State (Read Only)
+ * | | |This bit indicates the timer counter status of timer1.
+ * | | |0 = Timer1 is not active.
+ * | | |1 = Timer1 is active.
+ * |[15] |TMR2_ATV |Internal Timer2 Active State (Read Only)
+ * | | |This bit indicates the timer counter status of timer2.
+ * | | |0 = Timer2 is not active.
+ * | | |1 = Timer2 is active.
+ */
+ __IO uint32_t ALTCTL;
+
+ /**
+ * EGTR
+ * ===================================================================================================
+ * Offset: 0x0C SC Extend Guard Time Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |EGT |Extended Guard Time
+ * | | |This field indicates the extended guard timer value.
+ * | | |Note: The counter is ETU based and the real extended guard time is EGT.
+ */
+ __IO uint32_t EGTR;
+
+ /**
+ * RFTMR
+ * ===================================================================================================
+ * Offset: 0x10 SC Receive Buffer Time-Out Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |RFTM |SC Receiver Buffer Time-Out Register (ETU Based)
+ * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
+ * | | |Once the counter decrease to "1" and no new data is received or CPU does not read data by reading SC_RBR register, a receiver time-out interrupt INT_RTMR will be generated(if SC_IER[RTMR_IE] is high).
+ * | | |Note1: The counter is ETU based and the real count value is RFTM + 1
+ * | | |Note2: Fill all "0" to this field to disable this function.
+ */
+ __IO uint32_t RFTMR;
+
+ /**
+ * ETUCR
+ * ===================================================================================================
+ * Offset: 0x14 SC ETU Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |ETU_RDIV |ETU Rate Divider
+ * | | |The field indicates the clock rate divider.
+ * | | |The real ETU is ETU_RDIV + 1.
+ * | | |Note1: Software can configure this field, but this field must be greater than 0x04.
+ * | | |Note2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040.
+ * |[15] |COMPEN_EN |Compensation Mode Enable
+ * | | |This bit enables clock compensation function.
+ * | | |When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register.
+ * | | |0 = Compensation function Disabled.
+ * | | |1 = Compensation function Enabled.
+ */
+ __IO uint32_t ETUCR;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x18 SC Interrupt Enable Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDA_IE |Receive Data Reach Interrupt Enable
+ * | | |This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.
+ * | | |0 = INT_RDR Disabled.
+ * | | |1 = INT_RDR Enabled.
+ * |[1] |TBE_IE |Transmit Buffer Empty Interrupt Enable
+ * | | |This field is used for transmit buffer empty interrupt enable.
+ * | | |0 = INT_THRE Disabled.
+ * | | |1 = INT_THRE Enabled.
+ * |[2] |TERR_IE |Transfer Error Interrupt Enable
+ * | | |This field is used for transfer error interrupt enable.
+ * | | |The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY).
+ * | | |0 = INT_TERR Disabled.
+ * | | |1 = INT_TERR Enabled.
+ * |[3] |TMR0_IE |Timer0 Interrupt Enable
+ * | | |This field is used for TMR0 interrupt enable.
+ * | | |0 = INT_TMR0 Disabled.
+ * | | |1 = INT_TMR0 Enabled.
+ * |[4] |TMR1_IE |Timer1 Interrupt Enable
+ * | | |This field is used for TMR1 interrupt enable.
+ * | | |0 = INT_TMR1 Disabled.
+ * | | |1 = INT_TMR1 Enabled.
+ * |[5] |TMR2_IE |Timer2 Interrupt Enable
+ * | | |This field is used for TMR2 interrupt enable.
+ * | | |0 = INT_TMR2 Disabled.
+ * | | |1 = INT_TMR2 Enabled.
+ * |[6] |BGT_IE |Block Guard Time Interrupt Enable
+ * | | |This field is used for block guard time interrupt enable.
+ * | | |0 = INT_BGT Disabled.
+ * | | |1 = INT_BGT Enabled.
+ * |[7] |CD_IE |Card Detect Interrupt Enable
+ * | | |This field is used for card detect interrupt enable.
+ * | | |The card detect status register is SC_PINCSR [CD_CH] and SC_PINCSR[CD_CL].
+ * | | |0 = INT_CD Disabled.
+ * | | |1 = INT_CD Enabled.
+ * |[8] |INIT_IE |Initial End Interrupt Enable
+ * | | |This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.
+ * | | |0 = INT_INIT Disabled.
+ * | | |1 = INT_INIT Enabled.
+ * |[9] |RTMR_IE |Receiver Buffer Time-Out Interrupt Enable
+ * | | |This field is used for receiver buffer time-out interrupt enable.
+ * | | |0 = INT_RTMR Disabled.
+ * | | |1 = INT_RTMR Enabled.
+ * |[10] |ACON_ERR_IE|Auto Convention Error Interrupt Enable
+ * | | |This field is used for auto convention error interrupt enable.
+ * | | |0 = INT_ACON_ERR Disabled.
+ * | | |1 = INT_ACON_ERR Enabled.
+ */
+ __IO uint32_t IER;
+
+ /**
+ * ISR
+ * ===================================================================================================
+ * Offset: 0x1C SC Interrupt Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDA_IS |Receive Data Reach Interrupt Status Flag (Read Only)
+ * | | |This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt status flag.
+ * | | |Note: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV].
+ * | | |If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically.
+ * |[1] |TBE_IS |Transmit Buffer Empty Interrupt Status Flag (Read Only)
+ * | | |This field is used for transmit buffer empty interrupt status flag.
+ * | | |This bit is different with SC_TRSR [TX_EMPTY_F] flag and SC_TRSR [TX_ATV] flag; The TX_EMPTY_F will be set when the last byte data be read to shift register and TX_ATV flag indicates the transmitter is in active or not (the last data has been transmitted or not), but the TBE_IS may be set when the last byte data be read to shift register or the last data has been transmitted.
+ * | | |When this bit assert, software can write 1~4 byte data to SC_THR register.
+ * | | |Note: If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically.
+ * |[2] |TERR_IS |Transfer Error Interrupt Status Flag (Read Only)
+ * | | |This field is used for transfer error interrupt status flag.
+ * | | |The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY).
+ * | | |Note: This field is the status flag of SC_TRSR [RX_EBR_F], SC_TRSR [RX_EFR_F], SC_TRSR [RX_EPA_F], SC_TRSR [RX_OVER_F], SC_TRSR [TX_OVER_F], SC_TRSR [RX_OVER_ERETRY] or SC_TRSR [TX_OVER_ERETRY].
+ * | | |So if software wants to clear this bit, software must write "1" to each field.
+ * |[3] |TMR0_IS |Timer0 Interrupt Status Flag (Read Only)
+ * | | |This field is used for TMR0 interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[4] |TMR1_IS |Timer1 Interrupt Status Flag (Read Only)
+ * | | |This field is used for TMR1 interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[5] |TMR2_IS |Timer2 Interrupt Status Flag (Read Only)
+ * | | |This field is used for TMR2 interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[6] |BGT_IS |Block Guard Time Interrupt Status Flag (Read Only)
+ * | | |This field is used for block guard time interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[7] |CD_IS |Card Detect Interrupt Status Flag (Read Only)
+ * | | |This field is used for card detect interrupt status flag.
+ * | | |The card detect status register is SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F].
+ * | | |Note: This field is the status flag of SC_PINCSR [CD_INS_F] or SC_PINCSR [CD_REM_F].
+ * | | |So if software wants to clear this bit, software must write "1" to this field.
+ * |[8] |INIT_IS |Initial End Interrupt Status Flag (Read Only)
+ * | | |This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[9] |RTMR_IS |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
+ * | | |This field is used for receiver buffer time-out interrupt status flag.
+ * | | |Note: This field is the status flag of receiver buffer time-out state.
+ * | | |If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,.
+ * |[10] |ACON_ERR_IS|Auto Convention Error Interrupt Status Flag (Read Only)
+ * | | |This field indicates auto convention sequence error.
+ * | | |If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ */
+ __IO uint32_t ISR;
+
+ /**
+ * TRSR
+ * ===================================================================================================
+ * Offset: 0x20 SC Transfer Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_OVER_F |RX Overflow Error Status Flag (Read Only)
+ * | | |This bit is set when RX buffer overflow.
+ * | | |If the number of received bytes is greater than RX Buffer (SC_RBR) size, 4 bytes of SC, this bit will be set.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: The overwrite data will be ignored.
+ * |[1] |RX_EMPTY_F|Receiver Buffer Empty Status Flag(Read Only)
+ * | | |This bit indicates RX buffer empty or not.
+ * | | |When the last byte of RX buffer has been read by CPU, hardware sets this bit high.
+ * | | |It will be cleared when SC receives any new data.
+ * |[2] |RX_FULL_F |Receiver Buffer Full Status Flag (Read Only)
+ * | | |This bit indicates RX buffer full or not.
+ * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+ * |[4] |RX_EPA_F |Receiver Parity Error Status Flag (Read Only)
+ * | | |This bit is set to logic "1" whenever the received character does not have a valid "parity bit".
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
+ * |[5] |RX_EFR_F |Receiver Frame Error Status Flag (Read Only)
+ * | | |This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0").
+ * | | |Note1: This bit is read only, but can be cleared by writing "1" to it.
+ * | | |Note2: If CPI sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
+ * |[6] |RX_EBR_F |Receiver Break Error Status Flag (Read Only)
+ * | | |This bit is set to a logic "1" whenever the received data input (RX) held in the "spacing state" (logic "0") is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
+ * |[8] |TX_OVER_F |TX Overflow Error Interrupt Status Flag (Read Only)
+ * | | |If TX buffer is full (TX_FULL_F = "1"), an additional write data to SC_THR will cause this bit to logic "1".
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: The additional write data will be ignored.
+ * |[9] |TX_EMPTY_F|Transmit Buffer Empty Status Flag (Read Only)
+ * | | |This bit indicates TX buffer empty or not.
+ * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
+ * | | |It will be cleared when writing data into SC_THR (TX buffer not empty).
+ * |[10] |TX_FULL_F |Transmit Buffer Full Status Flag (Read Only)
+ * | | |This bit indicates TX buffer full or not.
+ * | | |This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+ * |[18:16] |RX_POINT_F|Receiver Buffer Pointer Status Flag (Read Only)
+ * | | |This field indicates the RX buffer pointer status flag.
+ * | | |When SC receives one byte from external device, RX_POINT_F increases one.
+ * | | |When one byte of RX buffer is read by CPU, RX_POINT_F decreases one.
+ * |[21] |RX_REERR |Receiver Retry Error (Read Only)
+ * | | |This bit is set by hardware when RX has any error and retries transfer.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2 This bit is a flag and can not generate any interrupt to CPU.
+ * | | |Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
+ * |[22] |RX_OVER_ERETRY|Receiver Over Retry Error (Read Only)
+ * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
+ * |[23] |RX_ATV |Receiver In Active Status Flag (Read Only)
+ * | | |This bit is set by hardware when RX transfer is in active.
+ * | | |This bit is cleared automatically when RX transfer is finished.
+ * |[26:24] |TX_POINT_F|Transmit Buffer Pointer Status Flag (Read Only)
+ * | | |This field indicates the TX buffer pointer status flag.
+ * | | |When CPU writes data into SC_THR, TX_POINT_F increases one.
+ * | | |When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
+ * |[29] |TX_REERR |Transmitter Retry Error (Read Only)
+ * | | |This bit is set by hardware when transmitter re-transmits.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2 This bit is a flag and can not generate any interrupt to CPU.
+ * |[30] |TX_OVER_ERETRY|Transmitter Over Retry Error (Read Only)
+ * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[31] |TX_ATV |Transmit In Active Status Flag (Read Only)
+ * | | |This bit is set by hardware when TX transfer is in active or the last byte transmission has not completed.
+ * | | |This bit is cleared automatically when TX transfer is finished and the STOP bit (include guard time) has been transmitted.
+ */
+ __IO uint32_t TRSR;
+
+ /**
+ * PINCSR
+ * ===================================================================================================
+ * Offset: 0x24 SC Pin Control State Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |POW_EN |SC_POW_EN Pin Signal
+ * | | |This bit is the pin status of SC_POW_EN but user can drive SC_POW_EN pin to high or low by setting this bit.
+ * | | |0 = Drive SC_POW_EN pin to low.
+ * | | |1 = Drive SC_POW_EN pin to high.
+ * | | |Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field When operating in these modes.
+ * |[1] |SC_RST |SC_RST Pin Signal
+ * | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
+ * | | |0 = Drive SC_RST pin to low.
+ * | | |1 = Drive SC_RST pin to high.
+ * | | |Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field When operating in these modes.
+ * |[2] |CD_REM_F |Card Detect Removal Status Of SC_CD Pin (Read Only)
+ * | | |This bit is set whenever card has been removal.
+ * | | |0 = No effect.
+ * | | |1 = Card Removal.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
+ * |[3] |CD_INS_F |Card Detect Insert Status Of SC_CD Pin (Read Only)
+ * | | |This bit is set whenever card has been inserted.
+ * | | |0 = No effect.
+ * | | |1 = Card insert.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
+ * |[4] |CD_PIN_ST |Card Detect Status Of SC_CD Pin Status (Read Only)
+ * | | |This bit is the pin status flag of SC_CD
+ * | | |0 = SC_CD pin state at low.
+ * | | |1 = SC_CD pin state at high.
+ * |[6] |CLK_KEEP |SC Clock Enable
+ * | | |0 = SC clock generation Disabled.
+ * | | |1 = SC clock always keeps free running.
+ * | | |Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field when operation in these modes.
+ * |[7] |ADAC_CD_EN|Auto Deactivation When Card Removal
+ * | | |0 = Auto deactivation Disabled when hardware detected the card is removal.
+ * | | |1 = Auto deactivation Enabled when hardware detected the card is removal.
+ * | | |Note1: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting).
+ * | | |If this process completes.
+ * | | |Hardware will generate an interrupt INT_INIT to CPU.
+ * |[8] |SC_OEN_ST |SC Data Pin Output Enable Status (Read Only)
+ * | | |0 = SC data output enable pin status is at low.
+ * | | |1 = SC data output enable pin status is at high.
+ * |[9] |SC_DATA_O |Output Of SC Data Pin
+ * | | |This bit is the pin status of SC data output but user can drive this pin to high or low by setting this bit.
+ * | | |0 = Drive SC data output pin to low.
+ * | | |1 = Drive SC data output pin to high.
+ * | | |Note: When SC is at activation, warm re set or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field when SC is in these modes.
+ * |[10] |CD_LEV |Card Detect Level
+ * | | |0 = When hardware detects the card detect pin from high to low, it indicates a card is detected.
+ * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
+ * | | |Note: Software must select card detect level before Smart Card engine enable
+ * |[11] |POW_INV |SC_POW Pin Inverse
+ * | | |This bit is used for inverse the SC_POW pin.
+ * | | |There are four kinds of combination for SC_POW pin setting by POW_INV and
+ * | | |POW_EN(SC_PINCSR[0]). POW_INV is bit 1 and POW_EN is bit 0 for SC_POW_Pin as
+ * | | |high or low voltage selection.
+ * | | |POW_INV is 0 and POW_EN is 0, than SC_POW Pin output 0.
+ * | | |POW_INV is 0 and POW_EN is 1, than SC_POW Pin output 1.
+ * | | |POW_INV is 1 and POW_EN is 0, than SC_POW Pin output 1.
+ * | | |POW_INV is 1 and POW_EN is 1, than SC_POW Pin output 0.
+ * | | |Note: Software must select POW_INV before Smart Card is enabled by SC_CEN (SC_CTL[0])
+ * |[16] |SC_DATA_I_ST|SC Data Input Pin Status (Read Only)
+ * | | |This bit is the pin status of SC_DATA_I
+ * | | |0 = The SC_DATA_I pin is low.
+ * | | |1 = The SC_DATA_I pin is high.
+ */
+ __IO uint32_t PINCSR;
+
+ /**
+ * TMR0
+ * ===================================================================================================
+ * Offset: 0x28 SC Internal Timer Control Register 0.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNT |Timer 0 Counter Value Register (ETU Base)
+ * | | |This field indicates the internal timer operation values.
+ * |[27:24] |MODE |Timer 0 Operation Mode Selection
+ * | | |This field indicates the internal 24 bit timer operation selection.
+ */
+ __IO uint32_t TMR0;
+
+ /**
+ * TMR1
+ * ===================================================================================================
+ * Offset: 0x2C SC Internal Timer Control Register 1.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNT |Timer 1 Counter Value Register (ETU Base)
+ * | | |This field indicates the internal timer operation values.
+ * |[27:24] |MODE |Timer 1 Operation Mode Selection
+ * | | |This field indicates the internal 8 bit timer operation selection.
+ */
+ __IO uint32_t TMR1;
+
+ /**
+ * TMR2
+ * ===================================================================================================
+ * Offset: 0x30 SC Internal Timer Control Register 2.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNT |Timer 2 Counter Value Register (ETU Base)
+ * | | |This field indicates the internal timer operation values.
+ * |[27:24] |MODE |Timer 2 Operation Mode Selection
+ * | | |This field indicates the internal 8 bit timer operation selection.
+ */
+ __IO uint32_t TMR2;
+
+ /**
+ * UACTL
+ * ===================================================================================================
+ * Offset: 0x34 SC UART Mode Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |UA_MODE_EN|UART Mode Enable
+ * | | |0 = Smart Card mode.
+ * | | |1 = UART mode.
+ * | | |Note1: When operating in UART mode, user must set SCx_CTL [CON_SEL] and SCx_CTL [AUTO_CON_EN] to "0".
+ * | | |Note2: When operating in smart card mode, user must set SCx_UACTL [7:0] register to "0".
+ * | | |Note3: When UART is enabled, hardware will generate a reset to reset internal buffer and internal state machine.
+ * |[5:4] |DATA_LEN |Data Length
+ * | | |00 = 8 bits
+ * | | |01 = 7 bits
+ * | | |10 = 6 bits
+ * | | |11 = 5 bits
+ * | | |Note: In Smart Card mode, this field must be '00'
+ * |[6] |PBDIS |Parity Bit Disable
+ * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
+ * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
+ * | | |Note: In Smart Card mode, this field must be '0' (default setting is with parity bit)
+ * |[7] |OPE |Odd Parity Enable
+ * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |Note: This bit has effect only when PBDIS bit is '0'.
+ */
+ __IO uint32_t UACTL;
+
+ /**
+ * TDRA
+ * ===================================================================================================
+ * Offset: 0x38 SC Timer Current Data Register A.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |TDR0 |Timer0 Current Data Register (Read Only)
+ * | | |This field indicates the current count values of timer0.
+ */
+ __I uint32_t TDRA;
+
+ /**
+ * TDRB
+ * ===================================================================================================
+ * Offset: 0x3C SC Timer Current Data Register B.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TDR1 |Timer1 Current Data Register (Read Only)
+ * | | |This field indicates the current count values of timer1.
+ * |[15:8] |TDR2 |Timer2 Current Data Register (Read Only)
+ * | | |This field indicates the current count values of timer2.
+ */
+ __I uint32_t TDRB;
+
+} SC_T;
+
+/**
+ @addtogroup SC_CONST SC Bit Field Definition
+ Constant Definitions for SC Controller
+@{ */
+
+#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
+#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
+
+#define SC_CTL_SC_CEN_Pos (0) /*!< SC_T::CTL: SC_CEN Position */
+#define SC_CTL_SC_CEN_Msk (0x1ul << SC_CTL_SC_CEN_Pos) /*!< SC_T::CTL: SC_CEN Mask */
+
+#define SC_CTL_DIS_RX_Pos (1) /*!< SC_T::CTL: DIS_RX Position */
+#define SC_CTL_DIS_RX_Msk (0x1ul << SC_CTL_DIS_RX_Pos) /*!< SC_T::CTL: DIS_RX Mask */
+
+#define SC_CTL_DIS_TX_Pos (2) /*!< SC_T::CTL: DIS_TX Position */
+#define SC_CTL_DIS_TX_Msk (0x1ul << SC_CTL_DIS_TX_Pos) /*!< SC_T::CTL: DIS_TX Mask */
+
+#define SC_CTL_AUTO_CON_EN_Pos (3) /*!< SC_T::CTL: AUTO_CON_EN Position */
+#define SC_CTL_AUTO_CON_EN_Msk (0x1ul << SC_CTL_AUTO_CON_EN_Pos) /*!< SC_T::CTL: AUTO_CON_EN Mask */
+
+#define SC_CTL_CON_SEL_Pos (4) /*!< SC_T::CTL: CON_SEL Position */
+#define SC_CTL_CON_SEL_Msk (0x3ul << SC_CTL_CON_SEL_Pos) /*!< SC_T::CTL: CON_SEL Mask */
+
+#define SC_CTL_RX_FTRI_LEV_Pos (6) /*!< SC_T::CTL: RX_FTRI_LEV Position */
+#define SC_CTL_RX_FTRI_LEV_Msk (0x3ul << SC_CTL_RX_FTRI_LEV_Pos) /*!< SC_T::CTL: RX_FTRI_LEV Mask */
+
+#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
+#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
+
+#define SC_CTL_TMR_SEL_Pos (13) /*!< SC_T::CTL: TMR_SEL Position */
+#define SC_CTL_TMR_SEL_Msk (0x3ul << SC_CTL_TMR_SEL_Pos) /*!< SC_T::CTL: TMR_SEL Mask */
+
+#define SC_CTL_SLEN_Pos (15) /*!< SC_T::CTL: SLEN Position */
+#define SC_CTL_SLEN_Msk (0x1ul << SC_CTL_SLEN_Pos) /*!< SC_T::CTL: SLEN Mask */
+
+#define SC_CTL_RX_ERETRY_Pos (16) /*!< SC_T::CTL: RX_ERETRY Position */
+#define SC_CTL_RX_ERETRY_Msk (0x7ul << SC_CTL_RX_ERETRY_Pos) /*!< SC_T::CTL: RX_ERETRY Mask */
+
+#define SC_CTL_RX_ERETRY_EN_Pos (19) /*!< SC_T::CTL: RX_ERETRY_EN Position */
+#define SC_CTL_RX_ERETRY_EN_Msk (0x1ul << SC_CTL_RX_ERETRY_EN_Pos) /*!< SC_T::CTL: RX_ERETRY_EN Mask */
+
+#define SC_CTL_TX_ERETRY_Pos (20) /*!< SC_T::CTL: TX_ERETRY Position */
+#define SC_CTL_TX_ERETRY_Msk (0x7ul << SC_CTL_TX_ERETRY_Pos) /*!< SC_T::CTL: TX_ERETRY Mask */
+
+#define SC_CTL_TX_ERETRY_EN_Pos (23) /*!< SC_T::CTL: TX_ERETRY_EN Position */
+#define SC_CTL_TX_ERETRY_EN_Msk (0x1ul << SC_CTL_TX_ERETRY_EN_Pos) /*!< SC_T::CTL: TX_ERETRY_EN Mask */
+
+#define SC_CTL_CD_DEB_SEL_Pos (24) /*!< SC_T::CTL: CD_DEB_SEL Position */
+#define SC_CTL_CD_DEB_SEL_Msk (0x3ul << SC_CTL_CD_DEB_SEL_Pos) /*!< SC_T::CTL: CD_DEB_SEL Mask */
+
+#define SC_ALTCTL_TX_RST_Pos (0) /*!< SC_T::ALTCTL: TX_RST Position */
+#define SC_ALTCTL_TX_RST_Msk (0x1ul << SC_ALTCTL_TX_RST_Pos) /*!< SC_T::ALTCTL: TX_RST Mask */
+
+#define SC_ALTCTL_RX_RST_Pos (1) /*!< SC_T::ALTCTL: RX_RST Position */
+#define SC_ALTCTL_RX_RST_Msk (0x1ul << SC_ALTCTL_RX_RST_Pos) /*!< SC_T::ALTCTL: RX_RST Mask */
+
+#define SC_ALTCTL_DACT_EN_Pos (2) /*!< SC_T::ALTCTL: DACT_EN Position */
+#define SC_ALTCTL_DACT_EN_Msk (0x1ul << SC_ALTCTL_DACT_EN_Pos) /*!< SC_T::ALTCTL: DACT_EN Mask */
+
+#define SC_ALTCTL_ACT_EN_Pos (3) /*!< SC_T::ALTCTL: ACT_EN Position */
+#define SC_ALTCTL_ACT_EN_Msk (0x1ul << SC_ALTCTL_ACT_EN_Pos) /*!< SC_T::ALTCTL: ACT_EN Mask */
+
+#define SC_ALTCTL_WARST_EN_Pos (4) /*!< SC_T::ALTCTL: WARST_EN Position */
+#define SC_ALTCTL_WARST_EN_Msk (0x1ul << SC_ALTCTL_WARST_EN_Pos) /*!< SC_T::ALTCTL: WARST_EN Mask */
+
+#define SC_ALTCTL_TMR0_SEN_Pos (5) /*!< SC_T::ALTCTL: TMR0_SEN Position */
+#define SC_ALTCTL_TMR0_SEN_Msk (0x1ul << SC_ALTCTL_TMR0_SEN_Pos) /*!< SC_T::ALTCTL: TMR0_SEN Mask */
+
+#define SC_ALTCTL_TMR1_SEN_Pos (6) /*!< SC_T::ALTCTL: TMR1_SEN Position */
+#define SC_ALTCTL_TMR1_SEN_Msk (0x1ul << SC_ALTCTL_TMR1_SEN_Pos) /*!< SC_T::ALTCTL: TMR1_SEN Mask */
+
+#define SC_ALTCTL_TMR2_SEN_Pos (7) /*!< SC_T::ALTCTL: TMR2_SEN Position */
+#define SC_ALTCTL_TMR2_SEN_Msk (0x1ul << SC_ALTCTL_TMR2_SEN_Pos) /*!< SC_T::ALTCTL: TMR2_SEN Mask */
+
+#define SC_ALTCTL_INIT_SEL_Pos (8) /*!< SC_T::ALTCTL: INIT_SEL Position */
+#define SC_ALTCTL_INIT_SEL_Msk (0x3ul << SC_ALTCTL_INIT_SEL_Pos) /*!< SC_T::ALTCTL: INIT_SEL Mask */
+
+#define SC_ALTCTL_RX_BGT_EN_Pos (12) /*!< SC_T::ALTCTL: RX_BGT_EN Position */
+#define SC_ALTCTL_RX_BGT_EN_Msk (0x1ul << SC_ALTCTL_RX_BGT_EN_Pos) /*!< SC_T::ALTCTL: RX_BGT_EN Mask */
+
+#define SC_ALTCTL_TMR0_ATV_Pos (13) /*!< SC_T::ALTCTL: TMR0_ATV Position */
+#define SC_ALTCTL_TMR0_ATV_Msk (0x1ul << SC_ALTCTL_TMR0_ATV_Pos) /*!< SC_T::ALTCTL: TMR0_ATV Mask */
+
+#define SC_ALTCTL_TMR1_ATV_Pos (14) /*!< SC_T::ALTCTL: TMR1_ATV Position */
+#define SC_ALTCTL_TMR1_ATV_Msk (0x1ul << SC_ALTCTL_TMR1_ATV_Pos) /*!< SC_T::ALTCTL: TMR1_ATV Mask */
+
+#define SC_ALTCTL_TMR2_ATV_Pos (15) /*!< SC_T::ALTCTL: TMR2_ATV Position */
+#define SC_ALTCTL_TMR2_ATV_Msk (0x1ul << SC_ALTCTL_TMR2_ATV_Pos) /*!< SC_T::ALTCTL: TMR2_ATV Mask */
+
+#define SC_EGTR_EGT_Pos (0) /*!< SC_T::EGTR: EGT Position */
+#define SC_EGTR_EGT_Msk (0xfful << SC_EGTR_EGT_Pos) /*!< SC_T::EGTR: EGT Mask */
+
+#define SC_RFTMR_RFTM_Pos (0) /*!< SC_T::RFTMR: RFTM Position */
+#define SC_RFTMR_RFTM_Msk (0x1fful << SC_RFTMR_RFTM_Pos) /*!< SC_T::RFTMR: RFTM Mask */
+
+#define SC_ETUCR_ETU_RDIV_Pos (0) /*!< SC_T::ETUCR: ETU_RDIV Position */
+#define SC_ETUCR_ETU_RDIV_Msk (0xffful << SC_ETUCR_ETU_RDIV_Pos) /*!< SC_T::ETUCR: ETU_RDIV Mask */
+
+#define SC_ETUCR_COMPEN_EN_Pos (15) /*!< SC_T::ETUCR: COMPEN_EN Position */
+#define SC_ETUCR_COMPEN_EN_Msk (0x1ul << SC_ETUCR_COMPEN_EN_Pos) /*!< SC_T::ETUCR: COMPEN_EN Mask */
+
+#define SC_IER_RDA_IE_Pos (0) /*!< SC_T::IER: RDA_IE Position */
+#define SC_IER_RDA_IE_Msk (0x1ul << SC_IER_RDA_IE_Pos) /*!< SC_T::IER: RDA_IE Mask */
+
+#define SC_IER_TBE_IE_Pos (1) /*!< SC_T::IER: TBE_IE Position */
+#define SC_IER_TBE_IE_Msk (0x1ul << SC_IER_TBE_IE_Pos) /*!< SC_T::IER: TBE_IE Mask */
+
+#define SC_IER_TERR_IE_Pos (2) /*!< SC_T::IER: TERR_IE Position */
+#define SC_IER_TERR_IE_Msk (0x1ul << SC_IER_TERR_IE_Pos) /*!< SC_T::IER: TERR_IE Mask */
+
+#define SC_IER_TMR0_IE_Pos (3) /*!< SC_T::IER: TMR0_IE Position */
+#define SC_IER_TMR0_IE_Msk (0x1ul << SC_IER_TMR0_IE_Pos) /*!< SC_T::IER: TMR0_IE Mask */
+
+#define SC_IER_TMR1_IE_Pos (4) /*!< SC_T::IER: TMR1_IE Position */
+#define SC_IER_TMR1_IE_Msk (0x1ul << SC_IER_TMR1_IE_Pos) /*!< SC_T::IER: TMR1_IE Mask */
+
+#define SC_IER_TMR2_IE_Pos (5) /*!< SC_T::IER: TMR2_IE Position */
+#define SC_IER_TMR2_IE_Msk (0x1ul << SC_IER_TMR2_IE_Pos) /*!< SC_T::IER: TMR2_IE Mask */
+
+#define SC_IER_BGT_IE_Pos (6) /*!< SC_T::IER: BGT_IE Position */
+#define SC_IER_BGT_IE_Msk (0x1ul << SC_IER_BGT_IE_Pos) /*!< SC_T::IER: BGT_IE Mask */
+
+#define SC_IER_CD_IE_Pos (7) /*!< SC_T::IER: CD_IE Position */
+#define SC_IER_CD_IE_Msk (0x1ul << SC_IER_CD_IE_Pos) /*!< SC_T::IER: CD_IE Mask */
+
+#define SC_IER_INIT_IE_Pos (8) /*!< SC_T::IER: INIT_IE Position */
+#define SC_IER_INIT_IE_Msk (0x1ul << SC_IER_INIT_IE_Pos) /*!< SC_T::IER: INIT_IE Mask */
+
+#define SC_IER_RTMR_IE_Pos (9) /*!< SC_T::IER: RTMR_IE Position */
+#define SC_IER_RTMR_IE_Msk (0x1ul << SC_IER_RTMR_IE_Pos) /*!< SC_T::IER: RTMR_IE Mask */
+
+#define SC_IER_ACON_ERR_IE_Pos (10) /*!< SC_T::IER: ACON_ERR_IE Position */
+#define SC_IER_ACON_ERR_IE_Msk (0x1ul << SC_IER_ACON_ERR_IE_Pos) /*!< SC_T::IER: ACON_ERR_IE Mask */
+
+#define SC_ISR_RDA_IS_Pos (0) /*!< SC_T::ISR: RDA_IS Position */
+#define SC_ISR_RDA_IS_Msk (0x1ul << SC_ISR_RDA_IS_Pos) /*!< SC_T::ISR: RDA_IS Mask */
+
+#define SC_ISR_TBE_IS_Pos (1) /*!< SC_T::ISR: TBE_IS Position */
+#define SC_ISR_TBE_IS_Msk (0x1ul << SC_ISR_TBE_IS_Pos) /*!< SC_T::ISR: TBE_IS Mask */
+
+#define SC_ISR_TERR_IS_Pos (2) /*!< SC_T::ISR: TERR_IS Position */
+#define SC_ISR_TERR_IS_Msk (0x1ul << SC_ISR_TERR_IS_Pos) /*!< SC_T::ISR: TERR_IS Mask */
+
+#define SC_ISR_TMR0_IS_Pos (3) /*!< SC_T::ISR: TMR0_IS Position */
+#define SC_ISR_TMR0_IS_Msk (0x1ul << SC_ISR_TMR0_IS_Pos) /*!< SC_T::ISR: TMR0_IS Mask */
+
+#define SC_ISR_TMR1_IS_Pos (4) /*!< SC_T::ISR: TMR1_IS Position */
+#define SC_ISR_TMR1_IS_Msk (0x1ul << SC_ISR_TMR1_IS_Pos) /*!< SC_T::ISR: TMR1_IS Mask */
+
+#define SC_ISR_TMR2_IS_Pos (5) /*!< SC_T::ISR: TMR2_IS Position */
+#define SC_ISR_TMR2_IS_Msk (0x1ul << SC_ISR_TMR2_IS_Pos) /*!< SC_T::ISR: TMR2_IS Mask */
+
+#define SC_ISR_BGT_IS_Pos (6) /*!< SC_T::ISR: BGT_IS Position */
+#define SC_ISR_BGT_IS_Msk (0x1ul << SC_ISR_BGT_IS_Pos) /*!< SC_T::ISR: BGT_IS Mask */
+
+#define SC_ISR_CD_IS_Pos (7) /*!< SC_T::ISR: CD_IS Position */
+#define SC_ISR_CD_IS_Msk (0x1ul << SC_ISR_CD_IS_Pos) /*!< SC_T::ISR: CD_IS Mask */
+
+#define SC_ISR_INIT_IS_Pos (8) /*!< SC_T::ISR: INIT_IS Position */
+#define SC_ISR_INIT_IS_Msk (0x1ul << SC_ISR_INIT_IS_Pos) /*!< SC_T::ISR: INIT_IS Mask */
+
+#define SC_ISR_RTMR_IS_Pos (9) /*!< SC_T::ISR: RTMR_IS Position */
+#define SC_ISR_RTMR_IS_Msk (0x1ul << SC_ISR_RTMR_IS_Pos) /*!< SC_T::ISR: RTMR_IS Mask */
+
+#define SC_ISR_ACON_ERR_IS_Pos (10) /*!< SC_T::ISR: ACON_ERR_IS Position */
+#define SC_ISR_ACON_ERR_IS_Msk (0x1ul << SC_ISR_ACON_ERR_IS_Pos) /*!< SC_T::ISR: ACON_ERR_IS Mask */
+
+#define SC_TRSR_RX_OVER_F_Pos (0) /*!< SC_T::TRSR: RX_OVER_F Position */
+#define SC_TRSR_RX_OVER_F_Msk (0x1ul << SC_TRSR_RX_OVER_F_Pos) /*!< SC_T::TRSR: RX_OVER_F Mask */
+
+#define SC_TRSR_RX_EMPTY_F_Pos (1) /*!< SC_T::TRSR: RX_EMPTY_F Position */
+#define SC_TRSR_RX_EMPTY_F_Msk (0x1ul << SC_TRSR_RX_EMPTY_F_Pos) /*!< SC_T::TRSR: RX_EMPTY_F Mask */
+
+#define SC_TRSR_RX_FULL_F_Pos (2) /*!< SC_T::TRSR: RX_FULL_F Position */
+#define SC_TRSR_RX_FULL_F_Msk (0x1ul << SC_TRSR_RX_FULL_F_Pos) /*!< SC_T::TRSR: RX_FULL_F Mask */
+
+#define SC_TRSR_RX_EPA_F_Pos (4) /*!< SC_T::TRSR: RX_EPA_F Position */
+#define SC_TRSR_RX_EPA_F_Msk (0x1ul << SC_TRSR_RX_EPA_F_Pos) /*!< SC_T::TRSR: RX_EPA_F Mask */
+
+#define SC_TRSR_RX_EFR_F_Pos (5) /*!< SC_T::TRSR: RX_EFR_F Position */
+#define SC_TRSR_RX_EFR_F_Msk (0x1ul << SC_TRSR_RX_EFR_F_Pos) /*!< SC_T::TRSR: RX_EFR_F Mask */
+
+#define SC_TRSR_RX_EBR_F_Pos (6) /*!< SC_T::TRSR: RX_EBR_F Position */
+#define SC_TRSR_RX_EBR_F_Msk (0x1ul << SC_TRSR_RX_EBR_F_Pos) /*!< SC_T::TRSR: RX_EBR_F Mask */
+
+#define SC_TRSR_TX_OVER_F_Pos (8) /*!< SC_T::TRSR: TX_OVER_F Position */
+#define SC_TRSR_TX_OVER_F_Msk (0x1ul << SC_TRSR_TX_OVER_F_Pos) /*!< SC_T::TRSR: TX_OVER_F Mask */
+
+#define SC_TRSR_TX_EMPTY_F_Pos (9) /*!< SC_T::TRSR: TX_EMPTY_F Position */
+#define SC_TRSR_TX_EMPTY_F_Msk (0x1ul << SC_TRSR_TX_EMPTY_F_Pos) /*!< SC_T::TRSR: TX_EMPTY_F Mask */
+
+#define SC_TRSR_TX_FULL_F_Pos (10) /*!< SC_T::TRSR: TX_FULL_F Position */
+#define SC_TRSR_TX_FULL_F_Msk (0x1ul << SC_TRSR_TX_FULL_F_Pos) /*!< SC_T::TRSR: TX_FULL_F Mask */
+
+#define SC_TRSR_RX_POINT_F_Pos (16) /*!< SC_T::TRSR: RX_POINT_F Position */
+#define SC_TRSR_RX_POINT_F_Msk (0x7ul << SC_TRSR_RX_POINT_F_Pos) /*!< SC_T::TRSR: RX_POINT_F Mask */
+
+#define SC_TRSR_RX_REERR_Pos (21) /*!< SC_T::TRSR: RX_REERR Position */
+#define SC_TRSR_RX_REERR_Msk (0x1ul << SC_TRSR_RX_REERR_Pos) /*!< SC_T::TRSR: RX_REERR Mask */
+
+#define SC_TRSR_RX_OVER_ERETRY_Pos (22) /*!< SC_T::TRSR: RX_OVER_ERETRY Position */
+#define SC_TRSR_RX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_RX_OVER_ERETRY_Pos) /*!< SC_T::TRSR: RX_OVER_ERETRY Mask */
+
+#define SC_TRSR_RX_ATV_Pos (23) /*!< SC_T::TRSR: RX_ATV Position */
+#define SC_TRSR_RX_ATV_Msk (0x1ul << SC_TRSR_RX_ATV_Pos) /*!< SC_T::TRSR: RX_ATV Mask */
+
+#define SC_TRSR_TX_POINT_F_Pos (24) /*!< SC_T::TRSR: TX_POINT_F Position */
+#define SC_TRSR_TX_POINT_F_Msk (0x7ul << SC_TRSR_TX_POINT_F_Pos) /*!< SC_T::TRSR: TX_POINT_F Mask */
+
+#define SC_TRSR_TX_REERR_Pos (29) /*!< SC_T::TRSR: TX_REERR Position */
+#define SC_TRSR_TX_REERR_Msk (0x1ul << SC_TRSR_TX_REERR_Pos) /*!< SC_T::TRSR: TX_REERR Mask */
+
+#define SC_TRSR_TX_OVER_ERETRY_Pos (30) /*!< SC_T::TRSR: TX_OVER_ERETRY Position */
+#define SC_TRSR_TX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_TX_OVER_ERETRY_Pos) /*!< SC_T::TRSR: TX_OVER_ERETRY Mask */
+
+#define SC_TRSR_TX_ATV_Pos (31) /*!< SC_T::TRSR: TX_ATV Position */
+#define SC_TRSR_TX_ATV_Msk (0x1ul << SC_TRSR_TX_ATV_Pos) /*!< SC_T::TRSR: TX_ATV Mask */
+
+#define SC_PINCSR_POW_EN_Pos (0) /*!< SC_T::PINCSR: POW_EN Position */
+#define SC_PINCSR_POW_EN_Msk (0x1ul << SC_PINCSR_POW_EN_Pos) /*!< SC_T::PINCSR: POW_EN Mask */
+
+#define SC_PINCSR_SC_RST_Pos (1) /*!< SC_T::PINCSR: SC_RST Position */
+#define SC_PINCSR_SC_RST_Msk (0x1ul << SC_PINCSR_SC_RST_Pos) /*!< SC_T::PINCSR: SC_RST Mask */
+
+#define SC_PINCSR_CD_REM_F_Pos (2) /*!< SC_T::PINCSR: CD_REM_F Position */
+#define SC_PINCSR_CD_REM_F_Msk (0x1ul << SC_PINCSR_CD_REM_F_Pos) /*!< SC_T::PINCSR: CD_REM_F Mask */
+
+#define SC_PINCSR_CD_INS_F_Pos (3) /*!< SC_T::PINCSR: CD_INS_F Position */
+#define SC_PINCSR_CD_INS_F_Msk (0x1ul << SC_PINCSR_CD_INS_F_Pos) /*!< SC_T::PINCSR: CD_INS_F Mask */
+
+#define SC_PINCSR_CD_PIN_ST_Pos (4) /*!< SC_T::PINCSR: CD_PIN_ST Position */
+#define SC_PINCSR_CD_PIN_ST_Msk (0x1ul << SC_PINCSR_CD_PIN_ST_Pos) /*!< SC_T::PINCSR: CD_PIN_ST Mask */
+
+#define SC_PINCSR_CLK_KEEP_Pos (6) /*!< SC_T::PINCSR: CLK_KEEP Position */
+#define SC_PINCSR_CLK_KEEP_Msk (0x1ul << SC_PINCSR_CLK_KEEP_Pos) /*!< SC_T::PINCSR: CLK_KEEP Mask */
+
+#define SC_PINCSR_ADAC_CD_EN_Pos (7) /*!< SC_T::PINCSR: ADAC_CD_EN Position */
+#define SC_PINCSR_ADAC_CD_EN_Msk (0x1ul << SC_PINCSR_ADAC_CD_EN_Pos) /*!< SC_T::PINCSR: ADAC_CD_EN Mask */
+
+#define SC_PINCSR_SC_OEN_ST_Pos (8) /*!< SC_T::PINCSR: SC_OEN_ST Position */
+#define SC_PINCSR_SC_OEN_ST_Msk (0x1ul << SC_PINCSR_SC_OEN_ST_Pos) /*!< SC_T::PINCSR: SC_OEN_ST Mask */
+
+#define SC_PINCSR_SC_DATA_O_Pos (9) /*!< SC_T::PINCSR: SC_DATA_O Position */
+#define SC_PINCSR_SC_DATA_O_Msk (0x1ul << SC_PINCSR_SC_DATA_O_Pos) /*!< SC_T::PINCSR: SC_DATA_O Mask */
+
+#define SC_PINCSR_CD_LEV_Pos (10) /*!< SC_T::PINCSR: CD_LEV Position */
+#define SC_PINCSR_CD_LEV_Msk (0x1ul << SC_PINCSR_CD_LEV_Pos) /*!< SC_T::PINCSR: CD_LEV Mask */
+
+#define SC_PINCSR_POW_INV_Pos (11) /*!< SC_T::PINCSR: POW_INV Position */
+#define SC_PINCSR_POW_INV_Msk (0x1ul << SC_PINCSR_POW_INV_Pos) /*!< SC_T::PINCSR: POW_INV Mask */
+
+#define SC_PINCSR_SC_DATA_I_ST_Pos (16) /*!< SC_T::PINCSR: SC_DATA_I_ST Position */
+#define SC_PINCSR_SC_DATA_I_ST_Msk (0x1ul << SC_PINCSR_SC_DATA_I_ST_Pos) /*!< SC_T::PINCSR: SC_DATA_I_ST Mask */
+
+#define SC_TMR0_CNT_Pos (0) /*!< SC_T::TMR0: CNT Position */
+#define SC_TMR0_CNT_Msk (0xfffffful << SC_TMR0_CNT_Pos) /*!< SC_T::TMR0: CNT Mask */
+
+#define SC_TMR0_MODE_Pos (24) /*!< SC_T::TMR0: MODE Position */
+#define SC_TMR0_MODE_Msk (0xful << SC_TMR0_MODE_Pos) /*!< SC_T::TMR0: MODE Mask */
+
+#define SC_TMR1_CNT_Pos (0) /*!< SC_T::TMR1: CNT Position */
+#define SC_TMR1_CNT_Msk (0xfful << SC_TMR1_CNT_Pos) /*!< SC_T::TMR1: CNT Mask */
+
+#define SC_TMR1_MODE_Pos (24) /*!< SC_T::TMR1: MODE Position */
+#define SC_TMR1_MODE_Msk (0xful << SC_TMR1_MODE_Pos) /*!< SC_T::TMR1: MODE Mask */
+
+#define SC_TMR2_CNT_Pos (0) /*!< SC_T::TMR2: CNT Position */
+#define SC_TMR2_CNT_Msk (0xfful << SC_TMR2_CNT_Pos) /*!< SC_T::TMR2: CNT Mask */
+
+#define SC_TMR2_MODE_Pos (24) /*!< SC_T::TMR2: MODE Position */
+#define SC_TMR2_MODE_Msk (0xful << SC_TMR2_MODE_Pos) /*!< SC_T::TMR2: MODE Mask */
+
+#define SC_UACTL_UA_MODE_EN_Pos (0) /*!< SC_T::UACTL: UA_MODE_EN Position */
+#define SC_UACTL_UA_MODE_EN_Msk (0x1ul << SC_UACTL_UA_MODE_EN_Pos) /*!< SC_T::UACTL: UA_MODE_EN Mask */
+
+#define SC_UACTL_DATA_LEN_Pos (4) /*!< SC_T::UACTL: DATA_LEN Position */
+#define SC_UACTL_DATA_LEN_Msk (0x3ul << SC_UACTL_DATA_LEN_Pos) /*!< SC_T::UACTL: DATA_LEN Mask */
+
+#define SC_UACTL_PBDIS_Pos (6) /*!< SC_T::UACTL: PBDIS Position */
+#define SC_UACTL_PBDIS_Msk (0x1ul << SC_UACTL_PBDIS_Pos) /*!< SC_T::UACTL: PBDIS Mask */
+
+#define SC_UACTL_OPE_Pos (7) /*!< SC_T::UACTL: OPE Position */
+#define SC_UACTL_OPE_Msk (0x1ul << SC_UACTL_OPE_Pos) /*!< SC_T::UACTL: OPE Mask */
+
+#define SC_TDRA_TDR0_Pos (0) /*!< SC_T::TDRA: TDR0 Position */
+#define SC_TDRA_TDR0_Msk (0xfffffful << SC_TDRA_TDR0_Pos) /*!< SC_T::TDRA: TDR0 Mask */
+
+#define SC_TDRB_TDR1_Pos (0) /*!< SC_T::TDRB: TDR1 Position */
+#define SC_TDRB_TDR1_Msk (0xfful << SC_TDRB_TDR1_Pos) /*!< SC_T::TDRB: TDR1 Mask */
+
+#define SC_TDRB_TDR2_Pos (8) /*!< SC_T::TDRB: TDR2 Position */
+#define SC_TDRB_TDR2_Msk (0xfful << SC_TDRB_TDR2_Pos) /*!< SC_T::TDRB: TDR2 Mask */
+
+/**@}*/ /* SC_CONST */
+/**@}*/ /* end of SC register group */
+
+
+/*---------------------- Serial Peripheral Interface Controller -------------------------*/
+/**
+ @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+ Memory Mapped Structure for SPI Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x00 SPI Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GO_BUSY |SPI Transfer Control Bit And Busy Status
+ * | | |0 = Writing this bit "0" will stop data transfer if SPI is transferring.
+ * | | |1 = In Master mode, writing "1" to this bit will start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master.
+ * | | |If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'.
+ * | | |As the transfer is finished, this bit will be cleared automatically.
+ * | | |Software can read this bit to check if the SPI is in busy status.
+ * | | |In FIFO mode, this bit will be controlled by hardware.
+ * | | |Software should not modify this bit.
+ * | | |In slave mode, this bit always returns 1 when software reads this register.
+ * | | |In master mode, this bit reflects the busy or idle status of SPI.
+ * | | |Note:
+ * | | |1. When FIFO mode is disabled, all configurations should be set before writing "1" to the GO_BUSY bit in the SPI_CTL register.
+ * | | |2. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
+ * |[1] |RX_NEG |Receive At Negative Edge
+ * | | |0 = The received data is latched on the rising edge of SPI_SCLK.
+ * | | |1 = The received data is latched on the falling edge of SPI_SCLK.
+ * |[2] |TX_NEG |Transmit At Negative Edge
+ * | | |0 = The transmitted data output is changed on the rising edge of SPI_SCLK.
+ * | | |1 = The transmitted data output is changed on the falling edge of SPI_SCLK.
+ * |[7:3] |TX_BIT_LEN|Transmit Bit Length
+ * | | |This field specifies how many bits can be transmitted / received in one transaction.
+ * | | |The minimum bit length is 8 bits and can be up to 32 bits.
+ * | | |TX_BIT_LEN Description
+ * | | |01000 8 bits are transmitted in one transaction
+ * | | |01001 9 bits are transmitted in one transaction
+ * | | |------ ----------
+ * | | |11111 31 bits are transmitted in one transaction
+ * | | |00000 32 bits are transmitted in one transaction
+ * |[10] |LSB |Send LSB First
+ * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of TX_BITLEN, is transmitted/received first.
+ * | | |1 = The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the SPI_RX register (SPI_RX0/1).
+ * |[11] |CLKP |Clock Polarity
+ * | | |0 = The default level of SCLK is low in idle state.
+ * | | |1 = The default level of SCLK is high in idle state.
+ * |[15:12] |SP_CYCLE |Suspend Interval (Master Only)
+ * | | |These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
+ * | | |The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = "0".
+ * | | |If CLKP = "1", the interval is from the rising clock edge to the falling clock edge.
+ * | | |The default value is 0x3. The desired suspend interval is obtained according to the following equation:
+ * | | |(SP_CYCLE[3:0) + 0.5) * period of SPICLK
+ * | | |Ex:
+ * | | |SP_CYCLE = 0x0 ... 0.5 SPICLK clock cycle.
+ * | | |SP_CYCLE = 0x1 ... 1.5 SPICLK clock cycle.
+ * | | |......
+ * | | |SP_CYCLE = 0xE ... 14.5 SPICLK clock cycle.
+ * | | |SP_CYCLE = 0xF ... 15.5 SPICLK clock cycle.
+ * | | |If the Variable Clock function is enabled, the minimum period of suspend interval (the transmit data in FIFO buffer is not empty) between the successive transaction is (6.5 + SP_CYCLE) * SPICLK clock cycle
+ * |[17] |INTEN |Interrupt Enable
+ * | | |0 = SPI Interrupt Disabled.
+ * | | |1 = SPI Interrupt Enabled.
+ * |[18] |SLAVE |Slave Mode
+ * | | |0 = SPI controller set as Master mode.
+ * | | |1 = SPI controller set as Slave mode.
+ * |[19] |REORDER |Byte Reorder Function Enable
+ * | | |0 = Disable byte reorder function
+ * | | |1 = Enable byte reorder function and insert a byte suspend interval among each byte.
+ * | | |The setting of TX_BIT_LEN must be configured as 00b ( 32 bits/ word).
+ * | | |The suspend interval is defined in SP_CYCLE.
+ * | | |Note:
+ * | | |1. The byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
+ * | | |2. In Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
+ * | | |3. The byte reorder function is not supported when the variable serial clock function or the dual I/O mode is enabled.
+ * |[21] |FIFOM |FIFO Mode Enable
+ * | | |0 = Normal mode.
+ * | | |1 = FIFO mode.
+ * | | |Note:
+ * | | |1. Before enabling FIFO mode, the other related settings should be set in advance.
+ * | | |2. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set "1" automatically after the data was written into the 8-depth FIFO.
+ * | | |The user can clear this FIFO bit after the transmit FIFO status is empty and the GO_BUSY back to 0.
+ * |[22] |TWOB |2-Bit Transfer Mode Active
+ * | | |0 = 2-bit transfer mode Disabled.
+ * | | |1 = 2-bit transfer mode Enabled.
+ * | | |Note that when enabling TWOB, the serial transmitted 2-bits data are from SPI_TX1/0, and the received 2-bits data input are put into SPI_RX1/0.
+ * |[23] |VARCLK_EN |Variable Clock Enable
+ * | | |0 = The serial clock output frequency is fixed and only decided by the value of DIVIDER1
+ * | | |1 = The serial clock output frequency is variable.
+ * | | |The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1, and DIVIDER2.
+ * | | |Note: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
+ * |[28] |DUAL_IO_DIR|Dual IO Mode Direction
+ * | | |0 = Date read in the Dual I/O Mode function.
+ * | | |1 = Data write in the Dual I/O Mode function.
+ * |[29] |DUAL_IO_EN|Dual IO Mode Enable
+ * | | |0 = Dual I/O Mode function Disabled.
+ * | | |1 = Dual I/O Mode function Enabled.
+ * |[31] |WKEUP_EN |Wake-Up Enable
+ * | | |0 = Wake-up function Disabled when the system enters Power-down mode.
+ * | | |1 = Wake-up function Enabled.
+ * | | |When the system enters Power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port.
+ * | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * STATUS
+ * ===================================================================================================
+ * Offset: 0x04 SPI Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_EMPTY |Received FIFO_EMPTY Status
+ * | | |0 = Received data FIFO is not empty in the dual FIFO mode.
+ * | | |1 = Received data FIFO is empty in the dual FIFO mode.
+ * |[1] |RX_FULL |Received FIFO_FULL Status
+ * | | |0 = Received data FIFO is not full in dual FIFO mode.
+ * | | |1 = Received data FIFO is full in the dual FIFO mode.
+ * |[2] |TX_EMPTY |Transmitted FIFO_EMPTY Status
+ * | | |0 = Transmitted data FIFO is not empty in the dual FIFO mode.
+ * | | |1 =Transmitted data FIFO is empty in the dual FIFO mode.
+ * |[3] |TX_FULL |Transmitted FIFO_FULL Status
+ * | | |0 = Transmitted data FIFO is not full in the dual FIFO mode.
+ * | | |1 = Transmitted data FIFO is full in the dual FIFO mode.
+ * |[4] |LTRIG_FLAG|Level Trigger Accomplish Flag
+ * | | |In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.
+ * | | |0 = The transferred bit length of one transaction does not meet the specified requirement.
+ * | | |1 = The transferred bit length meets the specified requirement which defined in TX_BIT_LEN.
+ * | | |Note: This bit is READ only.
+ * | | |As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period.
+ * | | |In FIFO mode, this bit is unmeaning.
+ * |[6] |SLV_START_INTSTS|Slave Start Interrupt Status
+ * | | |It is used to dedicate that the transfer has started in Slave mode with no slave select.
+ * | | |0 = Slave started transfer no active.
+ * | | |1 = Transfer has started in Slave mode with no slave select.
+ * | | |It is auto clear by transfer done or writing one clear.
+ * |[7] |INTSTS |Interrupt Status
+ * | | |0 = Transfer is not finished yet.
+ * | | |1 = Transfer is done. The interrupt is requested when the INTEN bit is enabled.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to this bit.
+ * |[8] |RXINT_STS |RX FIFO Threshold Interrupt Status (Read Only)
+ * | | |0 = RX valid data counts small or equal than RXTHRESHOLD.
+ * | | |1 = RX valid data counts bigger than RXTHRESHOLD.
+ * | | |Note: If RXINT_EN = 1 and RX_INTSTS = 1, SPI will generate interrupt.
+ * |[9] |RX_OVER_RUN|RX FIFO Over Run Status
+ * | | |If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will dropped.
+ * | | |Note: This bit will be cleared by writing 1 to itself.
+ * |[10] |TXINT_STS |TX FIFO Threshold Interrupt Status (Read Only)
+ * | | |0 = TX valid data counts bigger than TXTHRESHOLD.
+ * | | |1 = TX valid data counts small or equal than TXTHRESHOLD.
+ * |[12] |TIME_OUT_STS|TIMEOUT Interrupt Flag
+ * | | |0 = There is not timeout event on the received buffer.
+ * | | |1 = RX FIFO is not empty and there is not be read over the 64 SPI_CLK period in master mode and over the 576 ECLK period in slave mode.
+ * | | |When the received FIFO is read by user, the timeout status will be cleared automatically.
+ * | | |Note: This bit will be cleared by writing 1 to itself.
+ * |[19:16] |RX_FIFO_CNT|Data counts in RX FIFO (Read Only)
+ * |[23:20] |TX_FIFO_CNT|Data counts in TX FIFO (Read Only)
+ */
+ __IO uint32_t STATUS;
+
+ /**
+ * CLKDIV
+ * ===================================================================================================
+ * Offset: 0x08 SPI Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DIVIDER1 |Clock Divider 1 Register
+ * | | |The value in this field is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
+ * | | |The desired frequency is obtained according to the following equation:
+ * | | |Where
+ * | | |is the SPI engine clock source. It is defined in the CLK_SEL1.
+ * |[23:16] |DIVIDER2 |Clock Divider 2 Register
+ * | | |The value in this field is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
+ * | | |The desired frequency is obtained according to the following equation:
+ */
+ __IO uint32_t CLKDIV;
+
+ /**
+ * SSR
+ * ===================================================================================================
+ * Offset: 0x0C SPI Slave Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |SSR |Slave Select Active Register (Master Only)
+ * | | |If AUTOSS bit is cleared, writing "1" to SSR[0] bit sets the SPISS[0] line to an active state and writing "0" sets the line back to inactive state.(the same as SSR[1] for SPISS[1])
+ * | | |If AUTOSS bit is set, writing "1" to any bit location of this field will select appropriate SPISS[1:0] line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time.
+ * | | |(The active level of SPISS[1:0] is specified in SS_LVL).
+ * | | |Note:
+ * | | |1. This interface can only drive one device/slave at a given time.
+ * | | |Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
+ * | | |2. SPISS[0] is also defined as device/slave select input in Slave mode.
+ * | | |And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software.
+ * |[2] |SS_LVL |Slave Select Active Level
+ * | | |It defines the active level of device/slave select signal (SPISS[1:0]).
+ * | | |0 = The SPI_SS slave select signal is active Low.
+ * | | |1 = The SPI_SS slave select signal is active High.
+ * |[3] |AUTOSS |Automatic Slave Selection (Master Only)
+ * | | |0 = If this bit is set as "0", slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register.
+ * | | |1 = If this bit is set as "1", SPISS[1:0] signals are generated automatically.
+ * | | |It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done.
+ * |[4] |SS_LTRIG |Slave Select Level Trigger
+ * | | |0 = The input slave select signal is edge-trigger.
+ * | | |1 = The slave select signal will be level-trigger.
+ * | | |It depends on SS_LVL to decide the signal is active low or active high.
+ * |[5] |NOSLVSEL |No Slave Selected In Slave Mode
+ * | | |This is used to ignore the slave select signal in Slave mode.
+ * | | |The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.
+ * | | |0 = The controller is 4-wire bi-direction interface.
+ * | | |1 = The controller is 3-wire bi-direction interface in Slave mode.
+ * | | |When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input.
+ * | | |Note: In no slave select signal mode, the SS_LTRIG, SPI_SSR[4], shall be set as "1".
+ * |[8] |SLV_ABORT |Abort In Slave Mode With No Slave Selected
+ * | | |In normal operation, there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN.
+ * | | |If the received bits are less than the requirement and there is no more serial clock input over the time period which is defined by user in slave mode with no slave select, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event.
+ * | | |Note: It is auto cleared to "0" by hardware when the abort event is active.
+ * |[9] |SSTA_INTEN|Slave Start Interrupt Enable
+ * | | |It is used to enable interrupt when the transfer has started in Slave mode with no slave select.
+ * | | |If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
+ * | | |0 = Tansfer start interrupt Disabled.
+ * | | |1 = Transaction start interrupt Enabled.
+ * | | |It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write 1 clear).
+ * |[16] |SS_INT_OPT|Slave Select Interrupt Option
+ * | | |It is used to enable the interrupt when the transfer has done in slave mode.
+ * | | |0 = No any interrupt, even there is slave select inactive event.
+ * | | |1 = There is interrupt event when the slave select is inactive.
+ * | | |It is used to inform the user the transaction has finished and the slave select into the inactive state.
+ */
+ __IO uint32_t SSR;
+
+ /**
+ * RX0
+ * ===================================================================================================
+ * Offset: 0x10 SPI Receive Data FIFO Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RDATA |Receive Data FIFO Register
+ * | | |The received data can be read on it.
+ * | | |If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not.
+ * | | |Note: These registers are read only.
+ */
+ __I uint32_t RX0;
+
+ /**
+ * RX1
+ * ===================================================================================================
+ * Offset: 0x14 SPI Receive Data FIFO Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RDATA |Receive Data FIFO Register
+ * | | |The received data can be read on it.
+ * | | |If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not.
+ * | | |Note: These registers are read only.
+ */
+ __I uint32_t RX1;
+ uint32_t RESERVE0[2];
+
+
+ /**
+ * TX0
+ * ===================================================================================================
+ * Offset: 0x20 SPI Transmit Data FIFO Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TDATA |Transmit Data FIFO Register
+ * | | |The Data Transmit Registers hold the data to be transmitted in the next transfer.
+ * | | |The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
+ * | | |For example, if TX_BIT_LEN is set to 0x08, the bit SPI_TX[7:0] will be transmitted in next transfer.
+ * | | |If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.
+ * | | |Note: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1
+ */
+ __O uint32_t TX0;
+
+ /**
+ * TX1
+ * ===================================================================================================
+ * Offset: 0x24 SPI Transmit Data FIFO Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TDATA |Transmit Data FIFO Register
+ * | | |The Data Transmit Registers hold the data to be transmitted in the next transfer.
+ * | | |The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
+ * | | |For example, if TX_BIT_LEN is set to 0x08, the bit SPI_TX[7:0] will be transmitted in next transfer.
+ * | | |If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.
+ * | | |Note: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1
+ */
+ __O uint32_t TX1;
+ uint32_t RESERVE1[3];
+
+
+ /**
+ * VARCLK
+ * ===================================================================================================
+ * Offset: 0x34 SPI Variable Clock Pattern Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |VARCLK |Variable Clock Pattern Flag
+ * | | |The value in this field is the frequency patterns of the SPICLK.
+ * | | |If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER1.
+ * | | |If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2.
+ * | | |Note: It is used for CLKP = 0 only.
+ */
+ __IO uint32_t VARCLK;
+
+ /**
+ * DMA
+ * ===================================================================================================
+ * Offset: 0x38 SPI DMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TX_DMA_EN |Transmit PDMA Enable (PDMA Writes Data To SPI)
+ * | | |Set this bit to 1 will start the transmit PDMA process.
+ * | | |SPI controller will issue request to PDMA controller automatically.
+ * | | |If using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register.
+ * | | |The DMA controller inside SPI controller will set it automatically whenever necessary.
+ * | | |Note:
+ * | | |1. Two transaction need minimal 18 APB clock + 8 SPI serial clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 serial clocks for level mode.
+ * | | |2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.
+ * | | |Hardware will clear this bit to 0 automatically after PDMA transfer done. If FIFO mode not release, it should be remove.
+ * |[1] |RX_DMA_EN |Receiving PDMA Enable(PDMA Reads SPI Data To Memory)
+ * | | |Set this bit to "1" will start the receive PDMA process.
+ * | | |SPI controller will issue request to PDMA controller automatically when there is data written into the received buffer or the status of RX_EMPTY status is set to 0 in FIFO mode.
+ * | | |If using the RX_PDMA mode to receive data but TX_DMA is disabled, the GO_BUSY bit shall be set by user.
+ * | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
+ * | | |In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI slave engine clock + 4 APB clock for edge mode and 9.5 SPI slave engine clock + 4 APB clock
+ * |[2] |PDMA_RST |PDMA Reset
+ * | | |It is used to reset the SPI PDMA function into default state.
+ * | | |0 = After reset PDMA function or in normal operation.
+ * | | |1 = Reset PDMA function.
+ * | | |Note: it is auto cleared to "0" after the reset function done.
+ */
+ __IO uint32_t DMA;
+
+ /**
+ * FFCTL
+ * ===================================================================================================
+ * Offset: 0x3C SPI FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_CLR |Receiving FIFO Counter Clear
+ * | | |This bit is used to clear the receiver counter in FIFO Mode.
+ * | | |This bit can be written "1" to clear the receiver counter and this bit will be cleared to "0" automatically after clearing receiving counter.
+ * | | |After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to "1".
+ * |[1] |TX_CLR |Transmitting FIFO Counter Clear
+ * | | |This bit is used to clear the transmit counter in FIFO Mode.
+ * | | |This bit can be written "1" to clear the transmitting counter and this bit will be cleared to "0" automatically after clearing transmitting counter.
+ * | | |After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to "1".
+ * |[2] |RXINT_EN |RX Threshold Interrupt Enable
+ * | | |0 = Rx threshold interrupt Disabled.
+ * | | |1 = RX threshold interrupt Enable.
+ * |[3] |TXINT_EN |TX Threshold Interrupt Enable
+ * | | |0 = Tx threshold interrupt Disabled.
+ * | | |1 = TX threshold interrupt Enable.
+ * |[4] |RXOVINT_EN|RX FIFO Over Run Interrupt Enable
+ * | | |0 = RX FIFO over run interrupt Disabled.
+ * | | |1 = RX FIFO over run interrupt Enabled.
+ * |[7] |TIMEOUT_EN|RX Read Timeout Function Enable
+ * | | |0 = RX read Timeout function Disabled.
+ * | | |1 = RX read Timeout function Enabled.
+ * |[26:24] |RX_THRESHOLD|Received FIFO Threshold
+ * | | |3-bits register, value from 0 ~7.
+ * | | |If RX valid data counts large than RXTHRESHOLD, RXINT_STS will set to 1, else RXINT_STS will set to 0.
+ * |[30:28] |TX_THRESHOLD|Transmit FIFO Threshold
+ * | | |3-bit register, value from 0 ~7.
+ * | | |If TX valid data counts small or equal than TXTHRESHOLD, TXINT_STS will set to 1, else TXINT_STS will set to 0
+ */
+ __IO uint32_t FFCTL;
+} SPI_T;
+
+/**
+ @addtogroup SPI_CONST SPI Bit Field Definition
+ Constant Definitions for SPI Controller
+@{ */
+
+#define SPI_CTL_GO_BUSY_Pos (0) /*!< SPI_T::CTL: GO_BUSY Position */
+#define SPI_CTL_GO_BUSY_Msk (0x1ul << SPI_CTL_GO_BUSY_Pos) /*!< SPI_T::CTL: GO_BUSY Mask */
+
+#define SPI_CTL_RX_NEG_Pos (1) /*!< SPI_T::CTL: RX_NEG Position */
+#define SPI_CTL_RX_NEG_Msk (0x1ul << SPI_CTL_RX_NEG_Pos) /*!< SPI_T::CTL: RX_NEG Mask */
+
+#define SPI_CTL_TX_NEG_Pos (2) /*!< SPI_T::CTL: TX_NEG Position */
+#define SPI_CTL_TX_NEG_Msk (0x1ul << SPI_CTL_TX_NEG_Pos) /*!< SPI_T::CTL: TX_NEG Mask */
+
+#define SPI_CTL_TX_BIT_LEN_Pos (3) /*!< SPI_T::CTL: TX_BIT_LEN Position */
+#define SPI_CTL_TX_BIT_LEN_Msk (0x1ful << SPI_CTL_TX_BIT_LEN_Pos) /*!< SPI_T::CTL: TX_BIT_LEN Mask */
+
+#define SPI_CTL_LSB_Pos (10) /*!< SPI_T::CTL: LSB Position */
+#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
+
+#define SPI_CTL_CLKP_Pos (11) /*!< SPI_T::CTL: CLKP Position */
+#define SPI_CTL_CLKP_Msk (0x1ul << SPI_CTL_CLKP_Pos) /*!< SPI_T::CTL: CLKP Mask */
+
+#define SPI_CTL_SP_CYCLE_Pos (12) /*!< SPI_T::CTL: SP_CYCLE Position */
+#define SPI_CTL_SP_CYCLE_Msk (0xful << SPI_CTL_SP_CYCLE_Pos) /*!< SPI_T::CTL: SP_CYCLE Mask */
+
+#define SPI_CTL_INTEN_Pos (17) /*!< SPI_T::CTL: INTEN Position */
+#define SPI_CTL_INTEN_Msk (0x1ul << SPI_CTL_INTEN_Pos) /*!< SPI_T::CTL: INTEN Mask */
+
+#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
+#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
+
+#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
+#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
+
+#define SPI_CTL_FIFOM_Pos (21) /*!< SPI_T::CTL: FIFOM Position */
+#define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos) /*!< SPI_T::CTL: FIFOM Mask */
+
+#define SPI_CTL_TWOB_Pos (22) /*!< SPI_T::CTL: TWOB Position */
+#define SPI_CTL_TWOB_Msk (0x1ul << SPI_CTL_TWOB_Pos) /*!< SPI_T::CTL: TWOB Mask */
+
+#define SPI_CTL_VARCLK_EN_Pos (23) /*!< SPI_T::CTL: VARCLK_EN Position */
+#define SPI_CTL_VARCLK_EN_Msk (0x1ul << SPI_CTL_VARCLK_EN_Pos) /*!< SPI_T::CTL: VARCLK_EN Mask */
+
+#define SPI_CTL_DUAL_IO_DIR_Pos (28) /*!< SPI_T::CTL: DUAL_IO_DIR Position */
+#define SPI_CTL_DUAL_IO_DIR_Msk (0x1ul << SPI_CTL_DUAL_IO_DIR_Pos) /*!< SPI_T::CTL: DUAL_IO_DIR Mask */
+
+#define SPI_CTL_DUAL_IO_EN_Pos (29) /*!< SPI_T::CTL: DUAL_IO_EN Position */
+#define SPI_CTL_DUAL_IO_EN_Msk (0x1ul << SPI_CTL_DUAL_IO_EN_Pos) /*!< SPI_T::CTL: DUAL_IO_EN Mask */
+
+#define SPI_CTL_WKEUP_EN_Pos (31) /*!< SPI_T::CTL: WKEUP_EN Position */
+#define SPI_CTL_WKEUP_EN_Msk (0x1ul << SPI_CTL_WKEUP_EN_Pos) /*!< SPI_T::CTL: WKEUP_EN Mask */
+
+#define SPI_STATUS_RX_EMPTY_Pos (0) /*!< SPI_T::STATUS: RX_EMPTY Position */
+#define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos) /*!< SPI_T::STATUS: RX_EMPTY Mask */
+
+#define SPI_STATUS_RX_FULL_Pos (1) /*!< SPI_T::STATUS: RX_FULL Position */
+#define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos) /*!< SPI_T::STATUS: RX_FULL Mask */
+
+#define SPI_STATUS_TX_EMPTY_Pos (2) /*!< SPI_T::STATUS: TX_EMPTY Position */
+#define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos) /*!< SPI_T::STATUS: TX_EMPTY Mask */
+
+#define SPI_STATUS_TX_FULL_Pos (3) /*!< SPI_T::STATUS: TX_FULL Position */
+#define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos) /*!< SPI_T::STATUS: TX_FULL Mask */
+
+#define SPI_STATUS_LTRIG_FLAG_Pos (4) /*!< SPI_T::STATUS: LTRIG_FLAG Position */
+#define SPI_STATUS_LTRIG_FLAG_Msk (0x1ul << SPI_STATUS_LTRIG_FLAG_Pos) /*!< SPI_T::STATUS: LTRIG_FLAG Mask */
+
+#define SPI_STATUS_SLV_START_INTSTS_Pos (6) /*!< SPI_T::STATUS: SLV_START_INTSTS Position */
+#define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos) /*!< SPI_T::STATUS: SLV_START_INTSTS Mask */
+
+#define SPI_STATUS_INTSTS_Pos (7) /*!< SPI_T::STATUS: INTSTS Position */
+#define SPI_STATUS_INTSTS_Msk (0x1ul << SPI_STATUS_INTSTS_Pos) /*!< SPI_T::STATUS: INTSTS Mask */
+
+#define SPI_STATUS_RXINT_STS_Pos (8) /*!< SPI_T::STATUS: RXINT_STS Position */
+#define SPI_STATUS_RXINT_STS_Msk (0x1ul << SPI_STATUS_RXINT_STS_Pos) /*!< SPI_T::STATUS: RXINT_STS Mask */
+
+#define SPI_STATUS_RX_OVER_RUN_Pos (9) /*!< SPI_T::STATUS: RX_OVER_RUN Position */
+#define SPI_STATUS_RX_OVER_RUN_Msk (0x1ul << SPI_STATUS_RX_OVER_RUN_Pos) /*!< SPI_T::STATUS: RX_OVER_RUN Mask */
+
+#define SPI_STATUS_TXINT_STS_Pos (10) /*!< SPI_T::STATUS: TXINT_STS Position */
+#define SPI_STATUS_TXINT_STS_Msk (0x1ul << SPI_STATUS_TXINT_STS_Pos) /*!< SPI_T::STATUS: TXINT_STS Mask */
+
+#define SPI_STATUS_TIME_OUT_STS_Pos (12) /*!< SPI_T::STATUS: TIME_OUT_STS Position */
+#define SPI_STATUS_TIME_OUT_STS_Msk (0x1ul << SPI_STATUS_TIME_OUT_STS_Pos) /*!< SPI_T::STATUS: TIME_OUT_STS Mask */
+
+#define SPI_STATUS_RX_FIFO_CNT_Pos (16) /*!< SPI_T::STATUS: RX_FIFO_CNT Position */
+#define SPI_STATUS_RX_FIFO_CNT_Msk (0xful << SPI_STATUS_RX_FIFO_CNT_Pos) /*!< SPI_T::STATUS: RX_FIFO_CNT Mask */
+
+#define SPI_STATUS_TX_FIFO_CNT_Pos (20) /*!< SPI_T::STATUS: TX_FIFO_CNT Position */
+#define SPI_STATUS_TX_FIFO_CNT_Msk (0xful << SPI_STATUS_TX_FIFO_CNT_Pos) /*!< SPI_T::STATUS: TX_FIFO_CNT Mask */
+
+#define SPI_CLKDIV_DIVIDER1_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER1 Position */
+#define SPI_CLKDIV_DIVIDER1_Msk (0xfful << SPI_CLKDIV_DIVIDER1_Pos) /*!< SPI_T::CLKDIV: DIVIDER1 Mask */
+
+#define SPI_CLKDIV_DIVIDER2_Pos (16) /*!< SPI_T::CLKDIV: DIVIDER2 Position */
+#define SPI_CLKDIV_DIVIDER2_Msk (0xfful << SPI_CLKDIV_DIVIDER2_Pos) /*!< SPI_T::CLKDIV: DIVIDER2 Mask */
+
+#define SPI_SSR_SSR_Pos (0) /*!< SPI_T::SSR: SSR Position */
+#define SPI_SSR_SSR_Msk (0x3ul << SPI_SSR_SSR_Pos) /*!< SPI_T::SSR: SSR Mask */
+
+#define SPI_SSR_SS_LVL_Pos (2) /*!< SPI_T::SSR: SS_LVL Position */
+#define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos) /*!< SPI_T::SSR: SS_LVL Mask */
+
+#define SPI_SSR_AUTOSS_Pos (3) /*!< SPI_T::SSR: AUTOSS Position */
+#define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos) /*!< SPI_T::SSR: AUTOSS Mask */
+
+#define SPI_SSR_SS_LTRIG_Pos (4) /*!< SPI_T::SSR: SS_LTRIG Position */
+#define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos) /*!< SPI_T::SSR: SS_LTRIG Mask */
+
+#define SPI_SSR_NOSLVSEL_Pos (5) /*!< SPI_T::SSR: NOSLVSEL Position */
+#define SPI_SSR_NOSLVSEL_Msk (0x1ul << SPI_SSR_NOSLVSEL_Pos) /*!< SPI_T::SSR: NOSLVSEL Mask */
+
+#define SPI_SSR_SLV_ABORT_Pos (8) /*!< SPI_T::SSR: SLV_ABORT Position */
+#define SPI_SSR_SLV_ABORT_Msk (0x1ul << SPI_SSR_SLV_ABORT_Pos) /*!< SPI_T::SSR: SLV_ABORT Mask */
+
+#define SPI_SSR_SSTA_INTEN_Pos (9) /*!< SPI_T::SSR: SSTA_INTEN Position */
+#define SPI_SSR_SSTA_INTEN_Msk (0x1ul << SPI_SSR_SSTA_INTEN_Pos) /*!< SPI_T::SSR: SSTA_INTEN Mask */
+
+#define SPI_SSR_SS_INT_OPT_Pos (16) /*!< SPI_T::SSR: SS_INT_OPT Position */
+#define SPI_SSR_SS_INT_OPT_Msk (0x1ul << SPI_SSR_SS_INT_OPT_Pos) /*!< SPI_T::SSR: SS_INT_OPT Mask */
+
+#define SPI_RX0_RDATA_Pos (0) /*!< SPI_T::RX0: RDATA Position */
+#define SPI_RX0_RDATA_Msk (0xfffffffful << SPI_RX0_RDATA_Pos) /*!< SPI_T::RX0: RDATA Mask */
+
+#define SPI_RX1_RDATA_Pos (0) /*!< SPI_T::RX1: RDATA Position */
+#define SPI_RX1_RDATA_Msk (0xfffffffful << SPI_RX1_RDATA_Pos) /*!< SPI_T::RX1: RDATA Mask */
+
+#define SPI_TX0_TDATA_Pos (0) /*!< SPI_T::TX0: TDATA Position */
+#define SPI_TX0_TDATA_Msk (0xfffffffful << SPI_TX0_TDATA_Pos) /*!< SPI_T::TX0: TDATA Mask */
+
+#define SPI_TX1_TDATA_Pos (0) /*!< SPI_T::TX1: TDATA Position */
+#define SPI_TX1_TDATA_Msk (0xfffffffful << SPI_TX1_TDATA_Pos) /*!< SPI_T::TX1: TDATA Mask */
+
+#define SPI_VARCLK_VARCLK_Pos (0) /*!< SPI_T::VARCLK: VARCLK Position */
+#define SPI_VARCLK_VARCLK_Msk (0xfffffffful << SPI_VARCLK_VARCLK_Pos) /*!< SPI_T::VARCLK: VARCLK Mask */
+
+#define SPI_DMA_TX_DMA_EN_Pos (0) /*!< SPI_T::DMA: TX_DMA_EN Position */
+#define SPI_DMA_TX_DMA_EN_Msk (0x1ul << SPI_DMA_TX_DMA_EN_Pos) /*!< SPI_T::DMA: TX_DMA_EN Mask */
+
+#define SPI_DMA_RX_DMA_EN_Pos (1) /*!< SPI_T::DMA: RX_DMA_EN Position */
+#define SPI_DMA_RX_DMA_EN_Msk (0x1ul << SPI_DMA_RX_DMA_EN_Pos) /*!< SPI_T::DMA: RX_DMA_EN Mask */
+
+#define SPI_DMA_PDMA_RST_Pos (2) /*!< SPI_T::DMA: PDMA_RST Position */
+#define SPI_DMA_PDMA_RST_Msk (0x1ul << SPI_DMA_PDMA_RST_Pos) /*!< SPI_T::DMA: PDMA_RST Mask */
+
+#define SPI_FFCTL_RX_CLR_Pos (0) /*!< SPI_T::FFCTL: RX_CLR Position */
+#define SPI_FFCTL_RX_CLR_Msk (0x1ul << SPI_FFCTL_RX_CLR_Pos) /*!< SPI_T::FFCTL: RX_CLR Mask */
+
+#define SPI_FFCTL_TX_CLR_Pos (1) /*!< SPI_T::FFCTL: TX_CLR Position */
+#define SPI_FFCTL_TX_CLR_Msk (0x1ul << SPI_FFCTL_TX_CLR_Pos) /*!< SPI_T::FFCTL: TX_CLR Mask */
+
+#define SPI_FFCTL_RX_INTEN_Pos (2) /*!< SPI_T::FFCTL: RX_INTEN Position */
+#define SPI_FFCTL_RX_INTEN_Msk (0x1ul << SPI_FFCTL_RX_INTEN_Pos) /*!< SPI_T::FFCTL: RX_INTEN Mask */
+
+#define SPI_FFCTL_TX_INTEN_Pos (3) /*!< SPI_T::FFCTL: TX_INTEN Position */
+#define SPI_FFCTL_TX_INTEN_Msk (0x1ul << SPI_FFCTL_TX_INTEN_Pos) /*!< SPI_T::FFCTL: TX_INTEN Mask */
+
+#define SPI_FFCTL_RXOVR_INTEN_Pos (4) /*!< SPI_T::FFCTL: RXOVR_INTEN Position */
+#define SPI_FFCTL_RXOVR_INTEN_Msk (0x1ul << SPI_FFCTL_RXOVR_INTEN_Pos) /*!< SPI_T::FFCTL: RXOVR_INTEN Mask */
+
+#define SPI_FFCTL_TIMEOUT_EN_Pos (7) /*!< SPI_T::FFCTL: TIMEOUT_EN Position */
+#define SPI_FFCTL_TIMEOUT_EN_Msk (0x1ul << SPI_FFCTL_TIMEOUT_EN_Pos) /*!< SPI_T::FFCTL: TIMEOUT_EN Mask */
+
+#define SPI_FFCTL_RX_THRESHOLD_Pos (24) /*!< SPI_T::FFCTL: RX_THRESHOLD Position */
+#define SPI_FFCTL_RX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_RX_THRESHOLD_Pos) /*!< SPI_T::FFCTL: RX_THRESHOLD Mask */
+
+#define SPI_FFCTL_TX_THRESHOLD_Pos (28) /*!< SPI_T::FFCTL: TX_THRESHOLD Position */
+#define SPI_FFCTL_TX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_TX_THRESHOLD_Pos) /*!< SPI_T::FFCTL: TX_THRESHOLD Mask */
+
+/**@}*/ /* SPI_CONST */
+/**@}*/ /* end of SPI register group */
+
+
+/*---------------------- Timer Controller -------------------------*/
+/**
+ @addtogroup TIMER Timer Controller(TIMER)
+ Memory Mapped Structure for TIMER Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x00 Timer x Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TMR_EN |Timer Counter Enable Bit
+ * | | |0 = Stops/Suspends counting.
+ * | | |1 = Starts counting.
+ * | | |Note1: Set TMR_EN to 1 enables 24-bit counter keeps up counting from the last stop counting value.
+ * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (MODE_SEL [5:4] =2'b00) once the value of 24-bit up counter equals the TMRx_CMPR.
+ * |[1] |SW_RST |Software Reset
+ * | | |Set this bit will reset the timer counter, pre-scale counter and also force TMR_CTL [TMR_EN] to 0.
+ * | | |0 = No effect.
+ * | | |1 = Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit.
+ * | | |Note: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles.
+ * |[2] |WAKE_EN |Wake-Up Enable
+ * | | |When WAKE_EN is set and the TMR_IS or TCAP_IS is set, the timer controller will generate a wake-up trigger event to CPU.
+ * | | |0 = Wake-up trigger event Disabled.
+ * | | |1 = Wake-up trigger event Enabled.
+ * |[3] |DBGACK_EN |ICE Debug Mode Acknowledge Ineffective Enable
+ * | | |0 = ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged.
+ * | | |1 = ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not.
+ * |[5:4] |MODE_SEL |Timer Operating Mode Select
+ * | | |00 = The timer is operating in the one-shot mode.
+ * | | |In this mode, the associated interrupt signal is generated (if TMR_IER [TMR_IE] is enabled) once the value of 24-bit up counter equals the TMRx_CMPR.
+ * | | |And TMR_CTL [TMR_EN] is automatically cleared by hardware.
+ * | | |01 = The timer is operating in the periodic mode.
+ * | | |In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR.
+ * | | |After that, the 24-bit counter will be reset and starts counting from zero again.
+ * | | |10 = The timer is operating in the periodic mode with output toggling.
+ * | | |In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR.
+ * | | |After that, the 24-bit counter will be reset and starts counting from zero again.
+ * | | |At the same time, timer controller will also toggle the output pin TMRx_TOG_OUT to its inverse level (from low to high or from high to low).
+ * | | |Note: The default level of TMRx_TOG_OUT after reset is low.
+ * | | |11 = The timer is operating in continuous counting mode.
+ * | | |In this mode, the associated interrupt signal is generated when TMR_DR = TMR_CMPR (if TMR_IER [TMR_IE] is enabled).
+ * | | |However, the 24-bit up-counter counts continuously without reset.
+ * |[7] |TMR_ACT |Timer Active Status Bit (Read Only)
+ * | | |This bit indicates the timer counter status of timer.
+ * | | |0 = Timer is not active.
+ * | | |1 = Timer is in active.
+ * |[8] |ADC_TEEN |TMR_IS Or TCAP_IS Trigger ADC Enable
+ * | | |This bit controls if TMR_IS or TCAP_IS could trigger ADC.
+ * | | |When ADC_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to ADC controller.
+ * | | |When ADC_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to ADC controller.
+ * | | |0 = TMR_IS or TCAP_IS trigger ADC Disabled.
+ * | | |1 = TMR_IS or TCAP_IS trigger ADC Enabled.
+ * |[9] |DAC_TEEN |TMR_IS Or TCAP_IS Trigger DAC Enable
+ * | | |This bit controls if TMR_IS or TCAP_IS could trigger DAC.
+ * | | |When DAC_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to DAC controller.
+ * | | |When DAC_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to DAC controller.
+ * | | |0 = TMR_IS or TCAP_IS trigger DAC Disabled.
+ * | | |1 = TMR_IS or TCAP_IS trigger DAC Enabled.
+ * |[10] |PDMA_TEEN |TMR_IS Or TCAP_IS Trigger PDMA Enable
+ * | | |This bit controls if TMR_IS or TCAP_IS could trigger PDMA.
+ * | | |When PDMA_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to PDMA controller.
+ * | | |When PDMA_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to PDMA controller.
+ * | | |0 = TMR_IS or TCAP_IS trigger PDMA Disabled.
+ * | | |1 = TMR_IS or TCAP_IS trigger PDMA Enabled.
+ * |[11] |CAP_TRG_EN|TCAP_IS Trigger Mode Enable
+ * | | |This bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA, DAC and ADC while TMR_IS or TCAP_IS is set.
+ * | | |If this bit is low and TMR_IS is set, timer will generate an internal trigger event to PDMA, DAC or ADC while related trigger enable bit (PDMA_TEEN, DAC_TEEN or ADC_TEEN) is also set.
+ * | | |If this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA, DAC or ADC while related trigger enable bit (PDMA_TEEN, DAC_TEEN or ADC_TEEN) is also set.
+ * | | |0 = TMR_IS is used to trigger PDMA, DAC and ADC.
+ * | | |1 = TCAP_IS is used to trigger PDMA, DAC and ADC.
+ * |[12] |EVENT_EN |Event Counting Mode Enable
+ * | | |When EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.
+ * | | |While the transition of external event pin matches the definition of EVENT_EDGE, the 24-bit up-counting timer increases by 1.
+ * | | |Or, the 24-bit up-counting timer will keep its value unchanged.
+ * | | |0 = Timer counting is not controlled by external event pin.
+ * | | |1 = Timer counting is controlled by external event pin.
+ * | | |Note: When EVENT_EN is enabled, user can not choose EXT_TMx(GPB) as clock source.
+ * | | |However, the speed of chosen clock must 3 times greater than the speed of EXT_TMx(GPB).
+ * |[13] |EVENT_EDGE|Event Counting Mode Edge Selection
+ * | | |This bit indicates which edge of external event pin enabling the timer to increase 1.
+ * | | |0 = A falling edge of external event enabling the timer to increase 1.
+ * | | |1 = A rising edge of external event enabling the timer to increase 1.
+ * |[14] |EVNT_DEB_EN|External Event De-Bounce Enable
+ * | | |When EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
+ * | | |In de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.
+ * | | |0 = De-bounce circuit Disabled.
+ * | | |1 = De-bounce circuit Enabled.
+ * | | |Note: When EVENT_EN is enabled, enable this bit is recommended.
+ * | | |And, while EVENT_EN is disabled, disable this bit is recommended to save power consumption.
+ * |[16] |TCAP_EN |Tcapture Pin Functional Enable
+ * | | |This bit controls if the transition on Tcapture pin could be used as timer counter reset function or timer capture function.
+ * | | |0 = The transition on Tcapture pin is ignored.
+ * | | |1 = The transition on Tcapture pin will result in the capture or reset of 24-bit timer counter.
+ * | | |Note: For TMRx_CTL, if INTR_TRG_EN is set, the TCAP_EN will be forced to low and the Tcapture pin transition is ignored.
+ * | | |Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EN will be forced to high.
+ * |[17] |TCAP_MODE |Tcapture Pin Function Mode Selection
+ * | | |This bit indicates if the transition on Tcapture pin is used as timer counter reset function or timer capture function.
+ * | | |0 = The transition on Tcapture pin is used as timer capture function.
+ * | | |1 = The transition on Tcapture pin is used as timer counter reset function.
+ * | | |Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low.
+ * |[19:18] |TCAP_EDGE |Tcapture Pin Edge Detect Selection
+ * | | |This field defines that active transition of Tcapture pin is for timer counter reset function or for timer capture function.
+ * | | |For timer counter reset function and free-counting mode of timer capture function, the configurations are:
+ * | | |00 = A falling edge (1 to 0 transition) on Tcapture pin is an active transition.
+ * | | |01 = A rising edge (0 to 1 transition) on Tcapture pin is an active transition.
+ * | | |10 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions.
+ * | | |11 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions.
+ * | | |For trigger-counting mode of timer capture function, the configurations are:
+ * | | |00 = 1st falling edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting.
+ * | | |01 = 1st rising edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting.
+ * | | |10 = Falling edge on Tcapture pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting.
+ * | | |11 = Rising edge on Tcapture pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting.
+ * | | |Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EDGE will be forced to 11.
+ * |[20] |TCAP_CNT_MODE|Timer Capture Counting Mode Selection
+ * | | |This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high.
+ * | | |If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL field.
+ * | | |When TCAP_EN is set, TCAP_MODE is 0, and the transition of Tcapture pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAPn.
+ * | | |If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero.
+ * | | |When TCAP_EN is set, TCAP_MODE is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE setting, the 24-bit up-counting timer will start counting.
+ * | | |And then if the transition of external pin matches the 2nd transition of TCAP_EDGE setting, the 24-bit up-counting timer will stop counting.
+ * | | |And its value will be saved into register TMRx_TCAPn.
+ * | | |0 = Capture with free-counting timer mode.
+ * | | |1 = Capture with trigger-counting timer mode.
+ * | | |Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the CAP_CNT_MOD will be forced to high, the capture with Trigger-counting Timer mode.
+ * |[22] |TCAP_DEB_EN|Tcapture Pin De-Bounce Enable
+ * | | |When CAP_DEB_EN is set, the Tcapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
+ * | | |In de-bounce circuit the Tcapture pin signal will be sampled 4 times by TMRx_CLK.
+ * | | |0 = De-bounce circuit Disabled.
+ * | | |1 = De-bounce circuit Enabled.
+ * | | |Note: When TCAP_EN is enabled, enable this bit is recommended.
+ * | | |And, while TCAP_EN is disabled, disable this bit is recommended to save power consumption.
+ * |[24] |INTR_TRG_EN|Inter-Timer Trigger Mode Enable
+ * | | |This bit controls if Inter-timer Trigger mode is enabled.
+ * | | |If Inter-timer Trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event.
+ * | | |And, TMRx+1 will be in trigger-counting mode of capture function.
+ * | | |0 = Inter-timer trigger mode Disabled.
+ * | | |1 = Inter-timer trigger mode Enabled.
+ * | | |Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0.
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * PRECNT
+ * ===================================================================================================
+ * Offset: 0x04 Timer x Pre-Scale Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |PRESCALE_CNT|Pre-Scale Counter
+ * | | |Clock input is divided by PRESCALE_CNT + 1 before it is fed to the counter.
+ * | | |If PRESCALE_CNT =0, then there is no scaling.
+ */
+ __IO uint32_t PRECNT;
+
+ /**
+ * CMPR
+ * ===================================================================================================
+ * Offset: 0x08 Timer x Compare Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |TMR_CMP |Timer Compared Value
+ * | | |TMR_CMP is a 24-bit compared register.
+ * | | |When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled.
+ * | | |The TMR_CMP value defines the timer counting cycle time.
+ * | | |Time-out period = (Period of timer clock input) * (8-bit PRESCALE_CNT + 1) * (24-bit TMR_CMP).
+ * | | |Note1: Never write 0x0 or 0x1 in TMR_CMP, or the core will run into unknown state.
+ * | | |Note2: No matter TMR_CTL [TMR_EN] is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
+ */
+ __IO uint32_t CMPR;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x0C Timer x Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TMR_IE |Timer Interrupt Enable
+ * | | |0 = Timer Interrupt Disabled.
+ * | | |1 = Timer Interrupt Enabled.
+ * | | |Note: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR.
+ * |[1] |TCAP_IE |Timer Capture Function Interrupt Enable
+ * | | |0 = Timer External Pin Function Interrupt Disabled.
+ * | | |1 = Timer External Pin Function Interrupt Enabled.
+ * | | |Note: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting
+ */
+ __IO uint32_t IER;
+
+ /**
+ * ISR
+ * ===================================================================================================
+ * Offset: 0x10 Timer x Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TMR_IS |Timer Interrupt Status
+ * | | |This bit indicates the interrupt status of Timer.
+ * | | |This bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR).
+ * | | |Write 1 to clear this bit to 0.
+ * | | |If this bit is active and TMR_IE is enabled, Timer will trigger an interrupt to CPU.
+ * |[1] |TCAP_IS |Timer Capture Function Interrupt Status
+ * | | |This bit indicates the external pin function interrupt status of Timer.
+ * | | |This bit is set by hardware when TCAP_EN is set high, and the transition of external pin matches the TCAP_EDGE setting.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |If this bit is active and TCAP_IE is enabled, Timer will trigger an interrupt to CPU.
+ * |[4] |TMR_Wake_STS|Timer Wake-Up Status
+ * | | |If timer causes CPU wakes up from power-down mode, this bit will be set to high.
+ * | | |It must be cleared by software with a write 1 to this bit.
+ * | | |0 = Timer does not cause system wake-up.
+ * | | |1 = Wakes system up from power-down mode by Timer timeout.
+ * |[5] |NCAP_DET_STS|New Capture Detected Status
+ * | | |This status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status.
+ * | | |If the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value.
+ * | | |This bit is also cleared to 0 while TCAP_IS is cleared.
+ * | | |0 = New incoming capture event didn't detect before CPU clearing TCAP_IS status.
+ * | | |1 = New incoming capture event detected before CPU clearing TCAP_IS status.
+ */
+ __IO uint32_t ISR;
+
+ /**
+ * DR
+ * ===================================================================================================
+ * Offset: 0x14 Timer x Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |TDR |Timer Data Register
+ * | | |User can read this register for internal 24-bit timer up-counter value.
+ */
+ __I uint32_t DR;
+
+ /**
+ * TCAP
+ * ===================================================================================================
+ * Offset: 0x18 Timer x Capture Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CAP |Timer Capture Data Register
+ * | | |When TCAP_EN is set, TCAP_MODE is 0, and the transition of external pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.
+ * | | |User can read this register for the counter value.
+ */
+ __I uint32_t TCAP;
+} TIMER_T;
+
+
+/**
+ @addtogroup TMR_CONST TIMER Bit Field Definition
+ Constant Definitions for TIMER Controller
+@{ */
+
+#define TIMER_CTL_TMR_EN_Pos (0) /*!< TIMER_T::CTL: TMR_EN Position */
+#define TIMER_CTL_TMR_EN_Msk (0x1ul << TIMER_CTL_TMR_EN_Pos) /*!< TIMER_T::CTL: TMR_EN Mask */
+
+#define TIMER_CTL_SW_RST_Pos (1) /*!< TIMER_T::CTL: SW_RST Position */
+#define TIMER_CTL_SW_RST_Msk (0x1ul << TIMER_CTL_SW_RST_Pos) /*!< TIMER_T::CTL: SW_RST Mask */
+
+#define TIMER_CTL_WAKE_EN_Pos (2) /*!< TIMER_T::CTL: WAKE_EN Position */
+#define TIMER_CTL_WAKE_EN_Msk (0x1ul << TIMER_CTL_WAKE_EN_Pos) /*!< TIMER_T::CTL: WAKE_EN Mask */
+
+#define TIMER_CTL_DBGACK_EN_Pos (3) /*!< TIMER_T::CTL: DBGACK_EN Position */
+#define TIMER_CTL_DBGACK_EN_Msk (0x1ul << TIMER_CTL_DBGACK_EN_Pos) /*!< TIMER_T::CTL: DBGACK_EN Mask */
+
+#define TIMER_CTL_MODE_SEL_Pos (4) /*!< TIMER_T::CTL: MODE_SEL Position */
+#define TIMER_CTL_MODE_SEL_Msk (0x3ul << TIMER_CTL_MODE_SEL_Pos) /*!< TIMER_T::CTL: MODE_SEL Mask */
+
+#define TIMER_CTL_TMR_ACT_Pos (7) /*!< TIMER_T::CTL: TMR_ACT Position */
+#define TIMER_CTL_TMR_ACT_Msk (0x1ul << TIMER_CTL_TMR_ACT_Pos) /*!< TIMER_T::CTL: TMR_ACT Mask */
+
+#define TIMER_CTL_ADC_TEEN_Pos (8) /*!< TIMER_T::CTL: ADC_TEEN Position */
+#define TIMER_CTL_ADC_TEEN_Msk (0x1ul << TIMER_CTL_ADC_TEEN_Pos) /*!< TIMER_T::CTL: ADC_TEEN Mask */
+
+#define TIMER_CTL_DAC_TEEN_Pos (9) /*!< TIMER_T::CTL: DAC_TEEN Position */
+#define TIMER_CTL_DAC_TEEN_Msk (0x1ul << TIMER_CTL_DAC_TEEN_Pos) /*!< TIMER_T::CTL: DAC_TEEN Mask */
+
+#define TIMER_CTL_PDMA_TEEN_Pos (10) /*!< TIMER_T::CTL: PDMA_TEEN Position */
+#define TIMER_CTL_PDMA_TEEN_Msk (0x1ul << TIMER_CTL_PDMA_TEEN_Pos) /*!< TIMER_T::CTL: PDMA_TEEN Mask */
+
+#define TIMER_CTL_CAP_TRG_EN_Pos (11) /*!< TIMER_T::CTL: CAP_TRG_EN Position */
+#define TIMER_CTL_CAP_TRG_EN_Msk (0x1ul << TIMER_CTL_CAP_TRG_EN_Pos) /*!< TIMER_T::CTL: CAP_TRG_EN Mask */
+
+#define TIMER_CTL_EVENT_EN_Pos (12) /*!< TIMER_T::CTL: EVENT_EN Position */
+#define TIMER_CTL_EVENT_EN_Msk (0x1ul << TIMER_CTL_EVENT_EN_Pos) /*!< TIMER_T::CTL: EVENT_EN Mask */
+
+#define TIMER_CTL_EVENT_EDGE_Pos (13) /*!< TIMER_T::CTL: EVENT_EDGE Position */
+#define TIMER_CTL_EVENT_EDGE_Msk (0x1ul << TIMER_CTL_EVENT_EDGE_Pos) /*!< TIMER_T::CTL: EVENT_EDGE Mask */
+
+#define TIMER_CTL_EVNT_DEB_EN_Pos (14) /*!< TIMER_T::CTL: EVNT_DEB_EN Position */
+#define TIMER_CTL_EVNT_DEB_EN_Msk (0x1ul << TIMER_CTL_EVNT_DEB_EN_Pos) /*!< TIMER_T::CTL: EVNT_DEB_EN Mask */
+
+#define TIMER_CTL_TCAP_EN_Pos (16) /*!< TIMER_T::CTL: TCAP_EN Position */
+#define TIMER_CTL_TCAP_EN_Msk (0x1ul << TIMER_CTL_TCAP_EN_Pos) /*!< TIMER_T::CTL: TCAP_EN Mask */
+
+#define TIMER_CTL_TCAP_MODE_Pos (17) /*!< TIMER_T::CTL: TCAP_MODE Position */
+#define TIMER_CTL_TCAP_MODE_Msk (0x1ul << TIMER_CTL_TCAP_MODE_Pos) /*!< TIMER_T::CTL: TCAP_MODE Mask */
+
+#define TIMER_CTL_TCAP_EDGE_Pos (18) /*!< TIMER_T::CTL: TCAP_EDGE Position */
+#define TIMER_CTL_TCAP_EDGE_Msk (0x3ul << TIMER_CTL_TCAP_EDGE_Pos) /*!< TIMER_T::CTL: TCAP_EDGE Mask */
+
+#define TIMER_CTL_TCAP_CNT_MODE_Pos (20) /*!< TIMER_T::CTL: TCAP_CNT_MODE Position */
+#define TIMER_CTL_TCAP_CNT_MODE_Msk (0x1ul << TIMER_CTL_TCAP_CNT_MODE_Pos) /*!< TIMER_T::CTL: TCAP_CNT_MODE Mask */
+
+#define TIMER_CTL_TCAP_DEB_EN_Pos (22) /*!< TIMER_T::CTL: TCAP_DEB_EN Position */
+#define TIMER_CTL_TCAP_DEB_EN_Msk (0x1ul << TIMER_CTL_TCAP_DEB_EN_Pos) /*!< TIMER_T::CTL: TCAP_DEB_EN Mask */
+
+#define TIMER_CTL_INTR_TRG_EN_Pos (24) /*!< TIMER_T::CTL: INTR_TRG_EN Position */
+#define TIMER_CTL_INTR_TRG_EN_Msk (0x1ul << TIMER_CTL_INTR_TRG_EN_Pos) /*!< TIMER_T::CTL: INTR_TRG_EN Mask */
+
+#define TIMER_PRECNT_PRESCALE_CNT_Pos (0) /*!< TIMER_T::PRECNT: PRESCALE_CNT Position */
+#define TIMER_PRECNT_PRESCALE_CNT_Msk (0xfful << TIMER_PRECNT_PRESCALE_CNT_Pos) /*!< TIMER_T::PRECNT: PRESCALE_CNT Mask */
+
+#define TIMER_CMPR_TMR_CMP_Pos (0) /*!< TIMER_T::CMPR: TMR_CMP Position */
+#define TIMER_CMPR_TMR_CMP_Msk (0xfffffful << TIMER_CMPR_TMR_CMP_Pos) /*!< TIMER_T::CMPR: TMR_CMP Mask */
+
+#define TIMER_IER_TMR_IE_Pos (0) /*!< TIMER_T::IER: TMR_IE Position */
+#define TIMER_IER_TMR_IE_Msk (0x1ul << TIMER_IER_TMR_IE_Pos) /*!< TIMER_T::IER: TMR_IE Mask */
+
+#define TIMER_IER_TCAP_IE_Pos (1) /*!< TIMER_T::IER: TCAP_IE Position */
+#define TIMER_IER_TCAP_IE_Msk (0x1ul << TIMER_IER_TCAP_IE_Pos) /*!< TIMER_T::IER: TCAP_IE Mask */
+
+#define TIMER_ISR_TMR_IS_Pos (0) /*!< TIMER_T::ISR: TMR_IS Position */
+#define TIMER_ISR_TMR_IS_Msk (0x1ul << TIMER_ISR_TMR_IS_Pos) /*!< TIMER_T::ISR: TMR_IS Mask */
+
+#define TIMER_ISR_TCAP_IS_Pos (1) /*!< TIMER_T::ISR: TCAP_IS Position */
+#define TIMER_ISR_TCAP_IS_Msk (0x1ul << TIMER_ISR_TCAP_IS_Pos) /*!< TIMER_T::ISR: TCAP_IS Mask */
+
+#define TIMER_ISR_TMR_WAKE_STS_Pos (4) /*!< TIMER_T::ISR: TMR_WAKE_STS Position */
+#define TIMER_ISR_TMR_WAKE_STS_Msk (0x1ul << TIMER_ISR_TMR_WAKE_STS_Pos) /*!< TIMER_T::ISR: TMR_WAKE_STS Mask */
+
+#define TIMER_ISR_NCAP_DET_STS_Pos (5) /*!< TIMER_T::ISR: NCAP_DET_STS Position */
+#define TIMER_ISR_NCAP_DET_STS_Msk (0x1ul << TIMER_ISR_NCAP_DET_STS_Pos) /*!< TIMER_T::ISR: NCAP_DET_STS Mask */
+
+#define TIMER_DR_TDR_Pos (0) /*!< TIMER_T::DR: TDR Position */
+#define TIMER_DR_TDR_Msk (0xfffffful << TIMER_DR_TDR_Pos) /*!< TIMER_T::DR: TDR Mask */
+
+#define TIMER_TCAP_CAP_Pos (0) /*!< TIMER_T::TCAP: CAP Position */
+#define TIMER_TCAP_CAP_Msk (0xfffffful << TIMER_TCAP_CAP_Pos) /*!< TIMER_T::TCAP: CAP Mask */
+
+/**@}*/ /* TMR_CONST */
+
+
+/**@}*/ /* end of TMR register group */
+
+
+
+/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
+/**
+ @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+ Memory Mapped Structure for UART Controller
+@{ */
+
+typedef struct {
+
+
+ union {
+
+ /**
+ * RBR
+ * ===================================================================================================
+ * Offset: 0x00 UART Receive Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |RBR |Receiving Buffer
+ * | | |By reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first).
+ */
+ __I uint32_t RBR;
+
+
+ /**
+ * THR
+ * ===================================================================================================
+ * Offset: 0x00 UART Transmit Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |THR |Transmit Buffer
+ * | | |By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first).
+ */
+ __O uint32_t THR;
+ };
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x04 UART Control State Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_RST |RX Software Reset
+ * | | |When RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the RX internal state machine and pointers.
+ * | | |Note: This bit will be auto cleared and take at least 3 UART engine clock cycles.
+ * |[1] |TX_RST |TX Software Reset
+ * | | |When TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the TX internal state machine and pointers.
+ * | | |Note: This bit will be auto cleared and take at least 3 UART engine clock cycles.
+ * |[2] |RX_DIS |Receiver Disable Register
+ * | | |The receiver is disabled or not (set "1" to disable receiver)
+ * | | |0 = Receiver Enabled.
+ * | | |1 = Receiver Disabled.
+ * | | |Note1: When used for RS-485 NMM mode, user can set this bit to receive data before detecting address byte.
+ * | | |Note2: In RS-485 AAD mode, this bit will be setting to "1" automatically.
+ * | | |Note3: In RS-485 AUD mode and LIN "break + sync +PID" header mode, hardware will control data automatically, so don't fill any value to this bit.
+ * |[3] |TX_DIS |Transfer Disable Register
+ * | | |The transceiver is disabled or not (set "1" to disable transceiver)
+ * | | |0 = Transfer Enabled.
+ * | | |1 = Transfer Disabled.
+ * |[4] |AUTO_RTS_EN|RTSn Auto-Flow Control Enable
+ * | | |0 = RTSn auto-flow control. Disabled.
+ * | | |1 = RTSn auto-flow control Enabled.
+ * | | |Note: When RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the UART_FCR [RTS_Tri_Lev], the UART will reassert RTSn signal.
+ * |[5] |AUTO_CTS_EN|CTSn Auto-Flow Control Enable
+ * | | |0 = CTSn auto-flow control. Disabled
+ * | | |1 = CTSn auto-flow control Enabled.
+ * | | |Note: When CTSn auto-flow is enabled, the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted).
+ * |[6] |DMA_RX_EN |RX DMA Enable
+ * | | |This bit can enable or disable RX PDMA service.
+ * | | |0 = RX PDMA service function Disabled.
+ * | | |1 = RX PDMA service function Enabled.
+ * |[7] |DMA_TX_EN |TX DMA Enable
+ * | | |This bit can enable or disable TX PDMA service.
+ * | | |0 = TX PDMA service function Disabled.
+ * | | |1 = TX PDMA service function Enabled.
+ * |[8] |WAKE_CTS_EN|CTSn Wake-Up Function Enable
+ * | | |0 = CTSn wake-up system function Disabled.
+ * | | |1 = Wake-up function Enabled when the system is in power-down mode, an external CTSn change will wake-up system from power-down mode.
+ * |[9] |WAKE_DATA_EN|Incoming Data Wake-Up Function Enable
+ * | | |0 = Incoming data wake-up system Disabled.
+ * | | |1 = Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode.
+ * | | |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
+ * |[12] |ABAUD_EN |Auto-Baud Rate Detect Enable
+ * | | |0 = Auto-baud rate detect function Disabled.
+ * | | |1 = Auto-baud rate detect function Enabled.
+ * | | |Note: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If UART_IER [ABAUD_IE] be enabled).
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * TLCTL
+ * ===================================================================================================
+ * Offset: 0x08 UART Transfer Line Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |DATA_LEN |Data Length
+ * | | |00 = 5 bits.
+ * | | |01 = 6 bits.
+ * | | |10 = 7 bits.
+ * | | |11 = 8 bits.
+ * |[2] |NSB |Number Of STOP Bit Length
+ * | | |1 = 1.5 "STOP bit" is generated in the transmitted data when 5-bit word length is selected, and 2 STOP bit" is generated when 6, 7 and 8 bits data length is selected.
+ * | | |0 = 1 " STOP bit" is generated in the transmitted data.
+ * |[3] |PBE |Parity Bit Enable
+ * | | |1 = Parity bit is generated or checked bet"een the "last data"word "it" and "stop bit" of the serial data.
+ * | | |0 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
+ * |[4] |EPE |Even Parity Enable
+ * | | |1 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |0 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |Note: This bit has effect only when PBE bit (parity bit enable) is set.
+ * |[5] |SPE |Stick Parity Enable
+ * | | |1 = When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as "0".
+ * | | |When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as "1".
+ * | | |In RS-485 mode, PBE, EPE and SPE can control bit 9.
+ * | | |0 = Stick parity Disabled.
+ * |[6] |BCB |Break Control Bit
+ * | | |When this bit is set to logic "1", the serial data output (TX) is forced to the Spacing State (logic "0").
+ * | | |This bit acts only on TX pin and has no effect on the transmitter logic.
+ * |[9:8] |RFITL |RX-FIFO Interrupt (INT_RDA) Trigger Level
+ * | | |When the number of bytes in the receiving FIFO is equal to the RFITL then the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated)
+ * | | |00 = INTR_RDA Trigger Level 1 byte.
+ * | | |01 = INTR_RDA Trigger Level 4 byte.
+ * | | |10 = INTR_RDA Trigger Level 8 byte.
+ * | | |11 = INTR_RDA Trigger Level 14 byte.
+ * | | |Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to "0".
+ * |[13:12] |RTS_TRI_LEV|RTSn Trigger Level (For Auto-Flow Control Use)
+ * | | |00 = Trigger level 1 byte.
+ * | | |01 = Trigger level 4 bytes.
+ * | | |10 = Trigger level 8 bytes.
+ * | | |11 = Trigger level 14 bytes.
+ * | | |Note: This field is used for auto RTSn flow control.
+ */
+ __IO uint32_t TLCTL;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x0C UART Interrupt Enable Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDA_IE |Receive Data Available Interrupt Enable
+ * | | |0 = INT_RDA Masked off.
+ * | | |1 = INT_RDA Enabled.
+ * |[1] |THRE_IE |Transmit Holding Register Empty Interrupt Enable
+ * | | |0 = INT_THRE Masked off.
+ * | | |1 = INT_THRE Enabled.
+ * |[2] |RLS_IE |Receive Line Status Interrupt Enable
+ * | | |0 = INT_RLS Masked off.
+ * | | |1 = INT_RLS Enabled.
+ * |[3] |MODEM_IE |Modem Status Interrupt Enable
+ * | | |0 = INT_MOS Masked off.
+ * | | |1 = INT_MOS Enabled.
+ * |[4] |RTO_IE |RX Time-Out Interrupt Enable
+ * | | |0 = INT_TOUT Masked off.
+ * | | |1 = INT_TOUT Enabled.
+ * |[5] |BUF_ERR_IE|Buffer Error Interrupt Enable
+ * | | |0 = INT_BUT_ERR Masked off.
+ * | | |1 = INT_BUF_ERR Enabled.
+ * |[6] |WAKE_IE |Wake-Up Interrupt Enable
+ * | | |0 = INT_WAKE Masked off.
+ * | | |1 = INT_WAKE Enabled.
+ * |[7] |ABAUD_IE |Auto-Baud Rate Interrupt Enable
+ * | | |0 = INT_ABAUD Masked off.
+ * | | |1 = INT_ABAUD Enabled.
+ * |[8] |LIN_IE |LIN Interrupt Enable
+ * | | |0 = INT_LIN Masked off.
+ * | | |1 = INT_LIN Enabled.
+ */
+ __IO uint32_t IER;
+
+ /**
+ * ISR
+ * ===================================================================================================
+ * Offset: 0x10 UART Interrupt Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDA_IS |Receive Data Available Interrupt Flag (Read Only)
+ * | | |When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set.
+ * | | |If IER [RDA_IEN] is set then the RDA interrupt will be generated.
+ * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL).
+ * |[1] |THRE_IS |Transmit Holding Register Empty Interrupt Flag (Read Only)
+ * | | |This bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register.
+ * | | |If IER [THRE_IEN] is set that the THRE interrupt will be generated.
+ * | | |Note: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty).
+ * |[2] |RLS_IS |Receive Line Interrupt Status Flag (Read Only)
+ * | | |This bit is set when the RX received data has parity error (UART_FSR [PE_F]), framing error (UART_FSR [FE_F]), break error (UART_FSR [BI_F]) or RS-485 detect address byte (UART_TRSR [RS-485_ADDET_F]).If IER [RLS_IEN] is set then the RLS interrupt will be generated.
+ * | | |Note1: This bit is read only, but can be cleared by it by writing "1" to UART_FSR [BI_F], UART_FSR [FE_F], UART_FSR [PE_F] or UART_TRSR [RS-485_ADDET_F].
+ * | | |Note2: This bit is cleared when all the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared.
+ * |[3] |MODEM_IS |MODEM Interrupt Status Flag (Read Only)
+ * | | |This bit is set when the CTSn pin has state change (DCTSF = "1").
+ * | | |If IER [MODEM_IEN] is set then the modem interrupt will be generated.
+ * | | |Note: This bit is read only, but can be cleared by it by writing "1" to UART_MCSR [DCT_F].
+ * |[4] |RTO_IS |RX Time-Out Interrupt Status Flag (Read Only)
+ * | | |This bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC.
+ * | | |If IER [Tout_IEN] is set then the tout interrupt will be generated.
+ * | | |Note: This bit is read only and user can read UART_RBR (RX is in active) to clear it.
+ * |[5] |BUF_ERR_IS|Buffer Error Interrupt Status Flag (Read Only)
+ * | | |This bit is set when the TX or RX-FIFO overflowed.
+ * | | |When BUF_ERR_IS is set, the transfer maybe not correct.
+ * | | |If IER [BUF_ER_IEN] is set then the buffer error interrupt will be generated.
+ * | | |Note1: This bit is read only, but can be cleared by it by writing "1" to UART_FSR [TX_OVER_F] or UART_FSR [RX_OVER_F].
+ * | | |Note2: This bit is cleared when both the TX_OVER_F and RX_OVER_F are cleared.
+ * |[6] |WAKE_IS |Wake-Up Interrupt Status Flag (Read Only)
+ * | | |This bit is set in Power-down mode, the receiver received data or CTSn signal.
+ * | | |If IER [WAKE_IE] is set then the wake-up interrupt will be generated.
+ * | | |Note: This bit is read only, but can be cleared by it by writing "1" to it.
+ * |[7] |ABAUD_IS |Auto-Baud Rate Interrupt Status Flag (Read Only)
+ * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if IER [ABAUD_IE] is set then the auto-baud rate interrupt will be generated.
+ * | | |Note1: This bit is read only, but can be cleared by it by writing "1" to UART_TRSR [ABAUD_TOUT_F] or UART_TRSR [ABAUD_F].
+ * | | |Note2: This bit is cleared when both the ABAUD_TOUT_F and ABAUD_F are cleared.
+ * |[8] |LIN_IS |LIN Interrupt Status Flag (Read Only)
+ * | | |This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if IER [LIN_IE] is set then the LIN interrupt will be generated.
+ * | | |Note1: This bit is read only, but can be cleared by it by writing "1" to UART_TRSR [BIT_ERR_F], UART_TRSR [BIT_TX_F] or UART_TRSR [LIN_RX_F].
+ * | | |Note2: This bit is cleared when both the BIT_ERR_F, BIT_TX_F and LIN_RX_F are cleared.
+ */
+ __IO uint32_t ISR;
+
+ /**
+ * TRSR
+ * ===================================================================================================
+ * Offset: 0x14 UART Transfer State Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RS485_ADDET_F|RS-485 Address Byte Detection Status Flag (Read Only)
+ * | | |This bit is set to logic "1" and set UART_ALT_CTL [RS-485_ADD_EN] whenever in RS-485 mode the receiver detected any address byte character (bit 9 ='1') bit".
+ * | | |This bit is reset whenever the CPU writes "1" to this bit.
+ * | | |Note1: This field is used for RS-485 mode.
+ * | | |Note2: This bit is read only, but can be cleared by writing "1" to it.
+ * |[1] |ABAUD_F |Auto-Baud Rate Interrupt (Read Only)
+ * | | |This bit is set to logic "1" when auto-baud rate detect function finished.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[2] |ABAUD_TOUT_F|Auto-Baud Rate Time-Out Interrupt (Read Only)
+ * | | |This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[3] |LIN_TX_F |LIN TX Interrupt Flag (Read Only)
+ * | | |This bit is set to logic "1" when LIN transmitted header field.
+ * | | |The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", it can be choose by setting UART_ALT_CTL[LIN_HEAD_SEL] register.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[4] |LIN_RX_F |LIN RX Interrupt Flag (Read Only)
+ * | | |This bit is set to logic "1" when received LIN header field.
+ * | | |The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", and it can be choose by setting UART_ALT_CTL [LIN_HEAD_SEL] register.
+ * | | |If the field includes "break field", when the receiver received break field then the LIN_RX_F will be set.
+ * | | |The controller will receive next data and put it in FIFO.
+ * | | |If the field includes "break field + sync field", hardware will wait for the flag LIN_RX_F in UART_TRSR to check RX received break field and sync field.
+ * | | |If the break and sync field is received, hardware will set UART_TRSR [LIN_RX_F] flag, and if the break is received but the sync field does not equal 0x55, then hardware will set UART_TRSR [LIN_RX_F] and UART_TRSR [LIN_RX_SYNC_ERR_F] flag.
+ * | | |The break and sync data (equals 0x55 or not) will not be stored in FIFO.
+ * | | |If the field includes "break field + sync field + PID field", In this operation mode, hardware will control data automatically.
+ * | | |Hardware will ignore any data until received break + sync (0x55) + PID value match the UART_ALT_CTL [ADDR_MATCH] value (break + sync + PID will not be stored in FIFO).
+ * | | |When received break + sync (0x55) + PID value match the UART_ALT_CTL [ADDR_MATCH] value, hardware will set UART_TRSR [LIN_RX_F] and the following all data will be accepted and stored in the RX-FIFO until detect next break field.
+ * | | |If the receiver received break + wrong sync (not equal 0x55) + PID value, hardware will set UART_TRSR [LIN_RX_F] and UART_TRSR [LIN_RX_SYNC_ERR_F] flag and the receiver will be disabled.
+ * | | |If the receiver received break + sync (0x55) + wrong PID value, hardware will set UART_TRSR [LIN_RX_F] flag and the receiver will be disabled.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[5] |BIT_ERR_F |Bit Error Detect Status Flag (Read Only)
+ * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BIT_ERR_F will be set.
+ * | | |When occur bit error, hardware will generate an interrupt to CPU (INT_LIN).
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: This bit is only valid when enabling the bit error detection function (UART_ALT_CTL [BIT_ERR_EN] = "1").
+ * |[8] |LIN_RX_SYNC_ERR_F|LIN RX SYNC Error Flag (Read Only)
+ * | | |This bit is set to logic "1" when LIN received incorrect SYNC field.
+ * | | |User can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register.
+ * | | |If the field includes "break field + sync field" and if the sync data does not equal 0x55, the LIN_RX_F and LIN_RX_SYNC_ERR_F will be set and the wrong sync data will be ignored.
+ * | | |The controller will receive next data and put it in FIFO.
+ * | | |If the field includes "break field + sync field + PID field" and if the sync data does not equal 0x55, the LIN_RX_F and LIN_RX_SYNC_ERR_F will be set and the wrong sync data will be ignored.
+ * | | |The controller will receive next data and put it in FIFO.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to LIN_RX_F.
+ */
+ __IO uint32_t TRSR;
+
+ /**
+ * FSR
+ * ===================================================================================================
+ * Offset: 0x18 UART FIFO State Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RX_OVER_F |RX Overflow Error Status Flag (Read Only)
+ * | | |This bit is set when RX-FIFO overflow.
+ * | | |If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[1] |RX_EMPTY_F|Receiver FIFO Empty (Read Only)
+ * | | |This bit initiate RX-FIFO empty or not.
+ * | | |When the last byte of RX-FIFO has been read by CPU, hardware sets this bit high.
+ * | | |It will be cleared when UART receives any new data.
+ * |[2] |RX_FULL_F |Receiver FIFO Full (Read Only)
+ * | | |This bit initiates RX-FIFO full or not.
+ * | | |This bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware.
+ * |[4] |PE_F |Parity Error State Status Flag (Read Only)
+ * | | |This bit is set to logic "1" whenever the received character does not have a valid "parity bit", and it is reset whenever the CPU writes "1" to this bit.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[5] |FE_F |Framing Error Status Flag (Read Only)
+ * | | |This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0"), and it is reset whenever the CPU writes "1" to this bit.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[6] |BI_F |Break Status Flag (Read Only)
+ * | | |This bit is set to a logic "1" whenever the received data input(RX) is held in the "spacing state" (logic "0") for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and it is reset whenever the CPU writes "1" to this bit.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[8] |TX_OVER_F |TX Overflow Error Interrupt Status Flag (Read Only)
+ * | | |If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic "1".
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[9] |TX_EMPTY_F|Transmitter FIFO Empty (Read Only)
+ * | | |This bit indicates TX-FIFO empty or not.
+ * | | |When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
+ * | | |It will be cleared when writing data into THR (TX-FIFO not empty).
+ * |[10] |TX_FULL_F |Transmitter FIFO Full (Read Only)
+ * | | |This bit indicates TX-FIFO full or not.
+ * | | |This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware.
+ * |[11] |TE_F |Transmitter Empty Status Flag (Read Only)
+ * | | |Bit is set by hardware when TX is inactive. (TX shift register does not have data)
+ * | | |Bit is cleared automatically when TX-FIFO is transfer data to TX shift register or TX is empty but the transfer does not finish.
+ * |[20:16] |RX_POINTER_F|RX-FIFO Pointer (Read Only)
+ * | | |This field indicates the RX-FIFO Buffer Pointer.
+ * | | |When UART receives one byte from external device, RX_POINTER_F increases one.
+ * | | |When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one.
+ * |[28:24] |TX_POINTER_F|TX-FIFO Pointer (Read Only)
+ * | | |This field indicates the TX-FIFO Buffer Pointer.
+ * | | |When CPU writes one byte data into UART_THR, TX_POINTER_F increases one.
+ * | | |When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one.
+ */
+ __IO uint32_t FSR;
+
+ /**
+ * MCSR
+ * ===================================================================================================
+ * Offset: 0x1C UART Modem State Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LEV_RTS |RTSn Trigger Level
+ * | | |This bit can change the RTSn trigger level.
+ * | | |0 = low level triggered.
+ * | | |1 = high level triggered.
+ * | | |Note: In RS-485 AUD mode and RTS Auto-flow control mode, hardware will control the output RTS pin automatically, so the table indicates the default value.
+ * | | |Note: The default setting in UART mode is LEV_RTS = "0" and RTS_ST = "1".
+ * |[1] |RTS_ST |RTSn Pin State (Read Only)
+ * | | |This bit is the pin status of RTSn.
+ * |[16] |LEV_CTS |CTSn Trigger Level
+ * | | |This bit can change the CTSn trigger level.
+ * | | |0 = Low level triggered.
+ * | | |1 = High level triggered.
+ * |[17] |CTS_ST |CTSn Pin Status (Read Only)
+ * | | |This bit is the pin status of CTSn.
+ * |[18] |DCT_F |Detect CTSn State Change Status Flag (Read Only)
+ * | | |This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when UART_IER [Modem_IEN].
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to it.
+ */
+ __IO uint32_t MCSR;
+
+ /**
+ * TMCTL
+ * ===================================================================================================
+ * Offset: 0x20 UART Time-Out Control State Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |TOIC |Time-Out Comparator
+ * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX-FIFO receives a new data word.
+ * | | |Once the content of time-out counter (TOUT_CNT) is equal to time-out interrupt comparator (TOIC), a receiver time-out interrupt (INT_TOUT) is generated if UART_IER [RTO_IEN].
+ * | | |A new incoming data word or RX-FIFO empty clears INT_TOUT.
+ * | | |Note1: Fill all "0" to this field indicates to disable this function.
+ * | | |Note2: The real time-out value is TOIC + 1.
+ * | | |Note3: The counting clock is baud rate clock.
+ * | | |Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to filled this field great than 0xA.
+ * |[23:16] |DLY |TX Delay Time Value
+ * | | |This field is use to program the transfer delay time between the last stop bit leaving the TX-FIFO and the de-assertion of by setting UART_TMCTL [DLY] register.
+ * | | |Note1: Fill all "0" to this field indicates to disable this function.
+ * | | |Note2: The real delay value is DLY.
+ * | | |Note3: The counting clock is baud rate clock.
+ */
+ __IO uint32_t TMCTL;
+
+ /**
+ * BAUD
+ * ===================================================================================================
+ * Offset: 0x24 UART Baud Rate Divisor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |BRD |Baud Rate Divider
+ * |[31] |DIV_16_EN |Divider 16 Enable
+ * | | |The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = UART_CLK/ [16 * (BRD + 1)]; The default value of M is 16.
+ * | | |0 = The equation of baud rate is UART_CLK / [ (BRD+1)].
+ * | | |1 = The equation of baud rate is UART_CLK / [16 * (BRD+1)].
+ * | | |Note: In IrDA mode, this bit must disable.
+ */
+ __IO uint32_t BAUD;
+ uint32_t RESERVE0[2];
+
+
+ /**
+ * IRCR
+ * ===================================================================================================
+ * Offset: 0x30 UART IrDA Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TX_SELECT |TX_SELECT
+ * | | |0 = IrDA receiver Enabled.
+ * | | |1 = IrDA transmitter Enabled.
+ * | | |Note: In IrDA mode, the UART_BAUD [DIV_16_EN) register must be set (the baud equation must be Clock / 16 * (BRD)
+ * |[5] |INV_TX |INV_TX
+ * | | |0 = No inversion.
+ * | | |1 = Inverse TX output signal.
+ * |[6] |INV_RX |INV_RX
+ * | | |0 = No inversion.
+ * | | |1 = Inverse RX input signal.
+ */
+ __IO uint32_t IRCR;
+
+ /**
+ * ALT_CTL
+ * ===================================================================================================
+ * Offset: 0x34 UART Alternate Control State Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |LIN_TX_BCNT|LIN TX Break Field Count Register
+ * | | |The field contains 3-bit LIN TX break field count.
+ * | | |Note: The break field length is LIN_TX_BCNT + 8.
+ * |[5:4] |LIN_HEAD_SEL|LIN Header Selection
+ * | | |00 = The LIN header includes "break field".
+ * | | |01 = The LIN header includes "break field + sync field".
+ * | | |10 = The LIN header includes "break field + sync field + PID field".
+ * | | |11 = Reserved.
+ * |[6] |LIN_RX_EN |LIN RX Enable
+ * | | |When LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN)
+ * | | |0 = LIN RX mode Disabled.
+ * | | |1 = LIN RX mode Enabled.
+ * |[7] |LIN_TX_EN |LIN TX Header Trigger Enable
+ * | | |0 = LIN TX Header Trigger Disabled.
+ * | | |1 = LIN TX Header Trigger Enabled.
+ * | | |Note1: When TX header field (break field or break and sync field or break, sync and PID field) transfer operation finished, this bit will be cleared automatically and generate a interrupt to CPU (INT_LIN).
+ * | | |Note2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit.
+ * |[8] |Bit_ERR_EN|Bit Error Detect Enable
+ * | | |0 = Bit error detection function Disabled.
+ * | | |1 = Bit error detection Enabled.
+ * | | |Note: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN).
+ * |[16] |RS485_NMM |RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)
+ * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
+ * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
+ * | | |Note: It can't be active in RS-485_AAD Operation mode.
+ * |[17] |RS485_AAD |RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)
+ * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
+ * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
+ * | | |Note: It can't be active in RS-485_NMM Operation mode.
+ * |[18] |RS485_AUD |RS-485 Auto Direction Mode (RS-485 AUD Mode)
+ * | | |0 = RS-485 Auto Direction mode (AUD) Disabled.
+ * | | |1 = RS-485 Auto Direction mode (AUD) Enabled.
+ * | | |Note: It can be active in RS-485_AAD or RS-485_NMM operation mode.
+ * |[19] |RS485_ADD_EN|RS-485 Address Detection Enable
+ * | | |This bit is used to enable RS-485 hardware address detection mode.
+ * | | |If hardware detects address byte, and then the controller will set UART_TRSR [RS485_ADDET_F] = "1".
+ * | | |0 = Address detection mode Disabled.
+ * | | |1 = Address detection mode Enabled.
+ * | | |Note: This field is used for RS-485 any operation mode.
+ * |[31:24] |ADDR_PID_MATCH|Address / PID Match Value Register
+ * | | |This field contains the RS-485 address match values in RS-485 Function mode.
+ * | | |This field contains the LIN protected identifier field n LIN Function mode, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1.
+ * | | |Note: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID).
+ */
+ __IO uint32_t ALT_CTL;
+
+ /**
+ * FUN_SEL
+ * ===================================================================================================
+ * Offset: 0x38 UART Function Select Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FUN_SEL |Function Select Enable
+ * | | |00 = UART function mode.
+ * | | |01 = LIN function mode.
+ * | | |10 = IrDA Function.
+ * | | |11 = RS-485 Function.
+ */
+ __IO uint32_t FUN_SEL;
+
+} UART_T;
+
+/**
+ @addtogroup UART_CONST UART Bit Field Definition
+ Constant Definitions for UART Controller
+@{ */
+
+#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
+#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
+
+#define UART_CTL_RX_RST_Pos (0) /*!< UART_T::CTL: RX_RST Position */
+#define UART_CTL_RX_RST_Msk (0x1ul << UART_CTL_RX_RST_Pos) /*!< UART_T::CTL: RX_RST Mask */
+
+#define UART_CTL_TX_RST_Pos (1) /*!< UART_T::CTL: TX_RST Position */
+#define UART_CTL_TX_RST_Msk (0x1ul << UART_CTL_TX_RST_Pos) /*!< UART_T::CTL: TX_RST Mask */
+
+#define UART_CTL_RX_DIS_Pos (2) /*!< UART_T::CTL: RX_DIS Position */
+#define UART_CTL_RX_DIS_Msk (0x1ul << UART_CTL_RX_DIS_Pos) /*!< UART_T::CTL: RX_DIS Mask */
+
+#define UART_CTL_TX_DIS_Pos (3) /*!< UART_T::CTL: TX_DIS Position */
+#define UART_CTL_TX_DIS_Msk (0x1ul << UART_CTL_TX_DIS_Pos) /*!< UART_T::CTL: TX_DIS Mask */
+
+#define UART_CTL_AUTO_RTS_EN_Pos (4) /*!< UART_T::CTL: AUTO_RTS_EN Position */
+#define UART_CTL_AUTO_RTS_EN_Msk (0x1ul << UART_CTL_AUTO_RTS_EN_Pos) /*!< UART_T::CTL: AUTO_RTS_EN Mask */
+
+#define UART_CTL_AUTO_CTS_EN_Pos (5) /*!< UART_T::CTL: AUTO_CTS_EN Position */
+#define UART_CTL_AUTO_CTS_EN_Msk (0x1ul << UART_CTL_AUTO_CTS_EN_Pos) /*!< UART_T::CTL: AUTO_CTS_EN Mask */
+
+#define UART_CTL_DMA_RX_EN_Pos (6) /*!< UART_T::CTL: DMA_RX_EN Position */
+#define UART_CTL_DMA_RX_EN_Msk (0x1ul << UART_CTL_DMA_RX_EN_Pos) /*!< UART_T::CTL: DMA_RX_EN Mask */
+
+#define UART_CTL_DMA_TX_EN_Pos (7) /*!< UART_T::CTL: DMA_TX_EN Position */
+#define UART_CTL_DMA_TX_EN_Msk (0x1ul << UART_CTL_DMA_TX_EN_Pos) /*!< UART_T::CTL: DMA_TX_EN Mask */
+
+#define UART_CTL_WAKE_CTS_EN_Pos (8) /*!< UART_T::CTL: WAKE_CTS_EN Position */
+#define UART_CTL_WAKE_CTS_EN_Msk (0x1ul << UART_CTL_WAKE_CTS_EN_Pos) /*!< UART_T::CTL: WAKE_CTS_EN Mask */
+
+#define UART_CTL_WAKE_DATA_EN_Pos (9) /*!< UART_T::CTL: WAKE_DATA_EN Position */
+#define UART_CTL_WAKE_DATA_EN_Msk (0x1ul << UART_CTL_WAKE_DATA_EN_Pos) /*!< UART_T::CTL: WAKE_DATA_EN Mask */
+
+#define UART_CTL_ABAUD_EN_Pos (12) /*!< UART_T::CTL: ABAUD_EN Position */
+#define UART_CTL_ABAUD_EN_Msk (0x1ul << UART_CTL_ABAUD_EN_Pos) /*!< UART_T::CTL: ABAUD_EN Mask */
+
+#define UART_TLCTL_DATA_LEN_Pos (0) /*!< UART_T::TLCTL: DATA_LEN Position */
+#define UART_TLCTL_DATA_LEN_Msk (0x3ul << UART_TLCTL_DATA_LEN_Pos) /*!< UART_T::TLCTL: DATA_LEN Mask */
+
+#define UART_TLCTL_NSB_Pos (2) /*!< UART_T::TLCTL: NSB Position */
+#define UART_TLCTL_NSB_Msk (0x1ul << UART_TLCTL_NSB_Pos) /*!< UART_T::TLCTL: NSB Mask */
+
+#define UART_TLCTL_PBE_Pos (3) /*!< UART_T::TLCTL: PBE Position */
+#define UART_TLCTL_PBE_Msk (0x1ul << UART_TLCTL_PBE_Pos) /*!< UART_T::TLCTL: PBE Mask */
+
+#define UART_TLCTL_EPE_Pos (4) /*!< UART_T::TLCTL: EPE Position */
+#define UART_TLCTL_EPE_Msk (0x1ul << UART_TLCTL_EPE_Pos) /*!< UART_T::TLCTL: EPE Mask */
+
+#define UART_TLCTL_SPE_Pos (5) /*!< UART_T::TLCTL: SPE Position */
+#define UART_TLCTL_SPE_Msk (0x1ul << UART_TLCTL_SPE_Pos) /*!< UART_T::TLCTL: SPE Mask */
+
+#define UART_TLCTL_BCB_Pos (6) /*!< UART_T::TLCTL: BCB Position */
+#define UART_TLCTL_BCB_Msk (0x1ul << UART_TLCTL_BCB_Pos) /*!< UART_T::TLCTL: BCB Mask */
+
+#define UART_TLCTL_RFITL_Pos (8) /*!< UART_T::TLCTL: RFITL Position */
+#define UART_TLCTL_RFITL_Msk (0x3ul << UART_TLCTL_RFITL_Pos) /*!< UART_T::TLCTL: RFITL Mask */
+
+#define UART_TLCTL_RTS_TRI_LEV_Pos (12) /*!< UART_T::TLCTL: RTS_TRI_LEV Position */
+#define UART_TLCTL_RTS_TRI_LEV_Msk (0x3ul << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_T::TLCTL: RTS_TRI_LEV Mask */
+
+#define UART_IER_RDA_IE_Pos (0) /*!< UART_T::IER: RDA_IE Position */
+#define UART_IER_RDA_IE_Msk (0x1ul << UART_IER_RDA_IE_Pos) /*!< UART_T::IER: RDA_IE Mask */
+
+#define UART_IER_THRE_IE_Pos (1) /*!< UART_T::IER: THRE_IE Position */
+#define UART_IER_THRE_IE_Msk (0x1ul << UART_IER_THRE_IE_Pos) /*!< UART_T::IER: THRE_IE Mask */
+
+#define UART_IER_RLS_IE_Pos (2) /*!< UART_T::IER: RLS_IE Position */
+#define UART_IER_RLS_IE_Msk (0x1ul << UART_IER_RLS_IE_Pos) /*!< UART_T::IER: RLS_IE Mask */
+
+#define UART_IER_MODEM_IE_Pos (3) /*!< UART_T::IER: MODEM_IE Position */
+#define UART_IER_MODEM_IE_Msk (0x1ul << UART_IER_MODEM_IE_Pos) /*!< UART_T::IER: MODEM_IE Mask */
+
+#define UART_IER_RTO_IE_Pos (4) /*!< UART_T::IER: RTO_IE Position */
+#define UART_IER_RTO_IE_Msk (0x1ul << UART_IER_RTO_IE_Pos) /*!< UART_T::IER: RTO_IE Mask */
+
+#define UART_IER_BUF_ERR_IE_Pos (5) /*!< UART_T::IER: BUF_ERR_IE Position */
+#define UART_IER_BUF_ERR_IE_Msk (0x1ul << UART_IER_BUF_ERR_IE_Pos) /*!< UART_T::IER: BUF_ERR_IE Mask */
+
+#define UART_IER_WAKE_IE_Pos (6) /*!< UART_T::IER: WAKE_IE Position */
+#define UART_IER_WAKE_IE_Msk (0x1ul << UART_IER_WAKE_IE_Pos) /*!< UART_T::IER: WAKE_IE Mask */
+
+#define UART_IER_ABAUD_IE_Pos (7) /*!< UART_T::IER: ABAUD_IE Position */
+#define UART_IER_ABAUD_IE_Msk (0x1ul << UART_IER_ABAUD_IE_Pos) /*!< UART_T::IER: ABAUD_IE Mask */
+
+#define UART_IER_LIN_IE_Pos (8) /*!< UART_T::IER: LIN_IE Position */
+#define UART_IER_LIN_IE_Msk (0x1ul << UART_IER_LIN_IE_Pos) /*!< UART_T::IER: LIN_IE Mask */
+
+#define UART_ISR_RDA_IS_Pos (0) /*!< UART_T::ISR: RDA_IS Position */
+#define UART_ISR_RDA_IS_Msk (0x1ul << UART_ISR_RDA_IS_Pos) /*!< UART_T::ISR: RDA_IS Mask */
+
+#define UART_ISR_THRE_IS_Pos (1) /*!< UART_T::ISR: THRE_IS Position */
+#define UART_ISR_THRE_IS_Msk (0x1ul << UART_ISR_THRE_IS_Pos) /*!< UART_T::ISR: THRE_IS Mask */
+
+#define UART_ISR_RLS_IS_Pos (2) /*!< UART_T::ISR: RLS_IS Position */
+#define UART_ISR_RLS_IS_Msk (0x1ul << UART_ISR_RLS_IS_Pos) /*!< UART_T::ISR: RLS_IS Mask */
+
+#define UART_ISR_MODEM_IS_Pos (3) /*!< UART_T::ISR: MODEM_IS Position */
+#define UART_ISR_MODEM_IS_Msk (0x1ul << UART_ISR_MODEM_IS_Pos) /*!< UART_T::ISR: MODEM_IS Mask */
+
+#define UART_ISR_RTO_IS_Pos (4) /*!< UART_T::ISR: RTO_IS Position */
+#define UART_ISR_RTO_IS_Msk (0x1ul << UART_ISR_RTO_IS_Pos) /*!< UART_T::ISR: RTO_IS Mask */
+
+#define UART_ISR_BUF_ERR_IS_Pos (5) /*!< UART_T::ISR: BUF_ERR_IS Position */
+#define UART_ISR_BUF_ERR_IS_Msk (0x1ul << UART_ISR_BUF_ERR_IS_Pos) /*!< UART_T::ISR: BUF_ERR_IS Mask */
+
+#define UART_ISR_WAKE_IS_Pos (6) /*!< UART_T::ISR: WAKE_IS Position */
+#define UART_ISR_WAKE_IS_Msk (0x1ul << UART_ISR_WAKE_IS_Pos) /*!< UART_T::ISR: WAKE_IS Mask */
+
+#define UART_ISR_ABAUD_IS_Pos (7) /*!< UART_T::ISR: ABAUD_IS Position */
+#define UART_ISR_ABAUD_IS_Msk (0x1ul << UART_ISR_ABAUD_IS_Pos) /*!< UART_T::ISR: ABAUD_IS Mask */
+
+#define UART_ISR_LIN_IS_Pos (8) /*!< UART_T::ISR: LIN_IS Position */
+#define UART_ISR_LIN_IS_Msk (0x1ul << UART_ISR_LIN_IS_Pos) /*!< UART_T::ISR: LIN_IS Mask */
+
+#define UART_TRSR_RS485_ADDET_F_Pos (0) /*!< UART_T::TRSR: RS485_ADDET_F Position */
+#define UART_TRSR_RS485_ADDET_F_Msk (0x1ul << UART_TRSR_RS485_ADDET_F_Pos) /*!< UART_T::TRSR: RS485_ADDET_F Mask */
+
+#define UART_TRSR_ABAUD_F_Pos (1) /*!< UART_T::TRSR: ABAUD_F Position */
+#define UART_TRSR_ABAUD_F_Msk (0x1ul << UART_TRSR_ABAUD_F_Pos) /*!< UART_T::TRSR: ABAUD_F Mask */
+
+#define UART_TRSR_ABAUD_TOUT_F_Pos (2) /*!< UART_T::TRSR: ABAUD_TOUT_F Position */
+#define UART_TRSR_ABAUD_TOUT_F_Msk (0x1ul << UART_TRSR_ABAUD_TOUT_F_Pos) /*!< UART_T::TRSR: ABAUD_TOUT_F Mask */
+
+#define UART_TRSR_LIN_TX_F_Pos (3) /*!< UART_T::TRSR: LIN_TX_F Position */
+#define UART_TRSR_LIN_TX_F_Msk (0x1ul << UART_TRSR_LIN_TX_F_Pos) /*!< UART_T::TRSR: LIN_TX_F Mask */
+
+#define UART_TRSR_LIN_RX_F_Pos (4) /*!< UART_T::TRSR: LIN_RX_F Position */
+#define UART_TRSR_LIN_RX_F_Msk (0x1ul << UART_TRSR_LIN_RX_F_Pos) /*!< UART_T::TRSR: LIN_RX_F Mask */
+
+#define UART_TRSR_BIT_ERR_F_Pos (5) /*!< UART_T::TRSR: BIT_ERR_F Position */
+#define UART_TRSR_BIT_ERR_F_Msk (0x1ul << UART_TRSR_BIT_ERR_F_Pos) /*!< UART_T::TRSR: BIT_ERR_F Mask */
+
+#define UART_TRSR_LIN_RX_SYNC_ERR_F_Pos (8) /*!< UART_T::TRSR: LIN_RX_SYNC_ERR_F Position */
+#define UART_TRSR_LIN_RX_SYNC_ERR_F_Msk (0x1ul << UART_TRSR_LIN_RX_SYNC_ERR_F_Pos) /*!< UART_T::TRSR: LIN_RX_SYNC_ERR_F Mask */
+
+#define UART_FSR_RX_OVER_F_Pos (0) /*!< UART_T::FSR: RX_OVER_F Position */
+#define UART_FSR_RX_OVER_F_Msk (0x1ul << UART_FSR_RX_OVER_F_Pos) /*!< UART_T::FSR: RX_OVER_F Mask */
+
+#define UART_FSR_RX_EMPTY_F_Pos (1) /*!< UART_T::FSR: RX_EMPTY_F Position */
+#define UART_FSR_RX_EMPTY_F_Msk (0x1ul << UART_FSR_RX_EMPTY_F_Pos) /*!< UART_T::FSR: RX_EMPTY_F Mask */
+
+#define UART_FSR_RX_FULL_F_Pos (2) /*!< UART_T::FSR: RX_FULL_F Position */
+#define UART_FSR_RX_FULL_F_Msk (0x1ul << UART_FSR_RX_FULL_F_Pos) /*!< UART_T::FSR: RX_FULL_F Mask */
+
+#define UART_FSR_PE_F_Pos (4) /*!< UART_T::FSR: PE_F Position */
+#define UART_FSR_PE_F_Msk (0x1ul << UART_FSR_PE_F_Pos) /*!< UART_T::FSR: PE_F Mask */
+
+#define UART_FSR_FE_F_Pos (5) /*!< UART_T::FSR: FE_F Position */
+#define UART_FSR_FE_F_Msk (0x1ul << UART_FSR_FE_F_Pos) /*!< UART_T::FSR: FE_F Mask */
+
+#define UART_FSR_BI_F_Pos (6) /*!< UART_T::FSR: BI_F Position */
+#define UART_FSR_BI_F_Msk (0x1ul << UART_FSR_BI_F_Pos) /*!< UART_T::FSR: BI_F Mask */
+
+#define UART_FSR_TX_OVER_F_Pos (8) /*!< UART_T::FSR: TX_OVER_F Position */
+#define UART_FSR_TX_OVER_F_Msk (0x1ul << UART_FSR_TX_OVER_F_Pos) /*!< UART_T::FSR: TX_OVER_F Mask */
+
+#define UART_FSR_TX_EMPTY_F_Pos (9) /*!< UART_T::FSR: TX_EMPTY_F Position */
+#define UART_FSR_TX_EMPTY_F_Msk (0x1ul << UART_FSR_TX_EMPTY_F_Pos) /*!< UART_T::FSR: TX_EMPTY_F Mask */
+
+#define UART_FSR_TX_FULL_F_Pos (10) /*!< UART_T::FSR: TX_FULL_F Position */
+#define UART_FSR_TX_FULL_F_Msk (0x1ul << UART_FSR_TX_FULL_F_Pos) /*!< UART_T::FSR: TX_FULL_F Mask */
+
+#define UART_FSR_TE_F_Pos (11) /*!< UART_T::FSR: TE_F Position */
+#define UART_FSR_TE_F_Msk (0x1ul << UART_FSR_TE_F_Pos) /*!< UART_T::FSR: TE_F Mask */
+
+#define UART_FSR_RX_POINTER_F_Pos (16) /*!< UART_T::FSR: RX_POINTER_F Position */
+#define UART_FSR_RX_POINTER_F_Msk (0x1ful << UART_FSR_RX_POINTER_F_Pos) /*!< UART_T::FSR: RX_POINTER_F Mask */
+
+#define UART_FSR_TX_POINTER_F_Pos (24) /*!< UART_T::FSR: TX_POINTER_F Position */
+#define UART_FSR_TX_POINTER_F_Msk (0x1ful << UART_FSR_TX_POINTER_F_Pos) /*!< UART_T::FSR: TX_POINTER_F Mask */
+
+#define UART_MCSR_LEV_RTS_Pos (0) /*!< UART_T::MCSR: LEV_RTS Position */
+#define UART_MCSR_LEV_RTS_Msk (0x1ul << UART_MCSR_LEV_RTS_Pos) /*!< UART_T::MCSR: LEV_RTS Mask */
+
+#define UART_MCSR_RTS_ST_Pos (1) /*!< UART_T::MCSR: RTS_ST Position */
+#define UART_MCSR_RTS_ST_Msk (0x1ul << UART_MCSR_RTS_ST_Pos) /*!< UART_T::MCSR: RTS_ST Mask */
+
+#define UART_MCSR_LEV_CTS_Pos (16) /*!< UART_T::MCSR: LEV_CTS Position */
+#define UART_MCSR_LEV_CTS_Msk (0x1ul << UART_MCSR_LEV_CTS_Pos) /*!< UART_T::MCSR: LEV_CTS Mask */
+
+#define UART_MCSR_CTS_ST_Pos (17) /*!< UART_T::MCSR: CTS_ST Position */
+#define UART_MCSR_CTS_ST_Msk (0x1ul << UART_MCSR_CTS_ST_Pos) /*!< UART_T::MCSR: CTS_ST Mask */
+
+#define UART_MCSR_DCT_F_Pos (18) /*!< UART_T::MCSR: DCT_F Position */
+#define UART_MCSR_DCT_F_Msk (0x1ul << UART_MCSR_DCT_F_Pos) /*!< UART_T::MCSR: DCT_F Mask */
+
+#define UART_TMCTL_TOIC_Pos (0) /*!< UART_T::TMCTL: TOIC Position */
+#define UART_TMCTL_TOIC_Msk (0x1fful << UART_TMCTL_TOIC_Pos) /*!< UART_T::TMCTL: TOIC Mask */
+
+#define UART_TMCTL_DLY_Pos (16) /*!< UART_T::TMCTL: DLY Position */
+#define UART_TMCTL_DLY_Msk (0xfful << UART_TMCTL_DLY_Pos) /*!< UART_T::TMCTL: DLY Mask */
+
+#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
+#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
+
+#define UART_BAUD_DIV_16_EN_Pos (31) /*!< UART_T::BAUD: DIV_16_EN Position */
+#define UART_BAUD_DIV_16_EN_Msk (0x1ul << UART_BAUD_DIV_16_EN_Pos) /*!< UART_T::BAUD: DIV_16_EN Mask */
+
+#define UART_IRCR_TX_SELECT_Pos (1) /*!< UART_T::IRCR: TX_SELECT Position */
+#define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos) /*!< UART_T::IRCR: TX_SELECT Mask */
+
+#define UART_IRCR_INV_TX_Pos (5) /*!< UART_T::IRCR: INV_TX Position */
+#define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos) /*!< UART_T::IRCR: INV_TX Mask */
+
+#define UART_IRCR_INV_RX_Pos (6) /*!< UART_T::IRCR: INV_RX Position */
+#define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos) /*!< UART_T::IRCR: INV_RX Mask */
+
+#define UART_ALT_CTL_LIN_TX_BCNT_Pos (0) /*!< UART_T::ALT_CTL: LIN_TX_BCNT Position */
+#define UART_ALT_CTL_LIN_TX_BCNT_Msk (0x7ul << UART_ALT_CTL_LIN_TX_BCNT_Pos) /*!< UART_T::ALT_CTL: LIN_TX_BCNT Mask */
+
+#define UART_ALT_CTL_LIN_HEAD_SEL_Pos (4) /*!< UART_T::ALT_CTL: LIN_HEAD_SEL Position */
+#define UART_ALT_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_ALT_CTL_LIN_HEAD_SEL_Pos) /*!< UART_T::ALT_CTL: LIN_HEAD_SEL Mask */
+
+#define UART_ALT_CTL_LIN_RX_EN_Pos (6) /*!< UART_T::ALT_CTL: LIN_RX_EN Position */
+#define UART_ALT_CTL_LIN_RX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_RX_EN_Pos) /*!< UART_T::ALT_CTL: LIN_RX_EN Mask */
+
+#define UART_ALT_CTL_LIN_TX_EN_Pos (7) /*!< UART_T::ALT_CTL: LIN_TX_EN Position */
+#define UART_ALT_CTL_LIN_TX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_TX_EN_Pos) /*!< UART_T::ALT_CTL: LIN_TX_EN Mask */
+
+#define UART_ALT_CTL_Bit_ERR_EN_Pos (8) /*!< UART_T::ALT_CTL: Bit_ERR_EN Position */
+#define UART_ALT_CTL_Bit_ERR_EN_Msk (0x1ul << UART_ALT_CTL_Bit_ERR_EN_Pos) /*!< UART_T::ALT_CTL: Bit_ERR_EN Mask */
+
+#define UART_ALT_CTL_RS485_NMM_Pos (16) /*!< UART_T::ALT_CTL: RS485_NMM Position */
+#define UART_ALT_CTL_RS485_NMM_Msk (0x1ul << UART_ALT_CTL_RS485_NMM_Pos) /*!< UART_T::ALT_CTL: RS485_NMM Mask */
+
+#define UART_ALT_CTL_RS485_AAD_Pos (17) /*!< UART_T::ALT_CTL: RS485_AAD Position */
+#define UART_ALT_CTL_RS485_AAD_Msk (0x1ul << UART_ALT_CTL_RS485_AAD_Pos) /*!< UART_T::ALT_CTL: RS485_AAD Mask */
+
+#define UART_ALT_CTL_RS485_AUD_Pos (18) /*!< UART_T::ALT_CTL: RS485_AUD Position */
+#define UART_ALT_CTL_RS485_AUD_Msk (0x1ul << UART_ALT_CTL_RS485_AUD_Pos) /*!< UART_T::ALT_CTL: RS485_AUD Mask */
+
+#define UART_ALT_CTL_RS485_ADD_EN_Pos (19) /*!< UART_T::ALT_CTL: RS485_ADD_EN Position */
+#define UART_ALT_CTL_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CTL_RS485_ADD_EN_Pos) /*!< UART_T::ALT_CTL: RS485_ADD_EN Mask */
+
+#define UART_ALT_CTL_ADDR_PID_MATCH_Pos (24) /*!< UART_T::ALT_CTL: ADDR_PID_MATCH Position */
+#define UART_ALT_CTL_ADDR_PID_MATCH_Msk (0xfful << UART_ALT_CTL_ADDR_PID_MATCH_Pos) /*!< UART_T::ALT_CTL: ADDR_PID_MATCH Mask */
+
+#define UART_FUN_SEL_FUN_SEL_Pos (0) /*!< UART_T::FUN_SEL: FUN_SEL Position */
+#define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_T::FUN_SEL: FUN_SEL Mask */
+
+/**@}*/ /* UART_CONST */
+/**@}*/ /* end of UART register group */
+
+
+/*---------------------- USB Device Controller -------------------------*/
+/**
+ @addtogroup USBD USB Device Controller(USBD)
+ Memory Mapped Structure for USBD Controller
+@{ */
+
+/**
+ * @brief USBD endpoints register
+ */
+typedef struct {
+
+
+ /**
+ * BUFSEGx
+ * ===================================================================================================
+ * Offset: 0x20+x*0x10 Endpoint x Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:3] |BUFSEG |It Is Used To Define The Offset Address For Each Endpoint With The USB SRAM Starting Address Its physical address is USB_SRAM address + {BUFSEG[5:0], 000}; where the USB_SRAM = USB_BASE + 0x100h.
+ * | | |Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description.
+ */
+ __IO uint32_t BUFSEG;
+
+ /**
+ * MXPLDx
+ * ===================================================================================================
+ * Offset: 0x24+x*0x10 Endpoint x Maximal Payload Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |MXPLD |Maximal Payload
+ * | | |It is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token).
+ * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
+ * | | |(1). When the register is written by CPU,
+ * | | |For IN token, the value of MXPLD is used to define the length of data to be transmitted and indicate the data buffer is ready.
+ * | | |For OUT token, it means that the controller is ready to receive data from host and the value of MXPLD is the maximal data length comes from host.
+ * | | |(2). When the register is read by CPU,
+ * | | |For IN token, the value of MXPLD is indicated the length of data be transmitted to host
+ * | | |For OUT token, the value of MXPLD is indicated the actual length of data receiving from host.
+ * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
+ */
+ __IO uint32_t MXPLD;
+
+ /**
+ * CFGx
+ * ===================================================================================================
+ * Offset: 0x28+x*0x10 Endpoint x Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |EP_NUM |Endpoint Number
+ * | | |These bits are used to define the endpoint number of the current endpoint
+ * |[4] |ISOCH |Isochronous Endpoint
+ * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
+ * |[6:5] |EPMODE |Endpoint Mode
+ * | | |00 = Endpoint is disabled.
+ * | | |01 = Out endpoint.
+ * | | |10 = IN endpoint.
+ * | | |11 = Undefined.
+ * |[7] |DSQ_SYNC |Data Sequence Synchronization
+ * | | |0 = DATA0 PID.
+ * | | |1 = DATA1 PID.
+ * | | |It is used to specify the DATA0 or DATA1 PID in the current transaction.
+ * | | |It will toggle automatically in IN token after host response ACK.
+ * | | |In the other tokens, the user shall take care of it to confirm the right PID in its transaction.
+ * |[8] |CSTALL |Clear STALL Response
+ * | | |0 = Disable the device to clear the STALL handshake in setup stage.
+ * | | |1 = Clear the device to response STALL handshake in setup stage.
+ * |[9] |SSTALL |Set STALL Response
+ * | | |0 = Disable the device to response STALL.
+ * | | |1 = Set the device to respond STALL automatically.
+ * |[15] |CLRRDY |Clear Ready
+ * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data.
+ * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
+ * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
+ * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
+ * | | |This bit is write 1 only and is always 0 when it is read back.
+ */
+ __IO uint32_t CFG;
+ uint32_t RESERVE;
+
+} USBD_EP_T;
+
+typedef struct {
+
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x00 USB Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USB_EN |USB Function Enable
+ * | | |0 = USB Disabled.
+ * | | |1 = USB Enabled.
+ * |[1] |PHY_EN |PHY Transceiver Enable
+ * | | |0 = PHY transceiver Disabled.
+ * | | |1 = PHY transceiver Enabled.
+ * |[2] |PWRDB |Power Down PHY Transceiver, Low Active
+ * | | |0 = Power-down related circuit of PHY transceiver.
+ * | | |1 = Turn-on related circuit of PHY transceiver.
+ * |[3] |DPPU_EN |Pull-Up Resistor On USB_DP Enable
+ * | | |0 = Pull-up resistor in USB_DP bus Disabled.
+ * | | |1 = Pull-up resistor in USB_DP bus will be active.
+ * |[4] |DRVSE0 |Force USB PHY Transceiver To Drive SE0 (Single Ended Zero)
+ * | | |The Single Ended Zero is present when both lines (USB_DP, USB_DM) are being pulled low.
+ * | | |0 = None.
+ * | | |1 = Force USB PHY transceiver to drive SE0.
+ * | | |The default value is "1".
+ * |[8] |RWAKEUP |Remote Wake-Up
+ * | | |0 = Don't force USB bus to K state.
+ * | | |1 = Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up.
+ * |[9] |WAKEUP_EN |Wake-Up Function Enable
+ * | | |0 = USB wake-up function Disabled.
+ * | | |1 = USB wake-up function Enabled.
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * BUSSTS
+ * ===================================================================================================
+ * Offset: 0x04 USB Bus Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBRST |USB Reset Status
+ * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5uS. It is read only.
+ * |[1] |SUSPEND |Suspend Status
+ * | | |1 = Bus idle more than 3 ms, either cable is plugged off or host is sleeping. It is read only.
+ * |[2] |RESUME |Resume Status
+ * | | |1 = Resume from suspend. It is read only.
+ * |[3] |TIMEOUT |Time-Out Flag
+ * | | |1 = Bus no any response more than 18 bits time. It is read only.
+ * |[4] |FLDET |Device Floating Detection
+ * | | |0 = The controller didn't attach into the USB.
+ * | | |1 = When the controller is attached into the USB, this bit will be set as "1".
+ */
+ __I uint32_t BUSSTS;
+
+ /**
+ * INTEN
+ * ===================================================================================================
+ * Offset: 0x08 Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSEVT_IE |Bus Event Interrupt Enable
+ * | | |0 = BUS event interrupt Disabled.
+ * | | |1 = BUS event interrupt Enabled.
+ * |[1] |USBEVT_IE |USB Event Interrupt Enable
+ * | | |0 = USB event interrupt Disabled.
+ * | | |1 = USB event interrupt Enabled.
+ * |[2] |FLDET_IE |Floating Detect Interrupt Enable
+ * | | |0 = Floating detect Interrupt Disabled.
+ * | | |1 = Floating detect Interrupt Enabled.
+ * |[3] |WAKEUP_IE |USB Wake-Up Interrupt Enable
+ * | | |0 = Wake-up Interrupt Disabled.
+ * | | |1 = Wake-up Interrupt Enabled.
+ */
+ __IO uint32_t INTEN;
+
+ /**
+ * INTSTS
+ * ===================================================================================================
+ * Offset: 0x0C Interrupt Event Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUS_STS |BUS Interrupt Status
+ * | | |The BUS event means there is bus suspense or bus resume in the bus.
+ * | | |This bit is used to indicate that there is one of events in the bus.
+ * | | |0 = No BUS event is occurred.
+ * | | |1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0].
+ * |[1] |USB_STS |USB Interrupt Status
+ * | | |The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus.
+ * | | |This bit is used to indicate that there is one of events in the bus.
+ * | | |0 = No USB event is occurred.
+ * | | |1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7.
+ * |[2] |FLD_STS |Floating Interrupt Status
+ * | | |0 = There is not attached event in the USB.
+ * | | |1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2].
+ * |[3] |WKEUP_STS |Wake-Up Interrupt Status
+ * | | |0 = No wake-up event is occurred.
+ * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3].
+ * |[16] |EPEVT0 |USB Event Status On EP0
+ * | | |0 = No event occurred in Endpoint 0.
+ * | | |1 = USB event occurred on Endpoint 0, check USB_EPSTS[11:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [16] or USB_INTSTS [1].
+ * |[17] |EPEVT1 |USB Event Status On EP1
+ * | | |0 = No event occurred in Endpoint 1.
+ * | | |1 = USB event occurred on Endpoint 1, check USB_EPSTS[15:12] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [17] or USB_INTSTS [1].
+ * |[18] |EPEVT2 |USB Event Status On EP2
+ * | | |0 = No event occurred in Endpoint 2.
+ * | | |1 = USB event occurred on Endpoint 2, check USB_EPSTS[19:16] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [18] or USB_INTSTS [1].
+ * |[19] |EPEVT3 |USB Event Status On EP3
+ * | | |0 = No event occurred in Endpoint 3.
+ * | | |1 = USB event occurred on Endpoint 3, check USB_EPSTS[23:20] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [19] or USB_INTSTS [1].
+ * |[20] |EPEVT4 |USB Event Status On EP4
+ * | | |0 = No event occurred in Endpoint 4.
+ * | | |1 = USB event occurred on Endpoint 4, check USB_EPSTS[27:24] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [20] or USB_INTSTS [1].
+ * |[21] |EPEVT5 |USB Event Status On EP5
+ * | | |0 = No event occurred in Endpoint 5.
+ * | | |1 = USB event occurred on Endpoint 5, check USB_EPSTS[31:28] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [21] or USB_INTSTS [1].
+ * |[22] |EPEVT6 |USB Event Status On EP6
+ * | | |0 = No event occurred in Endpoint 6.
+ * | | |1 = USB event occurred on Endpoint 6, check USB_EPSTS2[2:0] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [22] or USB_INTSTS [1].
+ * |[23] |EPEVT7 |USB Event Status On EP7
+ * | | |0 = No event occurred in Endpoint 7.
+ * | | |1 = USB event occurred on Endpoint 7, check USB_EPSTS2[6:4] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [23] or USB_INTSTS [1].
+ * |[31] |SETUP |Setup Event Status
+ * | | |0 = No Setup event.
+ * | | |1 = Setup event occurred, cleared by write "1" to USB_INTSTS[31].
+ */
+ __IO uint32_t INTSTS;
+
+ /**
+ * FADDR
+ * ===================================================================================================
+ * Offset: 0x10 Device 's Function Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |FADDR |USB device's function address
+ */
+ __IO uint32_t FADDR;
+
+ /**
+ * EPSTS
+ * ===================================================================================================
+ * Offset: 0x14 Endpoint Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7] |OVERRUN |Overrun
+ * | | |It means the received data is over the maximum payload number or not.
+ * | | |0 = No overrun.
+ * | | |1 = Out Data more than the Max Payload in MXPLD register or the Setup Data more than 8 Bytes.
+ * |[11:8] |EPSTS0 |Endpoint 0 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |Definition is the same with EPSTS5(USB_EPSTS[27:24]).
+ * |[15:12] |EPSTS1 |Endpoint 1 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |Definition is the same with EPSTS5(USB_EPSTS[27:24]).
+ * |[19:16] |EPSTS2 |Endpoint 2 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |Definition is the same with EPSTS5(USB_EPSTS[27:24]).
+ * |[23:20] |EPSTS3 |Endpoint 3 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |Definition is the same with EPSTS5(USB_EPSTS[27:24]).
+ * |[27:24] |EPSTS4 |Endpoint 4 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |Definition is the same with EPSTS5(USB_EPSTS[27:24]).
+ * |[31:28] |EPSTS5 |Endpoint 5 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |0000 = INACK.
+ * | | |0001 = IN NAK (INTERNAL ONLY).
+ * | | |0010 = OUT Packet Data0 ACK.
+ * | | |0011 = Setup ACK
+ * | | |0110 = OUT Packet Data1 ACK.
+ * | | |0111 = Isochronous transfer end.
+ */
+ __I uint32_t EPSTS;
+
+ /**
+ * BUFSEG
+ * ===================================================================================================
+ * Offset: 0x18 Setup Token Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:3] |BUFSEG |This Register Is Used For Setup Token Only
+ * | | |It is used to define the offset address for the Setup Token with the USB SRAM starting address.
+ * | | |Its physical address is USB_SRAM address + {BUFSEG[5:0], 000} where the USB_SRAM = USB_BASE + 0x100h.
+ */
+ __IO uint32_t BUFSEG;
+
+ /**
+ * EPSTS2
+ * ===================================================================================================
+ * Offset: 0x1C Endpoint Bus Status
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |EPSTS6 |Endpoint 6 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |Definition is the same with EPSTS5(USB_EPSTS[27:24]).
+ * |[6:4] |EPSTS7 |Endpoint 7 Bus Status
+ * | | |These bits are used to show the current status of this endpoint.
+ * | | |Definition is the same with EPSTS5(USB_EPSTS[27:24]).
+ */
+ __I uint32_t EPSTS2;
+
+
+ USBD_EP_T EP[8];
+
+ uint32_t RESERVE0;
+
+ /**
+ * PDMA
+ * ===================================================================================================
+ * Offset: 0xA4 USB PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PDMA_RW |PDMA_RW
+ * | | |0 = The PDMA will read data from memory to USB buffer.
+ * | | |1 = The PDMA will read data from USB buffer to memory.
+ * |[1] |PDMA_TRG |Active PDMA Function
+ * | | |0 = The PDMA function is not active.
+ * | | |1 = The PDMA function in USB is active.
+ * | | |This bit will be automatically cleared after PDMA transfer done.
+ * |[2] |BYTEM |CPU Access USB SRAM Size Mode Select
+ * | | |0 = Word Mode: The size of the transfer from CPU to USB SRAM is Word order.
+ * | | |1 = Byte Mode: The size of the transfer from CPU to USB SRAM is Byte order.
+ * |[3] |PDMA_RST |PDMA Reset
+ * | | |It is used to reset the USB PDMA function into default state.
+ * | | |0 = No Reset PDMA Reset Disable.
+ * | | |1 = Reset the PDMA function in this controller.
+ * | | |Note: it is auto cleared to 0 after the reset function done.
+ */
+ __IO uint32_t PDMA;
+
+} USBD_T;
+
+/**
+ @addtogroup USBD_CONST USBD Bit Field Definition
+ Constant Definitions for USBD Controller
+@{ */
+
+#define USBD_CTL_USB_EN_Pos (0) /*!< USBD_T::CTL: USB_EN Position */
+#define USBD_CTL_USB_EN_Msk (0x1ul << USBD_CTL_USB_EN_Pos) /*!< USBD_T::CTL: USB_EN Mask */
+
+#define USBD_CTL_PHY_EN_Pos (1) /*!< USBD_T::CTL: PHY_EN Position */
+#define USBD_CTL_PHY_EN_Msk (0x1ul << USBD_CTL_PHY_EN_Pos) /*!< USBD_T::CTL: PHY_EN Mask */
+
+#define USBD_CTL_PWRDB_Pos (2) /*!< USBD_T::CTL: PWRDB Position */
+#define USBD_CTL_PWRDB_Msk (0x1ul << USBD_CTL_PWRDB_Pos) /*!< USBD_T::CTL: PWRDB Mask */
+
+#define USBD_CTL_DPPU_EN_Pos (3) /*!< USBD_T::CTL: DPPU_EN Position */
+#define USBD_CTL_DPPU_EN_Msk (0x1ul << USBD_CTL_DPPU_EN_Pos) /*!< USBD_T::CTL: DPPU_EN Mask */
+
+#define USBD_CTL_DRVSE0_Pos (4) /*!< USBD_T::CTL: DRVSE0 Position */
+#define USBD_CTL_DRVSE0_Msk (0x1ul << USBD_CTL_DRVSE0_Pos) /*!< USBD_T::CTL: DRVSE0 Mask */
+
+#define USBD_CTL_RWAKEUP_Pos (8) /*!< USBD_T::CTL: RWAKEUP Position */
+#define USBD_CTL_RWAKEUP_Msk (0x1ul << USBD_CTL_RWAKEUP_Pos) /*!< USBD_T::CTL: RWAKEUP Mask */
+
+#define USBD_CTL_WAKEUP_EN_Pos (9) /*!< USBD_T::CTL: WAKEUP_EN Position */
+#define USBD_CTL_WAKEUP_EN_Msk (0x1ul << USBD_CTL_WAKEUP_EN_Pos) /*!< USBD_T::CTL: WAKEUP_EN Mask */
+
+#define USBD_BUSSTS_USBRST_Pos (0) /*!< USBD_T::BUSSTS: USBRST Position */
+#define USBD_BUSSTS_USBRST_Msk (0x1ul << USBD_BUSSTS_USBRST_Pos) /*!< USBD_T::BUSSTS: USBRST Mask */
+
+#define USBD_BUSSTS_SUSPEND_Pos (1) /*!< USBD_T::BUSSTS: SUSPEND Position */
+#define USBD_BUSSTS_SUSPEND_Msk (0x1ul << USBD_BUSSTS_SUSPEND_Pos) /*!< USBD_T::BUSSTS: SUSPEND Mask */
+
+#define USBD_BUSSTS_RESUME_Pos (2) /*!< USBD_T::BUSSTS: RESUME Position */
+#define USBD_BUSSTS_RESUME_Msk (0x1ul << USBD_BUSSTS_RESUME_Pos) /*!< USBD_T::BUSSTS: RESUME Mask */
+
+#define USBD_BUSSTS_TIMEOUT_Pos (3) /*!< USBD_T::BUSSTS: TIMEOUT Position */
+#define USBD_BUSSTS_TIMEOUT_Msk (0x1ul << USBD_BUSSTS_TIMEOUT_Pos) /*!< USBD_T::BUSSTS: TIMEOUT Mask */
+
+#define USBD_BUSSTS_FLDET_Pos (4) /*!< USBD_T::BUSSTS: FLDET Position */
+#define USBD_BUSSTS_FLDET_Msk (0x1ul << USBD_BUSSTS_FLDET_Pos) /*!< USBD_T::BUSSTS: FLDET Mask */
+
+#define USBD_INTEN_BUSEVT_IE_Pos (0) /*!< USBD_T::INTEN: BUSEVT_IE Position */
+#define USBD_INTEN_BUSEVT_IE_Msk (0x1ul << USBD_INTEN_BUSEVT_IE_Pos) /*!< USBD_T::INTEN: BUSEVT_IE Mask */
+
+#define USBD_INTEN_USBEVT_IE_Pos (1) /*!< USBD_T::INTEN: USBEVT_IE Position */
+#define USBD_INTEN_USBEVT_IE_Msk (0x1ul << USBD_INTEN_USBEVT_IE_Pos) /*!< USBD_T::INTEN: USBEVT_IE Mask */
+
+#define USBD_INTEN_FLDET_IE_Pos (2) /*!< USBD_T::INTEN: FLDET_IE Position */
+#define USBD_INTEN_FLDET_IE_Msk (0x1ul << USBD_INTEN_FLDET_IE_Pos) /*!< USBD_T::INTEN: FLDET_IE Mask */
+
+#define USBD_INTEN_WAKEUP_IE_Pos (3) /*!< USBD_T::INTEN: WAKEUP_IE Position */
+#define USBD_INTEN_WAKEUP_IE_Msk (0x1ul << USBD_INTEN_WAKEUP_IE_Pos) /*!< USBD_T::INTEN: WAKEUP_IE Mask */
+
+#define USBD_INTSTS_BUS_STS_Pos (0) /*!< USBD_T::INTSTS: BUS_STS Position */
+#define USBD_INTSTS_BUS_STS_Msk (0x1ul << USBD_INTSTS_BUS_STS_Pos) /*!< USBD_T::INTSTS: BUS_STS Mask */
+
+#define USBD_INTSTS_USB_STS_Pos (1) /*!< USBD_T::INTSTS: USB_STS Position */
+#define USBD_INTSTS_USB_STS_Msk (0x1ul << USBD_INTSTS_USB_STS_Pos) /*!< USBD_T::INTSTS: USB_STS Mask */
+
+#define USBD_INTSTS_FLD_STS_Pos (2) /*!< USBD_T::INTSTS: FLD_STS Position */
+#define USBD_INTSTS_FLD_STS_Msk (0x1ul << USBD_INTSTS_FLD_STS_Pos) /*!< USBD_T::INTSTS: FLD_STS Mask */
+
+#define USBD_INTSTS_WKEUP_STS_Pos (3) /*!< USBD_T::INTSTS: WKEUP_STS Position */
+#define USBD_INTSTS_WKEUP_STS_Msk (0x1ul << USBD_INTSTS_WKEUP_STS_Pos) /*!< USBD_T::INTSTS: WKEUP_STS Mask */
+
+#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
+#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
+
+#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
+#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
+
+#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
+#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
+
+#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
+#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
+
+#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
+#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
+
+#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
+#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
+
+#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
+#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
+
+#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
+#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
+
+#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
+#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
+
+#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
+#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
+
+#define USBD_EPSTS_OVERRUN_Pos (7) /*!< USBD_T::EPSTS: OVERRUN Position */
+#define USBD_EPSTS_OVERRUN_Msk (0x1ul << USBD_EPSTS_OVERRUN_Pos) /*!< USBD_T::EPSTS: OVERRUN Mask */
+
+#define USBD_EPSTS_EPSTS0_Pos (8) /*!< USBD_T::EPSTS: EPSTS0 Position */
+#define USBD_EPSTS_EPSTS0_Msk (0xful << USBD_EPSTS_EPSTS0_Pos) /*!< USBD_T::EPSTS: EPSTS0 Mask */
+
+#define USBD_EPSTS_EPSTS1_Pos (12) /*!< USBD_T::EPSTS: EPSTS1 Position */
+#define USBD_EPSTS_EPSTS1_Msk (0xful << USBD_EPSTS_EPSTS1_Pos) /*!< USBD_T::EPSTS: EPSTS1 Mask */
+
+#define USBD_EPSTS_EPSTS2_Pos (16) /*!< USBD_T::EPSTS: EPSTS2 Position */
+#define USBD_EPSTS_EPSTS2_Msk (0xful << USBD_EPSTS_EPSTS2_Pos) /*!< USBD_T::EPSTS: EPSTS2 Mask */
+
+#define USBD_EPSTS_EPSTS3_Pos (20) /*!< USBD_T::EPSTS: EPSTS3 Position */
+#define USBD_EPSTS_EPSTS3_Msk (0xful << USBD_EPSTS_EPSTS3_Pos) /*!< USBD_T::EPSTS: EPSTS3 Mask */
+
+#define USBD_EPSTS_EPSTS4_Pos (24) /*!< USBD_T::EPSTS: EPSTS4 Position */
+#define USBD_EPSTS_EPSTS4_Msk (0xful << USBD_EPSTS_EPSTS4_Pos) /*!< USBD_T::EPSTS: EPSTS4 Mask */
+
+#define USBD_EPSTS_EPSTS5_Pos (28) /*!< USBD_T::EPSTS: EPSTS5 Position */
+#define USBD_EPSTS_EPSTS5_Msk (0xful << USBD_EPSTS_EPSTS5_Pos) /*!< USBD_T::EPSTS: EPSTS5 Mask */
+
+#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG: BUFSEG Position */
+#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_T::BUFSEG: BUFSEG Mask */
+
+#define USBD_EPSTS2_EPSTS6_Pos (0) /*!< USBD_T::EPSTS2: EPSTS6 Position */
+#define USBD_EPSTS2_EPSTS6_Msk (0x7ul << USBD_EPSTS2_EPSTS6_Pos) /*!< USBD_T::EPSTS2: EPSTS6 Mask */
+
+#define USBD_EPSTS2_EPSTS7_Pos (4) /*!< USBD_T::EPSTS2: EPSTS7 Position */
+#define USBD_EPSTS2_EPSTS7_Msk (0x7ul << USBD_EPSTS2_EPSTS7_Pos) /*!< USBD_T::EPSTS2: EPSTS7 Mask */
+
+#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_T::BUFSEG: BUFSEG Position */
+#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_T::BUFSEG: BUFSEG Mask */
+
+#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_T::MXPLD: MXPLD Position */
+#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_T::MXPLD: MXPLD Mask */
+
+#define USBD_CFG_EP_NUM_Pos (0) /*!< USBD_T::CFG: EP_NUM Position */
+#define USBD_CFG_EP_NUM_Msk (0xful << USBD_CFG_EP_NUM_Pos) /*!< USBD_T::CFG: EP_NUM Mask */
+
+#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_T::CFG: ISOCH Position */
+#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_T::CFG: ISOCH Mask */
+
+#define USBD_CFG_EPMODE_Pos (5) /*!< USBD_T::CFG: EPMODE Position */
+#define USBD_CFG_EPMODE_Msk (0x3ul << USBD_CFG_EPMODE_Pos) /*!< USBD_T::CFG: EPMODE Mask */
+
+#define USBD_CFG_DSQ_SYNC_Pos (7) /*!< USBD_T::CFG: DSQ_SYNC Position */
+#define USBD_CFG_DSQ_SYNC_Msk (0x1ul << USBD_CFG_DSQ_SYNC_Pos) /*!< USBD_T::CFG: DSQ_SYNC Mask */
+
+#define USBD_CFG_CSTALL_Pos (8) /*!< USBD_T::CFG: CSTALL Position */
+#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_T::CFG: CSTALL Mask */
+
+#define USBD_CFG_SSTALL_Pos (9) /*!< USBD_T::CFG: SSTALL Position */
+#define USBD_CFG_SSTALL_Msk (0x1ul << USBD_CFG_SSTALL_Pos) /*!< USBD_T::CFG: SSTALL Mask */
+
+#define USBD_CFG_CLRRDY_Pos (15) /*!< USBD_T::CFG: CLRRDY Position */
+#define USBD_CFG_CLRRDY_Msk (0x1ul << USBD_CFG_CLRRDY_Pos) /*!< USBD_T::CFG: CLRRDY Mask */
+
+#define USBD_PDMA_PDMA_RW_Pos (0) /*!< USBD_T::PDMA: PDMA_RW Position */
+#define USBD_PDMA_PDMA_RW_Msk (0x1ul << USBD_PDMA_PDMA_RW_Pos) /*!< USBD_T::PDMA: PDMA_RW Mask */
+
+#define USBD_PDMA_PDMA_TRG_Pos (1) /*!< USBD_T::PDMA: PDMA_TRG Position */
+#define USBD_PDMA_PDMA_TRG_Msk (0x1ul << USBD_PDMA_PDMA_TRG_Pos) /*!< USBD_T::PDMA: PDMA_TRG Mask */
+
+#define USBD_PDMA_BYTEM_Pos (2) /*!< USBD_T::PDMA: BYTEM Position */
+#define USBD_PDMA_BYTEM_Msk (0x1ul << USBD_PDMA_BYTEM_Pos) /*!< USBD_T::PDMA: BYTEM Mask */
+
+#define USBD_PDMA_PDMA_RST_Pos (3) /*!< USBD_T::PDMA: PDMA_RST Position */
+#define USBD_PDMA_PDMA_RST_Msk (0x1ul << USBD_PDMA_PDMA_RST_Pos) /*!< USBD_T::PDMA: PDMA_RST Mask */
+
+/**@}*/ /* USBD_CONST */
+/**@}*/ /* end of USBD register group */
+
+
+/*---------------------- Watch Dog Timer Controller -------------------------*/
+/**
+ @addtogroup WDT Watch Dog Timer Controller(WDT)
+ Memory Mapped Structure for WDT Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * CTL
+ * ===================================================================================================
+ * Offset: 0x00 Watchdog Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WTR |Clear Watchdog Timer
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Set this bit will clear the Watchdog timer.
+ * | | |0 = No effect.
+ * | | |1 = Reset the contents of the Watchdog timer.
+ * | | |Note: This bit will be auto cleared after few clock cycles.
+ * |[1] |WTRE |Watchdog Timer Reset Function Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Setting this bit will enable the Watchdog timer reset function.
+ * | | |0 = Watchdog timer reset function Disabled.
+ * | | |1 = Watchdog timer reset function Enabled.
+ * |[2] |WTWKE |Watchdog Timer Wake-Up Function Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Watchdog timer Wake-up CPU function Disabled.
+ * | | |1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from power-down mode.
+ * |[3] |WTE |Watchdog Timer Enable
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Watchdog timer Disabled (this action will reset the internal counter).
+ * | | |1 = Watchdog timer Enabled.
+ * |[6:4] |WTIS |Watchdog Timer Interval Selection
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |These three bits select the time-out interval for the Watchdog timer.
+ * | | |This count is free running counter.
+ * | | |Please refer to the Table 5-16.
+ * |[9:8] |WTRDSEL |Watchdog Timer Reset Delay Select
+ * | | |When watchdog timeout happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened.
+ * | | |Software can select a suitable value of watchdog reset delay period for different watchdog timeout period.
+ * | | |00 = Watchdog reset delay period is 1026 watchdog clock
+ * | | |01 = Watchdog reset delay period is 130 watchdog clock
+ * | | |10 = Watchdog reset delay period is 18 watchdog clock
+ * | | |11 = Watchdog reset delay period is 3 watchdog clock
+ * | | |This register will be reset if watchdog reset happened
+ */
+ __IO uint32_t CTL;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x04 Watchdog Timer Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WDT_IE |Watchdog Timer Interrupt Enable
+ * | | |0 = Watchdog timer interrupt Disabled.
+ * | | |1 = Watchdog timer interrupt Enabled.
+ */
+ __IO uint32_t IER;
+
+ /**
+ * ISR
+ * ===================================================================================================
+ * Offset: 0x08 Watchdog Timer Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IS |Watchdog Timer Interrupt Status
+ * | | |If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.
+ * | | |If the Watchdog timer interrupt is not enabled, then this bit indicates that a time-out period has elapsed.
+ * | | |0 = Watchdog timer interrupt did not occur.
+ * | | |1 = Watchdog timer interrupt occurs.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[1] |RST_IS |Watchdog Timer Reset Status
+ * | | |When the Watchdog timer initiates a reset, the hardware will set this bit.
+ * | | |This flag can be read by software to determine the source of reset.
+ * | | |Software is responsible to clear it manually by writing "1" to it.
+ * | | |If WTRE is disabled, then the Watchdog timer has no effect on this bit.
+ * | | |0 = Watchdog timer reset did not occur.
+ * | | |1 = Watchdog timer reset occurs.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[2] |WAKE_IS |Watchdog Timer Wake-Up Status
+ * | | |If Watchdog timer causes system to wake up from power-down mode, this bit will be set to high.
+ * | | |It must be cleared by software with a write "1" to this bit.
+ * | | |0 = Watchdog timer does not cause system wake-up.
+ * | | |1 = Wake system up from power-down mode by Watchdog time-out.
+ * | | |Note1: When system in power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS.
+ * | | |Note2: After one engine clock, this bit can be cleared by writing "1" to it
+ */
+ __IO uint32_t ISR;
+
+} WDT_T;
+
+/**
+ @addtogroup WDT_CONST WDT Bit Field Definition
+ Constant Definitions for WDT Controller
+@{ */
+
+#define WDT_CTL_WTR_Pos (0) /*!< WDT_T::CTL: WTR Position */
+#define WDT_CTL_WTR_Msk (0x1ul << WDT_CTL_WTR_Pos) /*!< WDT_T::CTL: WTR Mask */
+
+#define WDT_CTL_WTRE_Pos (1) /*!< WDT_T::CTL: WTRE Position */
+#define WDT_CTL_WTRE_Msk (0x1ul << WDT_CTL_WTRE_Pos) /*!< WDT_T::CTL: WTRE Mask */
+
+#define WDT_CTL_WTWKE_Pos (2) /*!< WDT_T::CTL: WTWKE Position */
+#define WDT_CTL_WTWKE_Msk (0x1ul << WDT_CTL_WTWKE_Pos) /*!< WDT_T::CTL: WTWKE Mask */
+
+#define WDT_CTL_WTE_Pos (3) /*!< WDT_T::CTL: WTE Position */
+#define WDT_CTL_WTE_Msk (0x1ul << WDT_CTL_WTE_Pos) /*!< WDT_T::CTL: WTE Mask */
+
+#define WDT_CTL_WTIS_Pos (4) /*!< WDT_T::CTL: WTIS Position */
+#define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos) /*!< WDT_T::CTL: WTIS Mask */
+
+#define WDT_CTL_WTRDSEL_Pos (8) /*!< WDT_T::CTL: WTRDSEL Position */
+#define WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos) /*!< WDT_T::CTL: WTRDSEL Mask */
+
+#define WDT_IER_IE_Pos (0) /*!< WDT_T::IER: IE Position */
+#define WDT_IER_IE_Msk (0x1ul << WDT_IER_IE_Pos) /*!< WDT_T::IER: IE Mask */
+
+#define WDT_ISR_IS_Pos (0) /*!< WDT_T::ISR: IS Position */
+#define WDT_ISR_IS_Msk (0x1ul << WDT_ISR_IS_Pos) /*!< WDT_T::ISR: IS Mask */
+
+#define WDT_ISR_RST_IS_Pos (1) /*!< WDT_T::ISR: RST_IS Position */
+#define WDT_ISR_RST_IS_Msk (0x1ul << WDT_ISR_RST_IS_Pos) /*!< WDT_T::ISR: RST_IS Mask */
+
+#define WDT_ISR_WAKE_IS_Pos (2) /*!< WDT_T::ISR: WAKE_IS Position */
+#define WDT_ISR_WAKE_IS_Msk (0x1ul << WDT_ISR_WAKE_IS_Pos) /*!< WDT_T::ISR: WAKE_IS Mask */
+
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* end of WDT register group */
+
+
+/*---------------------- Window Watchdog Timer -------------------------*/
+/**
+ @addtogroup WWDT Window Watchdog Timer(WWDT)
+ Memory Mapped Structure for WWDT Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * RLD
+ * ===================================================================================================
+ * Offset: 0x00 Window Watchdog Timer Reload Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RLD |Window Watchdog Timer Reload Counter Register
+ * | | |Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
+ * | | |Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP.
+ * | | |If SW writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal.
+ */
+ __O uint32_t RLD;
+
+ /**
+ * CR
+ * ===================================================================================================
+ * Offset: 0x04 Window Watchdog Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTEN |Window Watchdog Enable
+ * | | |Set this bit to enable Window Watchdog timer.
+ * | | |0 = Window Watchdog timer function Disabled.
+ * | | |1 = Window Watchdog timer function Enabled.
+ * |[11:8] |PERIODSEL |WWDT Pre-Scale Period Select
+ * | | |These three bits select the pre-scale for the WWDT counter period.
+ * | | |Please refer to Table 5-17
+ * |[21:16] |WINCMP |WWDT Window Compare Register
+ * | | |Set this register to adjust the valid reload window.
+ * | | |Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP.
+ * | | |If SW writes WWDTRLD when WWDT counter value larger than WWCMP, WWDT will generate RESET signal.
+ * |[31] |DBGEN |WWDT Debug Enable
+ * | | |0 = WWDT stopped count if system is in Debug mode.
+ * | | |1 = WWDT still counted even system is in Debug mode.
+ */
+ __IO uint32_t CR;
+
+ /**
+ * IER
+ * ===================================================================================================
+ * Offset: 0x08 Window Watchdog Timer Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTIE |WWDT Interrupt Enable
+ * | | |Setting this bit will enable the Watchdog timer interrupt function.
+ * | | |0 = Watchdog timer interrupt function Disabled.
+ * | | |1 = Watchdog timer interrupt function Enabled.
+ */
+ __IO uint32_t IER;
+
+ /**
+ * STS
+ * ===================================================================================================
+ * Offset: 0x0C Window Watchdog Timer Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IF |WWDT Compare Match Interrupt Flag
+ * | | |When WWCMP match the WWDT counter, then this bit is set to 1.
+ * | | |This bit will be cleared by software write 1 to this bit.
+ * |[1] |RF |WWDT Reset Flag
+ * | | |When WWDT counter down count to 0 or write WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1.
+ * | | |Software can write 1 to clear this bit to 0.
+ */
+ __IO uint32_t STS;
+
+ /**
+ * WWDTVAL
+ * ===================================================================================================
+ * Offset: 0x10 Window Watchdog Timer Counter Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |VAL |WWDT Counter Value
+ * | | |This register reflects the counter value of window watchdog. This register is read only
+ */
+ __I uint32_t VAL;
+
+} WWDT_T;
+
+/**
+ @addtogroup WWDT_CONST WWDT Bit Field Definition
+ Constant Definitions for WWDT Controller
+@{ */
+
+#define WWDT_RLD_WWDTRLD_Pos (0) /*!< WWDT_T::RLD: RLD Position */
+#define WWDT_RLD_WWDTRLD_Msk (0xfffffffful << WWDT_RLD_RLD_Pos) /*!< WWDT_T::RLD: RLD Mask */
+
+#define WWDT_CR_WWDTEN_Pos (0) /*!< WWDT_T::CR: WWDTEN Position */
+#define WWDT_CR_WWDTEN_Msk (0x1ul << WWDT_CR_WWDTEN_Pos) /*!< WWDT_T::CR: WWDTEN Mask */
+
+#define WWDT_CR_PERIODSEL_Pos (8) /*!< WWDT_T::CR: PERIODSEL Position */
+#define WWDT_CR_PERIODSEL_Msk (0xful << WWDT_CR_PERIODSEL_Pos) /*!< WWDT_T::CR: PERIODSEL Mask */
+
+#define WWDT_CR_WINCMP_Pos (16) /*!< WWDT_T::CR: WINCMP Position */
+#define WWDT_CR_WINCMP_Msk (0x3ful << WWDT_CR_WINCMP_Pos) /*!< WWDT_T::CR: WINCMP Mask */
+
+#define WWDT_CR_DBGEN_Pos (31) /*!< WWDT_T::CR: DBGEN Position */
+#define WWDT_CR_DBGEN_Msk (0x1ul << WWDT_CR_DBGEN_Pos) /*!< WWDT_T::CR: DBGEN Mask */
+
+#define WWDT_IER_WWDTIE_Pos (0) /*!< WWDT_T::IER: WWDTIE Position */
+#define WWDT_IER_WWDTIE_Msk (0x1ul << WWDT_IER_WWDTIE_Pos) /*!< WWDT_T::IER: WWDTIE Mask */
+
+#define WWDT_STS_IF_Pos (0) /*!< WWDT_T::STS: IF Position */
+#define WWDT_STS_IF_Msk (0x1ul << WWDT_STS_IF_Pos) /*!< WWDT_T::STS: IF Mask */
+
+#define WWDT_STS_RF_Pos (1) /*!< WWDT_T::STS: RF Position */
+#define WWDT_STS_RF_Msk (0x1ul << WWDT_STS_RF_Pos) /*!< WWDT_T::STS: RF Mask */
+
+#define WWDT_VAL_WWDTVAL_Pos (0) /*!< WWDT_T::VAL: WWDTVAL Position */
+#define WWDT_VAL_WWDTVAL_Msk (0x3ful << WWDT_VAL_WWDTVAL_Pos) /*!< WWDT_T::VAL: WWDTVAL Mask */
+
+/**@}*/ /* WWDT_CONST */
+/**@}*/ /* end of WWDT register group */
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/** @addtogroup NANO100_PERIPHERAL_MEM_MAP NANO100 Peripheral Memory Map
+ Memory Mapped Structure for NANO100 Series Peripheral
+ @{
+ */
+/*!<Peripheral and SRAM base address */
+#define FLASH_BASE ((uint32_t)0x00000000) ///< Flash base address
+#define SRAM_BASE ((uint32_t)0x20000000) ///< SRAM base address
+#define APB1PERIPH_BASE ((uint32_t)0x40000000) ///< APB1 base address
+#define APB2PERIPH_BASE ((uint32_t)0x40100000) ///< APB2 base address
+#define AHBPERIPH_BASE ((uint32_t)0x50000000) ///< AHB base address
+
+/*!<Peripheral memory map */
+
+#define WDT_BASE (APB1PERIPH_BASE + 0x04000) ///< WDT register base address
+#define WWDT_BASE (APB1PERIPH_BASE + 0x04100) ///< WWDT register base address
+#define RTC_BASE (APB1PERIPH_BASE + 0x08000) ///< RTC register base address
+#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000) ///< TIMER0 register base address
+#define TIMER1_BASE (APB1PERIPH_BASE + 0x10100) ///< TIMER1 register base address
+#define I2C0_BASE (APB1PERIPH_BASE + 0x20000) ///< I2C0 register base address
+#define SPI0_BASE (APB1PERIPH_BASE + 0x30000) ///< SPI0 register base address
+#define PWM0_BASE (APB1PERIPH_BASE + 0x40000) ///< PWM0 register base address
+#define UART0_BASE (APB1PERIPH_BASE + 0x50000) ///< UART0 register base address
+#define DAC_BASE (APB1PERIPH_BASE + 0xA0000) ///< DAC register base address
+#define LCD_BASE (APB1PERIPH_BASE + 0xB0000) ///< LCD register base address
+#define SPI2_BASE (APB1PERIPH_BASE + 0xD0000) ///< SPI2 register base address
+#define ADC_BASE (APB1PERIPH_BASE + 0xE0000) ///< ADC register base address
+
+#define TIMER2_BASE (APB2PERIPH_BASE + 0x10000) ///< TIMER2 register base address
+#define TIMER3_BASE (APB2PERIPH_BASE + 0x10100) ///< TIMER3 register base address
+#define SHADOW_BASE (APB1PERIPH_BASE + 0x10200) ///< GPIO shadow register base address
+#define I2C1_BASE (APB2PERIPH_BASE + 0x20000) ///< I2C1 register base address
+#define SPI1_BASE (APB2PERIPH_BASE + 0x30000) ///< SPI1 register base address
+#define PWM1_BASE (APB2PERIPH_BASE + 0x40000) ///< PWM1 register base address
+#define UART1_BASE (APB2PERIPH_BASE + 0x50000) ///< UART1 register base address
+#define USBD_BASE (APB1PERIPH_BASE + 0x60000) ///< USBD register base address
+#define SC0_BASE (APB2PERIPH_BASE + 0x90000) ///< SC0 register base address
+#define I2S_BASE (APB2PERIPH_BASE + 0xA0000) ///< I2S register base address
+#define SC1_BASE (APB2PERIPH_BASE + 0xB0000) ///< SC1 register base address
+#define SC2_BASE (APB2PERIPH_BASE + 0xC0000) ///< SC2 register base address
+
+#define SYS_BASE (AHBPERIPH_BASE + 0x00000) ///< SYS register base address
+#define CLK_BASE (AHBPERIPH_BASE + 0x00200) ///< CLK register base address
+#define INT_BASE (AHBPERIPH_BASE + 0x00300) ///< INT register base address
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000) ///< GPIO port A register base address
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040) ///< GPIO port B register base address
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080) ///< GPIO port C register base address
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) ///< GPIO port D register base address
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100) ///< GPIO port E register base address
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140) ///< GPIO port F register base address
+#define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) ///< GPIO debounce register base address
+#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) ///< GPIO bit access register base address
+#define VDMA_BASE (AHBPERIPH_BASE + 0x08000) ///< VDMA register base address
+#define PDMA1_BASE (AHBPERIPH_BASE + 0x08100) ///< PDMA1 register base address
+#define PDMA2_BASE (AHBPERIPH_BASE + 0x08200) ///< PDMA2 register base address
+#define PDMA3_BASE (AHBPERIPH_BASE + 0x08300) ///< PDMA3 register base address
+#define PDMA4_BASE (AHBPERIPH_BASE + 0x08400) ///< PDMA4 register base address
+#define PDMA5_BASE (AHBPERIPH_BASE + 0x08500) ///< PDMA5 register base address
+#define PDMA6_BASE (AHBPERIPH_BASE + 0x08600) ///< PDMA6 register base address
+#define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00) ///< PDMA global control register base address
+#define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) ///< PDMA CRC register base address
+#define FMC_BASE (AHBPERIPH_BASE + 0x0C000) ///< FMC register base address
+#define EBI_BASE (AHBPERIPH_BASE + 0x10000) ///< EBI register base address
+
+/*@}*/ /* end of group NANO100_PERIPHERAL_MEM_MAP */
+
+
+/** @addtogroup NANO100_PERIPHERAL_DECLARATION NANO100 Peripheral Declaration
+ The Declaration of NANO100 Series Peripheral
+ @{
+ */
+#define WDT ((WDT_T *) WDT_BASE) ///< Pointer to WDT register structure
+#define WWDT ((WWDT_T *) WWDT_BASE) ///< Pointer to WWDT register structure
+#define RTC ((RTC_T *) RTC_BASE) ///< Pointer to RTC register structure
+#define TIMER0 ((TIMER_T *) TIMER0_BASE) ///< Pointer to TIMER0 register structure
+#define TIMER1 ((TIMER_T *) TIMER1_BASE) ///< Pointer to TIMER1 register structure
+#define TIMER2 ((TIMER_T *) TIMER2_BASE) ///< Pointer to TIMER2 register structure
+#define TIMER3 ((TIMER_T *) TIMER3_BASE) ///< Pointer to TIMER3 register structure
+#define SHADOW ((SHADOW_T *) SHADOW_BASE) ///< Pointer to GPIO shadow register structure
+#define I2C0 ((I2C_T *) I2C0_BASE) ///< Pointer to I2C0 register structure
+#define I2C1 ((I2C_T *) I2C1_BASE) ///< Pointer to I2C1 register structure
+#define SPI0 ((SPI_T *) SPI0_BASE) ///< Pointer to SPI0 register structure
+#define SPI1 ((SPI_T *) SPI1_BASE) ///< Pointer to SPI1 register structure
+#define SPI2 ((SPI_T *) SPI2_BASE) ///< Pointer to SPI2 register structure
+#define PWM0 ((PWM_T *) PWM0_BASE) ///< Pointer to PWM0 register structure
+#define PWM1 ((PWM_T *) PWM1_BASE) ///< Pointer to PWM1 register structure
+#define UART0 ((UART_T *) UART0_BASE) ///< Pointer to UART0 register structure
+#define UART1 ((UART_T *) UART1_BASE) ///< Pointer to UART1 register structure
+#define LCD ((LCD_T *) LCD_BASE) ///< Pointer to LCD register structure
+#define ADC ((ADC_T *) ADC_BASE) ///< Pointer to ADC register structure
+#define SC0 ((SC_T *) SC0_BASE) ///< Pointer to SC0 register structure
+#define SC1 ((SC_T *) SC1_BASE) ///< Pointer to SC1 register structure
+#define SC2 ((SC_T *) SC2_BASE) ///< Pointer to SC2 register structure
+#define USBD ((USBD_T *) USBD_BASE) ///< Pointer to USBD register structure
+#define I2S ((I2S_T *) I2S_BASE) ///< Pointer to I2S register structure
+#define DAC ((DAC_T *) DAC_BASE) ///< Pointer to DAC register structure
+
+#define SYS ((SYS_T *) SYS_BASE) ///< Pointer to SYS register structure
+#define CLK ((CLK_T *) CLK_BASE) ///< Pointer to CLK register structure
+#define INTR ((INTR_T *) INTID_BASE) ///< Pointer to INTR register structure
+#define PA ((GPIO_T *) GPIOA_BASE) ///< Pointer to GPIO port A register structure
+#define PB ((GPIO_T *) GPIOB_BASE) ///< Pointer to GPIO port B register structure
+#define PC ((GPIO_T *) GPIOC_BASE) ///< Pointer to GPIO port C register structure
+#define PD ((GPIO_T *) GPIOD_BASE) ///< Pointer to GPIO port D register structure
+#define PE ((GPIO_T *) GPIOE_BASE) ///< Pointer to GPIO port E register structure
+#define PF ((GPIO_T *) GPIOF_BASE) ///< Pointer to GPIO port F register structure
+#define GPIO ((GP_DB_T *) GPIODBNCE_BASE) ///< Pointer to GPIO debounce register structure
+#define VDMA ((VDMA_T *) VDMA_BASE) ///< Pointer to VDMA register structure
+#define PDMA1 ((PDMA_T *) PDMA1_BASE) ///< Pointer to PDMA1 register structure
+#define PDMA2 ((PDMA_T *) PDMA2_BASE) ///< Pointer to PDMA2 register structure
+#define PDMA3 ((PDMA_T *) PDMA3_BASE) ///< Pointer to PDMA3 register structure
+#define PDMA4 ((PDMA_T *) PDMA4_BASE) ///< Pointer to PDMA4 register structure
+#define PDMA5 ((PDMA_T *) PDMA5_BASE) ///< Pointer to PDMA5 register structure
+#define PDMA6 ((PDMA_T *) PDMA6_BASE) ///< Pointer to PDMA6 register structure
+#define PDMACRC ((DMA_CRC_T *) PDMACRC_BASE) ///< Pointer to PDMA CRC register structure
+#define PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE) ///< Pointer to PDMA global control register structure
+#define FMC ((FMC_T *) FMC_BASE) ///< Pointer to FMC register structure
+#define EBI ((EBI_T *) EBI_BASE) ///< Pointer to EBI register structure
+
+/*@}*/ /* end of group NANO100_PERIPHERAL_DECLARATION */
+
+/*@}*/ /* end of group NANO100_Peripherals */
+
+/** @addtogroup NANO100_IO_ROUTINE NANO100 I/O Routines
+ The Declaration of NANO100 I/O Routines
+ @{
+ */
+
+typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
+typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
+typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
+
+/**
+ * @brief Get a 8-bit unsigned value from specified address
+ * @param[in] addr Address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified address
+ */
+#define M8(addr) (*((vu8 *) (addr)))
+
+/**
+ * @brief Get a 16-bit unsigned value from specified address
+ * @param[in] addr Address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified address
+ * @note The input address must be 16-bit aligned
+ */
+#define M16(addr) (*((vu16 *) (addr)))
+
+/**
+ * @brief Get a 32-bit unsigned value from specified address
+ * @param[in] addr Address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified address
+ * @note The input address must be 32-bit aligned
+ */
+#define M32(addr) (*((vu32 *) (addr)))
+
+/**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+#define outpw(port,value) *((volatile unsigned int *)(port)) = value
+
+/**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+#define inpw(port) (*((volatile unsigned int *)(port)))
+
+/**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+#define outps(port,value) *((volatile unsigned short *)(port)) = value
+
+/**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+#define inps(port) (*((volatile unsigned short *)(port)))
+
+/**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+#define outpb(port,value) *((volatile unsigned char *)(port)) = value
+
+/**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+#define inpb(port) (*((volatile unsigned char *)(port)))
+
+/**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+#define outp32(port,value) *((volatile unsigned int *)(port)) = value
+
+/**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+#define inp32(port) (*((volatile unsigned int *)(port)))
+
+/**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+#define outp16(port,value) *((volatile unsigned short *)(port)) = value
+
+/**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+#define inp16(port) (*((volatile unsigned short *)(port)))
+
+/**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+#define outp8(port,value) *((volatile unsigned char *)(port)) = value
+
+/**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+#define inp8(port) (*((volatile unsigned char *)(port)))
+
+/*@}*/ /* end of group NANO100_IO_ROUTINE */
+
+/******************************************************************************/
+/* Legacy Constants */
+/******************************************************************************/
+/** @addtogroup NANO100_legacy_Constants NANO100 Legacy Constants
+ NANO100 Legacy Constants
+ @{
+*/
+
+#ifndef NULL
+#define NULL (0) ///< NULL pointer
+#endif
+
+#define TRUE (1) ///< Boolean true, define to use in API parameters or return value
+#define FALSE (0) ///< Boolean false, define to use in API parameters or return value
+
+#define ENABLE (1) ///< Enable, define to use in API parameters
+#define DISABLE (0) ///< Disable, define to use in API parameters
+
+/* Define one bit mask */
+#define BIT0 (0x00000001) ///< Bit 0 mask of an 32 bit integer
+#define BIT1 (0x00000002) ///< Bit 1 mask of an 32 bit integer
+#define BIT2 (0x00000004) ///< Bit 2 mask of an 32 bit integer
+#define BIT3 (0x00000008) ///< Bit 3 mask of an 32 bit integer
+#define BIT4 (0x00000010) ///< Bit 4 mask of an 32 bit integer
+#define BIT5 (0x00000020) ///< Bit 5 mask of an 32 bit integer
+#define BIT6 (0x00000040) ///< Bit 6 mask of an 32 bit integer
+#define BIT7 (0x00000080) ///< Bit 7 mask of an 32 bit integer
+#define BIT8 (0x00000100) ///< Bit 8 mask of an 32 bit integer
+#define BIT9 (0x00000200) ///< Bit 9 mask of an 32 bit integer
+#define BIT10 (0x00000400) ///< Bit 10 mask of an 32 bit integer
+#define BIT11 (0x00000800) ///< Bit 11 mask of an 32 bit integer
+#define BIT12 (0x00001000) ///< Bit 12 mask of an 32 bit integer
+#define BIT13 (0x00002000) ///< Bit 13 mask of an 32 bit integer
+#define BIT14 (0x00004000) ///< Bit 14 mask of an 32 bit integer
+#define BIT15 (0x00008000) ///< Bit 15 mask of an 32 bit integer
+#define BIT16 (0x00010000) ///< Bit 16 mask of an 32 bit integer
+#define BIT17 (0x00020000) ///< Bit 17 mask of an 32 bit integer
+#define BIT18 (0x00040000) ///< Bit 18 mask of an 32 bit integer
+#define BIT19 (0x00080000) ///< Bit 19 mask of an 32 bit integer
+#define BIT20 (0x00100000) ///< Bit 20 mask of an 32 bit integer
+#define BIT21 (0x00200000) ///< Bit 21 mask of an 32 bit integer
+#define BIT22 (0x00400000) ///< Bit 22 mask of an 32 bit integer
+#define BIT23 (0x00800000) ///< Bit 23 mask of an 32 bit integer
+#define BIT24 (0x01000000) ///< Bit 24 mask of an 32 bit integer
+#define BIT25 (0x02000000) ///< Bit 25 mask of an 32 bit integer
+#define BIT26 (0x04000000) ///< Bit 26 mask of an 32 bit integer
+#define BIT27 (0x08000000) ///< Bit 27 mask of an 32 bit integer
+#define BIT28 (0x10000000) ///< Bit 28 mask of an 32 bit integer
+#define BIT29 (0x20000000) ///< Bit 29 mask of an 32 bit integer
+#define BIT30 (0x40000000) ///< Bit 30 mask of an 32 bit integer
+#define BIT31 (0x80000000) ///< Bit 31 mask of an 32 bit integer
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk (0x000000FF) ///< Mask to get bit0~bit7 from a 32 bit integer
+#define BYTE1_Msk (0x0000FF00) ///< Mask to get bit8~bit15 from a 32 bit integer
+#define BYTE2_Msk (0x00FF0000) ///< Mask to get bit16~bit23 from a 32 bit integer
+#define BYTE3_Msk (0xFF000000) ///< Mask to get bit24~bit31 from a 32 bit integer
+
+#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
+#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
+#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+/*@}*/ /* end of group NANO100_legacy_Constants */
+
+/*@}*/ /* end of group NANO100_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/******************************************************************************/
+/* Peripheral header files */
+/******************************************************************************/
+#include "nano100_sys.h"
+#include "nano100_clk.h"
+#include "nano100_adc.h"
+#include "nano100_dac.h"
+#include "nano100_fmc.h"
+#include "nano100_ebi.h"
+#include "nano100_gpio.h"
+#include "nano100_i2c.h"
+#include "nano100_crc.h"
+#include "nano100_pdma.h"
+#include "nano100_pwm.h"
+#include "nano100_rtc.h"
+#include "nano100_sc.h"
+#include "nano100_scuart.h"
+#include "nano100_spi.h"
+#include "nano100_timer.h"
+#include "nano100_uart.h"
+#include "nano100_usbd.h"
+#include "nano100_wdt.h"
+#include "nano100_wwdt.h"
+#include "nano100_i2s.h"
+#include "nano100_lcd.h"
+
+#endif // __NANO100SERIES_H__
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_adc.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,202 @@
+/**************************************************************************//**
+ * @file adc.c
+ * @version V1.00
+ * $Revision: 7 $
+ * $Date: 14/10/06 6:00p $
+ * @brief NANO100 series ADC driver source file
+ *
+ * @note
+ * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_ADC_Driver ADC Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This API configures ADC module to be ready for convert the input from selected channel
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32InputMode Input mode (single-end/differential). Valid values are:
+ * - \ref ADC_INPUT_MODE_SINGLE_END
+ * - \ref ADC_INPUT_MODE_DIFFERENTIAL
+ * @param[in] u32OpMode Operation mode (single/single cycle/continuous). Valid values are:
+ * - \ref ADC_OPERATION_MODE_SINGLE
+ * - \ref ADC_OPERATION_MODE_SINGLE_CYCLE
+ * - \ref ADC_OPERATION_MODE_CONTINUOUS
+ * @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @note This API does not turn on ADC power nor does trigger ADC conversion
+ */
+void ADC_Open(ADC_T *adc,
+ uint32_t u32InputMode,
+ uint32_t u32OpMode,
+ uint32_t u32ChMask)
+{
+
+ ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32InputMode;
+ ADC->CR = (ADC->CR & ~ADC_CR_ADMD_Msk) | u32OpMode;
+ ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk);
+ ADC->CHEN = u32ChMask;
+ return;
+}
+
+/**
+ * @brief Disable ADC module
+ * @param[in] adc Base address of ADC module
+ * @return None
+ */
+void ADC_Close(ADC_T *adc)
+{
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_ADC_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_ADC_RST_Msk;
+ return;
+
+}
+
+/**
+ * @brief Configure the hardware trigger condition and enable hardware trigger
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Source Decides the hardware trigger source. Valid values are:
+ * - \ref ADC_TRIGGER_BY_EXT_PIN
+ * @param[in] u32Param While ADC trigger by external pin, this parameter
+ * is used to set trigger condition. Valid values are:
+ * - \ref ADC_LOW_LEVEL_TRIGGER
+ * - \ref ADC_HIGH_LEVEL_TRIGGER
+ * - \ref ADC_FALLING_EDGE_TRIGGER
+ * - \ref ADC_RISING_EDGE_TRIGGER
+ * @return None
+ */
+void ADC_EnableHWTrigger(ADC_T *adc,
+ uint32_t u32Source,
+ uint32_t u32Param)
+{
+ ADC->CR &= ~(ADC_CR_TRGE_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGS_Msk);
+ ADC->CR |= u32Source | u32Param | ADC_CR_TRGE_Msk;
+ return;
+}
+
+/**
+ * @brief Disable hardware trigger ADC function.
+ * @param[in] adc Base address of ADC module
+ * @return None
+ */
+void ADC_DisableHWTrigger(ADC_T *adc)
+{
+ ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk);
+ return;
+}
+
+/**
+ * @brief Config and enable timer trigger
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Source Decides which timer trigger ADC. Valid values are: 0 ~ 3
+ * @param[in] u32PDMACnt When timer event occurred, PDMA will transfer u32PDMACnt+1 ADC result
+ * @return None
+ */
+void ADC_EnableTimerTrigger(ADC_T *adc,
+ uint32_t u32Source,
+ uint32_t u32PDMACnt)
+{
+ ADC->CR &= ~(ADC_CR_TMPDMACNT_Msk | ADC_CR_TMSEL_Msk);
+ ADC->CR |= (u32PDMACnt << ADC_CR_TMPDMACNT_Pos) | (u32Source << ADC_CR_TMSEL_Pos) | ADC_CR_TMTRGMOD_Msk;
+
+ return;
+}
+
+/**
+ * @brief Disable timer trigger ADC function.
+ * @param[in] adc Base address of ADC module
+ * @return None
+ */
+void ADC_DisableTimerTrigger(ADC_T *adc)
+{
+ ADC->CR &= ~ADC_CR_TMTRGMOD_Msk;
+
+ return;
+}
+
+/**
+ * @brief Configure the extended sampling time
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32ChNum The channel number
+ * @param[in] u32SampleTime Decides the extend sampling counter. Valid values are 0 ~ 15
+ * @return None
+ */
+void ADC_SetExtraSampleTime(ADC_T *adc,
+ uint32_t u32ChNum,
+ uint32_t u32SampleTime)
+{
+
+ if (u32ChNum < 8)
+ ADC->SMPLCNT0 = (ADC->SMPLCNT0 & ~(ADC_SMPLCNT0_CH0SAMPCNT_Msk << (u32ChNum * 4))) | (u32SampleTime << (u32ChNum * 4));
+ else if (u32ChNum < 12)
+ ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~(ADC_SMPLCNT1_CH8SAMPCNT_Msk << ((u32ChNum - 8) * 4))) | (u32SampleTime << ((u32ChNum - 8 ) * 4));
+ else
+ ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~ADC_SMPLCNT1_INTCHSAMPCNT_Msk) | (u32SampleTime << ADC_SMPLCNT1_INTCHSAMPCNT_Pos);
+}
+
+/**
+ * @brief Enable the interrupt(s) selected by u32Mask parameter.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
+ * corresponds to a interrupt status. This parameter decides which
+ * interrupts will be enabled.
+ * - \ref ADC_ADF_INT
+ * - \ref ADC_CMP0_INT
+ * - \ref ADC_CMP1_INT
+ * @return None
+ */
+void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
+{
+ if(u32Mask & ADC_ADF_INT)
+ ADC->CR |= ADC_CR_ADIE_Msk;
+ if(u32Mask & ADC_CMP0_INT)
+ ADC->CMPR0 |= ADC_CMPR_CMPIE_Msk;
+ if(u32Mask & ADC_CMP1_INT)
+ ADC->CMPR1 |= ADC_CMPR_CMPIE_Msk;
+
+ return;
+}
+
+/**
+ * @brief Disable the interrupt(s) selected by u32Mask parameter.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
+ * corresponds to a interrupt status. This parameter decides which
+ * interrupts will be disabled.
+ * - \ref ADC_ADF_INT
+ * - \ref ADC_CMP0_INT
+ * - \ref ADC_CMP1_INT
+ * @return None
+ */
+void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
+{
+ if(u32Mask & ADC_ADF_INT)
+ ADC->CR &= ~ADC_CR_ADIE_Msk;
+ if(u32Mask & ADC_CMP0_INT)
+ ADC->CMPR0 &= ~ADC_CMPR_CMPIE_Msk;
+ if(u32Mask & ADC_CMP1_INT)
+ ADC->CMPR1 &= ~ADC_CMPR_CMPIE_Msk;
+
+ return;
+}
+
+
+
+/*@}*/ /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_ADC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_adc.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,367 @@
+/**************************************************************************//**
+ * @file adc.h
+ * @version V1.00
+ * $Revision: 10 $
+ * $Date: 15/06/30 2:50p $
+ * @brief NANO100 series ADC driver header file
+ *
+ * @note
+ * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ADC_H__
+#define __ADC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_ADC_Driver ADC Driver
+ @{
+*/
+
+/** @addtogroup NANO100_ADC_EXPORTED_CONSTANTS ADC Exported Constants
+ @{
+*/
+
+#define ADC_CH_0_MASK (1UL << 0) /*!< ADC channel 0 mask */
+#define ADC_CH_1_MASK (1UL << 1) /*!< ADC channel 1 mask */
+#define ADC_CH_2_MASK (1UL << 2) /*!< ADC channel 2 mask */
+#define ADC_CH_3_MASK (1UL << 3) /*!< ADC channel 3 mask */
+#define ADC_CH_4_MASK (1UL << 4) /*!< ADC channel 4 mask */
+#define ADC_CH_5_MASK (1UL << 5) /*!< ADC channel 5 mask */
+#define ADC_CH_6_MASK (1UL << 6) /*!< ADC channel 6 mask */
+#define ADC_CH_7_MASK (1UL << 7) /*!< ADC channel 7 mask */
+#define ADC_CH_8_MASK (1UL << 8) /*!< ADC channel 8 mask */
+#define ADC_CH_9_MASK (1UL << 9) /*!< ADC channel 9 mask */
+#define ADC_CH_10_MASK (1UL << 10) /*!< ADC channel 10 mask */
+#define ADC_CH_11_MASK (1UL << 11) /*!< ADC channel 11 mask */
+#define ADC_CH_12_MASK (1UL << 12) /*!< ADC channel 12 mask */
+#define ADC_CH_13_MASK (1UL << 13) /*!< ADC channel 13 mask */
+#define ADC_CH_14_MASK (1UL << 14) /*!< ADC channel 14 mask */
+#define ADC_CH_15_MASK (1UL << 15) /*!< ADC channel 15 mask */
+#define ADC_CH_16_MASK (1UL << 16) /*!< ADC channel 16 mask */
+#define ADC_CH_17_MASK (1UL << 17) /*!< ADC channel 17 mask */
+#define ADC_CHEN_Msk (0x3FFFF) /*!< ADC channel 0 ~ 17 mask */
+#define ADC_PDMADATA_AD_PDMA_Msk (0xFFF) /*!< ADC PDMA current transfer data */
+#define ADC_CMP_LESS_THAN (0UL) /*!< ADC compare condition less than */
+#define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR_CMPCOND_Msk) /*!< ADC compare condition greater or equal to */
+#define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC (P3.2) pin */
+#define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos) /*!< External pin low level trigger ADC */
+#define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos) /*!< External pin high level trigger ADC */
+#define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos) /*!< External pin falling edge trigger ADC */
+#define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos) /*!< External pin rising edge trigger ADC */
+#define ADC_ADF_INT (ADC_SR_ADF_Msk) /*!< ADC convert complete interrupt */
+#define ADC_CMP0_INT (ADC_SR_CMPF0_Msk) /*!< ADC comparator 0 interrupt */
+#define ADC_CMP1_INT (ADC_SR_CMPF1_Msk) /*!< ADC comparator 1 interrupt */
+#define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CR_DIFF_Pos) /*!< ADC input mode set to single end */
+#define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CR_DIFF_Pos) /*!< ADC input mode set to differential */
+#define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to single conversion */
+#define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to single cycle scan */
+#define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos) /*!< ADC operation mode set to continuous scan */
+#define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CR_DIFF_Pos) /*!< ADC differential mode output format with unsigned */
+#define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CR_DIFF_Pos) /*!< ADC differential mode output format with 2's complement */
+#define ADC_RESSEL_6_BIT (0UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 6 bit */
+#define ADC_RESSEL_8_BIT (1UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 8 bit */
+#define ADC_RESSEL_10_BIT (2UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 10 bit */
+#define ADC_RESSEL_12_BIT (3UL << ADC_CR_RESSEL_Pos) /*!< ADC resolution selection set to 12 bit */
+#define ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to power */
+#define ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to Int_VREF */
+#define ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos) /*!< ADC reference voltage source selection set to VREF */
+
+/*@}*/ /* end of group NANO100_ADC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Get the latest ADC conversion data
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32ChNum Channel number
+ * @return Latest ADC conversion data
+ * \hideinitializer
+ */
+#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_RSLT_Msk)
+
+/**
+ * @brief Return the user-specified interrupt flags
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
+ * - \ref ADC_ADF_INT
+ * - \ref ADC_CMP0_INT
+ * - \ref ADC_CMP1_INT
+ * @return User specified interrupt flags
+ * \hideinitializer
+ */
+#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->SR & (u32Mask))
+
+/**
+ * @brief This macro clear the selected interrupt status bits
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
+ * - \ref ADC_ADF_INT
+ * - \ref ADC_CMP0_INT
+ * - \ref ADC_CMP1_INT
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->SR = (ADC->SR & ~(ADC_SR_ADF_Msk | \
+ ADC_SR_CMPF0_Msk | \
+ ADC_SR_CMPF1_Msk)) | (u32Mask))
+
+/**
+ * @brief Get the busy state of ADC
+ * @param[in] adc Base address of ADC module
+ * @return busy state of ADC
+ * @retval 0 ADC is not busy
+ * @retval 1 ADC is busy
+ * \hideinitializer
+ */
+#define ADC_IS_BUSY(adc) (ADC->SR & ADC_SR_BUSY_Msk ? 1 : 0)
+
+/**
+ * @brief Check if the ADC conversion data is over written or not
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32ChNum Currently not used
+ * @return Over run state of ADC data
+ * @retval 0 ADC data is not overrun
+ * @retval 1 ADC data us overrun
+ * \hideinitializer
+ */
+#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_OVERRUN_Msk ? 1 : 0)
+
+/**
+ * @brief Check if the ADC conversion data is valid or not
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32ChNum Currently not used
+ * @return Valid state of ADC data
+ * @retval 0 ADC data is not valid
+ * @retval 1 ADC data us valid
+ * \hideinitializer
+ */
+#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_VALID_Msk ? 1 : 0)
+
+/**
+ * @brief Power down ADC module
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_POWER_DOWN(adc) (ADC->CR &= ~ADC_CR_ADEN_Msk)
+
+/**
+ * @brief Power on ADC module
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_POWER_ON(adc) \
+do { \
+ ADC->CR |= ADC_CR_ADEN_Msk; \
+ while ((!(ADC->SR & ADC_SR_INITRDY_Msk)) || (!(ADC->PWRCTL & ADC_PWRCTL_PWUPRDY_Msk))); \
+} while(0)
+
+/**
+ * @brief Configure the comparator 0 and enable it
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
+ * @param[in] u32Condition Specifies the compare condition
+ * - \ref ADC_CMP_LESS_THAN
+ * - \ref ADC_CMP_GREATER_OR_EQUAL_TO
+ * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
+ * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
+ * @return None
+ * @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
+ * Means ADC will assert comparator 0 flag if channel 5 conversion result is
+ * greater or equal to 0x800 for 10 times continuously.
+ * \hideinitializer
+ */
+#define ADC_ENABLE_CMP0(adc, \
+ u32ChNum, \
+ u32Condition, \
+ u32Data, \
+ u32MatchCount) (ADC->CMPR0 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \
+ (u32Condition) | \
+ ((u32Data) << ADC_CMPR_CMPD_Pos) | \
+ (((u32MatchCount) - 1) << ADC_CMPR_CMPMATCNT_Pos) |\
+ ADC_CMPR_CMPEN_Msk)
+
+/**
+ * @brief Disable comparator 0
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_DISABLE_CMP0(adc) (ADC->CMPR0 = 0)
+
+/**
+ * @brief Configure the comparator 1 and enable it
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
+ * @param[in] u32Condition Specifies the compare condition
+ * - \ref ADC_CMP_LESS_THAN
+ * - \ref ADC_CMP_GREATER_OR_EQUAL_TO
+ * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
+ * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
+ * @return None
+ * @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
+ * Means ADC will assert comparator 1 flag if channel 5 conversion result is
+ * greater or equal to 0x800 for 10 times continuously.
+ * \hideinitializer
+ */
+#define ADC_ENABLE_CMP1(adc, \
+ u32ChNum, \
+ u32Condition, \
+ u32Data, \
+ u32MatchCount) (ADC->CMPR1 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \
+ (u32Condition) | \
+ ((u32Data) << ADC_CMPR_CMPD_Pos) | \
+ ((u32MatchCount - 1) << ADC_CMPR_CMPMATCNT_Pos) |\
+ ADC_CMPR_CMPEN_Msk)
+
+/**
+ * @brief Disable comparator 1
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_DISABLE_CMP1(adc) (ADC->CMPR1 = 0)
+
+/**
+ * @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_Msk) | (u32Mask))
+
+/**
+ * @brief Start the A/D conversion.
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_START_CONV(adc) (ADC->CR |= ADC_CR_ADST_Msk)
+
+/**
+ * @brief Stop the A/D conversion.
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_STOP_CONV(adc) (ADC->CR &= ~ADC_CR_ADST_Msk)
+
+/**
+ * @brief Set the output format in differential input mode.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Format Differential input mode output format. Valid values are:
+ * - \ref ADC_DMODE_OUT_FORMAT_UNSIGNED
+ * - \ref ADC_DMODE_OUT_FORMAT_2COMPLEMENT
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_SET_DMOF(adc, u32Format) (ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32Format)
+
+/**
+ * @brief Set the resolution of conversion result.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Resolution The resolution of conversion result. Valid values are:
+ * - \ref ADC_RESSEL_6_BIT
+ * - \ref ADC_RESSEL_8_BIT
+ * - \ref ADC_RESSEL_10_BIT
+ * - \ref ADC_RESSEL_12_BIT
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_SET_RESOLUTION(adc, u32Resolution) (ADC->CR = (ADC->CR & ~ADC_CR_RESSEL_Msk) | u32Resolution)
+
+/**
+ * @brief Set the reference voltage selection.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Ref The reference voltage selection. Valid values are:
+ * - \ref ADC_REFSEL_POWER
+ * - \ref ADC_REFSEL_INT_VREF
+ * - \ref ADC_REFSEL_VREF
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_SET_REF_VOLTAGE(adc, u32Ref) (ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk) | u32Ref)
+
+/**
+ * @brief Set power down mode.
+ * @param[in] adc Base address of ADC module
+ * @param[in] u32Mode The power down mode. 0: power down mode, 2: standby mode
+ * @param[in] u32CalEn Do calibration when power up.
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_SET_POWERDOWN_MODE(adc, u32Mode, u32CalEn) \
+ ADC->PWRCTL = (ADC->PWRCTL & ~(ADC_PWRCTL_PWDMOD_Msk | ADC_PWRCTL_PWDCALEN_Msk)) \
+ | (u32Mode << ADC_PWRCTL_PWDMOD_Pos) | (u32CalEn << ADC_PWRCTL_PWDCALEN_Pos)
+
+/**
+ * @brief Enable PDMA transfer.
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_ENABLE_PDMA(adc) (ADC->CR |= ADC_CR_PTEN_Msk)
+
+/**
+ * @brief Disable PDMA transfer.
+ * @param[in] adc Base address of ADC module
+ * @return None
+ * \hideinitializer
+ */
+#define ADC_DISABLE_PDMA(adc) (ADC->CR &= ~ADC_CR_PTEN_Msk)
+
+/**
+ * @brief Get PDMA current transfer data
+ * @param[in] adc Base address of ADC module
+ * @return PDMA current transfer data
+ * \hideinitializer
+ */
+#define ADC_GET_PDMA_DATA(adc) (ADC->PDMA & ADC_PDMADATA_AD_PDMA_Msk)
+
+void ADC_Open(ADC_T *adc,
+ uint32_t u32InputMode,
+ uint32_t u32OpMode,
+ uint32_t u32ChMask);
+void ADC_Close(ADC_T *adc);
+void ADC_EnableHWTrigger(ADC_T *adc,
+ uint32_t u32Source,
+ uint32_t u32Param);
+void ADC_DisableHWTrigger(ADC_T *adc);
+void ADC_EnableTimerTrigger(ADC_T *adc,
+ uint32_t u32Source,
+ uint32_t u32PDMACnt);
+void ADC_DisableTimerTrigger(ADC_T *adc);
+void ADC_SetExtraSampleTime(ADC_T *adc,
+ uint32_t u32ChNum,
+ uint32_t u32SampleTime);
+void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
+void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
+
+
+
+/*@}*/ /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_ADC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__ADC_H__
+
+/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_clk.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,628 @@
+/**************************************************************************//**
+ * @file clk.c
+ * @version V1.00
+ * $Revision: 29 $
+ * $Date: 15/06/30 3:10p $
+ * @brief NANO100 series CLK driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "Nano100Series.h"
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_CLK_Driver CLK Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function disable frequency output function.
+ * @param None
+ * @return None
+ */
+void CLK_DisableCKO(void)
+{
+ /* Disable CKO0 clock source */
+ CLK->APBCLK &= (~CLK_APBCLK_FDIV_EN_Msk);
+}
+
+/**
+ * @brief This function enable frequency divider module clock,
+ * enable frequency divider clock function and configure frequency divider.
+ * @param[in] u32ClkSrc is frequency divider function clock source
+ * - \ref CLK_CLKSEL2_FRQDIV_S_HXT
+ * - \ref CLK_CLKSEL2_FRQDIV_S_LXT
+ * - \ref CLK_CLKSEL2_FRQDIV_S_HCLK
+ * - \ref CLK_CLKSEL2_FRQDIV_S_HIRC
+ * @param[in] u32ClkDiv is divider output frequency selection.
+ * @return None
+ *
+ * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
+ * The formula is:
+ * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
+ * This function is just used to set CKO clock.
+ * User must enable I/O for CKO clock output pin by themselves.
+ */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ /* CKO = clock source / 2^(u32ClkDiv + 1) */
+ CLK->FRQDIV = CLK_FRQDIV_FDIV_EN_Msk | u32ClkDiv ;
+
+ /* Enable CKO clock source */
+ CLK->APBCLK |= CLK_APBCLK_FDIV_EN_Msk;
+
+ /* Select CKO clock source */
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV_S_Msk)) | u32ClkSrc;
+}
+
+/**
+ * @brief This function let system enter to Power-down mode.
+ * @param None
+ * @return None
+ */
+void CLK_PowerDown(void)
+{
+ SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
+ CLK->PWRCTL |= (CLK_PWRCTL_PD_EN_Msk | CLK_PWRCTL_WK_DLY_Msk );
+ __WFI();
+}
+
+/**
+ * @brief This function let system enter to Idle mode
+ * @return None
+ */
+void CLK_Idle(void)
+{
+ CLK->PWRCTL &= ~(CLK_PWRCTL_PD_EN_Msk );
+ __WFI();
+}
+
+/**
+ * @brief This function get external high frequency crystal frequency. The frequency unit is Hz.
+ * @param None
+ * @return None
+ */
+uint32_t CLK_GetHXTFreq(void)
+{
+ if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN )
+ return __HXT;
+ else
+ return 0;
+}
+
+/**
+ * @brief This function get external low frequency crystal frequency. The frequency unit is Hz.
+ * @return LXT frequency
+ */
+uint32_t CLK_GetLXTFreq(void)
+{
+ if(CLK->PWRCTL & CLK_PWRCTL_LXT_EN )
+ return __LXT;
+ else
+ return 0;
+}
+
+/**
+ * @brief This function get HCLK frequency. The frequency unit is Hz.
+ * @param None
+ * @return HCLK frequency
+ */
+uint32_t CLK_GetHCLKFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief This function get CPU frequency. The frequency unit is Hz.
+ * @param None
+ * @return CPU frequency
+ */
+uint32_t CLK_GetCPUFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+/**
+ * @brief This function get PLL frequency. The frequency unit is Hz.
+ * @param None
+ * @return PLL frequency
+ */
+uint32_t CLK_GetPLLClockFreq(void)
+{
+ uint32_t u32Freq =0, u32PLLSrc;
+ uint32_t u32NO, u32NR, u32IN_DV, u32PllReg;
+
+ u32PllReg = CLK->PLLCTL;
+
+ if (u32PllReg & CLK_PLLCTL_PD)
+ return 0; /* PLL is in power down mode */
+
+ if (u32PllReg & CLK_PLLCTL_PLL_SRC_Msk)
+ u32PLLSrc = __HIRC12M;
+ else
+ u32PLLSrc = __HXT;
+
+ u32NO = (u32PllReg & CLK_PLLCTL_OUT_DV) ? 2: 1;
+
+ u32IN_DV = (u32PllReg & CLK_PLLCTL_IN_DV_Msk) >> 8;
+ if (u32IN_DV == 0)
+ u32NR = 2;
+ else if (u32IN_DV == 1)
+ u32NR = 4;
+ else if (u32IN_DV == 2)
+ u32NR = 8;
+ else
+ u32NR = 16;
+ u32Freq = u32PLLSrc * ((u32PllReg & CLK_PLLCTL_FB_DV_Msk) +32) / u32NR / u32NO;
+ return u32Freq;
+}
+
+/**
+ * @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 ~ 42 MHz
+ * @param[in] u32Hclk is HCLK frequency
+ * @return None
+ */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+ uint32_t u32HIRCSTB;
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_HIRC_STB_Msk;
+
+ if(u32Hclk==__HIRC12M) {
+ CLK_EnableXtalRC(CLK_PWRCTL_HIRC_EN_Msk);
+ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC,CLK_HCLK_CLK_DIVIDER(1));
+ return SystemCoreClock;
+ }
+
+ if(u32Hclk<FREQ_24MHZ) u32Hclk=FREQ_24MHZ;
+ if(u32Hclk>FREQ_42MHZ) u32Hclk=FREQ_42MHZ;
+
+ if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN)
+ CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT,u32Hclk*2);
+ else {
+ CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC,u32Hclk*2);
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_HIRC_STB_Msk;
+ }
+ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(2));
+
+ /* Disable HIRC if HIRC is disabled before setting core clock */
+ if(u32HIRCSTB == 0)
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRC_EN_Msk;
+
+ return SystemCoreClock;
+}
+
+/**
+ * @brief This function set HCLK clock source and HCLK clock divider
+ * @param[in] u32ClkSrc is HCLK clock source. Including :
+ * - \ref CLK_CLKSEL0_HCLK_S_HXT
+ * - \ref CLK_CLKSEL0_HCLK_S_LXT
+ * - \ref CLK_CLKSEL0_HCLK_S_PLL
+ * - \ref CLK_CLKSEL0_HCLK_S_LIRC
+ * - \ref CLK_CLKSEL0_HCLK_S_HIRC
+ * @param[in] u32ClkDiv is HCLK clock divider. Including :
+ * - \ref CLK_HCLK_CLK_DIVIDER(x)
+ * @return None
+ */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32HIRCSTB;
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_HIRC_STB_Msk;
+
+ /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRC_EN_Msk;
+ CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk);
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC;
+
+ CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_N_Msk) | u32ClkDiv;
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc;
+ SystemCoreClockUpdate();
+
+ /* Disable HIRC if HIRC is disabled before switching HCLK source */
+ if(u32HIRCSTB == 0)
+ CLK->PWRCTL &= ~CLK_CLKSTATUS_HIRC_STB_Msk;
+}
+
+/**
+ * @brief This function set selected module clock source and module clock divider
+ * @param[in] u32ModuleIdx is module index.
+ * @param[in] u32ClkSrc is module clock source.
+ * @param[in] u32ClkDiv is module clock divider.
+ * @return None
+ * @details Valid parameter combinations listed in following table:
+ *
+ * |Module index |Clock source |Divider |
+ * | :------------------- | :------------------------------- | :------------------------- |
+ * |\ref GPIO_MODULE | x | x |
+ * |\ref DMA_MODULE | x | x |
+ * |\ref ISP_MODULE | x | x |
+ * |\ref EBI_MODULE | x | x |
+ * |\ref SRAM_MODULE | x | x |
+ * |\ref TICK_MODULE | x | x |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL2_SC_S_HXT |\ref CLK_SC2_CLK_DIVIDER(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL2_SC_S_PLL |\ref CLK_SC2_CLK_DIVIDER(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL2_SC_S_HIRC |\ref CLK_SC2_CLK_DIVIDER(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL2_SC_S_HXT |\ref CLK_SC1_CLK_DIVIDER(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL2_SC_S_PLL |\ref CLK_SC1_CLK_DIVIDER(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL2_SC_S_HIRC |\ref CLK_SC1_CLK_DIVIDER(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL2_SC_S_HXT |\ref CLK_SC0_CLK_DIVIDER(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL2_SC_S_PLL |\ref CLK_SC0_CLK_DIVIDER(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL2_SC_S_HIRC |\ref CLK_SC0_CLK_DIVIDER(x) |
+ * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_HXT |\ref CLK_I2S_CLK_DIVIDER(x) |
+ * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_PLL |\ref CLK_I2S_CLK_DIVIDER(x) |
+ * |\ref I2S_MODULE |\ref CLK_CLKSEL2_I2S_S_HIRC |\ref CLK_I2S_CLK_DIVIDER(x) |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HXT |\ref CLK_ADC_CLK_DIVIDER(x) |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_LXT |\ref CLK_ADC_CLK_DIVIDER(x) |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_PLL |\ref CLK_ADC_CLK_DIVIDER(x) |
+ * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADC_S_HIRC |\ref CLK_ADC_CLK_DIVIDER(x) |
+ * |\ref USBD_MODULE | x |\ref CLK_USB_CLK_DIVIDER(x) |
+ * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_HXT | x |
+ * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_LXT | x |
+ * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_HCLK | x |
+ * |\ref PWM1_CH23_MODULE |\ref CLK_CLKSEL2_PWM1_CH23_S_HIRC | x |
+ * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_HXT | x |
+ * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_LXT | x |
+ * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_HCLK | x |
+ * |\ref PWM1_CH01_MODULE |\ref CLK_CLKSEL2_PWM1_CH01_S_HIRC | x |
+ * |\ref LCD_MODULE |\ref CLK_CLKSEL1_LCD_S_LXT | x |
+ * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_HXT | x |
+ * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_LXT | x |
+ * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_HCLK | x |
+ * |\ref PWM0_CH23_MODULE |\ref CLK_CLKSEL1_PWM0_CH23_S_HIRC | x |
+ * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_HXT | x |
+ * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_LXT | x |
+ * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_HCLK | x |
+ * |\ref PWM0_CH01_MODULE |\ref CLK_CLKSEL1_PWM0_CH01_S_HIRC | x |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_LXT |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HXT |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_LXT |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_PLL |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART_S_HIRC |\ref CLK_UART_CLK_DIVIDER(x) |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2_S_PLL | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2_S_HCLK | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1_S_PLL | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1_S_HCLK | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0_S_PLL | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0_S_HCLK | x |
+ * |\ref I2C1_MODULE | x | x |
+ * |\ref I2C0_MODULE | x | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HXT | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_LXT | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HCLK | x |
+ * |\ref FDIV_MODULE |\ref CLK_CLKSEL2_FRQDIV_S_HIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_HXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_LXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_LIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_EXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL2_TMR3_S_HIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_HXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_LXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_LIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_EXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL2_TMR2_S_HIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_HXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_LXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_LIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_EXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1_S_HIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_LIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_EXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0_S_HIRC | x |
+ * |\ref RTC_MODULE | x | x |
+ * |\ref WDT_MODULE | x | x |
+ * |
+ */
+
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32tmp=0,u32sel=0,u32div=0;
+
+ if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
+ u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4);
+ u32tmp = *(volatile uint32_t *)(u32div);
+ u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
+ *(volatile uint32_t *)(u32div) = u32tmp;
+ }
+
+ if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
+ u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
+ u32tmp = *(volatile uint32_t *)(u32sel);
+ u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
+ *(volatile uint32_t *)(u32sel) = u32tmp;
+ }
+}
+
+/**
+ * @brief This function enable clock source
+ * @param[in] u32ClkMask is clock source mask. Including:
+ * - \ref CLK_PWRCTL_HXT_EN_Msk
+ * - \ref CLK_PWRCTL_LXT_EN_Msk
+ * - \ref CLK_PWRCTL_HIRC_EN_Msk
+ * - \ref CLK_PWRCTL_LIRC_EN_Msk
+ * @return None
+ */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL |= u32ClkMask;
+ if(u32ClkMask & CLK_PWRCTL_HXT_EN_Msk)
+ CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk);
+
+ if(u32ClkMask & CLK_PWRCTL_LXT_EN_Msk)
+ CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk);
+
+ if(u32ClkMask & CLK_PWRCTL_HIRC_EN_Msk)
+ CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk);
+
+ if(u32ClkMask & CLK_PWRCTL_LIRC_EN_Msk)
+ CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk);
+}
+
+/**
+ * @brief This function disable clock source
+ * @param[in] u32ClkMask is clock source mask. Including:
+ * - \ref CLK_PWRCTL_HXT_EN_Msk
+ * - \ref CLK_PWRCTL_LXT_EN_Msk
+ * - \ref CLK_PWRCTL_HIRC_EN_Msk
+ * - \ref CLK_PWRCTL_LIRC_EN_Msk
+ * @return None
+ */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL &= ~u32ClkMask;
+}
+
+/**
+ * @brief This function enable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref GPIO_MODULE
+ * - \ref DMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref SRAM_MODULE
+ * - \ref TICK_MODULE
+ * - \ref SC2_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC0_MODULE
+ * - \ref USBD_MODULE
+ * - \ref I2S_MODULE
+ * - \ref ADC_MODULE
+ * - \ref PWM1_CH23_MODULE
+ * - \ref PWM1_CH01_MODULE
+ * - \ref PWM0_CH23_MODULE
+ * - \ref PWM0_CH01_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART0_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref FDIV_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref RTC_MODULE
+ * - \ref WDT_MODULE
+ * - \ref LCD_MODULE
+ * - \ref DAC_MODULE
+ * @return None
+ */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+ *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
+}
+
+/**
+ * @brief This function disable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref GPIO_MODULE
+ * - \ref DMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref SRAM_MODULE
+ * - \ref TICK_MODULE
+ * - \ref SC2_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC0_MODULE
+ * - \ref USBD_MODULE
+ * - \ref I2S_MODULE
+ * - \ref ADC_MODULE
+ * - \ref PWM1_CH23_MODULE
+ * - \ref PWM1_CH01_MODULE
+ * - \ref PWM0_CH23_MODULE
+ * - \ref PWM0_CH01_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART0_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref FDIV_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref RTC_MODULE
+ * - \ref WDT_MODULE
+ * - \ref LCD_MODULE
+ * - \ref DAC_MODULE
+ * @return None
+ */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+ *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
+}
+
+/**
+ * @brief This function set PLL frequency
+ * @param[in] u32PllClkSrc is PLL clock source. Including :
+ * - \ref CLK_PLLCTL_PLL_SRC_HIRC
+ * - \ref CLK_PLLCTL_PLL_SRC_HXT
+ * @param[in] u32PllFreq is PLL frequency
+ * @return None
+ */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+ uint32_t u32ClkSrc,u32NR, u32NF,u32Register;
+ uint32_t u32NRTable[4]= {2,4,8,16};
+ int32_t i32NRVal;
+ if ( u32PllFreq < FREQ_48MHZ)
+ u32PllFreq=FREQ_48MHZ;
+ else if(u32PllFreq > FREQ_120MHZ)
+ u32PllFreq=FREQ_120MHZ;
+
+ if(u32PllClkSrc!=CLK_PLLCTL_PLL_SRC_HIRC) {
+ /* PLL source clock from HXT */
+ u32Register = (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos);
+ u32ClkSrc = __HXT;
+ } else {
+ /* PLL source clock from HIRC */
+ u32Register = (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos);
+ u32ClkSrc =__HIRC12M;
+ }
+
+ u32NF = u32PllFreq / 1000000;
+ u32NR = u32ClkSrc / 1000000;
+ if(u32ClkSrc%12==0) {
+ u32NF=(u32NF/3)*4;
+ u32NR=(u32NR/3)*4;
+ }
+
+ while( u32NR>16 || u32NF>(0x3F+32) ) {
+ u32NR = u32NR>>1;
+ u32NF = u32NF>>1;
+ }
+
+ for(i32NRVal=3; i32NRVal>=0; i32NRVal--)
+ if(u32NR==u32NRTable[i32NRVal]) break;
+
+ CLK->PLLCTL = u32Register | (i32NRVal<<8) | (u32NF - 32) ;
+
+ CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
+
+ CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
+
+ return CLK_GetPLLClockFreq();
+
+}
+
+/**
+ * @brief This function disable PLL
+ * @param None
+ * @return None
+ */
+void CLK_DisablePLL(void)
+{
+ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+}
+
+/**
+ * @brief This function execute delay function.
+ * @param us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
+ * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
+ * @return None
+ * @details Use the SysTick to generate the delay time and the UNIT is in us.
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.
+ */
+void CLK_SysTickDelay(uint32_t us)
+{
+ SysTick->LOAD = us * CyclesPerUs;
+ SysTick->VAL = (0x00);
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
+ SysTick->CTRL = 0;
+}
+
+/**
+ * @brief Enable System Tick counter
+ * @param[in] u32ClkSrc is System Tick clock source. Including:
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV8
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
+ * @param[in] u32Count is System Tick reload value. It should be 0x1~0xFFFFFF.
+ * @return None
+ * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt.
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
+{
+ SysTick->CTRL=0;
+ if( u32ClkSrc== CLK_CLKSEL0_STCLKSEL_HCLK ) /* Set System Tick clock source */
+ SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+ else {
+ SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
+ }
+ SysTick->LOAD = u32Count; /* Set System Tick reload value */
+ SysTick->VAL = 0; /* Clear System Tick current value and counter flag */
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; /* Set System Tick counter enabled */
+}
+
+/**
+ * @brief Disable System Tick counter
+ * @return None
+ * @details This function disable System Tick counter.
+ */
+void CLK_DisableSysTick(void)
+{
+ SysTick->CTRL = 0; /* Set System Tick counter disabled */
+}
+
+/**
+ * @brief This function check selected clock source status
+ * @param[in] u32ClkMask is selected clock source. Including
+ * - \ref CLK_CLKSTATUS_CLK_SW_FAIL_Msk
+ * - \ref CLK_CLKSTATUS_HIRC_STB_Msk
+ * - \ref CLK_CLKSTATUS_LIRC_STB_Msk
+ * - \ref CLK_CLKSTATUS_PLL_STB_Msk
+ * - \ref CLK_CLKSTATUS_LXT_STB_Msk
+ * - \ref CLK_CLKSTATUS_HXT_STB_Msk
+ * @return 0 clock is not stable
+ * 1 clock is stable
+ *
+ * @details To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)
+ */
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
+{
+ int32_t i32TimeOutCnt;
+
+ i32TimeOutCnt = __HSI / 200; /* About 5ms */
+
+ while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask) {
+ if(i32TimeOutCnt-- <= 0)
+ return 0;
+ }
+ return 1;
+}
+
+
+/*@}*/ /* end of group NANO100_CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_CLK_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_clk.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,367 @@
+/**************************************************************************//**
+ * @file clk.h
+ * @version V1.00
+ * $Revision: 20 $
+ * $Date: 15/07/08 10:00a $
+ * @brief Nano100 series CLK driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __CLK_H__
+#define __CLK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup NANO100_CLK_EXPORTED_CONSTANTS CLK Exported Constants
+ @{
+*/
+
+
+#define FREQ_128MHZ 128000000
+#define FREQ_120MHZ 120000000
+#define FREQ_48MHZ 48000000
+#define FREQ_42MHZ 42000000
+#define FREQ_32MHZ 32000000
+#define FREQ_24MHZ 24000000
+#define FREQ_12MHZ 12000000
+
+/********************* Bit definition of PWRCTL register **********************/
+#define CLK_PWRCTL_HXT_EN (0x1UL<<CLK_PWRCTL_HXT_EN_Pos) /*!<Enable high speed crystal */
+#define CLK_PWRCTL_LXT_EN (0x1UL<<CLK_PWRCTL_LXT_EN_Pos) /*!<Enable low speed crystal */
+#define CLK_PWRCTL_HIRC_EN (0x1UL<<CLK_PWRCTL_HIRC_EN_Pos) /*!<Enable internal high speed oscillator */
+#define CLK_PWRCTL_LIRC_EN (0x1UL<<CLK_PWRCTL_LIRC_EN_Pos) /*!<Enable internal low speed oscillator */
+#define CLK_PWRCTL_DELY_EN (0x1UL<<CLK_PWRCTL_WK_DLY_Pos) /*!<Enable the wake-up delay counter */
+#define CLK_PWRCTL_WAKEINT_EN (0x1UL<<CLK_PWRCTL_PD_WK_IE_Pos) /*!<Enable the wake-up interrupt */
+#define CLK_PWRCTL_PWRDOWN_EN (0x1UL<<CLK_PWRCTL_PD_EN_Pos) /*!<Power down enable bit */
+#define CLK_PWRCTL_HXT_SELXT (0x1UL<<CLK_PWRCTL_HXT_SELXT_Pos) /*!<High frequency crystal loop back path Enabled */
+#define CLK_PWRCTL_HXT_GAIN (0x1UL<<CLK_PWRCTL_HXT_GAIN_Pos) /*!<High frequency crystal Gain control Enabled */
+#define CLK_PWRCTL_LXT_SCNT (0x1UL<<CLK_PWRCTL_LXT_SCNT_Pos) /*!<Delay 8192 LXT before LXT output */
+
+
+/********************* Bit definition of AHBCLK register **********************/
+#define CLK_AHBCLK_GPIO_EN (0x1UL<<CLK_AHBCLK_GPIO_EN_Pos) /*!<GPIO clock enable */
+#define CLK_AHBCLK_DMA_EN (0x1UL<<CLK_AHBCLK_DMA_EN_Pos) /*!<DMA clock enable */
+#define CLK_AHBCLK_ISP_EN (0x1UL<<CLK_AHBCLK_ISP_EN_Pos) /*!<Flash ISP controller clock enable */
+#define CLK_AHBCLK_EBI_EN (0x1UL<<CLK_AHBCLK_EBI_EN_Pos) /*!<EBI clock enable */
+#define CLK_AHBCLK_SRAM_EN (0x1UL<<CLK_AHBCLK_SRAM_EN_Pos) /*!<SRAM Controller Clock Enable */
+#define CLK_AHBCLK_TICK_EN (0x1UL<<CLK_AHBCLK_TICK_EN_Pos) /*!<System Tick Clock Enable */
+
+/********************* Bit definition of APBCLK register **********************/
+#define CLK_APBCLK_WDT_EN (0x1UL<<CLK_APBCLK_WDT_EN_Pos) /*!<Watchdog clock enable */
+#define CLK_APBCLK_RTC_EN (0x1UL<<CLK_APBCLK_RTC_EN_Pos) /*!<RTC clock enable */
+#define CLK_APBCLK_TMR0_EN (0x1UL<<CLK_APBCLK_TMR0_EN_Pos) /*!<Timer 0 clock enable */
+#define CLK_APBCLK_TMR1_EN (0x1UL<<CLK_APBCLK_TMR1_EN_Pos) /*!<Timer 1 clock enable */
+#define CLK_APBCLK_TMR2_EN (0x1UL<<CLK_APBCLK_TMR2_EN_Pos) /*!<Timer 2 clock enable */
+#define CLK_APBCLK_TMR3_EN (0x1UL<<CLK_APBCLK_TMR3_EN_Pos) /*!<Timer 3 clock enable */
+#define CLK_APBCLK_FDIV_EN (0x1UL<<CLK_APBCLK_FDIV_EN_Pos) /*!<Frequency Divider Output clock enable */
+#define CLK_APBCLK_SC2_EN (0x1UL<<CLK_APBCLK_SC2_EN_Pos) /*!<SmartCard 2 Clock Enable Control */
+#define CLK_APBCLK_I2C0_EN (0x1UL<<CLK_APBCLK_I2C0_EN_Pos) /*!<I2C 0 clock enable */
+#define CLK_APBCLK_I2C1_EN (0x1UL<<CLK_APBCLK_I2C1_EN_Pos) /*!<I2C 1 clock enable */
+#define CLK_APBCLK_SPI0_EN (0x1UL<<CLK_APBCLK_SPI0_EN_Pos) /*!<SPI 0 clock enable */
+#define CLK_APBCLK_SPI1_EN (0x1UL<<CLK_APBCLK_SPI1_EN_Pos) /*!<SPI 1 clock enable */
+#define CLK_APBCLK_SPI2_EN (0x1UL<<CLK_APBCLK_SPI2_EN_Pos) /*!<SPI 2 clock enable */
+#define CLK_APBCLK_UART0_EN (0x1UL<<CLK_APBCLK_UART0_EN_Pos) /*!<UART 0 clock enable */
+#define CLK_APBCLK_UART1_EN (0x1UL<<CLK_APBCLK_UART1_EN_Pos) /*!<UART 1 clock enable */
+#define CLK_APBCLK_PWM0_CH01_EN (0x1UL<<CLK_APBCLK_PWM0_CH01_EN_Pos) /*!<PWM0 Channel 0 and Channel 1 Clock Enable Control */
+#define CLK_APBCLK_PWM0_CH23_EN (0x1UL<<CLK_APBCLK_PWM0_CH23_EN_Pos) /*!<PWM0 Channel 2 and Channel 3 Clock Enable Control */
+#define CLK_APBCLK_PWM1_CH01_EN (0x1UL<<CLK_APBCLK_PWM1_CH01_EN_Pos) /*!<PWM1 Channel 0 and Channel 1 Clock Enable Control */
+#define CLK_APBCLK_PWM1_CH23_EN (0x1UL<<CLK_APBCLK_PWM1_CH23_EN_Pos) /*!<PWM1 Channel 2 and Channel 3 Clock Enable Control */
+#define CLK_APBCLK_DAC_EN (0x1UL<<CLK_APBCLK_DAC_EN_Pos) /*!<DAC Clock Enable Control */
+#define CLK_APBCLK_LCD_EN (0x1UL<<CLK_APBCLK_LCD_EN_Pos) /*!<LCD Clock Enable Control */
+#define CLK_APBCLK_USBD_EN (0x1UL<<CLK_APBCLK_USBD_EN_Pos) /*!<USB device clock enable */
+#define CLK_APBCLK_ADC_EN (0x1UL<<CLK_APBCLK_ADC_EN_Pos) /*!<ADC clock enable */
+#define CLK_APBCLK_I2S_EN (0x1UL<<CLK_APBCLK_I2S_EN_Pos) /*!<I2S clock enable */
+#define CLK_APBCLK_SC0_EN (0x1UL<<CLK_APBCLK_SC0_EN_Pos) /*!<SmartCard 0 Clock Enable Control */
+#define CLK_APBCLK_SC1_EN (0x1UL<<CLK_APBCLK_SC1_EN_Pos) /*!<SmartCard 1 Clock Enable Control */
+
+/********************* Bit definition of CLKSTATUS register **********************/
+#define CLK_CLKSTATUS_HXT_STB (0x1UL<<CLK_CLKSTATUS_HXT_STB_Pos) /*!<External high speed crystal clock source stable flag */
+#define CLK_CLKSTATUS_LXT_STB (0x1UL<<CLK_CLKSTATUS_LXT_STB_Pos) /*!<External low speed crystal clock source stable flag */
+#define CLK_CLKSTATUS_PLL_STB (0x1UL<<CLK_CLKSTATUS_PLL_STB_Pos) /*!<Internal PLL clock source stable flag */
+#define CLK_CLKSTATUS_LIRC_STB (0x1UL<<CLK_CLKSTATUS_LIRC_STB_Pos) /*!<Internal low speed oscillator clock source stable flag */
+#define CLK_CLKSTATUS_HIRC_STB (0x1UL<<CLK_CLKSTATUS_HIRC_STB_Pos) /*!<Internal high speed oscillator clock source stable flag */
+#define CLK_CLKSTATUS_CLK_SW_FAIL (0x1UL<<CLK_CLKSTATUS_CLK_SW_FAIL_Pos) /*!<Clock switch fail flag */
+
+
+/********************* Bit definition of CLKSEL0 register **********************/
+#define CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from high speed crystal */
+#define CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from low speed crystal */
+#define CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from PLL */
+#define CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from low speed oscillator */
+#define CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from high speed oscillator */
+
+/********************* Bit definition of CLKSEL1 register **********************/
+#define CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) /*!<Select LCD clock source from low speed crystal */
+
+#define CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from high speed crystal */
+#define CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from low speed crystal */
+#define CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from low speed oscillator */
+#define CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from external trigger */
+#define CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from high speed oscillator */
+
+#define CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from high speed crystal */
+#define CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from low speed crystal */
+#define CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from low speed oscillator */
+#define CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from external trigger */
+#define CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from high speed oscillator */
+
+#define CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from high speed crystal */
+#define CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from low speed crystal */
+#define CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from HCLK */
+#define CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from high speed oscillator */
+
+#define CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from high speed crystal */
+#define CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from low speed crystal */
+#define CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from HCLK */
+#define CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from high speed oscillator */
+
+#define CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from high speed crystal */
+#define CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from low speed crystal */
+#define CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from PLL */
+#define CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from high speed oscillator */
+
+#define CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from high speed crystal */
+#define CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from low speed crystal */
+#define CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from PLL */
+#define CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from high speed oscillator */
+
+/********************* Bit definition of CLKSEL2 register **********************/
+#define CLK_CLKSEL2_SPI2_S_PLL (0x0UL<<CLK_CLKSEL2_SPI2_S_Pos) /*!<Select SPI2 clock source from PLL */
+#define CLK_CLKSEL2_SPI2_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI2_S_Pos) /*!<Select SPI2 clock source from HCLK */
+
+#define CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) /*!<Select SPI1 clock source from PLL */
+#define CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) /*!<Select SPI1 clock source from HCLK */
+
+#define CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) /*!<Select SPI0 clock source from PLL */
+#define CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) /*!<Select SPI0 clock source from HCLK */
+
+#define CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select SmartCard clock source from HXT */
+#define CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select smartCard clock source from PLL */
+#define CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select SmartCard clock source from HIRC */
+
+#define CLK_CLKSEL2_I2S_S_HXT (0x0UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from HXT */
+#define CLK_CLKSEL2_I2S_S_PLL (0x1UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from PLL */
+#define CLK_CLKSEL2_I2S_S_HIRC (0x2UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from HIRC */
+
+#define CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from high speed crystal */
+#define CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from low speed crystal */
+#define CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from low speed oscillator */
+#define CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from external trigger */
+#define CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from high speed oscillator */
+
+#define CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from high speed crystal */
+#define CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from low speed crystal */
+#define CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from low speed oscillator */
+#define CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from external trigger */
+#define CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from high speed oscillator */
+
+#define CLK_CLKSEL2_PWM1_CH01_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from high speed crystal */
+#define CLK_CLKSEL2_PWM1_CH01_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from low speed crystal */
+#define CLK_CLKSEL2_PWM1_CH01_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from HCLK */
+#define CLK_CLKSEL2_PWM1_CH01_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from high speed oscillator */
+
+#define CLK_CLKSEL2_PWM1_CH23_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from high speed crystal */
+#define CLK_CLKSEL2_PWM1_CH23_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from low speed crystal */
+#define CLK_CLKSEL2_PWM1_CH23_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from HCLK */
+#define CLK_CLKSEL2_PWM1_CH23_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from high speed oscillator */
+
+#define CLK_CLKSEL2_FRQDIV_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HXT */
+#define CLK_CLKSEL2_FRQDIV_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from LXT */
+#define CLK_CLKSEL2_FRQDIV_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HCLK */
+#define CLK_CLKSEL2_FRQDIV_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HIRC */
+
+/********************* Bit definition of CLKDIV0 register **********************/
+#define CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
+#define CLK_USB_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_USB_N_Pos) & CLK_CLKDIV0_USB_N_Msk) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
+#define CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) /*!< CLKDIV0 Setting for UART clock divider. It could be 1~16 */
+#define CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) /*!< CLKDIV0 Setting for ADC clock divider. It could be 1~256 */
+#define CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) /*!< CLKDIV0 Setting for SmartCard0 clock divider. It could be 1~16 */
+#define CLK_I2S_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_I2S_N_Pos) & CLK_CLKDIV0_I2S_N_Msk) /*!< CLKDIV0 Setting for I2S clock divider. It could be 1~16 */
+
+/********************* Bit definition of CLKDIV1 register **********************/
+#define CLK_SC2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC2_N_Pos ) & CLK_CLKDIV1_SC2_N_Msk) /*!< CLKDIV1 Setting for SmartCard2 clock divider. It could be 1~16 */
+#define CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) /*!< CLKDIV1 Setting for SmartCard1 clock divider. It could be 1~16 */
+
+/********************* Bit definition of SysTick register **********************/
+#define CLK_CLKSEL0_STCLKSEL_HCLK (1) /*!< Setting systick clock source as external HCLK */
+#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) /*!< Setting systick clock source as external HCLK/8 */
+
+/********************* Bit definition of PLLCTL register **********************/
+#define CLK_PLLCTL_OUT_DV (0x1UL<<CLK_PLLCTL_OUT_DV_Pos) /*!<PLL Output Divider Control */
+#define CLK_PLLCTL_PD (0x1UL<<CLK_PLLCTL_PD_Pos) /*!<PLL Power down mode */
+#define CLK_PLLCTL_PLL_SRC_HIRC (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos) /*!<PLL clock source from high speed oscillator */
+#define CLK_PLLCTL_PLL_SRC_HXT (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos) /*!<PLL clock source from high speed crystal */
+
+#define CLK_PLLCTL_NR_2 0x000 /*!< For PLL input divider is 2 */
+#define CLK_PLLCTL_NR_4 0x100 /*!< For PLL input divider is 4 */
+#define CLK_PLLCTL_NR_8 0x200 /*!< For PLL input divider is 8 */
+#define CLK_PLLCTL_NR_16 0x300 /*!< For PLL input divider is 16 */
+#define CLK_PLLCON_NF(x) ((x)-32) /*!< x must be constant and 32 <= x <= 95.) */
+
+#define CLK_PLLCON_NO_1 0x0000UL /*!< For PLL output divider is 1 */
+#define CLK_PLLCON_NO_2 0x1000UL /*!< For PLL output divider is 2 */
+
+#if (__HXT == 12000000)
+#define CLK_PLLCTL_120MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) /*!< Predefined PLLCTL setting for 120MHz PLL output with 12MHz X'tal */
+#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 96MHz PLL output with 12MHz X'tal */
+#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz X'tal */
+#define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz X'tal */
+#define CLK_PLLCTL_42MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 42MHz PLL output with 12MHz X'tal */
+#else
+# error "The PLL pre-definitions are only valid when external crystal is 12MHz"
+#endif
+#define CLK_PLLCTL_120MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) /*!< Predefined PLLCTL setting for 120MHz PLL output with 12MHz IRC */
+#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 96MHz PLL output with 12MHz IRC */
+#define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz IRC */
+#define CLK_PLLCTL_84MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz IRC */
+#define CLK_PLLCTL_42MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 42MHz PLL output with 12MHz IRC */
+
+/********************* Bit definition of FRQDIV register **********************/
+#define CLK_FRQDIV_EN (0x1UL<<CLK_FRQDIV_FDIV_EN_Pos) /*!<Frequency divider enable bit */
+
+/********************* Bit definition of WK_INTSTS register **********************/
+#define CLK_WK_INTSTS_IS (0x1UL<<CLK_WK_INTSTS_PD_WK_IS_Pos) /*!<Wake-up Interrupt Status in chip Power-down Mode */
+
+/********************* Bit definition of MCLKO register **********************/
+#define CLK_MCLKO_MCLK_SEL_ISP_CLK (0x00<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output ISP_CLK */
+#define CLK_MCLKO_MCLK_SEL_HIRC (0x01<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HIRC clock */
+#define CLK_MCLKO_MCLK_SEL_HXT (0x02<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HXT clock */
+#define CLK_MCLKO_MCLK_SEL_LXT (0x03<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LXT clock */
+#define CLK_MCLKO_MCLK_SEL_LIRC (0x04<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LIRC clock */
+#define CLK_MCLKO_MCLK_SEL_PLLO (0x05<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PLL input */
+#define CLK_MCLKO_MCLK_SEL_PLLI (0x06<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PLL input */
+#define CLK_MCLKO_MCLK_SEL_SYSTICK (0x07<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output system tick */
+#define CLK_MCLKO_MCLK_SEL_HCLK (0x08<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HCLK clock */
+#define CLK_MCLKO_MCLK_SEL_PCLK (0x0A<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PCLK clock */
+#define CLK_MCLKO_MCLK_SEL_TMR0 (0x20<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR0 clock */
+#define CLK_MCLKO_MCLK_SEL_TMR1 (0x21<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR1 clock */
+#define CLK_MCLKO_MCLK_SEL_UART0 (0x22<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output UART0 clock */
+#define CLK_MCLKO_MCLK_SEL_USB (0x23<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output USB clock */
+#define CLK_MCLKO_MCLK_SEL_ADC (0x24<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output ADC clock */
+#define CLK_MCLKO_MCLK_SEL_WDT (0x25<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output WDT clock */
+#define CLK_MCLKO_MCLK_SEL_PWM0CH01 (0x26<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM0CH01 clock */
+#define CLK_MCLKO_MCLK_SEL_PWM0CH23 (0x27<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM0CH23 clock */
+#define CLK_MCLKO_MCLK_SEL_LCD (0x29<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LCD clock */
+#define CLK_MCLKO_MCLK_SEL_TMR2 (0x38<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR2 clock */
+#define CLK_MCLKO_MCLK_SEL_TMR3 (0x39<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR3 clock */
+#define CLK_MCLKO_MCLK_SEL_UART1 (0x3A<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output UART1 clock */
+#define CLK_MCLKO_MCLK_SEL_PWM1CH01 (0x3B<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM1CH01 clock */
+#define CLK_MCLKO_MCLK_SEL_PWM1CH23 (0x3C<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM1CH23 clock */
+#define CLK_MCLKO_MCLK_SEL_I2S (0x3D<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output I2S clock */
+#define CLK_MCLKO_MCLK_SEL_SC0 (0x3E<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output SC0 clock */
+#define CLK_MCLKO_MCLK_SEL_SC1 (0x3F<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output SC1 clock */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* MODULE constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define MODULE_APBCLK(x) ((x >>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */
+#define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */
+#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */
+#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
+#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
+#define NA MODULE_NoMsk /*!< Not Available */
+
+#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK */
+#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2*/
+#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) /*!< CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV */
+#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< APBCLK offset on MODULE index */
+/*-------------------------------------------------------------------------------------------------------------------------------*/
+/* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5) */
+/*-------------------------------------------------------------------------------------------------------------------------------*/
+#define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) /*!< TICK Module */
+#define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) /*!< SRAM Module */
+#define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) /*!< EBI Module */
+#define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) /*!< ISP Module */
+#define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) /*!< DMA Module */
+#define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) /*!< GPIO Module */
+
+#define SC2_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_SC2_EN_Pos ) /*!< SmartCard2 Module */
+#define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) /*!< SmartCard1 Module */
+#define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) /*!< SmartCard0 Module */
+#define I2S_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(16<<20)|(0<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_I2S_EN_Pos ) /*!< I2S Module */
+#define ADC_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) /*!< ADC Module */
+#define USBD_MODULE ((1UL<<31)|(1<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_USBD_EN_Pos ) /*!< USBD Module */
+#define PWM1_CH23_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH23_EN_Pos) /*!< PWM1 Channel2 and Channel3 Module */
+#define PWM1_CH01_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH01_EN_Pos) /*!< PWM1 Channel0 and Channel1 Module */
+#define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) /*!< PWM0 Channel2 and Channel3 Module */
+#define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) /*!< PWM0 Channel0 and Channel1 Module */
+#define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) /*!< UART1 Module */
+#define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) /*!< UART0 Module */
+#define SPI2_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(22<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI2_EN_Pos ) /*!< SPI0 Module */
+#define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) /*!< SPI1 Module */
+#define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) /*!< SPI0 Module */
+#define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) /*!< I2C1 Module */
+#define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) /*!< I2C0 Module */
+#define FDIV_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV_EN_Pos ) /*!< Frequency Divider0 Output Module */
+#define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) /*!< Timer3 Module */
+#define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) /*!< Timer2 Module */
+#define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) /*!< Timer1 Module */
+#define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) /*!< Timer0 Module */
+#define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) /*!< Real-Time-Clock Module */
+#define WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) /*!< Watchdog Timer Module */
+#define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) /*!< LCD Module */
+#define DAC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_DAC_EN_Pos ) /*!< DAC Module */
+/*@}*/ /* end of group NANO100_CLK_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_GetPLLClockFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+void CLK_SysTickDelay(uint32_t us);
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
+void CLK_DisableSysTick(void);
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
+
+/*@}*/ /* end of group NANO100_CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_CLK_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CLK_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_crc.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,100 @@
+/**************************************************************************//**
+ * @file crc.c
+ * @version V1.00
+ * $Revision: 3 $
+ * $Date: 14/09/29 3:50p $
+ * @brief Nano100 series CRC driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_CRC_Driver CRC Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+ @{
+*/
+
+/**
+ * @brief CRC Open
+ *
+ * @param[in] u32Mode CRC Polynomial Mode \ref CRC_CCITT, \ref CRC_8, \ref CRC_16, \ref CRC_32
+ * @param[in] u32Attribute Parameter attribute \ref CRC_CHECKSUM_COM, \ref CRC_CHECKSUM_RVS, \ref CRC_WDATA_COM, \ref CRC_WDATA_RVS
+ * @param[in] u32Seed Seed value
+ * @param[in] u32DataLen CPU Write Data Length \ref CRC_CPU_WDATA_8, \ref CRC_CPU_WDATA_16, \ref CRC_CPU_WDATA_32
+ *
+ * @return None
+ *
+ * @details This function enable the CRC channel.
+ */
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
+{
+ PDMAGCR->GCRCSR |= DMA_GCR_GCRCSR_CRC_CLK_EN_Msk;
+ PDMACRC->SEED = u32Seed;
+ PDMACRC->CTL = u32Mode | u32Attribute | u32DataLen | DMA_CRC_CTL_CRCCEN_Msk;
+ /* When operated in CPU PIO mode, setting RST bit will reload the initial seed value (CRC_SEED register) */
+ PDMACRC->CTL |= DMA_CRC_CTL_CRC_RST_Msk;
+}
+
+/**
+ * @brief CRC Start DMA transfer
+ *
+ * @param[in] u32SrcAddr Source address
+ * @param[in] u32ByteCount Calculate byte count
+ *
+ * @return None
+ *
+ * @details This function start DMA transfer.
+ */
+void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount)
+{
+ PDMACRC->DMASAR = u32SrcAddr;
+ PDMACRC->DMABCR = u32ByteCount;
+ PDMACRC->CTL |= DMA_CRC_CTL_TRIG_EN_Msk;
+}
+
+/**
+ * @brief Get CRC Checksum
+ *
+ * @param[in] None
+ *
+ * @return Checksum
+ *
+ * @details This macro get the CRC checksum
+ */
+uint32_t CRC_GetChecksum(void)
+{
+ switch (PDMACRC->CTL & DMA_CRC_CTL_CRC_MODE_Msk) {
+ case CRC_CCITT:
+ case CRC_16:
+ return (PDMACRC->CHECKSUM & 0xffff);
+
+ case CRC_32:
+ return (PDMACRC->CHECKSUM);
+
+ case CRC_8:
+ return (PDMACRC->CHECKSUM & 0xff);
+
+ default:
+ return 0;
+ }
+}
+
+
+/*@}*/ /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_CRC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_crc.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,158 @@
+/**************************************************************************//**
+ * @file crc.h
+ * @version V1.00
+ * $Revision: 2 $
+ * $Date: 15/06/10 4:50p $
+ * @brief Nano100 series CRC driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_CRC_Driver CRC Driver
+ @{
+*/
+
+/** @addtogroup NANO100_CRC_EXPORTED_CONSTANTS CRC Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CRC Polynomial Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CCITT 0x00000000UL /*!<CRC Polynomial Mode - CCITT */
+#define CRC_8 0x40000000UL /*!<CRC Polynomial Mode - CRC8 */
+#define CRC_16 0x80000000UL /*!<CRC Polynomial Mode - CRC16 */
+#define CRC_32 0xC0000000UL /*!<CRC Polynomial Mode - CRC32 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Checksum, Write data Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CHECKSUM_COM 0x08000000UL /*!<CRC Checksum Complement */
+#define CRC_CHECKSUM_RVS 0x02000000UL /*!<CRC Checksum Reverse */
+#define CRC_WDATA_COM 0x04000000UL /*!<CRC Write Data Complement */
+#define CRC_WDATA_RVS 0x01000000UL /*!<CRC Write Data Reverse */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CPU Write Data Length Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CPU_WDATA_8 0x00000000UL /*!<CRC 8-bit CPU Write Data */
+#define CRC_CPU_WDATA_16 0x10000000UL /*!<CRC 16-bit CPU Write Data */
+#define CRC_CPU_WDATA_32 0x20000000UL /*!<CRC 32-bit CPU Write Data */
+
+
+/*@}*/ /* end of group NANO100_CRC_EXPORTED_CONSTANTS */
+
+/** @addtogroup NANO100_CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable CRC Interrupt
+ *
+ * @param[in] u32Mask Interrupt mask
+ *
+ * @return None
+ *
+ * @details This macro enable the interrupts.
+ */
+#define CRC_ENABLE_INT(u32Mask) (PDMACRC->DMAIER |= (u32Mask))
+
+/**
+ * @brief Disable CRC Interrupt
+ *
+ * @param[in] u32Mask Interrupt mask
+ *
+ * @return None
+ *
+ * @details This macro disable the interrupts.
+ */
+#define CRC_DISABLE_INT(u32Mask) (PDMACRC->DMAIER &= ~(u32Mask))
+
+/**
+ * @brief Get CRC Interrupt Flag
+ *
+ * @param[in] None
+ *
+ * @return Interrupt Flag
+ *
+ * @details This macro gets the interrupt flag.
+ */
+#define CRC_GET_INT_FLAG() ((uint32_t)(PDMACRC->DMAISR))
+
+/**
+ * @brief Clear CRC Interrupt Flag
+ *
+ * @param[in] u32Mask Interrupt mask
+ *
+ * @return None
+ *
+ * @details This macro clear the interrupt flag.
+ */
+#define CRC_CLR_INT_FLAG(u32Mask) (PDMACRC->DMAISR |= (u32Mask))
+
+/**
+ * @brief Set CRC seed value
+ *
+ * @param[in] u32Seed Seed value
+ *
+ * @return None
+ *
+ * @details This macro set seed value.
+ */
+#define CRC_SET_SEED(u32Seed) { PDMACRC->SEED = (u32Seed); PDMACRC->CTL |= DMA_CRC_CTL_CRC_RST_Msk; }
+
+/**
+ * @brief Get CRC Seed value
+ *
+ * @param[in] None
+ *
+ * @return Seed Value
+ *
+ * @details This macro gets the seed value.
+ */
+#define CRC_GET_SEED() ((uint32_t)(PDMACRC->SEED))
+
+/**
+ * @brief CRC write data
+ *
+ * @param[in] u32Data write data
+ *
+ * @return None
+ *
+ * @details This macro write CRC data.
+ */
+#define CRC_WRITE_DATA(u32Data) (PDMACRC->WDATA = (u32Data))
+
+
+/*********************************************************************/
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
+void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount);
+uint32_t CRC_GetChecksum(void);
+
+
+/*@}*/ /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_CRC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CRC_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_dac.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,114 @@
+/**************************************************************************//**
+ * @file dac.c
+ * @version V1.00
+ * $Revision: 4 $
+ * $Date: 14/09/08 12:31p $
+ * @brief NANO100 series DAC driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_DAC_Driver DAC Driver
+ @{
+*/
+
+/** @addtogroup NANO100_DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make a DAC channel ready to convert.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @param[in] u32TrgSrc Decides the trigger source of specified DAC channel. Valid options are:
+ * - \ref DAC_WRITE_DAT_TRIGGER
+ * - \ref DAC_PDMA_TRIGGER
+ * - \ref DAC_TIMER0_TRIGGER
+ * - \ref DAC_TIMER1_TRIGGER
+ * - \ref DAC_TIMER2_TRIGGER
+ * - \ref DAC_TIMER3_TRIGGER
+ * @return None
+ * @note This API also set DAC stable time to 2uc according to current PCLK
+ */
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc)
+{
+ uint32_t u32Delay;
+
+ // DAC needs 6 us to stable after power on
+ u32Delay = CLK_GetHCLKFreq() * 6 / 1000000;
+ if(u32Delay == 0)
+ u32Delay++;
+ if(u32Ch == 0)
+ DAC->CTL0 = (u32Delay << DAC_CTL_DACPWONSTBCNT_Pos) | u32TrgSrc | DAC_CTL_DACEN_Msk;
+ else
+ DAC->CTL1 = (u32Delay << DAC_CTL_DACPWONSTBCNT_Pos) | u32TrgSrc | DAC_CTL_DACEN_Msk;
+
+ // DAC needs 2 us to stable after convert.
+ u32Delay = CLK_GetHCLKFreq() * 2 / 1000000;
+ if(u32Delay == 0)
+ u32Delay++;
+ DAC->COMCTL = (DAC->COMCTL & ~DAC_COMCTL_WAITDACCONV_Msk) | u32Delay;
+}
+
+/**
+ * @brief Disable DAC analog power.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @return None
+ * @details Disable DAC analog power for saving power consumption.
+ */
+void DAC_Close(DAC_T *dac, uint32_t u32Ch)
+{
+ if(u32Ch == 0) {
+ DAC->CTL0 &= ~DAC_CTL_DACEN_Msk;
+ } else {
+ DAC->CTL1 &= ~DAC_CTL_DACEN_Msk;
+ }
+
+}
+
+
+/**
+ * @brief Set delay time for DAC to become stable.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Delay Decides the DAC conversion settling time, Valid values are between 1~0xFF.
+ * @return Success or failed
+ * @retval 0 Success
+ * @retval -1 Failed, the new setting will cause stable time less than 2us. So new setting is not applied.
+ * @details For example, DAC controller clock speed is 12MHz and DAC conversion settling time is 3 us,
+ * u32Delay should be given the value 3 * 12 = 36.
+ * @note User needs to write appropriate value to meet DAC conversion settling time base on
+ * PCLK (APB clock) speed. Minimum delay is 2 us.
+ * @note This setting is shared by both DAC channels.
+ */
+int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
+{
+ uint32_t u32Dly;
+
+ // DAC needs 2 us to stable after DAC convert, calculate minimal setting
+ u32Dly = CLK_GetHCLKFreq() * 2 / 1000000;
+ if(u32Dly == 0)
+ u32Dly++;
+
+ if(u32Delay < u32Dly) // return error id stable time is shorter than 2us
+ return -1;
+ DAC->COMCTL = (DAC->COMCTL & ~DAC_COMCTL_WAITDACCONV_Msk) | u32Delay;
+ return 0;
+}
+
+
+
+
+/*@}*/ /* end of group NANO100_DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_DAC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_dac.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,179 @@
+/******************************************************************************
+ * @file dac.h
+ * @version V1.00
+ * $Revision: 4 $
+ * $Date: 14/09/08 12:31p $
+ * @brief NANO100 series DAC driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __DAC_H__
+#define __DAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_DAC_Driver DAC Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_DAC_EXPORTED_CONSTANTS DAC Exported Constants
+ @{
+*/
+#define DAC_WRITE_DAT_TRIGGER (0UL << DAC_CTL_DACLSEL_Pos) ///< Write DACx_DAT trigger \hideinitializer
+#define DAC_PDMA_TRIGGER (1UL << DAC_CTL_DACLSEL_Pos) ///< PDMA trigger \hideinitializer
+#define DAC_TIMER0_TRIGGER (2UL << DAC_CTL_DACLSEL_Pos) ///< Timer 0 trigger \hideinitializer
+#define DAC_TIMER1_TRIGGER (3UL << DAC_CTL_DACLSEL_Pos) ///< Timer 1 trigger \hideinitializer
+#define DAC_TIMER2_TRIGGER (4UL << DAC_CTL_DACLSEL_Pos) ///< Timer 2 trigger \hideinitializer
+#define DAC_TIMER3_TRIGGER (5UL << DAC_CTL_DACLSEL_Pos) ///< Timer 3 trigger \hideinitializer
+
+#define DAC_REFSEL_POWER (0UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to power \hideinitializer
+#define DAC_REFSEL_INT_VREF (1UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to Int_VREF \hideinitializer
+#define DAC_REFSEL_VREF (2UL << DAC_COMCTL_REFSEL_Pos) ///< DAC reference voltage source selection set to VREF \hideinitializer
+
+/*@}*/ /* end of group NANO100_DAC_EXPORTED_CONSTANTS */
+
+
+
+/** @addtogroup NANO100_DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Write data for conversion.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_WRITE_DATA(dac, u32Ch, u32Data) do {\
+ if(u32Ch) {\
+ DAC->DATA1 = u32Data;\
+ } else {\
+ DAC->DATA0 = u32Data;\
+ }\
+ }while(0)
+
+
+/**
+ * @brief Enable DAC group mode
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_ENABLE_GROUP_MODE(dac) (DAC->COMCTL |= DAC_COMCTL_DAC01GRP_Msk)
+
+/**
+ * @brief Disable DAC group mode
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_DISABLE_GROUP_MODE(dac) (DAC->COMCTL &= ~DAC_COMCTL_DAC01GRP_Msk)
+
+/**
+ * @brief Get the busy state of DAC.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @return If DAC is able to convert or not.
+ * @retval 0 DAC is in idle state.
+ * @retval 1 DAC is in busy state, or DAC is not in ready state.
+ * @details If this macro returns 1, DAC is \b not in ready state. Ether DAC is busy or not in ready state.
+ * \hideinitializer
+ */
+#define DAC_IS_BUSY(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_BUSY_Msk ? 1 : 0)
+
+
+/**
+ * @brief Get the interrupt flag of specified channel.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @return Returns the interrupt flag of selected channel.
+ * @retval 0 DAC interrupt flag is not set.
+ * @retval 1 DAC interrupt flag is set.
+ * \hideinitializer
+ */
+#define DAC_GET_INT_FLAG(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_DACIFG_Msk ? 1 : 0)
+
+/**
+ * @brief This macro clear the interrupt status bit of specified channel.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_CLR_INT_FLAG(dac, u32Ch) do {\
+ if(u32Ch)\
+ DAC->STS1 = DAC_STS_DACIFG_Msk;\
+ else\
+ DAC->STS0 = DAC_STS_DACIFG_Msk;\
+ }while(0)
+
+
+/**
+ * @brief Set the DAC reference voltage. This setting affects both DAC channel
+ * @param[in] dac Base address of DAC module
+ * @param[in] u32Ref The reference voltage selection. Valid values are:
+ * - \ref DAC_REFSEL_POWER
+ * - \ref DAC_REFSEL_INT_VREF
+ * - \ref DAC_REFSEL_VREF
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_SET_REF_VOLTAGE(dac, u32Ref) (DAC->COMCTL = ((DAC->COMCTL) & ~DAC_COMCTL_REFSEL_Msk) | u32Ref)
+
+/**
+ * @brief This macro enable the interrupt of specified channel.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_ENABLE_INT(dac, u32Ch) do {\
+ if(u32Ch)\
+ DAC->CTL1 |= DAC_CTL_DACIE_Msk;\
+ else\
+ DAC->CTL0 |= DAC_CTL_DACIE_Msk;\
+ }while(0)
+
+/**
+ * @brief This macro disable the interrupt of specified channel.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch DAC channel number, could be 0 or 1
+ * @return None
+ * \hideinitializer
+ */
+#define DAC_DISABLE_INT(dac, u32Ch) do {\
+ if(u32Ch)\
+ DAC->CTL1 &= ~DAC_CTL_DACIE_Msk;\
+ else\
+ DAC->CTL0 &= ~DAC_CTL_DACIE_Msk;\
+ }while(0)
+
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
+void DAC_Close(DAC_T *dac, uint32_t u32Ch);
+int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
+
+/*@}*/ /* end of group NANO100_DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_DAC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__DAC_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_ebi.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,152 @@
+/****************************************************************************//**
+ * @file ebi.c
+ * @version V0.10
+ * $Revision: 3 $
+ * $Date: 14/02/05 10:36a $
+ * @brief NANO100 series EBI driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+//#include "ebi.h"
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_EBI_Driver EBI Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize and enable EBI
+ * @param[in] u32Bank argument is reserved in NANO100 series.
+ * @param[in] u32DataWidth Data bus width. Valid values are:
+ * - \ref EBI_BUSWIDTH_8BIT
+ * - \ref EBI_BUSWIDTH_16BIT
+ * @param[in] u32TimingClass Default timing configuration. Valid values are:
+ * - \ref EBI_TIMING_FASTEST
+ * - \ref EBI_TIMING_VERYFAST
+ * - \ref EBI_TIMING_FAST
+ * - \ref EBI_TIMING_NORMAL
+ * - \ref EBI_TIMING_SLOW
+ * - \ref EBI_TIMING_VERYSLOW
+ * - \ref EBI_TIMING_SLOWEST
+ * @param[in] u32BusMode argument is reserved in NANO100 series.
+ * @param[in] u32CSActiveLevel argument is reserved in NANO100 series.
+ * @return none
+ */
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+ EBI->EBICON = 0;
+
+ if (u32DataWidth == EBI_BUSWIDTH_8BIT)
+ EBI->EBICON &= ~EBI_EBICON_ExtBW16_Msk;
+ else
+ EBI->EBICON |= EBI_EBICON_ExtBW16_Msk;
+
+ EBI->EBICON &= ~(EBI_EBICON_ExttALE_Msk | EBI_EBICON_MCLKDIV_Msk);
+ switch (u32TimingClass) {
+ case EBI_TIMING_FASTEST:
+ EBI->EBICON |= (0 << EBI_EBICON_ExttALE_Pos);
+ EBI->EBICON |= (EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = 0;
+ break;
+
+ case EBI_TIMING_VERYFAST:
+ EBI->EBICON |= (1 << EBI_EBICON_ExttALE_Pos);
+ EBI->EBICON |= (EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = (4 << EBI_EXTIME_ExttACC_Pos) | (1 << EBI_EXTIME_ExttAHD_Pos) |
+ (2 << EBI_EXTIME_ExtIW2X_Pos) | (2 << EBI_EXTIME_ExtIR2W_Pos) |
+ (2 << EBI_EXTIME_ExtIR2R_Pos);
+ break;
+
+ case EBI_TIMING_FAST:
+ EBI->EBICON |= (2 << EBI_EBICON_ExttALE_Pos);
+ EBI->EBICON |= (EBI_MCLKDIV_4 << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = (8 << EBI_EXTIME_ExttACC_Pos) | (2 << EBI_EXTIME_ExttAHD_Pos) |
+ (4 << EBI_EXTIME_ExtIW2X_Pos) | (4 << EBI_EXTIME_ExtIR2W_Pos) |
+ (4 << EBI_EXTIME_ExtIR2R_Pos);
+ break;
+
+ case EBI_TIMING_NORMAL:
+ EBI->EBICON |= (3 << EBI_EBICON_ExttALE_Pos);
+ EBI->EBICON |= (EBI_MCLKDIV_8 << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = (16 << EBI_EXTIME_ExttACC_Pos) | (3 << EBI_EXTIME_ExttAHD_Pos) |
+ (8 << EBI_EXTIME_ExtIW2X_Pos) | (8 << EBI_EXTIME_ExtIR2W_Pos) |
+ (8 << EBI_EXTIME_ExtIR2R_Pos);
+ break;
+
+ case EBI_TIMING_SLOW:
+ EBI->EBICON |= (4 << EBI_EBICON_ExttALE_Pos);
+ EBI->EBICON |= (EBI_MCLKDIV_16 << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = (20 << EBI_EXTIME_ExttACC_Pos) | (4 << EBI_EXTIME_ExttAHD_Pos) |
+ (12 << EBI_EXTIME_ExtIW2X_Pos) | (12 << EBI_EXTIME_ExtIR2W_Pos) |
+ (12 << EBI_EXTIME_ExtIR2R_Pos);
+ break;
+
+ case EBI_TIMING_VERYSLOW:
+ EBI->EBICON |= (5 << EBI_EBICON_ExttALE_Pos);
+ EBI->EBICON |= (EBI_MCLKDIV_32 << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = (26 << EBI_EXTIME_ExttACC_Pos) | (5 << EBI_EXTIME_ExttAHD_Pos) |
+ (14 << EBI_EXTIME_ExtIW2X_Pos) | (14 << EBI_EXTIME_ExtIR2W_Pos) |
+ (14 << EBI_EXTIME_ExtIR2R_Pos);
+ break;
+
+ case EBI_TIMING_SLOWEST:
+ EBI->EBICON |= (6 << EBI_EBICON_ExttALE_Pos);
+ EBI->EBICON |= (EBI_MCLKDIV_32 << EBI_EBICON_MCLKDIV_Pos);
+ EBI->EXTIME = (31 << EBI_EXTIME_ExttACC_Pos) | (7 << EBI_EXTIME_ExttAHD_Pos) |
+ (15 << EBI_EXTIME_ExtIW2X_Pos) | (15 << EBI_EXTIME_ExtIR2W_Pos) |
+ (15 << EBI_EXTIME_ExtIR2R_Pos);
+ break;
+ }
+
+ EBI->EBICON |= EBI_EBICON_MCLKEN_Msk | EBI_EBICON_ExtEN_Msk;
+}
+
+/**
+ * @brief Disable EBI
+ * @param[in] u32Bank argument is reserved in NANO100 series.
+ * @return none
+ */
+void EBI_Close(uint8_t u32Bank)
+{
+ EBI->EBICON = 0;
+ EBI->EXTIME = 0;
+}
+
+/**
+ * @brief Set EBI bus timings
+ * @param[in] u32Bank argument is reserved in NANO100 series.
+ * @param[in] u32TimingConfig The new EBI timing settings. This value will be written to EXTIME register.
+ * @param[in] u32MclkDiv Divider for MCLK. Valid values are:
+ * - \ref EBI_MCLKDIV_1
+ * - \ref EBI_MCLKDIV_2
+ * - \ref EBI_MCLKDIV_4
+ * - \ref EBI_MCLKDIV_8
+ * - \ref EBI_MCLKDIV_16
+ * - \ref EBI_MCLKDIV_32
+ * @return none
+ */
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
+{
+ EBI->EXTIME = u32TimingConfig;
+ EBI->EBICON = (EBI->EBICON & ~EBI_EBICON_MCLKDIV_Msk) | (u32MclkDiv << EBI_EBICON_MCLKDIV_Pos);
+}
+
+
+/*@}*/ /* end of group NANO100_EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_EBI_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_ebi.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,150 @@
+/**************************************************************************//**
+ * @file ebi.h
+ * @version V1.00
+ * $Revision: 4 $
+ * $Date: 14/09/30 4:21p $
+ * @brief Nano100 Series Flash Memory Controller Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __EBI_H__
+#define __EBI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_EBI_Driver EBI Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_EBI_EXPORTED_CONSTANTS EBI Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BASE_ADDR 0x60000000 /*!< EBI base address */
+#define EBI_MAX_SIZE 0x20000 /*!< Maximum size of EBI bank */
+#define EBI_TIMEOUT_COUNT 0x10000 /*!< Time-out value */
+
+/* Constants for EBI data bus width */
+#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */
+#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EBI MCLK divider */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_MCLKDIV_1 0 /*!< MCLK divided by 1 */
+#define EBI_MCLKDIV_2 1 /*!< MCLK divided by 2 */
+#define EBI_MCLKDIV_4 2 /*!< MCLK divided by 4 */
+#define EBI_MCLKDIV_8 3 /*!< MCLK divided by 8 */
+#define EBI_MCLKDIV_16 4 /*!< MCLK divided by 16 */
+#define EBI_MCLKDIV_32 5 /*!< MCLK divided by 32 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EBI timing setting */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_TIMING_FASTEST 0x0 /*!< EBI timing is the fastest */
+#define EBI_TIMING_VERYFAST 0x1 /*!< EBI timing is the very fast */
+#define EBI_TIMING_FAST 0x2 /*!< EBI timing is the fast */
+#define EBI_TIMING_NORMAL 0x3 /*!< EBI timing is the normal */
+#define EBI_TIMING_SLOW 0x4 /*!< EBI timing is the slow */
+#define EBI_TIMING_VERYSLOW 0x5 /*!< EBI timing is the very slow */
+#define EBI_TIMING_SLOWEST 0x6 /*!< EBI timing is the slowest */
+
+
+/*@}*/ /* end of group NANO100_EBI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EBI access macros */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/**
+ * @brief Read one byte data from EBI.
+ * @param[in] Addr EBI offset address.
+ * @return Byte data read from EBI.
+ * \hideinitializer
+ */
+#define EBI_READ_DATA8(Addr) *((volatile unsigned char *)(EBI_BASE_ADDR+Addr))
+
+/**
+ * @brief Write one byte data to EBI.
+ * @param[in] Addr EBI offset address.
+ * @param[in] Data Byte data to be written.
+ * @return None
+ * \hideinitializer
+ */
+#define EBI_WRITE_DATA8(Addr, Data) *((volatile unsigned char *)(EBI_BASE_ADDR+Addr))=Data
+
+/**
+ * @brief Read a half-word data from EBI.
+ * @param[in] Addr EBI offset address.
+ * @return Half-word data read from EBI.
+ * \hideinitializer
+ */
+#define EBI_READ_DATA16(Addr) *((volatile unsigned short *)(EBI_BASE_ADDR+Addr))
+
+/**
+ * @brief Write a half-word data to EBI.
+ * @param[in] Addr EBI offset address.
+ * @param[in] Data Half-word data to be written.
+ * @return None
+ * \hideinitializer
+ */
+#define EBI_WRITE_DATA16(Addr, Data) *((volatile unsigned short *)(EBI_BASE_ADDR+Addr))=Data
+
+/**
+ * @brief Read a word data from EBI.
+ * @param[in] Addr EBI offset address.
+ * @return Word data read from EBI.
+ * \hideinitializer
+ */
+#define EBI_READ_DATA32(Addr) *((volatile unsigned int *)(EBI_BASE_ADDR+Addr))
+
+/**
+ * @brief Write a word data to EBI.
+ * @param[in] Addr EBI offset address.
+ * @param[in] Data Word data to be written.
+ * @return None
+ * \hideinitializer
+ */
+#define EBI_WRITE_DATA32(Addr, Data) *((volatile unsigned int *)(EBI_BASE_ADDR+Addr))=Data
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+void EBI_Close(uint8_t u32Bank);
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
+
+
+/*@}*/ /* end of group NANO100_EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_EBI_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __EBI_H__
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_fmc.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,269 @@
+/**************************************************************************//**
+ * @file fmc.c
+ * @version V1.00
+ * $Revision: 8 $
+ * $Date: 15/06/12 3:17p $
+ * @brief NANO100 series FMC driver source file
+ *
+ * @note
+ * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+//* Includes ------------------------------------------------------------------*/
+#include <stdio.h>
+
+#include "Nano100Series.h"
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Disable FMC ISP function.
+ * @return None
+ */
+void FMC_Close(void)
+{
+ FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk;
+}
+
+
+/**
+ * @brief Execute ISP command to erase a flash page. The page size is 512 bytes.
+ * @param[in] u32PageAddr Address of the flash page to be erased.
+ * It must be a 512-byte aligned address.
+ * @return ISP page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase(uint32_t u32PageAddr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+ FMC->ISPADR = u32PageAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+
+ if (FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) {
+ FMC->ISPCON |= FMC_ISPCON_ISPFF_Msk;
+ return -1;
+ }
+ return 0;
+}
+
+
+/**
+ * @brief Get the current boot source.
+ * @return The current boot source.
+ * @retval 0 Is boot from APROM.
+ * @retval 1 Is boot from LDROM.
+ */
+int32_t FMC_GetBootSource (void)
+{
+ if (FMC->ISPCON & FMC_ISPCON_BS_Msk)
+ return 1;
+ else
+ return 0;
+}
+
+
+/**
+ * @brief Enable FMC ISP function
+ * @return None
+ */
+void FMC_Open(void)
+{
+ FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk;
+}
+
+
+/**
+ * @brief Execute ISP command to read a word from flash.
+ * @param[in] u32Addr Address of the flash location to be read.
+ * It must be a word aligned address.
+ * @return The word data read from specified flash address.
+ */
+uint32_t FMC_Read(uint32_t u32Addr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ;
+ FMC->ISPADR = u32Addr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Read company ID.
+ * @return The company ID.
+ */
+uint32_t FMC_ReadCID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_CID;
+ FMC->ISPADR = 0x0;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Read product ID.
+ * @return The product ID.
+ */
+uint32_t FMC_ReadPID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_PID;
+ FMC->ISPADR = 0x04;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief This function reads one of the four UCID.
+ * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+ * @return The UCID.
+ */
+uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+ FMC->ISPADR = (0x04 * u32Index) + 0x10;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief This function reads one of the three UID.
+ * @param[in] u32Index Index of the UID to read. u32Index must be 0, 1, or 2.
+ * @return The UID.
+ */
+uint32_t FMC_ReadUID(uint32_t u32Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+ FMC->ISPADR = 0x04 * u32Index;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Get the base address of Data Flash if enabled.
+ * @return Base address of Data Flash
+ */
+uint32_t FMC_ReadDataFlashBaseAddr(void)
+{
+ return FMC->DFBADR;
+}
+
+
+/**
+ * @brief This function will force re-map assigned flash page to CPU address 0x0.
+ * @param[in] u32PageAddr Address of the page to be mapped to CPU address 0x0.
+ * @return None
+ */
+void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_VECMAP;
+ FMC->ISPADR = u32PageAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+}
+
+
+/**
+ * @brief Obtain the current vector page address setting.
+ * @return The vector page address.
+ */
+uint32_t FMC_GetVectorPageAddr(void)
+{
+ return (FMC->ISPSTA & 0x0FFFFF00ul);
+}
+
+
+/**
+ * @brief Execute ISP command to program a word to flash.
+ * @param[in] u32Addr Address of the flash location to be programmed.
+ * It must be a word aligned address.
+ * @param[in] u32Data The word data to be programmed.
+ * @return None
+ */
+void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADR = u32Addr;
+ FMC->ISPDAT = u32Data;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
+}
+
+
+/**
+ * @brief Execute ISP command to read User Configuration.
+ * @param[out] u32Config A two-word array.
+ * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+ * @param[in] u32Count Avaliable word count in u32Config.
+ * @return Success or not.
+ * @retval 0 Success.
+ * @retval -1 Invalid parameter.
+ */
+int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+ u32Config[0] = FMC_Read(FMC_CONFIG_BASE);
+ if (u32Count < 2)
+ return -1;
+ u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4);
+ return 0;
+}
+
+
+/**
+ * @brief Execute ISP command to write User Configuration.
+ * @param[in] u32Config A two-word array.
+ * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+ * @param[in] u32Count Avaliable word count in u32Config.
+ * @return Success or not.
+ * @retval 0 Success.
+ * @retval -1 Invalid parameter.
+ */
+int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+ FMC_ENABLE_CFG_UPDATE();
+ FMC_Erase(FMC_CONFIG_BASE);
+ FMC_Write(FMC_CONFIG_BASE, u32Config[0]);
+ FMC_Write(FMC_CONFIG_BASE+4, u32Config[1]);
+ FMC_DISABLE_CFG_UPDATE();
+ return 0;
+}
+
+
+/*@}*/ /* end of group NANO100_FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_FMC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_fmc.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file fmc.h
+ * @version V1.00
+ * $Revision: 5 $
+ * $Date: 15/06/12 2:11p $
+ * @brief Nano100B Series Flash Memory Controller Driver Header File
+ *
+ * @note
+ * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __FMC_H__
+#define __FMC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_FMC_EXPORTED_CONSTANTS FMC Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
+#define FMC_APROM_END 0x0001EC00UL /*!< APROM End Address */
+#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
+#define FMC_LDROM_END 0x00101000UL /*!< LDROM End Address */
+#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration Address */
+
+#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 bytes) */
+#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 Kbytes) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCMD constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read flash word */
+#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Write flash word */
+#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
+#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
+#define FMC_ISPCMD_READ_PID 0x0C /*!< ISP Command: Read Product ID */
+#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
+#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Vector Page Remap */
+
+#define IS_BOOT_FROM_APROM 0 /*!< Is booting from APROM */
+#define IS_BOOT_FROM_LDROM 1 /*!< Is booting from LDROM */
+
+
+/*@}*/ /* end of group NANO100_FMC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macros */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/**
+ * @brief This macro selects booting from APROM.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_SET_APROM_BOOT() (FMC->ISPCON &= ~FMC_ISPCON_BS_Msk)
+
+/**
+ * @brief This macro selects booting from LDROM.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_SET_LDROM_BOOT() (FMC->ISPCON |= FMC_ISPCON_BS_Msk)
+
+/**
+ * @brief This macro enables APROM update function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCON |= FMC_ISPCON_APUEN_Msk)
+
+/**
+ * @brief This macro disables APROM update function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk)
+
+/**
+ * @brief This macro enables User Configuration update function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk)
+
+/**
+ * @brief This macro disables User Configuration update function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk)
+
+/**
+ * @brief This macro enables LDROM update function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk)
+
+/**
+ * @brief This macro disables LDROM update function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk)
+
+/**
+ * @brief This macro enables ISP function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_ENABLE_ISP() (FMC->ISPCON |= FMC_ISPCON_ISPEN_Msk)
+
+/**
+ * @brief This macro disables ISP function.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_DISABLE_ISP() (FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk)
+
+/**
+ * @brief This macro gets ISP fail flag value.
+ * @param None
+ * @return ISP fail flag value.
+ * \hideinitializer
+ */
+#define FMC_GET_FAIL_FLAG() ((FMC->ISPCON & FMC_ISPCON_ISPFF_Msk) ? 1 : 0)
+
+/**
+ * @brief This macro clears ISP fail flag.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define FMC_CLR_FAIL_FLAG() (FMC->ISPCON |= FMC_ISPCON_ISPFF_Msk)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+extern void FMC_Close(void);
+extern int32_t FMC_Erase(uint32_t u32PageAddr);
+extern int32_t FMC_GetBootSource(void);
+extern void FMC_Open(void);
+extern uint32_t FMC_Read(uint32_t u32Addr);
+extern uint32_t FMC_ReadCID(void);
+extern uint32_t FMC_ReadPID(void);
+extern uint32_t FMC_ReadUCID(uint32_t u32Index);
+extern uint32_t FMC_ReadUID(uint32_t u32Index);
+extern uint32_t FMC_ReadDataFlashBaseAddr(void);
+extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
+extern uint32_t FMC_GetVectorPageAddr(void);
+extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
+extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
+extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
+
+
+/*@}*/ /* end of group NANO100_FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_FMC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FMC_H__
+
+/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_gpio.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,93 @@
+/**************************************************************************//**
+ * @file gpio.c
+ * @version V1.00
+ * $Revision: 3 $
+ * $Date: 14/09/29 3:50p $
+ * @brief Nano100 series GPIO driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_GPIO_Driver GPIO Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set GPIO operation mode
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * @param[in] u32Mode Operation mode. \ref GPIO_PMD_INPUT, \ref GPIO_PMD_OUTPUT, \ref GPIO_PMD_OPEN_DRAIN
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for (i=0; i<GPIO_PIN_MAX; i++) {
+ if (u32PinMask & (1 << i)) {
+ gpio->PMD = (gpio->PMD & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable GPIO interrupt
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+ gpio->IMD |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+ gpio->IER |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief Disable GPIO interrupt
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin)
+{
+ gpio->IMD &= ~(1UL << u32Pin);
+ gpio->IER &= ~((0x00010001UL) << u32Pin);
+}
+
+
+
+/*@}*/ /* end of group NANO100_GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_GPIO_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_gpio.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,443 @@
+/**************************************************************************//**
+ * @file gpio.h
+ * @version V1.00
+ * $Revision: 7 $
+ * $Date: 14/12/01 10:30a $
+ * @brief Nano100 series GPIO driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup NANO100_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+ @{
+*/
+#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PMD Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_PMD_INPUT 0x0UL /*!< Input Mode */
+#define GPIO_PMD_OUTPUT 0x1UL /*!< Output Mode */
+#define GPIO_PMD_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Interrupt Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
+#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
+#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
+#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
+#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* IMD Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_IMD_EDGE 0UL /*!< IMD Setting for Edge Trigger Mode */
+#define GPIO_IMD_LEVEL 1UL /*!< IMD Setting for Edge Level Mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* DBNCECON Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_ICLK_ON 0x00000020UL /*!< DBNCECON setting for all IO pins edge detection circuit is always active after reset */
+#define GPIO_ICLK_OFF 0x00000000UL /*!< DBNCECON setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
+
+#define GPIO_DBCLKSRC_IRC10K 0x00000010UL /*!< DBNCECON setting for de-bounce counter clock source is the internal 10 kHz */
+#define GPIO_DBCLKSRC_HCLK 0x00000000UL /*!< DBNCECON setting for de-bounce counter clock source is the internal HCLK */
+
+#define GPIO_DBCLKSEL_1 0x00000000UL /*!< DBNCECON setting for sampling cycle = 1 clocks */
+#define GPIO_DBCLKSEL_2 0x00000001UL /*!< DBNCECON setting for sampling cycle = 2 clocks */
+#define GPIO_DBCLKSEL_4 0x00000002UL /*!< DBNCECON setting for sampling cycle = 4 clocks */
+#define GPIO_DBCLKSEL_8 0x00000003UL /*!< DBNCECON setting for sampling cycle = 8 clocks */
+#define GPIO_DBCLKSEL_16 0x00000004UL /*!< DBNCECON setting for sampling cycle = 16 clocks */
+#define GPIO_DBCLKSEL_32 0x00000005UL /*!< DBNCECON setting for sampling cycle = 32 clocks */
+#define GPIO_DBCLKSEL_64 0x00000006UL /*!< DBNCECON setting for sampling cycle = 64 clocks */
+#define GPIO_DBCLKSEL_128 0x00000007UL /*!< DBNCECON setting for sampling cycle = 128 clocks */
+#define GPIO_DBCLKSEL_256 0x00000008UL /*!< DBNCECON setting for sampling cycle = 256 clocks */
+#define GPIO_DBCLKSEL_512 0x00000009UL /*!< DBNCECON setting for sampling cycle = 512 clocks */
+#define GPIO_DBCLKSEL_1024 0x0000000AUL /*!< DBNCECON setting for sampling cycle = 1024 clocks */
+#define GPIO_DBCLKSEL_2048 0x0000000BUL /*!< DBNCECON setting for sampling cycle = 2048 clocks */
+#define GPIO_DBCLKSEL_4096 0x0000000CUL /*!< DBNCECON setting for sampling cycle = 4096 clocks */
+#define GPIO_DBCLKSEL_8192 0x0000000DUL /*!< DBNCECON setting for sampling cycle = 8192 clocks */
+#define GPIO_DBCLKSEL_16384 0x0000000EUL /*!< DBNCECON setting for sampling cycle = 16384 clocks */
+#define GPIO_DBCLKSEL_32768 0x0000000FUL /*!< DBNCECON setting for sampling cycle = 32768 clocks */
+
+/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+ * Example 1:
+ *
+ * PA0 = 1;
+ *
+ * It is used to set PA0 to high;
+ *
+ * Example 2:
+ *
+ * if (PA0)
+ * PA0 = 0;
+ *
+ * If PA0 pin status is high, then set PA0 data output to low.
+ */
+#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
+#define PA0 GPIO_PIN_ADDR(0, 0) /*!< Specify PA0 Pin Data Input/Output */
+#define PA1 GPIO_PIN_ADDR(0, 1) /*!< Specify PA1 Pin Data Input/Output */
+#define PA2 GPIO_PIN_ADDR(0, 2) /*!< Specify PA2 Pin Data Input/Output */
+#define PA3 GPIO_PIN_ADDR(0, 3) /*!< Specify PA3 Pin Data Input/Output */
+#define PA4 GPIO_PIN_ADDR(0, 4) /*!< Specify PA4 Pin Data Input/Output */
+#define PA5 GPIO_PIN_ADDR(0, 5) /*!< Specify PA5 Pin Data Input/Output */
+#define PA6 GPIO_PIN_ADDR(0, 6) /*!< Specify PA6 Pin Data Input/Output */
+#define PA7 GPIO_PIN_ADDR(0, 7) /*!< Specify PA7 Pin Data Input/Output */
+#define PA8 GPIO_PIN_ADDR(0, 8) /*!< Specify PA8 Pin Data Input/Output */
+#define PA9 GPIO_PIN_ADDR(0, 9) /*!< Specify PA9 Pin Data Input/Output */
+#define PA10 GPIO_PIN_ADDR(0, 10) /*!< Specify PA10 Pin Data Input/Output */
+#define PA11 GPIO_PIN_ADDR(0, 11) /*!< Specify PA11 Pin Data Input/Output */
+#define PA12 GPIO_PIN_ADDR(0, 12) /*!< Specify PA12 Pin Data Input/Output */
+#define PA13 GPIO_PIN_ADDR(0, 13) /*!< Specify PA13 Pin Data Input/Output */
+#define PA14 GPIO_PIN_ADDR(0, 14) /*!< Specify PA14 Pin Data Input/Output */
+#define PA15 GPIO_PIN_ADDR(0, 15) /*!< Specify PA15 Pin Data Input/Output */
+
+#define PB0 GPIO_PIN_ADDR(1, 0) /*!< Specify PB0 Pin Data Input/Output */
+#define PB1 GPIO_PIN_ADDR(1, 1) /*!< Specify PB1 Pin Data Input/Output */
+#define PB2 GPIO_PIN_ADDR(1, 2) /*!< Specify PB2 Pin Data Input/Output */
+#define PB3 GPIO_PIN_ADDR(1, 3) /*!< Specify PB3 Pin Data Input/Output */
+#define PB4 GPIO_PIN_ADDR(1, 4) /*!< Specify PB4 Pin Data Input/Output */
+#define PB5 GPIO_PIN_ADDR(1, 5) /*!< Specify PB5 Pin Data Input/Output */
+#define PB6 GPIO_PIN_ADDR(1, 6) /*!< Specify PB6 Pin Data Input/Output */
+#define PB7 GPIO_PIN_ADDR(1, 7) /*!< Specify PB7 Pin Data Input/Output */
+#define PB8 GPIO_PIN_ADDR(1, 8) /*!< Specify PB8 Pin Data Input/Output */
+#define PB9 GPIO_PIN_ADDR(1, 9) /*!< Specify PB9 Pin Data Input/Output */
+#define PB10 GPIO_PIN_ADDR(1, 10) /*!< Specify PB10 Pin Data Input/Output */
+#define PB11 GPIO_PIN_ADDR(1, 11) /*!< Specify PB11 Pin Data Input/Output */
+#define PB12 GPIO_PIN_ADDR(1, 12) /*!< Specify PB12 Pin Data Input/Output */
+#define PB13 GPIO_PIN_ADDR(1, 13) /*!< Specify PB13 Pin Data Input/Output */
+#define PB14 GPIO_PIN_ADDR(1, 14) /*!< Specify PB14 Pin Data Input/Output */
+#define PB15 GPIO_PIN_ADDR(1, 15) /*!< Specify PB15 Pin Data Input/Output */
+
+#define PC0 GPIO_PIN_ADDR(2, 0) /*!< Specify PC0 Pin Data Input/Output */
+#define PC1 GPIO_PIN_ADDR(2, 1) /*!< Specify PC1 Pin Data Input/Output */
+#define PC2 GPIO_PIN_ADDR(2, 2) /*!< Specify PC2 Pin Data Input/Output */
+#define PC3 GPIO_PIN_ADDR(2, 3) /*!< Specify PC3 Pin Data Input/Output */
+#define PC4 GPIO_PIN_ADDR(2, 4) /*!< Specify PC4 Pin Data Input/Output */
+#define PC5 GPIO_PIN_ADDR(2, 5) /*!< Specify PC5 Pin Data Input/Output */
+#define PC6 GPIO_PIN_ADDR(2, 6) /*!< Specify PC6 Pin Data Input/Output */
+#define PC7 GPIO_PIN_ADDR(2, 7) /*!< Specify PC7 Pin Data Input/Output */
+#define PC8 GPIO_PIN_ADDR(2, 8) /*!< Specify PC8 Pin Data Input/Output */
+#define PC9 GPIO_PIN_ADDR(2, 9) /*!< Specify PC9 Pin Data Input/Output */
+#define PC10 GPIO_PIN_ADDR(2, 10) /*!< Specify PC10 Pin Data Input/Output */
+#define PC11 GPIO_PIN_ADDR(2, 11) /*!< Specify PC11 Pin Data Input/Output */
+#define PC12 GPIO_PIN_ADDR(2, 12) /*!< Specify PC12 Pin Data Input/Output */
+#define PC13 GPIO_PIN_ADDR(2, 13) /*!< Specify PC13 Pin Data Input/Output */
+#define PC14 GPIO_PIN_ADDR(2, 14) /*!< Specify PC14 Pin Data Input/Output */
+#define PC15 GPIO_PIN_ADDR(2, 15) /*!< Specify PC15 Pin Data Input/Output */
+
+#define PD0 GPIO_PIN_ADDR(3, 0) /*!< Specify PD0 Pin Data Input/Output */
+#define PD1 GPIO_PIN_ADDR(3, 1) /*!< Specify PD1 Pin Data Input/Output */
+#define PD2 GPIO_PIN_ADDR(3, 2) /*!< Specify PD2 Pin Data Input/Output */
+#define PD3 GPIO_PIN_ADDR(3, 3) /*!< Specify PD3 Pin Data Input/Output */
+#define PD4 GPIO_PIN_ADDR(3, 4) /*!< Specify PD4 Pin Data Input/Output */
+#define PD5 GPIO_PIN_ADDR(3, 5) /*!< Specify PD5 Pin Data Input/Output */
+#define PD6 GPIO_PIN_ADDR(3, 6) /*!< Specify PD6 Pin Data Input/Output */
+#define PD7 GPIO_PIN_ADDR(3, 7) /*!< Specify PD7 Pin Data Input/Output */
+#define PD8 GPIO_PIN_ADDR(3, 8) /*!< Specify PD8 Pin Data Input/Output */
+#define PD9 GPIO_PIN_ADDR(3, 9) /*!< Specify PD9 Pin Data Input/Output */
+#define PD10 GPIO_PIN_ADDR(3, 10) /*!< Specify PD10 Pin Data Input/Output */
+#define PD11 GPIO_PIN_ADDR(3, 11) /*!< Specify PD11 Pin Data Input/Output */
+#define PD12 GPIO_PIN_ADDR(3, 12) /*!< Specify PD12 Pin Data Input/Output */
+#define PD13 GPIO_PIN_ADDR(3, 13) /*!< Specify PD13 Pin Data Input/Output */
+#define PD14 GPIO_PIN_ADDR(3, 14) /*!< Specify PD14 Pin Data Input/Output */
+#define PD15 GPIO_PIN_ADDR(3, 15) /*!< Specify PD15 Pin Data Input/Output */
+
+#define PE0 GPIO_PIN_ADDR(4, 0) /*!< Specify PE0 Pin Data Input/Output */
+#define PE1 GPIO_PIN_ADDR(4, 1) /*!< Specify PE1 Pin Data Input/Output */
+#define PE2 GPIO_PIN_ADDR(4, 2) /*!< Specify PE2 Pin Data Input/Output */
+#define PE3 GPIO_PIN_ADDR(4, 3) /*!< Specify PE3 Pin Data Input/Output */
+#define PE4 GPIO_PIN_ADDR(4, 4) /*!< Specify PE4 Pin Data Input/Output */
+#define PE5 GPIO_PIN_ADDR(4, 5) /*!< Specify PE5 Pin Data Input/Output */
+#define PE6 GPIO_PIN_ADDR(4, 6) /*!< Specify PE6 Pin Data Input/Output */
+#define PE7 GPIO_PIN_ADDR(4, 7) /*!< Specify PE7 Pin Data Input/Output */
+#define PE8 GPIO_PIN_ADDR(4, 8) /*!< Specify PE8 Pin Data Input/Output */
+#define PE9 GPIO_PIN_ADDR(4, 9) /*!< Specify PE9 Pin Data Input/Output */
+#define PE10 GPIO_PIN_ADDR(4, 10) /*!< Specify PE10 Pin Data Input/Output */
+#define PE11 GPIO_PIN_ADDR(4, 11) /*!< Specify PE11 Pin Data Input/Output */
+#define PE12 GPIO_PIN_ADDR(4, 12) /*!< Specify PE12 Pin Data Input/Output */
+#define PE13 GPIO_PIN_ADDR(4, 13) /*!< Specify PE13 Pin Data Input/Output */
+#define PE14 GPIO_PIN_ADDR(4, 14) /*!< Specify PE14 Pin Data Input/Output */
+#define PE15 GPIO_PIN_ADDR(4, 15) /*!< Specify PE15 Pin Data Input/Output */
+
+#define PF0 GPIO_PIN_ADDR(5, 0) /*!< Specify PF0 Pin Data Input/Output */
+#define PF1 GPIO_PIN_ADDR(5, 1) /*!< Specify PF1 Pin Data Input/Output */
+#define PF2 GPIO_PIN_ADDR(5, 2) /*!< Specify PF2 Pin Data Input/Output */
+#define PF3 GPIO_PIN_ADDR(5, 3) /*!< Specify PF3 Pin Data Input/Output */
+#define PF4 GPIO_PIN_ADDR(5, 4) /*!< Specify PF4 Pin Data Input/Output */
+#define PF5 GPIO_PIN_ADDR(5, 5) /*!< Specify PF5 Pin Data Input/Output */
+
+/*@}*/ /* end of group NANO100_GPIO_EXPORTED_CONSTANTS */
+
+/** @addtogroup NANO100_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Clear the interrupt status of specified GPIO pin.
+ */
+#define GPIO_CLR_INT_FLAG(gpio, u32PinMask) ((gpio)->ISRC = u32PinMask)
+
+/**
+ * @brief Disable Pin De-bounce Function
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Disable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
+
+/**
+ * @brief Enable Pin De-bounce Function
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Enable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN |= u32PinMask)
+
+/**
+ * @brief Disable I/O Digital Input Path
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Disable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->OFFD |= (u32PinMask << 16))
+
+/**
+ * @brief Enable I/O Digital Input Path
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Enable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->OFFD &= ~(u32PinMask << 16))
+
+/**
+ * @brief Disable I/O DOUT mask
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Disable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DMASK &= ~u32PinMask)
+
+/**
+ * @brief Enable I/O DOUT mask
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Enable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DMASK |= u32PinMask)
+
+/**
+ * @brief Get GPIO Pin Interrupt Flag
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @retval 0 No interrupt at specified GPIO pin
+ * @retval 1 The specified GPIO pin generate an interrupt
+ *
+ * @details Get the interrupt status of specified GPIO pin.
+ */
+#define GPIO_GET_INT_FLAG(gpio, u32PinMask) ((gpio)->ISRC & u32PinMask)
+
+/**
+ * @brief Set De-bounce Sampling Cycle Time
+ *
+ * @param[in] u32ClkSrc The de-bounce counter clock source. It could be \ref GPIO_DBCLKSRC_HCLK or \ref GPIO_DBCLKSRC_IRC10K
+ * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be \n
+ * \ref GPIO_DBCLKSEL_1, \ref GPIO_DBCLKSEL_2, \ref GPIO_DBCLKSEL_4, \ref GPIO_DBCLKSEL_8, \n
+ * \ref GPIO_DBCLKSEL_16, \ref GPIO_DBCLKSEL_32, \ref GPIO_DBCLKSEL_64, \ref GPIO_DBCLKSEL_128, \n
+ * \ref GPIO_DBCLKSEL_256, \ref GPIO_DBCLKSEL_512, \ref GPIO_DBCLKSEL_1024, \ref GPIO_DBCLKSEL_2048, \n
+ * \ref GPIO_DBCLKSEL_4096, \ref GPIO_DBCLKSEL_8192, \ref GPIO_DBCLKSEL_16384, \ref GPIO_DBCLKSEL_32768
+ *
+ * @return None
+ *
+ * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ * Example: \ref GPIO_SET_DEBOUNCE_TIME(\ref GPIO_DBCLKSRC_IRC10K, \ref GPIO_DBCLKSEL_4) \n
+ * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ * Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us,
+ * and system will sampling interrupt input once per 1600 us.
+ */
+#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBNCECON = (GP_DBNCECON_DBCLK_ON_Msk | u32ClkSrc | u32ClkSel))
+
+/**
+ * @brief Get GPIO Port IN Data
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ *
+ * @retval The specified port data
+ *
+ * @details Get the PIN register of specified GPIO port.
+ */
+#define GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
+
+/**
+ * @brief Set GPIO Port OUT Data
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32Data GPIO port data
+ *
+ * @retval None
+ *
+ * @details Set the Data into specified GPIO port.
+ */
+#define GPIO_SET_OUT_DATA(gpio, u32Data) ((gpio)->DOUT = (u32Data))
+
+/**
+ * @brief Disable Pin Pull-up resistor Function
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Disable the Pull-up resistor function of specified GPIO pin.
+ */
+#define GPIO_DISABLE_PULL_UP(gpio, u32PinMask) ((gpio)->PUEN &= ~u32PinMask)
+
+/**
+ * @brief Enable Pin Pull-up resistor Function
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port
+ *
+ * @return None
+ *
+ * @details Enable the Pull-up resistor function of specified GPIO pin.
+ */
+#define GPIO_ENABLE_PULL_UP(gpio, u32PinMask) ((gpio)->PUEN |= u32PinMask)
+
+/**
+ * @brief Toggle Specified GPIO pin
+ *
+ * @param[in] u32Pin Pxy
+ *
+ * @retval None
+ *
+ * @details Toggle the specified GPIO pint.
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+/**
+ * @brief Enable External GPIO interrupt 0
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32Pin The pin of specified GPIO port
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_EnableEINT0 GPIO_EnableInt
+
+
+/**
+ * @brief Disable External GPIO interrupt 0
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_DisableEINT0 GPIO_DisableInt
+
+
+/**
+ * @brief Enable External GPIO interrupt 1
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32Pin The pin of specified GPIO port
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_EnableEINT1 GPIO_EnableInt
+
+
+/**
+ * @brief Disable External GPIO interrupt 1
+ *
+ * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE or \ref PF
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_DisableEINT1 GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin);
+
+
+
+/*@}*/ /* end of group NANO100_GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_GPIO_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__GPIO_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_i2c.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,296 @@
+/****************************************************************************//**
+ * @file i2c.c
+ * @version V0.10
+ * $Revision: 7 $
+ * $Date: 15/06/05 5:04p $
+ * @brief NANO100 series I2C driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_I2C_Driver I2C Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make I2C module be ready and set the wanted bus clock.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u32BusClock is the target bus speed of I2C module.
+ * @return Actual I2C bus clock frequency.
+ */
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+
+ u32Div = (uint32_t) (((SystemCoreClock * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+ i2c->DIV = u32Div;
+
+ /* Enable I2C */
+ i2c->CON |= I2C_CON_IPEN_Msk;
+
+ return ( SystemCoreClock / ((u32Div+1)<<2) );
+}
+
+/**
+ * @brief This function closes the I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_Close(I2C_T *i2c)
+{
+ /* Reset I2C */
+ if((uint32_t)i2c == I2C0_BASE) {
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_I2C0_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_I2C0_RST_Msk;
+ } else {
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_I2C1_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_I2C1_RST_Msk;
+ }
+
+ /* Disable I2C */
+ i2c->CON &= ~I2C_CON_IPEN_Msk;
+}
+
+/**
+ * @brief This function clears the timeout flag.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_ClearTimeoutFlag(I2C_T *i2c)
+{
+ i2c->INTSTS |= I2C_INTSTS_TIF_Msk;
+}
+
+/**
+ * @brief This function sets the control bit of the I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u8Start sets START bit to I2C module.
+ * @param[in] u8Stop sets STOP bit to I2C module.
+ * @param[in] u8Si sets SI bit to I2C module.
+ * @param[in] u8Ack sets ACK bit to I2C module.
+ * @return none
+ */
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
+{
+ uint32_t u32Reg = 0;
+ uint32_t u32Val = i2c->CON & ~(I2C_STA | I2C_STO | I2C_AA);
+
+ if (u8Start)
+ u32Reg |= I2C_STA;
+ if (u8Stop)
+ u32Reg |= I2C_STO;
+ if (u8Si)
+ u32Reg |= I2C_SI;
+ if (u8Ack)
+ u32Reg |= I2C_AA;
+
+ i2c->CON = u32Val | u32Reg;
+}
+
+/**
+ * @brief This function disables the interrupt of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_DisableInt(I2C_T *i2c)
+{
+ i2c->CON &= ~I2C_CON_INTEN_Msk;
+}
+
+/**
+ * @brief This function enables the interrupt (EI bit) of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_EnableInt(I2C_T *i2c)
+{
+ i2c->CON |= I2C_CON_INTEN_Msk;
+}
+
+/**
+ * @brief This function returns the real bus clock of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return Actual I2C bus clock frequency.
+ */
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
+{
+ uint32_t u32Divider = i2c->DIV;
+
+ return ( SystemCoreClock / ((u32Divider+1)<<2) );
+}
+
+/**
+ * @brief This function sets bus frequency of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u32BusClock is the target bus speed of I2C module.
+ * @return Actual I2C bus clock frequency.
+ */
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+
+ u32Div = (uint32_t) (((SystemCoreClock * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+ i2c->DIV = u32Div;
+
+ return ( SystemCoreClock / ((u32Div+1)<<2) );
+}
+
+/**
+ * @brief This function gets the interrupt flag of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return Interrupt flag.
+ * @retval 0 Flag is not set.
+ * @retval 1 Flag is set.
+ */
+uint32_t I2C_GetIntFlag(I2C_T *i2c)
+{
+ return ( (i2c->INTSTS & I2C_INTSTS_INTSTS_Msk) == I2C_INTSTS_INTSTS_Msk ? 1:0 );
+}
+
+/**
+ * @brief This function clears the interrupt flag of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_ClearIntFlag(I2C_T *i2c)
+{
+ i2c->INTSTS |= I2C_INTSTS_INTSTS_Msk;
+}
+
+/**
+ * @brief This function returns the status of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return I2C status
+ */
+uint32_t I2C_GetStatus(I2C_T *i2c)
+{
+ return ( i2c->STATUS );
+}
+
+/**
+ * @brief This function returns the data stored in data register of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return Data.
+ */
+uint32_t I2C_GetData(I2C_T *i2c)
+{
+ return ( i2c->DATA );
+}
+
+/**
+ * @brief This function writes the data to data register of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u8Data is the data which will be write to data register of I2C module.
+ * @return none
+ */
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
+{
+ i2c->DATA = u8Data;
+}
+
+/**
+ * @brief Configure slave address and enable GC mode.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u8SlaveNo is the set number of salve address.
+ * @param[in] u8SlaveAddr is the slave address.
+ * @param[in] u8GCMode GC mode enable or not. Valid values are:
+ * - \ref I2C_GCMODE_ENABLE
+ * - \ref I2C_GCMODE_DISABLE
+ * @return none
+ */
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
+{
+ switch (u8SlaveNo) {
+ case 0:
+ i2c->SADDR0 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ case 1:
+ i2c->SADDR1 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ }
+}
+
+/**
+ * @brief Configure the mask of slave address. The corresponding address bit is "Don't Care".
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u8SlaveNo is the set number of salve address.
+ * @param[in] u8SlaveAddrMask is the slave address mask.
+ * @return none
+ */
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
+{
+ switch (u8SlaveNo) {
+ case 0:
+ i2c->SAMASK0 = u8SlaveAddrMask << 1;
+ break;
+ case 1:
+ i2c->SAMASK1 = u8SlaveAddrMask << 1;
+ break;
+ }
+}
+
+/**
+ * @brief This function enables timeout function and configures DIV4 function to support long timeout.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u8LongTimeout Enable timeout counter input clock is divide by 4.
+ * @return none
+ */
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
+{
+ if(u8LongTimeout)
+ i2c->TOUT |= I2C_TOUT_DIV4_Msk;
+ else
+ i2c->TOUT &= ~I2C_TOUT_DIV4_Msk;
+
+ i2c->TOUT |= I2C_TOUT_TOUTEN_Msk;
+}
+
+/**
+ * @brief This function disables timeout function.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_DisableTimeout(I2C_T *i2c)
+{
+ i2c->TOUT &= ~I2C_TOUT_TOUTEN_Msk;
+}
+
+/**
+ * @brief This function enables the wakeup function of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_EnableWakeup(I2C_T *i2c)
+{
+ i2c->WKUPCON |= I2C_WKUPCON_WKUPEN_Msk;
+}
+
+/**
+ * @brief This function disables the wakeup function of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ */
+void I2C_DisableWakeup(I2C_T *i2c)
+{
+ i2c->WKUPCON &= ~I2C_WKUPCON_WKUPEN_Msk;
+}
+
+/*@}*/ /* end of group NANO100_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_I2C_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_i2c.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,181 @@
+/****************************************************************************//**
+ * @file i2c.h
+ * @version V1.00
+ * $Revision: 5 $
+ * $Date: 15/06/05 5:06p $
+ * @brief Nano100 series I2C driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_I2C_Driver I2C Driver
+ @{
+*/
+
+/** @addtogroup NANO100_I2C_EXPORTED_CONSTANTS I2C Exported Constants
+ @{
+*/
+
+#define I2C_STA 0x08 /*!< I2C START bit value */
+#define I2C_STO 0x04 /*!< I2C STOP bit value*/
+#define I2C_SI 0x10 /*!< I2C SI bit value */
+#define I2C_AA 0x02 /*!< I2C ACK bit value */
+
+#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */
+#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */
+
+/*@}*/ /* end of group NANO100_I2C_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro sets the I2C control register at one time.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u8Ctrl is the register value of I2C control register.
+ * @return none
+ * \hideinitializer
+ */
+#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ( (i2c)->CON = ((i2c)->CON & ~0x1e) | u8Ctrl )
+
+/**
+ * @brief This macro only set START bit to the control register of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2C_START(i2c) ( (i2c)->CON = ((i2c)->CON & ~I2C_CON_I2C_STS_Msk) | I2C_CON_START_Msk )
+
+/**
+ * @brief This macro only set STOP bit to the control register of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ * \hideinitializer
+ */
+static __INLINE void I2C_STOP(I2C_T *i2c)
+{
+ i2c->CON |= (I2C_CON_I2C_STS_Msk | I2C_CON_STOP_Msk);
+ while(i2c->CON & I2C_CON_STOP_Msk);
+}
+
+/**
+ * @brief This macro will return when I2C module is ready.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ * \hideinitializer
+ */
+static __INLINE void I2C_WAIT_READY(I2C_T *i2c)
+{
+ while(!(i2c->INTSTS & I2C_INTSTS_INTSTS_Msk));
+ i2c->INTSTS |= I2C_INTSTS_INTSTS_Msk;
+}
+
+/**
+ * @brief This macro returns the data stored in data register of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return Data.
+ * \hideinitializer
+ */
+#define I2C_GET_DATA(i2c) ( (i2c)->DATA )
+
+/**
+ * @brief This macro writes the data to data register of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @param[in] u8Data is the data which will be write to data register of I2C module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2C_SET_DATA(i2c, u8Data) ( (i2c)->DATA = u8Data )
+
+/**
+ * @brief This macro returns the status of I2C module.
+ * @param[in] i2c is the base address of I2C module.
+ * @return Status.
+ * \hideinitializer
+ */
+#define I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
+
+/**
+ * @brief This macro returns timeout flag.
+ * @param[in] i2c is the base address of I2C module.
+ * @return Status.
+ * @retval 0 Flag is not set.
+ * @retval 1 Flag is set.
+ * \hideinitializer
+ */
+#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->INTSTS & I2C_INTSTS_TIF_Msk) == I2C_INTSTS_TIF_Msk ? 1:0 )
+
+/**
+ * @brief This macro clears timeout flag.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2C_CLEAR_TIMEOUT_FLAG(i2c) ( (i2c)->INTSTS |= I2C_INTSTS_TIF_Msk )
+
+/**
+ * @brief This macro returns wakeup flag.
+ * @param[in] i2c is the base address of I2C module.
+ * @return Status.
+ * @retval 0 Flag is not set.
+ * @retval 1 Flag is set.
+ * \hideinitializer
+ */
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKUPSTS & I2C_WKUPSTS_WKUPIF_Msk) == I2C_WKUPSTS_WKUPIF_Msk ? 1:0 )
+
+/**
+ * @brief This macro clears wakeup flag.
+ * @param[in] i2c is the base address of I2C module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->WKUPSTS |= I2C_WKUPSTS_WKUPIF_Msk )
+
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
+void I2C_Close(I2C_T *i2c);
+void I2C_ClearTimeoutFlag(I2C_T *i2c);
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
+void I2C_DisableInt(I2C_T *i2c);
+void I2C_EnableInt(I2C_T *i2c);
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
+uint32_t I2C_GetIntFlag(I2C_T *i2c);
+void I2C_ClearIntFlag(I2C_T *i2c);
+uint32_t I2C_GetStatus(I2C_T *i2c);
+uint32_t I2C_GetData(I2C_T *i2c);
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
+void I2C_DisableTimeout(I2C_T *i2c);
+void I2C_EnableWakeup(I2C_T *i2c);
+void I2C_DisableWakeup(I2C_T *i2c);
+
+/*@}*/ /* end of group NANO100_I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_I2C_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__I2C_H__
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_i2s.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,204 @@
+/**************************************************************************//**
+ * @file i2s.c
+ * @version V1.00
+ * $Revision: 4 $
+ * $Date: 15/06/08 4:58p $
+ * @brief Nano100 series I2S driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include <stdio.h>
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_I2S_Driver I2S Driver
+ @{
+*/
+
+/** @addtogroup NANO100_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+ @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+/**
+ * @brief This function is used to get I2S source clock frequency.
+ * @param[in] i2s is the base address of I2S module.
+ * @return I2S source clock frequency (Hz).
+ */
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
+{
+ uint32_t u32Freq, u32ClkSrcSel;
+
+ // get I2S selection clock source
+ u32ClkSrcSel = CLK->CLKSEL2 & CLK_CLKSEL2_I2S_S_Msk;
+
+ switch (u32ClkSrcSel) {
+ case CLK_CLKSEL2_I2S_S_HXT:
+ u32Freq = __HXT;
+ break;
+
+ case CLK_CLKSEL2_I2S_S_PLL:
+ u32Freq = CLK_GetPLLClockFreq();
+ break;
+
+ case CLK_CLKSEL2_I2S_S_HIRC:
+ u32Freq = __HIRC;
+ break;
+
+ default:
+ u32Freq = __HIRC;
+ break;
+ }
+
+ return u32Freq;
+}
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/**
+ * @brief This function configures some parameters of I2S interface for general purpose use.
+ * The sample rate may not be used from the parameter, it depends on system's clock settings,
+ * but real sample rate used by system will be returned for reference.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32MasterSlave I2S operation mode. Valid values are:
+ * - \ref I2S_MODE_MASTER
+ * - \ref I2S_MODE_SLAVE
+ * @param[in] u32SampleRate Sample rate
+ * @param[in] u32WordWidth Data length. Valid values are:
+ * - \ref I2S_DATABIT_8
+ * - \ref I2S_DATABIT_16
+ * - \ref I2S_DATABIT_24
+ * - \ref I2S_DATABIT_32
+ * @param[in] u32Channels: Audio format. Valid values are:
+ * - \ref I2S_MONO
+ * - \ref I2S_STEREO
+ * @param[in] u32DataFormat: Data format. Valid values are:
+ * - \ref I2S_FORMAT_I2S
+ * - \ref I2S_FORMAT_MSB
+ * @param[in] u32AudioInterface: Audio interface. Valid values are:
+ * - \ref I2S_I2S
+ * @return Real sample rate.
+ */
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface)
+{
+ uint8_t u8Divider;
+ uint32_t u32BitRate, u32SrcClk;
+
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_I2S_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_I2S_RST_Msk;
+
+ i2s->CTRL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat | u32AudioInterface | I2S_FIFO_TX_LEVEL_WORD_4 | I2S_FIFO_RX_LEVEL_WORD_4;
+
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);
+
+ u32BitRate = u32SampleRate * (((u32WordWidth>>4) & 0x3) + 1) * 16;
+ u8Divider = ((u32SrcClk/u32BitRate) >> 1) - 1;
+ i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLK_DIV_Msk) | (u8Divider << 8);
+
+ //calculate real sample rate
+ u32BitRate = u32SrcClk / (2*(u8Divider+1));
+ u32SampleRate = u32BitRate / ((((u32WordWidth>>4) & 0x3) + 1) * 16);
+
+ i2s->CTRL |= I2S_CTRL_I2SEN_Msk;
+
+ return u32SampleRate;
+}
+
+/**
+ * @brief Disable I2S function and I2S clock.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ */
+void I2S_Close(I2S_T *i2s)
+{
+ i2s->CTRL &= ~I2S_CTRL_I2SEN_Msk;
+}
+
+/**
+ * @brief This function enables the interrupt according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * @return none
+ */
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+ i2s->INTEN |= u32Mask;
+}
+
+/**
+ * @brief This function disables the interrupt according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * @return none
+ */
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+ i2s->INTEN &= ~u32Mask;
+}
+
+/**
+ * @brief Enable MCLK .
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32BusClock is the target MCLK clock
+ * @return Actual MCLK clock
+ */
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
+{
+ uint8_t u8Divider;
+ uint32_t u32SrcClk, u32Reg;
+
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);
+ if (u32BusClock == u32SrcClk)
+ u8Divider = 0;
+ else
+ u8Divider = (u32SrcClk/u32BusClock) >> 1;
+
+ i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLK_DIV_Msk) | u8Divider;
+
+ i2s->CTRL |= I2S_CTRL_MCLKEN_Msk;
+
+ u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLK_DIV_Msk;
+
+ if (u32Reg == 0)
+ return u32SrcClk;
+ else
+ return ((u32SrcClk >> 1) / u32Reg);
+}
+
+/**
+ * @brief Disable MCLK .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ */
+void I2S_DisableMCLK(I2S_T *i2s)
+{
+ i2s->CTRL &= ~I2S_CTRL_MCLKEN_Msk;
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ i2s->CTRL = (i2s->CTRL & ~(I2S_CTRL_TXTH_Msk | I2S_CTRL_RXTH_Msk) |
+ (u32TxThreshold << I2S_CTRL_TXTH_Pos) |
+ (u32RxThreshold << I2S_CTRL_RXTH_Pos));
+}
+/*@}*/ /* end of group NANO100_I2S_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_I2S_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_i2s.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,296 @@
+/**************************************************************************//**
+ * @file i2s.h
+ * @version V1.00
+ * $Revision: 5 $
+ * $Date: 15/06/08 4:59p $
+ * @brief Nano100 series I2S driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __I2S_H__
+#define __I2S_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_I2S_Driver I2S Driver
+ @{
+*/
+
+/** @addtogroup NANO100_I2S_EXPORTED_CONSTANTS I2S Exported Constants
+ @{
+*/
+#define I2S_DATABIT_8 (0 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 8-bit */
+#define I2S_DATABIT_16 (1 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 16-bit */
+#define I2S_DATABIT_24 (2 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 24-bit */
+#define I2S_DATABIT_32 (3 << I2S_CTRL_WORDWIDTH_Pos) /*!< I2S data width is 32-bit */
+
+/* Audio Format */
+#define I2S_MONO I2S_CTRL_MONO_Msk /*!< Mono channel */
+#define I2S_STEREO 0 /*!< Stereo channel */
+
+/* I2S Data Format */
+#define I2S_FORMAT_MSB I2S_CTRL_FORMAT_Msk /*!< MSB data format */
+#define I2S_FORMAT_I2S 0 /*!< I2S data format */
+
+/* I2S Interface */
+#define I2S_I2S 0 /*!< I2S interface is selected */
+
+/* I2S Operation mode */
+#define I2S_MODE_SLAVE I2S_CTRL_SLAVE_Msk /*!< As slave mode */
+#define I2S_MODE_MASTER 0 /*!< As master mode */
+
+/* I2S FIFO Threshold */
+#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */
+#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 1 word */
+#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 2 words */
+#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 3 words */
+#define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 4 words */
+#define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 5 words */
+#define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 6 words */
+#define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTRL_TXTH_Pos) /*!< TX threshold is 7 words */
+
+#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */
+#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 2 words */
+#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 3 words */
+#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 4 words */
+#define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 5 words */
+#define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 6 words */
+#define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 7 words */
+#define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTRL_RXTH_Pos) /*!< RX threshold is 8 words */
+
+/* I2S Record Channel */
+#define I2S_MONO_RIGHT 0 /*!< Record mono right channel */
+#define I2S_MONO_LEFT I2S_CTRL_RXLCH_Msk /*!< Record mono left channel */
+
+/* I2S Channel */
+#define I2S_RIGHT 0 /*!< Select right channel */
+#define I2S_LEFT 1 /*!< Select left channel */
+
+/*@}*/ /* end of group NANO100_I2S_EXPORTED_CONSTANTS */
+
+/** @addtogroup NANO100_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+ @{
+*/
+/**
+ * @brief Enable zero cross detect function.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32ChMask is the mask for left or right channel. Valid values are:
+ * - \ref I2S_RIGHT
+ * - \ref I2S_LEFT
+ * @return none
+ * \hideinitializer
+ */
+static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+ if(u32ChMask == I2S_RIGHT)
+ i2s->CTRL |= I2S_CTRL_RCHZCEN_Msk;
+ else
+ i2s->CTRL |= I2S_CTRL_LCHZCEN_Msk;
+}
+
+/**
+ * @brief Disable zero cross detect function.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32ChMask is the mask for left or right channel. Valid values are:
+ * - \ref I2S_RIGHT
+ * - \ref I2S_LEFT
+ * @return none
+ * \hideinitializer
+ */
+static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+ if(u32ChMask == I2S_RIGHT)
+ i2s->CTRL &= ~I2S_CTRL_RCHZCEN_Msk;
+ else
+ i2s->CTRL &= ~I2S_CTRL_LCHZCEN_Msk;
+}
+
+/**
+ * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTRL |= I2S_CTRL_TXDMA_Msk )
+
+/**
+ * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_TXDMA_Msk )
+
+/**
+ * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTRL |= I2S_CTRL_RXDMA_Msk )
+
+/**
+ * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_RXDMA_Msk )
+
+/**
+ * @brief Enable I2S Tx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_TX(i2s) ( (i2s)->CTRL |= I2S_CTRL_TXEN_Msk )
+
+/**
+ * @brief Disable I2S Tx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_TX(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_TXEN_Msk )
+
+/**
+ * @brief Enable I2S Rx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_RX(i2s) ( (i2s)->CTRL |= I2S_CTRL_RXEN_Msk )
+
+/**
+ * @brief Disable I2S Rx function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_RX(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_RXEN_Msk )
+
+/**
+ * @brief Enable Tx Mute function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTRL |= I2S_CTRL_MUTE_Msk )
+
+/**
+ * @brief Disable Tx Mute function .
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTRL &= ~I2S_CTRL_MUTE_Msk )
+
+/**
+ * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTRL |= I2S_CTRL_CLR_TXFIFO_Msk )
+
+/**
+ * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
+ * @param[in] i2s is the base address of I2S module.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTRL |= I2S_CTRL_CLR_RXFIFO_Msk )
+
+/**
+ * @brief This function sets the recording source channel when mono mode is used.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Ch left or right channel. Valid values are:
+ * - \ref I2S_MONO_LEFT
+ * - \ref I2S_MONO_RIGHT
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_SET_MONO_RX_CHANNEL(i2s, u32Ch) ( u32Ch == I2S_MONO_LEFT ? ((i2s)->CTRL |= I2S_CTRL_RXLCH_Msk) : ((i2s)->CTRL &= ~I2S_CTRL_RXLCH_Msk) )
+
+/**
+ * @brief Write data to I2S Tx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Data The data written to FIFO.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = u32Data )
+
+/**
+ * @brief Read Rx FIFO.
+ * @param[in] i2s is the base address of I2S module.
+ * @return Data in Rx FIFO.
+ * \hideinitializer
+ */
+#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
+
+/**
+ * @brief This function gets the interrupt flag according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the mask for the all interrupt flags.
+ * @return The masked bit value of interrupt flag.
+ * \hideinitializer
+ */
+#define I2S_GET_INT_FLAG(i2s, u32Mask) ((i2s)->STATUS & (u32Mask))
+
+/**
+ * @brief This function clears the interrupt flag according to the mask parameter.
+ * @param[in] i2s is the base address of I2S module.
+ * @param[in] u32Mask is the mask for the all interrupt flags.
+ * @return none
+ * \hideinitializer
+ */
+#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS |= (u32Mask) )
+
+/**
+ * @brief Get transmit FIFO level
+ * @param[in] i2s is the base address of I2S module.
+ * @return FIFO level
+ * \hideinitializer
+ */
+#define I2S_GET_TX_FIFO_LEVEL(i2s) ((((i2s)->STATUS & I2S_STATUS_TX_LEVEL_Msk) >> I2S_STATUS_TX_LEVEL_Pos) & 0xF)
+
+/**
+ * @brief Get receive FIFO level
+ * @param[in] i2s is the base address of I2S module.
+ * @return FIFO level
+ * \hideinitializer
+ */
+#define I2S_GET_RX_FIFO_LEVEL(i2s) ((((i2s)->STATUS & I2S_STATUS_RX_LEVEL_Msk) >> I2S_STATUS_RX_LEVEL_Pos) & 0xF)
+
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface);
+void I2S_Close(I2S_T *i2s);
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
+void I2S_DisableMCLK(I2S_T *i2s);
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+
+/*@}*/ /* end of group NANO100_I2S_EXPORTED_FUNCTIONS */
+
+
+/*@}*/ /* end of group NANO100_I2S_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__I2S_H__
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_lcd.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,434 @@
+/**************************************************************************//**
+ * @file lcd.c
+ * @version V1.00
+ * $Revision: 9 $
+ * $Date: 15/07/06 2:08p $
+ * @brief Nano100 series LCD driver header file
+ * The LCD driver can directly drives a LCD glass by creating the ac
+ * segment and common voltage signals automatically. It can support
+ * static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty, 1/6 duty LCD glass with up to 34
+ * segments with 6 COM or 36 segments with 4 COM.
+ *
+ * @note
+ * Copyright (C) 2013~2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include "Nano100Series.h"
+
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_LCD_Driver LCD Driver
+ @{
+*/
+
+
+/// @cond HIDDEN_SYMBOLS
+
+/** @addtogroup NANO100_LCD_EXPORTED_VARIABLES LCD Exported Variables
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables */
+/*---------------------------------------------------------------------------------------------------------*/
+
+double g_LCDFreq;
+static uint32_t g_LCDFrameRate; /* src:32768Hz, COM:4, FREQ Div:64, frame-rate 64Hz */
+/* src:10240Hz, COM:4, FREQ Div:32, frame-rate 40Hz */
+
+
+/*@}*/ /* end of group NANO100_LCD_EXPORTED_VARIABLES */
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/** @addtogroup NANO100_LCD_EXPORTED_FUNCTIONS LCD Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enables a segment on the LCD display
+ *
+ * @param[in] u32Com COM number
+ * @param[in] u32Seg Segment number
+ * @param[in] u32OnFlag 1: segment display
+ * 0: segment not display
+ *
+ * @return None
+ *
+ */
+void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag)
+{
+ int32_t memnum = u32Seg / 4;
+ int32_t seg_shift = 8*(u32Seg-(4*memnum));
+
+ if(u32OnFlag) {
+ if(memnum==0) {
+ LCD->MEM_0 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==1) {
+ LCD->MEM_1 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==2) {
+ LCD->MEM_2 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==3) {
+ LCD->MEM_3 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==4) {
+ LCD->MEM_4 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==5) {
+ LCD->MEM_5 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==6) {
+ LCD->MEM_6 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==7) {
+ LCD->MEM_7 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==8) {
+ LCD->MEM_8 |= (1<<u32Com)<<seg_shift;
+ } else if(memnum==9) {
+ LCD->MEM_9 |= (1<<u32Com)<<seg_shift;
+ }
+ } else {
+ if(memnum==0) {
+ LCD->MEM_0 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==1) {
+ LCD->MEM_1 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==2) {
+ LCD->MEM_2 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==3) {
+ LCD->MEM_3 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==4) {
+ LCD->MEM_4 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==5) {
+ LCD->MEM_5 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==6) {
+ LCD->MEM_6 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==7) {
+ LCD->MEM_7 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==8) {
+ LCD->MEM_8 &= ~((1<<u32Com)<<seg_shift);
+ } else if(memnum==9) {
+ LCD->MEM_9 &= ~((1<<u32Com)<<seg_shift);
+ }
+
+ }
+
+ if(CyclesPerUs > 0)
+ SysTick->LOAD = 300 * CyclesPerUs;
+ else
+ SysTick->LOAD = 15;
+ SysTick->VAL = (0x00);
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
+}
+
+/**
+ * @brief LCD Enable/Disable all segments
+ *
+ * @param[in] u32OnOff 1: Enable all segments
+ * 0: Disable all segment
+ *
+ * @return None
+ *
+ */
+void LCD_SetAllPixels(uint32_t u32OnOff)
+{
+ uint32_t u32SetValue;
+
+ if(u32OnOff) {
+ u32SetValue = 0xFFFFFFFF;
+ } else {
+ u32SetValue = 0x00000000;
+ }
+
+ LCD->MEM_0 = u32SetValue;
+ LCD->MEM_1 = u32SetValue;
+ LCD->MEM_2 = u32SetValue;
+ LCD->MEM_3 = u32SetValue;
+ LCD->MEM_4 = u32SetValue;
+ LCD->MEM_5 = u32SetValue;
+ LCD->MEM_6 = u32SetValue;
+ LCD->MEM_7 = u32SetValue;
+ LCD->MEM_8 = u32SetValue;
+
+ if(CyclesPerUs > 0)
+ SysTick->LOAD = 300 * CyclesPerUs;
+ else
+ SysTick->LOAD = 15;
+ SysTick->VAL = (0x00);
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
+}
+
+
+/**
+ * @brief Set Frame Count and Enable frame count
+ *
+ * @param[in] u32Count Frame count value
+ *
+ *
+ * @return real frame count value.
+ *
+ */
+uint32_t LCD_EnableFrameCounter(uint32_t u32Count)
+{
+ uint32_t div = 1; // default prediv == LCD_FCPRESC_DIV1
+
+ LCD->FCR = 0x00;
+ LCD->FCSTS |= LCD_FCSTS_FCSTS_Msk; // clear fcsts flag
+
+ if(u32Count == 0) return 0;
+
+ if(u32Count > 0x3F) { // top value max. 63 = 0x3F
+ div = u32Count/64;
+
+ if(div > 3) {
+ div = 8;
+ LCD->FCR = LCD->FCR & ~LCD_FCR_PRESCL_Msk | LCD_FCPRESC_DIV8;
+ } else if(div > 1) {
+ div = 4;
+ LCD->FCR = LCD->FCR & ~LCD_FCR_PRESCL_Msk | LCD_FCPRESC_DIV4;
+ } else {
+ div = 2;
+ LCD->FCR = LCD->FCR & ~LCD_FCR_PRESCL_Msk | LCD_FCPRESC_DIV2;
+ }
+
+ u32Count = (u32Count+(div/2))/div;
+ } else {
+ div = 1;
+ LCD->FCR = LCD->FCR & ~LCD_FCR_PRESCL_Msk | LCD_FCPRESC_DIV1;
+ }
+
+ LCD->FCR = LCD->FCR & ~LCD_FCR_FCV_Msk | (u32Count << LCD_FCR_FCV_Pos);
+
+ u32Count = u32Count*div;
+
+ LCD->FCR |= LCD_FCR_FCEN_Msk; // enable LCD frame count
+
+ return u32Count;
+}
+
+/**
+ * @brief Disable frame count function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+void LCD_DisableFrameCounter(void)
+{
+ LCD->FCR = 0x00; // disable LCD frame count
+
+ if( LCD->FCSTS & LCD_FCSTS_FCSTS_Msk) // clear status flag
+ LCD->FCSTS = LCD_FCSTS_FCSTS_Msk;
+}
+
+
+/**
+ * @brief LCD Initialization routine.
+ *
+ * @param[in] u32DrivingType LCD driving type: \ref LCD_C_TYPE / \ref LCD_EXTERNAL_R_TYPE / \ref LCD_INTERNAL_R_TYPE / \ref LCD_EXTERNAL_C_TYPE
+ * @param[in] u32ComNum LCD Com number: 1 ~6
+ * @param[in] u32BiasLevel LCD bias level: \ref LCD_BIAS_STATIC / \ref LCD_BIAS_HALF / \ref LCD_BIAS_THIRD
+ * @param[in] u32FramerateDiv LCD frequency divider: \ref LCD_FREQ_DIV32 / \ref LCD_FREQ_DIV64 / \ref LCD_FREQ_DIV96 / \ref LCD_FREQ_DIV128 /
+ * \ref LCD_FREQ_DIV192/ \ref LCD_FREQ_DIV256 / \ref LCD_FREQ_DIV384 / \ref LCD_FREQ_DIV512
+ * @param[in] u32DrivingVol LCD charge pump driving voltage: \ref LCD_CPVOl_2_6V / \ref LCD_CPVOl_2_7V / \ref LCD_CPVOl_2_8V / \ref LCD_CPVOl_2_9V /
+ * \ref LCD_CPVOl_3V / \ref LCD_CPVOl_3_1V / \ref LCD_CPVOl_3_2V / \ref LCD_CPVOl_3_3V
+ *
+ * @return LCD frame rate.
+ *
+ */
+uint32_t LCD_Open(uint32_t u32DrivingType, uint32_t u32ComNum, uint32_t u32BiasLevel, uint32_t u32FramerateDiv, uint32_t u32DrivingVol)
+{
+ uint32_t clkdiv, muldiv;
+ uint32_t lcd_freq_div[] = {32, 64, 96, 128, 192, 256, 384, 512};
+ uint32_t multiplex_freq_div[] = {2, 4, 6, 8, 10, 12};
+ uint32_t u32clk_src;
+
+ /* IP reset */
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_LCD_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_LCD_RST_Msk;
+
+ LCD_DisableDisplay();
+
+ /* Turn all segments off */
+ LCD_SetAllPixels(0);
+
+
+ switch(u32DrivingType) {
+ case LCD_C_TYPE:
+ case LCD_EXTERNAL_C_TYPE:
+
+ LCD->DISPCTL &= ~LCD_DISPCTL_BV_SEL_Msk; // internal source for charge pump
+ LCD->DISPCTL = LCD->DISPCTL & ~LCD_DISPCTL_CPUMP_FREQ_Msk | (LCD_CPUMP_DIV1);
+ LCD->DISPCTL = LCD->DISPCTL & ~LCD_DISPCTL_CPUMP_VOL_SET_Msk | (u32DrivingVol);
+ LCD->DISPCTL &= ~LCD_DISPCTL_IBRL_EN_Msk;
+ LCD->DISPCTL |= LCD_DISPCTL_CPUMP_EN_Msk; // enable charge pump
+
+ break;
+
+ case LCD_EXTERNAL_R_TYPE:
+ case LCD_INTERNAL_R_TYPE:
+
+ LCD->DISPCTL &= ~LCD_DISPCTL_CPUMP_EN_Msk;
+ LCD->DISPCTL |= LCD_DISPCTL_BV_SEL_Msk;
+ LCD->DISPCTL &= ~LCD_DISPCTL_IBRL_EN_Msk;
+ LCD->DISPCTL |= (u32DrivingType == LCD_INTERNAL_R_TYPE)?LCD_DISPCTL_IBRL_EN_Msk:0;
+ break;
+
+ };
+
+ LCD->CTL &= ~LCD_CTL_FREQ_Msk;
+ LCD->CTL |= u32FramerateDiv;
+
+ LCD->CTL = (LCD->CTL & ~LCD_CTL_MUX_Msk) | ((u32ComNum - 1) << LCD_CTL_MUX_Pos);
+ LCD->DISPCTL = LCD->DISPCTL & ~LCD_DISPCTL_BIAS_SEL_Msk | u32BiasLevel;
+
+ if((CLK->CLKSEL1 & CLK_CLKSEL1_LCD_S_Msk) == 0)
+ u32clk_src = 32 * 1024;
+ else
+ u32clk_src = 10 * 1024;
+
+ clkdiv = (LCD->CTL & LCD_CTL_FREQ_Msk) >> LCD_CTL_FREQ_Pos;
+ muldiv = (LCD->CTL & LCD_CTL_MUX_Msk) >> LCD_CTL_MUX_Pos;
+
+ g_LCDFreq = (double)u32clk_src / lcd_freq_div[clkdiv];
+ g_LCDFrameRate = (uint32_t)g_LCDFreq / multiplex_freq_div[muldiv];
+
+ return g_LCDFrameRate;
+}
+
+
+
+/**
+ * @brief The function is used to disable LCD controller.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+void LCD_Close(void)
+{
+ LCD_DisableDisplay();
+}
+
+
+/**
+ * @brief Enable Blink function in LCD controller
+ *
+ * @param[in] u32ms Blinking display time(unit: ms).
+ *
+ * @return Real blinking delay time(ms).
+ *
+ */
+uint32_t LCD_EnableBlink(uint32_t u32ms)
+{
+ uint32_t prescale=LCD_FCPRESC_DIV1, div=1;
+ uint32_t framecount;
+
+ if((1000/u32ms) > g_LCDFrameRate) u32ms = (1000/g_LCDFrameRate);
+
+ framecount = (uint32_t) (u32ms / (1000/g_LCDFrameRate)) ;
+
+ if(framecount > 0x3F) {
+ for(div=2; div<=8; div*=2) {
+ framecount = (uint32_t) (u32ms / (1000/(g_LCDFrameRate/div)) );
+
+ if( framecount <= 0x40 )
+ break;
+ }
+ if(div==2) prescale = LCD_FCPRESC_DIV2;
+ else if(div==4) prescale = LCD_FCPRESC_DIV4;
+ else if(div==8) prescale = LCD_FCPRESC_DIV8;
+ else return 0;
+ } else if(framecount == 0) {
+ framecount = 1;
+ }
+
+ LCD->FCR = LCD->FCR & ~LCD_FCR_PRESCL_Msk | prescale;
+ LCD->FCR = LCD->FCR & ~LCD_FCR_FCV_Msk | ((framecount - 1) << LCD_FCR_FCV_Pos);
+ LCD->FCR |= LCD_FCR_FCEN_Msk;
+
+ /* Enable Blink LCD */
+ LCD->CTL |= LCD_CTL_BLINK_Msk;
+
+ return ( (framecount*1000)/(g_LCDFrameRate/div) );
+}
+
+
+/**
+ * @brief Disable Blink function in LCD controller
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+void LCD_DisableBlink(void)
+{
+ /* Disable Blink LCD */
+ LCD->CTL &= ~LCD_CTL_BLINK_Msk;
+
+ /* Disable frame count */
+ LCD->FCR = 0x00; // disable LCD frame count
+
+ if( LCD->FCSTS & LCD_FCSTS_FCSTS_Msk) // clear status flag
+ LCD->FCSTS = LCD_FCSTS_FCSTS_Msk;
+
+}
+
+/**
+ * @brief This function is used to enable LCD interrupt
+ *
+ * @param[in] IntSrc Interrupt Source: \ref LCD_FRAMECOUNT_INT / \ref LCD_POWERDOWN_INT / \ref LCD_ALL_INT
+ *
+ * @return None
+ *
+ */
+void LCD_EnableInt(uint32_t IntSrc)
+{
+ if((IntSrc & LCD_FRAMECOUNT_INT) == LCD_FRAMECOUNT_INT ) {
+ LCD->FCR |= LCD_FCR_FCEN_Msk;
+ }
+
+ if((IntSrc & LCD_POWERDOWN_INT) == LCD_POWERDOWN_INT ) {
+ LCD->CTL |= LCD_CTL_PDINT_EN_Msk;
+ }
+
+}
+
+/**
+ * @brief This function is used to disable LCD specified interrupt
+ *
+ * @param[in] IntSrc Interrupt Source: \ref LCD_FRAMECOUNT_INT / \ref LCD_POWERDOWN_INT / \ref LCD_ALL_INT
+ *
+ * @return None
+ *
+ */
+void LCD_DisableInt(uint32_t IntSrc)
+{
+ if((IntSrc & LCD_FRAMECOUNT_INT) == LCD_FRAMECOUNT_INT ) {
+ LCD->FCR &= ~LCD_FCR_FCEN_Msk;
+ LCD->FCSTS = LCD_FCSTS_FCSTS_Msk;
+ }
+
+ if((IntSrc & LCD_POWERDOWN_INT) == LCD_POWERDOWN_INT ) {
+ LCD->CTL &= ~LCD_CTL_PDINT_EN_Msk;
+ LCD->FCSTS = LCD_FCSTS_PDSTS_Msk;
+ }
+}
+
+/*@}*/ /* end of group NANO100_LCD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_LCD_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013~2014 Nuvoton Technology Corp. ***/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_lcd.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,225 @@
+/****************************************************************************//**
+ * @file lcd.h
+ * @version V1.00
+ * $Revision: 5 $
+ * $Date: 15/06/26 1:30p $
+ * @brief Nano100 series I2C driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __LCD_H__
+#define __LCD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+//#include <stdbool.h>
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_LCD_Driver LCD Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_LCD_EXPORTED_CONSTANTS LCD Exported Constants
+ @{
+*/
+
+/// @cond
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro, type and constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/// @endcond
+
+#define LCD_FREQ_DIV32 ((uint32_t) 0x00000000) /*!< Clock source (32 or 10KHz) divide by 32 */
+#define LCD_FREQ_DIV64 ((uint32_t) 0x00000010) /*!< Clock source (32 or 10KHz) divide by 64 */
+#define LCD_FREQ_DIV96 ((uint32_t) 0x00000020) /*!< Clock source (32 or 10KHz) divide by 96 */
+#define LCD_FREQ_DIV128 ((uint32_t) 0x00000030) /*!< Clock source (32 or 10KHz) divide by 128 */
+#define LCD_FREQ_DIV192 ((uint32_t) 0x00000040) /*!< Clock source (32 or 10KHz) divide by 192 */
+#define LCD_FREQ_DIV256 ((uint32_t) 0x00000050) /*!< Clock source (32 or 10KHz) divide by 256 */
+#define LCD_FREQ_DIV384 ((uint32_t) 0x00000060) /*!< Clock source (32 or 10KHz) divide by 384 */
+#define LCD_FREQ_DIV512 ((uint32_t) 0x00000070) /*!< Clock source (32 or 10KHz) divide by 512 */
+
+#define LCD_MUX_STATIC ((uint32_t) 0x00000000) /*!< Static multiplexing */
+#define LCD_MUX_ONE_SECOND ((uint32_t) 0x00000002) /*!< Duplex multiplexing */
+#define LCD_MUX_ONE_THIRD ((uint32_t) 0x00000004) /*!< Triplex multiplexing */
+#define LCD_MUX_ONE_FOURTH ((uint32_t) 0x00000006) /*!< Quadruplex multiplexing */
+#define LCD_MUX_ONE_FIFTH ((uint32_t) 0x00000008) /*!< 1/5 duty */
+#define LCD_MUX_ONE_SIXTH ((uint32_t) 0x0000000A) /*!< 1/6 duty */
+
+#define LCD_BIAS_STATIC ((uint32_t) 0x00000000) /*!< Static bias */
+#define LCD_BIAS_HALF ((uint32_t) 0x00000002) /*!< 1/2 bias */
+#define LCD_BIAS_THIRD ((uint32_t) 0x00000004) /*!< 1/3 bias */
+
+#define LCD_CPUMP_DIV1 ((uint32_t) 0x00000000) /*!< Clock source (32 or 10KHz) divide by 1 and is used by analog component */
+#define LCD_CPUMP_DIV2 ((uint32_t) 0x00000800) /*!< Clock source (32 or 10KHz) divide by 2 */
+#define LCD_CPUMP_DIV4 ((uint32_t) 0x00001000) /*!< Clock source (32 or 10KHz) divide by 4 */
+#define LCD_CPUMP_DIV8 ((uint32_t) 0x00001800) /*!< Clock source (32 or 10KHz) divide by 8 */
+#define LCD_CPUMP_DIV16 ((uint32_t) 0x00002000) /*!< Clock source (32 or 10KHz) divide by 16 */
+#define LCD_CPUMP_DIV32 ((uint32_t) 0x00002800) /*!< Clock source (32 or 10KHz) divide by 32 */
+#define LCD_CPUMP_DIV64 ((uint32_t) 0x00003000) /*!< Clock source (32 or 10KHz) divide by 64 */
+#define LCD_CPUMP_DIV128 ((uint32_t) 0x00003800) /*!< Clock source (32 or 10KHz) divide by 128 */
+
+#define LCD_CPVOl_2_6V ((uint32_t) 0x00000000) /*!< Set charge pump voltage to 2.6 V */
+#define LCD_CPVOl_2_7V ((uint32_t) 0x00000100) /*!< Set charge pump voltage to 2.7 V */
+#define LCD_CPVOl_2_8V ((uint32_t) 0x00000200) /*!< Set charge pump voltage to 2.8 V */
+#define LCD_CPVOl_2_9V ((uint32_t) 0x00000300) /*!< Set charge pump voltage to 2.9 V */
+#define LCD_CPVOl_3V ((uint32_t) 0x00000400) /*!< Set charge pump voltage to 3 V */
+#define LCD_CPVOl_3_1V ((uint32_t) 0x00000500) /*!< Set charge pump voltage to 3.1 V */
+#define LCD_CPVOl_3_2V ((uint32_t) 0x00000600) /*!< Set charge pump voltage to 3.2 V */
+#define LCD_CPVOl_3_3V ((uint32_t) 0x00000700) /*!< Set charge pump voltage to 3.3 V */
+
+#define LCD_FCPRESC_DIV1 ((uint32_t) 0x00000000) /*!< Set pre-scale divider value to 1 */
+#define LCD_FCPRESC_DIV2 ((uint32_t) 0x00000004) /*!< Set pre-scale divider value to 2 */
+#define LCD_FCPRESC_DIV4 ((uint32_t) 0x00000008) /*!< Set pre-scale divider value to 4 */
+#define LCD_FCPRESC_DIV8 ((uint32_t) 0x0000000C) /*!< Set pre-scale divider value to 8 */
+
+#define LCD_FRAMECOUNT_INT ((uint32_t) 0x00000001) /*!< Indicate frame count interrupt */
+#define LCD_POWERDOWN_INT ((uint32_t) 0x00000002) /*!< Indicate power down interrupt */
+#define LCD_ALL_INT ((uint32_t) 0x00000003) /*!< Indicate frame count & power down interrupt */
+
+#define ERR_LCD_CAL_BLINK_FAIL 0xFFFF0000 /*!< Specifies that overflow to calculate the blinking frequency */
+
+/*@}*/ /* end of group NANO100_LCD_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_LCD_EXPORTED_STRUCTS LCD Exported Structs
+ @{
+*/
+typedef enum {
+ LCD_C_TYPE = 0, /*!< Select LCD C-Type */
+ LCD_EXTERNAL_R_TYPE = 1, /*!< Select LCD External R-Type */
+ LCD_INTERNAL_R_TYPE = 2, /*!< Select LCD Internal R-Type */
+ LCD_EXTERNAL_C_TYPE = 3 /*!< Select LCD External C-Type */
+} LCD_PanelType;
+
+/*@}*/ /* end of group NANO100_LCD_EXPORTED_STRUCTS */
+
+
+/** @addtogroup NANO100_LCD_EXPORTED_FUNCTIONS LCD Exported Functions
+ @{
+*/
+
+/**
+ * @brief Get LCD Power Down interrupt flag.
+ *
+ * @param None
+ *
+ * @return LCD Power Down interrupt Flag.
+ */
+#define LCD_GET_PD_INT_FLAG() ((LCD->FCSTS & LCD_FCSTS_PDSTS_Msk) >> LCD_FCSTS_PDSTS_Pos)
+
+/**
+ * @brief Clear LCD Power Down interrupt flag.
+ *
+ * @param None
+ *
+ * @return None.
+ */
+#define LCD_CLR_PD_INT_FLAG() (LCD->FCSTS = LCD_FCSTS_PDSTS_Msk)
+
+/**
+ * @brief Get LCD Frame Count interrupt flag.
+ *
+ * @param None
+ *
+ * @return LCD Frame Count interrupt Flag.
+ */
+#define LCD_GET_FRAME_CNT_INT_FLAG() ((LCD->FCSTS & LCD_FCSTS_FCSTS_Msk) >> LCD_FCSTS_FCSTS_Pos)
+
+/**
+ * @brief Clear LCD Frame Count interrupt flag.
+ *
+ * @param None
+ *
+ * @return None.
+ */
+#define LCD_CLR_FRAME_CNT_INT_FLAG() (LCD->FCSTS = LCD_FCSTS_FCSTS_Msk)
+
+/**
+ * @brief Enable LCD Power Down Display function.
+ *
+ * @param None
+ *
+ * @return None.
+ */
+#define LCD_ENABLE_PD_DISPLAY() (LCD->CTL |= LCD_CTL_PDDISP_EN_Msk)
+
+/**
+ * @brief Disable LCD Power Down Display function.
+ *
+ * @param None
+ *
+ * @return None.
+ */
+#define LCD_DISABLE_PD_DISPLAY() (LCD->CTL &= ~LCD_CTL_PDDISP_EN_Msk)
+
+uint32_t LCD_EnableFrameCounter(uint32_t u32Count);
+void LCD_DisableFrameCounter(void);
+uint32_t LCD_EnableBlink(uint32_t u32ms);
+void LCD_DisableBlink(void);
+void LCD_EnableInt(uint32_t IntSrc);
+void LCD_DisableInt(uint32_t IntSrc);
+uint32_t LCD_Open(uint32_t u32DrivingType, uint32_t u32ComNum, uint32_t u32BiasLevel, uint32_t u32FramerateDiv, uint32_t u32DrivingVol);
+void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag);
+void LCD_SetAllPixels(uint32_t u32OnOff);
+void LCD_Close(void);
+
+/**
+ * @brief Enable LCD controller
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+static __INLINE void LCD_EnableDisplay(void)
+{
+ /* Enable LCD */
+ LCD->CTL |= LCD_CTL_EN_Msk;
+}
+
+/**
+ * @brief Disable LCD controller
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+static __INLINE void LCD_DisableDisplay(void)
+{
+ /* Enable LCD */
+ LCD->CTL &= ~LCD_CTL_EN_Msk;
+}
+
+
+
+/*@}*/ /* end of group NANO100_LCD_EXPORTED_FUNCTIONS */
+
+
+/*@}*/ /* end of group NANO100_LCD_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LCD_H__ */
+
+
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_pdma.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,241 @@
+/**************************************************************************//**
+ * @file pdma.c
+ * @version V1.00
+ * $Revision: 5 $
+ * $Date: 14/09/29 3:50p $
+ * @brief Nano100 series PDMA driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_PDMA_Driver PDMA Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+ @{
+*/
+
+/**
+ * @brief PDMA Open
+ *
+ * @param[in] u32Mask Channel enable bits
+ *
+ * @return None
+ *
+ * @details This function enable the PDMA channels.
+ */
+void PDMA_Open(uint32_t u32Mask)
+{
+ PDMAGCR->GCRCSR |= (u32Mask << 8);
+}
+
+/**
+ * @brief PDMA Close
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This function disable all PDMA channels.
+ */
+void PDMA_Close(void)
+{
+ PDMAGCR->GCRCSR = 0;
+}
+
+/**
+ * @brief Set PDMA Transfer Count
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Width Data width. \ref PDMA_WIDTH_8, \ref PDMA_WIDTH_16, or \ref PDMA_WIDTH_32
+ * @param[in] u32TransCount Transfer count
+ *
+ * @return None
+ *
+ * @details This function set the selected channel data width and transfer count.
+ */
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
+{
+ PDMA_T *pdma;
+ pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
+ pdma->CSR = (pdma->CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width;
+ switch (u32Width) {
+ case PDMA_WIDTH_32:
+ pdma->BCR = (u32TransCount << 2);
+ break;
+
+ case PDMA_WIDTH_8:
+ pdma->BCR = u32TransCount;
+ break;
+
+ case PDMA_WIDTH_16:
+ pdma->BCR = (u32TransCount << 1);
+ break;
+
+ default:
+ ;
+ }
+}
+
+/**
+ * @brief Set PDMA Transfer Address
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32SrcAddr Source address
+ * @param[in] u32SrcCtrl Source control attribute. \ref PDMA_SAR_INC, \ref PDMA_SAR_FIX, or \ref PDMA_SAR_WRA
+ * @param[in] u32DstAddr destination address
+ * @param[in] u32DstCtrl destination control attribute. \ref PDMA_DAR_INC, \ref PDMA_DAR_FIX, or \ref PDMA_DAR_WRA
+ *
+ * @return None
+ *
+ * @details This function set the selected channel source/destination address and attribute.
+ */
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
+{
+ PDMA_T *pdma;
+ pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
+
+ pdma->SAR = u32SrcAddr;
+ pdma->DAR = u32DstAddr;
+ pdma->CSR = (pdma->CSR & ~(PDMA_CSR_SAD_SEL_Msk|PDMA_CSR_DAD_SEL_Msk)) | (u32SrcCtrl | u32DstCtrl);
+}
+
+/**
+ * @brief Set PDMA Transfer Mode
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Peripheral The selected peripheral.
+ * \ref PDMA_SPI0_TX, \ref PDMA_SPI1_TX, \ref PDMA_UART0_TX, \ref PDMA_UART1_TX, \ref PDMA_USB_TX,
+ * \ref PDMA_I2S_TX, \ref PDMA_DAC0_TX, \ref PDMA_DAC1_TX, \ref PDMA_SPI2_TX, \ref PDMA_TMR0,
+ * \ref PDMA_TMR1, \ref PDMA_TMR2, \ref PDMA_TMR3, \ref PDMA_SPI0_RX, \ref PDMA_SPI1_RX,
+ * \ref PDMA_UART0_RX, \ref PDMA_UART1_RX, \ref PDMA_USB_RX, \ref PDMA_I2S_RX, \ref PDMA_ADC,
+ * \ref PDMA_SPI2_RX, \ref PDMA_PWM0_CH0, \ref PDMA_PWM0_CH2, \ref PDMA_PWM1_CH0, \ref PDMA_PWM1_CH2,
+ * \ref PDMA_MEM
+ * @param[in] u32ScatterEn Scatter-gather mode enable
+ * @param[in] u32DescAddr Scatter-gather descriptor address
+ *
+ * @return None
+ *
+ * @details This function set the selected channel transfer mode. Include peripheral setting.
+ */
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
+{
+ PDMA_T *pdma;
+ pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
+
+ switch (u32Ch) {
+ case 1:
+ PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH1_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH1_SEL_Pos);
+ break;
+ case 2:
+ PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH2_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH2_SEL_Pos);
+ break;
+ case 3:
+ PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH3_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH3_SEL_Pos);
+ break;
+ case 4:
+ PDMAGCR->DSSR1 = (PDMAGCR->DSSR1 & ~DMA_GCR_DSSR1_CH4_SEL_Msk) | u32Peripheral;
+ break;
+ default:
+ ;
+ }
+ if (u32Peripheral == PDMA_MEM)
+ pdma->CSR &= ~PDMA_CSR_MODE_SEL_Msk;
+ else if (u32Peripheral & 0x10)
+ pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x4; /* IP to memory */
+ else
+ pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x8; /* memory to IP */
+}
+
+/**
+ * @brief Set PDMA Timeout
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32OnOff Enable/disable time out function
+ * @param[in] u32TimeOutCnt Timeout count
+ *
+ * @return None
+ *
+ * @details This function set the timeout count.
+ */
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
+{
+ PDMA_T *pdma;
+ pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
+
+ pdma->TCR = (pdma->TCR & ~PDMA_TCR_PDMA_TCR_Msk) | u32TimeOutCnt;
+ pdma->CSR = (pdma->CSR & ~PDMA_CSR_TO_EN_Msk) | (u32OnOff << PDMA_CSR_TO_EN_Pos);
+
+}
+
+/**
+ * @brief Trigger PDMA
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details This function trigger the selected channel.
+ */
+void PDMA_Trigger(uint32_t u32Ch)
+{
+ PDMA_T *pdma;
+ pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
+
+ pdma->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk);
+}
+
+/**
+ * @brief Enable Interrupt
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Mask The Interrupt Type
+ *
+ * @return None
+ *
+ * @details This function enable the selected channel interrupt.
+ */
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+ PDMA_T *pdma;
+ pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
+
+ pdma->IER |= u32Mask;
+}
+
+/**
+ * @brief Disable Interrupt
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Mask The Interrupt Type
+ *
+ * @return None
+ *
+ * @details This function disable the selected channel interrupt.
+ */
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+ PDMA_T *pdma;
+ pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
+
+ pdma->IER &= ~u32Mask;
+}
+
+
+/*@}*/ /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_PDMA_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_pdma.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,219 @@
+/**************************************************************************//**
+ * @file pdma.h
+ * @version V1.00
+ * $Revision: 9 $
+ * $Date: 15/06/10 4:52p $
+ * @brief Nano100 series PDMA driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PDMA_H__
+#define __PDMA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_PDMA_Driver PDMA Driver
+ @{
+*/
+
+/** @addtogroup NANO100_PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Data Width Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_WIDTH_8 0x00080000UL /*!<DMA Transfer Width 8-bit */
+#define PDMA_WIDTH_16 0x00100000UL /*!<DMA Transfer Width 16-bit */
+#define PDMA_WIDTH_32 0x00000000UL /*!<DMA Transfer Width 32-bit */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Address Attribute Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment */
+#define PDMA_SAR_FIX 0x00000020UL /*!<DMA SAR fix address */
+#define PDMA_SAR_WRA 0x00000030UL /*!<DMA SAR wrap around */
+#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment */
+#define PDMA_DAR_FIX 0x00000080UL /*!<DMA DAR fix address */
+#define PDMA_DAR_WRA 0x000000C0UL /*!<DMA DAR wrap around */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Peripheral Transfer Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_SPI0_TX 0x00000000UL /*!<DMA Connect to SPI0 TX */
+#define PDMA_SPI1_TX 0x00000001UL /*!<DMA Connect to SPI1 TX */
+#define PDMA_UART0_TX 0x00000002UL /*!<DMA Connect to UART0 TX */
+#define PDMA_UART1_TX 0x00000003UL /*!<DMA Connect to UART1 TX */
+#define PDMA_USB_TX 0x00000004UL /*!<DMA Connect to USB TX */
+#define PDMA_I2S_TX 0x00000005UL /*!<DMA Connect to I2S TX */
+#define PDMA_DAC0_TX 0x00000006UL /*!<DMA Connect to DAC0 TX */
+#define PDMA_DAC1_TX 0x00000007UL /*!<DMA Connect to DAC1 TX */
+#define PDMA_SPI2_TX 0x00000008UL /*!<DMA Connect to SPI2 TX */
+#define PDMA_TMR0 0x00000009UL /*!<DMA Connect to TMR0 */
+#define PDMA_TMR1 0x0000000AUL /*!<DMA Connect to TMR1 */
+#define PDMA_TMR2 0x0000000BUL /*!<DMA Connect to TMR2 */
+#define PDMA_TMR3 0x0000000CUL /*!<DMA Connect to TMR3 */
+
+#define PDMA_SPI0_RX 0x00000010UL /*!<DMA Connect to SPI0 RX */
+#define PDMA_SPI1_RX 0x00000011UL /*!<DMA Connect to SPI1 RX */
+#define PDMA_UART0_RX 0x00000012UL /*!<DMA Connect to UART0 RX */
+#define PDMA_UART1_RX 0x00000013UL /*!<DMA Connect to UART1 RX */
+#define PDMA_USB_RX 0x00000014UL /*!<DMA Connect to USB RX */
+#define PDMA_I2S_RX 0x00000015UL /*!<DMA Connect to I2S RX */
+#define PDMA_ADC 0x00000016UL /*!<DMA Connect to I2S1 RX */
+#define PDMA_SPI2_RX 0x00000018UL /*!<DMA Connect to SPI2 RX */
+#define PDMA_PWM0_CH0 0x00000019UL /*!<DMA Connect to PWM0 CH0 */
+#define PDMA_PWM0_CH2 0x0000001AUL /*!<DMA Connect to PWM0 CH2 */
+#define PDMA_PWM1_CH0 0x0000001BUL /*!<DMA Connect to PWM1 CH0 */
+#define PDMA_PWM1_CH2 0x0000001CUL /*!<DMA Connect to PWM1 CH2 */
+#define PDMA_MEM 0x0000001FUL /*!<DMA Connect to Memory */
+
+
+
+/*@}*/ /* end of group NANO100_PDMA_EXPORTED_CONSTANTS */
+
+/** @addtogroup NANO100_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+ @{
+*/
+
+/**
+ * @brief Get PDMA Interrupt Status
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details This macro gets the interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMAGCR->GCRISR))
+
+/**
+ * @brief Get PDMA Channel Interrupt Status
+ *
+ * @param[in] u32Ch Selected DMA channel
+ *
+ * @return Interrupt Status
+ *
+ * @details This macro gets the channel interrupt status.
+ * \hideinitializer
+ */
+#define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))))
+
+/**
+ * @brief Clear PDMA Channel Interrupt Flag
+ *
+ * @param[in] u32Ch Selected DMA channel
+ * @param[in] u32Mask Interrupt Mask
+ *
+ * @return None
+ *
+ * @details This macro clear the channel interrupt flag.
+ * \hideinitializer
+ */
+#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))) = (u32Mask))
+
+/**
+ * @brief Check Channel Status
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return 0 = idle
+ * @return 1 = busy
+ *
+ * @details Check the selected channel is busy or not.
+ * \hideinitializer
+ */
+#define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA1->CSR +(uint32_t)((u32Ch-1)*0x100)))&PDMA_CSR_TRIG_EN_Msk)? 1 : 0)
+
+/**
+ * @brief Set Source Address
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The selected address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel source address.
+ * \hideinitializer
+ */
+#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->SAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
+
+/**
+ * @brief Set Destination Address
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The selected address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel destination address.
+ * \hideinitializer
+ */
+#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->DAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
+
+/**
+ * @brief Set Transfer Count
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Count Transfer Count
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel transfer count.
+ * \hideinitializer
+ */
+#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) \
+do{\
+ if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_32) \
+ *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 2); \
+ else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_8) \
+ *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = (u32Count); \
+ else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_16) \
+ *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 1); \
+}while(0)
+
+/**
+ * @brief Stop the channel
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details This macro stop the selected channel.
+ * \hideinitializer
+ */
+#define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) &= ~PDMA_CSR_PDMACEN_Msk)
+
+void PDMA_Open(uint32_t u32Mask);
+void PDMA_Close(void);
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
+void PDMA_Trigger(uint32_t u32Ch);
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
+
+/*@}*/ /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_PDMA_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PDMA_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_pwm.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,542 @@
+/**************************************************************************//**
+ * @file PWM.c
+ * @version V1.00
+ * $Revision: 14 $
+ * $Date: 14/09/04 11:58a $
+ * @brief NANO100 series PWM driver source file
+ *
+ * @note
+ * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_PWM_Driver PWM Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
+ * existing frequency of other channel.
+ */
+uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32Frequency,
+ uint32_t u32DutyCycle)
+{
+ return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
+}
+
+/**
+ * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
+ * existing frequency of other channel.
+ */
+uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32Frequency,
+ uint32_t u32DutyCycle,
+ uint32_t u32Frequency2)
+{
+ uint32_t i;
+ uint32_t u32ClkSrc;
+ uint32_t u32PWM_Clock = SystemCoreClock;
+ uint8_t u8Divider = 1, u8Prescale = 0xFF;
+ uint16_t u16CNR = 0xFFFF;
+
+ if(pwm == PWM0)
+ u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2));
+
+ else
+ u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2));
+
+ switch (u32ClkSrc) {
+ case 0:
+ u32PWM_Clock = __HXT;
+ break;
+ case 1:
+ u32PWM_Clock = __LXT;
+ break;
+ case 2:
+ u32PWM_Clock = SystemCoreClock;
+ break;
+ case 3:
+ u32PWM_Clock = __HIRC12M;
+ break;
+ }
+
+ for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
+ // Note: Support frequency < 1
+ i = (uint64_t) u32PWM_Clock * u32Frequency2 / u32Frequency / u8Divider;
+ // If target value is larger than CNR * prescale, need to use a larger divider
+ if(i > (0x10000 * 0x100))
+ continue;
+
+ // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
+ u8Prescale = (i + 0xFFFF)/ 0x10000;
+
+ // u8Prescale must at least be 2, otherwise the output stop
+ if(u8Prescale < 3)
+ u8Prescale = 2;
+
+ i /= u8Prescale;
+
+ if(i <= 0x10000) {
+ if(i == 1)
+ u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
+ else
+ u16CNR = i;
+ break;
+ }
+
+ }
+ // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
+ i = u32PWM_Clock / (u8Prescale * u8Divider * u16CNR);
+
+ u8Prescale -= 1;
+ u16CNR -= 1;
+ // convert to real register value
+ if(u8Divider == 1)
+ u8Divider = 4;
+ else if (u8Divider == 2)
+ u8Divider = 0;
+ else if (u8Divider == 4)
+ u8Divider = 1;
+ else if (u8Divider == 8)
+ u8Divider = 2;
+ else // 16
+ u8Divider = 3;
+
+ // every two channels share a prescaler
+ while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk);
+ pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
+ pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
+ pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
+ while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum));
+ if(u32DutyCycle == 0)
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
+ else {
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 100 - 1) << PWM_DUTY_CM_Pos);
+ }
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
+
+ return(i);
+}
+
+/**
+ * @brief This function config PWM capture and get the nearest unit time
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec Unit time of counter
+ * @param[in] u32CaptureEdge Condition to latch the counter
+ * @return Nearest unit time in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
+ * existing frequency of other channel.
+ */
+uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32UnitTimeNsec,
+ uint32_t u32CaptureEdge)
+{
+ uint32_t i;
+ uint32_t u32ClkSrc;
+ uint32_t u32PWM_Clock = SystemCoreClock;
+ uint8_t u8Divider = 1, u8Prescale = 0xFF;
+ uint16_t u16CNR = 0xFFFF;
+
+ if(pwm == PWM0)
+ u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2));
+ else
+ u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2));
+
+ switch (u32ClkSrc) {
+ case 0:
+ u32PWM_Clock = __HXT;
+ break;
+ case 1:
+ u32PWM_Clock = __LXT;
+ break;
+ case 2:
+ u32PWM_Clock = SystemCoreClock;
+ break;
+ case 3:
+ u32PWM_Clock = __HIRC12M;
+ break;
+ }
+
+ for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
+ i = ((long long)(u32PWM_Clock / u8Divider) * u32UnitTimeNsec) / 1000000000;
+
+ // If target value is larger than 0xFF, need to use a larger divider
+ if(i > (0xFF))
+ continue;
+
+ u8Prescale = i;
+
+ // u8Prescale must at least be 2, otherwise the output stop
+ if(u8Prescale < 3)
+ u8Prescale = 2;
+
+ break;
+ }
+
+ // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
+ i = (long long) (u8Prescale * u8Divider) * 1000000000 / u32PWM_Clock;
+
+ u8Prescale -= 1;
+ u16CNR -= 1;
+ // convert to real register value
+ if(u8Divider == 1)
+ u8Divider = 4;
+ else if (u8Divider == 2)
+ u8Divider = 0;
+ else if (u8Divider == 4)
+ u8Divider = 1;
+ else if (u8Divider == 8)
+ u8Divider = 2;
+ else // 16
+ u8Divider = 3;
+
+ // every two channels share a prescaler
+ while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk);
+ pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
+ pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
+ pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
+ while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum));
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
+
+ return(i);
+}
+
+/**
+ * @brief This function start PWM module
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ */
+void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint8_t i;
+ uint32_t u32Mask = 0;
+
+ for (i = 0; i < PWM_CHANNEL_NUM; i++) {
+ if ( u32ChannelMask & (1 << i))
+ u32Mask |= (PWM_CTL_CH0EN_Msk << (i * 8));
+ }
+
+ pwm->CTL |= u32Mask;
+}
+
+/**
+ * @brief This function stop PWM module
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ */
+void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
+ if(u32ChannelMask & (1 << i)) {
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * i) &= ~PWM_DUTY_CN_Msk;
+ }
+ }
+
+}
+
+/**
+ * @brief This function stop PWM generation immediately by clear channel enable bit
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ */
+void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for (i = 0; i < PWM_CHANNEL_NUM; i++) {
+ if ( u32ChannelMask & (1 << i))
+ pwm->CTL &= ~(PWM_CTL_CH0EN_Msk << (i * 8));
+ }
+}
+
+/**
+ * @brief This function enables PWM capture of selected channels
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ */
+void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint8_t i;
+ uint32_t u32Mask = 0;
+
+ for (i = 0; i < PWM_CHANNEL_NUM; i++) {
+ if ( u32ChannelMask & (1 << i)) {
+ u32Mask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
+ }
+ }
+
+ pwm->CAPCTL |= u32Mask;
+}
+
+/**
+ * @brief This function disables PWM capture of selected channels
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ */
+void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint8_t i;
+ uint32_t u32CTLMask = 0;
+ uint32_t u32CAPCTLMask = 0;
+
+ for (i = 0; i < PWM_CHANNEL_NUM; i++) {
+ if ( u32ChannelMask & (1 << i)) {
+ u32CTLMask |= (PWM_CTL_CH0EN_Msk << (i * 8));
+ u32CAPCTLMask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
+ }
+ }
+
+ pwm->CTL &= ~u32CTLMask;
+ pwm->CAPCTL &= ~u32CAPCTLMask;
+}
+
+/**
+ * @brief This function enables PWM output generation of selected channels
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ */
+void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ pwm->OE |= u32ChannelMask;
+}
+
+/**
+ * @brief This function disables PWM output generation of selected channels
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ */
+void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ pwm->OE &= ~u32ChannelMask;
+}
+
+/**
+ * @brief This function enable Dead zone of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no
+ * dead zone.
+ * @return None
+ */
+void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+ // every two channels shares the same setting
+ u32ChannelNum >>= 1;
+ // set duration
+ pwm->PRES = (pwm->PRES & ~(PWM_PRES_DZ01_Msk << (8 * u32ChannelNum))) | ((u32Duration << PWM_PRES_DZ01_Pos ) << (8 * u32ChannelNum));
+ // enable dead zone
+ pwm->CTL |= (PWM_CTL_DZEN01_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief This function disable Dead zone of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ */
+void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ // every two channels shares the same setting
+ u32ChannelNum >>= 1;
+ // enable dead zone
+ pwm->CTL &= ~(PWM_CTL_DZEN01_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief This function enable capture interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Capture interrupt type. It could be either
+ * - \ref PWM_RISING_LATCH_INT_ENABLE
+ * - \ref PWM_FALLING_LATCH_INT_ENABLE
+ * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
+ * @return None
+ */
+void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ // enable capture interrupt
+ pwm->CAPINTEN |= (u32Edge << (u32ChannelNum * 8));
+}
+
+/**
+ * @brief This function disable capture interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Capture interrupt type. It could be either
+ * - \ref PWM_RISING_LATCH_INT_ENABLE
+ * - \ref PWM_FALLING_LATCH_INT_ENABLE
+ * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
+ * @return None
+ */
+void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ // disable capture interrupt
+ pwm->CAPINTEN &= ~(u32Edge << (u32ChannelNum * 8));
+}
+
+/**
+ * @brief This function clear capture interrupt flag of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Capture interrupt type. It could be either
+ * - \ref PWM_RISING_LATCH_INT_FLAG
+ * - \ref PWM_FALLING_LATCH_INT_FLAG
+ * - \ref PWM_RISING_FALLING_LATCH_INT_FLAG
+ * @return None
+ */
+void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ // disable capture interrupt flag
+ pwm->CAPINTSTS = (u32Edge + 1) << (u32ChannelNum * 8);
+}
+
+/**
+ * @brief This function get capture interrupt flag of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Capture interrupt flag of specified channel
+ * @retval 0 Capture interrupt did not occurred
+ * @retval PWM_RISING_LATCH_INT_FLAG Rising edge latch interrupt occurred
+ * @retval PWM_FALLING_LATCH_INT_FLAG Falling edge latch interrupt occurred
+ * @retval PWM_RISING_FALLING_LATCH_INT_FLAG Rising and falling edge latch interrupt occurred
+ */
+uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return ((pwm->CAPINTSTS >> (u32ChannelNum * 8)) & (PWM_RISING_FALLING_LATCH_INT_FLAG));
+}
+
+/**
+ * @brief This function enable period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32IntPeriodType This parameter is not used
+ * @return None
+ * @note All channels share the same period interrupt type setting.
+ */
+void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
+{
+ // enable period interrupt
+ pwm->INTEN |= (PWM_INTEN_TMIE0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief This function disable period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ */
+void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ pwm->INTEN &= ~(PWM_INTEN_TMIE0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief This function clear period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ */
+void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ // write 1 clear
+ pwm->INTSTS = (PWM_INTSTS_TMINT0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief This function get period interrupt of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occurred
+ * @retval 1 Period interrupt occurred
+ */
+uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return ((pwm->INTSTS & (PWM_INTSTS_TMINT0_Msk << u32ChannelNum)) ? 1 : 0);
+}
+
+/**
+ * @brief This function enable capture PDMA of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2
+ * @param[in] u32RisingFirst Order of captured data transferred by PDMA. It could be either
+ * - \ref PWM_CAP_PDMA_RFORDER_R
+ * - \ref PWM_CAP_PDMA_RFORDER_F
+ * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
+ * - \ref PWM_RISING_LATCH_PDMA_ENABLE
+ * - \ref PWM_FALLING_LATCH_PDMA_ENABLE
+ * - \ref PWM_RISING_FALLING_LATCH_PDMA_ENABLE
+ * @return None
+ */
+void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
+{
+ if (u32ChannelNum == 0)
+ pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD0_Msk | PWM_CAPCTL_CH0RFORDER_Msk)) | u32Mode | u32RisingFirst | PWM_CAPCTL_CH0PDMAEN_Msk;
+ else
+ pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD2_Msk | PWM_CAPCTL_CH2RFORDER_Msk)) | (u32Mode << 16)| (u32RisingFirst << 16)| PWM_CAPCTL_CH2PDMAEN_Msk;
+}
+
+/**
+ * @brief This function disable capture PDMA of selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2
+ * @return None
+ */
+void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ if (u32ChannelNum == 0)
+ pwm->CAPCTL &= ~PWM_CAPCTL_CH0PDMAEN_Msk;
+ else
+ pwm->CAPCTL &= ~PWM_CAPCTL_CH2PDMAEN_Msk;
+}
+
+/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_PWM_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_pwm.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,209 @@
+/**************************************************************************//**
+ * @file pwm.h
+ * @version V1.00
+ * $Revision: 12 $
+ * $Date: 15/06/30 2:52p $
+ * @brief NANO100 series PWM driver header file
+ *
+ * @note
+ * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_PWM_Driver PWM Driver
+ @{
+*/
+
+/** @addtogroup NANO100_PWM_EXPORTED_CONSTANTS PWM Exported Constants
+ @{
+*/
+#define PWM_CHANNEL_NUM (4) /*!< PWM channel number \hideinitializer */
+#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
+#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
+#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
+#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
+#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
+#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
+#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
+#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
+#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
+#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
+#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
+#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */
+#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */
+#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */
+#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */
+#define PWM_RISING_LATCH_INT_ENABLE (1UL) /*!< PWM rising latch interrupt enable \hideinitializer */
+#define PWM_FALLING_LATCH_INT_ENABLE (2UL) /*!< PWM falling latch interrupt enable \hideinitializer */
+#define PWM_RISING_FALLING_LATCH_INT_ENABLE (3UL) /*!< PWM rising latch interrupt enable \hideinitializer */
+#define PWM_RISING_LATCH_INT_FLAG (2UL) /*!< PWM rising latch condition happened \hideinitializer */
+#define PWM_FALLING_LATCH_INT_FLAG (4UL) /*!< PWM falling latch condition happened \hideinitializer */
+#define PWM_RISING_FALLING_LATCH_INT_FLAG (6UL) /*!< PWM rising latch condition happened \hideinitializer */
+#define PWM_RISING_LATCH_PDMA_ENABLE (0x10UL) /*!< PWM rising latch PDMA enable \hideinitializer */
+#define PWM_FALLING_LATCH_PDMA_ENABLE (0x20UL) /*!< PWM falling latch PDMA enable \hideinitializer */
+#define PWM_RISING_FALLING_LATCH_PDMA_ENABLE (0x30UL) /*!< PWM rising and falling latch PDMA enable \hideinitializer */
+#define PWM_CAP_PDMA_RFORDER_R (0x1000UL) /*!< PWM captured data transferred by PDMA is rising latch first \hideinitializer */
+#define PWM_CAP_PDMA_RFORDER_F (0UL) /*!< PWM captured data transferred by PDMA is falling latch first \hideinitializer */
+
+/*@}*/ /* end of group NANO100_PWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * \hideinitializer
+ */
+#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask)\
+do { \
+ uint8_t i; \
+ (pwm)->CTL &= ~(PWM_CTL_CH0INV_Msk | PWM_CTL_CH1INV_Msk | PWM_CTL_CH2INV_Msk | PWM_CTL_CH3INV_Msk);\
+ for (i = 0; i < PWM_CHANNEL_NUM; i++) { \
+ if ( (u32ChannelMask) & (1 << i)) { \
+ (pwm)->CTL |= (PWM_CTL_CH0INV_Msk << (i * 8)); \
+ } \
+ } \
+ }while(0)
+
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CRL0 + 2 * u32ChannelNum))
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->CFL0 + 2 * u32ChannelNum))
+
+/**
+ * @brief This macro set the prescaler of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
+ * @return None
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
+ * channel 1 will also be affected.
+ * \hideinitializer
+ */
+#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
+ (pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
+
+/**
+ * @brief This macro set the divider of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Divider Clock divider of specified channel. Valid values are
+ * - \ref PWM_CLK_DIV_1
+ * - \ref PWM_CLK_DIV_2
+ * - \ref PWM_CLK_DIV_4
+ * - \ref PWM_CLK_DIV_8
+ * - \ref PWM_CLK_DIV_16
+ * @return None
+ * \hideinitializer
+ */
+#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
+ (pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u32Divider << (4 * u32ChannelNum)))
+
+/**
+ * @brief This macro set the duty of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next PWM period
+ * \hideinitializer
+ */
+#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) \
+do { \
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk; \
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= (u32CMR << PWM_DUTY_CM_Pos); \
+}while(0)
+
+/**
+ * @brief This macro set the period of the selected channel
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next PWM period
+ * @note PWM counter will stop if period length set to 0
+ * \hideinitializer
+ */
+#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) \
+do { \
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk; \
+ *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u32CNR; \
+} while(0)
+
+uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32Frequency,
+ uint32_t u32DutyCycle);
+uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32Frequency,
+ uint32_t u32DutyCycle,
+ uint32_t u32Frequency2);
+uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
+ uint32_t u32ChannelNum,
+ uint32_t u32UnitTimeNsec,
+ uint32_t u32CaptureEdge);
+void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
+void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
+void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
+
+/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_PWM_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PWM_H__
+
+/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_rtc.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,806 @@
+/**************************************************************************//**
+ * @file rtc.c
+ * @version V1.00
+ * $Revision: 11 $
+ * $Date: 15/06/26 1:26p $
+ * @brief Nano100 series RTC driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+
+#include <stdio.h>
+#include "Nano100Series.h"
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Includes of local headers */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_RTC_Driver RTC Driver
+ @{
+*/
+/// @cond HIDDEN_SYMBOLS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro, type and constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_GLOBALS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables */
+/*---------------------------------------------------------------------------------------------------------*/
+static volatile uint32_t g_u32Reg, g_u32Reg1,g_u32hiYear,g_u32loYear,g_u32hiMonth,g_u32loMonth,g_u32hiDay,g_u32loDay;
+static volatile uint32_t g_u32hiHour,g_u32loHour,g_u32hiMin,g_u32loMin,g_u32hiSec,g_u32loSec;
+
+/// @endcond HIDDEN_SYMBOLS
+
+/** @addtogroup NANO100_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Set Frequency Compensation Data
+ *
+ * @param[in] i32FrequencyX100 Specify the RTC clock X100, ex: 3277365 means 32773.65.
+ *
+ * @return None
+ *
+ */
+void RTC_32KCalibration(int32_t i32FrequencyX100)
+{
+ int32_t i32RegInt,i32RegFra ;
+
+ /* Compute Integer and Fraction for RTC register*/
+ i32RegInt = (i32FrequencyX100/100) - RTC_FCR_REFERENCE;
+ i32RegFra = (((i32FrequencyX100%100)) * 60) / 100;
+
+ /* Judge Integer part is reasonable */
+ if ( (i32RegInt < 0) | (i32RegInt > 15) ) {
+ return;
+ }
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->FCR = (uint32_t)((i32RegInt<<8) | i32RegFra);
+
+}
+
+/**
+ * @brief This function is used to write initial key to let RTC start count and set current time.
+ *
+ *
+ * @param[in] sPt \n
+ * Specify the time property and current time. Null pointer for using default starting time. It includes: \n
+ * u32Year: Year value. \n
+ * u32Month: Month value. \n
+ * u32Day: Day value. \n
+ * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
+ * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
+ * \ref RTC_SATURDAY] \n
+ * u32Hour: Hour value. \n
+ * u32Minute: Minute value. \n
+ * u32Second: Second value. \n
+ * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n
+ * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n
+ *
+ * @return None
+ *
+ */
+void RTC_Open (S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Reg;
+
+ volatile int32_t i32delay=1000;
+
+ RTC->INIR = RTC_INIT_KEY;
+
+ if(RTC->INIR != 0x1) {
+ RTC->INIR = RTC_INIT_KEY;
+
+ while(RTC->INIR != 0x1);
+ }
+
+ if(sPt == NULL)
+ return;
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Second, set RTC 24/12 hour setting */
+ /*-----------------------------------------------------------------------------------------------------*/
+ if (sPt->u32TimeScale == RTC_CLOCK_12) {
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+ RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk;
+
+ /*-------------------------------------------------------------------------------------------------*/
+ /* important, range of 12-hour PM mode is 21 upto 32 */
+ /*-------------------------------------------------------------------------------------------------*/
+ if (sPt->u32AmPm == RTC_PM)
+ sPt->u32Hour += 20;
+ } else {
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+ RTC->TSSR |= RTC_TSSR_24H_12H_Msk;
+ }
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Calender Loading */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
+ u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
+ u32Reg |= ((sPt->u32Month / 10) << 12);
+ u32Reg |= ((sPt->u32Month % 10) << 8);
+ u32Reg |= ((sPt->u32Day / 10) << 4);
+ u32Reg |= (sPt->u32Day % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->CLR = (uint32_t)g_u32Reg;
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Time Loading */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32Reg = ((sPt->u32Hour / 10) << 20);
+ u32Reg |= ((sPt->u32Hour % 10) << 16);
+ u32Reg |= ((sPt->u32Minute / 10) << 12);
+ u32Reg |= ((sPt->u32Minute % 10) << 8);
+ u32Reg |= ((sPt->u32Second / 10) << 4);
+ u32Reg |= (sPt->u32Second % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->TLR = (uint32_t)g_u32Reg;
+
+ RTC->DWR = sPt->u32DayOfWeek;
+
+ /* Waiting for RTC settings stable */
+ while(i32delay--);
+
+}
+
+/**
+ * @brief Read current date/time from RTC setting
+ *
+ * @param[out] sPt \n
+ * Specify the time property and current time. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24 \n
+ * u8AmPm: \ref RTC_AM / \ref RTC_PM \n
+ *
+ * @return None
+ *
+ */
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+
+ sPt->u32TimeScale = RTC->TSSR & RTC_TSSR_24H_12H_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->DWR & RTC_DWR_DWR_Msk; /* Day of week */
+
+ g_u32hiYear = (RTC->CLR & RTC_CLR_10YEAR_Msk) >> RTC_CLR_10YEAR_Pos;
+ g_u32loYear = (RTC->CLR & RTC_CLR_1YEAR_Msk) >> RTC_CLR_1YEAR_Pos;
+ g_u32hiMonth = (RTC->CLR & RTC_CLR_10MON_Msk) >> RTC_CLR_10MON_Pos;
+ g_u32loMonth = (RTC->CLR & RTC_CLR_1MON_Msk) >> RTC_CLR_1MON_Pos;
+ g_u32hiDay = (RTC->CLR & RTC_CLR_10DAY_Msk) >> RTC_CLR_10DAY_Pos;
+ g_u32loDay = (RTC->CLR & RTC_CLR_1DAY_Msk);
+
+ g_u32hiHour = (RTC->TLR & RTC_TLR_10HR_Msk) >> RTC_TLR_10HR_Pos;
+ g_u32loHour = (RTC->TLR & RTC_TLR_1HR_Msk) >> RTC_TLR_1HR_Pos;
+ g_u32hiMin = (RTC->TLR & RTC_TLR_10MIN_Msk) >> RTC_TLR_10MIN_Pos;
+ g_u32loMin = (RTC->TLR & RTC_TLR_1MIN_Msk) >> RTC_TLR_1MIN_Pos;
+ g_u32hiSec = (RTC->TLR & RTC_TLR_10SEC_Msk) >> RTC_TLR_10SEC_Pos;
+ g_u32loSec = (RTC->TLR & RTC_TLR_1SEC_Msk);
+
+ u32Tmp = (g_u32hiYear * 10); /* Compute to 20XX year */
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+ u32Tmp = (g_u32hiMonth * 10); /* Compute 0~12 month */
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+
+ u32Tmp = (g_u32hiDay * 10); /* Compute 0~31 day */
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ if (sPt->u32TimeScale == RTC_CLOCK_12) { /* Compute12/24 hour */
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp+= g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if (sPt->u32Hour >= 21) {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20;
+ } else {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp+= g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp+= g_u32loSec;
+ sPt->u32Second = u32Tmp;
+
+ } else {
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+
+}
+
+
+
+/**
+ * @brief Read alarm date/time from RTC setting
+ *
+ * @param[out] sPt \n
+ * Specify the time property and current time. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24 \n
+ * u8AmPm: \ref RTC_AM / \ref RTC_PM \n
+ *
+ * @return None
+ *
+ */
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+
+ sPt->u32TimeScale = RTC->TSSR & RTC_TSSR_24H_12H_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->DWR & RTC_DWR_DWR_Msk; /* Day of week */
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ g_u32hiYear = (RTC->CAR & RTC_CAR_10YEAR_Msk) >> RTC_CAR_10YEAR_Pos;
+ g_u32loYear = (RTC->CAR & RTC_CAR_1YEAR_Msk) >> RTC_CAR_1YEAR_Pos;
+ g_u32hiMonth = (RTC->CAR & RTC_CAR_10MON_Msk) >> RTC_CAR_10MON_Pos;
+ g_u32loMonth = (RTC->CAR & RTC_CAR_1MON_Msk) >> RTC_CAR_1MON_Pos;
+ g_u32hiDay = (RTC->CAR & RTC_CAR_10DAY_Msk) >> RTC_CAR_10DAY_Pos;
+ g_u32loDay = (RTC->CAR & RTC_CAR_1DAY_Msk);
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ g_u32hiHour = (RTC->TAR & RTC_TAR_10HR_Msk) >> RTC_TAR_10HR_Pos;
+ g_u32loHour = (RTC->TAR & RTC_TAR_1HR_Msk) >> RTC_TAR_1HR_Pos;
+ g_u32hiMin = (RTC->TAR & RTC_TAR_10MIN_Msk) >> RTC_TAR_10MIN_Pos;
+ g_u32loMin = (RTC->TAR & RTC_TAR_1MIN_Msk) >> RTC_TAR_1MIN_Pos;
+ g_u32hiSec = (RTC->TAR & RTC_TAR_10SEC_Msk) >> RTC_TAR_10SEC_Pos;
+ g_u32loSec = (RTC->TAR & RTC_TAR_1SEC_Msk);
+
+ u32Tmp = (g_u32hiYear * 10); /* Compute to 20XX year */
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+ u32Tmp = (g_u32hiMonth * 10); /* Compute 0~12 month */
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+
+ u32Tmp = (g_u32hiDay * 10); /* Compute 0~31 day */
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ if (sPt->u32TimeScale == RTC_CLOCK_12) { /* Compute12/24 hour */
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if (sPt->u32Hour >= 21) {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20;
+ } else {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+
+ } else {
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp+= g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+
+}
+
+
+
+/**
+ * @brief This function is used to update date/time to RTC.
+ *
+ * @param[in] sPt \n
+ * Specify the time property and current time. It includes: \n
+ * u32Year: Year value. \n
+ * u32Month: Month value. \n
+ * u32Day: Day value. \n
+ * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
+ * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
+ * \ref RTC_SATURDAY] \n
+ * u32Hour: Hour value. \n
+ * u32Minute: Minute value. \n
+ * u32Second: Second value. \n
+ * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n
+ * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n
+ *
+ *
+ * @return None
+ *
+ *
+ */
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ if (sPt->u32TimeScale == RTC_CLOCK_12) {
+ RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk;
+
+ /*-----------------------------------------------------------------------------------------*/
+ /* important, range of 12-hour PM mode is 21 upto 32 */
+ /*-----------------------------------------------------------------------------------------*/
+ if (sPt->u32AmPm == RTC_PM)
+ sPt->u32Hour += 20;
+ } else {
+ RTC->TSSR |= RTC_TSSR_24H_12H_Msk;
+ }
+
+ RTC->DWR = sPt->u32DayOfWeek & RTC_DWR_DWR_Msk;
+
+ u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
+ u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
+ u32Reg |= ((sPt->u32Month / 10) << 12);
+ u32Reg |= ((sPt->u32Month % 10) << 8);
+ u32Reg |= ((sPt->u32Day / 10) << 4);
+ u32Reg |= (sPt->u32Day % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->CLR = (uint32_t)g_u32Reg;
+
+ u32Reg = ((sPt->u32Hour / 10) << 20);
+ u32Reg |= ((sPt->u32Hour % 10) << 16);
+ u32Reg |= ((sPt->u32Minute / 10) << 12);
+ u32Reg |= ((sPt->u32Minute % 10) << 8);
+ u32Reg |= ((sPt->u32Second / 10) << 4);
+ u32Reg |= (sPt->u32Second % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->TLR = (uint32_t)g_u32Reg;
+
+}
+
+/**
+ * @brief This function is used to set alarm date/time to RTC.
+ *
+ * @param[in] sPt \n
+ * Specify the time property and current time. It includes: \n
+ * u32Year: Year value. \n
+ * u32Month: Month value. \n
+ * u32Day: Day value. \n
+ * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
+ * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
+ * \ref RTC_SATURDAY] \n
+ * u32Hour: Hour value. \n
+ * u32Minute: Minute value. \n
+ * u32Second: Second value. \n
+ * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n
+ * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n
+ *
+ * @return None
+ *
+ */
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ if (sPt->u32TimeScale == RTC_CLOCK_12) {
+ RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk;
+
+ /*-----------------------------------------------------------------------------------------*/
+ /* important, range of 12-hour PM mode is 21 upto 32 */
+ /*-----------------------------------------------------------------------------------------*/
+ if (sPt->u32AmPm == RTC_PM)
+ sPt->u32Hour += 20;
+ } else {
+ RTC->TSSR |= RTC_TSSR_24H_12H_Msk;
+ }
+
+ RTC->DWR = sPt->u32DayOfWeek & RTC_DWR_DWR_Msk;
+
+
+ u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
+ u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
+ u32Reg |= ((sPt->u32Month / 10) << 12);
+ u32Reg |= ((sPt->u32Month % 10) << 8);
+ u32Reg |= ((sPt->u32Day / 10) << 4);
+ u32Reg |= (sPt->u32Day % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->CAR = (uint32_t)g_u32Reg;
+
+ u32Reg = ((sPt->u32Hour / 10) << 20);
+ u32Reg |= ((sPt->u32Hour % 10) << 16);
+ u32Reg |= ((sPt->u32Minute / 10) << 12);
+ u32Reg |= ((sPt->u32Minute % 10) << 8);
+ u32Reg |= ((sPt->u32Second / 10) << 4);
+ u32Reg |= (sPt->u32Second % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->TAR = (uint32_t)g_u32Reg;
+
+}
+
+
+/**
+ * @brief This function is used to update date to RTC
+ *
+ * @param[in] u32Year The Year Calendar Digit of Alarm Setting
+ * @param[in] u32Month The Month Calendar Digit of Alarm Setting
+ * @param[in] u32Day The Day Calendar Digit of Alarm Setting
+ * @param[in] u32DayOfWeek The Day of Week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
+ * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
+ * \ref RTC_SATURDAY]
+ *
+ * @return None
+ *
+ */
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
+{
+ __IO uint32_t u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ RTC->DWR = u32DayOfWeek & RTC_DWR_DWR_Msk;
+
+ u32Reg = ((u32Year - RTC_YEAR2000) / 10) << 20;
+ u32Reg |= (((u32Year - RTC_YEAR2000) % 10) << 16);
+ u32Reg |= ((u32Month / 10) << 12);
+ u32Reg |= ((u32Month % 10) << 8);
+ u32Reg |= ((u32Day / 10) << 4);
+ u32Reg |= (u32Day % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->CLR = (uint32_t)g_u32Reg;
+
+}
+
+/**
+ * @brief This function is used to update time to RTC.
+ *
+ * @param[in] u32Hour The Hour Time Digit of Alarm Setting.
+ * @param[in] u32Minute The Minute Time Digit of Alarm Setting
+ * @param[in] u32Second The Second Time Digit of Alarm Setting
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [ \ref RTC_AM / \ref RTC_PM]
+ *
+ * @return None
+ *
+ */
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ __IO uint32_t u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ if (u32TimeMode == RTC_CLOCK_12) {
+ RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk;
+
+ if (u32AmPm == RTC_PM) /* important, range of 12-hour PM mode is 21 upto 32 */
+ u32Hour += 20;
+ } else if(u32TimeMode == RTC_CLOCK_24) {
+ RTC->TSSR |= RTC_TSSR_24H_12H_Msk;
+ }
+
+ u32Reg = ((u32Hour / 10) << 20);
+ u32Reg |= ((u32Hour % 10) << 16);
+ u32Reg |= ((u32Minute / 10) << 12);
+ u32Reg |= ((u32Minute % 10) << 8);
+ u32Reg |= ((u32Second / 10) << 4);
+ u32Reg |= (u32Second % 10);
+
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk));
+
+ RTC->TLR = (uint32_t)g_u32Reg;
+
+}
+
+/**
+ * @brief This function is used to set alarm date to RTC
+ *
+ * @param[in] u32Year The Year Calendar Digit of Alarm Setting
+ * @param[in] u32Month The Month Calendar Digit of Alarm Setting
+ * @param[in] u32Day The Day Calendar Digit of Alarm Setting
+ *
+ * @return None
+ *
+ */
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
+{
+ __IO uint32_t u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ u32Reg = ((u32Year - RTC_YEAR2000) / 10) << 20;
+ u32Reg |= (((u32Year - RTC_YEAR2000) % 10) << 16);
+ u32Reg |= ((u32Month / 10) << 12);
+ u32Reg |= ((u32Month % 10) << 8);
+ u32Reg |= ((u32Day / 10) << 4);
+ u32Reg |= (u32Day % 10);
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ RTC->CAR = (uint32_t)g_u32Reg;
+
+}
+
+/**
+ * @brief This function is used to set alarm date to RTC
+ *
+ * @param[in] u32Hour The Hour Time Digit of Alarm Setting.
+ * @param[in] u32Minute The Month Calendar Digit of Alarm Setting
+ * @param[in] u32Second The Day Calendar Digit of Alarm Setting
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [ \ref RTC_AM / \ref RTC_PM]
+ *
+ * @return None
+ *
+ */
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ __IO uint32_t u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ if (u32TimeMode == RTC_CLOCK_12) {
+ RTC->TSSR &= ~RTC_TSSR_24H_12H_Msk;
+
+ if (u32AmPm == RTC_PM) /* important, range of 12-hour PM mode is 21 upto 32 */
+ u32Hour += 20;
+ } else if(u32TimeMode == RTC_CLOCK_24) {
+ RTC->TSSR |= RTC_TSSR_24H_12H_Msk;
+ }
+
+ u32Reg = ((u32Hour / 10) << 20);
+ u32Reg |= ((u32Hour % 10) << 16);
+ u32Reg |= ((u32Minute / 10) << 12);
+ u32Reg |= ((u32Minute % 10) << 8);
+ u32Reg |= ((u32Second / 10) << 4);
+ u32Reg |= (u32Second % 10);
+
+ g_u32Reg = u32Reg;
+
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ RTC->TAR = (uint32_t)g_u32Reg;
+
+}
+
+
+/**
+ * @brief This function is used to enable tamper detection function and set tamper control register, interrupt.
+ *
+ * @param[in] u32PinCondition set tamper detection condition: 1=Falling detect, 0=Rising detect
+ *
+ * @return None
+ *
+ */
+void RTC_EnableTamperDetection(uint32_t u32PinCondition)
+{
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ /* detection edge select */
+ if(u32PinCondition)
+ RTC->SPRCTL |= RTC_SPRCTL_SNOOPEDGE_Msk;
+ else
+ RTC->SPRCTL &= ~RTC_SPRCTL_SNOOPEDGE_Msk;
+
+ while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRDY_Msk));
+
+ /* enable snooper pin event detection */
+ RTC->SPRCTL |= RTC_SPRCTL_SNOOPEN_Msk;
+ while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRDY_Msk));
+}
+
+/**
+ * @brief This function is used to disable tamper detection function.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+void RTC_DisableTamperDetection(void)
+{
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ RTC->SPRCTL &= ~RTC_SPRCTL_SNOOPEN_Msk;
+}
+
+/**
+ * @brief This function is used to get day of week.
+ *
+ * @param None
+ *
+ * @return Day of week
+ *
+ */
+uint32_t RTC_GetDayOfWeek(void)
+{
+ return (RTC->DWR & RTC_DWR_DWR_Msk);
+}
+
+
+/**
+ * @brief The function is used to set time tick period for periodic time tick Interrupt.
+ *
+ * @param[in] u32TickSelection
+ * It is used to set the RTC time tick period for Periodic Time Tick Interrupt request.
+ * It consists of: \n
+ * \ref RTC_TICK_1_SEC : Time tick is 1 second \n
+ * \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second \n
+ * \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second \n
+ * \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second \n
+ * \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second \n
+ * \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second \n
+ * \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second \n
+ * \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
+ *
+ * @return None
+ *
+ */
+void RTC_SetTickPeriod(uint32_t u32TickSelection)
+{
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ RTC->TTR = RTC->TTR & ~RTC_TTR_TTR_Msk | u32TickSelection;
+}
+
+/**
+ * @brief The function is used to enable specified interrupt.
+ *
+ * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n
+ * \ref RTC_RIER_AIER_Msk : Alarm interrupt \n
+ * \ref RTC_RIER_TIER_Msk : Tick interrupt \n
+ * \ref RTC_RIER_SNOOPIER_Msk : Snooper Pin Event Detection Interrupt\n
+ *
+ * @return None
+ *
+ */
+void RTC_EnableInt(uint32_t u32IntFlagMask)
+{
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ RTC->RIER |= u32IntFlagMask;
+}
+
+/**
+ * @brief The function is used to disable specified interrupt.
+ *
+ * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n
+ * \ref RTC_RIER_AIER_Msk : Alarm interrupt \n
+ * \ref RTC_RIER_TIER_Msk : Tick interrupt \n
+ * \ref RTC_RIER_SNOOPIER_Msk : Snooper Pin Event Detection Interrupt\n
+ *
+ * @return None
+ *
+ */
+void RTC_DisableInt(uint32_t u32IntFlagMask)
+{
+ RTC->AER = RTC_WRITE_KEY;
+ while(!(RTC->AER & RTC_AER_ENF_Msk)) RTC->AER = RTC_WRITE_KEY;
+
+ if(u32IntFlagMask & RTC_RIER_TIER_Msk) {
+ RTC->RIER &= ~RTC_RIER_TIER_Msk;
+ RTC->RIIR = RTC_RIIR_TIF_Msk;
+ }
+
+ if(u32IntFlagMask & RTC_RIER_AIER_Msk) {
+ RTC->RIER &= ~RTC_RIER_AIER_Msk;
+ RTC->RIIR = RTC_RIIR_AIF_Msk;
+ }
+
+ if(u32IntFlagMask & RTC_RIER_SNOOPIER_Msk) {
+ RTC->RIER &= ~RTC_RIER_SNOOPIER_Msk;
+ RTC->RIIR = RTC_RIIR_SNOOPIF_Msk;
+ }
+}
+
+/**
+ * @brief Disable RTC clock.
+ *
+ * @return None
+ *
+ */
+void RTC_Close (void)
+{
+ CLK->APBCLK &= ~CLK_APBCLK_RTC_EN_Msk;
+}
+
+
+/*@}*/ /* end of group NANO100_RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_RTC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_rtc.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,252 @@
+/**************************************************************************//**
+ * @file rtc.h
+ * @version V1.00
+ * $Revision: 7 $
+ * $Date: 15/06/26 1:34p $
+ * @brief Nano100 series RTC driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __RTC_H__
+#define __RTC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_RTC_Driver RTC Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_RTC_EXPORTED_CONSTANTS RTC Exported Constants
+ @{
+*/
+
+
+#define RTC_INIT_KEY 0xA5EB1357 /*!< RTC Access Key */
+#define RTC_WRITE_KEY 0xA965 /*!< RTC Access Key */
+
+#define RTC_WAIT_COUNT 0xFFFFFFFF /*!< Initial Time Out Value */
+
+#define RTC_YEAR2000 2000 /*!< RTC Reference */
+#define RTC_FCR_REFERENCE 32761 /*!< RTC Reference */
+
+#define RTC_CLOCK_12 0 /*!< RTC 12 Hour */
+#define RTC_CLOCK_24 1 /*!< RTC 24 Hour */
+
+#define RTC_AM 1 /*!< RTC AM */
+#define RTC_PM 2 /*!< RTC PM */
+
+#define RTC_TICK_1_SEC ((uint32_t) 0x00000000) /*!< Time tick is 1 second */
+#define RTC_TICK_1_2_SEC ((uint32_t) 0x00000001) /*!< Time tick is 1/2 second */
+#define RTC_TICK_1_4_SEC ((uint32_t) 0x00000002) /*!< Time tick is 1/4 second */
+#define RTC_TICK_1_8_SEC ((uint32_t) 0x00000003) /*!< Time tick is 1/8 second */
+#define RTC_TICK_1_16_SEC ((uint32_t) 0x00000004) /*!< Time tick is 1/16 second */
+#define RTC_TICK_1_32_SEC ((uint32_t) 0x00000005) /*!< Time tick is 1/32 second */
+#define RTC_TICK_1_64_SEC ((uint32_t) 0x00000006) /*!< Time tick is 1/64 second */
+#define RTC_TICK_1_128_SEC ((uint32_t) 0x00000007) /*!< Time tick is 1/128 second */
+
+#define RTC_SUNDAY ((uint32_t) 0x00000000) /*!< Day of week is sunday */
+#define RTC_MONDAY ((uint32_t) 0x00000001) /*!< Day of week is monday */
+#define RTC_TUESDAY ((uint32_t) 0x00000002) /*!< Day of week is tuesday */
+#define RTC_WEDNESDAY ((uint32_t) 0x00000003) /*!< Day of week is wednesday */
+#define RTC_THURSDAY ((uint32_t) 0x00000004) /*!< Day of week is thursday */
+#define RTC_FRIDAY ((uint32_t) 0x00000005) /*!< Day of week is friday */
+#define RTC_SATURDAY ((uint32_t) 0x00000006) /*!< Day of week is saturday */
+
+
+#define RTC_SNOOPER_RISING 0 /*!< Snooper Active Rising Edge */
+#define RTC_SNOOPER_FALLING 1 /*!< Snooper Active Falling Edge */
+
+
+/*@}*/ /* end of group NANO100_RTC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_RTC_EXPORTED_STRUCTS RTC Exported Structs
+ @{
+*/
+
+/**
+ * @brief RTC define Time Data Struct
+ */
+typedef struct {
+ uint32_t u32Year; /*!< Year value */
+ uint32_t u32Month; /*!< Month value */
+ uint32_t u32Day; /*!< Day value */
+ uint32_t u32DayOfWeek; /*!< Day of week value */
+ uint32_t u32Hour; /*!< Hour value */
+ uint32_t u32Minute; /*!< Minute value */
+ uint32_t u32Second; /*!< Second value */
+ uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
+ uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
+} S_RTC_TIME_DATA_T;
+
+/*@}*/ /* end of group NANO100_RTC_EXPORTED_STRUCTS */
+
+
+/** @addtogroup NANO100_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Read spare register
+ *
+ * @param[in] u32RegNum The spare register number(0~23)
+ *
+ * @return Spare register content.
+ *
+ */
+#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[u32RegNum])
+
+/**
+ * @brief Write spare register
+ *
+ * @param[in] u32RegNum The spare register number(0~23)
+ * @param[in] u32RegValue The spare register value
+ *
+ * @return None
+ *
+ */
+#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[u32RegNum] = u32RegValue)
+
+/**
+ * @brief According to current time, return this year is leap year or not
+ *
+ * @param None
+ *
+ * @return 0 = This year is not a leap year. \n
+ * 1 = This year is a leap year.
+ *
+ */
+#define RTC_IS_LEAP_YEAR() ((RTC->LIR & (RTC_LIR_LIR_Msk))?1:0)
+
+/**
+ * @brief Clear alarm interrupt status.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->RIIR = RTC_RIIR_AIF_Msk)
+
+/**
+ * @brief Clear tick interrupt status.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+#define RTC_CLEAR_TICK_INT_FLAG() (RTC->RIIR = RTC_RIIR_TIF_Msk)
+
+/**
+ * @brief Clear tamper detect pin status.
+ *
+ * @param[in] u32PinNum tamper detect pin number.
+ *
+ * @return None
+ *
+ */
+#define RTC_CLEAR_TAMPER_FLAG(u32PinNum) (RTC->RIIR = RTC_RIIR_SNOOPIF_Msk)
+
+/**
+ * @brief Get alarm interrupt status.
+ *
+ * @param None
+ *
+ * @return Alarm interrupt status
+ *
+ */
+#define RTC_GET_ALARM_INT_FLAG() ((RTC->RIIR & RTC_RIIR_AIF_Msk) >> RTC_RIIR_AIF_Pos)
+
+/**
+ * @brief Get alarm interrupt status.
+ *
+ * @param None
+ *
+ * @return Alarm interrupt status
+ *
+ */
+#define RTC_GET_TICK_INT_FLAG() ((RTC->RIIR & RTC_RIIR_TIF_Msk) >> RTC_RIIR_TIF_Pos)
+
+/**
+ * @brief Get tamper detect pin status.
+ *
+ * @param None
+ *
+ * @return 1: Snooper Pin Event Detected \n
+ * 0: Snooper Pin Event Never Detected
+ *
+ */
+#define RTC_GET_TAMPER_FLAG() ( (RTC->RIIR & RTC_RIIR_SNOOPIF_Msk) >> RTC_RIIR_SNOOPIF_Pos)
+
+/**
+ * @brief Enable Timer tick wakeup function.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+#define RTC_ENABLE_TICK_WAKEUP() (RTC->TTR |= RTC_TTR_TWKE_Msk);
+
+/**
+ * @brief Disable Timer tick wakeup function.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ */
+#define RTC_DISABLE_TICK_WAKEUP() (RTC->TTR &= ~RTC_TTR_TWKE_Msk);
+
+
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);
+void RTC_Close(void);
+void RTC_32KCalibration(int32_t i32FrequencyX100);
+void RTC_SetTickPeriod(uint32_t u32TickSelection);
+void RTC_EnableInt(uint32_t u32IntFlagMask);
+void RTC_DisableInt(uint32_t u32IntFlagMask);
+uint32_t RTC_GetDayOfWeek(void);
+void RTC_DisableTamperDetection(void);
+void RTC_EnableTamperDetection(uint32_t u32PinCondition);
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+
+
+
+/*@}*/ /* end of group NANO100_RTC_EXPORTED_FUNCTIONS */
+
+
+/*@}*/ /* end of group NANO100_RTC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RTC_H__ */
+
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_sc.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,261 @@
+/**************************************************************************//**
+ * @file sc.c
+ * @version V1.00
+ * $Revision: 6 $
+ * $Date: 15/07/31 7:30p $
+ * @brief Nano100 series Smartcard(SC) driver source file
+ *
+ * @note
+ * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+// Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined
+/// @cond HIDDEN_SYMBOLS
+static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0, 0, 0};
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SC_Driver SC Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_SC_EXPORTED_FUNCTIONS SC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function indicates specified smartcard slot status
+ * @param[in] sc Base address of smartcard module
+ * @return Card insert status
+ * @retval TRUE Card insert
+ * @retval FALSE Card remove
+ */
+uint32_t SC_IsCardInserted(SC_T *sc)
+{
+ // put conditions into two variable to remove IAR compilation warning
+ uint32_t cond1 = ((sc->PINCSR & SC_PINCSR_CD_PIN_ST_Msk) >> SC_PINCSR_CD_PIN_ST_Pos);
+ uint32_t cond2 = ((sc->PINCSR & SC_PINCSR_CD_LEV_Msk) >> SC_PINCSR_CD_LEV_Pos);
+
+ if(sc == SC0 && u32CardStateIgnore[0] == 1)
+ return TRUE;
+ else if(sc == SC1 && u32CardStateIgnore[1] == 1)
+ return TRUE;
+ else if(sc == SC2 && u32CardStateIgnore[2] == 1)
+ return TRUE;
+ else if(cond1 != cond2)
+ return FALSE;
+ else
+ return TRUE;
+}
+
+/**
+ * @brief This function reset both transmit and receive FIFO of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ */
+void SC_ClearFIFO(SC_T *sc)
+{
+ sc->ALTCTL |= (SC_ALTCTL_TX_RST_Msk | SC_ALTCTL_RX_RST_Msk);
+}
+
+/**
+ * @brief This function disable specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ */
+void SC_Close(SC_T *sc)
+{
+ sc->IER = 0;
+ sc->PINCSR = 0;
+ sc->ALTCTL = 0;
+ sc->CTL = 0;
+}
+
+/**
+ * @brief This function initialized smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card insert. Could be
+ * - \ref SC_PIN_STATE_HIGH
+ * - \ref SC_PIN_STATE_LOW
+ * - \ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present
+ * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be
+ * - \ref SC_PIN_STATE_HIGH
+ * - \ref SC_PIN_STATE_LOW
+ * @return None
+ */
+void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR)
+{
+ uint32_t u32Reg = 0, u32Intf;
+
+ if(sc == SC0)
+ u32Intf = 0;
+ else if(sc == SC1)
+ u32Intf = 1;
+ else
+ u32Intf = 2;
+
+ if(u32CD != SC_PIN_STATE_IGNORE) {
+ u32Reg = u32CD ? 0: SC_PINCSR_CD_LEV_Msk;
+ u32CardStateIgnore[u32Intf] = 0;
+ } else {
+ u32CardStateIgnore[u32Intf] = 1;
+ }
+ u32Reg |= u32PWR ? 0 : SC_PINCSR_POW_INV_Msk;
+ sc->PINCSR = u32Reg;
+ sc->CTL = SC_CTL_SC_CEN_Msk;
+}
+
+/**
+ * @brief This function reset specified smartcard module to its default state for activate smartcard
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ */
+void SC_ResetReader(SC_T *sc)
+{
+ uint32_t u32Intf;
+
+ if(sc == SC0)
+ u32Intf = 0;
+ else if(sc == SC1)
+ u32Intf = 1;
+ else
+ u32Intf = 2;
+
+ // Reset FIFO
+ sc->ALTCTL |= (SC_ALTCTL_TX_RST_Msk | SC_ALTCTL_RX_RST_Msk);
+ // Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry)
+ sc->CTL &= ~(SC_CTL_RX_FTRI_LEV_Msk | SC_CTL_CD_DEB_SEL_Msk | SC_CTL_TX_ERETRY_Msk | SC_CTL_RX_ERETRY_Msk);
+ // Enable auto convention, and all three smartcard internal timers
+ sc->CTL |= SC_CTL_AUTO_CON_EN_Msk | SC_CTL_TMR_SEL_Msk;
+ // Disable Rx timeout
+ sc->RFTMR = 0;
+ // 372 clocks per ETU by default
+ sc->ETUCR = 371;
+ // Enable auto de-activation while card removal
+ sc->PINCSR = (sc->PINCSR & ~SC_PINCSR_POW_EN_Msk) | SC_PINCSR_ADAC_CD_EN_Msk;
+
+ /* Enable necessary interrupt for smartcard operation */
+ if(u32CardStateIgnore[u32Intf]) // Do not enable card detect interrupt if card present state ignore
+ sc->IER = (SC_IER_RDA_IE_Msk |
+ SC_IER_TERR_IE_Msk |
+ SC_IER_TMR0_IE_Msk |
+ SC_IER_TMR1_IE_Msk |
+ SC_IER_TMR2_IE_Msk |
+ SC_IER_BGT_IE_Msk |
+ SC_IER_ACON_ERR_IE_Msk);
+ else
+ sc->IER = (SC_IER_RDA_IE_Msk |
+ SC_IER_TERR_IE_Msk |
+ SC_IER_TMR0_IE_Msk |
+ SC_IER_TMR1_IE_Msk |
+ SC_IER_TMR2_IE_Msk |
+ SC_IER_BGT_IE_Msk |
+ SC_IER_CD_IE_Msk |
+ SC_IER_ACON_ERR_IE_Msk);
+
+ return;
+}
+
+/**
+ * @brief This function block guard time (BGT) of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32
+ * @return None
+ */
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
+{
+ sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1) << SC_CTL_BGT_Pos);
+}
+
+/**
+ * @brief This function character guard time (CGT) of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267
+ * @return None
+ */
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
+{
+ u32CGT -= sc->CTL & SC_CTL_SLEN_Msk ? 11: 12;
+ sc->EGTR = u32CGT;
+}
+
+/**
+ * @brief This function stop all smartcard timer of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @return None
+ * @note This function stop the timers within smartcard module, \b not timer module
+ */
+void SC_StopAllTimer(SC_T *sc)
+{
+ sc->ALTCTL &= ~(SC_ALTCTL_TMR0_SEN_Msk | SC_ALTCTL_TMR1_SEN_Msk | SC_ALTCTL_TMR2_SEN_Msk);
+}
+
+/**
+ * @brief This function configure and start a smartcard timer of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2.
+ * @param[in] u32Mode Timer operating mode, valid values are:
+ * - \ref SC_TMR_MODE_0
+ * - \ref SC_TMR_MODE_1
+ * - \ref SC_TMR_MODE_2
+ * - \ref SC_TMR_MODE_3
+ * - \ref SC_TMR_MODE_4
+ * - \ref SC_TMR_MODE_5
+ * - \ref SC_TMR_MODE_6
+ * - \ref SC_TMR_MODE_7
+ * - \ref SC_TMR_MODE_8
+ * - \ref SC_TMR_MODE_F
+ * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs.
+ * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs
+ * @return None
+ * @note This function start the timer within smartcard module, \b not timer module
+ * @note Depend on the timer operating mode, timer may not start counting immediately
+ */
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
+{
+ uint32_t reg = u32Mode | (SC_TMR0_CNT_Msk & (u32ETUCount - 1));
+
+ if(u32TimerNum == 0) {
+ sc->TMR0 = reg;
+ sc->ALTCTL |= SC_ALTCTL_TMR0_SEN_Msk;
+ } else if(u32TimerNum == 1) {
+ sc->TMR1 = reg;
+ sc->ALTCTL |= SC_ALTCTL_TMR1_SEN_Msk;
+ } else { // timer 2
+ sc->TMR2 = reg;
+ sc->ALTCTL |= SC_ALTCTL_TMR2_SEN_Msk;
+ }
+}
+
+/**
+ * @brief This function stop a smartcard timer of specified smartcard module
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2.
+ * @return None
+ * @note This function stop the timer within smartcard module, \b not timer module
+ */
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
+{
+ if(u32TimerNum == 0)
+ sc->ALTCTL &= ~SC_ALTCTL_TMR0_SEN_Msk;
+ else if(u32TimerNum == 1)
+ sc->ALTCTL &= ~SC_ALTCTL_TMR1_SEN_Msk;
+ else // timer 2
+ sc->ALTCTL &= ~SC_ALTCTL_TMR2_SEN_Msk;
+}
+
+
+
+/*@}*/ /* end of group NANO100_SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_sc.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,265 @@
+/**************************************************************************//**
+ * @file sc.h
+ * @version V1.00
+ * $Revision: 7 $
+ * $Date: 15/07/31 7:26p $
+ * @brief Nano100 series Smartcard (SC) driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2014 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SC_H__
+#define __SC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SC_Driver SC Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SC_EXPORTED_CONSTANTS SC Exported Constants
+ @{
+*/
+#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers */
+#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high */
+#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low */
+#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status */
+#define SC_CLK_ON 1 /*!< Smartcard clock on */
+#define SC_CLK_OFF 0 /*!< Smartcard clock off */
+
+#define SC_TMR_MODE_0 (0ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 0, down count */
+#define SC_TMR_MODE_1 (1ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit */
+#define SC_TMR_MODE_2 (2ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit */
+#define SC_TMR_MODE_3 (3ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode */
+#define SC_TMR_MODE_4 (4ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout */
+#define SC_TMR_MODE_5 (5ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout */
+#define SC_TMR_MODE_6 (6ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout */
+#define SC_TMR_MODE_7 (7ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit */
+#define SC_TMR_MODE_8 (8ul << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 8, up count */
+#define SC_TMR_MODE_F (0xF << SC_TMR0_MODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit */
+
+
+/*@}*/ /* end of group NANO100_SC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_SC_EXPORTED_FUNCTIONS SC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro enable smartcard interrupt
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Mask Interrupt mask to be enabled. A combination of
+ * - \ref SC_IER_ACON_ERR_IE_Msk
+ * - \ref SC_IER_RTMR_IE_Msk
+ * - \ref SC_IER_INIT_IE_Msk
+ * - \ref SC_IER_CD_IE_Msk
+ * - \ref SC_IER_BGT_IE_Msk
+ * - \ref SC_IER_TMR2_IE_Msk
+ * - \ref SC_IER_TMR1_IE_Msk
+ * - \ref SC_IER_TMR0_IE_Msk
+ * - \ref SC_IER_TERR_IE_Msk
+ * - \ref SC_IER_TBE_IE_Msk
+ * - \ref SC_IER_RDA_IE_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SC_ENABLE_INT(sc, u32Mask) ((sc)->IER |= (u32Mask))
+
+/**
+ * @brief This macro disable smartcard interrupt
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Mask Interrupt mask to be disabled. A combination of
+ * - \ref SC_IER_ACON_ERR_IE_Msk
+ * - \ref SC_IER_RTMR_IE_Msk
+ * - \ref SC_IER_INIT_IE_Msk
+ * - \ref SC_IER_CD_IE_Msk
+ * - \ref SC_IER_BGT_IE_Msk
+ * - \ref SC_IER_TMR2_IE_Msk
+ * - \ref SC_IER_TMR1_IE_Msk
+ * - \ref SC_IER_TMR0_IE_Msk
+ * - \ref SC_IER_TERR_IE_Msk
+ * - \ref SC_IER_TBE_IE_Msk
+ * - \ref SC_IER_RDA_IE_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SC_DISABLE_INT(sc, u32Mask) ((sc)->IER &= ~(u32Mask))
+
+/**
+ * @brief This macro set VCC pin state of smartcard interface
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_VCC_PIN(sc, u32State) \
+ do {\
+ uint32_t reg = (sc)->PINCSR;\
+ if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
+ ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
+ reg &= ~SC_PINCSR_POW_EN_Msk;\
+ else\
+ reg |= SC_PINCSR_POW_EN_Msk;\
+ if(u32State)\
+ (sc)->PINCSR = reg | SC_PINCSR_POW_EN_Msk;\
+ else\
+ (sc)->PINCSR = reg & ~SC_PINCSR_POW_EN_Msk;\
+ }while(0)
+
+
+/**
+ * @brief This macro turns CLK output on or off
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_CLK_PIN(sc, u32OnOff)\
+ do {\
+ uint32_t reg = (sc)->PINCSR;\
+ if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
+ ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
+ reg &= ~SC_PINCSR_POW_EN_Msk;\
+ else\
+ reg |= SC_PINCSR_POW_EN_Msk;\
+ if(u32OnOff)\
+ (sc)->PINCSR = reg | SC_PINCSR_CLK_KEEP_Msk;\
+ else\
+ (sc)->PINCSR = reg & ~SC_PINCSR_CLK_KEEP_Msk;\
+ }while(0)
+
+/**
+ * @brief This macro set I/O pin state of smartcard interface
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_IO_PIN(sc, u32State)\
+ do {\
+ uint32_t reg = (sc)->PINCSR;\
+ if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
+ ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
+ reg &= ~SC_PINCSR_POW_EN_Msk;\
+ else\
+ reg |= SC_PINCSR_POW_EN_Msk;\
+ if(u32State)\
+ (sc)->PINCSR = reg | SC_PINCSR_SC_DATA_O_Msk;\
+ else\
+ (sc)->PINCSR = reg & ~SC_PINCSR_SC_DATA_O_Msk;\
+ }while(0)
+
+/**
+ * @brief This macro set RST pin state of smartcard interface
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
+ * @return None
+ * \hideinitializer
+ */
+#define SC_SET_RST_PIN(sc, u32State)\
+ do {\
+ uint32_t reg = (sc)->PINCSR;\
+ if(((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == 0) ||\
+ ((reg & (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)) == (SC_PINCSR_POW_EN_Msk | SC_PINCSR_POW_INV_Msk)))\
+ reg &= ~SC_PINCSR_POW_EN_Msk;\
+ else\
+ reg |= SC_PINCSR_POW_EN_Msk;\
+ if(u32State)\
+ (sc)->PINCSR = reg | SC_PINCSR_SC_RST_Msk;\
+ else\
+ (sc)->PINCSR = reg & ~SC_PINCSR_SC_RST_Msk;\
+ }while(0)
+
+/**
+ * @brief This macro read one byte from smartcard module receive FIFO
+ * @param[in] sc Base address of smartcard module
+ * @return[in] One byte read from receive FIFO
+ * \hideinitializer
+ */
+#define SC_READ(sc) ((char)((sc)->RBR))
+
+/**
+ * @brief This macro write one byte to smartcard module transmit FIFO
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u8Data Data to write to transmit FIFO
+ * @return None
+ * \hideinitializer
+ */
+#define SC_WRITE(sc, u8Data) ((sc)->THR = (u8Data))
+
+/**
+ * @brief This macro set smartcard stop bit length
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Len Stop bit length, ether 1 or 2.
+ * @return None
+ * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
+ * \hideinitializer
+ */
+#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_SLEN_Msk) | (u32Len == 1 ? SC_CTL_SLEN_Msk : 0))
+
+/**
+ * @brief Enable/Disable Tx error retry, and set Tx error retry count
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry
+ * @return None
+ */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
+{
+ if(u32Count == 0) { // disable Tx error retry
+ sc->CTL &= ~(SC_CTL_TX_ERETRY_Msk | SC_CTL_TX_ERETRY_EN_Msk);
+ } else {
+ sc->CTL = (sc->CTL & ~SC_CTL_TX_ERETRY_Msk) | ((u32Count - 1) << SC_CTL_TX_ERETRY_Pos) | SC_CTL_TX_ERETRY_EN_Msk;
+ }
+}
+
+/**
+ * @brief Enable/Disable Rx error retry, and set Rx error retry count
+ * @param[in] sc Base address of smartcard module
+ * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry
+ * @return None
+ */
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
+{
+
+ if(u32Count == 0) { // disable Rx error retry
+ sc->CTL &= ~(SC_CTL_RX_ERETRY_Msk | SC_CTL_RX_ERETRY_EN_Msk);
+ } else {
+ sc->CTL = (sc->CTL & ~SC_CTL_RX_ERETRY_Msk) | ((u32Count - 1) << SC_CTL_RX_ERETRY_Pos) | SC_CTL_RX_ERETRY_EN_Msk;
+ }
+}
+
+
+uint32_t SC_IsCardInserted(SC_T *sc);
+void SC_ClearFIFO(SC_T *sc);
+void SC_Close(SC_T *sc);
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
+void SC_ResetReader(SC_T *sc);
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
+void SC_StopAllTimer(SC_T *sc);
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
+
+
+/*@}*/ /* end of group NANO100_SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SC_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SC_H__
+
+/*** (C) COPYRIGHT 2013~2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_scuart.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,192 @@
+/**************************************************************************//**
+ * @file scuart.c
+ * @version V1.00
+ * $Revision: 5 $
+ * $Date: 15/05/14 11:14a $
+ * @brief Nano100 series Smartcard UART mode (SCUART) driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SCUART_Driver SCUART Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+ @{
+*/
+
+/**
+ * @brief The function is used to disable smartcard interface UART mode.
+ * @param sc The base address of smartcard module.
+ * @return None
+ */
+void SCUART_Close(SC_T* sc)
+{
+ sc->IER = 0;
+ sc->UACTL = 0;
+ sc->CTL = 0;
+
+}
+
+/// @cond HIDDEN_SYMBOLS
+/**
+ * @brief This function returns module clock of specified SC interface
+ * @param[in] sc The base address of smartcard module.
+ * @return Module clock of specified SC interface
+ */
+static uint32_t SCUART_GetClock(SC_T *sc)
+{
+ uint32_t u32ClkSrc = (CLK->CLKSEL2 & CLK_CLKSEL2_SC_S_Msk) >> CLK_CLKSEL2_SC_S_Pos;
+ uint32_t u32Clk;
+
+ // Get smartcard module clock
+ if(u32ClkSrc == 0)
+ u32Clk = __HXT;
+ else if(u32ClkSrc == 1)
+ u32Clk = CLK_GetPLLClockFreq();
+ else
+ u32Clk = __HIRC12M;
+
+ if(sc == SC0)
+ u32Clk /= ((CLK->CLKDIV0 & CLK_CLKDIV0_SC0_N_Msk) >> CLK_CLKDIV0_SC0_N_Pos) + 1;
+ else if(sc == SC1)
+ u32Clk /= (CLK->CLKDIV1 & CLK_CLKDIV1_SC1_N_Msk) + 1;
+ else // SC2
+ u32Clk /= ((CLK->CLKDIV1 & CLK_CLKDIV1_SC2_N_Msk) >> CLK_CLKDIV1_SC2_N_Pos) + 1;
+
+ return u32Clk;
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+ * @brief This function use to enable smartcard module UART mode and set baudrate.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u32baudrate Target baudrate of smartcard module.
+ * @return Actual baudrate of smartcard mode
+ * @note This function configures character width to 8 bits, 1 stop bit, and no parity.
+ * And can use \ref SCUART_SetLineConfig function to update these settings
+ */
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate)
+{
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+ // Calculate divider for target baudrate
+ u32Div = (u32Clk + (u32baudrate >> 1) - 1) / u32baudrate - 1;
+
+ sc->CTL = SC_CTL_SC_CEN_Msk | SC_CTL_SLEN_Msk; // Enable smartcard interface and stop bit = 1
+ sc->UACTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UACTL_UA_MODE_EN_Msk; // Enable UART mode, disable parity and 8 bit per character
+ sc->ETUCR = u32Div;
+
+ return(u32Clk / (u32Div + 1));
+}
+
+/**
+ * @brief The function is used to read Rx data from RX FIFO.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] pu8RxBuf The buffer to store receive the data
+ * @param[in] u32ReadBytes Target number of characters to receive
+ * @return Actual character number reads to buffer
+ * @note This function does not block and return immediately if there's no data available
+ */
+uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
+{
+ uint32_t u32Count;
+
+ for(u32Count = 0; u32Count < u32ReadBytes; u32Count++) {
+ if(SCUART_GET_RX_EMPTY(sc)) { // no data available
+ break;
+ }
+ pu8RxBuf[u32Count] = SCUART_READ(sc); // get data from FIFO
+ }
+
+ return u32Count;
+}
+
+/**
+ * @brief This function use to config smartcard UART mode line setting.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
+ * @param[in] u32DataWidth The data length, could be
+ * - \ref SCUART_CHAR_LEN_5
+ * - \ref SCUART_CHAR_LEN_6
+ * - \ref SCUART_CHAR_LEN_7
+ * - \ref SCUART_CHAR_LEN_8
+ * @param[in] u32Parity The parity setting, could be
+ * - \ref SCUART_PARITY_NONE
+ * - \ref SCUART_PARITY_ODD
+ * - \ref SCUART_PARITY_EVEN
+ * @param[in] u32StopBits The stop bit length, could be
+ * - \ref SCUART_STOP_BIT_1
+ * - \ref SCUART_STOP_BIT_2
+ * @return Actual baudrate of smartcard
+ */
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
+{
+
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+ if(u32Baudrate == 0) { // keep original baudrate setting
+ u32Div = sc->ETUCR & SC_ETUCR_ETU_RDIV_Msk;
+ } else {
+ // Calculate divider for target baudrate
+ u32Div = (u32Clk + (u32Baudrate >> 1) - 1)/ u32Baudrate - 1;
+ sc->ETUCR = u32Div;
+ }
+
+ sc->CTL = u32StopBits | SC_CTL_SC_CEN_Msk; // Set stop bit
+ sc->UACTL = u32Parity | u32DataWidth | SC_UACTL_UA_MODE_EN_Msk; // Set character width and parity
+
+ return(u32Clk / (u32Div + 1));
+}
+
+/**
+ * @brief This function use to set receive timeout count.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
+ * set this value to 0 will disable timeout counter
+ * @return None
+ * @details The time-out counter resets and starts counting whenever the RX buffer received a
+ * new data word. Once the counter decrease to 1 and no new data is received or CPU
+ * does not read any data from FIFO, a receiver time-out interrupt will be generated.
+ */
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
+{
+ sc->RFTMR = u32TOC;
+}
+
+
+/**
+ * @brief This function is to write data into transmit FIFO to send data out.
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
+ * @param[in] u32WriteBytes Number of data to send.
+ * @return None
+ * @note This function blocks until all data write into FIFO
+ */
+void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
+{
+ uint32_t u32Count;
+
+ for(u32Count = 0; u32Count != u32WriteBytes; u32Count++) {
+ while(SCUART_GET_TX_FULL(sc)); // Wait 'til FIFO not full
+ sc->THR = pu8TxBuf[u32Count]; // Write 1 byte to FIFO
+ }
+}
+
+
+/*@}*/ /* end of group NANO100_SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SCUART_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_scuart.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,260 @@
+/**************************************************************************//**
+ * @file sc.h
+ * @version V1.00
+ * $Revision: 3 $
+ * $Date: 14/05/20 7:57p $
+ * @brief Nano100 series Smartcard UART mode (SCUART) driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SCUART_H__
+#define __SCUART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SCUART_Driver SCUART Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
+ @{
+*/
+#define SCUART_CHAR_LEN_5 (0x3ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 5 bits */
+#define SCUART_CHAR_LEN_6 (0x2ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 6 bits */
+#define SCUART_CHAR_LEN_7 (0x1ul << SC_UACTL_DATA_LEN_Pos) /*!< Set SCUART word length to 7 bits */
+#define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits */
+
+#define SCUART_PARITY_NONE (SC_UACTL_PBDIS_Msk) /*!< Set SCUART transfer with no parity */
+#define SCUART_PARITY_ODD (SC_UACTL_OPE_Msk) /*!< Set SCUART transfer with odd parity */
+#define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity */
+
+#define SCUART_STOP_BIT_1 (SC_CTL_SLEN_Msk) /*!< Set SCUART transfer with one stop bit */
+#define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits */
+
+
+/*@}*/ /* end of group NANO100_SCUART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+ @{
+*/
+
+/* TX Macros */
+/**
+ * @brief Write Data to Tx data register
+ * @param[in] sc The base address of smartcard module.
+ * @param[in] u8Data Data byte to transmit
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_WRITE(sc, u8Data) ((sc)->THR = (u8Data))
+
+/**
+ * @brief Get TX FIFO empty flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit FIFO empty status
+ * @retval 0 Transmit FIFO is not empty
+ * @retval SC_TRSR_TX_EMPTY_F_Msk Transmit FIFO is empty
+ * \hideinitializer
+ */
+#define SCUART_GET_TX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_TX_EMPTY_F_Msk)
+
+/**
+ * @brief Get TX FIFO full flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit FIFO full status
+ * @retval 0 Transmit FIFO is not full
+ * @retval SC_TRSR_TX_FULL_F_Msk Transmit FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_GET_TX_FULL(sc) ((sc)->TRSR & SC_TRSR_TX_FULL_F_Msk)
+
+/**
+ * @brief Wait specified smartcard port transmission complete
+ * @param[in] sc The base address of smartcard module
+ * @return None
+ * @note This Macro blocks until transmit complete.
+ * \hideinitializer
+ */
+#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->TRSR & SC_TRSR_TX_ATV_Msk)
+
+/**
+ * @brief Check specified smartcard port transmit FIFO is full or not
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit FIFO full status
+ * @retval 0 Transmit FIFO is not full
+ * @retval 1 Transmit FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_IS_TX_FULL(sc) ((sc)->TRSR & SC_TRSR_TX_FULL_F_Msk ? 1 : 0)
+
+/**
+ * @brief Check specified smartcard port transmission is over
+ * @param[in] sc The base address of smartcard module
+ * @return Transmit complete status
+ * @retval 0 Transmit is not complete
+ * @retval 1 Transmit complete
+ * \hideinitializer
+ */
+#define SCUART_IS_TX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_TX_ATV_Msk ? 0 : 1)
+
+
+/* RX Macros */
+
+/**
+ * @brief Read Rx data register
+ * @param[in] sc The base address of smartcard module
+ * @return The oldest data byte in RX FIFO
+ * \hideinitializer
+ */
+#define SCUART_READ(sc) ((sc)->RBR)
+
+/**
+ * @brief Get RX FIFO empty flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO empty status
+ * @retval 0 Receive FIFO is not empty
+ * @retval SC_TRSR_RX_EMPTY_F_Msk Receive FIFO is empty
+ * \hideinitializer
+ */
+#define SCUART_GET_RX_EMPTY(sc) ((sc)->TRSR & SC_TRSR_RX_EMPTY_F_Msk)
+
+
+/**
+ * @brief Get RX FIFO full flag status from register
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO full status
+ * @retval 0 Receive FIFO is not full
+ * @retval SC_TRSR_TX_FULL_F_Msk Receive FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_GET_RX_FULL(sc) ((sc)->TRSR & SC_TRSR_RX_FULL_F_Msk)
+
+/**
+ * @brief Check if receive data number in FIFO reach FIFO trigger level or not
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO data status
+ * @retval 0 The number of bytes in receive FIFO is less than trigger level
+ * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
+ * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO
+ * \hideinitializer
+ */
+#define SCUART_IS_RX_READY(sc) ((sc)->ISR & SC_ISR_RDA_IS_Msk ? 1 : 0)
+
+/**
+ * @brief Check specified smartcard port receive FIFO is full or not
+ * @param[in] sc The base address of smartcard module
+ * @return Receive FIFO full status
+ * @retval 0 Receive FIFO is not full
+ * @retval 1 Receive FIFO is full
+ * \hideinitializer
+ */
+#define SCUART_IS_RX_FULL(sc) ((sc)->TRSR & SC_TRSR_RX_FULL_F_Msk ? 1 : 0)
+
+/* Interrupt Macros */
+
+/**
+ * @brief Enable specified interrupts
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Mask Interrupt masks to enable, a combination of following bits
+ * - \ref SC_IER_RTMR_IE_Msk
+ * - \ref SC_IER_TERR_IE_Msk
+ * - \ref SC_IER_TBE_IE_Msk
+ * - \ref SC_IER_RDA_IE_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->IER |= (u32Mask))
+
+/**
+ * @brief Disable specified interrupts
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Mask Interrupt masks to disable, a combination of following bits
+ * - \ref SC_IER_RTMR_IE_Msk
+ * - \ref SC_IER_TERR_IE_Msk
+ * - \ref SC_IER_TBE_IE_Msk
+ * - \ref SC_IER_RDA_IE_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->IER &= ~(u32Mask))
+
+/**
+ * @brief Get specified interrupt flag/status
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Type Interrupt flag/status to check, could be one of following value
+ * - \ref SC_ISR_RTMR_IS_Msk
+ * - \ref SC_ISR_TERR_IS_Msk
+ * - \ref SC_ISR_TBE_IS_Msk
+ * - \ref SC_ISR_RDA_IS_Msk
+ * @return The status of specified interrupt
+ * @retval 0 Specified interrupt does not happened
+ * @retval 1 Specified interrupt happened
+ * \hideinitializer
+ */
+#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->ISR & u32Type ? 1 : 0)
+
+/**
+ * @brief Clear specified interrupt flag/status
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
+ * - \ref SC_ISR_RTMR_IS_Msk
+ * - \ref SC_ISR_TERR_IS_Msk
+ * - \ref SC_ISR_TBE_IS_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->ISR = u32Type)
+
+/**
+ * @brief Get receive error flag/status
+ * @param[in] sc The base address of smartcard module
+ * @return Current receive error status, could one of following errors:
+ * @retval SC_TRSR_RX_EPA_F_Msk Parity error
+ * @retval SC_TRSR_RX_EFR_F_Msk Frame error
+ * @retval SC_TRSR_RX_EBR_F_Msk Break error
+ * \hideinitializer
+ */
+#define SCUART_GET_ERR_FLAG(sc) ((sc)->TRSR & (SC_TRSR_RX_EPA_F_Msk | SC_TRSR_RX_EFR_F_Msk | SC_TRSR_RX_EBR_F_Msk))
+
+/**
+ * @brief Clear specified receive error flag/status
+ * @param[in] sc The base address of smartcard module
+ * @param[in] u32Mask Receive error flag/status to clear, combination following values
+ * - \ref SC_TRSR_RX_EPA_F_Msk
+ * - \ref SC_TRSR_RX_EFR_F_Msk
+ * - \ref SC_TRSR_RX_EBR_F_Msk
+ * @return None
+ * \hideinitializer
+ */
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->TRSR = u32Mask)
+
+void SCUART_Close(SC_T* sc);
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
+uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
+void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
+
+/*@}*/ /* end of group NANO100_SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SCUART_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SCUART_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_spi.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,321 @@
+/****************************************************************************//**
+ * @file spi.c
+ * @version V0.10
+ * $Revision: 7 $
+ * $Date: 15/05/28 1:33p $
+ * @brief NANO100 series SPI driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SPI_Driver SPI Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make SPI module be ready to transfer.
+ * By default, the SPI transfer sequence is MSB first and
+ * the automatic slave select function is disabled. In
+ * Slave mode, the u32BusClock must be NULL and the SPI clock
+ * divider setting will be 0.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are:
+ * - \ref SPI_MASTER
+ * - \ref SPI_SLAVE
+ * @param[in] u32SPIMode decides the transfer timing. Valid values are:
+ * - \ref SPI_MODE_0
+ * - \ref SPI_MODE_1
+ * - \ref SPI_MODE_2
+ * - \ref SPI_MODE_3
+ * @param[in] u32DataWidth decides the data width of a SPI transaction.
+ * @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz.
+ * @return Actual frequency of SPI peripheral clock.
+ */
+uint32_t SPI_Open(SPI_T *spi,
+ uint32_t u32MasterSlave,
+ uint32_t u32SPIMode,
+ uint32_t u32DataWidth,
+ uint32_t u32BusClock)
+{
+ if(u32DataWidth == 32)
+ u32DataWidth = 0;
+
+ spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode);
+
+ return ( SPI_SetBusClock(spi, u32BusClock) );
+}
+
+/**
+ * @brief Reset SPI module and disable SPI peripheral clock.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ */
+void SPI_Close(SPI_T *spi)
+{
+ /* Reset SPI */
+ if(spi == SPI0) {
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI0_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk;
+ } else if(spi == SPI1) {
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI1_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk;
+ } else {
+ SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI2_RST_Msk;
+ SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI2_RST_Msk;
+ }
+}
+
+/**
+ * @brief Clear Rx FIFO buffer.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ */
+void SPI_ClearRxFIFO(SPI_T *spi)
+{
+ spi->FFCTL |= SPI_FFCTL_RX_CLR_Msk;
+}
+
+/**
+ * @brief Clear Tx FIFO buffer.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ */
+void SPI_ClearTxFIFO(SPI_T *spi)
+{
+ spi->FFCTL |= SPI_FFCTL_TX_CLR_Msk;
+}
+
+/**
+ * @brief Disable the automatic slave select function.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ */
+void SPI_DisableAutoSS(SPI_T *spi)
+{
+ spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
+}
+
+/**
+ * @brief Enable the automatic slave select function. Only available in Master mode.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32SSPinMask specifies slave select pins. (SPI_SS)
+ * @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are:
+ * - \ref SPI_SS0_ACTIVE_HIGH
+ * - \ref SPI_SS0_ACTIVE_LOW
+ * - \ref SPI_SS1_ACTIVE_HIGH
+ * - \ref SPI_SS1_ACTIVE_LOW
+ * @return none
+ */
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+ spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
+}
+
+/**
+ * @brief Set the SPI bus clock. Only available in Master mode.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32BusClock is the expected frequency of SPI bus clock.
+ * @return Actual frequency of SPI peripheral clock.
+ */
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc, u32Div = 0;
+
+ if(spi == SPI0) {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ } else if(spi == SPI1) {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ } else {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+
+ if(u32BusClock > u32ClkSrc)
+ u32BusClock = u32ClkSrc;
+
+ if(u32BusClock != 0 ) {
+ u32Div = (u32ClkSrc / u32BusClock) - 1;
+ if(u32Div > SPI_CLKDIV_DIVIDER1_Msk)
+ u32Div = SPI_CLKDIV_DIVIDER1_Msk;
+ } else
+ u32Div = 0;
+
+ spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div;
+
+ return ( u32ClkSrc / (u32Div+1) );
+}
+
+/**
+ * @brief Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32TxThreshold decides the Tx FIFO threshold.
+ * @param[in] u32RxThreshold decides the Rx FIFO threshold.
+ * @return none
+ */
+void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ spi->FFCTL = (spi->FFCTL & ~(SPI_FFCTL_TX_THRESHOLD_Msk | SPI_FFCTL_RX_THRESHOLD_Msk) |
+ (u32TxThreshold << SPI_FFCTL_TX_THRESHOLD_Pos) |
+ (u32RxThreshold << SPI_FFCTL_RX_THRESHOLD_Pos));
+
+ spi->CTL |= SPI_CTL_FIFOM_Msk;
+}
+
+/**
+ * @brief Disable FIFO mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ */
+void SPI_DisableFIFO(SPI_T *spi)
+{
+ spi->CTL &= ~SPI_CTL_FIFOM_Msk;
+}
+
+/**
+ * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return Actual SPI bus clock frequency.
+ */
+uint32_t SPI_GetBusClock(SPI_T *spi)
+{
+ uint32_t u32Div;
+ uint32_t u32ClkSrc;
+
+ if(spi == SPI0) {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ } else if(spi == SPI1) {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ } else {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
+ u32ClkSrc = CLK_GetHCLKFreq();
+ else
+ u32ClkSrc = CLK_GetPLLClockFreq();
+ }
+
+ u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER1_Msk;
+ return (u32ClkSrc / (u32Div + 1));
+}
+
+/**
+ * @brief Enable FIFO related interrupts specified by u32Mask parameter.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be enabled. Valid values are:
+ * - \ref SPI_IE_MASK
+ * - \ref SPI_SSTA_INTEN_MASK
+ * - \ref SPI_FIFO_TX_INTEN_MASK
+ * - \ref SPI_FIFO_RX_INTEN_MASK
+ * - \ref SPI_FIFO_RXOVR_INTEN_MASK
+ * - \ref SPI_FIFO_TIMEOUT_INTEN_MASK
+ * @return none
+ */
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
+ spi->CTL |= SPI_CTL_INTEN_Msk;
+
+ if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
+ spi->SSR |= SPI_SSR_SSTA_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
+ spi->FFCTL |= SPI_FFCTL_TX_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
+ spi->FFCTL |= SPI_FFCTL_RX_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
+ spi->FFCTL |= SPI_FFCTL_RXOVR_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
+ spi->FFCTL |= SPI_FFCTL_TIMEOUT_EN_Msk;
+}
+
+/**
+ * @brief Disable FIFO related interrupts specified by u32Mask parameter.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32Mask is the combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be enabled. Valid values are:
+ * - \ref SPI_IE_MASK
+ * - \ref SPI_SSTA_INTEN_MASK
+ * - \ref SPI_FIFO_TX_INTEN_MASK
+ * - \ref SPI_FIFO_RX_INTEN_MASK
+ * - \ref SPI_FIFO_RXOVR_INTEN_MASK
+ * - \ref SPI_FIFO_TIMEOUT_INTEN_MASK
+ * @return none
+ */
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
+ spi->CTL &= ~SPI_CTL_INTEN_Msk;
+
+ if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
+ spi->SSR &= ~SPI_SSR_SSTA_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
+ spi->FFCTL &= ~SPI_FFCTL_TX_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
+ spi->FFCTL &= ~SPI_FFCTL_RX_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
+ spi->FFCTL &= ~SPI_FFCTL_RXOVR_INTEN_Msk;
+
+ if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
+ spi->FFCTL &= ~SPI_FFCTL_TIMEOUT_EN_Msk;
+}
+
+/**
+ * @brief Enable wake-up function.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ */
+void SPI_EnableWakeup(SPI_T *spi)
+{
+ spi->CTL |= SPI_CTL_WKEUP_EN_Msk;
+}
+
+/**
+ * @brief Disable wake-up function.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ */
+void SPI_DisableWakeup(SPI_T *spi)
+{
+ spi->CTL &= ~SPI_CTL_WKEUP_EN_Msk;
+}
+
+/*@}*/ /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SPI_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_spi.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,386 @@
+/****************************************************************************//**
+ * @file spi.h
+ * @version V1.00
+ * $Revision: 8 $
+ * $Date: 15/06/08 5:03p $
+ * @brief NANO100 series SPI driver header file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SPI_Driver SPI Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_SPI_EXPORTED_CONSTANTS SPI Exported Constants
+ @{
+*/
+
+#define SPI_MODE_0 (SPI_CTL_TX_NEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
+#define SPI_MODE_1 (SPI_CTL_RX_NEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
+#define SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
+#define SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
+
+#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
+#define SPI_MASTER (0x0) /*!< Set as master */
+
+#define SPI_SS0 (0x1) /*!< Set SS0 */
+#define SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS0 active high */
+#define SPI_SS0_ACTIVE_LOW (0x0) /*!< SS0 active low */
+
+#define SPI_SS1 (0x2) /*!< Set SS1 */
+#define SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) /*!< SS1 active high */
+#define SPI_SS1_ACTIVE_LOW (0x0) /*!< SS1 active low */
+
+#define SPI_IE_MASK (0x01) /*!< Interrupt enable mask */
+#define SPI_SSTA_INTEN_MASK (0x04) /*!< Slave 3-Wire mode start interrupt enable mask */
+#define SPI_FIFO_TX_INTEN_MASK (0x08) /*!< FIFO TX interrupt mask */
+#define SPI_FIFO_RX_INTEN_MASK (0x10) /*!< FIFO RX interrupt mask */
+#define SPI_FIFO_RXOVR_INTEN_MASK (0x20) /*!< FIFO RX overrun interrupt mask */
+#define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) /*!< FIFO timeout interrupt mask */
+
+
+/*@}*/ /* end of group NANO100_SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Abort the current transfer in slave 3-wire mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSR |= SPI_SSR_SLV_ABORT_Msk )
+
+/**
+ * @brief Clear the slave 3-wire mode start interrupt flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk )
+
+/**
+ * @brief Clear the unit transfer interrupt flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_INTSTS_Msk )
+
+/**
+ * @brief Disable slave 3-wire mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSR &= ~SPI_SSR_NOSLVSEL_Msk )
+
+/**
+ * @brief Enable slave 3-wire mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSR |= SPI_SSR_NOSLVSEL_Msk )
+
+/**
+ * @brief Get the count of available data in RX FIFO.
+ * @param[in] spi is the base address of SPI module.
+ * @return The count of available data in RX FIFO.
+ * \hideinitializer
+ */
+#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RX_FIFO_CNT_Msk) >> SPI_STATUS_RX_FIFO_CNT_Pos) & 0xf )
+
+/**
+ * @brief Get the Rx FIFO empty flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return Rx FIFO flag
+ * @retval 0 Rx FIFO is not empty
+ * @retval 1 Rx FIFO is empty
+ * \hideinitializer
+ */
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0)
+
+/**
+ * @brief Get the Tx FIFO empty flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return Tx FIFO flag
+ * @retval 0 Tx FIFO is not empty
+ * @retval 1 Tx FIFO is empty
+ * \hideinitializer
+ */
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0)
+
+/**
+ * @brief Get the Tx FIFO full flag.
+ * @param[in] spi is the base address of SPI module.
+ * @return Tx FIFO flag
+ * @retval 0 Tx FIFO is not full
+ * @retval 1 Tx FIFO is full
+ * \hideinitializer
+ */
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0)
+
+/**
+ * @brief Get the datum read from RX0 FIFO.
+ * @param[in] spi is the base address of SPI module.
+ * @return Data in Rx0 register.
+ * \hideinitializer
+ */
+#define SPI_READ_RX0(spi) ( (spi)->RX0 )
+
+/**
+ * @brief Get the datum read from RX1 FIFO.
+ * @param[in] spi is the base address of SPI module.
+ * @return Data in Rx1 register.
+ */
+#define SPI_READ_RX1(spi) ( (spi)->RX1 )
+
+/**
+ * @brief Write datum to TX0 register.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_WRITE_TX0(spi, u32TxData) ( (spi)->TX0 = u32TxData )
+
+/**
+ * @brief Write datum to TX1 register.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_WRITE_TX1(spi, u32TxData) ( (spi)->TX1 = u32TxData )
+
+/**
+ * @brief Set SPIn_SS0 pin to high state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIn_SS0 pin to high state. Only available in Master mode.
+ * \hideinitializer
+ */
+#define SPI_SET_SS0_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)))
+
+/**
+ * @brief Set SPIn_SS0 pin to low state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIn_SS0 pin to low state. Only available in Master mode.
+ * \hideinitializer
+ */
+#define SPI_SET_SS0_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)) | SPI_SS0)
+
+/**
+ * @brief Set SPIn_SS1 pin to high state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIn_SS1 pin to high state. Only available in Master mode.
+ * \hideinitializer
+ */
+#define SPI_SET_SS1_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)))
+
+/**
+ * @brief Set SPIn_SS1 pin to low state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIn_SS1 pin to low state. Only available in Master mode.
+ * \hideinitializer
+ */
+#define SPI_SET_SS1_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)) | SPI_SS1)
+
+/**
+ * @brief Set SPIn_SS0, SPIn_SS1 pin to high or low state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] ss0 0 = Set SPIn_SS0 to low. 1 = Set SPIn_SS0 to high.
+ * @param[in] ss1 0 = Set SPIn_SS1 to low. 1 = Set SPIn_SS1 to high.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIn_SS0/SPIn_SS1 pin to specified high/low state.
+ * Only available in Master mode.
+ */
+#define SPI_SET_SS_LEVEL(spi, ss0, ss1) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SSR_SSR_Msk)) | (((ss1)^1) << 1) | ((ss0)^1))
+
+/**
+ * @brief Enable byte reorder function.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
+
+/**
+ * @brief Disable byte reorder function.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
+
+/**
+ * @brief Set the length of suspend interval.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32SuspCycle decides the length of suspend interval.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CTL_SP_CYCLE_Pos) )
+
+/**
+ * @brief Set the SPI transfer sequence with LSB first.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
+
+/**
+ * @brief Set the SPI transfer sequence with MSB first.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
+
+/**
+ * @brief Set the data width of a SPI transaction.
+ * @param[in] spi is the base address of SPI module.
+ * @param[in] u32Width is the data width (from 8-32 bits).
+ * @return none
+ * \hideinitializer
+ */
+static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
+{
+ if(u32Width == 32)
+ u32Width = 0;
+
+ spi->CTL = (spi->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (u32Width << SPI_CTL_TX_BIT_LEN_Pos);
+}
+
+/**
+ * @brief Get the SPI busy state.
+ * @param[in] spi is the base address of SPI module.
+ * @return SPI busy status
+ * @retval 0 SPI module is not busy
+ * @retval 1 SPI module is busy
+ * \hideinitializer
+ */
+#define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_GO_BUSY_Msk) == SPI_CTL_GO_BUSY_Msk ? 1:0)
+
+/**
+ * @brief Set the GO_BUSY bit to trigger SPI transfer.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_GO_BUSY_Msk )
+
+/**
+ * @brief Disable SPI Dual IO function.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUAL_IO_EN_Msk )
+
+/**
+ * @brief Enable Dual IO function and set SPI Dual IO direction to input.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DUAL_IO_DIR_Msk) | SPI_CTL_DUAL_IO_EN_Msk )
+
+/**
+ * @brief Enable Dual IO function and set SPI Dual IO direction to output.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= (SPI_CTL_DUAL_IO_DIR_Msk | SPI_CTL_DUAL_IO_EN_Msk) )
+
+/**
+ * @brief Trigger RX PDMA transfer.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_RX_DMA_EN_Msk )
+
+/**
+ * @brief Trigger TX PDMA transfer.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_TX_DMA_EN_Msk )
+
+/**
+ * @brief Enable 2-bit transfer mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOB_Msk )
+
+/**
+ * @brief Disable 2-bit transfer mode.
+ * @param[in] spi is the base address of SPI module.
+ * @return none
+ * \hideinitializer
+ */
+#define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOB_Msk )
+
+/**
+ * @brief Get the status register value.
+ * @param[in] spi is the base address of SPI module.
+ * @return status value.
+ * \hideinitializer
+ */
+#define SPI_GET_STATUS(spi) ( (spi)->STATUS )
+
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void SPI_Close(SPI_T *spi);
+void SPI_ClearRxFIFO(SPI_T *spi);
+void SPI_ClearTxFIFO(SPI_T *spi);
+void SPI_DisableAutoSS(SPI_T *spi);
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
+void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+void SPI_DisableFIFO(SPI_T *spi);
+uint32_t SPI_GetBusClock(SPI_T *spi);
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_EnableWakeup(SPI_T *spi);
+void SPI_DisableWakeup(SPI_T *spi);
+/*@}*/ /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SPI_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SPI_H__
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_sys.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,198 @@
+/**************************************************************************//**
+ * @file sys.c
+ * @version V1.00
+ * $Revision: 8 $
+ * $Date: 15/06/17 4:49p $
+ * @brief NANO100 series SYS driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "Nano100Series.h"
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SYS_Driver SYS Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function clear the selected system reset source
+ * @param[in] u32Src is system reset source
+ * @return None
+ */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+ SYS->RST_SRC |= u32Src;
+}
+
+/**
+ * @brief This function get Brown-out detector output status
+ * @param None
+ * @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0.
+ * 1: System voltage is lower than BOD_VL setting.
+ * Note : If the BOD_EN is 0, this function always return 0.
+ */
+uint32_t SYS_GetBODStatus()
+{
+ return (SYS->BODSTS);
+}
+
+/**
+ * @brief This function get the system reset source register value
+ * @param None
+ * @return Reset source
+ */
+uint32_t SYS_GetResetSrc(void)
+{
+ return (SYS->RST_SRC);
+}
+
+/**
+ * @brief This function check register write-protection bit setting
+ * @param None
+ * @return 0: Write-protection function is disabled.
+ * 1: Write-protection function is enabled.
+ */
+uint32_t SYS_IsRegLocked(void)
+{
+ return !(SYS->RegLockAddr & SYS_RegLockAddr_RegUnLock_Msk);
+}
+
+/**
+ * @brief This function get product ID.
+ * @param None
+ * @return Product ID
+ */
+uint32_t SYS_ReadPDID(void)
+{
+ return SYS->PDID;
+}
+
+/**
+ * @brief This function reset chip.
+ * @param None
+ * @return None
+ */
+void SYS_ResetChip(void)
+{
+ SYS->IPRST_CTL1 |= SYS_IPRST_CTL1_CHIP_RST_Msk;
+}
+
+/**
+ * @brief This function reset CPU.
+ * @param None
+ * @return None
+ */
+void SYS_ResetCPU(void)
+{
+ SYS->IPRST_CTL1 |= SYS_IPRST_CTL1_CPU_RST_Msk;
+}
+
+/**
+ * @brief This function reset selected modules.
+ * @param[in] u32ModuleIndex is module index. Including :
+ * - \ref CHIP_RST
+ * - \ref CPU_RST
+ * - \ref DMA_RST
+ * - \ref EBI_RST
+ * - \ref SC1_RST
+ * - \ref SC0_RST
+ * - \ref I2S_RST
+ * - \ref ADC_RST
+ * - \ref USBD_RST
+ * - \ref DAC_RST
+ * - \ref PWM1_RST
+ * - \ref PWM0_RST
+ * - \ref UART1_RST
+ * - \ref UART0_RST
+ * - \ref SPI2_RST
+ * - \ref SPI1_RST
+ * - \ref SPI0_RST
+ * - \ref I2C1_RST
+ * - \ref I2C0_RST
+ * - \ref TMR3_RST
+ * - \ref TMR2_RST
+ * - \ref TMR1_RST
+ * - \ref TMR0_RST
+ * - \ref GPIO_RST
+ * @return None
+ */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+ *(volatile uint32_t *)((uint32_t)&(SYS->IPRST_CTL1) + (u32ModuleIndex>>24)) |= 1<<(u32ModuleIndex & 0x00ffffff);
+ *(volatile uint32_t *)((uint32_t)&(SYS->IPRST_CTL1) + (u32ModuleIndex>>24)) &= ~(1<<(u32ModuleIndex & 0x00ffffff));
+}
+
+/**
+ * @brief This function configure BOD function.
+ * Configure BOD reset or interrupt mode and set Brown-out voltage level.
+ * Enable Brown-out function
+ * @param[in] i32Mode is reset or interrupt mode. Including :
+ * - \ref SYS_BODCTL_BOD25_RST_EN_Msk or \ref SYS_BODCTL_BOD25_INT_EN_Msk
+ * - \ref SYS_BODCTL_BOD20_RST_EN_Msk or \ref SYS_BODCTL_BOD20_INT_EN_Msk
+ * - \ref SYS_BODCTL_BOD17_RST_EN_Msk or \ref SYS_BODCTL_BOD17_INT_EN_Msk
+ * @param[in] u32BODLevel is Brown-out voltage level. Including :
+ * - \ref SYS_BODCTL_BOD25_EN_Msk
+ * - \ref SYS_BODCTL_BOD20_EN_Msk
+ * - \ref SYS_BODCTL_BOD17_EN_Msk
+ *
+ * @return None
+ */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+ SYS->BODCTL = (SYS->BODCTL & ~0xFFF) | (i32Mode | u32BODLevel);
+}
+
+/**
+ * @brief This function disable BOD function.
+ * @param None
+ * @return None
+ */
+void SYS_DisableBOD(void)
+{
+ SYS->BODCTL = SYS->BODCTL & ~(SYS_BODCTL_BOD25_EN_Msk | SYS_BODCTL_BOD20_EN_Msk | SYS_BODCTL_BOD17_EN_Msk);
+}
+
+/**
+ * @brief This function enable HIRC trim function.
+ * @param[in] u32TrimSel is trim frequency selection. Including :
+ * - \ref SYS_IRCTRIMCTL_TRIM_11_0592M
+ * - \ref SYS_IRCTRIMCTL_TRIM_12M
+ * - \ref SYS_IRCTRIMCTL_TRIM_12_288M
+ * @param[in] u32TrimEnInt is HIRC trim interrupt selection. Including :
+ * - \ref SYS_IRCTRIMIEN_FAIL_EN
+ * - \ref SYS_IRCTRIMIEN_32KERR_EN
+ * - \ref SYS_IRCTRIMIEN_DISABLE
+ * @return None
+ */
+void SYS_EnableIRCTrim(uint32_t u32TrimSel,uint32_t u32TrimEnInt)
+{
+ SYS->IRCTRIMIEN = (SYS->IRCTRIMIEN & ~(SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk|SYS_IRCTRIMIEN_32K_ERR_IEN_Msk)) | u32TrimEnInt;
+ SYS->IRCTRIMCTL = (SYS->IRCTRIMCTL & ~SYS_IRCTRIMCTL_TRIM_SEL_Msk)|u32TrimSel;
+}
+
+/**
+ * @brief This function disable HIRC trim function.
+ * @param None
+ * @return None
+ */
+void SYS_DisableIRCTrim(void)
+{
+ SYS->IRCTRIMCTL = 0;
+}
+
+/*@}*/ /* end of group NANO100_SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SYS_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_sys.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,872 @@
+/**************************************************************************//**
+* @file sys.h
+* @version V1.00
+* $Revision: 17 $
+* $Date: 15/06/24 1:11p $
+* @brief Nano100 Series system control header file.
+*
+* @note
+* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __SYS_H__
+#define __SYS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SYS_Driver SYS Driver
+ @{
+*/
+
+/** @addtogroup NANO100_SYS_EXPORTED_CONSTANTS SYS Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Module Reset Control Resister constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CHIP_RST ((0x0<<24) | SYS_IPRST_CTL1_CPU_RST_Pos ) /*!< CPU reset is one of the SYS_ResetModule parameter */
+#define CPU_RST ((0x0<<24) | SYS_IPRST_CTL1_CHIP_RST_Pos ) /*!< CHIP reset is one of the SYS_ResetModule parameter */
+#define DMA_RST ((0x0<<24) | SYS_IPRST_CTL1_DMA_RST_Pos ) /*!< DMA reset is one of the SYS_ResetModule parameter */
+#define EBI_RST ((0x0<<24) | SYS_IPRST_CTL1_EBI_RST_Pos ) /*!< EBI reset is one of the SYS_ResetModule parameter */
+#define SC1_RST ((0x4<<24) | SYS_IPRST_CTL2_SC1_RST_Pos ) /*!< SmartCard1 reset is one of the SYS_ResetModule parameter */
+#define SC0_RST ((0x4<<24) | SYS_IPRST_CTL2_SC0_RST_Pos ) /*!< SmartCard0 reset is one of the SYS_ResetModule parameter */
+#define I2S_RST ((0x4<<24) | SYS_IPRST_CTL2_I2S_RST_Pos ) /*!< I2S reset is one of the SYS_ResetModule parameter */
+#define ADC_RST ((0x4<<24) | SYS_IPRST_CTL2_ADC_RST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */
+#define USBD_RST ((0x4<<24) | SYS_IPRST_CTL2_USBD_RST_Pos ) /*!< USBD reset is one of the SYS_ResetModule parameter */
+#define DAC_RST ((0x4<<24) | SYS_IPRST_CTL2_DAC_RST_Pos ) /*!< DAC reset is one of the SYS_ResetModule parameter */
+#define PWM1_RST ((0x4<<24) | SYS_IPRST_CTL2_PWM1_RST_Pos ) /*!< PWM1 reset is one of the SYS_ResetModule parameter */
+#define PWM0_RST ((0x4<<24) | SYS_IPRST_CTL2_PWM0_RST_Pos ) /*!< PWM0 reset is one of the SYS_ResetModule parameter */
+#define UART1_RST ((0x4<<24) | SYS_IPRST_CTL2_UART1_RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */
+#define UART0_RST ((0x4<<24) | SYS_IPRST_CTL2_UART0_RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */
+#define SPI2_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI2_RST_Pos ) /*!< SPI2 reset is one of the SYS_ResetModule parameter */
+#define SPI1_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI1_RST_Pos ) /*!< SPI1 reset is one of the SYS_ResetModule parameter */
+#define SPI0_RST ((0x4<<24) | SYS_IPRST_CTL2_SPI0_RST_Pos ) /*!< SPI0 reset is one of the SYS_ResetModule parameter */
+#define I2C1_RST ((0x4<<24) | SYS_IPRST_CTL2_I2C1_RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */
+#define I2C0_RST ((0x4<<24) | SYS_IPRST_CTL2_I2C0_RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */
+#define TMR3_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR3_RST_Pos ) /*!< Timer3 reset is one of the SYS_ResetModule parameter */
+#define TMR2_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR2_RST_Pos ) /*!< Timer2 reset is one of the SYS_ResetModule parameter */
+#define TMR1_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR1_RST_Pos ) /*!< Timer1 reset is one of the SYS_ResetModule parameter */
+#define TMR0_RST ((0x4<<24) | SYS_IPRST_CTL2_TMR0_RST_Pos ) /*!< Timer0 reset is one of the SYS_ResetModule parameter */
+#define GPIO_RST ((0x4<<24) | SYS_IPRST_CTL2_GPIO_RST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Multi-Function constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/********************* Bit definition of VREFCTL register **********************/
+#define SYS_VREFCTL_BGP_EN SYS_VREFCTL_BGP_EN_Msk /*!<Band-gap Enable */
+#define SYS_VREFCTL_REG_EN SYS_VREFCTL_REG_EN_Msk /*!<Regulator Enable */
+#define SYS_VREFCTL_SEL25 SYS_VREFCTL_SEL25_Msk /*!<Regulator Output Voltage 2.5V */
+#define SYS_VREFCTL_EXTMODE SYS_VREFCTL_EXT_MODE_Msk /*!<Regulator External Mode */
+
+/********************* Bit definition of IRCTRIMCTL register **********************/
+#define SYS_IRCTRIMCTL_TRIM_11_0592M (0x1UL<<SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!<Trim HIRC to 11.0592 MHz */
+#define SYS_IRCTRIMCTL_TRIM_12M (0x2UL<<SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!<Trim HIRC to 12 MHz */
+#define SYS_IRCTRIMCTL_TRIM_12_288M (0x3UL<<SYS_IRCTRIMCTL_TRIM_SEL_Pos) /*!<Trim HIRC to 12.288 MHz */
+
+#define SYS_IRCTRIMCTL_LOOP_4CLK (0x0UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 4 x 32.768 kHz clock */
+#define SYS_IRCTRIMCTL_LOOP_8CLK (0x1UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 8 x 32.768 kHz clock */
+#define SYS_IRCTRIMCTL_LOOP_16CLK (0x2UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 16 x 32.768 kHz clock */
+#define SYS_IRCTRIMCTL_LOOP_32CLK (0x3UL<<SYS_IRCTRIMCTL_TRIM_LOOP_Pos) /*!<Based on average difference in 32 x 32.768 kHz clock */
+
+#define SYS_IRCTRIMCTL_RETRY_64 (0x0UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 64 */
+#define SYS_IRCTRIMCTL_RETRY_128 (0x1UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 128 */
+#define SYS_IRCTRIMCTL_RETRY_256 (0x2UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 256 */
+#define SYS_IRCTRIMCTL_RETRY_512 (0x3UL<<SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) /*!<Trim retry count limitation is 512 */
+
+/********************* Bit definition of IRCTRIMIEN register **********************/
+#define SYS_IRCTRIMIEN_DISABLE ((uint32_t)0x00000000) /*!<Trim failure interrupt disable */
+#define SYS_IRCTRIMIEN_FAIL_EN SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk /*!<Trim failure interrupt enable */
+#define SYS_IRCTRIMIEN_32KERR_EN SYS_IRCTRIMIEN_32K_ERR_IEN_Msk /*!<32.768 kHz Clock Error Interrupt Enable */
+
+/********************* Bit definition of IRCTRIMINT register **********************/
+#define SYS_IRCTRIMINT_FREQLOCK SYS_IRCTRIMINT_FREQ_LOCK_Msk /*!<HIRC frequency lock status */
+#define SYS_IRCTRIMINT_FAIL_INT SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk /*!<Trim failure interrupt status */
+#define SYS_IRCTRIMINT_32KERR_INT SYS_IRCTRIMINT_32K_ERR_INT_Msk /*!<32.768 kHz Clock Error Interrupt Status */
+
+/********************* Bit definition of PA_L_MFP register **********************/
+
+#define SYS_PA_L_MFP_PA7_MFP_GPA7 (0UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - GPIOA[7] */
+#define SYS_PA_L_MFP_PA7_MFP_ADC_CH7 (1UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - ADC input channel 7 */
+#define SYS_PA_L_MFP_PA7_MFP_EBI_AD6 (2UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - EBI AD[6] */
+#define SYS_PA_L_MFP_PA7_MFP_TMR2_CAP (3UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - Timer 2 capture event */
+#define SYS_PA_L_MFP_PA7_MFP_SC2_DAT (4UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - SmartCard 2 data pin */
+#define SYS_PA_L_MFP_PA7_MFP_PWM0_CH2 (5UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - PWM0 Channel 2 */
+#define SYS_PA_L_MFP_PA7_MFP_LCD_S36 (7UL<<SYS_PA_L_MFP_PA7_MFP_Pos) /*!<PA7 Pin Function - LCD SEG 36 */
+
+#define SYS_PA_L_MFP_PA6_MFP_GPA6 (0UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - GPIOA[6] */
+#define SYS_PA_L_MFP_PA6_MFP_ADC_CH6 (1UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - ADC input channel 6 */
+#define SYS_PA_L_MFP_PA6_MFP_EBI_AD7 (2UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - EBI AD[7] */
+#define SYS_PA_L_MFP_PA6_MFP_TMR3_CAP (3UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - Timer 3 Capture event */
+#define SYS_PA_L_MFP_PA6_MFP_SC2_CLK (4UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - SmartCard 2 clock */
+#define SYS_PA_L_MFP_PA6_MFP_PWM0_CH3 (5UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - PWM0 Channel 3 */
+#define SYS_PA_L_MFP_PA6_MFP_LCD_S37 (7UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - LCD SEG 37 */
+#define SYS_PA_L_MFP_PA6_MFP_LCD_S19 (7UL<<SYS_PA_L_MFP_PA6_MFP_Pos) /*!<PA6 Pin Function - LCD SEG 19 */
+
+#define SYS_PA_L_MFP_PA5_MFP_GPA5 (0UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - GPIOA[5] */
+#define SYS_PA_L_MFP_PA5_MFP_ADC_CH5 (1UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - ADC input channel 5 */
+#define SYS_PA_L_MFP_PA5_MFP_EBI_AD8 (2UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - EBI AD[8] */
+#define SYS_PA_L_MFP_PA5_MFP_SC2_RST (4UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - SmartCard2 RST */
+#define SYS_PA_L_MFP_PA5_MFP_I2C0_SCL (5UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - I2C0 clock */
+#define SYS_PA_L_MFP_PA5_MFP_LCD_S38 (7UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - LCD SEG 38 */
+#define SYS_PA_L_MFP_PA5_MFP_LCD_S20 (7UL<<SYS_PA_L_MFP_PA5_MFP_Pos) /*!<PA5 Pin Function - LCD SEG 20 */
+
+#define SYS_PA_L_MFP_PA4_MFP_GPA4 (0UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - GPIOA[4] */
+#define SYS_PA_L_MFP_PA4_MFP_ADC_CH4 (1UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - ADC input channel 4 */
+#define SYS_PA_L_MFP_PA4_MFP_EBI_AD9 (2UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - EBI AD[9] */
+#define SYS_PA_L_MFP_PA4_MFP_SC2_PWR (4UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - SmartCard 2 power */
+#define SYS_PA_L_MFP_PA4_MFP_I2C0_SDA (5UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - I2C0 DATA */
+#define SYS_PA_L_MFP_PA4_MFP_LCD_S39 (7UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - LCD SEG 39 */
+#define SYS_PA_L_MFP_PA4_MFP_LCD_S21 (7UL<<SYS_PA_L_MFP_PA4_MFP_Pos) /*!<PA4 Pin Function - LCD SEG 21 */
+
+#define SYS_PA_L_MFP_PA3_MFP_GPA3 (0UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - GPIOA[3] */
+#define SYS_PA_L_MFP_PA3_MFP_ADC_CH3 (1UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - ADC input channel 3 */
+#define SYS_PA_L_MFP_PA3_MFP_EBI_AD10 (2UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - EBI AD[10] */
+#define SYS_PA_L_MFP_PA3_MFP_UART1_TX (5UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - UART 1 RX */
+#define SYS_PA_L_MFP_PA3_MFP_LCD_S22 (7UL<<SYS_PA_L_MFP_PA3_MFP_Pos) /*!<PA3 Pin Function - LCD SEG 22 */
+
+#define SYS_PA_L_MFP_PA2_MFP_GPA2 (0UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - GPIOA[2] */
+#define SYS_PA_L_MFP_PA2_MFP_ADC_CH2 (1UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - ADC input channel 2 */
+#define SYS_PA_L_MFP_PA2_MFP_EBI_AD11 (2UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - EBI AD[11] */
+#define SYS_PA_L_MFP_PA2_MFP_UART1_RX (5UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - UART1 TX */
+#define SYS_PA_L_MFP_PA2_MFP_LCD_S23 (7UL<<SYS_PA_L_MFP_PA2_MFP_Pos) /*!<PA2 Pin Function - LCD SEG 23 */
+
+#define SYS_PA_L_MFP_PA1_MFP_GPA1 (0UL<<SYS_PA_L_MFP_PA1_MFP_Pos) /*!<PA1 Pin Function - GPIOA[1] */
+#define SYS_PA_L_MFP_PA1_MFP_ADC_CH1 (1UL<<SYS_PA_L_MFP_PA1_MFP_Pos) /*!<PA1 Pin Function - ADC input channel 1 */
+#define SYS_PA_L_MFP_PA1_MFP_EBI_AD12 (2UL<<SYS_PA_L_MFP_PA1_MFP_Pos) /*!<PA1 Pin Function - EBI AD[12] */
+
+#define SYS_PA_L_MFP_PA0_MFP_GPA0 (0UL<<SYS_PA_L_MFP_PA0_MFP_Pos) /*!<PA0 Pin Function - GPIOA[0] */
+#define SYS_PA_L_MFP_PA0_MFP_ADC_CH0 (1UL<<SYS_PA_L_MFP_PA0_MFP_Pos) /*!<PA0 Pin Function - ADC input channel 0 */
+#define SYS_PA_L_MFP_PA0_MFP_SC2_CD (4UL<<SYS_PA_L_MFP_PA0_MFP_Pos) /*!<PA0 Pin Function - SmartCard 2 card detect */
+
+/********************* Bit definition of PA_H_MFP register **********************/
+#define SYS_PA_H_MFP_PA15_MFP_GPA15 (0UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - GPIOA[15] */
+#define SYS_PA_H_MFP_PA15_MFP_PWM0_CH3 (1UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - PWM0 Channel 3 */
+#define SYS_PA_H_MFP_PA15_MFP_I2S_MCLK (2UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - I2S MCLK */
+#define SYS_PA_H_MFP_PA15_MFP_TMR3_CAP (3UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - Timer3 capture event */
+#define SYS_PA_H_MFP_PA15_MFP_SC0_PWR (4UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - SmartCard 0 power */
+#define SYS_PA_H_MFP_PA15_MFP_UART0_TX (6UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - UART0 TX */
+#define SYS_PA_H_MFP_PA15_MFP_LCD_S27 (7UL<<SYS_PA_H_MFP_PA15_MFP_Pos) /*!<PA15 Pin Function - LCD SEG 27 */
+
+#define SYS_PA_H_MFP_PA14_MFP_GPA14 (0UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - GPIOA[14] */
+#define SYS_PA_H_MFP_PA14_MFP_PWM0_CH2 (1UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - PWM0 Channel 2 */
+#define SYS_PA_H_MFP_PA14_MFP_EBI_AD15 (2UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - EBI AD[15] */
+#define SYS_PA_H_MFP_PA14_MFP_TMR2_CAP (3UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - Timer2 capture event */
+#define SYS_PA_H_MFP_PA14_MFP_UART0_RX (6UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - UART0 RX */
+#define SYS_PA_H_MFP_PA14_MFP_LCD_S26 (7UL<<SYS_PA_H_MFP_PA14_MFP_Pos) /*!<PA14 Pin Function - LCD SEG 26 */
+
+#define SYS_PA_H_MFP_PA13_MFP_GPA13 (0UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - GPIOA[13] */
+#define SYS_PA_H_MFP_PA13_MFP_PWM0_CH1 (1UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - PWM0 Channel 1 */
+#define SYS_PA_H_MFP_PA13_MFP_EBI_AD14 (2UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - EBI AD[14] */
+#define SYS_PA_H_MFP_PA13_MFP_TMR1_CAP (3UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - Timer1 capture event */
+#define SYS_PA_H_MFP_PA13_MFP_I2C0_SCL (5UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - I2C0 clock */
+#define SYS_PA_H_MFP_PA13_MFP_LCD_S25 (7UL<<SYS_PA_H_MFP_PA13_MFP_Pos) /*!<PA13 Pin Function - LCD SEG 25 */
+
+#define SYS_PA_H_MFP_PA12_MFP_GPA12 (0UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - GPIOA[12] */
+#define SYS_PA_H_MFP_PA12_MFP_PWM0_CH0 (1UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - PWM0 Channel 0 */
+#define SYS_PA_H_MFP_PA12_MFP_EBI_AD13 (2UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - EBI AD[13] */
+#define SYS_PA_H_MFP_PA12_MFP_TMR0_CAP (3UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - Timer0 capture event */
+#define SYS_PA_H_MFP_PA12_MFP_I2C0_SDA (5UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - I2C0 DATA */
+#define SYS_PA_H_MFP_PA12_MFP_LCD_S24 (7UL<<SYS_PA_H_MFP_PA12_MFP_Pos) /*!<PA12 Pin Function - LCD SEG 24 */
+
+#define SYS_PA_H_MFP_PA11_MFP_GPA11 (0UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - GPIOA[11] */
+#define SYS_PA_H_MFP_PA11_MFP_I2C1_SCL (1UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - I2C1 clock */
+#define SYS_PA_H_MFP_PA11_MFP_EBI_NRE (2UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - EBI nRE */
+#define SYS_PA_H_MFP_PA11_MFP_SC0_RST (3UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - SmartCard0 RST */
+#define SYS_PA_H_MFP_PA11_MFP_SPI2_MOSI0 (4UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - SPI2 MOSI[0] */
+#define SYS_PA_H_MFP_PA11_MFP_LCD_S23 (7UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - LCD SEG 23 */
+#define SYS_PA_H_MFP_PA11_MFP_LCD_S9 (7UL<<SYS_PA_H_MFP_PA11_MFP_Pos) /*!<PA11 Pin Function - LCD SEG 9 */
+
+#define SYS_PA_H_MFP_PA10_MFP_GPA10 (0UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - GPIOA[10] */
+#define SYS_PA_H_MFP_PA10_MFP_I2C1_SDA (1UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - I2C1 DATA */
+#define SYS_PA_H_MFP_PA10_MFP_EBI_NWE (2UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - EBI nWE */
+#define SYS_PA_H_MFP_PA10_MFP_SC0_PWR (3UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - SmartCard0 Power */
+#define SYS_PA_H_MFP_PA10_MFP_SPI2_MISO0 (4UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - SPI2 MISO[0] */
+#define SYS_PA_H_MFP_PA10_MFP_LCD_S22 (7UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - LCD SEG 22 */
+#define SYS_PA_H_MFP_PA10_MFP_LCD_S8 (7UL<<SYS_PA_H_MFP_PA10_MFP_Pos) /*!<PA10 Pin Function - LCD SEG 8 */
+
+#define SYS_PA_H_MFP_PA9_MFP_GPA9 (0UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - GPIOA[9] */
+#define SYS_PA_H_MFP_PA9_MFP_I2C0_SCL (1UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - I2C0 clock */
+#define SYS_PA_H_MFP_PA9_MFP_SC0_DAT (3UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - SmartCard0 DATA */
+#define SYS_PA_H_MFP_PA9_MFP_SPI2_SCLK (4UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - SPI2 SCLK */
+#define SYS_PA_H_MFP_PA9_MFP_LCD_S21 (7UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - LCD SEG 21 */
+#define SYS_PA_H_MFP_PA9_MFP_LCD_S7 (7UL<<SYS_PA_H_MFP_PA9_MFP_Pos) /*!<PA9 Pin Function - LCD SEG 7 */
+
+#define SYS_PA_H_MFP_PA8_MFP_GPA8 (0UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - GPIOA[8] */
+#define SYS_PA_H_MFP_PA8_MFP_I2C0_SDA (1UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - I2C0 DATA */
+#define SYS_PA_H_MFP_PA8_MFP_SC0_CLK (3UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - SmartCard0 clock */
+#define SYS_PA_H_MFP_PA8_MFP_SPI2_SS0 (4UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - SPI2 1st chip selection */
+#define SYS_PA_H_MFP_PA8_MFP_LCD_S20 (7UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - LCD SEG 20 */
+#define SYS_PA_H_MFP_PA8_MFP_LCD_S6 (7UL<<SYS_PA_H_MFP_PA8_MFP_Pos) /*!<PA8 Pin Function - LCD SEG 6 */
+
+/********************* Bit definition of PB_L_MFP register **********************/
+#define SYS_PB_L_MFP_PB7_MFP_GPB7 (0UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - GPIOB[7] */
+#define SYS_PB_L_MFP_PB7_MFP_UART1_CTS (1UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - UART1 CTSn */
+#define SYS_PB_L_MFP_PB7_MFP_EBI_NCS (2UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - EBI nCS */
+#define SYS_PB_L_MFP_PB7_MFP_SPI2_MOSI0 (4UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - SPI2 MOSI[0] */
+#define SYS_PB_L_MFP_PB7_MFP_LCD_S10 (7UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - LCD SEG 10 */
+#define SYS_PB_L_MFP_PB7_MFP_LCD_S2 (7UL<<SYS_PB_L_MFP_PB7_MFP_Pos) /*!<PB7 Pin Function - LCD SEG 2 */
+
+#define SYS_PB_L_MFP_PB6_MFP_GPB6 (0UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - GPIOB[6] */
+#define SYS_PB_L_MFP_PB6_MFP_UART1_RTS (1UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - UART1 RTSn */
+#define SYS_PB_L_MFP_PB6_MFP_EBI_ALE (2UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - EBI ALE */
+#define SYS_PB_L_MFP_PB6_MFP_SPI2_MISO0 (4UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - SPI2 MISO[0] */
+#define SYS_PB_L_MFP_PB6_MFP_LCD_S11 (7UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - LCD SEG 11 */
+#define SYS_PB_L_MFP_PB6_MFP_LCD_S3 (7UL<<SYS_PB_L_MFP_PB6_MFP_Pos) /*!<PB6 Pin Function - LCD SEG 3 */
+
+#define SYS_PB_L_MFP_PB5_MFP_GPB5 (0UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - GPIOB[5] */
+#define SYS_PB_L_MFP_PB5_MFP_UART1_TX (1UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - UART1 TX */
+#define SYS_PB_L_MFP_PB5_MFP_SC0_RST (3UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - SmartCard0 RST */
+#define SYS_PB_L_MFP_PB5_MFP_SPI2_SCLK (4UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - SPI2 SCLK */
+#define SYS_PB_L_MFP_PB5_MFP_LCD_S12 (7UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - LCD SEG 12 */
+#define SYS_PB_L_MFP_PB5_MFP_LCD_S4 (7UL<<SYS_PB_L_MFP_PB5_MFP_Pos) /*!<PB5 Pin Function - LCD SEG 4 */
+
+#define SYS_PB_L_MFP_PB4_MFP_GPB4 (0UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - GPIOB[4] */
+#define SYS_PB_L_MFP_PB4_MFP_UART1_RX (1UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - UART1 RX */
+#define SYS_PB_L_MFP_PB4_MFP_SC0_CD (3UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - SmartCard0 card detection */
+#define SYS_PB_L_MFP_PB4_MFP_SPI2_SS0 (4UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - SPI2 chip selection 0 */
+#define SYS_PB_L_MFP_PB4_MFP_LCD_S13 (7UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - LCD SEG 13 */
+#define SYS_PB_L_MFP_PB4_MFP_LCD_S5 (7UL<<SYS_PB_L_MFP_PB4_MFP_Pos) /*!<PB4 Pin Function - LCD SEG 5 */
+
+#define SYS_PB_L_MFP_PB3_MFP_GPB3 (0UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - GPIOB[3] */
+#define SYS_PB_L_MFP_PB3_MFP_UART0_CTS (1UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - UART0 CTSn */
+#define SYS_PB_L_MFP_PB3_MFP_EBI_NWRH (2UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - EBI nWRH */
+#define SYS_PB_L_MFP_PB3_MFP_SPI1_SS0 (3UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - SPI1 chip selection 0 */
+#define SYS_PB_L_MFP_PB3_MFP_LCD_S4 (7UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - LCD SEG 4 */
+#define SYS_PB_L_MFP_PB3_MFP_LCD_COM2 (7UL<<SYS_PB_L_MFP_PB3_MFP_Pos) /*!<PB3 Pin Function - LCD COM 2 */
+
+#define SYS_PB_L_MFP_PB2_MFP_GPB2 (0UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - GPIOB[2] */
+#define SYS_PB_L_MFP_PB2_MFP_UART0_RTS (1UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - UART0 RTSn */
+#define SYS_PB_L_MFP_PB2_MFP_EBI_NWRL (2UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - EBI nWRL */
+#define SYS_PB_L_MFP_PB2_MFP_SPI1_SCLK (3UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - SPI1 SCLK */
+#define SYS_PB_L_MFP_PB2_MFP_LCD_S5 (7UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - LCD SEG 5 */
+#define SYS_PB_L_MFP_PB2_MFP_LCD_COM3 (7UL<<SYS_PB_L_MFP_PB2_MFP_Pos) /*!<PB2 Pin Function - LCD COM 3 */
+
+#define SYS_PB_L_MFP_PB1_MFP_GPB1 (0UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - GPIOB[1] */
+#define SYS_PB_L_MFP_PB1_MFP_UART0_TX (1UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - UART0 TX */
+#define SYS_PB_L_MFP_PB1_MFP_SPI1_MISO0 (3UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - SPI1 MISO[0] */
+#define SYS_PB_L_MFP_PB1_MFP_LCD_S6 (7UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - LCD SEG 6 */
+#define SYS_PB_L_MFP_PB1_MFP_LCD_S0 (7UL<<SYS_PB_L_MFP_PB1_MFP_Pos) /*!<PB1 Pin Function - LCD SEG 0 */
+
+#define SYS_PB_L_MFP_PB0_MFP_GPB0 (0UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - GPIOB[0] */
+#define SYS_PB_L_MFP_PB0_MFP_UART0_RX (1UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - UART0 RX */
+#define SYS_PB_L_MFP_PB0_MFP_SPI1_MOSI0 (3UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - SPI1 MOSI[0] */
+#define SYS_PB_L_MFP_PB0_MFP_LCD_S7 (7UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - LCD SEG 7 */
+#define SYS_PB_L_MFP_PB0_MFP_LCD_S1 (7UL<<SYS_PB_L_MFP_PB0_MFP_Pos) /*!<PB0 Pin Function - LCD SEG 1 */
+
+/********************* Bit definition of PB_H_MFP register **********************/
+#define SYS_PB_H_MFP_PB15_MFP_GPB15 (0UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - GPIOB[15] */
+#define SYS_PB_H_MFP_PB15_MFP_EXT_INT1 (1UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - External interrupt 1 */
+#define SYS_PB_H_MFP_PB15_MFP_SNOOPER (3UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - Snooper pin */
+#define SYS_PB_H_MFP_PB15_MFP_SC1_CD (4UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - SmartCard1 card detect */
+#define SYS_PB_H_MFP_PB15_MFP_LCD_S31 (7UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - LCD SEG 31 */
+#define SYS_PB_H_MFP_PB15_MFP_LCD_S14 (7UL<<SYS_PB_H_MFP_PB15_MFP_Pos) /*!<PB15 Pin Function - LCD SEG 14 */
+
+#define SYS_PB_H_MFP_PB14_MFP_GPB14 (0UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - GPIOB[14] */
+#define SYS_PB_H_MFP_PB14_MFP_EXT_INT0 (1UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - External interrupt 0 */
+#define SYS_PB_H_MFP_PB14_MFP_SC2_CD (3UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - SmartCard 2 card detect */
+#define SYS_PB_H_MFP_PB14_MFP_SPI2_SS1 (4UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - SPI2 2nd chip selection */
+#define SYS_PB_H_MFP_PB14_MFP_LCD_S26 (7UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - LCD SEG 26 */
+#define SYS_PB_H_MFP_PB14_MFP_LCD_S12 (7UL<<SYS_PB_H_MFP_PB14_MFP_Pos) /*!<PB14 Pin Function - LCD SEG 12 */
+
+#define SYS_PB_H_MFP_PB13_MFP_GPB13 (0UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - GPIOB[13] */
+#define SYS_PB_H_MFP_PB13_MFP_EBI_AD1 (2UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - EBI AD[1] */
+#define SYS_PB_H_MFP_PB13_MFP_LCD_S25 (7UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - LCD SEG 25 */
+#define SYS_PB_H_MFP_PB13_MFP_LCD_S11 (7UL<<SYS_PB_H_MFP_PB13_MFP_Pos) /*!<PB13 Pin Function - LCD SEG 11 */
+
+#define SYS_PB_H_MFP_PB12_MFP_GPB12 (0UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - GPIOB[12] */
+#define SYS_PB_H_MFP_PB12_MFP_EBI_AD0 (2UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - EBI AD[0] */
+#define SYS_PB_H_MFP_PB12_MFP_CKO (4UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - CKO */
+#define SYS_PB_H_MFP_PB12_MFP_LCD_S24 (7UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - LCD SEG 24 */
+#define SYS_PB_H_MFP_PB12_MFP_LCD_S10 (7UL<<SYS_PB_H_MFP_PB12_MFP_Pos) /*!<PB12 Pin Function - LCD SEG 10 */
+
+#define SYS_PB_H_MFP_PB11_MFP_GPB11 (0UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - GPIOB[11] */
+#define SYS_PB_H_MFP_PB11_MFP_PWM1_CH0 (1UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - PWM1 Channel 0 */
+#define SYS_PB_H_MFP_PB11_MFP_TMR3_EXT (2UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - Timer3 external event input */
+#define SYS_PB_H_MFP_PB11_MFP_TMR3_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - Timer3 toggle output */
+#define SYS_PB_H_MFP_PB11_MFP_SC2_DAT (4UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - SmartCard2 DATA */
+#define SYS_PB_H_MFP_PB11_MFP_SPI0_MISO0 (5UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - SPI 0 MISO[0] */
+#define SYS_PB_H_MFP_PB11_MFP_LCD_V1 (7UL<<SYS_PB_H_MFP_PB11_MFP_Pos) /*!<PB11 Pin Function - LCD V1 */
+
+#define SYS_PB_H_MFP_PB10_MFP_GPB10 (0UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - GPIOB[10] */
+#define SYS_PB_H_MFP_PB10_MFP_SPI0_SS1 (1UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - SPI0 chip selection 1 */
+#define SYS_PB_H_MFP_PB10_MFP_TMR2_EXT (2UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - Timer2 external event input */
+#define SYS_PB_H_MFP_PB10_MFP_TMR2_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - Timer2 toggle output */
+#define SYS_PB_H_MFP_PB10_MFP_SC2_CLK (4UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - SmartCard2 clock */
+#define SYS_PB_H_MFP_PB10_MFP_SPI0_MOSI0 (5UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - SPI0 MOSI[0] */
+#define SYS_PB_H_MFP_PB10_MFP_LCD_V2 (7UL<<SYS_PB_H_MFP_PB10_MFP_Pos) /*!<PB10 Pin Function - LCD V2 */
+
+#define SYS_PB_H_MFP_PB9_MFP_GPB9 (0UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - GPIOB[9] */
+#define SYS_PB_H_MFP_PB9_MFP_SPI1_SS1 (1UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - SPI1 chip selection 1 */
+#define SYS_PB_H_MFP_PB9_MFP_TMR1_EXT (2UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - Timer1 external event input */
+#define SYS_PB_H_MFP_PB9_MFP_TMR1_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - Timer1 toggle output */
+#define SYS_PB_H_MFP_PB9_MFP_SC2_RST (4UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - SmartCard2 RST */
+#define SYS_PB_H_MFP_PB9_MFP_EXT_INT0 (5UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - External interrupt 0 */
+#define SYS_PB_H_MFP_PB9_MFP_LCD_V3 (7UL<<SYS_PB_H_MFP_PB9_MFP_Pos) /*!<PB9 Pin Function - LCD V3 */
+
+#define SYS_PB_H_MFP_PB8_MFP_GPB8 (0UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - GPIOB[8] */
+#define SYS_PB_H_MFP_PB8_MFP_ADC_EXT (1UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - ADC external trigger */
+#define SYS_PB_H_MFP_PB8_MFP_TMR0_EXT (2UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - Timer0 external event input */
+#define SYS_PB_H_MFP_PB8_MFP_TMR0_TOGGLE_OUT (2UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - Timer0 toggle output */
+#define SYS_PB_H_MFP_PB8_MFP_EXT_INT0 (3UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - External interrupt 0 */
+#define SYS_PB_H_MFP_PB8_MFP_SC2_PWR (4UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - SmartCard 2 power */
+#define SYS_PB_H_MFP_PB8_MFP_LCD_S30 (7UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - LCD SEG 30 */
+#define SYS_PB_H_MFP_PB8_MFP_LCD_S13 (7UL<<SYS_PB_H_MFP_PB8_MFP_Pos) /*!<PB8 Pin Function - LCD SEG 13 */
+
+/********************* Bit definition of PC_L_MFP register **********************/
+#define SYS_PC_L_MFP_PC7_MFP_GPC7 (0UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - GPIOC[7] */
+#define SYS_PC_L_MFP_PC7_MFP_DA_OUT1 (1UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - DA out1 */
+#define SYS_PC_L_MFP_PC7_MFP_EBI_AD5 (2UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - EBI AD[5] */
+#define SYS_PC_L_MFP_PC7_MFP_TMR1_CAP (3UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - Timer1 capture event */
+#define SYS_PC_L_MFP_PC7_MFP_PWM0_CH1 (5UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - PWM0 Channel 1 */
+#define SYS_PC_L_MFP_PC7_MFP_LCD_S17 (7UL<<SYS_PC_L_MFP_PC7_MFP_Pos) /*!<PC7 Pin Function - LCD SEG 17 */
+
+#define SYS_PC_L_MFP_PC6_MFP_GPC6 (0UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - GPIOC[6] */
+#define SYS_PC_L_MFP_PC6_MFP_DA_OUT0 (1UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - DA out0 */
+#define SYS_PC_L_MFP_PC6_MFP_EBI_AD4 (2UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - EBI AD[4] */
+#define SYS_PC_L_MFP_PC6_MFP_TMR0_CAP (3UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - Timer0 Capture event */
+#define SYS_PC_L_MFP_PC6_MFP_SC1_CD (4UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - SmartCard1 card detection */
+#define SYS_PC_L_MFP_PC6_MFP_PWM0_CH0 (5UL<<SYS_PC_L_MFP_PC6_MFP_Pos) /*!<PC6 Pin Function - PWM0 Channel 0 */
+
+#define SYS_PC_L_MFP_PC5_MFP_GPC5 (0UL<<SYS_PC_L_MFP_PC5_MFP_Pos) /*!<PC5 Pin Function - GPIOC[5] */
+#define SYS_PC_L_MFP_PC5_MFP_SPI0_MOSI1 (1UL<<SYS_PC_L_MFP_PC5_MFP_Pos) /*!<PC5 Pin Function - SPI0 MOSI[1] */
+#define SYS_PC_L_MFP_PC5_MFP_LCD_COM3 (7UL<<SYS_PC_L_MFP_PC5_MFP_Pos) /*!<PC5 Pin Function - LCD COM 3 */
+
+#define SYS_PC_L_MFP_PC4_MFP_GPC4 (0UL<<SYS_PC_L_MFP_PC4_MFP_Pos) /*!<PC4 Pin Function - GPIOC[4] */
+#define SYS_PC_L_MFP_PC4_MFP_SPI0_MISO1 (1UL<<SYS_PC_L_MFP_PC4_MFP_Pos) /*!<PC4 Pin Function - SPI0 MISO[1] */
+#define SYS_PC_L_MFP_PC4_MFP_LCD_COM2 (7UL<<SYS_PC_L_MFP_PC4_MFP_Pos) /*!<PC4 Pin Function - LCD COM 2 */
+
+#define SYS_PC_L_MFP_PC3_MFP_GPC3 (0UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - GPIOC[3] */
+#define SYS_PC_L_MFP_PC3_MFP_SPI0_MOSI0 (1UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - SPI0 MOSI[0] */
+#define SYS_PC_L_MFP_PC3_MFP_I2S_DOUT (2UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - I2S Dout */
+#define SYS_PC_L_MFP_PC3_MFP_SC1_RST (4UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - SmartCard1 RST */
+#define SYS_PC_L_MFP_PC3_MFP_LCD_COM1 (7UL<<SYS_PC_L_MFP_PC3_MFP_Pos) /*!<PC3 Pin Function - LCD COM 1 */
+
+#define SYS_PC_L_MFP_PC2_MFP_GPC2 (0UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - GPIOC[2] */
+#define SYS_PC_L_MFP_PC2_MFP_SPI0_MISO0 (1UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - SPI0 MISO[0] */
+#define SYS_PC_L_MFP_PC2_MFP_I2S_DIN (2UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - I2S Din */
+#define SYS_PC_L_MFP_PC2_MFP_SC1_PWR (4UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - SmartCard1 Power */
+#define SYS_PC_L_MFP_PC2_MFP_LCD_COM0 (7UL<<SYS_PC_L_MFP_PC2_MFP_Pos) /*!<PC2 Pin Function - LCD COM 0 */
+
+#define SYS_PC_L_MFP_PC1_MFP_GPC1 (0UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - GPIOC[1] */
+#define SYS_PC_L_MFP_PC1_MFP_SPI0_SCLK (1UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - SPI0 SCLK */
+#define SYS_PC_L_MFP_PC1_MFP_I2S_BCLK (2UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - I2S BCLK */
+#define SYS_PC_L_MFP_PC1_MFP_SC1_DAT (4UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - SmartCard1 DATA */
+#define SYS_PC_L_MFP_PC1_MFP_LCD_DH2 (7UL<<SYS_PC_L_MFP_PC1_MFP_Pos) /*!<PC1 Pin Function - LCD DH2 */
+
+#define SYS_PC_L_MFP_PC0_MFP_GPC0 (0UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - GPIOC[0] */
+#define SYS_PC_L_MFP_PC0_MFP_SPI0_SS0 (1UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - SPI0 chip selection 0 */
+#define SYS_PC_L_MFP_PC0_MFP_I2S_WS (2UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - I2S WS */
+#define SYS_PC_L_MFP_PC0_MFP_SC1_CLK (4UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - SmartCard1 clock */
+#define SYS_PC_L_MFP_PC0_MFP_LCD_DH1 (7UL<<SYS_PC_L_MFP_PC0_MFP_Pos) /*!<PC0 Pin Function - LCD DH1 */
+
+/********************* Bit definition of PC_H_MFP register **********************/
+#define SYS_PC_H_MFP_PC15_MFP_GPC15 (0UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - GPIOC[15] */
+#define SYS_PC_H_MFP_PC15_MFP_EBI_AD3 (2UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - EBI AD[3] */
+#define SYS_PC_H_MFP_PC15_MFP_TMR0_CAP (3UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - Timer0 capture event */
+#define SYS_PC_H_MFP_PC15_MFP_PWM1_CH2 (4UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - PWM1 Channel 2 */
+#define SYS_PC_H_MFP_PC15_MFP_LCD_S33 (7UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - LCD SEG 33 */
+#define SYS_PC_H_MFP_PC15_MFP_LCD_S16 (7UL<<SYS_PC_H_MFP_PC15_MFP_Pos) /*!<PC15 Pin Function - LCD SEG 16 */
+
+#define SYS_PC_H_MFP_PC14_MFP_GPC14 (0UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - GPIOC[14] */
+#define SYS_PC_H_MFP_PC14_MFP_EBI_AD2 (2UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - EBI AD[2] */
+#define SYS_PC_H_MFP_PC14_MFP_PWM1_CH3 (4UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - PWM1 Channel 3 */
+#define SYS_PC_H_MFP_PC14_MFP_LCD_S32 (7UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - LCD SEG 32 */
+#define SYS_PC_H_MFP_PC14_MFP_LCD_S15 (7UL<<SYS_PC_H_MFP_PC14_MFP_Pos) /*!<PC14 Pin Function - LCD SEG 15 */
+
+#define SYS_PC_H_MFP_PC13_MFP_GPC13 (0UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - GPIOC[13] */
+#define SYS_PC_H_MFP_PC13_MFP_SPI1_MOSI1 (1UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - SPI1 MOSI[1] */
+#define SYS_PC_H_MFP_PC13_MFP_PWM1_CH1 (2UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - PWM1 Channel 1 */
+#define SYS_PC_H_MFP_PC13_MFP_SNOOPER (4UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - Snooper pin */
+#define SYS_PC_H_MFP_PC13_MFP_EXT_INT1 (5UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - External interrupt 1 */
+#define SYS_PC_H_MFP_PC13_MFP_I2C0_SCL (6UL<<SYS_PC_H_MFP_PC13_MFP_Pos) /*!<PC13 Pin Function - I2C0 clock */
+
+#define SYS_PC_H_MFP_PC12_MFP_GPC12 (0UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - GPIOC[12] */
+#define SYS_PC_H_MFP_PC12_MFP_SPI1_MISO1 (1UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - SPI1 MISO[1] */
+#define SYS_PC_H_MFP_PC12_MFP_PWM1_CH0 (2UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - PWM1 Channel 0 */
+#define SYS_PC_H_MFP_PC12_MFP_EXT_INT0 (5UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - External interrupt 0 */
+#define SYS_PC_H_MFP_PC12_MFP_I2C0_SDA (6UL<<SYS_PC_H_MFP_PC12_MFP_Pos) /*!<PC12 Pin Function - I2C0 DATA */
+
+#define SYS_PC_H_MFP_PC11_MFP_GPC11 (0UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - GPIOC[11] */
+#define SYS_PC_H_MFP_PC11_MFP_SPI1_MOSI0 (1UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - SPI1 MOSI[0] */
+#define SYS_PC_H_MFP_PC11_MFP_UART1_TX (5UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - UART1 TX */
+#define SYS_PC_H_MFP_PC11_MFP_LCD_S31 (7UL<<SYS_PC_H_MFP_PC11_MFP_Pos) /*!<PC11 Pin Function - LCD SEG 31 */
+
+#define SYS_PC_H_MFP_PC10_MFP_GPC10 (0UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - GPIOC[10] */
+#define SYS_PC_H_MFP_PC10_MFP_SPI1_MISO0 (1UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - SPI1 MISO[0] */
+#define SYS_PC_H_MFP_PC10_MFP_UART1_RX (5UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - UART1 RX */
+#define SYS_PC_H_MFP_PC10_MFP_LCD_S30 (7UL<<SYS_PC_H_MFP_PC10_MFP_Pos) /*!<PC10 Pin Function - LCD SEG 30 */
+
+#define SYS_PC_H_MFP_PC9_MFP_GPC9 (0UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - GPIOC[9] */
+#define SYS_PC_H_MFP_PC9_MFP_SPI1_SCLK (1UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - SPI1 SCLK */
+#define SYS_PC_H_MFP_PC9_MFP_I2C1_SCL (5UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - I2C1 clock */
+#define SYS_PC_H_MFP_PC9_MFP_LCD_S29 (7UL<<SYS_PC_H_MFP_PC9_MFP_Pos) /*!<PC9 Pin Function - LCD SEG 29 */
+
+#define SYS_PC_H_MFP_PC8_MFP_GPC8 (0UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - GPIOC[8] */
+#define SYS_PC_H_MFP_PC8_MFP_SPI1_SS0 (1UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - SPI1 SS[0] */
+#define SYS_PC_H_MFP_PC8_MFP_EBI_XCLK (2UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - EBI XCLK */
+#define SYS_PC_H_MFP_PC8_MFP_I2C1_SDA (5UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - I2C1 DATA */
+#define SYS_PC_H_MFP_PC8_MFP_LCD_S28 (7UL<<SYS_PC_H_MFP_PC8_MFP_Pos) /*!<PC8 Pin Function - LCD SEG 28 */
+
+/********************* Bit definition of PD_L_MFP register **********************/
+#define SYS_PD_L_MFP_PD7_MFP_GPD7 (0UL<<SYS_PD_L_MFP_PD7_MFP_Pos) /*!<PD7 Pin Function - GPIOD[7] */
+#define SYS_PD_L_MFP_PD7_MFP_LCD_S2 (7UL<<SYS_PD_L_MFP_PD7_MFP_Pos) /*!<PD7 Pin Function - LCD SEG 2 */
+
+#define SYS_PD_L_MFP_PD6_MFP_GPD6 (0UL<<SYS_PD_L_MFP_PD6_MFP_Pos) /*!<PD6 Pin Function - GPIOD[6] */
+#define SYS_PD_L_MFP_PD6_MFP_LCD_S3 (7UL<<SYS_PD_L_MFP_PD6_MFP_Pos) /*!<PD6 Pin Function - LCD SEG 3 */
+
+#define SYS_PD_L_MFP_PD5_MFP_GPD5 (0UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - GPIOD[5] */
+#define SYS_PD_L_MFP_PD5_MFP_I2S_DOUT (2UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - I2S Dout */
+#define SYS_PD_L_MFP_PD5_MFP_SPI2_MOSI1 (3UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - SPI2 MOSI[1] */
+#define SYS_PD_L_MFP_PD5_MFP_LCD_S34 (7UL<<SYS_PD_L_MFP_PD5_MFP_Pos) /*!<PD5 Pin Function - LCD SEG 34 */
+
+#define SYS_PD_L_MFP_PD4_MFP_GPD4 (0UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - GPIOD[4] */
+#define SYS_PD_L_MFP_PD4_MFP_I2S_DIN (2UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - I2S Din */
+#define SYS_PD_L_MFP_PD4_MFP_SPI2_MISO1 (3UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - SPI2 MISO[1] */
+#define SYS_PD_L_MFP_PD4_MFP_SC1_CD (4UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - SmartCard1 card detection */
+#define SYS_PD_L_MFP_PD4_MFP_LCD_S35 (7UL<<SYS_PD_L_MFP_PD4_MFP_Pos) /*!<PD4 Pin Function - LCD SEG 35 */
+
+#define SYS_PD_L_MFP_PD3_MFP_GPD3 (0UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - GPIOD[3] */
+#define SYS_PD_L_MFP_PD3_MFP_UART1_CTS (1UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - UART1 CTSn */
+#define SYS_PD_L_MFP_PD3_MFP_I2S_BCLK (2UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - I2S BCLK */
+#define SYS_PD_L_MFP_PD3_MFP_SPI2_MOSI0 (3UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - SPI2 MOSI[0] */
+#define SYS_PD_L_MFP_PD3_MFP_SC1_RST (4UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - SmartCard1 reset */
+#define SYS_PD_L_MFP_PD3_MFP_ADC_CH11 (5UL<<SYS_PD_L_MFP_PD3_MFP_Pos) /*!<PD3 Pin Function - ADC input channel 11 */
+
+#define SYS_PD_L_MFP_PD2_MFP_GPD2 (0UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - GPIOD[2] */
+#define SYS_PD_L_MFP_PD2_MFP_UART1_RTS (1UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - UART1 RTSn */
+#define SYS_PD_L_MFP_PD2_MFP_I2S_WS (2UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - I2S WS */
+#define SYS_PD_L_MFP_PD2_MFP_SPI2_MISO0 (3UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - SPI2 MISO[0] */
+#define SYS_PD_L_MFP_PD2_MFP_SC1_PWR (4UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - SmartCard1 power */
+#define SYS_PD_L_MFP_PD2_MFP_ADC_CH10 (5UL<<SYS_PD_L_MFP_PD2_MFP_Pos) /*!<PD2 Pin Function - ADC input channel 10 */
+
+#define SYS_PD_L_MFP_PD1_MFP_GPD1 (0UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - GPIOD[1] */
+#define SYS_PD_L_MFP_PD1_MFP_UART1_TX (1UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - UART1 TX */
+#define SYS_PD_L_MFP_PD1_MFP_SPI2_SCLK (3UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - SPI2 SCLK */
+#define SYS_PD_L_MFP_PD1_MFP_SC1_DAT (4UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - SmartCard1 DATA */
+#define SYS_PD_L_MFP_PD1_MFP_ADC_CH9 (5UL<<SYS_PD_L_MFP_PD1_MFP_Pos) /*!<PD1 Pin Function - ADC input channel 9 */
+
+#define SYS_PD_L_MFP_PD0_MFP_GPD0 (0UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - GPIOD[0] */
+#define SYS_PD_L_MFP_PD0_MFP_UART1_RX (1UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - UART1 RX */
+#define SYS_PD_L_MFP_PD0_MFP_SPI2_SS0 (3UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - SPI2 chip selection 0 */
+#define SYS_PD_L_MFP_PD0_MFP_SC1_CLK (4UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - SmartCard1 clock */
+#define SYS_PD_L_MFP_PD0_MFP_ADC_CH8 (5UL<<SYS_PD_L_MFP_PD0_MFP_Pos) /*!<PD0 Pin Function - ADC input channel 8 */
+
+/********************* Bit definition of PD_H_MFP register **********************/
+#define SYS_PD_H_MFP_PD15_MFP_GPD15 (0UL<<SYS_PD_H_MFP_PD15_MFP_Pos) /*!<PD15 Pin Function - GPIOD[15] */
+#define SYS_PD_H_MFP_PD15_MFP_LCD_S0 (7UL<<SYS_PD_H_MFP_PD15_MFP_Pos) /*!<PD15 Pin Function - LCD SEG 0 */
+
+#define SYS_PD_H_MFP_PD14_MFP_GPD14 (0UL<<SYS_PD_H_MFP_PD14_MFP_Pos) /*!<PD14 Pin Function - GPIOD[14] */
+#define SYS_PD_H_MFP_PD14_MFP_LCD_S1 (7UL<<SYS_PD_H_MFP_PD14_MFP_Pos) /*!<PD14 Pin Function - LCD SEG 1 */
+
+#define SYS_PD_H_MFP_PD13_MFP_GPD13 (0UL<<SYS_PD_H_MFP_PD13_MFP_Pos) /*!<PD13 Pin Function - GPIOD[13] */
+#define SYS_PD_H_MFP_PD13_MFP_LCD_S14 (7UL<<SYS_PD_H_MFP_PD13_MFP_Pos) /*!<PD13 Pin Function - LCD SEG 14 */
+
+#define SYS_PD_H_MFP_PD12_MFP_GPD12 (0UL<<SYS_PD_H_MFP_PD12_MFP_Pos) /*!<PD12 Pin Function - GPIOD[12] */
+#define SYS_PD_H_MFP_PD12_MFP_LCD_S15 (7UL<<SYS_PD_H_MFP_PD12_MFP_Pos) /*!<PD12 Pin Function - LCD SEG 15 */
+
+#define SYS_PD_H_MFP_PD11_MFP_GPD11 (0UL<<SYS_PD_H_MFP_PD11_MFP_Pos) /*!<PD11 Pin Function - GPIOD[11] */
+#define SYS_PD_H_MFP_PD11_MFP_LCD_S16 (7uL<<SYS_PD_H_MFP_PD11_MFP_Pos) /*!<PD11 Pin Function - LCD SEG 16 */
+
+#define SYS_PD_H_MFP_PD10_MFP_GPD10 (0UL<<SYS_PD_H_MFP_PD10_MFP_Pos) /*!<PD10 Pin Function - GPIOD[10] */
+#define SYS_PD_H_MFP_PD10_MFP_LCD_S17 (7UL<<SYS_PD_H_MFP_PD10_MFP_Pos) /*!<PD10 Pin Function - LCD SEG 17 */
+
+#define SYS_PD_H_MFP_PD9_MFP_GPD9 (0UL<<SYS_PD_H_MFP_PD9_MFP_Pos) /*!<PD9 Pin Function - GPIOD[9] */
+#define SYS_PD_H_MFP_PD9_MFP_LCD_S18 (7UL<<SYS_PD_H_MFP_PD9_MFP_Pos) /*!<PD9 Pin Function - LCD SEG 18 */
+
+#define SYS_PD_H_MFP_PD8_MFP_GPD8 (0UL<<SYS_PD_H_MFP_PD8_MFP_Pos) /*!<PD8 Pin Function - GPIOD[8] */
+#define SYS_PD_H_MFP_PD8_MFP_LCD_S19 (7UL<<SYS_PD_H_MFP_PD8_MFP_Pos) /*!<PD8 Pin Function - LCD SEG 19 */
+
+/********************* Bit definition of PE_L_MFP register **********************/
+#define SYS_PE_L_MFP_PE7_MFP_GPE7 (0UL<<SYS_PE_L_MFP_PE7_MFP_Pos) /*!<PE7 Pin Function - GPIOE[7] */
+#define SYS_PE_L_MFP_PE7_MFP_LCD_S8 (7UL<<SYS_PE_L_MFP_PE7_MFP_Pos) /*!<PE7 Pin Function - LCD SEG 8 */
+
+#define SYS_PE_L_MFP_PE6_MFP_GPE6 (0UL<<SYS_PE_L_MFP_PE6_MFP_Pos) /*!<PE6 Pin Function - GPIOE[6] */
+
+#define SYS_PE_L_MFP_PE5_MFP_GPE5 (0UL<<SYS_PE_L_MFP_PE5_MFP_Pos) /*!<PE5 Pin Function - GPIOE[5] */
+#define SYS_PE_L_MFP_PE5_MFP_PWM1_CH1 (1UL<<SYS_PE_L_MFP_PE5_MFP_Pos) /*!<PE5 Pin Function - PWM1 Channel 1 */
+
+#define SYS_PE_L_MFP_PE4_MFP_GPE4 (0UL<<SYS_PE_L_MFP_PE4_MFP_Pos) /*!<PE4 Pin Function - GPIOE[4] */
+#define SYS_PE_L_MFP_PE4_MFP_SPI0_MOSI0 (6UL<<SYS_PE_L_MFP_PE4_MFP_Pos) /*!<PE4 Pin Function - SPI0 MOSI[0] */
+
+#define SYS_PE_L_MFP_PE3_MFP_GPE3 (0UL<<SYS_PE_L_MFP_PE3_MFP_Pos) /*!<PE3 Pin Function - GPIOE[3] */
+#define SYS_PE_L_MFP_PE3_MFP_SPI0_MISO0 (6UL<<SYS_PE_L_MFP_PE3_MFP_Pos) /*!<PE3 Pin Function - SPI0 MISO[0] */
+
+#define SYS_PE_L_MFP_PE2_MFP_GPE2 (0UL<<SYS_PE_L_MFP_PE2_MFP_Pos) /*!<PE2 Pin Function - GPIOE[2] */
+#define SYS_PE_L_MFP_PE2_MFP_SPI0_SCLK (6UL<<SYS_PE_L_MFP_PE2_MFP_Pos) /*!<PE2 Pin Function - SPI0 SCLK */
+
+#define SYS_PE_L_MFP_PE1_MFP_GPE1 (0UL<<SYS_PE_L_MFP_PE1_MFP_Pos) /*!<PE1 Pin Function - GPIOE[1] */
+#define SYS_PE_L_MFP_PE1_MFP_PWM1_CH3 (1UL<<SYS_PE_L_MFP_PE1_MFP_Pos) /*!<PE1 Pin Function - PWM1 Channel 3 */
+#define SYS_PE_L_MFP_PE1_MFP_SPI0_SS0 (6UL<<SYS_PE_L_MFP_PE1_MFP_Pos) /*!<PE1 Pin Function - SPI0 chip selection 0 */
+
+#define SYS_PE_L_MFP_PE0_MFP_GPE0 (0UL<<SYS_PE_L_MFP_PE0_MFP_Pos) /*!<PE0 Pin Function - GPIOE[0] */
+#define SYS_PE_L_MFP_PE0_MFP_PWM1_CH2 (1UL<<SYS_PE_L_MFP_PE0_MFP_Pos) /*!<PE0 Pin Function - PWM1 Channel 2 */
+#define SYS_PE_L_MFP_PE0_MFP_I2S_MCLK (2UL<<SYS_PE_L_MFP_PE0_MFP_Pos) /*!<PE0 Pin Function - I2S MCLK */
+
+/********************* Bit definition of PE_H_MFP register **********************/
+#define SYS_PE_H_MFP_PE15_MFP_GPE15 (0UL<<SYS_PE_H_MFP_PE15_MFP_Pos) /*!<PE15 Pin Function - GPIOE[15] */
+#define SYS_PE_H_MFP_PE15_MFP_LCD_S29 (7UL<<SYS_PE_H_MFP_PE15_MFP_Pos) /*!<PE15 Pin Function - LCD SEG 29 */
+
+#define SYS_PE_H_MFP_PE14_MFP_GPE14 (0UL<<SYS_PE_H_MFP_PE14_MFP_Pos) /*!<PE14 Pin Function - GPIOE[14] */
+#define SYS_PE_H_MFP_PE14_MFP_LCD_S28 (7UL<<SYS_PE_H_MFP_PE14_MFP_Pos) /*!<PE14 Pin Function - LCD SEG 28 */
+
+#define SYS_PE_H_MFP_PE13_MFP_GPE13 (0UL<<SYS_PE_H_MFP_PE13_MFP_Pos) /*!<PE13 Pin Function - GPIOE[13] */
+#define SYS_PE_H_MFP_PE13_MFP_LCD_S27 (7UL<<SYS_PE_H_MFP_PE13_MFP_Pos) /*!<PE13 Pin Function - LCD SEG 27 */
+
+#define SYS_PE_H_MFP_PE12_MFP_GPE12 (0UL<<SYS_PE_H_MFP_PE12_MFP_Pos) /*!<PE12 Pin Function - GPIOE[12] */
+#define SYS_PE_H_MFP_PE12_MFP_UART1_CTS (7UL<<SYS_PE_H_MFP_PE12_MFP_Pos) /*!<PE12 Pin Function - UART1 CTSn */
+
+#define SYS_PE_H_MFP_PE11_MFP_GPE11 (0UL<<SYS_PE_H_MFP_PE11_MFP_Pos) /*!<PE11 Pin Function - GPIOE[11] */
+#define SYS_PE_H_MFP_PE11_MFP_UART1_RTS (7UL<<SYS_PE_H_MFP_PE11_MFP_Pos) /*!<PE11 Pin Function - UART1 RTSn */
+
+#define SYS_PE_H_MFP_PE10_MFP_GPE10 (0UL<<SYS_PE_H_MFP_PE10_MFP_Pos) /*!<PE10 Pin Function - GPIOE[10] */
+#define SYS_PE_H_MFP_PE10_MFP_UART1_TX (7UL<<SYS_PE_H_MFP_PE10_MFP_Pos) /*!<PE10 Pin Function - UART1 TX */
+
+#define SYS_PE_H_MFP_PE9_MFP_GPE9 (0UL<<SYS_PE_H_MFP_PE9_MFP_Pos) /*!<PE9 Pin Function - GPIOE[9] */
+#define SYS_PE_H_MFP_PE9_MFP_UART1_RX (7UL<<SYS_PE_H_MFP_PE9_MFP_Pos) /*!<PE9 Pin Function - UART1 RX */
+
+#define SYS_PE_H_MFP_PE8_MFP_GPE8 (0UL<<SYS_PE_H_MFP_PE8_MFP_Pos) /*!<PE8 Pin Function - GPIOA[8] */
+#define SYS_PE_H_MFP_PE8_MFP_LCD_S9 (7UL<<SYS_PE_H_MFP_PE8_MFP_Pos) /*!<PE8 Pin Function - LCD SEG 9 */
+
+/********************* Bit definition of PF_L_MFP register **********************/
+#define SYS_PF_L_MFP_PF5_MFP_GPF5 (0UL<<SYS_PF_L_MFP_PF5_MFP_Pos) /*!<PF5 Pin Function - GPIOF[5] */
+#define SYS_PF_L_MFP_PF5_MFP_I2C0_SCL (1UL<<SYS_PF_L_MFP_PF5_MFP_Pos) /*!<PF5 Pin Function - I2C0 clock */
+
+#define SYS_PF_L_MFP_PF4_MFP_GPF4 (0UL<<SYS_PF_L_MFP_PF4_MFP_Pos) /*!<PF4 Pin Function - GPIOF[4] */
+#define SYS_PF_L_MFP_PF4_MFP_I2C0_SDA (1UL<<SYS_PF_L_MFP_PF4_MFP_Pos) /*!<PF4 Pin Function - I2C0 DATA */
+
+#define SYS_PF_L_MFP_PF3_MFP_GPF3 (0UL<<SYS_PF_L_MFP_PF3_MFP_Pos) /*!<PF3 Pin Function - GPIOF[3] */
+#define SYS_PF_L_MFP_PF3_MFP_HXT_IN (7UL<<SYS_PF_L_MFP_PF3_MFP_Pos) /*!<PF3 Pin Function - HXT IN */
+
+#define SYS_PF_L_MFP_PF2_MFP_GPF2 (0UL<<SYS_PF_L_MFP_PF2_MFP_Pos) /*!<PF2 Pin Function - GPIOF[2] */
+#define SYS_PF_L_MFP_PF2_MFP_HXT_OUT (7UL<<SYS_PF_L_MFP_PF2_MFP_Pos) /*!<PF2 Pin Function - HXT OUT */
+
+#define SYS_PF_L_MFP_PF1_MFP_GPF1 (0UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - GPIOF[1] */
+#define SYS_PF_L_MFP_PF1_MFP_CKO (4UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - CKO */
+#define SYS_PF_L_MFP_PF1_MFP_EXT_INT1 (5UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - External interrupt 1 */
+#define SYS_PF_L_MFP_PF1_MFP_ICE_CLK (7UL<<SYS_PF_L_MFP_PF1_MFP_Pos) /*!<PF1 Pin Function - ICE CLOCK */
+
+#define SYS_PF_L_MFP_PF0_MFP_GPF0 (0UL<<SYS_PF_L_MFP_PF0_MFP_Pos) /*!<PF0 Pin Function - GPIOF[0] */
+#define SYS_PF_L_MFP_PF0_MFP_EXT_INT0 (5UL<<SYS_PF_L_MFP_PF0_MFP_Pos) /*!<PF0 Pin Function - External interrupt 0 */
+#define SYS_PF_L_MFP_PF0_MFP_ICE_DAT (7UL<<SYS_PF_L_MFP_PF0_MFP_Pos) /*!<PF0 Pin Function - ICE DATA */
+
+/*@}*/ /* end of group NANO100_SYS_EXPORTED_CONSTANTS */
+
+/** @addtogroup NANO100_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear Brown-out detector interrupt flag
+ * @param None
+ * @return None
+ * @details This macro clear Brown-out detector interrupt flag.
+ */
+#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODSTS |= SYS_BODSTS_BOD_INT_Msk)
+
+/**
+ * @brief Disable Brown-out 2.5V detector function
+ * @param None
+ * @return None
+ * @details This macro disable Brown-out 2.5V detector function.
+ */
+#define SYS_DISABLE_BOD25() (SYS->BODCTL &= ~SYS_BODCTL_BOD25_EN_Msk)
+
+/**
+ * @brief Enable Brown-out 2.5V detector function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out 2.5V detector function.
+ */
+#define SYS_ENABLE_BOD25() (SYS->BODCTL |= SYS_BODCTL_BOD25_EN_Msk)
+
+/**
+ * @brief Disable Brown-out 2.0V detector function
+ * @param None
+ * @return None
+ * @details This macro disable Brown-out 2.0V detector function.
+ */
+#define SYS_DISABLE_BOD20() (SYS->BODCTL &= ~SYS_BODCTL_BOD20_EN_Msk)
+
+/**
+ * @brief Enable Brown-out 2.0V detector function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out 2.0V detector function.
+ */
+#define SYS_ENABLE_BOD20() (SYS->BODCTL |= SYS_BODCTL_BOD20_EN_Msk)
+
+/**
+ * @brief Disable Brown-out 1.7V detector function
+ * @param None
+ * @return None
+ * @details This macro disable Brown-out 1.7V detector function.
+ */
+#define SYS_DISABLE_BOD17() (SYS->BODCTL &= ~SYS_BODCTL_BOD17_EN_Msk)
+
+/**
+ * @brief Enable Brown-out 1.7V detector function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out 1.7V detector function.
+ */
+#define SYS_ENABLE_BOD17() (SYS->BODCTL |= SYS_BODCTL_BOD17_EN_Msk)
+
+/**
+ * @brief Get Brown-out detector interrupt flag
+ * @param None
+ * @retval 0 Brown-out detect interrupt flag is not set.
+ * @retval >=1 Brown-out detect interrupt flag is set.
+ * @details This macro get Brown-out detector interrupt flag.
+ */
+#define SYS_GET_BOD_INT_FLAG() (SYS->BODSTS & SYS_BODSTS_BOD_INT_Msk)
+
+/**
+ * @brief Get Brown-out 2.5V detector status
+ * @param None
+ * @retval 0 System voltage is higher than 2.5V setting or BOD_EN is 0.
+ * @retval >=1 System voltage is lower than 2.5V setting.
+ * @details This macro get Brown-out detector output status.
+ * If the BOD_EN is 0, this function always return 0.
+ */
+#define SYS_GET_BOD25_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD25_drop_Msk)
+
+/**
+ * @brief Get Brown-out 2.0V detector status
+ * @param None
+ * @retval 0 System voltage is higher than 2.0V setting or BOD_EN is 0.
+ * @retval >=1 System voltage is lower than 2.0V setting.
+ * @details This macro get Brown-out detector output status.
+ * If the BOD_EN is 0, this function always return 0.
+ */
+#define SYS_GET_BOD20_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD20_drop_Msk)
+
+/**
+ * @brief Get Brown-out 1.7V detector status
+ * @param None
+ * @retval 0 System voltage is higher than 1.7V setting or BOD_EN is 0.
+ * @retval >=1 System voltage is lower than 1.7V setting.
+ * @details This macro get Brown-out detector output status.
+ * If the BOD_EN is 0, this function always return 0.
+ */
+#define SYS_GET_BOD17_OUTPUT() (SYS->BODSTS & SYS_BODSTS_BOD17_drop_Msk)
+
+/**
+ * @brief Disable Brown-out 2.5V detector interrupt function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector interrupt function.
+ */
+#define SYS_DISABLE_BOD25_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD25_RST_EN_Msk)
+
+/**
+ * @brief Enable Brown-out 2.5V detector reset function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detect reset function.
+ */
+#define SYS_ENABLE_BOD25_RST() (SYS->BODCTL |= SYS_BODCTL_BOD25_RST_EN_Msk)
+
+/**
+ * @brief Disable Brown-out 2.0V detector interrupt function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector interrupt function.
+ */
+#define SYS_DISABLE_BOD20_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD20_RST_EN_Msk)
+
+/**
+ * @brief Enable Brown-out 2.0V detector reset function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detect reset function.
+ */
+#define SYS_ENABLE_BOD20_RST() (SYS->BODCTL |= SYS_BODCTL_BOD20_RST_EN_Msk)
+
+/**
+ * @brief Disable Brown-out 1.7V detector interrupt function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector interrupt function.
+ */
+#define SYS_DISABLE_BOD17_RST() (SYS->BODCTL &= ~SYS_BODCTL_BOD17_RST_EN_Msk)
+
+/**
+ * @brief Enable Brown-out 1.7V detector reset function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detect reset function.
+ */
+#define SYS_ENABLE_BOD17_RST() (SYS->BODCTL |= SYS_BODCTL_BOD17_RST_EN_Msk)
+
+/**
+ * @brief Get reset source is from Brown-out detector reset
+ * @param None
+ * @retval 0 Previous reset source is not from Brown-out detector reset
+ * @retval >=1 Previous reset source is from Brown-out detector reset
+ * @details This macro get previous reset source is from Brown-out detect reset or not.
+ */
+#define SYS_IS_BOD_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_BOD_Msk)
+
+
+/**
+ * @brief Get reset source is from CPU reset
+ * @param None
+ * @retval 0 Previous reset source is not from CPU reset
+ * @retval >=1 Previous reset source is from CPU reset
+ * @details This macro get previous reset source is from CPU reset.
+ */
+#define SYS_IS_CPU_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_CPU_Msk)
+
+/**
+ * @brief Get reset source is from Power-on Reset
+ * @param None
+ * @retval 0 Previous reset source is not from Power-on Reset
+ * @retval >=1 Previous reset source is from Power-on Reset
+ * @details This macro get previous reset source is from Power-on Reset.
+ */
+#define SYS_IS_POR_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_POR_Msk)
+
+/**
+ * @brief Get reset source is from reset pin reset
+ * @param None
+ * @retval 0 Previous reset source is not from reset pin reset
+ * @retval >=1 Previous reset source is from reset pin reset
+ * @details This macro get previous reset source is from reset pin reset.
+ */
+#define SYS_IS_RSTPIN_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_PAD_Msk)
+
+
+/**
+ * @brief Get reset source is from system reset
+ * @param None
+ * @retval 0 Previous reset source is not from system reset
+ * @retval >=1 Previous reset source is from system reset
+ * @details This macro get previous reset source is from system reset.
+ */
+#define SYS_IS_SYSTEM_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_SYS_Msk)
+
+
+/**
+ * @brief Get reset source is from window watch dog reset
+ * @param None
+ * @retval 0 Previous reset source is not from window watch dog reset
+ * @retval >=1 Previous reset source is from window watch dog reset
+ * @details This macro get previous reset source is from window watch dog reset.
+ */
+#define SYS_IS_WDT_RST() (SYS->RST_SRC & SYS_RST_SRC_RSTS_WDT_Msk)
+
+/**
+ * @brief Disable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro disable Power-on Reset function.
+ */
+#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
+
+/**
+ * @brief Enable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro enable Power-on Reset function.
+ */
+#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
+
+
+/**
+ * @brief Clear reset source flag
+ * @param[in] u32RstSrc is reset source. Including:
+ * - \ref SYS_RST_SRC_RSTS_POR_Msk
+ * - \ref SYS_RST_SRC_RSTS_PAD_Msk
+ * - \ref SYS_RST_SRC_RSTS_WDT_Msk
+ * - \ref SYS_RST_SRC_RSTS_BOD_Msk
+ * - \ref SYS_RST_SRC_RSTS_SYS_Msk
+ * - \ref SYS_RST_SRC_RSTS_CPU_Msk
+ * @return None
+ * @details This macro clear reset source flag.
+ */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RST_SRC = u32RstSrc )
+
+/**
+ * @brief Get HIRC trim status
+ * @param None
+ * @retval BIT0 HIRC Frequency Lock
+ * @retval BIT1 Trim Failure Interrupt
+ * @retval BIT2 LXT Clock error
+ * @details This macro get HIRC trim interrupt status register.
+ */
+#define SYS_GET_IRCTRIM_INT_FLAG() (SYS->IRCTRIMINT)
+
+/**
+ * @brief Clear HIRC trim flag
+ * @param[in] u32IRCTrimFlg is HIRC trim flags. Including:
+ * - \ref SYS_IRCTRIMINT_FAIL_INT
+ * - \ref SYS_IRCTRIMINT_32KERR_INT
+ * @return None
+ * @details This macro clear HIRC trim flag.
+ */
+#define SYS_CLEAR_IRCTRIM_INT_FLAG(u32IRCTrimFlg) (SYS->IRCTRIMINT = u32IRCTrimFlg )
+
+
+/**
+ * @brief Disable register write-protection function
+ * @param None
+ * @return None
+ * @details This function disable register write-protection function.
+ * To unlock the protected register to allow write access.
+ */
+__STATIC_INLINE void SYS_UnlockReg(void)
+{
+ while(SYS->RegLockAddr != SYS_RegLockAddr_RegUnLock_Msk) {
+ SYS->RegLockAddr = 0x59;
+ SYS->RegLockAddr = 0x16;
+ SYS->RegLockAddr = 0x88;
+ }
+}
+
+/**
+ * @brief Enable register write-protection function
+ * @param None
+ * @return None
+ * @details This function is used to enable register write-protection function.
+ * To lock the protected register to forbid write access.
+ */
+__STATIC_INLINE void SYS_LockReg(void)
+{
+ SYS->RegLockAddr = 0;
+}
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+void SYS_EnableIRCTrim(uint32_t u32TrimSel,uint32_t u32TrimEnInt);
+void SYS_DisableIRCTrim(void);
+/*@}*/ /* end of group NANO100_SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_SYS_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SYS_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_timer.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,284 @@
+/**************************************************************************//**
+ * @file timer.c
+ * @version V1.00
+ * $Revision: 11 $
+ * $Date: 15/06/23 5:15p $
+ * @brief Nano100 series TIMER driver source file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_TIMER_Driver TIMER Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief This API is used to configure timer to operate in specified mode
+ * and frequency. If timer cannot work in target frequency, a closest
+ * frequency will be chose and returned.
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Mode Operation mode. Possible options are
+ * - \ref TIMER_ONESHOT_MODE
+ * - \ref TIMER_PERIODIC_MODE
+ * - \ref TIMER_TOGGLE_MODE
+ * - \ref TIMER_CONTINUOUS_MODE
+ * @param[in] u32Freq Target working frequency
+ * @return Real Timer working frequency
+ * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+ * \ref TIMER_Start macro or program registers directly
+ */
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Cmpr = 0, u32Prescale = 0;
+
+ // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
+ if(u32Freq > (u32Clk / 2)) {
+ u32Cmpr = 2;
+ } else {
+ if(u32Clk >= 0x2000000) {
+ u32Prescale = 3; // real prescaler value is 4
+ u32Clk >>= 2;
+ } else if(u32Clk >= 0x1000000) {
+ u32Prescale = 1; // real prescaler value is 2
+ u32Clk >>= 1;
+ }
+ u32Cmpr = u32Clk / u32Freq;
+ }
+ timer->CMPR = u32Cmpr;
+ timer->PRECNT = u32Prescale;
+ timer->CTL = u32Mode;
+
+
+ return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
+}
+
+/**
+ * @brief This API stops Timer counting and disable the Timer interrupt function
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+void TIMER_Close(TIMER_T *timer)
+{
+ timer->CTL = 0;
+ timer->IER = 0;
+}
+
+/**
+ * @brief This API is used to create a delay loop for u32usec micro seconds
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Usec Delay period in micro seconds with 10 usec every step. Valid values are between 10~1000000 (10 micro second ~ 1 second)
+ * @return None
+ * @note This API overwrites the register setting of the timer used to count the delay time.
+ * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay
+ */
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
+ long long u64Cmpr;
+
+ // Clear current timer configuration
+ timer->CTL = 0;
+
+ if(u32Clk == 10000) { // min delay is 100us if timer clock source is LIRC 10k
+ u32Usec = ((u32Usec + 99) / 100) * 100;
+ } else { // 10 usec every step
+ u32Usec = ((u32Usec + 9) / 10) * 10;
+ }
+
+ if(u32Clk >= 0x2000000) {
+ u32Prescale = 3; // real prescaler value is 4
+ u32Clk >>= 2;
+ } else if(u32Clk >= 0x1000000) {
+ u32Prescale = 1; // real prescaler value is 2
+ u32Clk >>= 1;
+ }
+
+ // u32Usec * u32Clk might overflow if using uint32_t
+ u64Cmpr = ((long long)u32Usec * (long long)u32Clk) / (long long)1000000;
+
+ timer->CMPR = (uint32_t)u64Cmpr;
+ timer->PRECNT = u32Prescale;
+ timer->CTL = TIMER_CTL_TMR_EN_Msk; // one shot mode
+
+ // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+ // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
+ for(; delay > 0; delay--) {
+ __NOP();
+ }
+
+ while(timer->CTL & TIMER_CTL_TMR_ACT_Msk);
+
+}
+
+/**
+ * @brief This API is used to enable timer capture function with specified mode and capture edge
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32CapMode Timer capture mode. Could be
+ * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
+ * - \ref TIMER_CAPTURE_TRIGGER_COUNTING_MODE
+ * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
+ * @param[in] u32Edge Timer capture edge. Possible values are
+ * - \ref TIMER_CAPTURE_FALLING_EDGE
+ * - \ref TIMER_CAPTURE_RISING_EDGE
+ * - \ref TIMER_CAPTURE_FALLING_THEN_RISING_EDGE
+ * - \ref TIMER_CAPTURE_RISING_THEN_FALLING_EDGE
+ * @return None
+ * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly
+ */
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
+{
+
+ timer->CTL = (timer->CTL & ~(TIMER_CTL_TCAP_MODE_Msk |
+ TIMER_CTL_TCAP_CNT_MODE_Msk |
+ TIMER_CTL_TCAP_EDGE_Msk)) |
+ u32CapMode | u32Edge | TIMER_CTL_TCAP_EN_Msk;
+}
+
+/**
+ * @brief This API is used to disable the Timer capture function
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+void TIMER_DisableCapture(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_TCAP_EN_Msk;
+
+}
+
+/**
+ * @brief This function is used to enable the Timer counter function with specify detection edge
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Edge Detection edge of counter pin. Could be ether
+ * - \ref TIMER_COUNTER_RISING_EDGE, or
+ * - \ref TIMER_COUNTER_FALLING_EDGE
+ * @return None
+ * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly
+ */
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
+{
+ timer->CTL = (timer->CTL & ~TIMER_CTL_EVENT_EDGE_Msk) | u32Edge;
+ timer->CTL |= TIMER_CTL_EVENT_EN_Msk;
+}
+
+/**
+ * @brief This API is used to disable the Timer event counter function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+void TIMER_DisableEventCounter(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_EVENT_EN_Msk;
+}
+
+/**
+ * @brief This API is used to get the clock frequency of Timer
+ * @param[in] timer The base address of Timer module
+ * @return Timer clock frequency
+ * @note This API cannot return correct clock rate if timer source is external clock input.
+ */
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)
+{
+ uint32_t u32Src;
+ const uint32_t au32Clk[] = {__HXT, __LXT, __LIRC, 0}; // we don't know actual clock if external pin is clock source, set to 0 here
+
+ if(timer == TIMER0)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0_S_Msk) >> CLK_CLKSEL1_TMR0_S_Pos;
+ else if(timer == TIMER1)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1_S_Msk) >> CLK_CLKSEL1_TMR1_S_Pos;
+ else if(timer == TIMER2)
+ u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR2_S_Msk) >> CLK_CLKSEL2_TMR2_S_Pos;
+ else // Timer 3
+ u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR3_S_Msk) >> CLK_CLKSEL2_TMR3_S_Pos;
+
+ if(u32Src < 4)
+ return au32Clk[u32Src];
+ else
+ return __HIRC;
+
+}
+
+/**
+ * @brief This function is used to enable the Timer frequency counter function
+ * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2
+ * @param[in] u32DropCount This parameter has no effect in Nano100 series BSP
+ * @param[in] u32Timeout This parameter has no effect in Nano100 series BSP
+ * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE
+ * @return None
+ * @details This function is used to calculate input event frequency. After enable
+ * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3
+ * will be configured for this function. The mode used to calculate input
+ * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical
+ * Reference Manual
+ */
+void TIMER_EnableFreqCounter(TIMER_T *timer,
+ uint32_t u32DropCount,
+ uint32_t u32Timeout,
+ uint32_t u32EnableInt)
+{
+ TIMER_T *t; // store the timer base to configure compare value
+
+ t = (timer == TIMER0) ? TIMER1 : TIMER3;
+
+ t->CMPR = 0xFFFFFF;
+ t->IER = u32EnableInt ? TIMER_IER_TCAP_IE_Msk : 0;
+ timer->CTL = TIMER_CTL_INTR_TRG_EN_Msk | TIMER_CTL_TMR_EN_Msk;
+
+ return;
+}
+/**
+ * @brief This function is used to disable the Timer frequency counter function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+void TIMER_DisableFreqCounter(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_INTR_TRG_EN_Msk;
+}
+
+/**
+ * @brief This function is used to select the interrupt source used to trigger other modules.
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be:
+ * - \ref TIMER_TIMEOUT_TRIGGER
+ * - \ref TIMER_CAPTURE_TRIGGER
+ * @return None
+ */
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
+{
+ timer->CTL = (timer->CTL & ~TIMER_CTL_CAP_TRG_EN_Msk) | u32Src;
+}
+
+/**
+ * @brief This function is used to set modules trigger by timer interrupt
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Mask The mask of modules (ADC, DAC and PDMA) trigger by timer. Is the combination of
+ * - \ref TIMER_CTL_PDMA_TEEN_Msk,
+ * - \ref TIMER_CTL_ADC_TEEN_Msk, and
+ * - \ref TIMER_CTL_DAC_TEEN_Msk,
+ * @return None
+ */
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
+{
+ timer->CTL = (timer->CTL & ~(TIMER_CTL_PDMA_TEEN_Msk | TIMER_CTL_DAC_TEEN_Msk | TIMER_CTL_ADC_TEEN_Msk)) | u32Mask;
+}
+
+/*@}*/ /* end of group NANO100_TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_TIMER_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_timer.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,325 @@
+/**************************************************************************//**
+ * @file timer.h
+ * @version V1.00
+ * $Revision: 6 $
+ * $Date: 14/08/29 7:56p $
+ * @brief Nano100 series TIMER driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_TIMER_Driver TIMER Driver
+ @{
+*/
+
+/** @addtogroup NANO100_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
+ @{
+*/
+
+#define TIMER_ONESHOT_MODE (0UL) /*!< Timer working in one shot mode */
+#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in periodic mode */
+#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in toggle mode */
+#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_MODE_SEL_Pos) /*!< Timer working in continuous mode */
+
+#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL) /*!< Free counting mode */
+#define TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_CTL_TCAP_CNT_MODE_Msk) /*!< Trigger counting mode */
+#define TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_CTL_TCAP_MODE_Msk) /*!< Counter reset mode */
+
+#define TIMER_CAPTURE_FALLING_EDGE (0UL) /*!< Falling edge trigger timer capture */
+#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Rising edge trigger timer capture */
+#define TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Falling edge then rising edge trigger timer capture */
+#define TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_CTL_TCAP_EDGE_Pos) /*!< Rising edge then falling edge trigger timer capture */
+
+#define TIMER_COUNTER_RISING_EDGE (TIMER_CTL_EVENT_EDGE_Msk) /*!< Counter increase on rising edge */
+#define TIMER_COUNTER_FALLING_EDGE (0UL) /*!< Counter increase on falling edge */
+
+#define TIMER_TIMEOUT_TRIGGER (0UL) /*!< Timer timeout trigger other modules */
+#define TIMER_CAPTURE_TRIGGER (TIMER_CTL_CAP_TRG_EN_Msk) /*!< Timer capture trigger other modules */
+
+/*@}*/ /* end of group NANO100_TIMER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro is used to set new Timer compared value
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF
+ * @return None
+ * \hideinitializer
+ */
+#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMPR = (u32Value))
+
+/**
+ * @brief This macro is used to set new Timer prescale value
+ * @param[in] timer The base address of Timer module
+ * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF
+ * @return None
+ * @note Clock input is divided by (prescale + 1) before it is fed into timer
+ * \hideinitializer
+ */
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->PRECNT = (u32Value))
+
+/**
+ * @brief This macro is used to check if specify Timer is inactive or active
+ * @return timer is activate or inactivate
+ * @retval 0 Timer 24-bit up counter is inactive
+ * @retval 1 Timer 24-bit up counter is active
+ * \hideinitializer
+ */
+#define TIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_TMR_ACT_Msk ? 1 : 0)
+
+
+/**
+ * @brief This function is used to start Timer counting
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_TMR_EN_Msk;
+}
+
+/**
+ * @brief This function is used to stop Timer counting
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_TMR_EN_Msk;
+}
+
+/**
+ * @brief This function is used to enable the Timer wake-up function
+ * @param[in] timer The base address of Timer module
+ * @return None
+ * @note To wake the system from power down mode, timer clock source must be ether LXT or LIRC
+ */
+__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_WAKE_EN_Msk;
+}
+
+/**
+ * @brief This function is used to disable the Timer wake-up function
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_WAKE_EN_Msk;
+}
+
+
+/**
+ * @brief This function is used to enable the capture pin detection de-bounce function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_TCAP_DEB_EN_Msk;
+}
+
+/**
+ * @brief This function is used to disable the capture pin detection de-bounce function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_TCAP_DEB_EN_Msk;
+}
+
+
+/**
+ * @brief This function is used to enable the counter pin detection de-bounce function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_EVNT_DEB_EN_Msk;
+}
+
+/**
+ * @brief This function is used to disable the counter pin detection de-bounce function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_EVNT_DEB_EN_Msk;
+}
+
+/**
+ * @brief This function is used to enable the Timer time-out interrupt function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
+{
+ timer->IER |= TIMER_IER_TMR_IE_Msk;
+}
+
+/**
+ * @brief This function is used to disable the Timer time-out interrupt function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
+{
+ timer->IER &= ~TIMER_IER_TMR_IE_Msk;
+}
+
+/**
+ * @brief This function is used to enable the Timer capture trigger interrupt function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
+{
+ timer->IER |= TIMER_IER_TCAP_IE_Msk;
+}
+
+/**
+ * @brief This function is used to disable the Timer capture trigger interrupt function.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
+{
+ timer->IER &= ~TIMER_IER_TCAP_IE_Msk;
+}
+
+/**
+ * @brief This function indicates Timer time-out interrupt occurred or not.
+ * @param[in] timer The base address of Timer module
+ * @return Timer time-out interrupt occurred or not
+ * @retval 0 Timer time-out interrupt did not occur
+ * @retval 1 Timer time-out interrupt occurred
+ */
+__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
+{
+ return(timer->ISR & TIMER_ISR_TMR_IS_Msk ? 1 : 0);
+}
+
+/**
+ * @brief This function clears the Timer time-out interrupt flag.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
+{
+ timer->ISR = TIMER_ISR_TMR_IS_Msk;
+}
+
+/**
+ * @brief This function indicates Timer capture interrupt occurred or not.
+ * @param[in] timer The base address of Timer module
+ * @return Timer capture interrupt occurred or not
+ * @retval 0 Timer capture interrupt did not occur
+ * @retval 1 Timer capture interrupt occurred
+ */
+__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
+{
+ return(timer->ISR & TIMER_ISR_TCAP_IS_Msk ? 1 : 0);
+}
+
+/**
+ * @brief This function clears the Timer capture interrupt flag.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
+{
+ timer->ISR = TIMER_ISR_TCAP_IS_Msk;
+}
+
+/**
+ * @brief This function indicates Timer has waked up system or not.
+ * @param[in] timer The base address of Timer module
+ * @return Timer has waked up system or not
+ * @retval 0 Timer did not wake up system
+ * @retval 1 Timer wake up system
+ */
+__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
+{
+ return (timer->ISR & TIMER_ISR_TMR_WAKE_STS_Msk ? 1 : 0);
+}
+
+/**
+ * @brief This function clears the Timer wakeup interrupt flag.
+ * @param[in] timer The base address of Timer module
+ * @return None
+ */
+__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
+{
+ timer->ISR = TIMER_ISR_TMR_WAKE_STS_Msk;
+}
+
+/**
+ * @brief This function gets the Timer capture data.
+ * @param[in] timer The base address of Timer module
+ * @return Timer capture data value
+ */
+__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
+{
+ return timer->TCAP;
+}
+
+/**
+ * @brief This function reports the current timer counter value.
+ * @param[in] timer The base address of Timer module
+ * @return Timer counter value
+ */
+__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
+{
+ return timer->DR;
+}
+
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
+void TIMER_Close(TIMER_T *timer);
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
+void TIMER_DisableCapture(TIMER_T *timer);
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
+void TIMER_DisableEventCounter(TIMER_T *timer);
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);
+void TIMER_EnableFreqCounter(TIMER_T *timer,
+ uint32_t u32DropCount,
+ uint32_t u32Timeout,
+ uint32_t u32EnableInt);
+void TIMER_DisableFreqCounter(TIMER_T *timer);
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
+
+/*@}*/ /* end of group NANO100_TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_TIMER_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__TIMER_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_uart.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,408 @@
+/**************************************************************************//**
+ * @file uart.c
+ * @version V1.00
+ * $Revision: 11 $
+ * $Date: 15/06/26 1:28p $
+ * @brief Nano100 series Smartcard UART mode (UART) driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_UART_Driver UART Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+/// @cond HIDDEN_SYMBOLS
+extern uint32_t SysGet_PLLClockFreq(void);
+/// @endcond /* HIDDEN_SYMBOLS */
+
+
+/**
+ * @brief The function is used to clear UART specified interrupt flag.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module..
+ *
+ * @return None
+ */
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
+{
+
+ if(u32InterruptFlag & UART_ISR_RLS_IS_Msk) { /* clear Receive Line Status Interrupt */
+ uart->FSR |= UART_FSR_BI_F_Msk | UART_FSR_FE_F_Msk | UART_FSR_FE_F_Msk;
+ uart->TRSR |= UART_TRSR_RS485_ADDET_F_Msk;
+ }
+
+ if(u32InterruptFlag & UART_ISR_MODEM_IS_Msk) /* clear Modem Interrupt */
+ uart->MCSR |= UART_MCSR_DCT_F_Msk;
+
+ if(u32InterruptFlag & UART_ISR_BUF_ERR_IS_Msk) { /* clear Buffer Error Interrupt */
+ uart->FSR |= UART_FSR_RX_OVER_F_Msk | UART_FSR_TX_OVER_F_Msk;
+ }
+
+ if(u32InterruptFlag & UART_ISR_WAKE_IS_Msk) { /* clear wake up Interrupt */
+ uart->ISR |= UART_ISR_WAKE_IS_Msk;
+ }
+
+ if(u32InterruptFlag & UART_ISR_ABAUD_IS_Msk) { /* clear auto-baud rate Interrupt */
+ uart->TRSR |= UART_TRSR_ABAUD_TOUT_F_Msk | UART_TRSR_ABAUD_F_Msk;
+ }
+
+ if(u32InterruptFlag & UART_ISR_LIN_IS_Msk) { /* clear LIN break Interrupt */
+ uart->TRSR |= UART_TRSR_LIN_TX_F_Msk | UART_TRSR_LIN_RX_F_Msk | UART_TRSR_BIT_ERR_F_Msk;
+ }
+
+}
+
+
+/**
+ * @brief The function is used to disable UART.
+ *
+ * @param[in] uart The base address of UART module.
+ *
+ * @return None
+ */
+void UART_Close(UART_T* uart)
+{
+ uart->IER = 0;
+}
+
+
+/**
+ * @brief The function is used to disable UART auto flow control.
+ *
+ * @param[in] uart The base address of UART module.
+ *
+ * @return None
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+ uart->CTL &= ~(UART_CTL_AUTO_RTS_EN_Msk | UART_CTL_AUTO_CTS_EN_Msk);
+}
+
+
+/**
+ * @brief The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.
+ * - \ref UART_IER_LIN_IE_Msk : LIN interrupt
+ * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt
+ * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt
+ * - \ref UART_IER_ABAUD_IE_Msk : Auto Baud-rate interrupt
+ * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt
+ * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt
+ * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt
+ * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt
+ * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt
+ * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt
+ *
+ * @return None
+ */
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag )
+{
+ uart->IER &= ~ u32InterruptFlag;
+}
+
+
+
+/**
+ * @brief The function is used to Enable UART auto flow control.
+ *
+ * @param[in] uart The base address of UART module.
+ *
+ * @return None
+ */
+void UART_EnableFlowCtrl(UART_T* uart )
+{
+ uart->MCSR |= UART_MCSR_LEV_RTS_Msk | UART_MCSR_LEV_CTS_Msk;
+ uart->CTL |= UART_CTL_AUTO_RTS_EN_Msk | UART_CTL_AUTO_CTS_EN_Msk;
+}
+
+
+/**
+ * @brief The function is used to enable UART specified interrupt and disable NVIC UART IRQ.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module:
+ * - \ref UART_IER_LIN_IE_Msk : LIN interrupt
+ * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt
+ * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt
+ * - \ref UART_IER_ABAUD_IE_Msk : Auto Baud-rate interrupt
+ * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt
+ * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt
+ * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt
+ * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt
+ * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt
+ * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt
+ *
+ * @return None
+ */
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag )
+{
+ uart->IER |= u32InterruptFlag;
+}
+
+
+/**
+ * @brief This function use to enable UART function and set baud-rate.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32baudrate The baudrate of UART module.
+ *
+ * @return None
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+ uint8_t u8UartClkSrcSel;
+ uint32_t u32ClkTbl[4] = {__HXT, __LXT, 0, __HIRC12M};
+ uint32_t u32Baud_Div;
+ uint32_t u32SrcFreq;
+ uint32_t u32SrcFreqDiv;
+
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos;
+
+ u32SrcFreq = u32ClkTbl[u8UartClkSrcSel];
+
+ u32SrcFreqDiv = (((CLK->CLKDIV0 & CLK_CLKDIV0_UART_N_Msk) >> CLK_CLKDIV0_UART_N_Pos) + 1);
+
+ if(u32SrcFreq == 0) {
+ u32SrcFreq = SysGet_PLLClockFreq() / u32SrcFreqDiv;
+ } else {
+ u32SrcFreq = u32SrcFreq / u32SrcFreqDiv;
+ }
+
+ uart->FUN_SEL = UART_FUNC_SEL_UART;
+ uart->TLCTL = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1 |
+ UART_TLCTL_RFITL_1BYTE | UART_TLCTL_RTS_TRI_LEV_1BYTE;
+
+ if(u32baudrate != 0) {
+ u32Baud_Div = UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32baudrate);
+
+ if(u32Baud_Div > 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE1 | UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32baudrate));
+ else
+ uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+ }
+}
+
+
+/**
+ * @brief The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[out] pu8RxBuf The buffer to receive the data of receive FIFO.
+ * @param[in] u32ReadBytes The the read bytes number of data.
+ *
+ * @return u32Count: Receive byte count
+ *
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count=0; u32Count < u32ReadBytes; u32Count++) {
+ u32delayno = 0;
+
+ while(uart->FSR & UART_FSR_RX_EMPTY_F_Msk) { /* Check RX empty => failed */
+ u32delayno++;
+ if( u32delayno >= 0x40000000 )
+ return FALSE;
+ }
+ pu8RxBuf[u32Count] = uart->RBR; /* Get Data from UART RX */
+ }
+
+ return u32Count;
+
+}
+
+
+/**
+ * @brief This function use to config UART line setting.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32baudrate The register value of baudrate of UART module.
+ * if u32baudrate = 0, UART baudrate will not change.
+ * @param[in] u32data_width The data length of UART module.
+ * @param[in] u32parity The parity setting (odd/even/none) of UART module.
+ * @param[in] u32stop_bits The stop bit length (1/1.5 bit) of UART module.
+ *
+ * @return None
+ */
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+ uint8_t u8UartClkSrcSel;
+ uint32_t u32ClkTbl[4] = {__HXT, __LXT, 0, __HIRC12M};
+ uint32_t u32Baud_Div = 0;
+ uint32_t u32SrcFreq;
+ uint32_t u32SrcFreqDiv;
+
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos;
+
+ u32SrcFreq = u32ClkTbl[u8UartClkSrcSel];
+
+ u32SrcFreqDiv = (((CLK->CLKDIV0 & CLK_CLKDIV0_UART_N_Msk) >> CLK_CLKDIV0_UART_N_Pos) + 1);
+
+ if(u32SrcFreq == 0) {
+ u32SrcFreq = SysGet_PLLClockFreq() / u32SrcFreqDiv;
+ } else {
+ u32SrcFreq = u32SrcFreq / u32SrcFreqDiv;
+ }
+
+ if(u32baudrate != 0) {
+ u32Baud_Div = UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32baudrate);
+
+ if(u32Baud_Div > 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE1 | UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32baudrate));
+ else
+ uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+ }
+
+ uart->TLCTL = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ * @brief This function use to set Rx timeout count.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32TOC Rx timeout counter.
+ *
+ * @return None
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+ uart->TMCTL = (uart->TMCTL & ~UART_TMCTL_TOIC_Msk)| (u32TOC);
+ uart->IER |= UART_IER_RTO_IE_Msk;
+}
+
+
+/**
+ * @brief The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32Buadrate The baudrate of UART module.
+ * @param[in] u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode.
+ *
+ * @return None
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+ uint8_t u8UartClkSrcSel;
+ uint32_t u32ClkTbl[4] = {__HXT, __LXT, 0, __HIRC12M};
+ uint32_t u32SrcFreq;
+ uint32_t u32SrcFreqDiv;
+
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART_S_Msk) >> CLK_CLKSEL1_UART_S_Pos;
+
+ u32SrcFreq = u32ClkTbl[u8UartClkSrcSel];
+
+ u32SrcFreqDiv = (((CLK->CLKDIV0 & CLK_CLKDIV0_UART_N_Msk) >> CLK_CLKDIV0_UART_N_Pos) + 1);
+
+ if(u32SrcFreq == 0) {
+ u32SrcFreq = SysGet_PLLClockFreq() / u32SrcFreqDiv;
+ } else {
+ u32SrcFreq = u32SrcFreq / u32SrcFreqDiv;
+ }
+
+ uart->BAUD = UART_BAUD_MODE1 | UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32Buadrate);
+
+ uart->IRCR &= ~UART_IRCR_INV_TX_Msk;
+ uart->IRCR |= UART_IRCR_INV_RX_Msk;
+ uart->IRCR = u32Direction ? uart->IRCR | UART_IRCR_TX_SELECT_Msk : uart->IRCR &~ UART_IRCR_TX_SELECT_Msk;
+ uart->FUN_SEL = (0x2 << UART_FUN_SEL_FUN_SEL_Pos);
+}
+
+
+/**
+ * @brief The function is used to set RS485 relative setting.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u32Mode The operation mode( \ref UART_ALT_CTL_RS485_NMM_Msk / \ref UART_ALT_CTL_RS485_AUD_Msk / \ref UART_ALT_CTL_RS485_AAD_Msk).
+ * @param[in] u32Addr The RS485 address.
+ *
+ * @return None
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+ uart->FUN_SEL = UART_FUNC_SEL_RS485;
+ uart->ALT_CTL = 0;
+ uart->ALT_CTL |= u32Mode | (u32Addr << UART_ALT_CTL_ADDR_PID_MATCH_Pos);
+}
+
+/**
+ * @brief Select and configure LIN function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Mode The LIN direction :
+ * - UART_ALT_CTL_LIN_TX_EN_Msk
+ * - UART_ALT_CTL_LIN_RX_EN_Msk
+ * - (UART_ALT_CTL_LIN_TX_EN_Msk|UART_ALT_CTL_LIN_RX_EN_Msk)
+ * @param[in] u32BreakLength The breakfield length.
+ *
+ * @return None
+ *
+ * @details The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+ /* Select LIN function mode */
+ uart->FUN_SEL = UART_FUNC_SEL_LIN;
+
+ /* Select LIN function setting : Tx enable, Rx enable and break field length */
+ uart->FUN_SEL = UART_FUNC_SEL_LIN;
+ uart->ALT_CTL &= ~(UART_ALT_CTL_LIN_TX_BCNT_Msk | UART_ALT_CTL_LIN_RX_EN_Msk | UART_ALT_CTL_LIN_TX_EN_Msk);
+ uart->ALT_CTL |= u32BreakLength & UART_ALT_CTL_LIN_TX_BCNT_Msk;
+ uart->ALT_CTL |= u32Mode;
+}
+
+/**
+ * @brief The function is to write data into TX buffer to transmit data by UART.
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
+ * @param[in] u32WriteBytes The byte number of data.
+ *
+ * @return u32Count: transfer byte count
+ */
+uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count=0; u32Count != u32WriteBytes; u32Count++) {
+ u32delayno = 0;
+ while((uart->FSR & UART_FSR_TX_EMPTY_F_Msk) == 0) { /* Wait Tx empty and Time-out manner */
+ u32delayno++;
+ if( u32delayno >= 0x40000000 )
+ return FALSE;
+ }
+ uart->THR = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
+ }
+
+ return u32Count;
+
+}
+
+
+/*@}*/ /* end of group NANO100_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_UART_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_uart.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,379 @@
+/**************************************************************************//**
+ * @file uart.h
+ * @version V1.00
+ * $Revision: 9 $
+ * $Date: 15/06/26 1:36p $
+ * @brief Nano100 Series uart control header file.
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_UART_Driver UART Driver
+ @{
+*/
+
+/** @addtogroup NANO100_UART_EXPORTED_CONSTANTS UART Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_LCR constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_WORD_LEN_5 (0) /*!< UART_TLCTL setting to set UART word length to 5 bits */
+#define UART_WORD_LEN_6 (1) /*!< UART_TLCTL setting to set UART word length to 6 bits */
+#define UART_WORD_LEN_7 (2) /*!< UART_TLCTL setting to set UART word length to 7 bits */
+#define UART_WORD_LEN_8 (3) /*!< UART_TLCTL setting to set UART word length to 8 bits */
+
+#define UART_PARITY_NONE (0x0 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as no parity */
+#define UART_PARITY_ODD (0x1 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as odd parity */
+#define UART_PARITY_EVEN (0x3 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to set UART as even parity */
+#define UART_PARITY_MARK (0x5 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to keep parity bit as '1' */
+#define UART_PARITY_SPACE (0x7 << UART_TLCTL_PBE_Pos) /*!< UART_TLCTL setting to keep parity bit as '0' */
+
+#define UART_STOP_BIT_1 (0x0 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for one stop bit */
+#define UART_STOP_BIT_1_5 (0x1 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for 1.5 stop bit when 5-bit word length */
+#define UART_STOP_BIT_2 (0x1 << UART_TLCTL_NSB_Pos) /*!< UART_TLCTL setting for two stop bit when 6, 7, 8-bit word length */
+
+#define UART_TLCTL_RFITL_1BYTE (0x0 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 1 bit */
+#define UART_TLCTL_RFITL_4BYTES (0x1 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 4 bits */
+#define UART_TLCTL_RFITL_8BYTES (0x2 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 8 bits */
+#define UART_TLCTL_RFITL_14BYTES (0x3 << UART_TLCTL_RFITL_Pos) /*!< UART_TLCTL setting to set RX FIFO Trigger Level to 14 bits */
+
+#define UART_TLCTL_RTS_TRI_LEV_1BYTE (0x0 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 1 bit */
+#define UART_TLCTL_RTS_TRI_LEV_4BYTES (0x1 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 4 bits */
+#define UART_TLCTL_RTS_TRI_LEV_8BYTES (0x2 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 8 bits */
+#define UART_TLCTL_RTS_TRI_LEV_14BYTES (0x3 << UART_TLCTL_RTS_TRI_LEV_Pos) /*!< UART_TLCTL setting to set RTS Trigger Level to 14 bits */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART RTS LEVEL TRIGGER constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MCSR_LEV_RTS_Pos) /*!< Set RTS is High Level Trigger */
+#define UART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MCSR_LEV_RTS_Pos) /*!< Set RTS is Low Level Trigger */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UA_FUNC_SEL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FUNC_SEL_UART (0x0 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set UART Function (Default) */
+#define UART_FUNC_SEL_LIN (0x1 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set LIN Function */
+#define UART_FUNC_SEL_IrDA (0x2 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set IrDA Function */
+#define UART_FUNC_SEL_RS485 (0x3 << UART_FUN_SEL_FUN_SEL_Pos) /*!< UART_FUN_SEL setting to set RS485 Function */
+
+
+/*@}*/ /* end of group NANO100_UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param None
+ *
+ * @return UART baudrate mode0 register setting value
+ *
+ */
+#define UART_BAUD_MODE0 (0)
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param None
+ *
+ * @return UART baudrate mode1 register setting value
+ *
+ */
+#define UART_BAUD_MODE1 (UART_BAUD_DIV_16_EN_Msk)
+
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param[in] u32SrcFreq UART clock frequency
+ * @param[in] u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode1 divider
+ *
+ */
+#define UART_BAUD_MODE1_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-1)
+
+/**
+ * @brief Calculate UART baudrate mode2 divider
+ *
+ * @param[in] u32SrcFreq UART clock frequency
+ * @param[in] u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode0 divider
+ */
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-1)
+
+
+/**
+ * @brief Write Data to Tx data register
+ *
+ * @param[in] uart The base address of UART module.
+ * @param[in] u8Data Data byte to transmit
+ *
+ * @return None
+ */
+#define UART_WRITE(uart, u8Data) (uart->THR = (u8Data))
+
+/**
+ * @brief Read Rx data register
+ *
+ * @param[in] uart The base address of UART module.
+ *
+ * @return The oldest data byte in RX FIFO
+ */
+#define UART_READ(uart) (uart->RBR)
+
+
+/**
+ * @brief Get Tx empty register value.
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return Tx empty register value.
+ */
+#define UART_GET_TX_EMPTY(uart) (uart->FSR & UART_FSR_TX_EMPTY_F_Msk)
+
+
+/**
+ * @brief Get Rx empty register value.
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return Rx empty register value.
+ */
+#define UART_GET_RX_EMPTY(uart) (uart->FSR & UART_FSR_RX_EMPTY_F_Msk)
+
+/**
+ * @brief Check specified uart port transmission is over.
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return TE_Flag.
+ */
+#define UART_IS_TX_EMPTY(uart) ((uart->FSR & UART_FSR_TE_F_Msk) >> UART_FSR_TE_F_Pos)
+
+
+/**
+ * @brief Wait specified uart port transmission is over
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return None
+ */
+#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FSR) & UART_FSR_TX_EMPTY_F_Msk) >> UART_FSR_TX_EMPTY_F_Pos))
+
+/**
+ * @brief Check RDA_IF is set or not
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return
+ * 0 : The number of bytes in the RX FIFO is less than the RFITL
+ * 1 : The number of bytes in the RX FIFO equals or larger than RFITL
+ */
+#define UART_IS_RX_READY(uart) ((uart->ISR & UART_ISR_RDA_IS_Msk)>>UART_ISR_RDA_IS_Pos)
+
+
+/**
+ * @brief Check TX FIFO is full or not
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return
+ * 1 = TX FIFO is full
+ * 0 = TX FIFO is not full
+ */
+#define UART_IS_TX_FULL(uart) ((uart->FSR & UART_FSR_TX_FULL_F_Msk)>>UART_FSR_TX_FULL_F_Pos)
+
+/**
+ * @brief Check RX FIFO is full or not
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return
+ * 1 = RX FIFO is full
+ * 0 = RX FIFO is not full
+ *
+ */
+#define UART_IS_RX_FULL(uart) ((uart->FSR & UART_FSR_RX_FULL_F_Msk)>>UART_FSR_RX_FULL_F_Pos)
+
+
+/**
+ * @brief Get Tx full register value
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return Tx full register value
+ */
+#define UART_GET_TX_FULL(uart) (uart->FSR & UART_FSR_TX_FULL_F_Msk)
+
+
+/**
+ * @brief Get Rx full register value
+ *
+ * @param[in] uart The base address of UART module
+ *
+ * @return Rx full register value
+ */
+#define UART_GET_RX_FULL(uart) (uart->FSR & UART_FSR_RX_FULL_F_Msk)
+
+
+/**
+ * @brief Enable specified interrupt
+ *
+ * @param[in] uart The base address of UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_IER_LIN_IE_Msk : LIN interrupt
+ * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt
+ * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt
+ * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt
+ * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt
+ * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt
+ * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt
+ * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt
+ * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt
+ *
+ * @return None
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel) (uart->IER |= (u32eIntSel))
+
+
+/**
+ * @brief Disable specified interrupt
+ *
+ * @param[in] uart The base address of UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_IER_LIN_IE_Msk : LIN interrupt
+ * - \ref UART_IER_ABAUD_IE_Msk : Auto baudrate interrupt
+ * - \ref UART_IER_WAKE_IE_Msk : Wakeup interrupt
+ * - \ref UART_IER_BUF_ERR_IE_Msk : Buffer Error interrupt
+ * - \ref UART_IER_RTO_IE_Msk : Rx time-out interrupt
+ * - \ref UART_IER_MODEM_IE_Msk : Modem interrupt
+ * - \ref UART_IER_RLS_IE_Msk : Rx Line status interrupt
+ * - \ref UART_IER_THRE_IE_Msk : Tx empty interrupt
+ * - \ref UART_IER_RDA_IE_Msk : Rx ready interrupt
+ * @return None
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel) (uart->IER &= ~ (u32eIntSel))
+
+
+/**
+ * @brief Get specified interrupt flag/status
+ *
+ * @param[in] uart The base address of UART module
+ * @param[in] u32eIntTypeFlag Interrupt Type Flag,should be
+ * - \ref UART_ISR_LIN_IS_Msk : LIN interrupt flag
+ * - \ref UART_ISR_ABAUD_IS_Msk : Auto baudrate interrupt flag
+ * - \ref UART_ISR_WAKE_IS_Msk : Wakeup interrupt flag
+ * - \ref UART_ISR_BUF_ERR_IS_Msk : Buffer Error interrupt flag
+ * - \ref UART_ISR_RTO_IS_Msk : Rx time-out interrupt flag
+ * - \ref UART_ISR_MODEM_IS_Msk : Modem interrupt flag
+ * - \ref UART_ISR_RLS_IS_Msk : Rx Line status interrupt flag
+ * - \ref UART_ISR_THRE_IS_Msk : Tx empty interrupt flag
+ * - \ref UART_ISR_RDA_IS_Msk : Rx ready interrupt flag
+ *
+ * @return
+ * 0 = The specified interrupt is not happened.
+ * 1 = The specified interrupt is happened.
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->ISR & (u32eIntTypeFlag))?1:0)
+
+
+/**
+ * @brief Set RTS pin is low
+ *
+ * @param[in] uart The base address of UART module
+ * @return None
+ */
+__INLINE void UART_CLEAR_RTS(UART_T* uart)
+{
+ uart->MCSR |= UART_MCSR_LEV_RTS_Msk;
+}
+
+/**
+ * @brief Set RTS pin is high
+ *
+ * @param[in] uart The base address of UART module
+ * @return None
+ */
+__INLINE void UART_SET_RTS(UART_T* uart)
+{
+ uart->MCSR &= ~UART_MCSR_LEV_RTS_Msk;
+}
+
+/**
+ * @brief Clear RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The base address of UART module
+ * @return None
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->TRSR |= UART_TRSR_RS485_ADDET_F_Msk)
+
+
+/**
+ * @brief Get RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The base address of UART module
+ * @return RS-485 Address Byte Detection Flag
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->TRSR & UART_TRSR_RS485_ADDET_F_Msk) >> UART_TRSR_RS485_ADDET_F_Pos)
+
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
+void UART_Close(UART_T* uart );
+void UART_DisableFlowCtrl(UART_T* uart );
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag );
+void UART_EnableFlowCtrl(UART_T* uart );
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag );
+void UART_Open(UART_T* uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
+
+
+/*@}*/ /* end of group NANO100_UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_UART_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__UART_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
+
+
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_usbd.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,526 @@
+/******************************************************************************
+ * @file usbd.c
+ * @brief NANO100 series USBD driver Sample file
+ * @version 2.0.0
+ * @date 20, September, 2014
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+
+/*!<Includes */
+#include <string.h>
+#include "Nano100Series.h"
+
+/*--------------------------------------------------------------------------*/
+/* Global variables for Control Pipe */
+uint8_t g_usbd_SetupPacket[8] = {0};
+volatile uint8_t g_usbd_RemoteWakeupEn = 0; /*!< Remote wake up function enable flag */
+
+/**
+ * @cond HIDDEN_SYMBOLS
+ */
+static volatile uint8_t *g_usbd_CtrlInPointer = 0;
+static volatile uint32_t g_usbd_CtrlInSize = 0;
+static volatile uint8_t *g_usbd_CtrlOutPointer = 0;
+static volatile uint32_t g_usbd_CtrlOutSize = 0;
+static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0;
+static volatile uint32_t g_usbd_UsbAddr = 0;
+static volatile uint32_t g_usbd_CtrlMaxPktSize = 8;
+static volatile uint32_t g_usbd_UsbAltInterface = 0;
+volatile uint32_t g_usbd_UsbConfig = 0;
+/**
+ * @endcond
+ */
+
+S_USBD_INFO_T *g_usbd_sInfo;
+
+VENDOR_REQ g_usbd_pfnVendorRequest = NULL;
+CLASS_REQ g_usbd_pfnClassRequest = NULL;
+SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL;
+uint32_t g_u32EpStallLock = 0; /*!< Bit map flag to lock specified EP when SET_FEATURE */
+
+/**
+ * @brief USBD Initial, Enable clock and reset USB.
+ * @param[in] param Descriptor
+ * @param[in] pfnClassReq Class Request Callback Function
+ * @param[in] pfnSetInterface SetInterface Request Callback Function
+ * @retval None.
+ */
+void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
+{
+ g_usbd_sInfo = param;
+ g_usbd_pfnClassRequest = pfnClassReq;
+ g_usbd_pfnSetInterface = pfnSetInterface;
+
+ /* get EP0 maximum packet size */
+ g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
+
+ /* Initial USB engine */
+ USBD->CTL = 0x29f;
+ USBD->PDMA |= USBD_PDMA_BYTEM_Msk;
+ /* Force SE0, and then clear it to connect*/
+ USBD_SET_SE0();
+}
+
+/**
+ * @brief USBD Start
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to start transfer
+ */
+void USBD_Start(void)
+{
+ /* Enable USB-related interrupts. */
+ USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+ CLK_SysTickDelay(100000);
+ USBD_CLR_SE0();
+}
+
+/**
+ * @brief Get Setup Packet
+ *
+ * @param[in] buf Buffer pointer to store setup packet
+ *
+ * @return None
+ *
+ * @details This function is used to get Setup packet.
+ */
+void USBD_GetSetupPacket(uint8_t *buf)
+{
+ USBD_MemCopy(buf, g_usbd_SetupPacket, 8);
+}
+
+/**
+ * @brief Process Setup Packet
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to process Setup packet.
+ */
+void USBD_ProcessSetupPacket(void)
+{
+ // Setup packet process
+ USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8);
+
+ switch (g_usbd_SetupPacket[0] & 0x60) { /* request type */
+ case REQ_STANDARD: { // Standard
+ USBD_StandardRequest();
+ break;
+ }
+ case REQ_CLASS: { // Class
+ if (g_usbd_pfnClassRequest != NULL) {
+ g_usbd_pfnClassRequest();
+ }
+ break;
+ }
+ case REQ_VENDOR: { // Vendor
+ if (g_usbd_pfnVendorRequest != NULL) {
+ g_usbd_pfnVendorRequest();
+ }
+ break;
+ }
+ default: { // reserved
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Get Descriptor request
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to process GetDescriptor request.
+ */
+void USBD_GetDescriptor(void)
+{
+ uint32_t u32Len;
+
+ u32Len = 0;
+ u32Len = g_usbd_SetupPacket[7];
+ u32Len <<= 8;
+ u32Len += g_usbd_SetupPacket[6];
+
+ switch (g_usbd_SetupPacket[3]) {
+ // Get Device Descriptor
+ case DESC_DEVICE: {
+ u32Len = Minimum(u32Len, LEN_DEVICE);
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
+ USBD_PrepareCtrlOut(0,0);
+ break;
+ }
+ // Get Configuration Descriptor
+ case DESC_CONFIG: {
+ uint32_t u32TotalLen;
+
+ u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
+ u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+ u32Len = Minimum(u32Len, u32TotalLen);
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
+ USBD_PrepareCtrlOut(0,0);
+ break;
+ }
+ // Get HID Descriptor
+ case DESC_HID: {
+ /* CV3.0 HID Class Descriptor Test,
+ Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
+ uint32_t u32ConfigDescOffset; // u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index)
+ u32Len = Minimum(u32Len, LEN_HID);
+ u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]];
+ USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
+ USBD_PrepareCtrlOut(0,0);
+ break;
+ }
+ // Get Report Descriptor
+ case DESC_HID_RPT: {
+ u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]);
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len);
+ USBD_PrepareCtrlOut(0,0);
+ break;
+ }
+ // Get String Descriptor
+ case DESC_STRING: {
+ // Get String Descriptor
+ if(g_usbd_SetupPacket[2] < 4) {
+ u32Len = Minimum(u32Len, g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]);
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len);
+ USBD_PrepareCtrlOut(0, 0);
+ } else {
+ // Not support. Reply STALL.
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ }
+ break;
+ }
+ default:
+ // Not support. Reply STALL.
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+}
+
+/**
+ * @brief Process USB standard request
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to process USB Standard Request.
+ */
+void USBD_StandardRequest(void)
+{
+ /* clear global variables for new request */
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+
+ if (g_usbd_SetupPacket[0] & 0x80) { /* request data transfer direction */
+ // Device to host
+ switch (g_usbd_SetupPacket[1]) {
+ case GET_CONFIGURATION: {
+ // Return current configuration setting
+ /* Data stage */
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbConfig;
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 1);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0,0);
+ break;
+ }
+ case GET_DESCRIPTOR: {
+ USBD_GetDescriptor();
+ break;
+ }
+ case GET_INTERFACE: {
+ // Return current interface setting
+ /* Data stage */
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbAltInterface;
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 1);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0,0);
+ break;
+ }
+ case GET_STATUS: {
+ // Device
+ if(g_usbd_SetupPacket[0] == 0x80) {
+ uint8_t u8Tmp;
+
+ u8Tmp = 0;
+ if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x40) u8Tmp |= 1; // Self-Powered/Bus-Powered.
+ if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x20) u8Tmp |= (g_usbd_RemoteWakeupEn << 1); // Remote wake up
+
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp;
+ }
+ // Interface
+ else if (g_usbd_SetupPacket[0] == 0x81)
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = 0;
+ // Endpoint
+ else if (g_usbd_SetupPacket[0] == 0x82) {
+ uint8_t ep = g_usbd_SetupPacket[4] & 0xF;
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = USBD_GetStall(ep)? 1 : 0;
+ }
+
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = 0;
+ /* Data stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 2);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0,0);
+ break;
+ }
+ default: {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+ } else {
+ // Host to device
+ switch (g_usbd_SetupPacket[1]) {
+ case CLEAR_FEATURE: {
+ if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) {
+
+ int32_t epNum, i;
+
+ /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+ a flag: g_u32EpStallLock is added to support it */
+ epNum = g_usbd_SetupPacket[4] & 0xF;
+ for(i = 0; i < USBD_MAX_EP; i++) {
+ if(((USBD->EP[i].CFG & 0xF) == epNum) && ((g_u32EpStallLock & (1 << i)) == 0))
+ USBD->EP[i].CFG &= ~(USBD_CFG_SSTALL_Msk | USBD_CFG_DSQ_SYNC_Msk);
+ }
+ } else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+ g_usbd_RemoteWakeupEn = 0;
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+ break;
+ }
+ case SET_ADDRESS: {
+ g_usbd_UsbAddr = g_usbd_SetupPacket[2];
+
+ // DATA IN for end of setup
+ /* Status Stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+ break;
+ }
+ case SET_CONFIGURATION: {
+ g_usbd_UsbConfig = g_usbd_SetupPacket[2];
+
+ if (g_usbd_UsbConfig == 0) {
+ int volatile i;
+ /* Reset PID DATA0 */
+ for (i=2; i<USBD_MAX_EP; i++)
+ USBD->EP[i].CFG &= ~USBD_CFG_DSQ_SYNC_Msk;
+ }
+ // DATA IN for end of setup
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+ break;
+ }
+ case SET_FEATURE: {
+ if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+ USBD_SetStall(g_usbd_SetupPacket[4] & 0xF);
+ else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+ g_usbd_RemoteWakeupEn = 1;
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+ break;
+ }
+ case SET_INTERFACE: {
+ g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
+ if (g_usbd_pfnSetInterface != NULL)
+ g_usbd_pfnSetInterface(g_usbd_UsbAltInterface);
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+ break;
+ }
+ default: {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * @brief Prepare Control IN transaction
+ *
+ * @param[in] pu8Buf Control IN data pointer
+ * @param[in] u32Size IN transfer size
+ *
+ * @return None
+ *
+ * @details This function is used to prepare Control IN transfer
+ */
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size)
+{
+ if(u32Size > g_usbd_CtrlMaxPktSize) {
+ // Data size > MXPLD
+ g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize;
+ g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize;
+ USBD_SET_DATA1(EP0);
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, g_usbd_CtrlMaxPktSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+ } else {
+ // Data size <= MXPLD
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+ USBD_SET_DATA1(EP0);
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size);
+ USBD_SET_PAYLOAD_LEN(EP0, u32Size);
+ }
+}
+
+/**
+ * @brief Start Control IN transfer
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to start Control IN
+ */
+void USBD_CtrlIn(void)
+{
+ if(g_usbd_CtrlInSize) {
+ // Process remained data
+ if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) {
+ // Data size > MXPLD
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+ g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize;
+ g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
+ } else {
+ // Data size <= MXPLD
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize);
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+ }
+ } else {
+ // In ACK for Set address
+ if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) {
+ if((USBD_GET_ADDR() != g_usbd_UsbAddr) && (USBD_GET_ADDR() == 0)) {
+ USBD_SET_ADDR(g_usbd_UsbAddr);
+ }
+ }
+
+ // No more data for IN token
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+ }
+}
+
+/**
+ * @brief Prepare Control OUT transaction
+ *
+ * @param[in] pu8Buf Control OUT data pointer
+ * @param[in] u32Size OUT transfer size
+ *
+ * @return None
+ *
+ * @details This function is used to prepare Control OUT transfer
+ */
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
+{
+ g_usbd_CtrlOutPointer = pu8Buf;
+ g_usbd_CtrlOutSize = 0;
+ g_usbd_CtrlOutSizeLimit = u32Size;
+ USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+}
+
+/**
+ * @brief Start Control OUT transfer
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to start Control OUT
+ */
+void USBD_CtrlOut(void)
+{
+ uint32_t u32Size;
+
+ if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) {
+ u32Size = USBD_GET_PAYLOAD_LEN(EP1);
+ USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size);
+ g_usbd_CtrlOutPointer += u32Size;
+ g_usbd_CtrlOutSize += u32Size;
+ }
+}
+
+/**
+ * @brief Clear all software flags
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to clear all software control flag
+ */
+void USBD_SwReset(void)
+{
+ int i;
+
+ // Reset all variables for protocol
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+ g_usbd_CtrlOutPointer = 0;
+ g_usbd_CtrlOutSize = 0;
+ g_usbd_CtrlOutSizeLimit = 0;
+ memset(g_usbd_SetupPacket, 0, 8);
+
+ /* Reset PID DATA0 */
+ for (i=0; i<USBD_MAX_EP; i++)
+ USBD->EP[i].CFG &= ~USBD_CFG_DSQ_SYNC_Msk;
+
+ // Reset USB device address
+ USBD_SET_ADDR(0);
+}
+
+
+/**
+ * @brief USBD Set Vendor Request
+ *
+ * @param[in] pfnVendorReq Vendor Request Callback Function
+ *
+ * @return None
+ *
+ * @details This function is used to set USBD vendor request callback function
+ */
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
+{
+ g_usbd_pfnVendorRequest = pfnVendorReq;
+}
+
+
+void USBD_LockEpStall(uint32_t u32EpBitmap)
+{
+ g_u32EpStallLock = u32EpBitmap;
+}
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_usbd.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,507 @@
+/******************************************************************************
+ * @file usbd.h
+ * @brief NANO100 series USB driver header file
+ * @version 2.0.0
+ * @date 20, September, 2014
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __USBD_H__
+#define __USBD_H__
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_USBD_Driver USBD Driver
+ @{
+*/
+
+/** @addtogroup NANO100_USBD_EXPORTED_STRUCTS USBD Exported Structs
+ @{
+*/
+typedef struct s_usbd_info {
+ uint8_t *gu8DevDesc; /*!< Device descriptor */
+ uint8_t *gu8ConfigDesc; /*!< Config descriptor */
+ uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
+ uint8_t **gu8HidReportDesc; /*!< Pointer for HID Report descriptor */
+ uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
+ uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
+} S_USBD_INFO_T;
+
+/// @cond HIDDEN_SYMBOLS
+extern S_USBD_INFO_T gsInfo;
+/// @endcond /* HIDDEN_SYMBOLS */
+
+/*@}*/ /* end of group NANO100_USBD_EXPORTED_STRUCTS */
+
+/** @addtogroup NANO100_USBD_EXPORTED_CONSTANTS USBD Exported Constants
+ @{
+*/
+#define USBD_BUF_BASE (USBD_BASE+0x100)
+
+#define USBD_MAX_EP 8
+
+#define EP0 0 /*!< Endpoint 0 */
+#define EP1 1 /*!< Endpoint 1 */
+#define EP2 2 /*!< Endpoint 2 */
+#define EP3 3 /*!< Endpoint 3 */
+#define EP4 4 /*!< Endpoint 4 */
+#define EP5 5 /*!< Endpoint 5 */
+#define EP6 6 /*!< Endpoint 6 */
+#define EP7 7 /*!< Endpoint 7 */
+
+/// @cond HIDDEN_SYMBOLS
+extern volatile uint32_t g_usbd_UsbConfig;
+
+/*!<USB Request Type */
+#define REQ_STANDARD 0x00
+#define REQ_CLASS 0x20
+#define REQ_VENDOR 0x40
+
+/*!<USB Standard Request */
+#define GET_STATUS 0x00
+#define CLEAR_FEATURE 0x01
+#define SET_FEATURE 0x03
+#define SET_ADDRESS 0x05
+#define GET_DESCRIPTOR 0x06
+#define SET_DESCRIPTOR 0x07
+#define GET_CONFIGURATION 0x08
+#define SET_CONFIGURATION 0x09
+#define GET_INTERFACE 0x0A
+#define SET_INTERFACE 0x0B
+#define SYNC_FRAME 0x0C
+
+/*!<USB Descriptor Type */
+#define DESC_DEVICE 0x01
+#define DESC_CONFIG 0x02
+#define DESC_STRING 0x03
+#define DESC_INTERFACE 0x04
+#define DESC_ENDPOINT 0x05
+#define DESC_QUALIFIER 0x06
+#define DESC_OTHERSPEED 0x07
+
+/*!<USB HID Descriptor Type */
+#define DESC_HID 0x21
+#define DESC_HID_RPT 0x22
+
+/*!<USB Descriptor Length */
+#define LEN_DEVICE 18
+#define LEN_CONFIG 9
+#define LEN_INTERFACE 9
+#define LEN_ENDPOINT 7
+#define LEN_HID 9
+#define LEN_CCID 0x36
+
+/*!<USB Endpoint Type */
+#define EP_ISO 0x01
+#define EP_BULK 0x02
+#define EP_INT 0x03
+
+#define EP_INPUT 0x80
+#define EP_OUTPUT 0x00
+
+/*!<USB Feature Selector */
+#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01
+#define FEATURE_ENDPOINT_HALT 0x00
+
+/// @endcond
+
+#define USBD_WAKEUP_EN USBD_CTL_WAKEUP_EN_Msk /*!< USB Wake-up Enable */
+#define USBD_DRVSE0 USBD_CTL_DRVSE0_Msk /*!< Drive SE0 */
+
+#define USBD_DPPU_EN USBD_CTL_DPPU_EN_Msk /*!< USB D+ Pull-up Enable */
+#define USBD_PWRDN USBD_CTL_PWRDB_Msk /*!< PHY Turn-On */
+#define USBD_PHY_EN USBD_CTL_PHY_EN_Msk /*!< PHY Enable */
+#define USBD_USB_EN USBD_CTL_USB_EN_Msk /*!< USB Enable */
+
+#define USBD_INT_BUS USBD_INTEN_BUSEVT_IE_Msk /*!< USB Bus Event Interrupt */
+#define USBD_INT_USB USBD_INTEN_USBEVT_IE_Msk /*!< USB usb Event Interrupt */
+#define USBD_INT_FLDET USBD_INTEN_FLDET_IE_Msk /*!< USB Float Detect Interrupt */
+#define USBD_INT_WAKEUP USBD_INTEN_WAKEUP_IE_Msk /*!< USB Wake-up Interrupt */
+
+#define USBD_INTSTS_WAKEUP USBD_INTSTS_WKEUP_STS_Msk /*!< USB Wakeup Interrupt Status */
+#define USBD_INTSTS_FLDET USBD_INTSTS_FLD_STS_Msk /*!< USB Float Detect Interrupt Status */
+#define USBD_INTSTS_BUS USBD_INTSTS_BUS_STS_Msk /*!< USB Bus Event Interrupt Status */
+#define USBD_INTSTS_USB USBD_INTSTS_USB_STS_Msk /*!< USB usb Event Interrupt Status */
+#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event */
+#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event */
+#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event */
+#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event */
+#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event */
+#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event */
+#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event */
+#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event */
+#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event */
+
+#define USBD_STATE_USBRST USBD_BUSSTS_USBRST_Msk /*!< USB Bus Reset */
+#define USBD_STATE_SUSPEND USBD_BUSSTS_SUSPEND_Msk /*!< USB Bus Suspend */
+#define USBD_STATE_RESUME USBD_BUSSTS_RESUME_Msk /*!< USB Bus Resume */
+#define USBD_STATE_TIMEOUT USBD_BUSSTS_TIMEOUT_Msk /*!< USB Bus Timeout */
+
+#define USBD_CFG_SSTALL USBD_CFG_SSTALL_Msk /*!< Set Stall */
+#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */
+
+#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_EPMODE_Pos)/*!< Endpoint Disable */
+#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_EPMODE_Pos)/*!< Out Endpoint */
+#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_EPMODE_Pos)/*!< In Endpoint */
+#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous */
+
+
+/*@}*/ /* end of group NANO100_USBD_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+ @{
+*/
+
+/**
+ * @brief Compare two input numbers and return maximum one.
+ *
+ * @param[in] a First number to be compared.
+ * @param[in] b Second number to be compared.
+ *
+ * @return Maximum value between a and b.
+ *
+ * @details If a > b, then return a. Otherwise, return b.
+ */
+#define Maximum(a,b) ((a)>(b) ? (a) : (b))
+
+
+/**
+ * @brief Compare two input numbers and return minimum one
+ *
+ * @param[in] a First number to be compared
+ * @param[in] b Second number to be compared
+ *
+ * @return Minimum value between a and b
+ *
+ * @details If a < b, then return a. Otherwise, return b.
+ */
+#define Minimum(a,b) ((a)<(b) ? (a) : (b))
+
+/**
+ * @brief Enable USBD engine
+ * @param None
+ * @retval None
+ */
+#define USBD_ENABLE_USB() ((uint32_t)(USBD->CTL |= 0xF))
+
+/**
+ * @brief Disable USBD engine
+ * @param None
+ * @retval None
+ */
+#define USBD_DISABLE_USB() ((uint32_t)(USBD->CTL &= ~USBD_USB_EN))
+
+/**
+ * @brief Enable USBD PHY
+ * @param None
+ * @retval None
+ */
+#define USBD_ENABLE_PHY() ((uint32_t)(USBD->CTL |= USBD_PHY_EN))
+
+/**
+ * @brief Disable USBD PHY
+ * @param None
+ * @retval None
+ */
+#define USBD_DISABLE_PHY() ((uint32_t)(USBD->CTL &= ~USBD_PHY_EN))
+
+/**
+ * @brief Force USB PHY Transceiver to Drive SE0
+ * @param None
+ * @retval None
+ */
+#define USBD_SET_SE0() ((uint32_t)(USBD->CTL |= USBD_DRVSE0))
+
+/**
+ * @brief Release SE0
+ * @param None
+ * @retval None
+ */
+#define USBD_CLR_SE0() ((uint32_t)(USBD->CTL &= ~USBD_DRVSE0))
+
+/**
+ * @brief Set USBD address
+ * @param[in] addr host assign address number
+ * @retval None
+ */
+#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
+
+/**
+ * @brief Get USBD address
+ * @param None
+ * @retval USBD address
+ */
+#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
+
+/**
+ * @brief Enable USBD interrupt
+ * @param[in] intr interrupt mask
+ * @retval None
+ */
+#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
+
+/**
+ * @brief Get USBD interrupt flag
+ * @param None
+ * @retval interrupt status
+ */
+#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
+
+/**
+ * @brief Clear USBD interrupt
+ * @param[in] flag interrupt flag
+ * @retval None
+ */
+#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = flag)
+
+/**
+ * @brief Get USBD Endpoint status
+ * @param None
+ * @retval endpoint status
+ */
+#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
+
+/**
+ * @brief Get USBD bus state
+ * @param None
+ * @retval bus status
+ */
+#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->BUSSTS & 0xf))
+
+/**
+ * @brief check cable connect state
+ * @param None
+ * @retval connect / disconnect
+ */
+#define USBD_IS_ATTACHED() ((uint32_t)(USBD->BUSSTS & USBD_BUSSTS_FLDET_Msk))
+
+/**
+ * @brief Stop USB endpoint transaction
+ * @param[in] ep endpoint
+ * @retval None
+ */
+#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_CLRRDY_Msk)
+
+/**
+ * @brief Set USB data1 token
+ * @param[in] ep endpoint
+ * @retval None
+ */
+#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQ_SYNC_Msk)
+
+/**
+ * @brief Set USB data0 token
+ * @param[in] ep endpoint
+ * @retval None
+ */
+#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQ_SYNC_Msk))
+
+/**
+ * @brief Set USB payload size (IN data)
+ * @param[in] ep endpoint
+ * @param[in] size IN transfer length
+ * @retval None
+ */
+#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
+
+/**
+ * @brief Get USB payload size (OUT data)
+ * @param[in] ep endpoint
+ * @retval received data length
+ */
+#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
+
+/**
+ * @brief config endpoint
+ * @param[in] ep endpoint
+ * @param[in] config config value
+ * @retval None
+ */
+#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
+
+/**
+ * @brief Set buffer for USB endpoint
+ * @param[in] ep endpoint
+ * @param[in] offset buffer offset
+ * @retval None
+ */
+#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
+
+/**
+ * @brief Get buffer for USB endpoint
+ * @param[in] ep endpoint
+ * @retval buffer offset
+ */
+#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
+
+/**
+ * @brief Set USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID.
+ *
+ * @return None
+ *
+ * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+ *
+ */
+#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_SSTALL_Msk)
+
+/**
+ * @brief Clear USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID.
+ *
+ * @return None
+ *
+ * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+ */
+#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= ~USBD_CFG_SSTALL_Msk)
+
+/**
+ * @brief Get USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID.
+ *
+ * @retval 0 USB endpoint is not stalled.
+ * @retval Others USB endpoint is stalled.
+ *
+ * @details Get USB endpoint stall state of the specified endpoint ID.
+ *
+ */
+#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_SSTALL_Msk)
+
+/**
+ * @brief To support byte access between USB SRAM and system SRAM
+ *
+ * @param[in] dest Destination pointer.
+ *
+ * @param[in] src Source pointer.
+ *
+ * @param[in] size Byte count.
+ *
+ * @return None
+ *
+ * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
+ *
+ */
+static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size)
+{
+ while (size--) *dest++ = *src++;
+}
+
+
+/**
+ * @brief Set USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ * @return None
+ *
+ * @details Set USB endpoint stall state, endpoint will return STALL token.
+ */
+static __INLINE void USBD_SetStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ int i;
+
+ for (i=0; i<USBD_MAX_EP; i++) {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
+
+ if((u32Cfg & 0xf) == epnum) {
+ *((__IO uint32_t *) (u32CfgAddr)) = (u32Cfg | USBD_CFG_SSTALL);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Clear USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ * @return None
+ *
+ * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token.
+ */
+static __INLINE void USBD_ClearStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ int i;
+
+ for (i=0; i<USBD_MAX_EP; i++) {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
+
+ if((u32Cfg & 0xf) == epnum) {
+ *((__IO uint32_t *) (u32CfgAddr)) = (u32Cfg & ~USBD_CFG_SSTALL);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Get USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ * @retval 0 USB endpoint is not stalled.
+ * @retval non-0 USB endpoint is stalled.
+ *
+ * @details Get USB endpoint stall state.
+ */
+static __INLINE uint32_t USBD_GetStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ int i;
+
+ for (i=0; i<USBD_MAX_EP; i++) {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
+
+ if((u32Cfg & 0xf) == epnum)
+ break;
+ }
+ return (u32Cfg & USBD_CFG_SSTALL);
+}
+
+
+/*--------------------------------------------------------------------*/
+extern volatile uint8_t g_usbd_RemoteWakeupEn;
+
+typedef void (*VENDOR_REQ)(void); /*!<USB Vendor request callback function */
+
+typedef void (*CLASS_REQ)(void); /*!<USB Class request callback function */
+
+typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!<USB Standard request "Set Interface" callback function */
+
+/*--------------------------------------------------------------------*/
+void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
+void USBD_Start(void);
+void USBD_GetSetupPacket(uint8_t *buf);
+void USBD_ProcessSetupPacket(void);
+void USBD_StandardRequest(void);
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlIn(void);
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlOut(void);
+void USBD_SwReset(void);
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
+void USBD_LockEpStall(uint32_t u32EpBitmap);
+
+
+/*@}*/ /* end of group NANO100_USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_USBD_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+
+#endif //__USBD_H__
+
+/*** (C) COPYRIGHT 2013~2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_wdt.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,65 @@
+/**************************************************************************//**
+ * @file wdt.c
+ * @version V1.00
+ * $Revision: 2 $
+ * $Date: 15/03/18 5:37p $
+ * @brief Nano100 series WDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_WDT_Driver WDT Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make WDT module start counting with different time-out interval
+ * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
+ * - \ref WDT_TIMEOUT_2POW4
+ * - \ref WDT_TIMEOUT_2POW6
+ * - \ref WDT_TIMEOUT_2POW8
+ * - \ref WDT_TIMEOUT_2POW10
+ * - \ref WDT_TIMEOUT_2POW12
+ * - \ref WDT_TIMEOUT_2POW14
+ * - \ref WDT_TIMEOUT_2POW16
+ * - \ref WDT_TIMEOUT_2POW18
+ * @param[in] u32ResetDelay Reset delay period while WDT time-out happened. Valid values are:
+ * - \ref WDT_RESET_DELAY_3CLK
+ * - \ref WDT_RESET_DELAY_18CLK
+ * - \ref WDT_RESET_DELAY_130CLK
+ * - \ref WDT_RESET_DELAY_1026CLK
+ * @param[in] u32EnableReset Enable WDT reset system function. Valid values are TRUE and FALSE
+ * @param[in] u32EnableWakeup Enable WDT wake-up system function. Valid values are TRUE and FALSE
+ * @return None
+ */
+void WDT_Open(uint32_t u32TimeoutInterval,
+ uint32_t u32ResetDelay,
+ uint32_t u32EnableReset,
+ uint32_t u32EnableWakeup)
+{
+
+ WDT->CTL = u32TimeoutInterval | u32ResetDelay | WDT_CTL_WTE_Msk |
+ (u32EnableReset << WDT_CTL_WTRE_Pos) |
+ (u32EnableWakeup << WDT_CTL_WTWKE_Pos);
+ return;
+}
+
+
+/*@}*/ /* end of group NANO100_WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_WDT_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_wdt.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,161 @@
+/**************************************************************************//**
+ * @file wdt.h
+ * @version V1.00
+ * $Revision: 4 $
+ * $Date: 14/08/29 7:56p $
+ * @brief Nano100 series WDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_H__
+#define __WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_WDT_Driver WDT Driver
+ @{
+*/
+
+/** @addtogroup NANO100_WDT_EXPORTED_CONSTANTS WDT Exported Constants
+ @{
+*/
+#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^4 * WDT clocks */
+#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^6 * WDT clocks */
+#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^8 * WDT clocks */
+#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^10 * WDT clocks */
+#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^12 * WDT clocks */
+#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^14 * WDT clocks */
+#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^16 * WDT clocks */
+#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_WTIS_Pos) /*!< WDT setting for timeout interval = 2^18 * WDT clocks */
+
+#define WDT_RESET_DELAY_3CLK (3UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 3 WDT clocks */
+#define WDT_RESET_DELAY_18CLK (2UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 18 WDT clocks */
+#define WDT_RESET_DELAY_130CLK (1UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 130 WDT clocks */
+#define WDT_RESET_DELAY_1026CLK (0UL << WDT_CTL_WTRDSEL_Pos) /*!< WDT setting reset delay to 1026 WDT clocks */
+
+/*@}*/ /* end of group NANO100_WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro clear WDT time-out reset system flag.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define WDT_CLEAR_RESET_FLAG() (WDT->ISR = WDT_ISR_RST_IS_Msk)
+
+/**
+ * @brief This macro clear WDT time-out interrupt flag.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->ISR = WDT_ISR_IS_Msk)
+
+/**
+ * @brief This macro clear WDT time-out wake-up system flag.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->ISR = WDT_ISR_WAKE_IS_Msk)
+
+/**
+ * @brief This macro indicate WDT time-out to reset system or not.
+ * @return WDT reset system or not
+ * @retval 0 WDT did not cause system reset
+ * @retval 1 WDT caused system reset
+ * \hideinitializer
+ */
+#define WDT_GET_RESET_FLAG() (WDT->ISR & WDT_ISR_RST_IS_Msk ? 1 : 0)
+
+/**
+ * @brief This macro indicate WDT time-out interrupt occurred or not.
+ * @return WDT time-out interrupt occurred or not
+ * @retval 0 WDT time-out interrupt did not occur
+ * @retval 1 WDT time-out interrupt occurred
+ * \hideinitializer
+ */
+#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->ISR & WDT_ISR_IS_Msk ? 1 : 0)
+
+/**
+ * @brief This macro indicate WDT time-out waked system up or not
+ * @return WDT time-out waked system up or not
+ * @retval 0 WDT did not wake up system
+ * @retval 1 WDT waked up system
+ * \hideinitializer
+ */
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->ISR & WDT_ISR_WAKE_IS_Msk ? 1 : 0)
+
+/**
+ * @brief This macro is used to reset 18-bit WDT counter.
+ * @details If WDT is activated and enabled to reset system, software must reset WDT counter
+ * before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
+ * \hideinitializer
+ */
+#define WDT_RESET_COUNTER() (WDT->CTL |= WDT_CTL_WTR_Msk)
+
+/**
+ * @brief This function stops WDT counting and disable WDT module
+ * @param None
+ * @return None
+ */
+__STATIC_INLINE void WDT_Close(void)
+{
+ WDT->CTL = 0;
+ return;
+}
+
+/**
+ * @brief This function enables the WDT time-out interrupt
+ * @param None
+ * @return None
+ */
+__STATIC_INLINE void WDT_EnableInt(void)
+{
+ WDT->IER = WDT_IER_IE_Msk;
+ return;
+}
+
+/**
+ * @brief This function disables the WDT time-out interrupt
+ * @param None
+ * @return None
+ */
+__STATIC_INLINE void WDT_DisableInt(void)
+{
+ WDT->IER = 0;
+ return;
+}
+
+void WDT_Open(uint32_t u32TimeoutInterval,
+ uint32_t u32ResetDelay,
+ uint32_t u32EnableReset,
+ uint32_t u32EnableWakeup);
+
+/*@}*/ /* end of group NANO100_WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_WDT_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WDT_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_wwdt.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,66 @@
+/**************************************************************************//**
+ * @file wwdt.c
+ * @version V1.00
+ * $Revision: 3 $
+ * $Date: 14/08/29 7:57p $
+ * @brief Nano100 series WWDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "Nano100Series.h"
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_WWDT_Driver WWDT Driver
+ @{
+*/
+
+
+/** @addtogroup NANO100_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make WWDT module start counting with different counter period and compared window value
+ * @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are:
+ * - \ref WWDT_PRESCALER_1
+ * - \ref WWDT_PRESCALER_2
+ * - \ref WWDT_PRESCALER_4
+ * - \ref WWDT_PRESCALER_8
+ * - \ref WWDT_PRESCALER_16
+ * - \ref WWDT_PRESCALER_32
+ * - \ref WWDT_PRESCALER_64
+ * - \ref WWDT_PRESCALER_128
+ * - \ref WWDT_PRESCALER_192
+ * - \ref WWDT_PRESCALER_256
+ * - \ref WWDT_PRESCALER_384
+ * - \ref WWDT_PRESCALER_512
+ * - \ref WWDT_PRESCALER_768
+ * - \ref WWDT_PRESCALER_1024
+ * - \ref WWDT_PRESCALER_1536
+ * - \ref WWDT_PRESCALER_2048
+ * @param[in] u32CmpValue Window compared value. Valid values are between 0x0 to 0x3F
+ * @param[in] u32EnableInt Enable WWDT interrupt or not. Valid values are TRUE and FALSE
+ * @return None
+ * @note Application can call this function can only once after boot up
+ */
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt)
+{
+ WWDT->IER = u32EnableInt;
+ WWDT->CR = u32PreScale | (u32CmpValue << WWDT_CR_WINCMP_Pos) | WWDT_CR_WWDTEN_Msk;
+ return;
+}
+
+
+
+
+/*@}*/ /* end of group NANO100_WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_WDT_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_wwdt.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,125 @@
+/**************************************************************************//**
+ * @file wwdt.h
+ * @version V1.00
+ * $Revision: 2 $
+ * $Date: 14/01/14 5:38p $
+ * @brief Nano100 series WWDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_H__
+#define __WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
+ @{
+*/
+
+/** @addtogroup NANO100_WWDT_Driver WWDT Driver
+ @{
+*/
+
+/** @addtogroup NANO100_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+ @{
+*/
+#define WWDT_PRESCALER_1 (0UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1 */
+#define WWDT_PRESCALER_2 (1UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 2 */
+#define WWDT_PRESCALER_4 (2UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 4 */
+#define WWDT_PRESCALER_8 (3UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 8 */
+#define WWDT_PRESCALER_16 (4UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 16 */
+#define WWDT_PRESCALER_32 (5UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 32 */
+#define WWDT_PRESCALER_64 (6UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 64 */
+#define WWDT_PRESCALER_128 (7UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 128 */
+#define WWDT_PRESCALER_192 (8UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 192 */
+#define WWDT_PRESCALER_256 (9UL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 256 */
+#define WWDT_PRESCALER_384 (0xAUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 384 */
+#define WWDT_PRESCALER_512 (0xBUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 512 */
+#define WWDT_PRESCALER_768 (0xCUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 768 */
+#define WWDT_PRESCALER_1024 (0xDUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1024 */
+#define WWDT_PRESCALER_1536 (0xEUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 1536 */
+#define WWDT_PRESCALER_2048 (0xFUL << WWDT_CR_PERIODSEL_Pos) /*!< WWDT setting prescaler to 2048 */
+
+#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to RLD register to reload WWDT counter */
+/*@}*/ /* end of group NANO100_WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup NANO100_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro clear WWDT time-out reset system flag.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define WWDT_CLEAR_RESET_FLAG() (WWDT->STS = WWDT_STS_RF_Msk)
+
+/**
+ * @brief This macro clears WWDT compare match interrupt flag.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define WWDT_CLEAR_INT_FLAG() (WWDT->STS = WWDT_STS_IF_Msk)
+
+/**
+ * @brief This macro is use to get WWDT time-out reset system flag.
+ * @return WWDT reset system or not
+ * @retval 0 WWDT did not cause system reset
+ * @retval 1 WWDT caused system reset
+ * \hideinitializer
+ */
+#define WWDT_GET_RESET_FLAG() (WWDT->STS & WWDT_STS_RF_Msk ? 1 : 0)
+
+/**
+ * @brief This macro is used to indicate WWDT compare match interrupt flag.
+ * @return WWDT compare match interrupt occurred or not
+ * @retval 0 WWDT compare match interrupt did not occur
+ * @retval 1 WWDT compare match interrupt occurred
+ * \hideinitializer
+ */
+#define WWDT_GET_INT_FLAG() (WWDT->STS & WWDT_STS_IF_Msk ? 1 : 0)
+
+/**
+ * @brief This macro to reflects current WWDT counter value
+ * @param None
+ * @return Return current WWDT counter value
+ * \hideinitializer
+ */
+#define WWDT_GET_COUNTER() (WWDT->VAL)
+
+/**
+ * @brief This macro is used to reload the WWDT counter value to 0x3F.
+ * @param None
+ * @return None
+ * @details After WWDT enabled, application must reload WWDT counter while
+ * current counter is less than compare value and larger than 0,
+ * otherwise WWDT will cause system reset.
+ * \hideinitializer
+ */
+#define WWDT_RELOAD_COUNTER() (WWDT->RLD = WWDT_RELOAD_WORD)
+
+
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+
+/*@}*/ /* end of group NANO100_WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group NANO100_WWDT_Driver */
+
+/*@}*/ /* end of group NANO100_Device_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WWDT_H__
+
+/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,25 @@
+
+LR_IROM1 0x00000000 {
+ ER_IROM1 0x00000000 { ; load address = execution address
+ *(RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
+ ; uvisor-lib.a (+RW +ZI)
+ ;}
+
+ ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
+ }
+
+ RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x4000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
+ }
+}
+ScatterAssert(LoadLimit(LR_IROM1) <= 0x00020000) ; 128 KB APROM
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20004000) ; 16 KB SRAM
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+
+ struct __initial_stackheap r;
+ r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+ r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/NANO130.sct Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,25 @@
+
+LR_IROM1 0x00000000 {
+ ER_IROM1 0x00000000 { ; load address = execution address
+ *(RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
+ ; uvisor-lib.a (+RW +ZI)
+ ;}
+
+ ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
+ }
+
+ RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x4000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
+ }
+}
+ScatterAssert(LoadLimit(LR_IROM1) <= 0x00020000) ; 128 KB APROM
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20004000) ; 16 KB SRAM
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+
+ struct __initial_stackheap r;
+ r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+ r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/NANO130.ld Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,246 @@
+/*
+ * Nuvoton NANO130 GCC linker script file
+ */
+
+StackSize = 0x600;
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00020000 - 0x00000400
+ RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 - 0x00000000
+}
+
+/**
+ * Must match cmsis_nvic.h
+ */
+__vector_size = 4 * (16 + 32);
+
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ . = ALIGN(4);
+ } > VECTORS
+
+ /* ensure that uvisor bss is at the beginning of memory */
+ .uvisor.bss (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uvisor_bss_start = .;
+
+ /* protected uvisor main bss */
+ . = ALIGN(32);
+ __uvisor_bss_main_start = .;
+ KEEP(*(.keep.uvisor.bss.main))
+ . = ALIGN(32);
+ __uvisor_bss_main_end = .;
+
+ /* protected uvisor secure boxes bss */
+ . = ALIGN(32);
+ __uvisor_bss_boxes_start = .;
+ KEEP(*(.keep.uvisor.bss.boxes))
+ . = ALIGN(32);
+ __uvisor_bss_boxes_end = .;
+
+ /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
+ . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
+ __uvisor_bss_end = .;
+ } > RAM_INTERN
+
+ .text :
+ {
+ /* uVisor code and data */
+ . = ALIGN(4);
+ __uvisor_main_start = .;
+ *(.uvisor.main)
+ __uvisor_main_end = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ .ARM.exidx :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > FLASH
+
+ /* .stack section doesn't contains any symbols. It is only
+ * used for linker to reserve space for the main stack section
+ * WARNING: .stack should come immediately after the last secure memory
+ * section. This provides stack overflow detection. */
+ .stack (NOLOAD):
+ {
+ __StackLimit = .;
+ *(.stack*);
+ . += StackSize - (. - __StackLimit);
+ } > RAM_INTERN
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ADDR(.stack) + SIZEOF(.stack);
+ __StackLimit = ADDR(.stack);
+ PROVIDE(__stack = __StackTop);
+
+ .data :
+ {
+ PROVIDE( __etext = LOADADDR(.data) );
+
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ /* All data end */
+ . = ALIGN(32);
+ __data_end__ = .;
+
+ } >RAM_INTERN AT>FLASH
+
+ /* uvisor configuration data */
+ .uvisor.secure :
+ {
+ . = ALIGN(32);
+ __uvisor_secure_start = .;
+
+ /* uvisor secure boxes configuration tables */
+ . = ALIGN(32);
+ __uvisor_cfgtbl_start = .;
+ KEEP(*(.keep.uvisor.cfgtbl))
+ . = ALIGN(32);
+ __uvisor_cfgtbl_end = .;
+
+ /* pointers to uvisor secure boxes configuration tables */
+ /* note: no further alignment here, we need to have the exact list of pointers */
+ __uvisor_cfgtbl_ptr_start = .;
+ KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
+ KEEP(*(.keep.uvisor.cfgtbl_ptr))
+ __uvisor_cfgtbl_ptr_end = .;
+
+ /* the following symbols are kept for backward compatibility and will be soon
+ * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
+ * will need to use uVisor 0.8.x or above, or the security assertions will halt the
+ * system */
+ /************************/
+ __uvisor_data_src = .;
+ __uvisor_data_start = .;
+ __uvisor_data_end = .;
+ /************************/
+
+ . = ALIGN(32);
+ __uvisor_secure_end = .;
+ } >FLASH
+
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM_INTERN
+
+ .bss (NOLOAD):
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM_INTERN
+
+ .heap (NOLOAD):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*);
+ . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
+ __HeapLimit = .;
+ } > RAM_INTERN
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+
+ /* Provide physical memory boundaries for uVisor. */
+ __uvisor_flash_start = ORIGIN(VECTORS);
+ __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+ __uvisor_sram_start = ORIGIN(RAM_INTERN);
+ __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/nano100_retarget.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,40 @@
+/******************************************************************************
+ * @file startup_NUC472_442.c
+ * @version V0.10
+ * $Revision: 11 $
+ * $Date: 15/09/02 10:02a $
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for NUC472/442 MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "Nano100Series.h"
+#include <errno.h>
+#include "nu_miscutil.h"
+
+extern uint32_t __mbed_sbrk_start;
+extern uint32_t __mbed_krbs_start;
+
+#define NU_HEAP_ALIGN 4
+
+/**
+ * The default implementation of _sbrk() (in common/retarget.cpp) for GCC_ARM requires one-region model (heap and stack share one region), which doesn't
+ * fit two-region model (heap and stack are two distinct regions), for example, NUMAKER-PFM-NUC472 locates heap on external SRAM. Define __wrap__sbrk() to
+ * override the default _sbrk(). It is expected to get called through gcc hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
+ */
+void *__wrap__sbrk(int incr)
+{
+ static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
+ uint32_t heap_ind_old = NU_ALIGN_UP(heap_ind, NU_HEAP_ALIGN);
+ uint32_t heap_ind_new = NU_ALIGN_UP(heap_ind_old + incr, NU_HEAP_ALIGN);
+
+ if (heap_ind_new > &__mbed_krbs_start) {
+ errno = ENOMEM;
+ return (void *) -1;
+ }
+
+ heap_ind = heap_ind_new;
+
+ return (void *) heap_ind_old;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00020000 - 1;
+define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM_end__ = 0x20004000 - 1;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x600;
+define symbol __ICFEDIT_size_heap__ = 0x1200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place at start of IRAM_region { block CSTACK };
+place in IRAM_region { readwrite };
+place in IRAM_region { block HEAP };
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/cmsis.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,33 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2017 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "Nano100Series.h" +#include "cmsis_nvic.h" + +// Support linker-generated symbol as start of relocated vector table. +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; +#elif defined(__ICCARM__) + +#elif defined(__GNUC__) +extern uint32_t __start_vector_table__; +#endif + + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/cmsis_nvic.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis_nvic.h"
+#include "platform/mbed_error.h"
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ // NOTE: On NANO130, relocating vector table is not supported due to just 16KB small SRAM.
+ // Add guard code to prevent from unsupported relocating.
+ uint32_t vector_static = NVIC_GetVector(IRQn);
+ if (vector_static != vector) {
+ error("No support for relocating vector table");
+ }
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t*) NVIC_FLASH_VECTOR_ADDRESS;
+
+ // Return the vector
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_USER_IRQ_OFFSET 16
+#define NVIC_USER_IRQ_NUMBER 32
+#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
+
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
+#elif defined(__ICCARM__)
+# pragma section = "IRAMVEC"
+# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
+#elif defined(__GNUC__)
+# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
+#endif
+
+
+#define NVIC_FLASH_VECTOR_ADDRESS 0
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Set the ISR for IRQn
+ *
+ * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
+ * the first time this function is called
+ * @param[in] IRQn The Interrupt Request number for which a vector will be registered
+ * @param[in] vector The ISR vector to register for IRQn
+ */
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+
+/** Get the ISR registered for IRQn
+ *
+ * Reads the Interrupt Service Routine currently registered for IRQn
+ * @param[in] IRQn The Interrupt Request number the vector of which will be read
+ * @return Returns the ISR registered for IRQn
+ */
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/startup_Nano100Series.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,243 @@
+/******************************************************************************
+ * @file startup_Nano100Series.c
+ * @version V1.00
+ * $Revision: 4 $
+ * $Date: 15/06/08 5:12p $
+ * @brief CMSIS ARM Cortex-M0 Core Device Startup File
+ *
+ * @note
+ * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "Nano100Series.h"
+
+/* Suppress warning messages */
+#if defined(__CC_ARM)
+// Suppress warning message: extended constant initialiser used
+#pragma diag_suppress 1296
+#elif defined(__ICCARM__)
+#elif defined(__GNUC__)
+#endif
+
+/* Macro Definitions */
+#if defined(__CC_ARM)
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias(#f)))
+
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
+
+#elif defined(__ICCARM__)
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void); \
+_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)))
+#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)
+#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS
+
+#elif defined(__GNUC__)
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias(#f)))
+
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
+
+#endif
+
+
+/* Initialize segments */
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern void __main(void);
+#elif defined(__ICCARM__)
+void __iar_program_start(void);
+#elif defined(__GNUC__)
+extern uint32_t __StackTop;
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+
+extern void uvisor_init(void);
+#if defined(TOOLCHAIN_GCC_ARM)
+extern void _start(void);
+#else
+#error("For GCC toolchain, only support GNU ARM Embedded")
+#endif
+#endif
+
+/* Default empty handler */
+void Default_Handler(void);
+
+/* Reset handler */
+void Reset_Handler(void);
+
+/* Cortex-M0 core handlers */
+WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler) // NMI Handler
+WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler) // Hard Fault Handler
+WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler) // SVCall Handler
+WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler) // PendSV Handler
+WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler) // SysTick Handler
+
+/* Peripherals handlers */
+WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // Brownout low voltage detected interrupt
+WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler) // Watch Dog Timer interrupt
+WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler) // External signal interrupt from PB.14 pin
+WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler) // External signal interrupt from PB.15 pin
+WEAK_ALIAS_FUNC(GPABC_IRQHandler, Default_Handler) // External interrupt from PA[15:0]/PB[15:0]/PC[15:0]
+WEAK_ALIAS_FUNC(GPDEF_IRQHandler, Default_Handler) // External interrupt from PD[15:0]/PE[15:0]/PF[7:0]
+WEAK_ALIAS_FUNC(PWM0_IRQHandler, Default_Handler) // PWM 0 interrupt
+WEAK_ALIAS_FUNC(PWM1_IRQHandler, Default_Handler) // PWM 1 interrupt
+WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // Timer 0 interrupt
+WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // Timer 1 interrupt
+WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // Timer 2 interrupt
+WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler) // Timer 3 interrupt
+WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // UART0 interrupt
+WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // UART1 interrupt
+WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // SPI0 interrupt
+WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler) // SPI1 interrupt
+WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler) // SPI2 interrupt
+WEAK_ALIAS_FUNC(HIRC_IRQHandler, Default_Handler) // HIRC interrupt
+WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // I2C0 interrupt
+WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // I2C1 interrupt
+WEAK_ALIAS_FUNC(SC2_IRQHandler, Default_Handler) // SC2 interrupt
+WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler) // SC0 interrupt
+WEAK_ALIAS_FUNC(SC1_IRQHandler, Default_Handler) // SC1 interrupt
+WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler) // USB FS Device interrupt
+ // Reserved
+WEAK_ALIAS_FUNC(LCD_IRQHandler, Default_Handler) // LCD interrupt
+WEAK_ALIAS_FUNC(PDMA_IRQHandler, Default_Handler) // PDMA interrupt
+WEAK_ALIAS_FUNC(I2S_IRQHandler, Default_Handler) // I2S interrupt
+WEAK_ALIAS_FUNC(PDWU_IRQHandler, Default_Handler) // Power Down Wake up interrupt
+WEAK_ALIAS_FUNC(ADC_IRQHandler, Default_Handler) // ADC interrupt
+WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // DAC interrupt
+WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // Real time clock interrupt
+
+/* Vector table */
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+__attribute__ ((section("RESET")))
+const uint32_t __vector_handlers[] = {
+#elif defined(__ICCARM__)
+extern uint32_t CSTACK$$Limit;
+const uint32_t __vector_table[] @ ".intvec" = {
+#elif defined(__GNUC__)
+__attribute__ ((section(".vector_table")))
+const uint32_t __vector_handlers[] = {
+#endif
+
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
+#elif defined(__ICCARM__)
+ (uint32_t) &CSTACK$$Limit,
+#elif defined(__GNUC__)
+ (uint32_t) &__StackTop,
+#endif
+
+ (uint32_t) Reset_Handler, // Reset Handler
+ (uint32_t) NMI_Handler, // NMI Handler
+ (uint32_t) HardFault_Handler, // Hard Fault Handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ (uint32_t) SVC_Handler, // SVCall Handler
+ 0, // Reserved
+ 0, // Reserved
+ (uint32_t) PendSV_Handler, // PendSV Handler
+ (uint32_t) SysTick_Handler, // SysTick Handler
+
+ /* External Interrupts */
+ (uint32_t) BOD_IRQHandler, // Brownout low voltage detected interrupt
+ (uint32_t) WDT_IRQHandler, // Watch Dog Timer interrupt
+ (uint32_t) EINT0_IRQHandler, // External signal interrupt from PB.14 pin
+ (uint32_t) EINT1_IRQHandler, // External signal interrupt from PB.15 pin
+ (uint32_t) GPABC_IRQHandler, // External interrupt from PA[15:0]/PB[15:0]/PC[15:0]
+ (uint32_t) GPDEF_IRQHandler, // External interrupt from PD[15:0]/PE[15:0]/PF[7:0]
+ (uint32_t) PWM0_IRQHandler, // PWM 0 interrupt
+ (uint32_t) PWM1_IRQHandler, // PWM 1 interrupt
+ (uint32_t) TMR0_IRQHandler, // Timer 0 interrupt
+ (uint32_t) TMR1_IRQHandler, // Timer 1 interrupt
+ (uint32_t) TMR2_IRQHandler, // Timer 2 interrupt
+ (uint32_t) TMR3_IRQHandler, // Timer 3 interrupt
+ (uint32_t) UART0_IRQHandler, // UART0 interrupt
+ (uint32_t) UART1_IRQHandler, // UART1 interrupt
+ (uint32_t) SPI0_IRQHandler, // SPI0 interrupt
+ (uint32_t) SPI1_IRQHandler, // SPI1 interrupt
+ (uint32_t) SPI2_IRQHandler, // SPI2 interrupt
+ (uint32_t) HIRC_IRQHandler, // HIRC interrupt
+ (uint32_t) I2C0_IRQHandler, // I2C0 interrupt
+ (uint32_t) I2C1_IRQHandler, // I2C1 interrupt
+ (uint32_t) SC2_IRQHandler, // SC2 interrupt
+ (uint32_t) SC0_IRQHandler, // SC0 interrupt
+ (uint32_t) SC1_IRQHandler, // SC1 interrupt
+ (uint32_t) USBD_IRQHandler, // USB FS Device interrupt
+ (uint32_t) Default_Handler, // Reserved
+ (uint32_t) LCD_IRQHandler, // LCD interrupt
+ (uint32_t) PDMA_IRQHandler, // PDMA interrupt
+ (uint32_t) I2S_IRQHandler, // I2S interrupt
+ (uint32_t) PDWU_IRQHandler, // Power Down Wake up interrupt
+ (uint32_t) ADC_IRQHandler, // ADC interrupt
+ (uint32_t) DAC_IRQHandler, // DAC interrupt
+ (uint32_t) RTC_IRQHandler, // Real time clock interrupt
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ */
+void Reset_Handler(void)
+{
+ /* Disable register write-protection function */
+ SYS_UnlockReg();
+
+ /* Disable Power-on Reset function */
+ SYS_DISABLE_POR();
+
+ /* Enable register write-protection function */
+ SYS_LockReg();
+
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ __main();
+
+#elif defined(__ICCARM__)
+ __iar_program_start();
+
+#elif defined(__GNUC__)
+ uint32_t *src_ind = (uint32_t *) &__etext;
+ uint32_t *dst_ind = (uint32_t *) &__data_start__;
+ uint32_t *dst_end = (uint32_t *) &__data_end__;
+
+ /* Move .data section from ROM to RAM */
+ if (src_ind != dst_ind) {
+ for (; dst_ind < dst_end;) {
+ *dst_ind ++ = *src_ind ++;
+ }
+ }
+
+ /* Initialize .bss section to zero */
+ dst_ind = (uint32_t *) &__bss_start__;
+ dst_end = (uint32_t *) &__bss_end__;
+ if (dst_ind != dst_end) {
+ for (; dst_ind < dst_end;) {
+ *dst_ind ++ = 0;
+ }
+ }
+
+ _start();
+
+#endif
+
+ /* Infinite loop */
+ while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Default_Handler(void)
+{
+ while (1);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/system_Nano100Series.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,126 @@
+/******************************************************************************
+ * @file system_Nano100Series.c
+ * @version V1.00
+ * $Revision: 4 $
+ * $Date: 14/01/29 4:09p $
+ * @brief Nano100 series system clock init code and assert handler
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdint.h>
+#include "Nano100Series.h"
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
+uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
+
+/**
+ * @brief Calculate current PLL clock frequency.
+ * @param None.
+ * @return PLL clock frequency. The clock UNIT is in Hz.
+ */
+uint32_t SysGet_PLLClockFreq(void)
+{
+ uint32_t u32Freq =0, u32PLLSrc;
+ uint32_t u32NO, u32NR, u32IN_DV, u32PllReg;
+
+ u32PllReg = CLK->PLLCTL;
+
+ if (u32PllReg & CLK_PLLCTL_PD)
+ return 0; /* PLL is in power down mode */
+
+ if (u32PllReg & CLK_PLLCTL_PLL_SRC_Msk)
+ u32PLLSrc = __HIRC12M;
+ else
+ u32PLLSrc = __HXT;
+
+ u32NO = (u32PllReg & CLK_PLLCTL_OUT_DV) ? 2: 1;
+
+ u32IN_DV = (u32PllReg & CLK_PLLCTL_IN_DV_Msk) >> 8;
+ if (u32IN_DV == 0)
+ u32NR = 2;
+ else if (u32IN_DV == 1)
+ u32NR = 4;
+ else if (u32IN_DV == 2)
+ u32NR = 8;
+ else
+ u32NR = 16;
+
+ u32Freq = u32PLLSrc * ((u32PllReg & CLK_PLLCTL_FB_DV_Msk) +32) / u32NR / u32NO;
+
+ return u32Freq;
+}
+
+
+/**
+ * @brief Get current HCLK clock frequency.
+ * @param None.
+ * @return HCLK clock frequency. The clock UNIT is in Hz.
+ */
+uint32_t SysGet_HCLKFreq(void)
+{
+
+ uint32_t u32Freqout, u32AHBDivider, u32ClkSel;
+
+ u32ClkSel = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
+
+ if (u32ClkSel == CLK_CLKSEL0_HCLK_S_HXT) { /* external HXT crystal clock */
+ u32Freqout = __HXT;
+ } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LXT) { /* external LXT crystal clock */
+ u32Freqout = __LXT;
+ } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_PLL) { /* PLL clock */
+ u32Freqout = SysGet_PLLClockFreq();
+ } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LIRC) { /* internal LIRC oscillator clock */
+ u32Freqout = __LIRC;
+ } else { /* internal HIRC oscillator clock */
+ u32Freqout = __HIRC12M;
+ }
+ u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK_N_Msk) + 1 ;
+
+ return (u32Freqout/u32AHBDivider);
+}
+
+
+/**
+ * @brief This function is used to update the variable SystemCoreClock
+ * and must be called whenever the core clock is changed.
+ * @param None.
+ * @retval None.
+ */
+
+void SystemCoreClockUpdate (void)
+{
+
+ SystemCoreClock = SysGet_HCLKFreq();
+ CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
+}
+
+#if USE_ASSERT
+
+/**
+ * @brief Assert Error Message
+ *
+ * @param[in] file the source file name
+ * @param[in] line line number
+ *
+ * @return None
+ *
+ * @details The function prints the source file name and line number where
+ * the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
+ */
+void AssertError(uint8_t * file, uint32_t line)
+{
+
+ printf("[%s] line %d : wrong parameters.\r\n", file, line);
+
+ /* Infinite loop */
+ while(1) ;
+}
+#endif
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/system_Nano100Series.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file system_Nano100Series.h
+ * @version V1.00
+ * $Revision: 2 $
+ * $Date: 14/01/07 7:35p $
+ * @brief Nano100 series system clock definition file
+ *
+ * @note
+ * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+
+#ifndef __SYSTEM_NANO100SERIES_H__
+#define __SYSTEM_NANO100SERIES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Define SYSCLK
+ *----------------------------------------------------------------------------*/
+
+#define __HXT (12000000UL)
+#define __LXT (32768UL)
+#define __HIRC12M (12000000UL)
+#define __LIRC (10000UL)
+#define __HIRC __HIRC12M
+#define __HSI (__HIRC12M) /* Factory Default is internal 12MHz */
+
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param None
+ * @return None
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from CPU registers.
+ */
+
+extern void SystemCoreClockUpdate (void);
+extern uint32_t SysGet_PLLClockFreq(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SYSTEM_NANO100SERIES_H__
+
+
+/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/dma.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_DMA_H
+#define MBED_DMA_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DMA_CAP_NONE (0 << 0)
+
+#define DMA_EVENT_ABORT (1 << 0)
+#define DMA_EVENT_TRANSFER_DONE (1 << 1)
+#define DMA_EVENT_TIMEOUT (1 << 2)
+#define DMA_EVENT_ALL (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT)
+#define DMA_EVENT_MASK DMA_EVENT_ALL
+
+void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event);
+PDMA_T *dma_modbase(int channelid);
+void dma_enable(int channelid, int enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/dma_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,177 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "dma_api.h"
+#include "string.h"
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "PeripheralNames.h"
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+#include "dma.h"
+
+#define NU_PDMA_CH_MAX 6 /* Specify maximum channels of PDMA */
+#define NU_PDMA_CH_Pos 1 /* Specify first channel number of PDMA */
+#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos)
+
+struct nu_dma_chn_s {
+ void (*handler)(uint32_t, uint32_t);
+ uint32_t id;
+ uint32_t event;
+};
+
+static int dma_inited = 0;
+static uint32_t dma_chn_mask = 0;
+static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX];
+static const DMAName dmaname_chn_arr[NU_PDMA_CH_MAX] = {
+ // NOTE: DMA_0_0 for VDMA
+ DMA_1_0, DMA_2_0, DMA_3_0, DMA_4_0, DMA_5_0, DMA_6_0
+};
+
+void PDMA_IRQHandler(void);
+static const struct nu_modinit_s dma_modinit = {DMAGCR_0, DMA_MODULE, 0, 0, DMA_RST, PDMA_IRQn, (void *) PDMA_IRQHandler};
+
+
+void dma_init(void)
+{
+ if (dma_inited) {
+ return;
+ }
+
+ dma_inited = 1;
+ dma_chn_mask = ~NU_PDMA_CH_Msk;
+ memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
+
+ // Reset this module
+ SYS_ResetModule(dma_modinit.rsetidx);
+
+ // Enable IP clock
+ CLK_EnableModuleClock(dma_modinit.clkidx);
+
+ PDMA_Open(0);
+
+ NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
+ NVIC_EnableIRQ(dma_modinit.irq_n);
+}
+
+int dma_channel_allocate(uint32_t capabilities)
+{
+ if (! dma_inited) {
+ dma_init();
+ }
+
+ int i = nu_cto(dma_chn_mask);
+ if (i != 32) {
+ dma_chn_mask |= 1 << i;
+ memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s));
+ return i;
+ }
+
+ // No channel available
+ return DMA_ERROR_OUT_OF_CHANNELS;
+}
+
+int dma_channel_free(int channelid)
+{
+ if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
+ dma_chn_mask &= ~(1 << channelid);
+ }
+
+ return 0;
+}
+
+void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
+{
+ MBED_ASSERT(dma_chn_mask & (1 << channelid));
+
+ dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler;
+ dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id;
+ dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event;
+
+ // Set interrupt vector if someone has removed it.
+ NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
+ NVIC_EnableIRQ(dma_modinit.irq_n);
+}
+
+PDMA_T *dma_modbase(int channelid)
+{
+ DMAName dma_name = dmaname_chn_arr[channelid - NU_PDMA_CH_Pos];
+ return (PDMA_T *) NU_MODBASE(dma_name);
+}
+
+void dma_enable(int channelid, int enable)
+{
+ DMA_GCR_T *dmagcr_base = (DMA_GCR_T *) NU_MODBASE(dma_modinit.modname);
+ PDMA_T *pdma_base = dma_modbase(channelid);
+ uint32_t pos = channelid - NU_PDMA_CH_Pos + DMA_GCR_GCRCSR_CLK1_EN_Pos;
+
+ if (enable) {
+ dmagcr_base->GCRCSR |= 1 << pos; // Enable channel clock
+ pdma_base->CSR |= (PDMA_CSR_PDMACEN_Msk); // Enable channel
+ }
+ else {
+ dmagcr_base->GCRCSR &= ~(1 << pos); // Disable channel clock
+ pdma_base->CSR &= ~(PDMA_CSR_PDMACEN_Msk); // Disable channel
+ }
+}
+
+void PDMA_IRQHandler(void)
+{
+ uint32_t intsts = PDMA_GET_INT_STATUS();
+ // Just interested in INTR1-INTR6
+ intsts &= ((NU_PDMA_CH_Msk >> NU_PDMA_CH_Pos) << DMA_GCR_GCRISR_INTR1_Pos);
+
+ while (intsts) {
+ int chn_id = nu_ctz(intsts) - DMA_GCR_GCRISR_INTR1_Pos + NU_PDMA_CH_Pos;
+ uint32_t intsts_chn = PDMA_GET_CH_INT_STS(chn_id);
+
+ if (dma_chn_mask & (1 << chn_id)) {
+ struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos;
+
+ // Abort
+ if (intsts_chn & PDMA_ISR_TABORT_IS_Msk) {
+ // Clear ABORT IF of the channel
+ PDMA_CLR_CH_INT_FLAG(chn_id, PDMA_ISR_TABORT_IS_Msk);
+
+ if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
+ dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
+ }
+ }
+
+ // Transfer done
+ if (intsts_chn & PDMA_ISR_TD_IS_Msk) {
+ // Clear TD IF of the channel
+ PDMA_CLR_CH_INT_FLAG(chn_id, PDMA_ISR_TD_IS_Msk);
+
+ if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
+ dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
+ }
+ }
+
+ // Timeout
+ if (intsts_chn & PDMA_ISR_TO_IS_Msk) {
+ // Clear TIMEOUT IF of the channel
+ PDMA_CLR_CH_INT_FLAG(chn_id, PDMA_ISR_TO_IS_Msk);
+
+ if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
+ dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
+ }
+ }
+ }
+
+ intsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + DMA_GCR_GCRISR_INTR1_Pos));
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio_api.h"
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+uint32_t gpio_set(PinName pin)
+{
+ if (pin == (PinName) NC) {
+ return 0;
+ }
+
+ uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+
+ // GPIO PinMap
+ pin_function(pin, 0 << NU_MFP_POS(pin_index));
+
+ return (uint32_t)(1 << pin_index); // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ obj->pin = pin;
+
+ if (obj->pin == (PinName) NC) {
+ return;
+ }
+
+ obj->mask = gpio_set(pin);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ if (obj->pin == (PinName) NC) {
+ return;
+ }
+
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ if (obj->pin == (PinName) NC) {
+ return;
+ }
+
+ uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+ GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+ uint32_t mode_intern = GPIO_PMD_INPUT;
+
+ switch (direction) {
+ case PIN_INPUT:
+ mode_intern = GPIO_PMD_INPUT;
+ break;
+
+ case PIN_OUTPUT:
+ mode_intern = GPIO_PMD_OUTPUT;
+ break;
+
+ default:
+ return;
+ }
+
+ GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,274 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio_irq_api.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "mbed_error.h"
+#include "nu_bitutil.h"
+
+#define NU_MAX_PIN_PER_PORT 16
+
+struct nu_gpio_irq_var {
+ gpio_irq_t * obj_arr;
+ uint32_t gpio_n;
+ void (*vec)(void);
+};
+
+void GPABC_IRQHandler(void);
+void GPDEF_IRQHandler(void);
+static void gpio_irq(struct nu_gpio_irq_var *var);
+
+//EINT0_IRQn
+static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
+ {NULL, 0, GPABC_IRQHandler},
+ {NULL, 1, GPABC_IRQHandler},
+ {NULL, 2, GPABC_IRQHandler},
+ {NULL, 3, GPDEF_IRQHandler},
+ {NULL, 4, GPDEF_IRQHandler},
+ {NULL, 5, GPDEF_IRQHandler}
+};
+
+#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
+
+#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE
+#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE 0
+#endif
+
+#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
+#endif
+static PinName gpio_irq_debounce_arr[] = {
+ MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+};
+
+#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCLKSRC_IRC10K
+#endif
+
+#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCLKSEL_16
+#endif
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ if (pin == NC) {
+ return -1;
+ }
+
+ uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+ if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
+ return -1;
+ }
+
+ obj->pin = pin;
+ obj->irq_handler = (uint32_t) handler;
+ obj->irq_id = id;
+ obj->next = NULL;
+
+ GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+ // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting.
+ // There is no need to call gpio_set() redundantly.
+
+ {
+#if MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE
+ // Suppress compiler warning
+ (void) gpio_irq_debounce_arr;
+
+ // Configure de-bounce clock source and sampling cycle time
+ GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+ GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+#else
+ // Enable de-bounce if the pin is in the de-bounce enable list
+
+ // De-bounce defaults to disabled.
+ GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+
+ PinName *debounce_pos = gpio_irq_debounce_arr;
+ PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
+ for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
+ uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
+ uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
+
+ if (pin_index == pin_index_debunce &&
+ port_index == port_index_debounce) {
+ // Configure de-bounce clock source and sampling cycle time
+ GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+ GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+ break;
+ }
+ }
+#endif
+ }
+
+ struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+ // Add obj to linked list
+ gpio_irq_t *cur_obj = var->obj_arr;
+ if (cur_obj == NULL) {
+ var->obj_arr = obj;
+ } else {
+ while (cur_obj->next != NULL)
+ cur_obj = cur_obj->next;
+ cur_obj->next = obj;
+ }
+
+ // NOTE: InterruptIn requires IRQ enabled by default.
+ gpio_irq_enable(obj);
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+ struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+ NVIC_DisableIRQ((var->gpio_n < 3) ? GPABC_IRQn : GPDEF_IRQn);
+ NU_PORT_BASE(port_index)->IER = 0;
+
+ MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
+ gpio_irq_t *pre_obj = var->obj_arr;
+ if (pre_obj->pin == obj->pin)
+ var->obj_arr = pre_obj->next;
+ else {
+ int error_flag = 1;
+ while (pre_obj->next) {
+ gpio_irq_t *cur_obj = pre_obj->next;
+ if (cur_obj->pin == obj->pin) {
+ pre_obj->next = cur_obj->next;
+ error_flag = 0;
+ break;
+ }
+ pre_obj = pre_obj->next;
+ }
+ if (error_flag)
+ error("cannot find obj in gpio_irq_free()");
+ }
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+ GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+ switch (event) {
+ case IRQ_RISE:
+ if (enable) {
+ GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
+ }
+ else {
+ gpio_base->IER &= ~(GPIO_INT_RISING << pin_index);
+ }
+ break;
+
+ case IRQ_FALL:
+ if (enable) {
+ GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
+ }
+ else {
+ gpio_base->IER &= ~(GPIO_INT_FALLING << pin_index);
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+ struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+ NVIC_SetVector((var->gpio_n < 3) ? GPABC_IRQn : GPDEF_IRQn, (uint32_t) var->vec);
+ NVIC_EnableIRQ((var->gpio_n < 3) ? GPABC_IRQn : GPDEF_IRQn);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+ struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+
+ NVIC_DisableIRQ((var->gpio_n < 3) ? GPABC_IRQn : GPDEF_IRQn);
+}
+
+void GPABC_IRQHandler(void)
+{
+ if (PA->ISRC)
+ gpio_irq(gpio_irq_var_arr + 0);
+ if (PB->ISRC)
+ gpio_irq(gpio_irq_var_arr + 1);
+ if (PC->ISRC)
+ gpio_irq(gpio_irq_var_arr + 2);
+}
+void GPDEF_IRQHandler(void)
+{
+ if (PD->ISRC)
+ gpio_irq(gpio_irq_var_arr + 3);
+ if (PE->ISRC)
+ gpio_irq(gpio_irq_var_arr + 4);
+ if (PF->ISRC)
+ gpio_irq(gpio_irq_var_arr + 5);
+}
+
+static void gpio_irq(struct nu_gpio_irq_var *var)
+{
+ uint32_t port_index = var->gpio_n;
+ GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+ uint32_t isrc = gpio_base->ISRC;
+ uint32_t ier = gpio_base->IER;
+ while (isrc) {
+ int pin_index = nu_ctz(isrc);
+ PinName pin = (PinName) NU_PINNAME(port_index, pin_index);
+ gpio_irq_t *obj = var->obj_arr;
+ while (obj) {
+ if (obj->pin == pin)
+ break;
+ obj = obj->next;
+ }
+ if (ier & (GPIO_INT_RISING << pin_index)) {
+ if (GPIO_PIN_ADDR(port_index, pin_index)) {
+ if (obj && obj->irq_handler) {
+ ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
+ }
+ }
+ }
+
+ if (ier & (GPIO_INT_FALLING << pin_index)) {
+ if (! GPIO_PIN_ADDR(port_index, pin_index)) {
+ if (obj && obj->irq_handler) {
+ ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
+ }
+ }
+ }
+
+ isrc &= ~(1 << pin_index);
+ }
+ // Clear all interrupt flags
+ gpio_base->ISRC = gpio_base->ISRC;
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_object.h Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+
+ GPIO_PIN_ADDR(port_index, pin_index) = value ? 1 : 0;
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+
+ return (GPIO_PIN_ADDR(port_index, pin_index) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,1022 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+#include "mbed_critical.h"
+
+#define NU_I2C_DEBUG 0
+
+#if NU_I2C_DEBUG
+struct i2c_s MY_I2C;
+struct i2c_s MY_I2C_2;
+char MY_I2C_STATUS[64];
+int MY_I2C_STATUS_POS = 0;
+uint32_t MY_I2C_TIMEOUT;
+uint32_t MY_I2C_ELAPSED;
+uint32_t MY_I2C_T1;
+uint32_t MY_I2C_T2;
+#endif
+
+struct nu_i2c_var {
+ i2c_t * obj;
+ void (*vec)(void);
+};
+
+// NOTE: NANO130 doesn't support relocating vector table. ISR vector passed into NVIC_SetVector() can only be weak symbol defined in startup_Nano100Series.c.
+void I2C0_IRQHandler(void);
+void I2C1_IRQHandler(void);
+static void i2c_irq(i2c_t *obj);
+static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
+static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked);
+
+static struct nu_i2c_var i2c0_var = {
+ .obj = NULL,
+ .vec = I2C0_IRQHandler,
+};
+static struct nu_i2c_var i2c1_var = {
+ .obj = NULL,
+ .vec = I2C1_IRQHandler,
+};
+
+static uint32_t i2c_modinit_mask = 0;
+
+static const struct nu_modinit_s i2c_modinit_tab[] = {
+ {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
+ {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
+
+ {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
+static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
+#define NU_I2C_TIMEOUT_STAT_INT 500000
+#define NU_I2C_TIMEOUT_STOP 500000
+static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
+static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
+static int i2c_is_trsn_done(i2c_t *obj);
+static int i2c_is_tran_started(i2c_t *obj);
+static int i2c_addr2data(int address, int read);
+
+/*
+ * Wrapper for I2C_SET_CONTROL_REG. Clear new state IF before state change is triggered.
+ *
+ * NOTE:
+ * NUC472/M453/M487: I2C_T::CTL.SI for both I2C new state IF and trigger state change
+ * NANO130: I2C_T::INTSTS.INTSTS for I2C new state IF and I2C_T::CON.I2C_STS for trigger state change
+ */
+__STATIC_INLINE void i2c_set_control_reg(I2C_T *i2c_base, uint8_t i2c_ctrl)
+{
+ if ((i2c_ctrl & I2C_CON_I2C_STS_Msk) && (i2c_base->INTSTS & I2C_INTSTS_INTSTS_Msk)) {
+ i2c_base->INTSTS = I2C_INTSTS_INTSTS_Msk;
+ }
+ I2C_SET_CONTROL_REG(i2c_base, i2c_ctrl);
+}
+
+#if DEVICE_I2CSLAVE
+// Convert mbed address to BSP address.
+static int i2c_addr2bspaddr(int address);
+#endif // #if DEVICE_I2CSLAVE
+static void i2c_enable_int(i2c_t *obj);
+static void i2c_disable_int(i2c_t *obj);
+static int i2c_set_int(i2c_t *obj, int inten);
+
+
+#if DEVICE_I2C_ASYNCH
+static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
+static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
+static void i2c_teardown_async(i2c_t *obj);
+#endif
+
+#define TRANCTRL_STARTED (1)
+#define TRANCTRL_NAKLASTDATA (1 << 1)
+#define TRANCTRL_LASTDATANAKED (1 << 2)
+
+uint32_t us_ticker_read(void);
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+ uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
+ uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT((int)obj->i2c.i2c != NC);
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((I2CName) modinit->modname == obj->i2c.i2c);
+
+ // Reset this module
+ SYS_ResetModule(modinit->rsetidx);
+
+ // Enable IP clock
+ CLK_EnableModuleClock(modinit->clkidx);
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+
+#if DEVICE_I2C_ASYNCH
+ obj->i2c.dma_usage = DMA_USAGE_NEVER;
+ obj->i2c.event = 0;
+ obj->i2c.stop = 0;
+ obj->i2c.address = 0;
+#endif
+
+ // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
+ I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
+ // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL0. We cannot control interrupt through
+ // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+ i2c_base->CON |= (I2C_CON_INTEN_Msk | I2C_CON_IPEN_Msk);
+
+ // Enable sync-mode vector interrupt.
+ struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+ var->obj = obj;
+ obj->i2c.tran_ctrl = 0;
+ obj->i2c.stop = 0;
+ obj->i2c.hdlr_async = 0;
+ i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
+
+ // Mark this module to be inited.
+ int i = modinit - i2c_modinit_tab;
+ i2c_modinit_mask |= 1 << i;
+}
+
+int i2c_start(i2c_t *obj)
+{
+ return i2c_do_trsn(obj, I2C_CON_START_Msk | I2C_CON_I2C_STS_Msk, 1);
+}
+
+int i2c_stop(i2c_t *obj)
+{
+ return i2c_do_trsn(obj, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk, 1);
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ if (i2c_start(obj)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Read in bytes
+ length = i2c_do_tran(obj, data, length, 1, 1);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ if (i2c_start(obj)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Write out bytes
+ length = i2c_do_tran(obj, (char *) data, length, 0, 1);
+
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ char data = 0;
+ i2c_do_tran(obj, &data, 1, 1, last);
+ return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ char data_[1];
+ data_[0] = data & 0xFF;
+
+ if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 &&
+ ! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) {
+ return 1;
+ }
+ else {
+ return 0;
+ }
+}
+
+#if DEVICE_I2CSLAVE
+
+// See I2CSlave.h
+#define NoData 0 // the slave has not been addressed
+#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral 2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+ i2c_disable_int(obj);
+
+ obj->i2c.slaveaddr_state = NoData;
+ obj->i2c.hdlr_async = 0;
+
+ // Switch to not addressed mode
+ i2c_set_control_reg(i2c_base, I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk);
+
+ i2c_enable_int(obj);
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+ int slaveaddr_state;
+
+ i2c_disable_int(obj);
+ slaveaddr_state = obj->i2c.slaveaddr_state;
+ i2c_enable_int(obj);
+
+ return slaveaddr_state;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ return i2c_do_tran(obj, data, length, 1, 1);
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ return i2c_do_tran(obj, (char *) data, length, 0, 1);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+ i2c_disable_int(obj);
+
+ // NOTE: On NUC472/M451, non-zero slave address can still work as GC mode is enabled.
+ // On M480, non-zero slave address won't work as GC mode is enabled.
+ I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_DISABLE);
+
+ i2c_enable_int(obj);
+}
+
+static int i2c_addr2bspaddr(int address)
+{
+ return (address >> 1);
+}
+
+#endif // #if DEVICE_I2CSLAVE
+
+static void i2c_enable_int(i2c_t *obj)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+
+ core_util_critical_section_enter();
+
+ // Enable I2C interrupt
+ NVIC_EnableIRQ(modinit->irq_n);
+ obj->i2c.inten = 1;
+
+ core_util_critical_section_exit();
+}
+
+static void i2c_disable_int(i2c_t *obj)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+
+ core_util_critical_section_enter();
+
+ // Disable I2C interrupt
+ NVIC_DisableIRQ(modinit->irq_n);
+ obj->i2c.inten = 0;
+
+ core_util_critical_section_exit();
+}
+
+static int i2c_set_int(i2c_t *obj, int inten)
+{
+ int inten_back;
+
+ core_util_critical_section_enter();
+
+ inten_back = obj->i2c.inten;
+
+ core_util_critical_section_exit();
+
+ if (inten) {
+ i2c_enable_int(obj);
+ }
+ else {
+ i2c_disable_int(obj);
+ }
+
+ return inten_back;
+}
+
+int i2c_allow_powerdown(void)
+{
+ uint32_t modinit_mask = i2c_modinit_mask;
+ while (modinit_mask) {
+ int i2c_idx = nu_ctz(modinit_mask);
+ const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
+ struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+ if (var->obj) {
+ // Disallow entering power-down mode if I2C transfer is enabled.
+ if (i2c_active(var->obj)) {
+ return 0;
+ }
+ }
+ modinit_mask &= ~(1 << i2c_idx);
+ }
+
+ return 1;
+}
+
+static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
+{
+ if (! buf || ! length) {
+ return 0;
+ }
+
+ int tran_len = 0;
+
+ i2c_disable_int(obj);
+ obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
+ obj->i2c.tran_beg = buf;
+ obj->i2c.tran_pos = buf;
+ obj->i2c.tran_end = buf + length;
+ obj->i2c.hdlr_async = 0;
+ i2c_enable_int(obj);
+
+ if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
+#if NU_I2C_DEBUG
+ MY_I2C_2 = obj->i2c;
+ while (1);
+#endif
+ }
+ else {
+ i2c_disable_int(obj);
+ tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
+ obj->i2c.tran_beg = NULL;
+ obj->i2c.tran_pos = NULL;
+ obj->i2c.tran_end = NULL;
+ i2c_enable_int(obj);
+ }
+
+ return tran_len;
+}
+
+static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
+{
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+ int err = 0;
+
+ i2c_disable_int(obj);
+
+ if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
+ err = I2C_ERROR_BUS_BUSY;
+#if NU_I2C_DEBUG
+ MY_I2C_2 = obj->i2c;
+ while (1);
+#endif
+ }
+ else {
+#if 1
+ // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
+ uint32_t status = I2C_GET_STATUS(i2c_base);
+
+ switch (status) {
+ case 0x08: // Start
+ case 0x10: // Master Repeat Start
+ if (i2c_ctl & I2C_CON_START_Msk) {
+ return 0;
+ }
+ else {
+ break;
+ }
+ case 0xF8: // Bus Released
+ if ((i2c_ctl & (I2C_CON_START_Msk | I2C_CON_STOP_Msk)) == I2C_CON_STOP_Msk) {
+ return 0;
+ }
+ else {
+ break;
+ }
+ }
+#endif
+ i2c_set_control_reg(i2c_base, i2c_ctl);
+ if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
+ err = I2C_ERROR_BUS_BUSY;
+#if NU_I2C_DEBUG
+ MY_I2C_2 = obj->i2c;
+ while (1);
+#endif
+ }
+ }
+
+ i2c_enable_int(obj);
+
+ return err;
+}
+
+static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
+{
+ uint32_t t1, t2, elapsed = 0;
+ int status_assert = 0;
+
+ t1 = us_ticker_read();
+ while (1) {
+ status_assert = is_status(obj);
+ if (status_assert) {
+ break;
+ }
+
+ t2 = us_ticker_read();
+ elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
+ if (elapsed >= timeout) {
+#if NU_I2C_DEBUG
+ MY_I2C_T1 = t1;
+ MY_I2C_T2 = t2;
+ MY_I2C_ELAPSED = elapsed;
+ MY_I2C_TIMEOUT = timeout;
+ MY_I2C_2 = obj->i2c;
+ while (1);
+#endif
+ break;
+ }
+ }
+
+ return (elapsed >= timeout);
+}
+
+static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
+{
+ uint32_t t1, t2, elapsed = 0;
+ int tran_started;
+ char *tran_pos = NULL;
+ char *tran_pos2 = NULL;
+
+ i2c_disable_int(obj);
+ tran_pos = obj->i2c.tran_pos;
+ i2c_enable_int(obj);
+ t1 = us_ticker_read();
+ while (1) {
+ i2c_disable_int(obj);
+ tran_started = i2c_is_tran_started(obj);
+ i2c_enable_int(obj);
+ if (! tran_started) { // Transfer completed or stopped
+ break;
+ }
+
+ i2c_disable_int(obj);
+ tran_pos2 = obj->i2c.tran_pos;
+ i2c_enable_int(obj);
+ t2 = us_ticker_read();
+ if (tran_pos2 != tran_pos) { // Transfer on-going
+ t1 = t2;
+ tran_pos = tran_pos2;
+ continue;
+ }
+
+ elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
+ if (elapsed >= timeout) { // Transfer idle
+#if NU_I2C_DEBUG
+ MY_I2C = obj->i2c;
+ MY_I2C_T1 = t1;
+ MY_I2C_T2 = t2;
+ MY_I2C_ELAPSED = elapsed;
+ MY_I2C_TIMEOUT = timeout;
+ MY_I2C_2 = obj->i2c;
+ while (1);
+#endif
+ break;
+ }
+ }
+
+ return (elapsed >= timeout);
+}
+
+
+static int i2c_is_trsn_done(i2c_t *obj)
+{
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+ int i2c_int;
+ uint32_t status;
+ int inten_back;
+
+ inten_back = i2c_set_int(obj, 0);
+ // NANO130
+ i2c_int = !! (i2c_base->INTSTS & I2C_INTSTS_INTSTS_Msk);
+ status = I2C_GET_STATUS(i2c_base);
+ i2c_set_int(obj, inten_back);
+
+ return (i2c_int || status == 0xF8);
+}
+
+static int i2c_is_tran_started(i2c_t *obj)
+{
+ int started;
+ int inten_back;
+
+ inten_back = i2c_set_int(obj, 0);
+ started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
+ i2c_set_int(obj, inten_back);
+
+ return started;
+}
+
+static int i2c_addr2data(int address, int read)
+{
+ return read ? (address | 1) : (address & 0xFE);
+}
+
+void I2C0_IRQHandler(void)
+{
+ i2c_irq(i2c0_var.obj);
+}
+void I2C1_IRQHandler(void)
+{
+ i2c_irq(i2c1_var.obj);
+}
+
+static void i2c_irq(i2c_t *obj)
+{
+ if (obj->i2c.hdlr_async) {
+ void (*hdlr_async)(void) = (void(*)(void))(obj->i2c.hdlr_async);
+ hdlr_async();
+ return;
+ }
+
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+ uint32_t status;
+
+ if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
+ I2C_ClearTimeoutFlag(i2c_base);
+ return;
+ }
+
+ status = I2C_GET_STATUS(i2c_base);
+#if NU_I2C_DEBUG
+ if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
+ MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
+ }
+ else {
+ memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
+ MY_I2C_STATUS_POS = 0;
+ }
+#endif
+
+ switch (status) {
+ // Master Transmit
+ case 0x28: // Master Transmit Data ACK
+ case 0x18: // Master Transmit Address ACK
+ case 0x08: // Start
+ case 0x10: // Master Repeat Start
+ if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+ if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+ I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
+ i2c_set_control_reg(i2c_base, I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk);
+ }
+ else {
+ i2c_fsm_tranfini(obj, 0);
+ }
+ }
+ else {
+ i2c_disable_int(obj);
+ }
+ break;
+
+ case 0x30: // Master Transmit Data NACK
+ i2c_fsm_tranfini(obj, 1);
+ break;
+
+ case 0x20: // Master Transmit Address NACK
+ i2c_fsm_tranfini(obj, 1);
+ break;
+
+ case 0x38: // Master Arbitration Lost
+ i2c_fsm_reset(obj, I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk);
+ break;
+
+ case 0x48: // Master Receive Address NACK
+ i2c_fsm_tranfini(obj, 1);
+ break;
+
+ case 0x40: // Master Receive Address ACK
+ case 0x50: // Master Receive Data ACK
+ case 0x58: // Master Receive Data NACK
+ if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+ if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+ if (status == 0x50 || status == 0x58) {
+ *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+ }
+
+ if (status == 0x58) {
+#if NU_I2C_DEBUG
+ if (obj->i2c.tran_pos != obj->i2c.tran_end) {
+ MY_I2C = obj->i2c;
+ while (1);
+ }
+#endif
+ i2c_fsm_tranfini(obj, 1);
+ }
+ else {
+ uint32_t i2c_ctl = I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk;
+ if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+ obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+ // Last data
+ i2c_ctl &= ~I2C_CON_ACK_Msk;
+ }
+ i2c_set_control_reg(i2c_base, i2c_ctl);
+ }
+ }
+ else {
+ obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+ i2c_disable_int(obj);
+ break;
+ }
+ }
+ else {
+ i2c_disable_int(obj);
+ }
+ break;
+
+ //case 0x00: // Bus error
+
+ // Slave Transmit
+ case 0xB8: // Slave Transmit Data ACK
+ case 0xA8: // Slave Transmit Address ACK
+ case 0xB0: // Slave Transmit Arbitration Lost
+ if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+ if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+ uint32_t i2c_ctl = I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk;
+
+ I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
+ if (obj->i2c.tran_pos == obj->i2c.tran_end &&
+ obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+ // Last data
+ i2c_ctl &= ~I2C_CON_ACK_Msk;
+ }
+ i2c_set_control_reg(i2c_base, i2c_ctl);
+ }
+ else {
+ obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+ i2c_disable_int(obj);
+ break;
+ }
+ }
+ else {
+ i2c_disable_int(obj);
+ }
+ obj->i2c.slaveaddr_state = ReadAddressed;
+ break;
+ //case 0xA0: // Slave Transmit Repeat Start or Stop
+ case 0xC0: // Slave Transmit Data NACK
+ case 0xC8: // Slave Transmit Last Data ACK
+ obj->i2c.slaveaddr_state = NoData;
+ i2c_fsm_reset(obj, I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk);
+ break;
+
+ // Slave Receive
+ case 0x80: // Slave Receive Data ACK
+ case 0x88: // Slave Receive Data NACK
+ case 0x60: // Slave Receive Address ACK
+ case 0x68: // Slave Receive Arbitration Lost
+ obj->i2c.slaveaddr_state = WriteAddressed;
+ if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+ if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+ if (status == 0x80 || status == 0x88) {
+ *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+ }
+
+ if (status == 0x88) {
+#if NU_I2C_DEBUG
+ if (obj->i2c.tran_pos != obj->i2c.tran_end) {
+ MY_I2C = obj->i2c;
+ while (1);
+ }
+#endif
+ obj->i2c.slaveaddr_state = NoData;
+ i2c_fsm_reset(obj, I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk);
+ }
+ else {
+ uint32_t i2c_ctl = I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk;
+ if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+ obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+ // Last data
+ i2c_ctl &= ~I2C_CON_ACK_Msk;
+ }
+ i2c_set_control_reg(i2c_base, i2c_ctl);
+ }
+ }
+ else {
+ obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+ i2c_disable_int(obj);
+ break;
+ }
+ }
+ else {
+ i2c_disable_int(obj);
+ }
+ break;
+ //case 0xA0: // Slave Receive Repeat Start or Stop
+
+ // GC mode
+ //case 0xA0: // GC mode Repeat Start or Stop
+ case 0x90: // GC mode Data ACK
+ case 0x98: // GC mode Data NACK
+ case 0x70: // GC mode Address ACK
+ case 0x78: // GC mode Arbitration Lost
+ obj->i2c.slaveaddr_state = WriteAddressed;
+ if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+ if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+ if (status == 0x90 || status == 0x98) {
+ *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+ }
+
+ if (status == 0x98) {
+#if NU_I2C_DEBUG
+ if (obj->i2c.tran_pos != obj->i2c.tran_end) {
+ MY_I2C = obj->i2c;
+ while (1);
+ }
+#endif
+ obj->i2c.slaveaddr_state = NoData;
+ i2c_fsm_reset(obj, I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk);
+ }
+ else {
+ uint32_t i2c_ctl = I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk;
+ if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+ obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+ // Last data
+ i2c_ctl &= ~I2C_CON_ACK_Msk;
+ }
+ i2c_set_control_reg(i2c_base, i2c_ctl);
+ }
+ }
+ else {
+ obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+ i2c_disable_int(obj);
+ break;
+ }
+ }
+ else {
+ i2c_disable_int(obj);
+ }
+ break;
+
+ case 0xF8: // Bus Released
+ break;
+
+ default:
+ i2c_fsm_reset(obj, I2C_CON_I2C_STS_Msk | I2C_CON_ACK_Msk);
+ }
+}
+
+static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
+{
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+ obj->i2c.stop = 0;
+
+ obj->i2c.tran_ctrl = 0;
+
+ i2c_set_control_reg(i2c_base, i2c_ctl);
+ obj->i2c.slaveaddr_state = NoData;
+}
+
+static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked)
+{
+ if (lastdatanaked) {
+ obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED;
+ }
+
+ obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+ i2c_disable_int(obj);
+}
+
+#if DEVICE_I2C_ASYNCH
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ // NOTE: M451 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
+ MBED_ASSERT((address & 0xFFFFFF00) == 0);
+
+ // NOTE: First transmit and then receive.
+
+ (void) hint;
+ obj->i2c.dma_usage = DMA_USAGE_NEVER;
+ obj->i2c.stop = stop;
+ obj->i2c.address = address;
+ obj->i2c.event = event;
+ i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
+
+ obj->i2c.hdlr_async = handler;
+ i2c_start(obj);
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+ int event = 0;
+
+ I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+ uint32_t status = I2C_GET_STATUS(i2c_base);
+ switch (status) {
+ case 0x08: // Start
+ case 0x10: {// Master Repeat Start
+ if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+ I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
+ i2c_set_control_reg(i2c_base, I2C_CON_I2C_STS_Msk);
+ }
+ else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+ I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
+ i2c_set_control_reg(i2c_base, I2C_CON_I2C_STS_Msk);
+ }
+ else {
+ event = I2C_EVENT_TRANSFER_COMPLETE;
+ if (obj->i2c.stop) {
+ i2c_set_control_reg(i2c_base, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ }
+ break;
+ }
+
+ case 0x18: // Master Transmit Address ACK
+ case 0x28: // Master Transmit Data ACK
+ if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+ uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
+ I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
+ i2c_set_control_reg(i2c_base, I2C_CON_I2C_STS_Msk);
+ }
+ else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+ i2c_set_control_reg(i2c_base, I2C_CON_START_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ else {
+ event = I2C_EVENT_TRANSFER_COMPLETE;
+ if (obj->i2c.stop) {
+ i2c_set_control_reg(i2c_base, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ }
+ break;
+
+ case 0x20: // Master Transmit Address NACK
+ event = I2C_EVENT_ERROR_NO_SLAVE;
+ if (obj->i2c.stop) {
+ i2c_set_control_reg(i2c_base, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ break;
+
+ case 0x30: // Master Transmit Data NACK
+ if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+ event = I2C_EVENT_TRANSFER_EARLY_NACK;
+ i2c_set_control_reg(i2c_base, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+ i2c_set_control_reg(i2c_base, I2C_CON_START_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ else {
+ event = I2C_EVENT_TRANSFER_COMPLETE;
+ if (obj->i2c.stop) {
+ i2c_set_control_reg(i2c_base, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ }
+ break;
+
+ case 0x38: // Master Arbitration Lost
+ i2c_set_control_reg(i2c_base, I2C_CON_I2C_STS_Msk); // Enter not addressed SLV mode
+ event = I2C_EVENT_ERROR;
+ break;
+
+ case 0x50: // Master Receive Data ACK
+ if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+ uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
+ rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
+ }
+ case 0x40: // Master Receive Address ACK
+ i2c_set_control_reg(i2c_base, I2C_CON_I2C_STS_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CON_ACK_Msk : 0));
+ break;
+
+ case 0x48: // Master Receive Address NACK
+ event = I2C_EVENT_ERROR_NO_SLAVE;
+ if (obj->i2c.stop) {
+ i2c_set_control_reg(i2c_base, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ break;
+
+ case 0x58: // Master Receive Data NACK
+ if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+ uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
+ rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
+ }
+ i2c_set_control_reg(i2c_base, I2C_CON_START_Msk | I2C_CON_I2C_STS_Msk);
+ break;
+
+ case 0x00: // Bus error
+ event = I2C_EVENT_ERROR;
+ i2c_reset(obj);
+ break;
+
+ default:
+ event = I2C_EVENT_ERROR;
+ if (obj->i2c.stop) {
+ i2c_set_control_reg(i2c_base, I2C_CON_STOP_Msk | I2C_CON_I2C_STS_Msk);
+ }
+ }
+
+ if (event) {
+ i2c_teardown_async(obj);
+ }
+
+ return (event & obj->i2c.event);
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{
+ // hdlr_async will get non-NULL for async transfer. Use it to judge if async transfer is on-going.
+ return !! obj->i2c.hdlr_async;
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+ i2c_teardown_async(obj);
+ i2c_stop(obj);
+}
+
+static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
+{
+ obj->tx_buff.buffer = (void *) tx;
+ obj->tx_buff.length = tx_length;
+ obj->tx_buff.pos = 0;
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.length = rx_length;
+ obj->rx_buff.pos = 0;
+}
+
+static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((I2CName) modinit->modname == obj->i2c.i2c);
+
+ if (enable) {
+ NVIC_SetVector(modinit->irq_n, handler);
+ i2c_enable_int(obj);
+ }
+ else {
+ i2c_disable_int(obj);
+ }
+
+}
+
+static void i2c_teardown_async(i2c_t *obj)
+{
+ obj->i2c.hdlr_async = 0;
+}
+
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,227 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "sleep_api.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "mbed_critical.h"
+#include "mbed_wait_api.h"
+
+// lp_ticker tick = us = timestamp
+#define US_PER_TICK (1)
+#define US_PER_SEC (1000 * 1000)
+
+#define US_PER_TMR2_INT (US_PER_SEC * 10)
+#define TMR2_CLK_PER_SEC (__LXT)
+#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
+#define TMR3_CLK_PER_SEC (__LXT)
+
+void TMR2_IRQHandler(void);
+void TMR3_IRQHandler(void);
+static void lp_ticker_arm_cd(void);
+
+static int lp_ticker_inited = 0;
+static volatile uint32_t counter_major = 0;
+static volatile uint32_t cd_major_minor_clks = 0;
+static volatile uint32_t cd_minor_clks = 0;
+static volatile uint32_t wakeup_tick = (uint32_t) -1;
+
+// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
+// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
+static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL2_TMR2_S_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) TMR2_IRQHandler};
+static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL2_TMR3_S_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) TMR3_IRQHandler};
+
+#define TMR_CMP_MIN 2
+#define TMR_CMP_MAX 0xFFFFFFu
+
+void lp_ticker_init(void)
+{
+ if (lp_ticker_inited) {
+ return;
+ }
+ lp_ticker_inited = 1;
+
+ counter_major = 0;
+ cd_major_minor_clks = 0;
+ cd_minor_clks = 0;
+ wakeup_tick = (uint32_t) -1;
+
+ // Reset module
+ SYS_ResetModule(timer2_modinit.rsetidx);
+ SYS_ResetModule(timer3_modinit.rsetidx);
+
+ // Select IP clock source
+ CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
+ CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
+ // Enable IP clock
+ CLK_EnableModuleClock(timer2_modinit.clkidx);
+ CLK_EnableModuleClock(timer3_modinit.clkidx);
+
+ // Configure clock
+ uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+ uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
+ MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
+ uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
+ MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
+ // Continuous mode
+ ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE;
+ ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->PRECNT = prescale_timer2;
+ ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMPR = cmp_timer2;
+
+ // Set vector
+ NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
+ NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
+
+ NVIC_EnableIRQ(timer2_modinit.irq_n);
+ NVIC_EnableIRQ(timer3_modinit.irq_n);
+
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+ TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+
+ // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
+ // timer is not running.
+
+ // Wait 3 cycles of engine clock to ensure previous CTL write action is finish
+ nu_nop(SystemCoreClock / __LXT * 3);
+ // Start timer
+ TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+
+ // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
+ lp_ticker_set_interrupt(wakeup_tick);
+}
+
+timestamp_t lp_ticker_read()
+{
+ if (! lp_ticker_inited) {
+ lp_ticker_init();
+ }
+
+ TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
+
+ do {
+ uint64_t major_minor_clks;
+ uint32_t minor_clks;
+
+ // NOTE: As TIMER_DR = TIMER_CMPR and counter_major has increased by one, TIMER_DR doesn't change to 0 for one tick time.
+ // NOTE: As TIMER_DR = TIMER_CMPR or TIMER_DR = 0, counter_major (ISR) may not sync with TIMER_DR. So skip and fetch stable one at the cost of 1 clock delay on this read.
+ do {
+ core_util_critical_section_enter();
+
+ // NOTE: Order of reading minor_us/carry here is significant.
+ minor_clks = TIMER_GetCounter(timer2_base);
+ uint32_t carry = (timer2_base->ISR & TIMER_ISR_TMR_IS_Msk) ? 1 : 0;
+ // When TIMER_DR approaches TIMER_CMPR and will wrap soon, we may get carry but TIMER_DR not wrapped. Hanlde carefully carry == 1 && TIMER_DR is near TIMER_CMPR.
+ if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
+ major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
+ }
+ else {
+ major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
+ }
+
+ core_util_critical_section_exit();
+ }
+ while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
+
+ // Add power-down compensation
+ return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
+ }
+ while (0);
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+ uint32_t delta = timestamp - lp_ticker_read();
+ wakeup_tick = timestamp;
+
+ TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+ lp_ticker_arm_cd();
+
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+ cd_major_minor_clks = cd_minor_clks = 0;
+ /**
+ * This event was in the past. Set the interrupt as pending, but don't process it here.
+ * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+ */
+ NVIC_SetPendingIRQ(timer3_modinit.irq_n);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+}
+
+void TMR2_IRQHandler(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+ TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+ counter_major ++;
+}
+
+void TMR3_IRQHandler(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
+ if (cd_major_minor_clks == 0) {
+ // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+ lp_ticker_irq_handler();
+ }
+ else {
+ lp_ticker_arm_cd();
+ }
+}
+
+static void lp_ticker_arm_cd(void)
+{
+ TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
+
+ // Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit
+ timer3_base->CTL |= TIMER_CTL_SW_RST_Msk;
+ // One-shot mode, Clock = 1 KHz
+ uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
+ MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
+ uint32_t ctl_timer3 = timer3_base->CTL;
+ ctl_timer3 &= ~TIMER_CTL_MODE_SEL_Msk;
+ ctl_timer3 |= TIMER_ONESHOT_MODE;
+ timer3_base->PRECNT = prescale_timer3;
+
+ cd_minor_clks = cd_major_minor_clks;
+ cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer3_base->CMPR = cd_minor_clks;
+
+ TIMER_EnableInt(timer3_base);
+ TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ // Wait 2 cycles of engine clock to ensure previous CTL write action is finish
+ wait_us(30 * 2);
+ timer3_base->CTL = ctl_timer3 | TIMER_CTL_TMR_EN_Msk;
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_lib.json Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,22 @@
+{
+ "name": "NANO100",
+ "config": {
+ "gpio-irq-debounce-enable": {
+ "help": "Enable GPIO IRQ debounce",
+ "value": 0
+ },
+ "gpio-irq-debounce-enable-list": {
+ "help": "Comma separated pin list to enable GPIO IRQ debounce",
+ "value": "NC"
+ },
+ "gpio-irq-debounce-clock-source": {
+ "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K",
+ "value": "GPIO_DBCLKSRC_IRC10K"
+ },
+
+ "gpio-irq-debounce-sample-rate": {
+ "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
+ "value": "GPIO_DBCLKSEL_16"
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/pinmap.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+
+/**
+ * Configure pin multi-function
+ */
+void pin_function(PinName pin, int data)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+ __IO uint32_t *Px_x_MFP = ((__IO uint32_t *) &SYS->PA_L_MFP) + port_index * 2 + (pin_index / 8);
+ uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
+
+ // E.g.: SYS->PA_L_MFP = (SYS->PA_L_MFP & (~SYS_PA_L_MFP_PA0_MFP_Msk) ) | SYS_PA_L_MFP_PA0_MFP_SC0_CD ;
+ *Px_x_MFP = (*Px_x_MFP & (~MFP_Msk)) | data;
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+ uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+ GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+
+ uint32_t mode_intern = GPIO_PMD_INPUT;
+
+ switch (mode) {
+ case PullUp:
+ mode_intern = GPIO_PMD_INPUT;
+ break;
+
+ case PullDown:
+ case PullNone:
+ // NOTE: Not support
+ return;
+
+ case PushPull:
+ mode_intern = GPIO_PMD_OUTPUT;
+ break;
+
+ case OpenDrain:
+ mode_intern = GPIO_PMD_OPEN_DRAIN;
+ break;
+
+ case Quasi:
+ // NOTE: Not support
+ break;
+ }
+
+ GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/port_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "port_api.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT
+
+PinName port_pin(PortName port, int pin_n)
+{
+ return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+ obj->port = port;
+ obj->mask = mask;
+ obj->direction = dir;
+
+ uint32_t i;
+ obj->direction = dir;
+ for (i = 0; i < GPIO_PIN_MAX; i++) {
+ if (obj->mask & (1 << i)) {
+ gpio_set(port_pin(port, i));
+ }
+ }
+
+ port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+ uint32_t i;
+ obj->direction = dir;
+ for (i = 0; i < GPIO_PIN_MAX; i++) {
+ if (obj->mask & (1 << i)) {
+ if (dir == PIN_OUTPUT) {
+ GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_PMD_OUTPUT);
+ } else { // PIN_INPUT
+ GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_PMD_INPUT);
+ }
+ }
+ }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ uint32_t i;
+
+ for (i = 0; i < GPIO_PIN_MAX; i++) {
+ if (obj->mask & (1 << i)) {
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_write(port_t *obj, int value)
+{
+ uint32_t i;
+ uint32_t port_index = obj->port;
+
+ for (i = 0; i < GPIO_PIN_MAX; i++) {
+ if (obj->mask & (1 << i)) {
+ GPIO_PIN_ADDR(port_index, i) = (value & obj->mask) ? 1 : 0;
+ }
+ }
+}
+
+int port_read(port_t *obj)
+{
+ uint32_t i;
+ uint32_t port_index = obj->port;
+ int value = 0;
+
+ for (i = 0; i < GPIO_PIN_MAX; i++) {
+ if (obj->mask & (1 << i)) {
+ value = value | (GPIO_PIN_ADDR(port_index, i) << i);
+ }
+ }
+
+ return value;
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,211 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+
+struct nu_pwm_var {
+ uint32_t en_msk;
+};
+
+static struct nu_pwm_var pwm0_01_var = {
+ .en_msk = 0
+};
+
+static struct nu_pwm_var pwm0_23_var = {
+ .en_msk = 0
+};
+
+static struct nu_pwm_var pwm1_01_var = {
+ .en_msk = 0
+};
+
+static struct nu_pwm_var pwm1_23_var = {
+ .en_msk = 0
+};
+
+static uint32_t pwm_modinit_mask = 0;
+
+static const struct nu_modinit_s pwm_modinit_tab[] = {
+ {PWM_0_0, PWM0_CH01_MODULE, CLK_CLKSEL1_PWM0_CH01_S_HCLK, 0, PWM0_RST, PWM0_IRQn, &pwm0_01_var},
+ {PWM_0_1, PWM0_CH01_MODULE, CLK_CLKSEL1_PWM0_CH01_S_HCLK, 0, PWM0_RST, PWM0_IRQn, &pwm0_01_var},
+ {PWM_0_2, PWM0_CH23_MODULE, CLK_CLKSEL1_PWM0_CH23_S_HCLK, 0, PWM0_RST, PWM0_IRQn, &pwm0_23_var},
+ {PWM_0_3, PWM0_CH23_MODULE, CLK_CLKSEL1_PWM0_CH23_S_HCLK, 0, PWM0_RST, PWM0_IRQn, &pwm0_23_var},
+
+ {PWM_1_0, PWM1_CH01_MODULE, CLK_CLKSEL2_PWM1_CH01_S_HCLK, 0, PWM1_RST, PWM1_IRQn, &pwm1_01_var},
+ {PWM_1_1, PWM1_CH01_MODULE, CLK_CLKSEL2_PWM1_CH01_S_HCLK, 0, PWM1_RST, PWM1_IRQn, &pwm1_01_var},
+ {PWM_1_2, PWM1_CH23_MODULE, CLK_CLKSEL2_PWM1_CH23_S_HCLK, 0, PWM1_RST, PWM1_IRQn, &pwm1_23_var},
+ {PWM_1_3, PWM1_CH23_MODULE, CLK_CLKSEL2_PWM1_CH23_S_HCLK, 0, PWM1_RST, PWM1_IRQn, &pwm1_23_var},
+
+ {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+static void pwmout_config(pwmout_t* obj);
+
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+ obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
+ MBED_ASSERT((int) obj->pwm != NC);
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((PWMName) modinit->modname == obj->pwm);
+
+ PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
+ uint32_t chn = NU_MODSUBINDEX(obj->pwm);
+
+ // NOTE: Channels 0/1, 2/3 share a clock source.
+ if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0xF) == 0) {
+ // Select clock source of paired channels
+ CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+ // Enable clock of paired channels
+ CLK_EnableModuleClock(modinit->clkidx);
+ }
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+
+ // Default: period = 10 ms, pulse width = 0 ms
+ obj->period_us = 1000 * 10;
+ obj->pulsewidth_us = 0;
+ pwmout_config(obj);
+ // enable inverter to ensure the first PWM cycle is correct
+ pwm_base->CTL |= (PWM_CTL_CH0INV_Msk << (chn * 8));
+
+ // Enable output of the specified PWM channel
+ PWM_EnableOutput(pwm_base, 1 << chn);
+ PWM_Start(pwm_base, 1 << chn);
+
+ ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
+
+ if (((struct nu_pwm_var *) modinit->var)->en_msk) {
+ // Mark this module to be inited.
+ int i = modinit - pwm_modinit_tab;
+ pwm_modinit_mask |= 1 << i;
+ }
+}
+
+void pwmout_free(pwmout_t* obj)
+{
+ PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
+ uint32_t chn = NU_MODSUBINDEX(obj->pwm);
+ PWM_ForceStop(pwm_base, 1 << chn);
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((PWMName) modinit->modname == obj->pwm);
+ ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
+
+
+ if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0xF) == 0) {
+ CLK_DisableModuleClock(modinit->clkidx);
+ }
+
+ if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) {
+ // Mark this module to be deinited.
+ int i = modinit - pwm_modinit_tab;
+ pwm_modinit_mask &= ~(1 << i);
+ }
+}
+
+void pwmout_write(pwmout_t* obj, float value)
+{
+ obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
+ pwmout_config(obj);
+}
+
+float pwmout_read(pwmout_t* obj)
+{
+ return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+ pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+ uint32_t period_us_old = obj->period_us;
+ uint32_t pulsewidth_us_old = obj->pulsewidth_us;
+ obj->period_us = us;
+ obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
+ pwmout_config(obj);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+ obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
+ pwmout_config(obj);
+}
+
+int pwmout_allow_powerdown(void)
+{
+ uint32_t modinit_mask = pwm_modinit_mask;
+ while (modinit_mask) {
+ int pwm_idx = nu_ctz(modinit_mask);
+ const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
+ if (modinit->modname != NC) {
+ PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
+ uint32_t chn = NU_MODSUBINDEX(modinit->modname);
+ // Disallow entering power-down mode if PWM counter is enabled.
+ if (pwm_base->OE & (1 << chn)) {
+ return 0;
+ }
+ }
+ modinit_mask &= ~(1 << pwm_idx);
+ }
+
+ return 1;
+}
+
+static void pwmout_config(pwmout_t* obj)
+{
+ PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
+ uint32_t chn = NU_MODSUBINDEX(obj->pwm);
+ // NOTE: Support period < 1s
+ // NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
+ // 1. Inverse duty cycle (100 - duty)
+ // 2. Inverse PWM output polarity
+ // This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
+ PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - (obj->pulsewidth_us * 100 / obj->period_us), obj->period_us);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,128 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "mbed_wait_api.h"
+#include "mbed_error.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "mbed_mktime.h"
+
+#define YEAR0 1900
+
+
+static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
+
+void rtc_init(void)
+{
+ if (rtc_isenabled()) {
+ return;
+ }
+
+ RTC_Open(NULL);
+}
+
+void rtc_free(void)
+{
+ // N/A
+}
+
+int rtc_isenabled(void)
+{
+ // NOTE: To access (RTC) registers, clock must be enabled first.
+ if (! (CLK->APBCLK & CLK_APBCLK_RTC_EN_Msk)) {
+ // Enable IP clock
+ CLK_EnableModuleClock(rtc_modinit.clkidx);
+ }
+
+ // NOTE: Check RTC Init Active flag to support crossing reset cycle.
+ return !! (RTC->INIR & RTC_INIR_ACTIVE_Msk);
+}
+
+/*
+ struct tm
+ tm_sec seconds after the minute 0-61
+ tm_min minutes after the hour 0-59
+ tm_hour hours since midnight 0-23
+ tm_mday day of the month 1-31
+ tm_mon months since January 0-11
+ tm_year years since 1900
+ tm_wday days since Sunday 0-6
+ tm_yday days since January 1 0-365
+ tm_isdst Daylight Saving Time flag
+*/
+
+time_t rtc_read(void)
+{
+ // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+ // RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+ if (! rtc_isenabled()) {
+ rtc_init();
+ }
+
+ S_RTC_TIME_DATA_T rtc_datetime;
+ RTC_GetDateAndTime(&rtc_datetime);
+
+ struct tm timeinfo;
+
+ // Convert struct tm to S_RTC_TIME_DATA_T
+ timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
+ timeinfo.tm_mon = rtc_datetime.u32Month - 1;
+ timeinfo.tm_mday = rtc_datetime.u32Day;
+ timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
+ timeinfo.tm_hour = rtc_datetime.u32Hour;
+ timeinfo.tm_min = rtc_datetime.u32Minute;
+ timeinfo.tm_sec = rtc_datetime.u32Second;
+
+ // Convert to timestamp
+ time_t t = _rtc_mktime(&timeinfo);
+
+ return t;
+}
+
+void rtc_write(time_t t)
+{
+ if (! rtc_isenabled()) {
+ rtc_init();
+ }
+
+ // Convert timestamp to struct tm
+ struct tm timeinfo;
+ if (_rtc_localtime(t, &timeinfo) == false) {
+ return;
+ }
+
+ S_RTC_TIME_DATA_T rtc_datetime;
+
+ // Convert S_RTC_TIME_DATA_T to struct tm
+ rtc_datetime.u32Year = timeinfo.tm_year + YEAR0;
+ rtc_datetime.u32Month = timeinfo.tm_mon + 1;
+ rtc_datetime.u32Day = timeinfo.tm_mday;
+ rtc_datetime.u32DayOfWeek = timeinfo.tm_wday;
+ rtc_datetime.u32Hour = timeinfo.tm_hour;
+ rtc_datetime.u32Minute = timeinfo.tm_min;
+ rtc_datetime.u32Second = timeinfo.tm_sec;
+ rtc_datetime.u32TimeScale = RTC_CLOCK_24;
+
+ RTC_SetDateAndTime(&rtc_datetime);
+ // Wait 3 cycles of engine clock to ensure previous CTL write action is finish
+ wait_us(30 * 3);
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,1012 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include <string.h>
+#include "cmsis.h"
+#include "mbed_error.h"
+#include "mbed_assert.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "dma_api.h"
+#include "dma.h"
+#endif
+
+struct nu_uart_var {
+ uint32_t ref_cnt; // Reference count of the H/W module
+ serial_t * obj;
+ uint32_t fifo_size_tx;
+ uint32_t fifo_size_rx;
+ void (*vec)(void);
+#if DEVICE_SERIAL_ASYNCH
+ uint8_t pdma_perp_tx;
+ uint8_t pdma_perp_rx;
+#endif
+};
+
+void UART0_IRQHandler(void);
+void UART1_IRQHandler(void);
+static void uart_irq(serial_t *obj);
+
+#if DEVICE_SERIAL_ASYNCH
+static void uart_irq_async(serial_t *obj);
+
+static void uart_dma_handler_tx(uint32_t id, uint32_t event);
+static void uart_dma_handler_rx(uint32_t id, uint32_t event);
+
+static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
+static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
+static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable);
+static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq);
+static int serial_write_async(serial_t *obj);
+static int serial_read_async(serial_t *obj);
+
+static uint32_t serial_rx_event_check(serial_t *obj);
+static uint32_t serial_tx_event_check(serial_t *obj);
+
+static int serial_is_tx_complete(serial_t *obj);
+static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
+
+static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
+static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
+static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
+static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
+static int serial_is_rx_complete(serial_t *obj);
+
+static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
+static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
+#endif
+
+static struct nu_uart_var uart0_var = {
+ .ref_cnt = 0,
+ .obj = NULL,
+ .fifo_size_tx = 16,
+ .fifo_size_rx = 16,
+ .vec = UART0_IRQHandler,
+#if DEVICE_SERIAL_ASYNCH
+ .pdma_perp_tx = PDMA_UART0_TX,
+ .pdma_perp_rx = PDMA_UART0_RX
+#endif
+};
+static struct nu_uart_var uart1_var = {
+ .ref_cnt = 0,
+ .obj = NULL,
+ .fifo_size_tx = 16,
+ .fifo_size_rx = 16,
+ .vec = UART1_IRQHandler,
+#if DEVICE_SERIAL_ASYNCH
+ .pdma_perp_tx = PDMA_UART1_TX,
+ .pdma_perp_rx = PDMA_UART1_RX
+#endif
+};
+
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+static uint32_t uart_modinit_mask = 0;
+
+static const struct nu_modinit_s uart_modinit_tab[] = {
+ {UART_0, UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_UART_CLK_DIVIDER(1), UART0_RST, UART0_IRQn, &uart0_var},
+ {UART_1, UART1_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_UART_CLK_DIVIDER(1), UART1_RST, UART1_IRQn, &uart1_var},
+
+ {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+extern void mbed_sdk_init(void);
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
+ mbed_sdk_init();
+
+ // Determine which UART_x the pins are used for
+ uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+ uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+ // Get the peripheral name (UART_x) from the pins and assign it to the object
+ obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
+ MBED_ASSERT((int)obj->serial.uart != NC);
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+
+ if (! var->ref_cnt) {
+ // Reset this module
+ SYS_ResetModule(modinit->rsetidx);
+
+ // Select IP clock source
+ CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+ // Enable IP clock
+ CLK_EnableModuleClock(modinit->clkidx);
+
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ obj->serial.pin_tx = tx;
+ obj->serial.pin_rx = rx;
+ }
+ var->ref_cnt ++;
+
+ // Configure the UART module and set its baudrate
+ serial_baud(obj, 9600);
+ // Configure data bits, parity, and stop bits
+ serial_format(obj, 8, ParityNone, 1);
+
+ obj->serial.vec = var->vec;
+ obj->serial.irq_en = 0;
+
+#if DEVICE_SERIAL_ASYNCH
+ obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
+ obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
+ obj->serial.event = 0;
+ obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+ obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+#endif
+
+ // For stdio management
+ if (obj->serial.uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+
+ if (var->ref_cnt) {
+ // Mark this module to be inited.
+ int i = modinit - uart_modinit_tab;
+ uart_modinit_mask |= 1 << i;
+ }
+}
+
+void serial_free(serial_t *obj)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+
+ var->ref_cnt --;
+ if (! var->ref_cnt) {
+#if DEVICE_SERIAL_ASYNCH
+ if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+ dma_channel_free(obj->serial.dma_chn_id_tx);
+ obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+ if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+ dma_channel_free(obj->serial.dma_chn_id_rx);
+ obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+#endif
+
+ UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
+
+ UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_IER_RDA_IE_Msk | UART_IER_THRE_IE_Msk | UART_IER_RTO_IE_Msk));
+ NVIC_DisableIRQ(modinit->irq_n);
+
+ // Disable IP clock
+ CLK_DisableModuleClock(modinit->clkidx);
+ }
+
+ if (var->obj == obj) {
+ var->obj = NULL;
+ }
+
+ if (obj->serial.uart == STDIO_UART) {
+ stdio_uart_inited = 0;
+ }
+
+ if (! var->ref_cnt) {
+ // Mark this module to be deinited.
+ int i = modinit - uart_modinit_tab;
+ uart_modinit_mask &= ~(1 << i);
+ }
+}
+
+void serial_baud(serial_t *obj, int baudrate) {
+ // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+ while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
+
+ obj->serial.baudrate = baudrate;
+ UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+ while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
+
+ // TODO: Assert for not supported parity and data bits
+ obj->serial.databits = data_bits;
+ obj->serial.parity = parity;
+ obj->serial.stopbits = stop_bits;
+
+ uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
+ (data_bits == 6) ? UART_WORD_LEN_6 :
+ (data_bits == 7) ? UART_WORD_LEN_7 :
+ UART_WORD_LEN_8;
+ uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
+ (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
+ UART_PARITY_NONE;
+ uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
+ UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
+ 0, // Don't change baudrate
+ databits_intern,
+ parity_intern,
+ stopbits_intern);
+}
+
+#if DEVICE_SERIAL_FC
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+ UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+ // First, disable flow control completely.
+ UART_DisableFlowCtrl(uart_base);
+
+ if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
+ // Check if RTS pin matches.
+ uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
+ MBED_ASSERT(uart_rts == obj->serial.uart);
+ // Enable the pin for RTS function
+ pinmap_pinout(rxflow, PinMap_UART_RTS);
+ // nRTS pin output is low level active
+ uart_base->MCSR |= UART_MCSR_LEV_RTS_Msk;
+ // Set RTS Trigger Level as 8 bytes
+ uart_base->TLCTL = (uart_base->TLCTL & ~UART_TLCTL_RTS_TRI_LEV_Msk) | UART_TLCTL_RTS_TRI_LEV_8BYTES;
+ // Set RX Trigger Level as 8 bytes
+ uart_base->TLCTL = (uart_base->TLCTL & ~UART_TLCTL_RFITL_Msk) | UART_TLCTL_RFITL_8BYTES;
+ // Enable RTS
+ uart_base->CTL |= UART_CTL_AUTO_RTS_EN_Msk;
+ }
+
+ if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
+ // Check if CTS pin matches.
+ uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
+ MBED_ASSERT(uart_cts == obj->serial.uart);
+ // Enable the pin for CTS function
+ pinmap_pinout(txflow, PinMap_UART_CTS);
+ // nCTS pin input is low level active
+ uart_base->MCSR |= UART_MCSR_LEV_CTS_Msk;
+ // Enable CTS
+ uart_base->CTL |= UART_CTL_AUTO_CTS_EN_Msk;
+ }
+}
+
+#endif //DEVICE_SERIAL_FC
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+ while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ obj->serial.irq_handler = (uint32_t) handler;
+ obj->serial.irq_id = id;
+
+ // Restore sync-mode vector
+ obj->serial.async_en = 0;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ obj->serial.irq_en = enable;
+ serial_enable_interrupt(obj, irq, enable);
+}
+
+int serial_getc(serial_t *obj)
+{
+ // TODO: Fix every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
+ while (! serial_readable(obj));
+ int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+
+ // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
+ // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
+ if (obj->serial.ier_msk & (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk)) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk));
+ }
+
+ return c;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ // TODO: Fix every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
+ while (! serial_writable(obj));
+ UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
+
+ // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
+ // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
+ if (obj->serial.ier_msk & UART_IER_THRE_IE_Msk) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_THRE_IE_Msk);
+ }
+}
+
+int serial_readable(serial_t *obj)
+{
+ return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
+}
+
+int serial_writable(serial_t *obj)
+{
+ return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
+}
+
+void serial_pinout_tx(PinName tx)
+{
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+ ((UART_T *) NU_MODBASE(obj->serial.uart))->TLCTL |= UART_TLCTL_BCB_Msk;
+}
+
+void serial_break_clear(serial_t *obj)
+{
+ ((UART_T *) NU_MODBASE(obj->serial.uart))->TLCTL &= ~UART_TLCTL_BCB_Msk;
+}
+
+void UART0_IRQHandler(void)
+{
+#if DEVICE_SERIAL_ASYNCH
+ if (uart0_var.obj->serial.async_en)
+ uart_irq_async(uart0_var.obj);
+ else
+#endif
+ uart_irq(uart0_var.obj);
+}
+
+void UART1_IRQHandler(void)
+{
+#if DEVICE_SERIAL_ASYNCH
+ if (uart1_var.obj->serial.async_en)
+ uart_irq_async(uart1_var.obj);
+ else
+#endif
+ uart_irq(uart1_var.obj);
+}
+
+static void uart_irq(serial_t *obj)
+{
+ UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+ if (uart_base->ISR & (UART_ISR_RDA_IS_Msk | UART_ISR_RTO_IS_Msk)) {
+ // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
+ UART_DISABLE_INT(uart_base, (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk));
+ if (obj->serial.irq_handler) {
+ ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
+ }
+ }
+
+ if (uart_base->ISR & UART_ISR_THRE_IS_Msk) {
+ // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
+ UART_DISABLE_INT(uart_base, UART_IER_THRE_IE_Msk);
+ if (obj->serial.irq_handler) {
+ ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
+ }
+ }
+
+ // NOTE: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
+ uart_base->ISR = uart_base->ISR;
+ uart_base->FSR = uart_base->FSR;
+}
+
+
+#if DEVICE_SERIAL_ASYNCH
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
+
+ obj->serial.dma_usage_tx = hint;
+ serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
+
+ // UART IRQ is necessary for both interrupt way and DMA way
+ serial_tx_enable_event(obj, event, 1);
+ serial_tx_buffer_set(obj, tx, tx_length, tx_width);
+
+ int n_word = 0;
+ if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
+ // Interrupt way
+ n_word = serial_write_async(obj);
+ serial_tx_enable_interrupt(obj, handler, 1);
+ } else {
+ // DMA way
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ dma_enable(obj->serial.dma_chn_id_tx, 1); // Enable this DMA channel
+ PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
+ ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
+ 0, // Scatter-gather disabled
+ 0); // Scatter-gather descriptor address
+ PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
+ (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+ tx_length);
+ PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
+ (uint32_t) tx, // NOTE:
+ // NUC472: End of source address
+ // M451: Start of source address
+ PDMA_SAR_INC, // Source address incremental
+ (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
+ PDMA_DAR_FIX); // Destination address fixed
+ PDMA_EnableInt(obj->serial.dma_chn_id_tx,
+ PDMA_IER_TD_IE_Msk); // Interrupt type
+ // Register DMA event handler
+ dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
+ serial_tx_enable_interrupt(obj, handler, 1);
+ PDMA_Trigger(obj->serial.dma_chn_id_tx);
+ ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL |= UART_CTL_DMA_TX_EN_Msk; // Start DMA transfer
+ }
+
+ return n_word;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+ MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
+
+ obj->serial.dma_usage_rx = hint;
+ serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
+ // DMA doesn't support char match, so fall back to IRQ if it is requested.
+ if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
+ (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
+ char_match != SERIAL_RESERVED_CHAR_MATCH) {
+ obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
+ dma_channel_free(obj->serial.dma_chn_id_rx);
+ obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+
+ // UART IRQ is necessary for both interrupt way and DMA way
+ serial_rx_enable_event(obj, event, 1);
+ serial_rx_buffer_set(obj, rx, rx_length, rx_width);
+ serial_rx_set_char_match(obj, char_match);
+
+ if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
+ // Interrupt way
+ serial_rx_enable_interrupt(obj, handler, 1);
+ } else {
+ // DMA way
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ dma_enable(obj->serial.dma_chn_id_rx, 1); // Enable this DMA channel
+ PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
+ ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
+ 0, // Scatter-gather disabled
+ 0); // Scatter-gather descriptor address
+ PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
+ (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+ rx_length);
+ PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
+ (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
+ PDMA_SAR_FIX, // Source address fixed
+ (uint32_t) rx, // NOTE:
+ // NUC472: End of destination address
+ // M451: Start of destination address
+ PDMA_DAR_INC); // Destination address incremental
+ PDMA_EnableInt(obj->serial.dma_chn_id_rx,
+ PDMA_IER_TD_IE_Msk); // Interrupt type
+ // Register DMA event handler
+ dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
+ serial_rx_enable_interrupt(obj, handler, 1);
+ PDMA_Trigger(obj->serial.dma_chn_id_rx);
+ ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL |= UART_CTL_DMA_RX_EN_Msk; // Start DMA transfer
+ }
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+ // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+ while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
+
+ if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
+ if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+ PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_IER_TD_IE_Msk);
+ // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
+ dma_enable(obj->serial.dma_chn_id_tx, 0);
+ }
+ ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL &= ~UART_CTL_DMA_TX_EN_Msk;
+ }
+
+ // Necessary for both interrupt way and DMA way
+ serial_enable_interrupt(obj, TxIrq, 0);
+ serial_rollback_interrupt(obj, TxIrq);
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+ if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
+ if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+ PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_IER_TD_IE_Msk);
+ // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
+ dma_enable(obj->serial.dma_chn_id_rx, 0);
+ }
+ ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL &= ~UART_CTL_DMA_RX_EN_Msk;
+ }
+
+ // Necessary for both interrupt way and DMA way
+ serial_enable_interrupt(obj, RxIrq, 0);
+ serial_rollback_interrupt(obj, RxIrq);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+ // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ return (obj->serial.async_en);
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+ // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ return (obj->serial.async_en);
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+ int event_rx = 0;
+ int event_tx = 0;
+
+ // Necessary for both interrupt way and DMA way
+ if (serial_is_irq_en(obj, RxIrq)) {
+ event_rx = serial_rx_event_check(obj);
+ if (event_rx) {
+ serial_rx_abort_asynch(obj);
+ }
+ }
+
+ if (serial_is_irq_en(obj, TxIrq)) {
+ event_tx = serial_tx_event_check(obj);
+ if (event_tx) {
+ serial_tx_abort_asynch(obj);
+ }
+ }
+
+ return (obj->serial.event & (event_rx | event_tx));
+}
+
+int serial_allow_powerdown(void)
+{
+ uint32_t modinit_mask = uart_modinit_mask;
+ while (modinit_mask) {
+ int uart_idx = nu_ctz(modinit_mask);
+ const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
+ if (modinit->modname != NC) {
+ UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+ // Disallow entering power-down mode if Tx FIFO has data to flush
+ if (! UART_IS_TX_EMPTY((uart_base))) {
+ return 0;
+ }
+ // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
+ if (uart_base->IER & (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk)) {
+ return 0;
+ }
+ // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
+ if (uart_base->CTL & UART_CTL_DMA_RX_EN_Msk) {
+ return 0;
+ }
+ }
+ modinit_mask &= ~(1 << uart_idx);
+ }
+
+ return 1;
+}
+
+static void uart_irq_async(serial_t *obj)
+{
+ if (serial_is_irq_en(obj, RxIrq)) {
+ (*obj->serial.irq_handler_rx_async)();
+ }
+ if (serial_is_irq_en(obj, TxIrq)) {
+ (*obj->serial.irq_handler_tx_async)();
+ }
+}
+
+static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
+{
+ obj->char_match = char_match;
+ obj->char_found = 0;
+}
+
+static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+ obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
+ obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
+
+}
+
+static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+ obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
+ obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
+
+ if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_RLS_IE_Msk);
+ }
+ if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_RLS_IE_Msk);
+ }
+ if (event & SERIAL_EVENT_RX_OVERFLOW) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_BUF_ERR_IE_Msk);
+ }
+}
+
+static int serial_is_tx_complete(serial_t *obj)
+{
+ // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
+ return (obj->tx_buff.pos == obj->tx_buff.length);
+}
+
+static int serial_is_rx_complete(serial_t *obj)
+{
+ return (obj->rx_buff.pos == obj->rx_buff.length);
+}
+
+static uint32_t serial_tx_event_check(serial_t *obj)
+{
+ UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+ if (uart_base->ISR & UART_ISR_THRE_IS_Msk) {
+ // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
+ UART_DISABLE_INT(uart_base, UART_IER_THRE_IE_Msk);
+ }
+
+ uint32_t event = 0;
+
+ if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
+ serial_write_async(obj);
+ }
+
+ if (serial_is_tx_complete(obj)) {
+ event |= SERIAL_EVENT_TX_COMPLETE;
+ }
+
+ return event;
+}
+
+static uint32_t serial_rx_event_check(serial_t *obj)
+{
+ UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+ if (uart_base->ISR & (UART_ISR_RDA_IS_Msk | UART_ISR_RTO_IS_Msk)) {
+ // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
+ UART_DISABLE_INT(uart_base, (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk));
+ }
+
+ uint32_t event = 0;
+
+ if (uart_base->FSR & UART_FSR_BI_F_Msk) {
+ uart_base->FSR = UART_FSR_BI_F_Msk;
+ }
+ if (uart_base->FSR & UART_FSR_FE_F_Msk) {
+ uart_base->FSR = UART_FSR_FE_F_Msk;
+ event |= SERIAL_EVENT_RX_FRAMING_ERROR;
+ }
+ if (uart_base->FSR & UART_FSR_PE_F_Msk) {
+ uart_base->FSR = UART_FSR_PE_F_Msk;
+ event |= SERIAL_EVENT_RX_PARITY_ERROR;
+ }
+
+ if (uart_base->FSR & UART_FSR_RX_OVER_F_Msk) {
+ uart_base->FSR = UART_FSR_RX_OVER_F_Msk;
+ event |= SERIAL_EVENT_RX_OVERFLOW;
+ }
+
+ if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
+ serial_read_async(obj);
+ }
+
+ if (serial_is_rx_complete(obj)) {
+ event |= SERIAL_EVENT_RX_COMPLETE;
+ }
+ if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
+ event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+ // NOTE: Timing to reset char_found?
+ // by obj->char_found = 0;
+ }
+
+ return event;
+}
+
+static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
+{
+ serial_t *obj = (serial_t *) id;
+
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_ABORT) {
+ }
+ // Expect UART IRQ will catch this transfer done event
+ if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+ obj->tx_buff.pos = obj->tx_buff.length;
+ }
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_TIMEOUT) {
+ }
+
+ uart_irq_async(obj);
+}
+
+static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
+{
+ serial_t *obj = (serial_t *) id;
+
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_ABORT) {
+ }
+ // Expect UART IRQ will catch this transfer done event
+ if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+ obj->rx_buff.pos = obj->rx_buff.length;
+ }
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_TIMEOUT) {
+ }
+
+ uart_irq_async(obj);
+}
+
+static int serial_write_async(serial_t *obj)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+ uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
+ uint32_t tx_fifo_busy = (uart_base->FSR & UART_FSR_TX_POINTER_F_Msk) >> UART_FSR_TX_POINTER_F_Pos;
+ if (uart_base->FSR & UART_FSR_TX_FULL_F_Msk) {
+ tx_fifo_busy = tx_fifo_max;
+ }
+ uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
+ if (tx_fifo_free == 0) {
+ // Simulate clear of the interrupt flag
+ if (obj->serial.ier_msk & UART_IER_THRE_IE_Msk) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_THRE_IE_Msk);
+ }
+ return 0;
+ }
+
+ uint32_t bytes_per_word = obj->tx_buff.width / 8;
+
+ uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
+ int n_words = 0;
+ while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
+ switch (bytes_per_word) {
+ case 4:
+ UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+ UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+ case 2:
+ UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+ case 1:
+ UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+ }
+
+ n_words ++;
+ tx_fifo_free -= bytes_per_word;
+ obj->tx_buff.pos ++;
+ }
+
+ if (n_words) {
+ // Simulate clear of the interrupt flag
+ if (obj->serial.ier_msk & UART_IER_THRE_IE_Msk) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_THRE_IE_Msk);
+ }
+ }
+
+ return n_words;
+}
+
+static int serial_read_async(serial_t *obj)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FSR & UART_FSR_RX_POINTER_F_Msk) >> UART_FSR_RX_POINTER_F_Pos;
+
+ uint32_t bytes_per_word = obj->rx_buff.width / 8;
+
+ uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
+ int n_words = 0;
+ while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
+ switch (bytes_per_word) {
+ case 4:
+ *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+ *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+ case 2:
+ *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+ case 1:
+ *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+ }
+
+ n_words ++;
+ rx_fifo_busy -= bytes_per_word;
+ obj->rx_buff.pos ++;
+
+ if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
+ obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
+ uint8_t *rx_cmp = rx;
+ switch (bytes_per_word) {
+ case 4:
+ rx_cmp -= 2;
+ case 2:
+ rx_cmp --;
+ case 1:
+ rx_cmp --;
+ }
+ if (*rx_cmp == obj->char_match) {
+ obj->char_found = 1;
+ break;
+ }
+ }
+ }
+
+ if (n_words) {
+ // Simulate clear of the interrupt flag
+ if (obj->serial.ier_msk & (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk)) {
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk));
+ }
+ }
+
+ return n_words;
+}
+
+static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
+{
+ obj->tx_buff.buffer = (void *) tx;
+ obj->tx_buff.length = length;
+ obj->tx_buff.pos = 0;
+ obj->tx_buff.width = width;
+}
+
+static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
+{
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.length = length;
+ obj->rx_buff.pos = 0;
+ obj->rx_buff.width = width;
+}
+
+static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ // Necessary for both interrupt way and DMA way
+ // A flag to indicate async mode, and tx/rx handlers can be different.
+ obj->serial.async_en = 1;
+ obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
+ serial_enable_interrupt(obj, TxIrq, enable);
+}
+
+static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ // Necessary for both interrupt way and DMA way
+ // A flag to indicate async mode, and tx/rx handlers can be different.
+ obj->serial.async_en = 1;
+ obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
+ serial_enable_interrupt(obj, RxIrq, enable);
+}
+
+static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ if (enable) {
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
+ NVIC_EnableIRQ(modinit->irq_n);
+
+ struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
+ // Multiple serial S/W objects for single UART H/W module possibly.
+ // Bind serial S/W object to UART H/W module as interrupt is enabled.
+ var->obj = obj;
+
+ switch (irq) {
+ // NOTE: Setting ier_msk first to avoid race condition
+ case RxIrq:
+ obj->serial.ier_msk = obj->serial.ier_msk | (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk);
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk));
+ break;
+ case TxIrq:
+ obj->serial.ier_msk = obj->serial.ier_msk | UART_IER_THRE_IE_Msk;
+ UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_THRE_IE_Msk);
+ break;
+ }
+ }
+ else { // disable
+ switch (irq) {
+ case RxIrq:
+ UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk));
+ obj->serial.ier_msk = obj->serial.ier_msk & ~(UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk);
+ break;
+ case TxIrq:
+ UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_THRE_IE_Msk);
+ obj->serial.ier_msk = obj->serial.ier_msk & ~UART_IER_THRE_IE_Msk;
+ break;
+ }
+ }
+}
+
+static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
+
+ obj->serial.async_en = 0;
+ serial_enable_interrupt(obj, irq, obj->serial.irq_en);
+}
+
+static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
+{
+ if (*dma_usage != DMA_USAGE_NEVER) {
+ if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
+ *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
+ }
+ if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
+ *dma_usage = DMA_USAGE_NEVER;
+ }
+ }
+ else {
+ dma_channel_free(*dma_ch);
+ *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+}
+
+static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
+{
+ int ier_msk = 0;
+
+ switch (irq) {
+ case RxIrq:
+ ier_msk = obj->serial.ier_msk & (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk);
+ break;
+ case TxIrq:
+ ier_msk = obj->serial.ier_msk & UART_IER_THRE_IE_Msk;
+ break;
+ }
+
+ return !! ier_msk;
+}
+
+#endif // #if DEVICE_SERIAL_ASYNCH
+#endif // #if DEVICE_SERIAL
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "sleep_api.h"
+#include "serial_api.h"
+#include "lp_ticker_api.h"
+
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+#include "device.h"
+#include "objects.h"
+#include "PeripheralPins.h"
+
+static void mbed_enter_sleep(struct sleep_s *obj);
+static void mbed_exit_sleep(struct sleep_s *obj);
+
+int serial_allow_powerdown(void);
+int spi_allow_powerdown(void);
+int i2c_allow_powerdown(void);
+int pwmout_allow_powerdown(void);
+
+/**
+ * Enter Idle mode.
+ */
+void hal_sleep(void)
+{
+ struct sleep_s sleep_obj;
+ sleep_obj.powerdown = 0;
+ mbed_enter_sleep(&sleep_obj);
+ mbed_exit_sleep(&sleep_obj);
+}
+
+/**
+ * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
+ */
+void hal_deepsleep(void)
+{
+ struct sleep_s sleep_obj;
+ sleep_obj.powerdown = 1;
+ mbed_enter_sleep(&sleep_obj);
+ mbed_exit_sleep(&sleep_obj);
+}
+
+static void mbed_enter_sleep(struct sleep_s *obj)
+{
+ // Check if serial allows entering power-down mode
+ if (obj->powerdown) {
+ obj->powerdown = serial_allow_powerdown();
+ }
+ // Check if spi allows entering power-down mode
+ if (obj->powerdown) {
+ obj->powerdown = spi_allow_powerdown();
+ }
+ // Check if i2c allows entering power-down mode
+ if (obj->powerdown) {
+ obj->powerdown = i2c_allow_powerdown();
+ }
+ // Check if pwmout allows entering power-down mode
+ if (obj->powerdown) {
+ obj->powerdown = pwmout_allow_powerdown();
+ }
+ // TODO: Check if other peripherals allow entering power-down mode
+
+ if (obj->powerdown) { // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
+ SYS_UnlockReg();
+ CLK_PowerDown();
+ SYS_LockReg();
+ } else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
+ SYS_UnlockReg();
+ CLK_Idle();
+ SYS_LockReg();
+ }
+ __NOP();
+ __NOP();
+ __NOP();
+ __NOP();
+}
+
+static void mbed_exit_sleep(struct sleep_s *obj)
+{
+ (void)obj;
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,844 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "dma_api.h"
+#include "dma.h"
+#endif
+
+#define NU_SPI_FRAME_MIN 8
+#define NU_SPI_FRAME_MAX 32
+#define NU_SPI_FIFO_DEPTH 8
+
+struct nu_spi_var {
+ spi_t * obj;
+ void (*vec)(void);
+#if DEVICE_SPI_ASYNCH
+ uint8_t pdma_perp_tx;
+ uint8_t pdma_perp_rx;
+#endif
+};
+
+// NOTE:
+// NANO130: No support for relocating vector table. ISR vector passed into NVIC_SetVector() can only be weak symbol defined in startup_Nano100Series.c.
+void SPI0_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void SPI2_IRQHandler(void);
+static void spi_irq(spi_t *obj);
+
+static struct nu_spi_var spi0_var = {
+ .obj = NULL,
+ .vec = SPI0_IRQHandler,
+#if DEVICE_SPI_ASYNCH
+ .pdma_perp_tx = PDMA_SPI0_TX,
+ .pdma_perp_rx = PDMA_SPI0_RX
+#endif
+};
+static struct nu_spi_var spi1_var = {
+ .obj = NULL,
+ .vec = SPI1_IRQHandler,
+#if DEVICE_SPI_ASYNCH
+ .pdma_perp_tx = PDMA_SPI1_TX,
+ .pdma_perp_rx = PDMA_SPI1_RX
+#endif
+};
+static struct nu_spi_var spi2_var = {
+ .obj = NULL,
+ .vec = SPI2_IRQHandler,
+#if DEVICE_SPI_ASYNCH
+ .pdma_perp_tx = PDMA_SPI2_TX,
+ .pdma_perp_rx = PDMA_SPI2_RX
+#endif
+};
+
+#if DEVICE_SPI_ASYNCH
+static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
+static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable, uint32_t mask);
+static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
+static uint32_t spi_master_read_asynch(spi_t *obj);
+static uint32_t spi_event_check(spi_t *obj);
+static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
+static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
+static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
+static uint8_t spi_get_data_width(spi_t *obj);
+static int spi_is_tx_complete(spi_t *obj);
+static int spi_is_rx_complete(spi_t *obj);
+static int spi_writeable(spi_t * obj);
+static int spi_readable(spi_t * obj);
+static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
+static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
+#endif
+
+static uint32_t spi_modinit_mask = 0;
+
+static const struct nu_modinit_s spi_modinit_tab[] = {
+ {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0_S_HCLK, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var},
+ {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1_S_HCLK, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var},
+ {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2_S_HCLK, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var},
+
+ {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // Determine which SPI_x the pins are used for
+ uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+ uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+ uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+ // NOTE:
+ // NANO130: Support two-port SPI MOSI/MISO 0/1
+ if (NU_MODBASE(spi_data) == NU_MODBASE(spi_cntl)) {
+ // NOTE: spi_data has subindex(port) encoded but spi_cntl hasn't.
+ obj->spi.spi = (SPIName) spi_data;
+ }
+ else {
+ obj->spi.spi = (SPIName) NC;
+ }
+ MBED_ASSERT((int)obj->spi.spi != NC);
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
+
+ // Reset this module
+ SYS_ResetModule(modinit->rsetidx);
+
+ // Select IP clock source
+ CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+ // Enable IP clock
+ CLK_EnableModuleClock(modinit->clkidx);
+
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+
+ obj->spi.pin_mosi = mosi;
+ obj->spi.pin_miso = miso;
+ obj->spi.pin_sclk = sclk;
+ obj->spi.pin_ssel = ssel;
+
+
+#if DEVICE_SPI_ASYNCH
+ obj->spi.dma_usage = DMA_USAGE_NEVER;
+ obj->spi.event = 0;
+ obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+ obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+#endif
+
+ // Mark this module to be inited.
+ int i = modinit - spi_modinit_tab;
+ spi_modinit_mask |= 1 << i;
+}
+
+void spi_free(spi_t *obj)
+{
+#if DEVICE_SPI_ASYNCH
+ if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+ dma_channel_free(obj->spi.dma_chn_id_tx);
+ obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+ if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+ dma_channel_free(obj->spi.dma_chn_id_rx);
+ obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+#endif
+
+ SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
+ SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOVR_INTEN_MASK | SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK));
+ NVIC_DisableIRQ(modinit->irq_n);
+
+ // Disable IP clock
+ CLK_DisableModuleClock(modinit->clkidx);
+
+ // Mark this module to be deinited.
+ int i = modinit - spi_modinit_tab;
+ spi_modinit_mask &= ~(1 << i);
+}
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
+
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ // NOTE: All configurations should be ready before enabling SPI peripheral.
+ // NOTE: Re-configuration is allowed only as SPI peripheral is idle.
+ // NOTE:
+ // NANO130, SPI_CTL.GO_BUSY always reads as 1 in slave/FIFO mode. So disable FIFO first.
+ SPI_DisableFIFO(spi_base);
+ while (SPI_IS_BUSY(spi_base));
+
+
+ SPI_Open(spi_base,
+ slave ? SPI_SLAVE : SPI_MASTER,
+ (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
+ bits,
+ SPI_GetBusClock(spi_base));
+ // NOTE: Hardcode to be MSB first.
+ SPI_SET_MSB_FIRST(spi_base);
+
+ if (! slave) {
+ // Master
+ if (obj->spi.pin_ssel != NC) {
+ // Configure SS as low active.
+ switch (NU_MODSUBINDEX(obj->spi.spi)) {
+ case 0:
+ SPI_EnableAutoSS(spi_base, SPI_SS0, SPI_SS0_ACTIVE_LOW);
+ break;
+
+ case 1:
+ SPI_EnableAutoSS(spi_base, SPI_SS1, SPI_SS1_ACTIVE_LOW);
+ break;
+ }
+ }
+ else {
+ SPI_DisableAutoSS(spi_base);
+ }
+ }
+ else {
+ // Slave
+ // Configure SS as low active.
+ switch (NU_MODSUBINDEX(obj->spi.spi)) {
+ case 0:
+ spi_base->SSR &= ~SPI_SS0_ACTIVE_HIGH;
+ break;
+ case 1:
+ spi_base->SSR &= ~SPI_SS1_ACTIVE_HIGH;
+ break;
+ }
+ // NOTE:
+ // NANO130: Configure slave select signal to edge-trigger rather than level-trigger
+ spi_base->SSR |= SPI_SSR_SS_LTRIG_Msk;
+ }
+
+ // NOTE:
+ // NANO130: FIFO mode defaults to disabled.
+ SPI_EnableFIFO(spi_base, NU_SPI_FIFO_DEPTH / 2, NU_SPI_FIFO_DEPTH / 2);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ // NANO130, SPI_CTL.GO_BUSY always reads as 1 in slave/FIFO mode. So disable FIFO first.
+ SPI_DisableFIFO(spi_base);
+ while (SPI_IS_BUSY(spi_base));
+
+ SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
+
+ // NOTE:
+ // NANO130: FIFO mode defaults to disabled.
+ SPI_EnableFIFO(spi_base, NU_SPI_FIFO_DEPTH / 2, NU_SPI_FIFO_DEPTH / 2);
+}
+
+
+int spi_master_write(spi_t *obj, int value)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ // NOTE: Data in receive FIFO can be read out via ICE.
+ // NOTE:
+ // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
+ // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
+
+ // Wait for tx buffer empty
+ while(! spi_writeable(obj));
+ uint32_t TX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->TX0) : ((uint32_t) &spi_base->TX1);
+ M32(TX) = value;
+
+ // Wait for rx buffer full
+ while (! spi_readable(obj));
+ uint32_t RX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->RX0) : ((uint32_t) &spi_base->RX1);
+ int value2 = M32(RX);
+
+ return value2;
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+ char *rx_buffer, int rx_length, char write_fill)
+{
+ int total = (tx_length > rx_length) ? tx_length : rx_length;
+
+ for (int i = 0; i < total; i++) {
+ char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+ char in = spi_master_write(obj, out);
+ if (i < rx_length) {
+ rx_buffer[i] = in;
+ }
+ }
+
+ return total;
+}
+
+#if DEVICE_SPISLAVE
+int spi_slave_receive(spi_t *obj)
+{
+ // NOTE:
+ // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
+ // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
+
+ return spi_readable(obj);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ // NOTE:
+ // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
+ // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
+
+ // Wait for rx buffer full
+ while (! spi_readable(obj));
+ uint32_t RX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->RX0) : ((uint32_t) &spi_base->RX1);
+ int value = M32(RX);
+ return value;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ // NOTE:
+ // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
+ // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
+
+ // Wait for tx buffer empty
+ while(! spi_writeable(obj));
+ uint32_t TX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->TX0) : ((uint32_t) &spi_base->TX1);
+ M32(TX) = value;
+}
+#endif
+
+#if DEVICE_SPI_ASYNCH
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+ SPI_SET_DATA_WIDTH(spi_base, bit_width);
+
+ obj->spi.dma_usage = hint;
+ spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
+ uint32_t data_width = spi_get_data_width(obj);
+ // Conditions to go DMA way:
+ // (1) No DMA support for non-8 multiple data width.
+ // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
+ if ((data_width % 8) ||
+ (tx_length < rx_length)) {
+ obj->spi.dma_usage = DMA_USAGE_NEVER;
+ dma_channel_free(obj->spi.dma_chn_id_tx);
+ obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+ dma_channel_free(obj->spi.dma_chn_id_rx);
+ obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+
+ // SPI IRQ is necessary for both interrupt way and DMA way
+ spi_enable_event(obj, event, 1);
+ spi_buffer_set(obj, tx, tx_length, rx, rx_length);
+
+ // NOTE:
+ // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
+ // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
+
+ if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+ // Interrupt way
+ spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
+ spi_enable_vector_interrupt(obj, handler, 1);
+ spi_master_enable_interrupt(obj, 1, SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK);
+ } else {
+ // DMA way
+ const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
+
+ // Configure tx DMA
+ dma_enable(obj->spi.dma_chn_id_tx, 1); // Enable this DMA channel
+ PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
+ ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
+ 0, // Scatter-gather disabled
+ 0); // Scatter-gather descriptor address
+ PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
+ (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+ tx_length);
+ PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
+ (uint32_t) tx, // NOTE:
+ // NUC472: End of source address
+ // M451: Start of source address
+ // NANO130: Start of destination address
+ PDMA_SAR_INC, // Source address incremental
+ NU_MODSUBINDEX(obj->spi.spi) == 0 ? (uint32_t) &spi_base->TX0 : (uint32_t) &spi_base->TX1, // Destination address
+ PDMA_DAR_FIX); // Destination address fixed
+ PDMA_EnableInt(obj->spi.dma_chn_id_tx,
+ PDMA_IER_TD_IE_Msk); // Interrupt type
+ // Register DMA event handler
+ dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
+
+ // Configure rx DMA
+ dma_enable(obj->spi.dma_chn_id_rx, 1); // Enable this DMA channel
+ PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
+ ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
+ 0, // Scatter-gather disabled
+ 0); // Scatter-gather descriptor address
+ PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
+ (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
+ rx_length);
+ PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
+ NU_MODSUBINDEX(obj->spi.spi) == 0 ? (uint32_t) &spi_base->RX0 : (uint32_t) &spi_base->RX1, // Source address
+ PDMA_SAR_FIX, // Source address fixed
+ (uint32_t) rx, // NOTE:
+ // NUC472: End of destination address
+ // M451: Start of destination address
+ // NANO130: Start of destination address
+ PDMA_DAR_INC); // Destination address incremental
+ PDMA_EnableInt(obj->spi.dma_chn_id_rx,
+ PDMA_IER_TD_IE_Msk); // Interrupt type
+ // Register DMA event handler
+ dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
+
+ // Start tx/rx DMA transfer
+ spi_enable_vector_interrupt(obj, handler, 1);
+ // No TX/RX FIFO threshold interrupt
+ spi_master_enable_interrupt(obj, 0, SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK);
+ // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
+ SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+ SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+ PDMA_Trigger(obj->spi.dma_chn_id_rx);
+ PDMA_Trigger(obj->spi.dma_chn_id_tx);
+ }
+}
+
+/**
+ * Abort an SPI transfer
+ * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
+ * transfers
+ * @param[in] obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
+ // Receive FIFO Overrun in case of tx length > rx length on DMA way
+ if (spi_base->STATUS & SPI_STATUS_RX_OVER_RUN_Msk) {
+ spi_base->STATUS = SPI_STATUS_RX_OVER_RUN_Msk;
+ }
+
+ if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+ PDMA_DisableInt(obj->spi.dma_chn_id_tx, PDMA_IER_TD_IE_Msk);
+ // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
+ dma_enable(obj->spi.dma_chn_id_tx, 0);
+ }
+ //SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+ spi_base->DMA &= ~SPI_DMA_TX_DMA_EN_Msk;
+
+ if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+ PDMA_DisableInt(obj->spi.dma_chn_id_rx, PDMA_IER_TD_IE_Msk);
+ // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
+ dma_enable(obj->spi.dma_chn_id_rx, 0);
+ }
+ //SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+ spi_base->DMA &= ~SPI_DMA_RX_DMA_EN_Msk;
+ }
+
+ // Necessary for both interrupt way and DMA way
+ spi_enable_vector_interrupt(obj, 0, 0);
+ spi_master_enable_interrupt(obj, 0, SPI_FIFO_RX_INTEN_MASK | SPI_FIFO_TX_INTEN_MASK);
+
+ // NOTE: SPI H/W may get out of state without the busy check.
+ while (SPI_IS_BUSY(spi_base));
+
+ SPI_ClearRxFIFO(spi_base);
+ SPI_ClearTxFIFO(spi_base);
+}
+
+/**
+ * Handle the SPI interrupt
+ * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way,
+ * it is unlikely that the RX FIFO will overflow.
+ * @param[in] obj The SPI peripheral that generated the interrupt
+ * @return
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+ // Check for SPI events
+ uint32_t event = spi_event_check(obj);
+ if (event) {
+ spi_abort_asynch(obj);
+ }
+
+ return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ return SPI_IS_BUSY(spi_base);
+}
+
+int spi_allow_powerdown(void)
+{
+ uint32_t modinit_mask = spi_modinit_mask;
+ while (modinit_mask) {
+ int spi_idx = nu_ctz(modinit_mask);
+ const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
+ if (modinit->modname != NC) {
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
+ if (SPI_IS_BUSY(spi_base)) {
+ return 0;
+ }
+ }
+ modinit_mask &= ~(1 << spi_idx);
+ }
+
+ return 1;
+}
+
+void SPI0_IRQHandler(void)
+{
+ spi_irq(spi0_var.obj);
+}
+void SPI1_IRQHandler(void)
+{
+ spi_irq(spi1_var.obj);
+}
+void SPI2_IRQHandler(void)
+{
+ spi_irq(spi2_var.obj);
+}
+static void spi_irq(spi_t *obj)
+{
+ if (obj && obj->spi.hdlr_async) {
+ void (*hdlr_async)(void) = (void(*)(void))(obj->spi.hdlr_async);
+ hdlr_async();
+ }
+}
+
+static int spi_writeable(spi_t * obj)
+{
+ // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
+ return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
+}
+
+static int spi_readable(spi_t * obj)
+{
+ return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+}
+
+static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
+{
+ obj->spi.event &= ~SPI_EVENT_ALL;
+ obj->spi.event |= (event & SPI_EVENT_ALL);
+ if (event & SPI_EVENT_RX_OVERFLOW) {
+ SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOVR_INTEN_MASK);
+ }
+}
+
+static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
+{
+ const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
+
+ struct nu_spi_var *var = (struct nu_spi_var *) modinit->var;
+
+ if (enable) {
+ var->obj = obj;
+ obj->spi.hdlr_async = handler;
+ NVIC_SetVector(modinit->irq_n, (uint32_t) var->vec);
+ NVIC_EnableIRQ(modinit->irq_n);
+ }
+ else {
+ NVIC_DisableIRQ(modinit->irq_n);
+ var->obj = NULL;
+ obj->spi.hdlr_async = handler;
+ }
+}
+
+static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable, uint32_t mask)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ // NOTE:
+ // NANO130: SPI_IE_MASK/SPI_STATUS_INTSTS_Msk are for unit transfer IE/EF. Don't get confused.
+ if (enable) {
+ // Enable tx/rx FIFO threshold interrupt
+ SPI_EnableInt(spi_base, mask);
+ }
+ else {
+ SPI_DisableInt(spi_base, mask);
+ }
+}
+
+static uint32_t spi_event_check(spi_t *obj)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+ uint32_t event = 0;
+
+ if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+ uint32_t n_rec = spi_master_read_asynch(obj);
+ spi_master_write_asynch(obj, n_rec);
+ }
+
+ if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
+ event |= SPI_EVENT_COMPLETE;
+ }
+
+ // Receive FIFO Overrun
+ if (spi_base->STATUS & SPI_STATUS_RX_OVER_RUN_Msk) {
+ spi_base->STATUS = SPI_STATUS_RX_OVER_RUN_Msk;
+ // In case of tx length > rx length on DMA way
+ if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+ event |= SPI_EVENT_RX_OVERFLOW;
+ }
+ }
+
+ // Receive Time-Out
+ if (spi_base->STATUS & SPI_STATUS_TIME_OUT_STS_Msk) {
+ spi_base->STATUS = SPI_STATUS_TIME_OUT_STS_Msk;
+ }
+
+ return event;
+}
+
+/**
+ * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
+ * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
+ * @param[in] obj The SPI object on which to operate
+ * @param[in] tx_limit The maximum number of words to send
+ * @return The number of SPI words that have been transfered
+ */
+static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
+{
+ uint32_t n_words = 0;
+ uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
+ uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
+ uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
+ max_tx = NU_MIN(max_tx, tx_limit);
+ uint8_t data_width = spi_get_data_width(obj);
+ uint8_t bytes_per_word = (data_width + 7) / 8;
+ uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+ uint32_t TX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->TX0) : ((uint32_t) &spi_base->TX1);
+
+ while ((n_words < max_tx) && spi_writeable(obj)) {
+ if (spi_is_tx_complete(obj)) {
+ // Transmit dummy as transmit buffer is empty
+ M32(TX) = 0;
+ }
+ else {
+ switch (bytes_per_word) {
+ case 4:
+ M32(TX) = nu_get32_le(tx);
+ tx += 4;
+ break;
+ case 2:
+ M32(TX) = nu_get16_le(tx);
+ tx += 2;
+ break;
+ case 1:
+ M32(TX) = *((uint8_t *) tx);
+ tx += 1;
+ break;
+ }
+
+ obj->tx_buff.pos ++;
+ }
+ n_words ++;
+ }
+
+ //Return the number of words that have been sent
+ return n_words;
+}
+
+/**
+ * Read SPI words out of the RX FIFO
+ * Continues reading words out of the RX FIFO until the following condition is met:
+ * o There are no more words in the FIFO
+ * OR BOTH OF:
+ * o At least as many words as the TX buffer have been received
+ * o At least as many words as the RX buffer have been received
+ * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
+ * @param[in] obj The SPI object on which to operate
+ * @return Returns the number of words extracted from the RX FIFO
+ */
+static uint32_t spi_master_read_asynch(spi_t *obj)
+{
+ uint32_t n_words = 0;
+ uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
+ uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
+ uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
+ uint8_t data_width = spi_get_data_width(obj);
+ uint8_t bytes_per_word = (data_width + 7) / 8;
+ uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+ uint32_t RX = (NU_MODSUBINDEX(obj->spi.spi) == 0) ? ((uint32_t) &spi_base->RX0) : ((uint32_t) &spi_base->RX1);
+
+ while ((n_words < max_rx) && spi_readable(obj)) {
+ if (spi_is_rx_complete(obj)) {
+ // Disregard as receive buffer is full
+ M32(RX);
+ }
+ else {
+ switch (bytes_per_word) {
+ case 4: {
+ uint32_t val = M32(RX);
+ nu_set32_le(rx, val);
+ rx += 4;
+ break;
+ }
+ case 2: {
+ uint16_t val = M32(RX);
+ nu_set16_le(rx, val);
+ rx += 2;
+ break;
+ }
+ case 1:
+ *rx ++ = M32(RX);
+ break;
+ }
+
+ obj->rx_buff.pos ++;
+ }
+ n_words ++;
+ }
+
+ // Return the number of words received
+ return n_words;
+}
+
+static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
+{
+ obj->tx_buff.buffer = (void *) tx;
+ obj->tx_buff.length = tx_length;
+ obj->tx_buff.pos = 0;
+ obj->tx_buff.width = spi_get_data_width(obj);
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.length = rx_length;
+ obj->rx_buff.pos = 0;
+ obj->rx_buff.width = spi_get_data_width(obj);
+}
+
+static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
+{
+ if (*dma_usage != DMA_USAGE_NEVER) {
+ if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
+ *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
+ }
+ if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
+ *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
+ }
+
+ if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
+ *dma_usage = DMA_USAGE_NEVER;
+ }
+ }
+
+ if (*dma_usage == DMA_USAGE_NEVER) {
+ dma_channel_free(*dma_ch_tx);
+ *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
+ dma_channel_free(*dma_ch_rx);
+ *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
+ }
+}
+
+static uint8_t spi_get_data_width(spi_t *obj)
+{
+ SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+
+ uint32_t data_width = ((spi_base->CTL & SPI_CTL_TX_BIT_LEN_Msk) >> SPI_CTL_TX_BIT_LEN_Pos);
+ if (data_width == 0) {
+ data_width = 32;
+ }
+
+ return data_width;
+}
+
+static int spi_is_tx_complete(spi_t *obj)
+{
+ return (obj->tx_buff.pos == obj->tx_buff.length);
+}
+
+static int spi_is_rx_complete(spi_t *obj)
+{
+ return (obj->rx_buff.pos == obj->rx_buff.length);
+}
+
+static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
+{
+ spi_t *obj = (spi_t *) id;
+
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_ABORT) {
+ }
+ // Expect SPI IRQ will catch this transfer done event
+ if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+ obj->tx_buff.pos = obj->tx_buff.length;
+ }
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_TIMEOUT) {
+ }
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
+
+ void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
+ vec();
+}
+
+static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
+{
+ spi_t *obj = (spi_t *) id;
+
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_ABORT) {
+ }
+ // Expect SPI IRQ will catch this transfer done event
+ if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+ obj->rx_buff.pos = obj->rx_buff.length;
+ }
+ // TODO: Pass this error to caller
+ if (event_dma & DMA_EVENT_TIMEOUT) {
+ }
+
+ const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+ MBED_ASSERT(modinit != NULL);
+ MBED_ASSERT((SPIName) modinit->modname == obj->spi.spi);
+
+ void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
+ vec();
+}
+
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,204 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2017 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "us_ticker_api.h"
+#include "sleep_api.h"
+#include "mbed_assert.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "mbed_critical.h"
+
+// us_ticker tick = us = timestamp
+#define US_PER_TICK 1
+#define US_PER_SEC (1000 * 1000)
+
+#define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
+#define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
+
+#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
+#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
+
+#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
+#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
+
+
+void TMR0_IRQHandler(void);
+void TMR1_IRQHandler(void);
+static void us_ticker_arm_cd(void);
+
+static int us_ticker_inited = 0;
+static volatile uint32_t counter_major = 0;
+static volatile uint32_t cd_major_minor_us = 0;
+static volatile uint32_t cd_minor_us = 0;
+
+// NOTE: Choose clock source of timer:
+// 1. HIRC: Be the most accurate but might cause unknown HardFault.
+// 2. HXT: Less accurate and cannot pass mbed-drivers test.
+// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
+static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0, TMR0_RST, TMR0_IRQn, (void *) TMR0_IRQHandler};
+static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1_S_HXT, 0, TMR1_RST, TMR1_IRQn, (void *) TMR1_IRQHandler};
+
+#define TMR_CMP_MIN 2
+#define TMR_CMP_MAX 0xFFFFFFu
+
+void us_ticker_init(void)
+{
+ if (us_ticker_inited) {
+ return;
+ }
+
+ counter_major = 0;
+ cd_major_minor_us = 0;
+ cd_minor_us = 0;
+ us_ticker_inited = 1;
+
+ // Reset IP
+ SYS_ResetModule(timer0hires_modinit.rsetidx);
+ SYS_ResetModule(timer1hires_modinit.rsetidx);
+
+ // Select IP clock source
+ CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
+ CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
+ // Enable IP clock
+ CLK_EnableModuleClock(timer0hires_modinit.clkidx);
+ CLK_EnableModuleClock(timer1hires_modinit.clkidx);
+
+ // Timer for normal counter
+ uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+ uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
+ MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
+ uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
+ MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
+ ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE;
+ ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->PRECNT = prescale_timer0;
+ ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMPR = cmp_timer0;
+
+ NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
+ NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
+
+ NVIC_EnableIRQ(timer0hires_modinit.irq_n);
+ NVIC_EnableIRQ(timer1hires_modinit.irq_n);
+
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+ TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+}
+
+uint32_t us_ticker_read()
+{
+ if (! us_ticker_inited) {
+ us_ticker_init();
+ }
+
+ TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
+
+ do {
+ uint32_t major_minor_us;
+ uint32_t minor_us;
+
+ // NOTE: As TIMER_DR = TIMER_CMPR and counter_major has increased by one, TIMER_DR doesn't change to 0 for one tick time.
+ // NOTE: As TIMER_DR = TIMER_CMPR or TIMER_DR = 0, counter_major (ISR) may not sync with TIMER_DR. So skip and fetch stable one at the cost of 1 clock delay on this read.
+ do {
+ core_util_critical_section_enter();
+
+ // NOTE: Order of reading minor_us/carry here is significant.
+ minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
+ uint32_t carry = (timer0_base->ISR & TIMER_ISR_TMR_IS_Msk) ? 1 : 0;
+ // When TIMER_DR approaches TIMER_CMPR and will wrap soon, we may get carry but TIMER_DR not wrapped. Hanlde carefully carry == 1 && TIMER_DR is near TIMER_CMPR.
+ if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
+ major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
+ }
+ else {
+ major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
+ }
+
+ core_util_critical_section_exit();
+ }
+ while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
+
+ return (major_minor_us / US_PER_TICK);
+ }
+ while (0);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+
+ uint32_t delta = timestamp - us_ticker_read();
+ cd_major_minor_us = delta * US_PER_TICK;
+ us_ticker_arm_cd();
+}
+
+void us_ticker_fire_interrupt(void)
+{
+ cd_major_minor_us = cd_minor_us = 0;
+ NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
+}
+
+void TMR0_IRQHandler(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+ counter_major ++;
+}
+
+void TMR1_IRQHandler(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+ cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
+ if (cd_major_minor_us == 0) {
+ // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
+ us_ticker_irq_handler();
+ }
+ else {
+ us_ticker_arm_cd();
+ }
+}
+
+static void us_ticker_arm_cd(void)
+{
+ TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname);
+
+ cd_minor_us = cd_major_minor_us;
+
+ // Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit
+ timer1_base->CTL |= TIMER_CTL_SW_RST_Msk;
+ // One-shot mode, Clock = 1 MHz
+ uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+ uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
+ MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0);
+ timer1_base->CTL &= ~TIMER_CTL_MODE_SEL_Msk;
+ timer1_base->CTL |= TIMER_ONESHOT_MODE;
+ timer1_base->PRECNT = prescale_timer1;
+
+ uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK;
+ cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer1_base->CMPR = cmp_timer1;
+
+ TIMER_EnableInt(timer1_base);
+ TIMER_Start(timer1_base);
+}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -9,13 +9,17 @@
extern "C" {
#endif
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
struct __initial_stackheap r;
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/sys.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -9,13 +9,17 @@
extern "C" {
#endif
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
struct __initial_stackheap r;
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis.h Mon Oct 02 15:33:19 2017 +0100 @@ -22,7 +22,7 @@ // Support linker-generated symbol as start of relocated vector table. -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; #elif defined(__ICCARM__)
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -19,7 +19,7 @@ #define NVIC_NUM_VECTORS (16 + 142) -#if defined(__CC_ARM) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) #elif defined(__ICCARM__) # pragma section = "IRAMVEC"
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c Mon Oct 02 15:33:19 2017 +0100
@@ -47,7 +47,7 @@
/* Initialize segments */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern void __main(void);
#elif defined(__ICCARM__)
@@ -232,7 +232,7 @@
WEAK_ALIAS_FUNC(CRC_IRQHandler, Default_Handler) // 141: CRC
/* Vector table */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__attribute__ ((section("RESET")))
const uint32_t __vector_handlers[] = {
#elif defined(__ICCARM__)
@@ -244,7 +244,7 @@
#endif
/* Configure Initial Stack Pointer, using linker-generated symbols */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
(uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
#elif defined(__ICCARM__)
//(uint32_t) __sfe("CSTACK"),
@@ -439,7 +439,7 @@
/* Enable register write-protection function */
SYS_LockReg();
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__main();
#elif defined(__ICCARM__)
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -144,31 +144,23 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t now = lp_ticker_read();
+ uint32_t delta = timestamp - lp_ticker_read();
wakeup_tick = timestamp;
TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-
+ cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+ lp_ticker_arm_cd();
+
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+ cd_major_minor_clks = cd_minor_clks = 0;
/**
- * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
- * Conditions in which delta is negative:
- * 1. Wrap around
- * 2. Newly scheduled alarm is behind now
- */
- //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
- int delta = (int) (timestamp - now);
- if (delta > 0) {
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
- }
- else {
- cd_major_minor_clks = cd_minor_clks = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
- }
+ * This event was in the past. Set the interrupt as pending, but don't process it here.
+ * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+ */
+ NVIC_SetPendingIRQ(timer3_modinit.irq_n);
}
void lp_ticker_disable_interrupt(void)
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -149,19 +149,15 @@
{
TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- int delta = (int) (timestamp - us_ticker_read());
- if (delta > 0) {
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
- }
- else {
- cd_major_minor_us = cd_minor_us = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
- }
+ uint32_t delta = timestamp - us_ticker_read();
+ cd_major_minor_us = delta * US_PER_TICK;
+ us_ticker_arm_cd();
+}
+
+void us_ticker_fire_interrupt(void)
+{
+ cd_major_minor_us = cd_minor_us = 0;
+ NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
}
static void tmr0_vec(void)
--- a/targets/TARGET_NUVOTON/mbed_rtx.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NUVOTON/mbed_rtx.h Mon Oct 02 15:33:19 2017 +0100
@@ -21,7 +21,7 @@
#if defined(TARGET_NUVOTON)
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
--- a/targets/TARGET_NUVOTON/nu_bitutil.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NUVOTON/nu_bitutil.h Mon Oct 02 15:33:19 2017 +0100 @@ -17,6 +17,9 @@ #ifndef NU_BIT_UTIL_H #define NU_BIT_UTIL_H +#if defined(__ICCARM__) && defined(TARGET_M0) +#include <arm_math.h> +#endif #include "cmsis.h" #ifdef __cplusplus
--- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC11U6X/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11U6X/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -53,6 +53,11 @@
US_TICKER_TIMER->MCR |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CS/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-#include "cmsis.h"
-#include <sys/types.h>
-#include <errno.h>
-
-extern "C" {
-
-struct SCS3Regions {
- unsigned long Dummy;
- unsigned long* InitRam;
- unsigned long* StartRam;
- unsigned long InitSizeRam;
- unsigned long ZeroSizeRam;
-};
-
-extern unsigned long __cs3_regions;
-extern unsigned long __cs3_heap_start;
-
-int main(void);
-void __libc_init_array(void);
-void exit(int ErrorCode);
-
-static void *heap_pointer = NULL;
-
-void __cs3_start_c(void) {
- static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
- unsigned long* pulDest;
- unsigned long* pulSrc;
- unsigned long ByteCount;
- unsigned long i;
-
- pulSrc = pCS3Regions->InitRam;
- pulDest = pCS3Regions->StartRam;
- ByteCount = pCS3Regions->InitSizeRam;
- if (pulSrc != pulDest) {
- for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
- *(pulDest++) = *(pulSrc++);
- }
- } else {
- pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
- }
-
- ByteCount = pCS3Regions->ZeroSizeRam;
- for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
- *(pulDest++) = 0;
- }
-
- heap_pointer = &__cs3_heap_start;
- __libc_init_array();
- exit(main());
-}
-
-int _kill(int pid, int sig) {
- errno = EINVAL;
- return -1;
-}
-
-void _exit(int status) {
- exit(status);
-}
-
-int _getpid(void) {
- return 1;
-}
-
-void *_sbrk(unsigned int incr) {
- void *mem;
-
- unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
- if (next > __get_MSP()) {
- mem = NULL;
- } else {
- mem = (void *)heap_pointer;
- }
- heap_pointer = (void *)next;
-
- return mem;
-}
-
-}
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -53,6 +53,11 @@
US_TICKER_TIMER->MCR |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_CS/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-#include "cmsis.h"
-#include <sys/types.h>
-#include <errno.h>
-
-extern "C" {
-
-struct SCS3Regions {
- unsigned long Dummy;
- unsigned long* InitRam;
- unsigned long* StartRam;
- unsigned long InitSizeRam;
- unsigned long ZeroSizeRam;
-};
-
-extern unsigned long __cs3_regions;
-extern unsigned long __cs3_heap_start;
-
-int main(void);
-void __libc_init_array(void);
-void exit(int ErrorCode);
-
-static void *heap_pointer = NULL;
-
-void __cs3_start_c(void) {
- static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
- unsigned long* pulDest;
- unsigned long* pulSrc;
- unsigned long ByteCount;
- unsigned long i;
-
- pulSrc = pCS3Regions->InitRam;
- pulDest = pCS3Regions->StartRam;
- ByteCount = pCS3Regions->InitSizeRam;
- if (pulSrc != pulDest) {
- for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
- *(pulDest++) = *(pulSrc++);
- }
- } else {
- pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
- }
-
- ByteCount = pCS3Regions->ZeroSizeRam;
- for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
- *(pulDest++) = 0;
- }
-
- heap_pointer = &__cs3_heap_start;
- __libc_init_array();
- exit(main());
-}
-
-int _kill(int pid, int sig) {
- errno = EINVAL;
- return -1;
-}
-
-void _exit(int status) {
- exit(status);
-}
-
-int _getpid(void) {
- return 1;
-}
-
-void *_sbrk(unsigned int incr) {
- void *mem;
-
- unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
- if (next > __get_MSP()) {
- mem = NULL;
- } else {
- mem = (void *)heap_pointer;
- }
- heap_pointer = (void *)next;
-
- return mem;
-}
-
-}
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -53,6 +53,11 @@
US_TICKER_TIMER->MCR |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
--- a/targets/TARGET_NXP/TARGET_LPC13XX/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC13XX/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC13XX/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC13XX/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -53,6 +53,11 @@
US_TICKER_TIMER->MCR |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
--- a/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC15XX/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC15XX/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -72,6 +72,11 @@
LPC_SCT3->EVEN = (1 << 0);
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
// Disable interrupt on SCT3 event 0
LPC_SCT3->EVEN = 0;
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CS/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,80 +0,0 @@
-#include "cmsis.h"
-#include <sys/types.h>
-#include <errno.h>
-
-extern "C" {
-
-struct SCS3Regions {
- unsigned long Dummy;
- unsigned long* InitRam;
- unsigned long* StartRam;
- unsigned long InitSizeRam;
- unsigned long ZeroSizeRam;
-};
-
-extern unsigned long __cs3_regions;
-extern unsigned long __cs3_heap_start;
-
-int main(void);
-void __libc_init_array(void);
-void exit(int ErrorCode);
-
-static void *heap_pointer = NULL;
-
-void __cs3_start_c(void) {
- static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
- unsigned long* pulDest;
- unsigned long* pulSrc;
- unsigned long ByteCount;
- unsigned long i;
-
- pulSrc = pCS3Regions->InitRam;
- pulDest = pCS3Regions->StartRam;
- ByteCount = pCS3Regions->InitSizeRam;
- if (pulSrc != pulDest) {
- for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
- *(pulDest++) = *(pulSrc++);
- }
- } else {
- pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
- }
-
- ByteCount = pCS3Regions->ZeroSizeRam;
- for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
- *(pulDest++) = 0;
- }
-
- heap_pointer = &__cs3_heap_start;
- __libc_init_array();
-
- exit(main());
-}
-
-int _kill(int pid, int sig) {
- errno = EINVAL;
- return -1;
-}
-
-void _exit(int status) {
- exit(status);
-}
-
-int _getpid(void) {
- return 1;
-}
-
-void *_sbrk(unsigned int incr) {
- void *mem;
-
- unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
- if (next > __get_MSP()) {
- mem = NULL;
- } else {
- mem = (void *)heap_pointer;
- }
- heap_pointer = (void *)next;
-
- return mem;
-}
-
-}
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf Mon Oct 02 15:33:19 2017 +0100 @@ -9,7 +9,7 @@ define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; define symbol __ICFEDIT_region_NVIC_end__ = 0x100000C7; define symbol __ICFEDIT_region_RAM_start__ = 0x100000C8; -define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF; +define symbol __ICFEDIT_region_RAM_end__ = 0x10007FE0; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -13,55 +13,169 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
+#if DEVICE_FLASH
+#include "mbed_critical.h"
#include "flash_api.h"
-#include "platform/mbed_critical.h"
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include <stdlib.h>
+#include <string.h>
+
+#define MEMMAP (*((volatile unsigned long *) 0x400FC040))
-// This file is automatically generated
+#define PLL0CON (*((volatile unsigned long *) 0x400FC080))
+#define PLL0CFG (*((volatile unsigned long *) 0x400FC084))
+#define PLL0STAT (*((volatile unsigned long *) 0x400FC088))
+#define PLL0FEED (*((volatile unsigned long *) 0x400FC08C))
+#define CCLKSEL (*((volatile unsigned long *) 0x400FC104))
+#define CLKSRCSEL (*((volatile unsigned long *) 0x400FC10C))
+
+#define STACK_SIZE 64 // Stack Size
-#if DEVICE_FLASH
+#define SET_VALID_CODE 1 // Set Valid User Code Signature
+/* IAP Call */
+typedef void (*IAP_Entry) (unsigned long *cmd, unsigned long *stat);
+#define IAP_Call ((IAP_Entry) 0x1FFF1FF1)
+
+typedef struct flash_s flash_t;
+unsigned long CCLK; // CCLK in kHz
-#include "flash_data.h"
+struct sIAP { // IAP Structure
+ unsigned long cmd;// Command
+ unsigned long par[4];// Parameters
+ unsigned long stat;// Status
+ unsigned long res[2];// Result
+}IAP;
+
+/*
+ * Get Sector Number
+ * Parameter: address: Sector Address
+ * Return Value: Sector Number
+ */
-// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
-static uint32_t FLASH_ALGO[] = {
- 0x28100b00, 0x210ed302, 0x00d0eb01, 0xf44f4770, 0xfbb1707a, 0x4933f0f0, 0x60084449, 0x20014932,
- 0x20006408, 0x20004770, 0xe92d4770, 0xf7ff41f0, 0x4d2effe7, 0x444d4604, 0xe9c52032, 0xf1050400,
- 0x4e2b0114, 0x4628460f, 0x47b060ac, 0xb9686968, 0xe9c52034, 0x48230400, 0x444860ac, 0x68004639,
- 0x462860e8, 0x696847b0, 0xd0002800, 0xe8bd2001, 0xe92d81f0, 0x461441f0, 0xd10e0006, 0x0100e9d4,
- 0xe9d44408, 0x44111202, 0x69214408, 0x69614408, 0x69a14408, 0x42404408, 0x463061e0, 0xffb0f7ff,
- 0x21324d12, 0x4f12444d, 0x1000e9c5, 0x0114f105, 0x468860a8, 0x47b84628, 0xb9806968, 0xe9c52033,
- 0xf44f0600, 0xe9c56080, 0x48064002, 0x44484641, 0x61286800, 0x47b84628, 0x28006968, 0x2001d0c7,
- 0x0000e7c5, 0x00000004, 0x400fc000, 0x00000008, 0x1fff1ff1, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-};
+unsigned long GetSecNum (unsigned long address)
+{
+ unsigned long n;
+
+ n = address >> 12; // 4kB Sector
+ if (n >= 0x10) {
+ n = 0x0E + (n >> 3); // 32kB Sector
+ }
+
+ return (n); // Sector Number
+}
+int32_t flash_init(flash_t *obj)
+{
+ CCLK = SystemCoreClock / 1000; // CCLK value is in kHz, clk in Hz
+
+ MEMMAP = 0x01;// User Flash Mode
+
+ return (0);
+}
+
+int32_t flash_free(flash_t *obj)
+{
+ return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+ unsigned long n;
+
+ n = GetSecNum(address); // Get Sector Number
+
+ core_util_critical_section_enter();
+ IAP.cmd = 50;// Prepare Sector for Erase
+ IAP.par[0] = n;// Start Sector
+ IAP.par[1] = n;// End Sector
+ IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+ if (IAP.stat) {
+ return (1); // Command Failed
+ }
-static const flash_algo_t flash_algo_config = {
- .init = 0xf,
- .uninit = 0x27,
- .erase_sector = 0x2b,
- .program_page = 0x73,
- .static_base = 0xf4,
- .algo_blob = FLASH_ALGO
-};
+ IAP.cmd = 52; // Erase Sector
+ IAP.par[0] = n;// Start Sector
+ IAP.par[1] = n;// End Sector
+ IAP.par[2] = CCLK;// CCLK in kHz
+ IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+ core_util_critical_section_exit();
+ if (IAP.stat) {
+ return (1); // Command Failed
+ }
+
+ return (0); // Finished without Errors
+
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address,
+ const uint8_t *data, uint32_t size)
+{
+ unsigned long n;
+ // always malloc outside critical section
+ uint8_t *alignedData = malloc(size);
+
+ n = GetSecNum(address); // Get Sector Number
+
+ core_util_critical_section_enter();
+ IAP.cmd = 50;// Prepare Sector for Write
+ IAP.par[0] = n;// Start Sector
+ IAP.par[1] = n;// End Sector
+ IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+ if (IAP.stat) {
+ return (1); // Command Failed
+ }
+
+ IAP.cmd = 51; // Copy RAM to Flash
+ IAP.par[0] = address;// Destination Flash Address
-static const sector_info_t sectors_info[] = {
- {0x0, 0x1000},
- {0x10000, 0x8000},
-};
+ if ((unsigned long)data%4==0) { // Word boundary
+ IAP.par[1] = (unsigned long)data;// Source RAM Address
+ } else {
+ memcpy(alignedData,data,size);
+ IAP.par[1] = (unsigned long)alignedData; // Source RAM Address
+ }
+
+ IAP.par[2] = 1024; // Fixed Page Size
+ IAP.par[3] = CCLK;// CCLK in kHz
+ IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+ core_util_critical_section_exit();
+
+ if(alignedData !=0) { // We allocated our own memory
+ free(alignedData);
+ }
+
+ if (IAP.stat) {
+ return (1); // Command Failed
+ }
+ return (0); // Finished without Errors
+}
-static const flash_target_config_t flash_target_config = {
- .page_size = 0x400,
- .flash_start = 0x0,
- .flash_size = 0x80000,
- .sectors = sectors_info,
- .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
-};
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+ if (address < flash_get_start_address(obj) || address >= flash_get_start_address(obj) +flash_get_size(obj)) {
+ return MBED_FLASH_INVALID_SIZE;
+ }
+ if(GetSecNum(address)>=0x10) {
+ return 0x8000;
+ } else {
+ return 0x1000;
+ }
+}
-void flash_set_target_config(flash_t *obj)
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+ return 1024;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
{
- obj->flash_algo = &flash_algo_config;
- obj->target_config = &flash_target_config;
+ return LPC_FLASH_BASE;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+ return 0x80000;
}
#endif
--- a/targets/TARGET_NXP/TARGET_LPC176X/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -71,6 +71,10 @@
LPC_SSP_TypeDef *spi;
};
+struct flash_s {
+ /* nothing to be stored for now */
+ uint32_t dummy;
+};
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_NXP/TARGET_LPC176X/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -55,6 +55,11 @@
US_TICKER_TIMER->MCR |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
--- a/targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-#include "sys_helper.h"
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit - __reserved_stack_size();
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC408X/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -55,6 +55,11 @@
US_TICKER_TIMER->MCR |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -55,6 +55,11 @@
US_TICKER_TIMER->MCR |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
US_TICKER_TIMER->MCR &= ~1;
}
--- a/targets/TARGET_NXP/TARGET_LPC81X/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -110,6 +110,11 @@
LPC_MRT->CTRL1 |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
//Disable Timestamped interrupts triggered by TIMER1
void us_ticker_disable_interrupt() {
//Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
--- a/targets/TARGET_NXP/TARGET_LPC82X/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -86,6 +86,11 @@
LPC_MRT->CTRL1 |= 1;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
//Disable Timestamped interrupts triggered by TIMER1
void us_ticker_disable_interrupt() {
//Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#if defined(__CC_ARM) -extern uint32_t Image$$VECTOR_RAM$$Base[]; -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#else -extern uint32_t __VECTOR_RAM[]; -#endif - -/* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 40) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM - -#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_common.c Mon Oct 02 15:33:19 2017 +0100
@@ -58,7 +58,7 @@
void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#if defined(__CC_ARM) -extern uint32_t Image$$VECTOR_RAM$$Base[]; -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#else -extern uint32_t __VECTOR_RAM[]; -#endif - -/* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 57) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM - -#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c Mon Oct 02 15:33:19 2017 +0100
@@ -72,7 +72,7 @@
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +extern uint32_t Image$$VECTOR_RAM$$Base[]; +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#else +extern uint32_t __VECTOR_RAM[]; +#endif + +/* Symbols defined by the linker script */ +#define NVIC_NUM_VECTORS (16 + 57) // CORE + MCU Peripherals +#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM + +#endif
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -58,6 +58,11 @@
fRtcSetInterrupt(timestamp);
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(Rtc_IRQn);
+}
+
/** Disable low power ticker interrupt
*
*/
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -128,6 +128,11 @@
return retval;
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(Tim0_IRQn);
+}
+
/*******************************************************************************
* Event Timer
*
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c Mon Oct 02 15:33:19 2017 +0100
@@ -125,17 +125,6 @@
{
uint64_t current_time = fRtcRead();
- /* compute delta between current time and timestamp.
- * Note: the current time used to compute the delta is relative (truncated
- * to 32 bits).
- */
- int32_t delta = timestamp - (uint32_t) current_time;
- if (delta <= 0) {
- // event considered in the past, set the interrupt as pending.
- NVIC_SetPendingIRQ(Rtc_IRQn);
- return;
- }
-
uint64_t full_timestamp = (current_time & ~UINT32_MAX) | timestamp;
if ( (uint32_t)current_time > timestamp) {
full_timestamp += ((uint64_t) UINT32_MAX) + 1;
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c Mon Oct 02 15:33:19 2017 +0100
@@ -64,6 +64,8 @@
/** Enter into deep sleep mode */
__ISB();
__WFI();
+ __NOP();
+ __NOP();
/** Wait for the external 32MHz to be power-ed up & running
* Re-power down the 32MHz internal osc
@@ -115,4 +117,4 @@
fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */
}
-#endif /* DEVICE_SLEEP */
\ No newline at end of file
+#endif /* DEVICE_SLEEP */
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -144,6 +144,10 @@
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
+void us_ticker_fire_interrupt(void) {
+ GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
}
--- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -130,6 +130,10 @@
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
+void us_ticker_fire_interrupt(void) {
+ GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void) {
GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -28,7 +28,7 @@
#include "osdep_service.h"
typedef struct _wifi_scan_hdl {
- void *scan_sema;
+ _sema scan_sema;
nsapi_size_t ap_num;
nsapi_size_t scan_num;
WiFiAccessPoint *ap_details;
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Mon Oct 02 15:33:19 2017 +0100
@@ -19,18 +19,9 @@
ER_IRAM +0 FIXED {
*rtl8195a_crypto.o (+RO)
- * (i.mbedtls*)
+ *(i.mbedtls*)
*libc.a (+RO)
-
- *rtx_*.o (+RO)
- *Ticker.o (+RO)
- *Timeout.o (+RO)
- *rtx_timer.o (+RO)
- *TimerEvent.o (+RO)
- *mbed_ticker_api.o (+RO)
- *mbed_critical.o (+RO)
- *us_ticker.o (+RO)
-
+ *rtx_*.o (+RO)
*lib_peripheral_mbed_arm.ar (+RO)
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,31 @@ +; +; Copyright (c) 2017 Realtek Semiconductor Corp. +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + + PRESERVE8 + THUMB + + AREA |i.PLAT_Start|, CODE, READONLY + +PLAT_Start PROC + + EXPORT PLAT_Start + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + IMPORT PLAT_Init + LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =PLAT_Init + BX R0 + ENDP + ALIGN + END
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM2$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM2$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld Mon Oct 02 15:33:19 2017 +0100
@@ -70,15 +70,7 @@
*rtl8195a_crypto.o (.text* .rodata*)
*mbedtls*.o (.text* .rodata*)
*libc.a: (.text* .rodata*)
- *Ticker.o (.text*)
- *Timeout.o (.text*)
- *TimerEvent.o (.text*)
- *mbed_ticker_api.o (.text*)
- *mbed_critical.o (.text*)
- *us_ticker.o (.text*)
-
*lib_peripheral_mbed_gcc.a: (.text*)
-
} > SRAM1
.text.sram2 :
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + .syntax unified + .thumb + + .global __StackTop + .global PLAT_Init + + /* entry point of application image */ + .section .text.PLAT_Start + .weak PLAT_Start + .type PLAT_Start, %function +PLAT_Start: + ldr sp, =__StackTop + ldr r0, =PLAT_Init + bx r0 + .size PLAT_Start, .-PLAT_Start + .end
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf Mon Oct 02 15:33:19 2017 +0100
@@ -213,13 +213,6 @@
define block .sram1.text with fixed order {
block MBEDTLS_TEXT,
- section .text* object Ticker.o,
- section .text* object Timeout.o,
- section .text* object TimerEvent.o,
- section .text* object mbed_ticker_api.o,
- section .text* object mbed_critical.o,
- section .text* object us_ticker.o,
-
section .text* object lib_peripheral_mbed_iar.a,
};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,31 @@ +; +; Copyright (c) 2017 Realtek Semiconductor Corp. +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + + MODULE ?cstartup + + SECTION .text:CODE:NOROOT:REORDER(2) + EXTERN CSTACK$$Limit + EXTERN PLAT_Init + + ; Default image 2 entry + THUMB + PUBWEAK PLAT_Start + +PLAT_Start + LDR SP, =CSTACK$$Limit + LDR R0, =PLAT_Init + BX R0 + + END
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h Mon Oct 02 15:33:19 2017 +0100 @@ -29,6 +29,12 @@ #define __romcall #define __longcall +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#ifndef __longcall +#define __longcall +#endif + #elif defined(__CC_ARM) #ifndef __longcall
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Mon Oct 02 15:33:19 2017 +0100
@@ -17,6 +17,8 @@
#if defined(__CC_ARM)
#include "cmsis_armcc.h"
+#elif (defined(__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
#elif defined(__GNUC__)
#include "cmsis_gcc.h"
#else
@@ -27,7 +29,6 @@
#if defined(__CC_ARM) || \
(defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
@@ -40,13 +41,11 @@
#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
#define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
-#define __stackp Image$$ARM_LIB_STACK$$ZI$$Limit
#elif defined (__ICCARM__)
#pragma section=".ram.bss"
-extern uint32_t CSTACK$$Limit;
uint8_t *__bss_start__;
uint8_t *__bss_end__;
@@ -55,12 +54,9 @@
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
}
-#define __stackp CSTACK$$Limit
#else
-extern uint32_t __StackTop;
-extern uint32_t __StackLimit;
extern uint8_t __bss_sram_start__[];
extern uint8_t __bss_sram_end__[];
extern uint8_t __bss_dtcm_start__[];
@@ -68,7 +64,6 @@
extern uint8_t __bss_dram_start__[];
extern uint8_t __bss_dram_end__[];
-#define __stackp __StackTop
#endif
extern VECTOR_Func NewVectorTable[];
@@ -173,16 +168,19 @@
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
// Image2 Entry Function
-void PLAT_Start(void)
+void PLAT_Init(void)
{
uint32_t val;
-#if defined (__ICCARM__)
- __iar_data_init_app();
+ // Overwrite vector table
+ NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
+#if defined ( __ICCARM__ )
+ NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
#endif
// Clear RAM BSS
#if defined (__ICCARM__)
+ __iar_data_init_app();
__rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
#else
__rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
@@ -190,14 +188,6 @@
__rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
#endif
- // Set MSP
- __set_MSP((uint32_t)&__stackp - 0x100);
- // Overwrite vector table
- NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
-#if defined ( __ICCARM__ )
- NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
-#endif
-
extern HAL_TIMER_OP_EXT HalTimerOpExt;
__rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
__rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
@@ -270,7 +260,11 @@
#else
__asm ("ldr r0, =SystemInit \n"
"blx r0 \n"
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ "ldr r0, =__main \n"
+#else
"ldr r0, =_start \n"
+#endif
"bx r0 \n"
);
#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp Mon Oct 02 15:33:19 2017 +0100
@@ -217,11 +217,8 @@
{
if (_emac == NULL) {
- _emac = new emac_interface_t();
- if (_emac == NULL) {//new emac_interface_t fail
- printf("emac initialization failed\r\n");
- return NULL;
- }
+ _emac = (emac_interface_t*) malloc(sizeof(emac_interface_t));
+ MBED_ASSERT(_emac);
_emac->hw = NULL;
memcpy((void*)&_emac->ops, &wlan_emac_interface, sizeof(wlan_emac_interface));
}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c Mon Oct 02 15:33:19 2017 +0100
@@ -548,7 +548,7 @@
static u32 _rtx2_get_current_time(void)
{
- return osKernelGetTickCount();
+ return osKernelGetSysTimerCount();
}
static u32 _rtx2_systime_to_ms(u32 systime)
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h Mon Oct 02 15:33:19 2017 +0100 @@ -206,6 +206,23 @@ #define _LONG_CALL_ROM_ _LONG_CALL_ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define SECTION(_name) __attribute__ ((__section__(_name))) +#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound))) +#define _PACKED_ __attribute__ ((packed)) +#ifdef CONFIG_RELEASE_BUILD_LIBRARIES +#define _LONG_CALL_ +#define _LONG_CALL_ROM_ +#ifdef E_CUT_ROM_DOMAIN +#undef _LONG_CALL_ROM_ +#define _LONG_CALL_ROM_ +#endif +#else +#define _LONG_CALL_ +#define _LONG_CALL_ROM_ _LONG_CALL_ +#endif +#define _WEAK __attribute__ ((weak)) + #else #define SECTION(_name) __attribute__ ((__section__(_name))) #define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
--- a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -20,8 +20,22 @@
#include "PeripheralNames.h"
#define TICK_READ_FROM_CPU 0 // 1: read tick from CPU, 0: read tick from G-Timer
-#define SYS_TIM_ID 1 // the G-Timer ID for System
-#define APP_TIM_ID 6 // the G-Timer ID for Application
+#define SYS_TIM_ID 1 // the G-Timer ID for System
+#define APP_TIM_ID 6 // the G-Timer ID for Application
+
+/*
+ * For RTL8195AM, clock source is 32k
+ *
+ * us per tick: 30.5
+ * tick per ms: 32.7
+ * tick per us: 0.032
+ * tick per sec: 32768
+ *
+ * Define the following macros to convert between TICK and US.
+ */
+#define MS_TO_TICK(x) (uint64_t)(((x)*327) / 10)
+#define US_TO_TICK(x) (uint64_t)(((x)*32) / 1000)
+#define TICK_TO_US(x) (uint64_t)(((x)/2) * 61 + ((x)%2) * TIMER_TICK_US)
static int us_ticker_inited = 0;
static TIMER_ADAPTER TimerAdapter;
@@ -29,19 +43,25 @@
extern HAL_TIMER_OP HalTimerOp;
extern HAL_TIMER_OP_EXT HalTimerOpExt;
-VOID _us_ticker_irq_handler(IN VOID *Data)
+VOID _us_ticker_irq_handler(void *Data)
{
us_ticker_irq_handler();
}
-void us_ticker_init(void)
+void us_ticker_init(void)
{
-
- if (us_ticker_inited) return;
+ if (us_ticker_inited) {
+ return;
+ }
+
us_ticker_inited = 1;
-
- // Initial a G-Timer
+ // Reload and restart sys-timer
+ HalTimerOp.HalTimerDis(SYS_TIM_ID);
+ HalTimerOpExt.HalTimerReLoad(SYS_TIM_ID, 0xFFFFFFFFUL);
+ HalTimerOp.HalTimerEn(SYS_TIM_ID);
+
+ // Initial a app-timer
TimerAdapter.IrqDis = 0; // Enable Irq @ initial
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) _us_ticker_irq_handler;
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
@@ -52,58 +72,58 @@
TimerAdapter.TimerLoadValueUs = 0xFFFFFFFF;
TimerAdapter.TimerMode = USER_DEFINED;
- HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
+ HalTimerOp.HalTimerInit((void *) &TimerAdapter);
DBG_TIMER_INFO("%s: Timer_Id=%d\n", __FUNCTION__, APP_TIM_ID);
}
-uint32_t us_ticker_read()
+uint32_t us_ticker_read(void)
{
uint32_t tick_cnt;
- uint32_t ticks_125ms;
- uint32_t ticks_remain;
- uint64_t us_tick;
+ uint64_t tick_us;
+
+ if (!us_ticker_inited) {
+ us_ticker_init();
+ }
tick_cnt = HalTimerOp.HalTimerReadCount(SYS_TIM_ID);
- tick_cnt = 0xffffffff - tick_cnt; // it's a down counter
- ticks_125ms = tick_cnt/(GTIMER_CLK_HZ/8); //use 125ms as a intermediate unit;
- ticks_remain = tick_cnt - (ticks_125ms*(GTIMER_CLK_HZ/8)); //calculate the remainder
- us_tick = ticks_125ms * 125000; //change unit to us, 125ms is 125000 us
- us_tick += (ticks_remain * 1000000)/GTIMER_CLK_HZ; //also use us as unit
+ tick_us = TICK_TO_US(0xFFFFFFFFUL - tick_cnt);
- return ((uint32_t)us_tick); //return ticker value in micro-seconds (us)
+ return ((uint32_t)tick_us); //return ticker value in micro-seconds (us)
}
-void us_ticker_set_interrupt(timestamp_t timestamp)
+void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t cur_time_us;
- uint32_t time_dif;
+ uint32_t time_cur;
+ uint32_t time_cnt;
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
- cur_time_us = us_ticker_read();
- if ((uint32_t)timestamp > cur_time_us) {
- time_dif = (uint32_t)timestamp - cur_time_us;
+ time_cur = us_ticker_read();
+ if (timestamp > time_cur + TIMER_TICK_US) {
+ time_cnt = timestamp - time_cur;
} else {
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, 0xffffffff);
- HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
- NVIC_SetPendingIRQ(TIMER2_7_IRQ);
+ us_ticker_fire_interrupt();
return;
- }
+ }
- TimerAdapter.TimerLoadValueUs = time_dif;
- HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, time_dif / TIMER_TICK_US);
- HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
+ TimerAdapter.TimerLoadValueUs = MAX(MS_TO_TICK(time_cnt/1000) + US_TO_TICK(time_cnt%1000), 1);
+ HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs);
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
-
}
-void us_ticker_disable_interrupt(void)
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(TIMER2_7_IRQ);
+}
+
+void us_ticker_disable_interrupt(void)
{
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
}
-void us_ticker_clear_interrupt(void)
+void us_ticker_clear_interrupt(void)
{
HalTimerOp.HalTimerIrqClear((u32)TimerAdapter.TimerId);
}
--- a/targets/TARGET_Realtek/mbed_rtx.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Realtek/mbed_rtx.h Mon Oct 02 15:33:19 2017 +0100
@@ -20,7 +20,7 @@
#include "rtl8195a.h"
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) || (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[];
#define ISR_STACK_START (unsigned char *)(Image$$ARM_LIB_STACK$$ZI$$Base)
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/stm32f070xb.icf Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/stm32f070xb.icf Mon Oct 02 15:33:19 2017 +0100 @@ -9,7 +9,7 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0; define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_cstack__ = 0x400; define symbol __ICFEDIT_size_heap__ = 0x1000; /**** End of ICF editor section. ###ICF###*/
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/stm32f072xb.icf Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/stm32f072xb.icf Mon Oct 02 15:33:19 2017 +0100 @@ -9,7 +9,7 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0; define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_cstack__ = 0x400; define symbol __ICFEDIT_size_heap__ = 0x1000; /**** End of ICF editor section. ###ICF###*/
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -128,6 +128,14 @@
};
#endif
+#if DEVICE_CAN
+struct can_s {
+ CAN_HandleTypeDef CanHandle;
+ int index;
+ int hz;
+};
+#endif
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -116,6 +116,14 @@
uint8_t channel;
};
+#if DEVICE_CAN
+struct can_s {
+ CAN_HandleTypeDef CanHandle;
+ int index;
+ int hz;
+};
+#endif
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F2/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -136,10 +136,13 @@
uint8_t inverted;
};
+#ifdef DEVICE_CAN
struct can_s {
- CANName can;
+ CAN_HandleTypeDef CanHandle;
int index;
+ int hz;
};
+#endif
#define GPIO_IP_WITHOUT_BRR
#include "gpio_object.h"
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,13 +54,6 @@
__IO uint32_t *reg_out;
};
-#if defined (DEVICE_CAN)
-struct can_s {
- CANName can;
- int index;
-};
-#endif
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -124,6 +124,14 @@
uint8_t channel;
};
+#if DEVICE_CAN
+struct can_s {
+ CAN_HandleTypeDef CanHandle;
+ int index;
+ int hz;
+};
+#endif
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x80000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,52 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x20000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x80000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -40,11 +40,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2017, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x180000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 12, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08120000) /* Base @ of Sector 13, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08140000) /* Base @ of Sector 14, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x08160000) /* Base @ of Sector 15, 128 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -40,11 +40,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/nvic_addr.h Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef NVIC_ADDR_H
-#define NVIC_ADDR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__ICCARM__)
- #pragma section=".intvec"
- #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
-#elif defined(__CC_ARM)
- extern uint32_t Load$$LR$$LR_IROM1$$Base[];
- #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
-#elif defined(__GNUC__)
- extern uint32_t g_pfnVectors[];
- #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors)
-#else
- #error "Flash vector address not set for this toolchain"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -59,11 +59,6 @@
};
#include "common_objects.h"
-struct can_s {
- CANName can;
- int index;
-};
-
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x80000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x200000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +/* Base address of the Flash sectors Bank 2 */ +#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_16 ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_17 ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_18 ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_19 ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_20 ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_21 ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_22 ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_23 ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */ + + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -133,6 +133,14 @@
};
#endif
+#if DEVICE_CAN
+struct can_s {
+ CAN_HandleTypeDef CanHandle;
+ int index;
+ int hz;
+};
+#endif
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -129,9 +129,10 @@
uint32_t flash_get_page_size(const flash_t *obj)
{
- // not applicable for STM32F4
- return (0x4000); // minimum sector size
+ // Flash of STM32F4 devices can be programed 1 byte at a time
+ return (1);
}
+
uint32_t flash_get_start_address(const flash_t *obj)
{
return FLASH_BASE;
@@ -151,7 +152,7 @@
uint32_t sector = 0;
uint32_t tmp = address - ADDR_FLASH_SECTOR_0;
/* This function supports 1Mb and 2Mb flash sizes */
-#if defined(ADDR_FLASH_SECTOR_12)
+#if defined(ADDR_FLASH_SECTOR_16)
if (address & 0x100000) { // handle 2nd bank
sector = FLASH_SECTOR_12;
tmp = address - ADDR_FLASH_SECTOR_12;
@@ -159,11 +160,19 @@
#endif
if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
sector += tmp >>14;
- } else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
+ }
+#if defined(ADDR_FLASH_SECTOR_5)
+ else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
sector += FLASH_SECTOR_4;
} else {
sector += 4 + (tmp >>17);
}
+#else
+ // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one.
+ else { //64k sector size
+ sector += FLASH_SECTOR_4;
+ }
+#endif
return sector;
}
@@ -175,7 +184,7 @@
static uint32_t GetSectorSize(uint32_t Sector)
{
uint32_t sectorsize = 0x00;
-#if defined(FLASH_SECTOR_12)
+#if defined(FLASH_SECTOR_16)
if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
(Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\
(Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Flash size */ +#define FLASH_SIZE (uint32_t) 0x100000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base @ of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base @ of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base @ of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base @ of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base @ of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base @ of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base @ of Sector 7, 256 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Flash size */ +#define FLASH_SIZE (uint32_t) 0x100000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base @ of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base @ of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base @ of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base @ of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base @ of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base @ of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base @ of Sector 7, 256 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x200000 + +/* We're considering the default reset SINGLE BANK CONFIGURATION ONLY */ +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base @ of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base @ of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base @ of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base @ of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base @ of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base @ of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base @ of Sector 7, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08100000) /* Base @ of Sector 8, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x08140000) /* Base @ of Sector 9, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x08180000) /* Base @ of Sector 10, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x081C0000) /* Base @ of Sector 11, 256 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/flash_data.h Mon Oct 02 15:33:19 2017 +0100 @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x200000 + +/* We're considering the default reset SINGLE BANK CONFIGURATION ONLY */ +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base @ of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base @ of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base @ of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base @ of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base @ of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base @ of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base @ of Sector 7, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08100000) /* Base @ of Sector 8, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x08140000) /* Base @ of Sector 9, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x08180000) /* Base @ of Sector 10, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x081C0000) /* Base @ of Sector 11, 256 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -127,6 +127,19 @@
DAC_HandleTypeDef handle;
};
+struct flash_s {
+ /* nothing to be stored for now */
+ uint32_t dummy;
+};
+
+#if DEVICE_CAN
+struct can_s {
+ CAN_HandleTypeDef CanHandle;
+ int index;
+ int hz;
+};
+#endif
+
#ifdef __cplusplus
}
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -0,0 +1,206 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#if DEVICE_FLASH
+#include "flash_api.h"
+#include "flash_data.h"
+#include "platform/mbed_critical.h"
+
+static uint32_t GetSector(uint32_t Address);
+static uint32_t GetSectorSize(uint32_t Sector);
+
+int32_t flash_init(flash_t *obj)
+{
+ /* Allow Access to Flash control registers and user Flash */
+ if (HAL_FLASH_Unlock()) {
+ return -1;
+ } else {
+ return 0;
+ }
+}
+int32_t flash_free(flash_t *obj)
+{
+ /* Disable the Flash option control register access (recommended to protect
+ the option Bytes against possible unwanted operations) */
+ if (HAL_FLASH_Lock()) {
+ return -1;
+ } else {
+ return 0;
+ }
+}
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+ /* Variable used for Erase procedure */
+ FLASH_EraseInitTypeDef EraseInitStruct;
+ FLASH_OBProgramInitTypeDef OBInit;
+ uint32_t SectorId;
+ uint32_t SectorError = 0;
+
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return -1;
+ }
+
+ /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+ you have to make sure that these data are rewritten before they are accessed during code
+ execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+ DCRST and ICRST bits in the FLASH_CR register. */
+ __HAL_FLASH_ART_DISABLE();
+ __HAL_FLASH_ART_RESET();
+ __HAL_FLASH_ART_ENABLE();
+
+ /* Get the 1st sector to erase */
+ SectorId = GetSector(address);
+
+ /* Allow Access to option bytes sector */
+ HAL_FLASH_OB_Unlock();
+ /* Get the Dual bank configuration status */
+ HAL_FLASHEx_OBGetConfig(&OBInit);
+ /* Allow Access to option bytes sector */
+ HAL_FLASH_OB_Lock();
+
+#if defined (FLASH_OPTCR_nDBANK)
+ /* On targets that support dynamic single or dual bank configuration
+ * Check that we're in SINGLE Bank mode, only supported mode now.
+ */
+ if((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) != OB_NDBANK_SINGLE_BANK) {
+ /* We don't support the DUAL BANK MODE for now, so return error */
+ return -1;
+ }
+#endif
+
+ /* Fill EraseInit structure*/
+ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
+ EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
+ EraseInitStruct.Sector = SectorId;
+ EraseInitStruct.NbSectors = 1;
+
+ if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
+ uint32_t size)
+{
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return -1;
+ }
+
+ /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+ you have to make sure that these data are rewritten before they are accessed during code
+ execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+ DCRST and ICRST bits in the FLASH_CR register. */
+ __HAL_FLASH_ART_DISABLE();
+ __HAL_FLASH_ART_RESET();
+ __HAL_FLASH_ART_ENABLE();
+
+ while (size > 0) {
+ if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE,
+ address, (uint64_t)*data) != HAL_OK) {
+ return -1;
+ } else {
+ size--;
+ address++;
+ data++;
+ }
+ }
+ return 0;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return MBED_FLASH_INVALID_SIZE;
+ }
+
+ return (GetSectorSize(GetSector(address)));
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+ // Flash of STM32F7 devices can be programed 1 byte at a time
+ return (1);
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+ return FLASH_BASE;
+}
+uint32_t flash_get_size(const flash_t *obj)
+{
+ return FLASH_SIZE;
+}
+
+/**
+ * @brief Gets the sector of a given address
+ * @param None
+ * @retval The sector of a given address
+ */
+static uint32_t GetSector(uint32_t address)
+{
+ uint32_t sector = 0;
+ uint32_t tmp = address - ADDR_FLASH_SECTOR_0;
+
+ if (address < ADDR_FLASH_SECTOR_4) {
+ // 32k sectorsize
+ sector += tmp >>15;
+ } else if (address < ADDR_FLASH_SECTOR_5) {
+ //64k sector size
+ sector += FLASH_SECTOR_4;
+ } else {
+ sector += 4 + (tmp >>18);
+ }
+
+ return sector;
+}
+
+/**
+ * @brief Gets sector Size
+ * @param None
+ * @retval The size of a given sector
+ */
+static uint32_t GetSectorSize(uint32_t Sector)
+{
+ uint32_t sectorsize = 0x00;
+ if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) ||\
+ (Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3)) {
+ sectorsize = 32 * 1024;
+ } else if (Sector == FLASH_SECTOR_4) {
+ sectorsize = 128 * 1024;
+ } else {
+ sectorsize = 256 * 1024;
+ }
+
+ return sectorsize;
+}
+
+#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -128,7 +128,8 @@
}
uint32_t flash_get_page_size(const flash_t *obj) {
- return FLASH_PAGE_SIZE;
+ /* Page size is the minimum programable size, which 4 bytes */
+ return 4;
}
uint32_t flash_get_start_address(const flash_t *obj) {
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h Mon Oct 02 15:33:19 2017 +0100
@@ -170,6 +170,22 @@
SE_IO = PB_10,
SE_CLK = PB_11,
+#ifdef TARGET_FF1705_L151CC
+ // Arduino Headers
+ A0 = PA_0,
+ A1 = PB_0,
+ D0 = PA_10,
+ D1 = PA_9,
+ D2 = PA_11,
+ D3 = PA_12,
+ D10 = PB_12,
+ D11 = PB_15,
+ D12 = PB_14,
+ D13 = PB_13,
+ D14 = I2C_SDA,
+ D15 = I2C_SCL,
+#endif
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c Mon Oct 02 15:33:19 2017 +0100
@@ -91,7 +91,7 @@
#if defined(__ICCARM__)
#pragma section=".intvec"
#define FLASH_VTOR_BASE ((uint32_t)__section_begin(".intvec"))
-#elif defined(__CC_ARM)
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define FLASH_VTOR_BASE ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__GNUC__)
--- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -127,7 +127,8 @@
uint32_t flash_get_page_size(const flash_t *obj)
{
- return FLASH_PAGE_SIZE;
+ /* Page size is the minimum programable size, which 4 bytes */
+ return 4;
}
uint32_t flash_get_start_address(const flash_t *obj)
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -54,11 +54,6 @@
__IO uint32_t *reg_out;
};
-struct can_s {
- CANName can;
- int index;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h Mon Oct 02 15:33:19 2017 +0100
@@ -135,6 +135,14 @@
}
#endif
+#if DEVICE_CAN
+struct can_s {
+ CAN_HandleTypeDef CanHandle;
+ int index;
+ int hz;
+};
+#endif
+
/* STM32L4 HAL doesn't provide this API called in rtc_api.c */
#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
--- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -221,8 +221,8 @@
* @return The size of a page
*/
uint32_t flash_get_page_size(const flash_t *obj) {
- /* considering 1 sector = 1 page */
- return FLASH_PAGE_SIZE;
+ /* Page size is the minimum programable size, which 8 bytes */
+ return 8;
}
/** Get start address for the flash region
--- a/targets/TARGET_STM/can_api.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/can_api.c Mon Oct 02 15:33:19 2017 +0100
@@ -25,10 +25,21 @@
#include <math.h>
#include <string.h>
-static CAN_HandleTypeDef CanHandle;
static uint32_t can_irq_ids[CAN_NUM] = {0};
static can_irq_handler irq_handler;
+static void can_registers_init(can_t *obj)
+{
+ if (HAL_CAN_Init(&obj->CanHandle) != HAL_OK) {
+ error("Cannot initialize CAN");
+ }
+
+ // Set initial CAN frequency to specified frequency
+ if (can_frequency(obj, obj->hz) != 1) {
+ error("Can frequency could not be set\n");
+ }
+}
+
void can_init(can_t *obj, PinName rd, PinName td)
{
can_init_freq(obj, rd, td, 100000);
@@ -38,16 +49,16 @@
{
CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+ CANName can = (CANName)pinmap_merge(can_rd, can_td);
- obj->can = (CANName)pinmap_merge(can_rd, can_td);
- MBED_ASSERT((int)obj->can != NC);
+ MBED_ASSERT((int)can != NC);
- if (obj->can == CAN_1) {
+ if (can == CAN_1) {
__HAL_RCC_CAN1_CLK_ENABLE();
obj->index = 0;
}
#if defined(CAN2_BASE) && (CAN_NUM == 2)
- else if (obj->can == CAN_2) {
+ else if (can == CAN_2) {
__HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters
__HAL_RCC_CAN2_CLK_ENABLE();
obj->index = 1;
@@ -67,33 +78,30 @@
pin_mode(td, PullUp);
}
- CanHandle.Instance = (CAN_TypeDef *)(obj->can);
+ /* Use default values for rist init */
+ obj->CanHandle.Instance = (CAN_TypeDef *)can;
+ obj->CanHandle.Init.TTCM = DISABLE;
+ obj->CanHandle.Init.ABOM = DISABLE;
+ obj->CanHandle.Init.AWUM = DISABLE;
+ obj->CanHandle.Init.NART = DISABLE;
+ obj->CanHandle.Init.RFLM = DISABLE;
+ obj->CanHandle.Init.TXFP = DISABLE;
+ obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
+ obj->CanHandle.Init.SJW = CAN_SJW_1TQ;
+ obj->CanHandle.Init.BS1 = CAN_BS1_6TQ;
+ obj->CanHandle.Init.BS2 = CAN_BS2_8TQ;
+ obj->CanHandle.Init.Prescaler = 2;
- CanHandle.Init.TTCM = DISABLE;
- CanHandle.Init.ABOM = DISABLE;
- CanHandle.Init.AWUM = DISABLE;
- CanHandle.Init.NART = DISABLE;
- CanHandle.Init.RFLM = DISABLE;
- CanHandle.Init.TXFP = DISABLE;
- CanHandle.Init.Mode = CAN_MODE_NORMAL;
- CanHandle.Init.SJW = CAN_SJW_1TQ;
- CanHandle.Init.BS1 = CAN_BS1_6TQ;
- CanHandle.Init.BS2 = CAN_BS2_8TQ;
- CanHandle.Init.Prescaler = 2;
+ /* Store frequency to be restored in case of reset */
+ obj->hz = hz;
- if (HAL_CAN_Init(&CanHandle) != HAL_OK) {
- error("Cannot initialize CAN");
- }
+ can_registers_init(obj);
- // Set initial CAN frequency to specified frequency
- if (can_frequency(obj, hz) != 1) {
- error("Can frequency could not be set\n");
- }
-
- uint32_t filter_number = (obj->can == CAN_1) ? 0 : 14;
+ uint32_t filter_number = (can == CAN_1) ? 0 : 14;
can_filter(obj, 0, 0, CANStandard, filter_number);
}
+
void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
{
irq_handler = handler;
@@ -102,7 +110,7 @@
void can_irq_free(can_t *obj)
{
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
@@ -111,14 +119,15 @@
void can_free(can_t *obj)
{
+ CANName can = (CANName) obj->CanHandle.Instance;
// Reset CAN and disable clock
- if (obj->can == CAN_1) {
+ if (can == CAN_1) {
__HAL_RCC_CAN1_FORCE_RESET();
__HAL_RCC_CAN1_RELEASE_RESET();
__HAL_RCC_CAN1_CLK_DISABLE();
}
#if defined(CAN2_BASE) && (CAN_NUM == 2)
- if (obj->can == CAN_2) {
+ if (can == CAN_2) {
__HAL_RCC_CAN2_FORCE_RESET();
__HAL_RCC_CAN2_RELEASE_RESET();
__HAL_RCC_CAN2_CLK_DISABLE();
@@ -196,7 +205,7 @@
{
int pclk = HAL_RCC_GetPCLK1Freq();
int btr = can_speed(pclk, (unsigned int)f, 1);
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
uint32_t tickstart = 0;
int status = 1;
@@ -211,7 +220,11 @@
}
}
if (status != 0) {
- can->BTR = btr;
+ /* Do not erase all BTR registers (e.g. silent mode), only the
+ * ones calculated in can_speed */
+ can->BTR &= ~(CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_SJW | CAN_BTR_BRP);
+ can->BTR |= btr;
+
can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
/* Get tick */
tickstart = HAL_GetTick();
@@ -236,7 +249,7 @@
int can_write(can_t *obj, CAN_Message msg, int cc)
{
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
/* Select one empty transmit mailbox */
if ((can->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
@@ -279,7 +292,7 @@
{
//handle is the FIFO number
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
// check FPM0 which holds the pending message count in FIFO 0
// if no message is pending, return 0
@@ -324,46 +337,61 @@
void can_reset(can_t *obj)
{
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
+
+ /* Reset IP and delete errors */
can->MCR |= CAN_MCR_RESET;
can->ESR = 0x0;
+
+ /* restore registers state as saved in obj context */
+ can_registers_init(obj);
}
unsigned char can_rderror(can_t *obj)
{
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
return (can->ESR >> 24) & 0xFF;
}
unsigned char can_tderror(can_t *obj)
{
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
return (can->ESR >> 16) & 0xFF;
}
void can_monitor(can_t *obj, int silent)
{
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
-
- can->MCR |= CAN_MCR_INRQ ;
- while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
+ CanMode mode = MODE_NORMAL;
+ /* Update current state w/ or w/o silent */
+ if(silent) {
+ switch (obj->CanHandle.Init.Mode) {
+ case CAN_MODE_LOOPBACK:
+ case CAN_MODE_SILENT_LOOPBACK:
+ mode = MODE_TEST_SILENT;
+ break;
+ default:
+ mode = MODE_SILENT;
+ break;
+ }
+ } else {
+ switch (obj->CanHandle.Init.Mode) {
+ case CAN_MODE_LOOPBACK:
+ case CAN_MODE_SILENT_LOOPBACK:
+ mode = MODE_TEST_LOCAL;
+ break;
+ default:
+ mode = MODE_NORMAL;
+ break;
+ }
}
- if (silent) {
- can->BTR |= ((uint32_t)1 << 31);
- } else {
- can->BTR &= ~((uint32_t)1 << 31);
- }
-
- can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
- while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
- }
+ can_mode(obj, mode);
}
int can_mode(can_t *obj, CanMode mode)
{
int success = 0;
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
can->MCR |= CAN_MCR_INRQ ;
while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
@@ -371,21 +399,25 @@
switch (mode) {
case MODE_NORMAL:
+ obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
can->BTR &= ~(CAN_BTR_SILM | CAN_BTR_LBKM);
success = 1;
break;
case MODE_SILENT:
+ obj->CanHandle.Init.Mode = CAN_MODE_SILENT;
can->BTR |= CAN_BTR_SILM;
can->BTR &= ~CAN_BTR_LBKM;
success = 1;
break;
case MODE_TEST_GLOBAL:
case MODE_TEST_LOCAL:
+ obj->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
can->BTR |= CAN_BTR_LBKM;
can->BTR &= ~CAN_BTR_SILM;
success = 1;
break;
case MODE_TEST_SILENT:
+ obj->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
can->BTR |= (CAN_BTR_SILM | CAN_BTR_LBKM);
success = 1;
break;
@@ -407,7 +439,6 @@
// filter for CANAny format cannot be configured for STM32
if ((format == CANStandard) || (format == CANExtended)) {
- CanHandle.Instance = (CAN_TypeDef *)(obj->can);
CAN_FilterConfTypeDef sFilterConfig;
sFilterConfig.FilterNumber = handle;
sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
@@ -429,7 +460,7 @@
sFilterConfig.FilterActivation = ENABLE;
sFilterConfig.BankNumber = 14 + handle;
- HAL_CAN_ConfigFilter(&CanHandle, &sFilterConfig);
+ HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig);
retval = handle;
}
return retval;
@@ -438,6 +469,7 @@
static void can_irq(CANName name, int id)
{
uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+ CAN_HandleTypeDef CanHandle;
CanHandle.Instance = (CAN_TypeDef *)name;
if (__HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_TME)) {
@@ -535,13 +567,12 @@
void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
{
-
- CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+ CAN_TypeDef *can = obj->CanHandle.Instance;
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
uint32_t ier;
- if (obj->can == CAN_1) {
+ if ((CANName) can == CAN_1) {
switch (type) {
case IRQ_RX:
ier = CAN_IT_FMP0;
@@ -573,7 +604,7 @@
}
}
#if defined(CAN2_BASE) && (CAN_NUM == 2)
- else if (obj->can == CAN_2) {
+ else if ((CANName) can == CAN_2) {
switch (type) {
case IRQ_RX:
ier = CAN_IT_FMP0;
--- a/targets/TARGET_STM/hal_tick_16b.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/hal_tick_16b.c Mon Oct 02 15:33:19 2017 +0100
@@ -168,15 +168,15 @@
return HAL_OK;
}
+/* NOTE: must be called with interrupts disabled! */
void HAL_SuspendTick(void)
{
- TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
}
+/* NOTE: must be called with interrupts disabled! */
void HAL_ResumeTick(void)
{
- TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
}
--- a/targets/TARGET_STM/hal_tick_32b.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/hal_tick_32b.c Mon Oct 02 15:33:19 2017 +0100
@@ -138,15 +138,15 @@
return HAL_OK;
}
+/* NOTE: must be called with interrupts disabled! */
void HAL_SuspendTick(void)
{
- TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
}
+/* NOTE: must be called with interrupts disabled! */
void HAL_ResumeTick(void)
{
- TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
}
--- a/targets/TARGET_STM/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -70,6 +70,11 @@
rtc_set_wake_up_timer(delta);
}
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(RTC_WKUP_IRQn);
+}
+
void lp_ticker_disable_interrupt(void)
{
rtc_deactivate_wake_up_timer();
--- a/targets/TARGET_STM/nvic_addr.h Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/nvic_addr.h Mon Oct 02 15:33:19 2017 +0100
@@ -23,7 +23,7 @@
#if defined(__ICCARM__)
#pragma section=".intvec"
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
-#elif defined(__CC_ARM)
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__GNUC__)
--- a/targets/TARGET_STM/us_ticker_16b.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/us_ticker_16b.c Mon Oct 02 15:33:19 2017 +0100
@@ -26,22 +26,13 @@
volatile uint32_t SlaveCounter = 0;
volatile uint32_t oc_int_part = 0;
-static int us_ticker_inited = 0;
-
void us_ticker_init(void)
{
- if (us_ticker_inited) return;
- us_ticker_inited = 1;
-
- TimMasterHandle.Instance = TIM_MST;
-
- HAL_InitTick(0); // The passed value is not used
+ /* NOTE: assuming that HAL tick has already been initialized! */
}
uint32_t us_ticker_read()
{
- if (!us_ticker_inited) us_ticker_init();
-
uint16_t cntH_old, cntH, cntL;
do {
cntH_old = SlaveCounter;
@@ -73,7 +64,7 @@
{
// NOTE: This function must be called with interrupts disabled to keep our
// timer interrupt setup atomic
- TimMasterHandle.Instance = TIM_MST;
+
// Set new output compare value
__HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, timestamp & 0xFFFF);
// Ensure the compare event starts clear
@@ -81,120 +72,119 @@
// Enable IT
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
- int current_time = us_ticker_read();
- int delta = (int)(timestamp - current_time);
-
- if (delta <= 0) { // This event was in the past
- /* Immediately set the compare event to cause the event to be handled in
- * the next interrupt context. This prevents calling interrupt handlers
- * recursively as us_ticker_set_interrupt might be called again from the
- * application handler
+ /* Set the number of timer wrap-around loops before the actual timestamp
+ * is reached. If the calculated delta time is more than halfway to the
+ * next compare event, check to see if a compare event has already been
+ * set, and if so, add one to the wrap-around count. This is done to
+ * ensure the correct wrap count is used in the corner cases where the
+ * 16 bit counter passes the compare value during the process of
+ * configuring this interrupt.
+ *
+ * Assumption: The time to execute this function is less than 32ms
+ * (otherwise incorrect behaviour could result)
+ *
+ * Consider the following corner cases:
+ * 1) timestamp is 1 us in the future:
+ * oc_int_part = 0 initially
+ * oc_int_part left at 0 because ((delta - 1) & 0xFFFF) < 0x8000
+ * Compare event should happen in 1 us and us_ticker_irq_handler()
+ * called
+ * 2) timestamp is 0x8000 us in the future:
+ * oc_int_part = 0 initially
+ * oc_int_part left at 0 because ((delta - 1) & 0xFFFF) < 0x8000
+ * There should be no possibility of the CC1 flag being set yet
+ * (see assumption above). When the compare event does occur in
+ * 32768 us, us_ticker_irq_handler() will be called
+ * 3) timestamp is 0x8001 us in the future:
+ * oc_int_part = 0 initially
+ * ((delta - 1) & 0xFFFF) >= 0x8000 but there should be no
+ * possibility of the CC1 flag being set yet (see assumption above),
+ * so oc_int_part will be left at 0, and when the compare event
+ * does occur in 32769 us, us_ticker_irq_handler() will be called
+ * 4) timestamp is 0x10000 us in the future:
+ * oc_int_part = 0 initially
+ * ((delta - 1) & 0xFFFF) >= 0x8000
+ * There are two subcases:
+ * a) The timer counter has not incremented past the compare
+ * value while setting up the interrupt. In this case, the
+ * CC1 flag will not be set, so oc_int_part will be
+ * left at 0, and when the compare event occurs in 65536 us,
+ * us_ticker_irq_handler() will be called
+ * b) The timer counter has JUST incremented past the compare
+ * value. In this case, the CC1 flag will be set, so
+ * oc_int_part will be incremented to 1, and the interrupt will
+ * occur immediately after this function returns, where
+ * oc_int_part will decrement to 0 without calling
+ * us_ticker_irq_handler(). Then about 65536 us later, the
+ * compare event will occur again, and us_ticker_irq_handler()
+ * will be called
+ * 5) timestamp is 0x10001 us in the future:
+ * oc_int_part = 1 initially
+ * oc_int_part left at 1 because ((delta - 1) & 0xFFFF) < 0x8000
+ * CC1 flag will not be set (see assumption above). In 1 us the
+ * compare event will cause an interrupt, where oc_int_part will be
+ * decremented to 0 without calling us_ticker_irq_handler(). Then
+ * about 65536 us later, the compare event will occur again, and
+ * us_ticker_irq_handler() will be called
+ * 6) timestamp is 0x18000 us in the future:
+ * oc_int_part = 1 initially
+ * oc_int_part left at 1 because ((delta - 1) & 0xFFFF) < 0x8000
+ * There should be no possibility of the CC1 flag being set yet
+ * (see assumption above). When the compare event does occur in
+ * 32768 us, oc_int_part will be decremented to 0 without calling
+ * us_ticker_irq_handler(). Then about 65536 us later, the
+ * compare event will occur again, and us_ticker_irq_handler() will
+ * be called
+ * 7) timestamp is 0x18001 us in the future:
+ * oc_int_part = 1 initially
+ * ((delta - 1) & 0xFFFF) >= 0x8000 but there should be no
+ * possibility of the CC1 flag being set yet (see assumption above),
+ * so oc_int_part will be left at 1, and when the compare event
+ * does occur in 32769 us, oc_int_part will be decremented to 0
+ * without calling us_ticker_irq_handler(). Then about 65536 us
+ * later, the compare event will occur again, and
+ * us_ticker_irq_handler() will be called
+ *
+ * delta - 1 is used because the timer compare event happens on the
+ * counter incrementing to match the compare value, and it won't occur
+ * immediately when the compare value is set to the current counter
+ * value.
+ */
+ uint32_t current_time = us_ticker_read();
+ uint32_t delta = timestamp - current_time;
+ /* Note: The case of delta <= 0 is handled in MBED upper layer */
+ oc_int_part = (delta - 1) >> 16;
+ if ( ((delta - 1) & 0xFFFF) >= 0x8000 &&
+ __HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET ) {
+ ++oc_int_part;
+ /* NOTE: Instead of incrementing oc_int_part here, we could clear
+ * the CC1 flag, but then you'd have to wait to ensure the
+ * interrupt is knocked down before returning and reenabling
+ * interrupts. Since this is a rare case, it's not worth it
+ * to try and optimize it, and it keeps the code simpler and
+ * safer to just do this increment instead.
*/
- oc_int_part = 0;
- HAL_TIM_GenerateEvent(&TimMasterHandle, TIM_EVENTSOURCE_CC1);
- } else {
- /* Set the number of timer wrap-around loops before the actual timestamp
- * is reached. If the calculated delta time is more than halfway to the
- * next compare event, check to see if a compare event has already been
- * set, and if so, add one to the wrap-around count. This is done to
- * ensure the correct wrap count is used in the corner cases where the
- * 16 bit counter passes the compare value during the process of
- * configuring this interrupt.
- *
- * Assumption: The time to execute this function is less than 32ms
- * (otherwise incorrect behaviour could result)
- *
- * Consider the following corner cases:
- * 1) timestamp is 1 us in the future:
- * oc_int_part = 0 initially
- * oc_int_part left at 0 because ((delta - 1) & 0xFFFF) < 0x8000
- * Compare event should happen in 1 us and us_ticker_irq_handler()
- * called
- * 2) timestamp is 0x8000 us in the future:
- * oc_int_part = 0 initially
- * oc_int_part left at 0 because ((delta - 1) & 0xFFFF) < 0x8000
- * There should be no possibility of the CC1 flag being set yet
- * (see assumption above). When the compare event does occur in
- * 32768 us, us_ticker_irq_handler() will be called
- * 3) timestamp is 0x8001 us in the future:
- * oc_int_part = 0 initially
- * ((delta - 1) & 0xFFFF) >= 0x8000 but there should be no
- * possibility of the CC1 flag being set yet (see assumption above),
- * so oc_int_part will be left at 0, and when the compare event
- * does occur in 32769 us, us_ticker_irq_handler() will be called
- * 4) timestamp is 0x10000 us in the future:
- * oc_int_part = 0 initially
- * ((delta - 1) & 0xFFFF) >= 0x8000
- * There are two subcases:
- * a) The timer counter has not incremented past the compare
- * value while setting up the interrupt. In this case, the
- * CC1 flag will not be set, so oc_int_part will be
- * left at 0, and when the compare event occurs in 65536 us,
- * us_ticker_irq_handler() will be called
- * b) The timer counter has JUST incremented past the compare
- * value. In this case, the CC1 flag will be set, so
- * oc_int_part will be incremented to 1, and the interrupt will
- * occur immediately after this function returns, where
- * oc_int_part will decrement to 0 without calling
- * us_ticker_irq_handler(). Then about 65536 us later, the
- * compare event will occur again, and us_ticker_irq_handler()
- * will be called
- * 5) timestamp is 0x10001 us in the future:
- * oc_int_part = 1 initially
- * oc_int_part left at 1 because ((delta - 1) & 0xFFFF) < 0x8000
- * CC1 flag will not be set (see assumption above). In 1 us the
- * compare event will cause an interrupt, where oc_int_part will be
- * decremented to 0 without calling us_ticker_irq_handler(). Then
- * about 65536 us later, the compare event will occur again, and
- * us_ticker_irq_handler() will be called
- * 6) timestamp is 0x18000 us in the future:
- * oc_int_part = 1 initially
- * oc_int_part left at 1 because ((delta - 1) & 0xFFFF) < 0x8000
- * There should be no possibility of the CC1 flag being set yet
- * (see assumption above). When the compare event does occur in
- * 32768 us, oc_int_part will be decremented to 0 without calling
- * us_ticker_irq_handler(). Then about 65536 us later, the
- * compare event will occur again, and us_ticker_irq_handler() will
- * be called
- * 7) timestamp is 0x18001 us in the future:
- * oc_int_part = 1 initially
- * ((delta - 1) & 0xFFFF) >= 0x8000 but there should be no
- * possibility of the CC1 flag being set yet (see assumption above),
- * so oc_int_part will be left at 1, and when the compare event
- * does occur in 32769 us, oc_int_part will be decremented to 0
- * without calling us_ticker_irq_handler(). Then about 65536 us
- * later, the compare event will occur again, and
- * us_ticker_irq_handler() will be called
- *
- * delta - 1 is used because the timer compare event happens on the
- * counter incrementing to match the compare value, and it won't occur
- * immediately when the compare value is set to the current counter
- * value.
- */
- oc_int_part = ((uint32_t)delta - 1) >> 16;
- if ( ((delta - 1) & 0xFFFF) >= 0x8000 &&
- __HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET ) {
- ++oc_int_part;
- /* NOTE: Instead of incrementing oc_int_part here, we could clear
- * the CC1 flag, but then you'd have to wait to ensure the
- * interrupt is knocked down before returning and reenabling
- * interrupts. Since this is a rare case, it's not worth it
- * to try and optimize it, and it keeps the code simpler and
- * safer to just do this increment instead.
- */
- }
}
+
}
+void us_ticker_fire_interrupt(void)
+{
+ /* When firing the event, the number of 16 bits counter wrap-ups (oc_int)
+ * must be re-initialized */
+ oc_int_part = 0;
+ HAL_TIM_GenerateEvent(&TimMasterHandle, TIM_EVENTSOURCE_CC1);
+}
+
+/* NOTE: must be called with interrupts disabled! */
void us_ticker_disable_interrupt(void)
{
- TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
+/* NOTE: must be called with interrupts disabled! */
void us_ticker_clear_interrupt(void)
{
- TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
}
--- a/targets/TARGET_STM/us_ticker_32b.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_STM/us_ticker_32b.c Mon Oct 02 15:33:19 2017 +0100
@@ -23,49 +23,44 @@
TIM_HandleTypeDef TimMasterHandle;
-static int us_ticker_inited = 0;
-
void us_ticker_init(void)
{
- if (us_ticker_inited) return;
- us_ticker_inited = 1;
-
- TimMasterHandle.Instance = TIM_MST;
-
- HAL_InitTick(0); // The passed value is not used
+ /* NOTE: assuming that HAL tick has already been initialized! */
}
uint32_t us_ticker_read()
{
- if (!us_ticker_inited) us_ticker_init();
return TIM_MST->CNT;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- TimMasterHandle.Instance = TIM_MST;
+ // NOTE: This function must be called with interrupts disabled to keep our
+ // timer interrupt setup atomic
+
// disable IT while we are handling the correct timestamp
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
// Set new output compare value
__HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp);
- // Check if timestamp has already passed, and if so, set the event immediately
- if ((int32_t)(timestamp - TIM_MST->CNT) <= 0) {
- LL_TIM_GenerateEvent_CC1(TimMasterHandle.Instance);
- }
// Enable IT
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
+void us_ticker_fire_interrupt(void)
+{
+ LL_TIM_GenerateEvent_CC1(TimMasterHandle.Instance);
+}
+
+/* NOTE: must be called with interrupts disabled! */
void us_ticker_disable_interrupt(void)
{
- TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
+/* NOTE: must be called with interrupts disabled! */
void us_ticker_clear_interrupt(void)
{
- TimMasterHandle.Instance = TIM_MST;
- __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
}
#endif // !TIM_MST_16BIT
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/cmsis_nvic.h Mon Oct 02 15:33:19 2017 +0100 @@ -8,7 +8,7 @@ #define NVIC_NUM_VECTORS (16 + EXT_IRQ_COUNT) // CORE + MCU Peripherals /* For GCC, use dynamic vector table placement since otherwise we run into an alignment conflict */ -#if (defined (__GNUC__) && (!defined(__CC_ARM))) +#if (defined (__GNUC__) && (!defined(__CC_ARM) && (!defined(__ARMCC_VERSION)))) extern uint32_t __start_vector_table__; // Dynamic vector positioning in GCC #define NVIC_RAM_VECTOR_ADDRESS (&__start_vector_table__) #else
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -92,6 +92,11 @@
RTC_FreezeEnable(false);
}
+void lp_ticker_fire_interrupt(void)
+{
+ RTC_IntSet(RTC_IFS_COMP0);
+}
+
inline void lp_ticker_disable_interrupt()
{
RTC_IntDisable(RTC_IF_COMP0);
@@ -160,6 +165,11 @@
RTCC_IntEnable(RTCC_IF_CC0);
}
+void lp_ticker_fire_interrupt(void)
+{
+ RTCC_IntSet(RTCC_IFS_CC0);
+}
+
inline void lp_ticker_disable_interrupt()
{
RTCC_IntDisable(RTCC_IF_CC0);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -211,6 +211,11 @@
TIMER_IntEnable(US_TICKER_TIMER, TIMER_IEN_CC0);
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQ);
+}
+
void us_ticker_disable_interrupt(void)
{
if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) != 0) {
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf Fri Sep 15 14:59:18 2017 +0100 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf Mon Oct 02 15:33:19 2017 +0100 @@ -6,7 +6,7 @@ /*-Memory Regions-*/ define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x200;
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_WIZNET/TARGET_W7500x/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -96,12 +96,6 @@
dev = (int32_t)(timestamp - us_ticker_read());
dev = dev * ((GetSystemClock() / 1000000) / 16);
- if(dev <= 0)
- {
- us_ticker_irq_handler();
- return;
- }
-
DUALTIMER_ClockEnable(TIMER_0);
DUALTIMER_Stop(TIMER_0);
@@ -123,6 +117,11 @@
}
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(TIMER_IRQn);
+}
+
void us_ticker_disable_interrupt(void)
{
NVIC_DisableIRQ(TIMER_IRQn);
--- a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2016 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_ublox/TARGET_HI2110/lp_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ublox/TARGET_HI2110/lp_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -323,6 +323,14 @@
core_util_critical_section_exit();
}
+void lp_ticker_fire_interrupt(void)
+{
+ // user interrupt only set, this will invoke from ISR routine directly lp handler
+ g_user_interrupt_pending = false;
+ g_user_interrupt_set = true;
+ NVIC_SetPendingIRQ(RTC_IRQn);
+}
+
void lp_ticker_disable_interrupt(void)
{
/* Can't disable interrupts as we need them to manage
--- a/targets/TARGET_ublox/TARGET_HI2110/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/TARGET_ublox/TARGET_HI2110/us_ticker.c Mon Oct 02 15:33:19 2017 +0100
@@ -226,6 +226,12 @@
core_util_critical_section_exit();
}
+void us_ticker_fire_interrupt(void)
+{
+ g_user_interrupt = true;
+ NVIC_SetPendingIRQ(Timer_IRQn);
+}
+
void us_ticker_disable_interrupt(void)
{
/* Can't actually disable the interrupt here
--- a/targets/targets.json Fri Sep 15 14:59:18 2017 +0100
+++ b/targets/targets.json Mon Oct 02 15:33:19 2017 +0100
@@ -58,7 +58,7 @@
"extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_name": "LPC11C24FBD48/301"
},
"LPC1114": {
@@ -68,7 +68,7 @@
"extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC1114FN28/102"
@@ -81,7 +81,7 @@
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"detect_code": ["1040"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC11U24FBD48/401"
@@ -90,7 +90,7 @@
"inherits": ["LPC11U24"],
"macros": ["TARGET_LPC11U24", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"extra_labels": ["NXP", "LPC11UXX"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2"]
},
"LPC11U24_301": {
@@ -99,7 +99,7 @@
"extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_name": "LPC11U24FHI33/301"
},
"LPC11U34_421": {
@@ -109,7 +109,7 @@
"extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"device_name": "LPC11U34FBD48/311"
},
@@ -127,7 +127,7 @@
"extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC11U35FBD48/401"
@@ -139,7 +139,7 @@
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC11U35FHI33/501"
@@ -151,7 +151,7 @@
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"device_name": "LPC11U35FHI33/501"
},
@@ -165,7 +165,7 @@
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"device_name": "LPC11U35FHI33/501"
},
@@ -181,7 +181,7 @@
},
"LPCCAPPUCCINO": {
"inherits": ["LPC11U37_501"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"device_name": "LPC11U37FBD64/501"
},
"ARCH_GPRS": {
@@ -192,7 +192,7 @@
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"inherits": ["LPCTarget"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC11U37FBD64/501"
@@ -205,7 +205,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"],
"inherits": ["LPCTarget"],
"detect_code": ["1168"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC11U68JBD100"
@@ -238,7 +238,7 @@
"extra_labels": ["NXP", "LPC176X", "MBED_LPC1768"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"detect_code": ["1010"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
"features": ["LWIP"],
"device_name": "LPC1768"
@@ -250,7 +250,7 @@
"extra_labels": ["NXP", "LPC176X"],
"macros": ["TARGET_LPC1768"],
"inherits": ["LPCTarget"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
"features": ["LWIP"],
"device_name": "LPC1768"
@@ -259,7 +259,7 @@
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M3",
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
- "extra_labels": ["NXP", "LPC176X", "FLASH_CMSIS_ALGO"],
+ "extra_labels": ["NXP", "LPC176X"],
"config": {
"modem_is_on_board": {
"help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
@@ -274,7 +274,7 @@
},
"macros": ["TARGET_LPC1768"],
"inherits": ["LPCTarget"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_RED", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
"features": ["LWIP"],
"device_name": "LPC1768"
@@ -283,10 +283,10 @@
"inherits": ["LPCTarget"],
"core": "Cortex-M3",
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
- "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768", "FLASH_CMSIS_ALGO"],
+ "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
"macros": ["TARGET_LPC1768"],
"detect_code": ["1010"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"device_name": "LPC1768"
},
"LPC810": {
@@ -296,7 +296,7 @@
"extra_labels": ["NXP", "LPC81X"],
"is_disk_virtual": true,
"supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
- "device_has": ["ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"device_name": "LPC810M021FN8"
},
@@ -309,7 +309,7 @@
"supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
"inherits": ["LPCTarget"],
"detect_code": ["1050"],
- "device_has": ["ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC812M101JDH20"
@@ -322,7 +322,7 @@
"is_disk_virtual": true,
"supported_toolchains": ["uARM", "GCC_ARM", "GCC_CR", "IAR"],
"inherits": ["LPCTarget"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC824M201JDH20"
@@ -334,7 +334,7 @@
"extra_labels": ["NXP", "LPC82X"],
"is_disk_virtual": true,
"supported_toolchains": ["uARM", "GCC_ARM"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"]
},
@@ -347,7 +347,7 @@
"post_binary_hook": {
"function": "LPC4088Code.binary_hook"
},
- "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"features": ["LWIP"],
"device_name": "LPC4088FBD144"
},
@@ -364,7 +364,7 @@
"core": "Cortex-M4F",
"extra_labels": ["NXP", "LPC43XX", "LPC4330"],
"supported_toolchains": ["ARM", "GCC_CR", "IAR", "GCC_ARM"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_name": "LPC4330"
},
"LPC4330_M0": {
@@ -372,14 +372,14 @@
"core": "Cortex-M0",
"extra_labels": ["NXP", "LPC43XX", "LPC4330"],
"supported_toolchains": ["ARM", "GCC_CR", "IAR"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
+ "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
},
"LPC4337": {
"inherits": ["LPCTarget"],
"core": "Cortex-M4F",
"extra_labels": ["NXP", "LPC43XX", "LPC4337"],
"supported_toolchains": ["ARM"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ERROR_RED", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2"],
"device_name": "LPC4337"
},
@@ -398,7 +398,7 @@
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR"],
"inherits": ["LPCTarget"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "LPC11U37HFBD64/401"
@@ -422,7 +422,7 @@
"is_disk_virtual": true,
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_lib": "small",
"release_versions": ["2"],
"device_name": "MKL05Z32xxx4"
@@ -435,7 +435,7 @@
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"detect_code": ["0200"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name": "MKL25Z128xxx4"
},
@@ -446,7 +446,7 @@
"is_disk_virtual": true,
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_name": "MKL26Z128xxx4"
},
"KL46Z": {
@@ -457,7 +457,7 @@
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"inherits": ["Target"],
"detect_code": ["0220"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "MKL46Z256xxx4",
"bootloader_supported": true
@@ -469,7 +469,7 @@
"is_disk_virtual": true,
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"detect_code": ["0230"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2"],
"device_name": "MK20DX128xxx5"
},
@@ -485,7 +485,7 @@
"toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
},
"detect_code": ["0230"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2"],
"device_name": "MK20DX256xxx7"
},
@@ -498,7 +498,7 @@
"macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0231"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
"device_name": "MK22DN512xxx5"
},
"K22F": {
@@ -517,7 +517,7 @@
"is_disk_virtual": true,
"default_toolchain": "ARM",
"detect_code": ["0261"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_lib": "std",
"release_versions": ["2"],
"device_name": "MKL27Z64xxx4"
@@ -531,7 +531,7 @@
"is_disk_virtual": true,
"inherits": ["Target"],
"detect_code": ["0262"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name": "MKL43Z256xxx4"
},
@@ -544,7 +544,7 @@
"is_disk_virtual": true,
"inherits": ["Target"],
"detect_code": ["0218"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
"release_versions": ["2", "5"],
"device_name": "MKL82Z128xxx7"
},
@@ -563,9 +563,10 @@
"macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0250"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
- "device_name": "MKW24D512xxx5"
+ "device_name": "MKW24D512xxx5",
+ "bootloader_supported": true
},
"KW41Z": {
"supported_form_factors": ["ARDUINO"],
@@ -576,7 +577,7 @@
"macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0201"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name": "MKW41Z512xxx4"
},
@@ -588,7 +589,7 @@
"public": false,
"macros": ["CPU_MK24FN1M0VDC12", "FSL_RTOS_MBED"],
"inherits": ["Target"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
"device_name": "MK24FN1M0xxx12"
},
"RO359B": {
@@ -606,7 +607,7 @@
"macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0240"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
"features": ["LWIP", "STORAGE"],
"release_versions": ["2", "5"],
"device_name": "MK64FN1M0xxx12",
@@ -631,7 +632,7 @@
"is_disk_virtual": true,
"default_toolchain": "ARM",
"detect_code": ["0214"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
"default_lib": "std",
"release_versions": ["2", "5"],
"device_name": "MK64FN1M0xxx12"
@@ -645,7 +646,7 @@
"macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0311"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "MK66FN2M0xxx18"
@@ -659,7 +660,7 @@
"macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0217"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
"release_versions": ["2", "5"],
"device_name": "MK82FN256xxx15"
},
@@ -685,7 +686,7 @@
"macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["1054"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name" : "LPC54114J256BD64"
},
@@ -698,7 +699,7 @@
"macros": ["CPU_LPC54608J512ET180", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["1056"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name" : "LPC54608J512ET180"
},
@@ -964,7 +965,7 @@
},
"detect_code": ["0720"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ERROR_RED", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F401RE"
},
@@ -981,7 +982,7 @@
}
},
"detect_code": ["0744"],
- "device_has_add": ["ANALOGOUT", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F410RB"
},
@@ -1004,7 +1005,7 @@
}
},
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "device_has_add": ["LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F411RE"
},
@@ -1022,7 +1023,7 @@
},
"detect_code": ["0826"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F412ZG",
"bootloader_supported": true
@@ -1041,7 +1042,7 @@
},
"detect_code": ["0743"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F413ZH"
},
@@ -1081,7 +1082,7 @@
},
"extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
"detect_code": ["0796"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
@@ -1111,7 +1112,7 @@
},
"extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "STM32F439xI"],
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
"detect_code": ["0797"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
@@ -1132,7 +1133,7 @@
},
"detect_code": ["0777"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F446RE"
},
@@ -1150,7 +1151,7 @@
},
"detect_code": ["0778"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F446ZE"
},
@@ -1160,7 +1161,7 @@
"core": "Cortex-M4F",
"extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446VE"],
"detect_code": ["0840"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
"release_versions": ["2", "5"],
"device_name":"STM32F446VE"
},
@@ -1183,7 +1184,7 @@
"macros_add": ["USBHOST_OTHER"],
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0816"],
- "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "STM32F746ZG"
@@ -1207,7 +1208,7 @@
"macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0819"],
- "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "STM32F756ZG"
@@ -1231,7 +1232,7 @@
"supported_form_factors": ["ARDUINO"],
"macros_add": ["USBHOST_OTHER"],
"detect_code": ["0818"],
- "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "STM32F767ZI"
@@ -1323,7 +1324,7 @@
}
},
"detect_code": ["0710"],
- "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+ "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32L152RE"
},
@@ -1449,7 +1450,7 @@
"extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
"macros_add": ["USB_STM_HAL"],
- "device_has_add": ["ANALOGOUT", "ERROR_RED"],
+ "device_has_add": ["ANALOGOUT"],
"device_name": "STM32F407VG"
},
"DISCO_F429ZI": {
@@ -1469,7 +1470,7 @@
}
},
"macros_add": ["RTC_LSI=1", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F429ZI"
},
@@ -1486,7 +1487,7 @@
}
},
"detect_code": ["0788"],
- "device_has_add": ["ANALOGOUT", "CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_FC", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F469NI"
},
@@ -1538,7 +1539,7 @@
}
},
"detect_code": ["0815"],
- "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "STM32F746NG"
@@ -1556,7 +1557,7 @@
}
},
"detect_code": ["0817"],
- "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "STM32F769NI"
@@ -1662,6 +1663,11 @@
"device_name": "STM32L151CC",
"bootloader_supported": true
},
+ "FF1705_L151CC": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["XDOT_L151CC"],
+ "detect_code": ["8080"]
+ },
"MOTE_L152RC": {
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M3",
@@ -1680,7 +1686,7 @@
"default_toolchain": "GCC_ARM",
"extra_labels_add": ["STM32F4", "STM32F401", "STM32F401xC", "STM32F401VC"],
"supported_toolchains": ["GCC_ARM"],
- "device_has_add": ["ERROR_RED"],
+ "device_has_add": [],
"device_name": "STM32F401VC"
},
"UBLOX_EVK_ODIN_W2": {
@@ -1787,7 +1793,7 @@
},
"program_cycle_s": 6,
"features": ["BLE"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
},
"MCU_NRF51_16K_BASE": {
"inherits": ["MCU_NRF51"],
@@ -2014,7 +2020,7 @@
"inherits": ["MCU_NRF51_32K"],
"program_cycle_s": 10,
"macros_add": ["TARGET_NRF_LFCLK_RC"],
- "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"release_versions": ["2"],
"device_name": "nRF51822_xxAA"
},
@@ -2033,7 +2039,7 @@
"DELTA_DFCM_NNN50": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF51_32K_UNIFIED"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"device_name": "nRF51822_xxAC"
},
"DELTA_DFCM_NNN50_BOOT": {
@@ -2131,7 +2137,7 @@
"TY51822R3": {
"inherits": ["MCU_NRF51_32K_UNIFIED"],
"macros_add": ["TARGET_NRF_32MHZ_XTAL"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"detect_code": ["1019"],
"release_versions": ["2", "5"],
"overrides": {"uart_hwfc": 0},
@@ -2248,7 +2254,7 @@
"extra_labels": ["RENESAS", "MBRZA1H"],
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
- "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"features": ["LWIP"],
"release_versions": ["2"]
},
@@ -2259,7 +2265,7 @@
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"default_toolchain": "ARM",
"program_cycle_s": 2,
- "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"features": ["LWIP"],
"default_lib": "std",
"release_versions": ["2"]
@@ -2270,7 +2276,7 @@
"macros": ["__SYSTEM_HFX=24000000"],
"extra_labels": ["Maxim", "MAX32610"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
"features": ["BLE"],
"release_versions": ["2", "5"]
},
@@ -2280,7 +2286,7 @@
"macros": ["__SYSTEM_HFX=24000000"],
"extra_labels": ["Maxim", "MAX32600"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
"release_versions": ["2", "5"]
},
"MAX32620HSP": {
@@ -2288,7 +2294,7 @@
"core": "Cortex-M4F",
"extra_labels": ["Maxim", "MAX32620"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
"features": ["BLE"],
"release_versions": ["2", "5"]
},
@@ -2298,7 +2304,7 @@
"macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
"extra_labels": ["Maxim", "MAX32625"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
"release_versions": ["2", "5"]
},
"MAX32625NEXPAQ": {
@@ -2307,7 +2313,7 @@
"macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
"extra_labels": ["Maxim", "MAX32625"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
"release_versions": ["2", "5"]
},
"MAX32630FTHR": {
@@ -2316,7 +2322,7 @@
"macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132", "BLE_HCI_UART", "OPEN_DRAIN_LEDS"],
"extra_labels": ["Maxim", "MAX32630"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
"features": ["BLE"],
"release_versions": ["2", "5"]
},
@@ -2339,7 +2345,7 @@
"EFM32GG_STK3700": {
"inherits": ["EFM32GG990F1024"],
"progen": {"target": "efm32gg-stk"},
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -2392,7 +2398,7 @@
},
"EFM32LG_STK3600": {
"inherits": ["EFM32LG990F256"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
"forced_reset_timeout": 2,
"device_name": "EFM32LG990F256",
"config": {
@@ -2447,7 +2453,7 @@
"EFM32WG_STK3800": {
"inherits": ["EFM32WG990F256"],
"progen": {"target": "efm32wg-stk"},
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -2501,7 +2507,7 @@
},
"EFM32ZG_STK3200": {
"inherits": ["EFM32ZG222F32"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -2555,7 +2561,7 @@
},
"EFM32HG_STK3400": {
"inherits": ["EFM32HG322F64"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -2608,7 +2614,7 @@
},
"EFM32PG_STK3401": {
"inherits": ["EFM32PG1B100F256GM32"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -2671,7 +2677,7 @@
},
"EFR32MG1_BRD4150": {
"inherits": ["EFR32MG1P132F256GM48"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -2714,7 +2720,7 @@
},
"TB_SENSE_1": {
"inherits": ["EFR32MG1P233F256GM48"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
"forced_reset_timeout": 5,
"config": {
"hf_clock_src": {
@@ -2761,7 +2767,7 @@
},
"EFM32PG12_STK3402": {
"inherits": ["EFM32PG12B500F1024GL125"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -2813,7 +2819,7 @@
},
"TB_SENSE_12": {
"inherits": ["EFR32MG12P332F1024GL125"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
"forced_reset_timeout": 5,
"config": {
"hf_clock_src": {
@@ -2939,7 +2945,9 @@
"S130",
"TARGET_MCU_NRF51822",
"CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
+ "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+ "NO_SYSTICK",
+ "MBED_TICKLESS"
],
"MERGE_BOOTLOADER": false,
"extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5", "SDK11"],
@@ -2973,7 +2981,7 @@
"macro_name": "MBED_CONF_NORDIC_UART_HWFC"
}
},
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
},
"MCU_NRF51_32K_UNIFIED": {
"inherits": ["MCU_NRF51_UNIFIED"],
@@ -2984,20 +2992,20 @@
"NRF51_DK": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF51_32K_UNIFIED"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"],
"device_name": "nRF51822_xxAA"
},
"NRF51_DONGLE": {
"inherits": ["MCU_NRF51_32K_UNIFIED"],
"progen": {"target": "nrf51-dongle"},
- "device_has": ["ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"]
},
"MCU_NRF52": {
"inherits": ["Target"],
"core": "Cortex-M4F",
- "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
"extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"],
"OUTPUT_EXT": "hex",
"is_disk_virtual": true,
@@ -3035,14 +3043,14 @@
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52"],
"macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"],
"device_name": "nRF52832_xxAA"
},
"UBLOX_EVA_NINA": {
"inherits": ["MCU_NRF52"],
"macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"],
"overrides": {"uart_hwfc": 0},
"device_name": "nRF52832_xxAA"
@@ -3051,7 +3059,7 @@
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52"],
"macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"],
"device_name": "nRF52832_xxAA"
},
@@ -3059,7 +3067,7 @@
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52"],
"macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"],
"overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
"config": {
@@ -3116,7 +3124,7 @@
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52840"],
"macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
- "device_has": ["FLASH", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
+ "device_has": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
"release_versions": ["2", "5"],
"device_name": "nRF52840_xxAA"
},
@@ -3229,6 +3237,18 @@
"device_name": "M453VG6AE",
"bootloader_supported": true
},
+ "NUMAKER_PFM_NANO130": {
+ "core": "Cortex-M0",
+ "default_toolchain": "ARM",
+ "extra_labels": ["NUVOTON", "NANO100", "NANO130KE3BN"],
+ "is_disk_virtual": true,
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "inherits": ["Target"],
+ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+ "release_versions": ["5"],
+ "device_name": "NANO130KE3BN"
+ },
"HI2110": {
"inherits": ["Target"],
"core": "Cortex-M0",
@@ -3292,7 +3312,7 @@
"VBLUNO51": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF51_32K_UNIFIED"],
- "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2"],
"device_name": "nRF51822_xxAC"
},
