mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_clk.h@174:b96e65c34a4d, 2017-10-02 (annotated)

Committer:
AnnaBridge
Date:
Mon Oct 02 15:33:19 2017 +0100
Revision:
174:b96e65c34a4d
This updates the lib to the mbed lib v 152

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 174:b96e65c34a4d 1 /**************************************************************************//**
AnnaBridge 174:b96e65c34a4d 2 * @file clk.h
AnnaBridge 174:b96e65c34a4d 3 * @version V1.00
AnnaBridge 174:b96e65c34a4d 4 * $Revision: 20 $
AnnaBridge 174:b96e65c34a4d 5 * $Date: 15/07/08 10:00a $
AnnaBridge 174:b96e65c34a4d 6 * @brief Nano100 series CLK driver header file
AnnaBridge 174:b96e65c34a4d 7 *
AnnaBridge 174:b96e65c34a4d 8 * @note
AnnaBridge 174:b96e65c34a4d 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
AnnaBridge 174:b96e65c34a4d 10 *****************************************************************************/
AnnaBridge 174:b96e65c34a4d 11 #ifndef __CLK_H__
AnnaBridge 174:b96e65c34a4d 12 #define __CLK_H__
AnnaBridge 174:b96e65c34a4d 13
AnnaBridge 174:b96e65c34a4d 14 #ifdef __cplusplus
AnnaBridge 174:b96e65c34a4d 15 extern "C"
AnnaBridge 174:b96e65c34a4d 16 {
AnnaBridge 174:b96e65c34a4d 17 #endif
AnnaBridge 174:b96e65c34a4d 18
AnnaBridge 174:b96e65c34a4d 19
AnnaBridge 174:b96e65c34a4d 20 /** @addtogroup NANO100_Device_Driver NANO100 Device Driver
AnnaBridge 174:b96e65c34a4d 21 @{
AnnaBridge 174:b96e65c34a4d 22 */
AnnaBridge 174:b96e65c34a4d 23
AnnaBridge 174:b96e65c34a4d 24 /** @addtogroup NANO100_CLK_Driver CLK Driver
AnnaBridge 174:b96e65c34a4d 25 @{
AnnaBridge 174:b96e65c34a4d 26 */
AnnaBridge 174:b96e65c34a4d 27
AnnaBridge 174:b96e65c34a4d 28 /** @addtogroup NANO100_CLK_EXPORTED_CONSTANTS CLK Exported Constants
AnnaBridge 174:b96e65c34a4d 29 @{
AnnaBridge 174:b96e65c34a4d 30 */
AnnaBridge 174:b96e65c34a4d 31
AnnaBridge 174:b96e65c34a4d 32
AnnaBridge 174:b96e65c34a4d 33 #define FREQ_128MHZ 128000000
AnnaBridge 174:b96e65c34a4d 34 #define FREQ_120MHZ 120000000
AnnaBridge 174:b96e65c34a4d 35 #define FREQ_48MHZ 48000000
AnnaBridge 174:b96e65c34a4d 36 #define FREQ_42MHZ 42000000
AnnaBridge 174:b96e65c34a4d 37 #define FREQ_32MHZ 32000000
AnnaBridge 174:b96e65c34a4d 38 #define FREQ_24MHZ 24000000
AnnaBridge 174:b96e65c34a4d 39 #define FREQ_12MHZ 12000000
AnnaBridge 174:b96e65c34a4d 40
AnnaBridge 174:b96e65c34a4d 41 /********************* Bit definition of PWRCTL register **********************/
AnnaBridge 174:b96e65c34a4d 42 #define CLK_PWRCTL_HXT_EN (0x1UL<<CLK_PWRCTL_HXT_EN_Pos) /*!<Enable high speed crystal */
AnnaBridge 174:b96e65c34a4d 43 #define CLK_PWRCTL_LXT_EN (0x1UL<<CLK_PWRCTL_LXT_EN_Pos) /*!<Enable low speed crystal */
AnnaBridge 174:b96e65c34a4d 44 #define CLK_PWRCTL_HIRC_EN (0x1UL<<CLK_PWRCTL_HIRC_EN_Pos) /*!<Enable internal high speed oscillator */
AnnaBridge 174:b96e65c34a4d 45 #define CLK_PWRCTL_LIRC_EN (0x1UL<<CLK_PWRCTL_LIRC_EN_Pos) /*!<Enable internal low speed oscillator */
AnnaBridge 174:b96e65c34a4d 46 #define CLK_PWRCTL_DELY_EN (0x1UL<<CLK_PWRCTL_WK_DLY_Pos) /*!<Enable the wake-up delay counter */
AnnaBridge 174:b96e65c34a4d 47 #define CLK_PWRCTL_WAKEINT_EN (0x1UL<<CLK_PWRCTL_PD_WK_IE_Pos) /*!<Enable the wake-up interrupt */
AnnaBridge 174:b96e65c34a4d 48 #define CLK_PWRCTL_PWRDOWN_EN (0x1UL<<CLK_PWRCTL_PD_EN_Pos) /*!<Power down enable bit */
AnnaBridge 174:b96e65c34a4d 49 #define CLK_PWRCTL_HXT_SELXT (0x1UL<<CLK_PWRCTL_HXT_SELXT_Pos) /*!<High frequency crystal loop back path Enabled */
AnnaBridge 174:b96e65c34a4d 50 #define CLK_PWRCTL_HXT_GAIN (0x1UL<<CLK_PWRCTL_HXT_GAIN_Pos) /*!<High frequency crystal Gain control Enabled */
AnnaBridge 174:b96e65c34a4d 51 #define CLK_PWRCTL_LXT_SCNT (0x1UL<<CLK_PWRCTL_LXT_SCNT_Pos) /*!<Delay 8192 LXT before LXT output */
AnnaBridge 174:b96e65c34a4d 52
AnnaBridge 174:b96e65c34a4d 53
AnnaBridge 174:b96e65c34a4d 54 /********************* Bit definition of AHBCLK register **********************/
AnnaBridge 174:b96e65c34a4d 55 #define CLK_AHBCLK_GPIO_EN (0x1UL<<CLK_AHBCLK_GPIO_EN_Pos) /*!<GPIO clock enable */
AnnaBridge 174:b96e65c34a4d 56 #define CLK_AHBCLK_DMA_EN (0x1UL<<CLK_AHBCLK_DMA_EN_Pos) /*!<DMA clock enable */
AnnaBridge 174:b96e65c34a4d 57 #define CLK_AHBCLK_ISP_EN (0x1UL<<CLK_AHBCLK_ISP_EN_Pos) /*!<Flash ISP controller clock enable */
AnnaBridge 174:b96e65c34a4d 58 #define CLK_AHBCLK_EBI_EN (0x1UL<<CLK_AHBCLK_EBI_EN_Pos) /*!<EBI clock enable */
AnnaBridge 174:b96e65c34a4d 59 #define CLK_AHBCLK_SRAM_EN (0x1UL<<CLK_AHBCLK_SRAM_EN_Pos) /*!<SRAM Controller Clock Enable */
AnnaBridge 174:b96e65c34a4d 60 #define CLK_AHBCLK_TICK_EN (0x1UL<<CLK_AHBCLK_TICK_EN_Pos) /*!<System Tick Clock Enable */
AnnaBridge 174:b96e65c34a4d 61
AnnaBridge 174:b96e65c34a4d 62 /********************* Bit definition of APBCLK register **********************/
AnnaBridge 174:b96e65c34a4d 63 #define CLK_APBCLK_WDT_EN (0x1UL<<CLK_APBCLK_WDT_EN_Pos) /*!<Watchdog clock enable */
AnnaBridge 174:b96e65c34a4d 64 #define CLK_APBCLK_RTC_EN (0x1UL<<CLK_APBCLK_RTC_EN_Pos) /*!<RTC clock enable */
AnnaBridge 174:b96e65c34a4d 65 #define CLK_APBCLK_TMR0_EN (0x1UL<<CLK_APBCLK_TMR0_EN_Pos) /*!<Timer 0 clock enable */
AnnaBridge 174:b96e65c34a4d 66 #define CLK_APBCLK_TMR1_EN (0x1UL<<CLK_APBCLK_TMR1_EN_Pos) /*!<Timer 1 clock enable */
AnnaBridge 174:b96e65c34a4d 67 #define CLK_APBCLK_TMR2_EN (0x1UL<<CLK_APBCLK_TMR2_EN_Pos) /*!<Timer 2 clock enable */
AnnaBridge 174:b96e65c34a4d 68 #define CLK_APBCLK_TMR3_EN (0x1UL<<CLK_APBCLK_TMR3_EN_Pos) /*!<Timer 3 clock enable */
AnnaBridge 174:b96e65c34a4d 69 #define CLK_APBCLK_FDIV_EN (0x1UL<<CLK_APBCLK_FDIV_EN_Pos) /*!<Frequency Divider Output clock enable */
AnnaBridge 174:b96e65c34a4d 70 #define CLK_APBCLK_SC2_EN (0x1UL<<CLK_APBCLK_SC2_EN_Pos) /*!<SmartCard 2 Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 71 #define CLK_APBCLK_I2C0_EN (0x1UL<<CLK_APBCLK_I2C0_EN_Pos) /*!<I2C 0 clock enable */
AnnaBridge 174:b96e65c34a4d 72 #define CLK_APBCLK_I2C1_EN (0x1UL<<CLK_APBCLK_I2C1_EN_Pos) /*!<I2C 1 clock enable */
AnnaBridge 174:b96e65c34a4d 73 #define CLK_APBCLK_SPI0_EN (0x1UL<<CLK_APBCLK_SPI0_EN_Pos) /*!<SPI 0 clock enable */
AnnaBridge 174:b96e65c34a4d 74 #define CLK_APBCLK_SPI1_EN (0x1UL<<CLK_APBCLK_SPI1_EN_Pos) /*!<SPI 1 clock enable */
AnnaBridge 174:b96e65c34a4d 75 #define CLK_APBCLK_SPI2_EN (0x1UL<<CLK_APBCLK_SPI2_EN_Pos) /*!<SPI 2 clock enable */
AnnaBridge 174:b96e65c34a4d 76 #define CLK_APBCLK_UART0_EN (0x1UL<<CLK_APBCLK_UART0_EN_Pos) /*!<UART 0 clock enable */
AnnaBridge 174:b96e65c34a4d 77 #define CLK_APBCLK_UART1_EN (0x1UL<<CLK_APBCLK_UART1_EN_Pos) /*!<UART 1 clock enable */
AnnaBridge 174:b96e65c34a4d 78 #define CLK_APBCLK_PWM0_CH01_EN (0x1UL<<CLK_APBCLK_PWM0_CH01_EN_Pos) /*!<PWM0 Channel 0 and Channel 1 Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 79 #define CLK_APBCLK_PWM0_CH23_EN (0x1UL<<CLK_APBCLK_PWM0_CH23_EN_Pos) /*!<PWM0 Channel 2 and Channel 3 Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 80 #define CLK_APBCLK_PWM1_CH01_EN (0x1UL<<CLK_APBCLK_PWM1_CH01_EN_Pos) /*!<PWM1 Channel 0 and Channel 1 Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 81 #define CLK_APBCLK_PWM1_CH23_EN (0x1UL<<CLK_APBCLK_PWM1_CH23_EN_Pos) /*!<PWM1 Channel 2 and Channel 3 Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 82 #define CLK_APBCLK_DAC_EN (0x1UL<<CLK_APBCLK_DAC_EN_Pos) /*!<DAC Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 83 #define CLK_APBCLK_LCD_EN (0x1UL<<CLK_APBCLK_LCD_EN_Pos) /*!<LCD Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 84 #define CLK_APBCLK_USBD_EN (0x1UL<<CLK_APBCLK_USBD_EN_Pos) /*!<USB device clock enable */
AnnaBridge 174:b96e65c34a4d 85 #define CLK_APBCLK_ADC_EN (0x1UL<<CLK_APBCLK_ADC_EN_Pos) /*!<ADC clock enable */
AnnaBridge 174:b96e65c34a4d 86 #define CLK_APBCLK_I2S_EN (0x1UL<<CLK_APBCLK_I2S_EN_Pos) /*!<I2S clock enable */
AnnaBridge 174:b96e65c34a4d 87 #define CLK_APBCLK_SC0_EN (0x1UL<<CLK_APBCLK_SC0_EN_Pos) /*!<SmartCard 0 Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 88 #define CLK_APBCLK_SC1_EN (0x1UL<<CLK_APBCLK_SC1_EN_Pos) /*!<SmartCard 1 Clock Enable Control */
AnnaBridge 174:b96e65c34a4d 89
AnnaBridge 174:b96e65c34a4d 90 /********************* Bit definition of CLKSTATUS register **********************/
AnnaBridge 174:b96e65c34a4d 91 #define CLK_CLKSTATUS_HXT_STB (0x1UL<<CLK_CLKSTATUS_HXT_STB_Pos) /*!<External high speed crystal clock source stable flag */
AnnaBridge 174:b96e65c34a4d 92 #define CLK_CLKSTATUS_LXT_STB (0x1UL<<CLK_CLKSTATUS_LXT_STB_Pos) /*!<External low speed crystal clock source stable flag */
AnnaBridge 174:b96e65c34a4d 93 #define CLK_CLKSTATUS_PLL_STB (0x1UL<<CLK_CLKSTATUS_PLL_STB_Pos) /*!<Internal PLL clock source stable flag */
AnnaBridge 174:b96e65c34a4d 94 #define CLK_CLKSTATUS_LIRC_STB (0x1UL<<CLK_CLKSTATUS_LIRC_STB_Pos) /*!<Internal low speed oscillator clock source stable flag */
AnnaBridge 174:b96e65c34a4d 95 #define CLK_CLKSTATUS_HIRC_STB (0x1UL<<CLK_CLKSTATUS_HIRC_STB_Pos) /*!<Internal high speed oscillator clock source stable flag */
AnnaBridge 174:b96e65c34a4d 96 #define CLK_CLKSTATUS_CLK_SW_FAIL (0x1UL<<CLK_CLKSTATUS_CLK_SW_FAIL_Pos) /*!<Clock switch fail flag */
AnnaBridge 174:b96e65c34a4d 97
AnnaBridge 174:b96e65c34a4d 98
AnnaBridge 174:b96e65c34a4d 99 /********************* Bit definition of CLKSEL0 register **********************/
AnnaBridge 174:b96e65c34a4d 100 #define CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 101 #define CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 102 #define CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from PLL */
AnnaBridge 174:b96e65c34a4d 103 #define CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from low speed oscillator */
AnnaBridge 174:b96e65c34a4d 104 #define CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) /*!<Select HCLK clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 105
AnnaBridge 174:b96e65c34a4d 106 /********************* Bit definition of CLKSEL1 register **********************/
AnnaBridge 174:b96e65c34a4d 107 #define CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) /*!<Select LCD clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 108
AnnaBridge 174:b96e65c34a4d 109 #define CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 110 #define CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 111 #define CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from low speed oscillator */
AnnaBridge 174:b96e65c34a4d 112 #define CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from external trigger */
AnnaBridge 174:b96e65c34a4d 113 #define CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) /*!<Select TMR1 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 114
AnnaBridge 174:b96e65c34a4d 115 #define CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 116 #define CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 117 #define CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from low speed oscillator */
AnnaBridge 174:b96e65c34a4d 118 #define CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from external trigger */
AnnaBridge 174:b96e65c34a4d 119 #define CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) /*!<Select TMR0 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 120
AnnaBridge 174:b96e65c34a4d 121 #define CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 122 #define CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 123 #define CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 124 #define CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) /*!<Select PWM0_CH01 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 125
AnnaBridge 174:b96e65c34a4d 126 #define CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 127 #define CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 128 #define CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 129 #define CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) /*!<Select PWM0_CH23 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 130
AnnaBridge 174:b96e65c34a4d 131 #define CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 132 #define CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 133 #define CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from PLL */
AnnaBridge 174:b96e65c34a4d 134 #define CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) /*!<Select ADC clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 135
AnnaBridge 174:b96e65c34a4d 136 #define CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 137 #define CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 138 #define CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from PLL */
AnnaBridge 174:b96e65c34a4d 139 #define CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) /*!<Select UART clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 140
AnnaBridge 174:b96e65c34a4d 141 /********************* Bit definition of CLKSEL2 register **********************/
AnnaBridge 174:b96e65c34a4d 142 #define CLK_CLKSEL2_SPI2_S_PLL (0x0UL<<CLK_CLKSEL2_SPI2_S_Pos) /*!<Select SPI2 clock source from PLL */
AnnaBridge 174:b96e65c34a4d 143 #define CLK_CLKSEL2_SPI2_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI2_S_Pos) /*!<Select SPI2 clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 144
AnnaBridge 174:b96e65c34a4d 145 #define CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) /*!<Select SPI1 clock source from PLL */
AnnaBridge 174:b96e65c34a4d 146 #define CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) /*!<Select SPI1 clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 147
AnnaBridge 174:b96e65c34a4d 148 #define CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) /*!<Select SPI0 clock source from PLL */
AnnaBridge 174:b96e65c34a4d 149 #define CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) /*!<Select SPI0 clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 150
AnnaBridge 174:b96e65c34a4d 151 #define CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select SmartCard clock source from HXT */
AnnaBridge 174:b96e65c34a4d 152 #define CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select smartCard clock source from PLL */
AnnaBridge 174:b96e65c34a4d 153 #define CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) /*!<Select SmartCard clock source from HIRC */
AnnaBridge 174:b96e65c34a4d 154
AnnaBridge 174:b96e65c34a4d 155 #define CLK_CLKSEL2_I2S_S_HXT (0x0UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from HXT */
AnnaBridge 174:b96e65c34a4d 156 #define CLK_CLKSEL2_I2S_S_PLL (0x1UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from PLL */
AnnaBridge 174:b96e65c34a4d 157 #define CLK_CLKSEL2_I2S_S_HIRC (0x2UL<<CLK_CLKSEL2_I2S_S_Pos) /*!<Select I2S clock source from HIRC */
AnnaBridge 174:b96e65c34a4d 158
AnnaBridge 174:b96e65c34a4d 159 #define CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 160 #define CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 161 #define CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from low speed oscillator */
AnnaBridge 174:b96e65c34a4d 162 #define CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from external trigger */
AnnaBridge 174:b96e65c34a4d 163 #define CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) /*!<Select TMR3 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 164
AnnaBridge 174:b96e65c34a4d 165 #define CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 166 #define CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 167 #define CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from low speed oscillator */
AnnaBridge 174:b96e65c34a4d 168 #define CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from external trigger */
AnnaBridge 174:b96e65c34a4d 169 #define CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) /*!<Select TMR2 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 170
AnnaBridge 174:b96e65c34a4d 171 #define CLK_CLKSEL2_PWM1_CH01_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 172 #define CLK_CLKSEL2_PWM1_CH01_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 173 #define CLK_CLKSEL2_PWM1_CH01_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 174 #define CLK_CLKSEL2_PWM1_CH01_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) /*!<Select PWM1_CH01 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 175
AnnaBridge 174:b96e65c34a4d 176 #define CLK_CLKSEL2_PWM1_CH23_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 177 #define CLK_CLKSEL2_PWM1_CH23_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from low speed crystal */
AnnaBridge 174:b96e65c34a4d 178 #define CLK_CLKSEL2_PWM1_CH23_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 179 #define CLK_CLKSEL2_PWM1_CH23_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) /*!<Select PWM1_CH23 clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 180
AnnaBridge 174:b96e65c34a4d 181 #define CLK_CLKSEL2_FRQDIV_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HXT */
AnnaBridge 174:b96e65c34a4d 182 #define CLK_CLKSEL2_FRQDIV_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from LXT */
AnnaBridge 174:b96e65c34a4d 183 #define CLK_CLKSEL2_FRQDIV_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HCLK */
AnnaBridge 174:b96e65c34a4d 184 #define CLK_CLKSEL2_FRQDIV_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!<Select FRQDIV clock source from HIRC */
AnnaBridge 174:b96e65c34a4d 185
AnnaBridge 174:b96e65c34a4d 186 /********************* Bit definition of CLKDIV0 register **********************/
AnnaBridge 174:b96e65c34a4d 187 #define CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
AnnaBridge 174:b96e65c34a4d 188 #define CLK_USB_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_USB_N_Pos) & CLK_CLKDIV0_USB_N_Msk) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
AnnaBridge 174:b96e65c34a4d 189 #define CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) /*!< CLKDIV0 Setting for UART clock divider. It could be 1~16 */
AnnaBridge 174:b96e65c34a4d 190 #define CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) /*!< CLKDIV0 Setting for ADC clock divider. It could be 1~256 */
AnnaBridge 174:b96e65c34a4d 191 #define CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) /*!< CLKDIV0 Setting for SmartCard0 clock divider. It could be 1~16 */
AnnaBridge 174:b96e65c34a4d 192 #define CLK_I2S_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_I2S_N_Pos) & CLK_CLKDIV0_I2S_N_Msk) /*!< CLKDIV0 Setting for I2S clock divider. It could be 1~16 */
AnnaBridge 174:b96e65c34a4d 193
AnnaBridge 174:b96e65c34a4d 194 /********************* Bit definition of CLKDIV1 register **********************/
AnnaBridge 174:b96e65c34a4d 195 #define CLK_SC2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC2_N_Pos ) & CLK_CLKDIV1_SC2_N_Msk) /*!< CLKDIV1 Setting for SmartCard2 clock divider. It could be 1~16 */
AnnaBridge 174:b96e65c34a4d 196 #define CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) /*!< CLKDIV1 Setting for SmartCard1 clock divider. It could be 1~16 */
AnnaBridge 174:b96e65c34a4d 197
AnnaBridge 174:b96e65c34a4d 198 /********************* Bit definition of SysTick register **********************/
AnnaBridge 174:b96e65c34a4d 199 #define CLK_CLKSEL0_STCLKSEL_HCLK (1) /*!< Setting systick clock source as external HCLK */
AnnaBridge 174:b96e65c34a4d 200 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) /*!< Setting systick clock source as external HCLK/8 */
AnnaBridge 174:b96e65c34a4d 201
AnnaBridge 174:b96e65c34a4d 202 /********************* Bit definition of PLLCTL register **********************/
AnnaBridge 174:b96e65c34a4d 203 #define CLK_PLLCTL_OUT_DV (0x1UL<<CLK_PLLCTL_OUT_DV_Pos) /*!<PLL Output Divider Control */
AnnaBridge 174:b96e65c34a4d 204 #define CLK_PLLCTL_PD (0x1UL<<CLK_PLLCTL_PD_Pos) /*!<PLL Power down mode */
AnnaBridge 174:b96e65c34a4d 205 #define CLK_PLLCTL_PLL_SRC_HIRC (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos) /*!<PLL clock source from high speed oscillator */
AnnaBridge 174:b96e65c34a4d 206 #define CLK_PLLCTL_PLL_SRC_HXT (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos) /*!<PLL clock source from high speed crystal */
AnnaBridge 174:b96e65c34a4d 207
AnnaBridge 174:b96e65c34a4d 208 #define CLK_PLLCTL_NR_2 0x000 /*!< For PLL input divider is 2 */
AnnaBridge 174:b96e65c34a4d 209 #define CLK_PLLCTL_NR_4 0x100 /*!< For PLL input divider is 4 */
AnnaBridge 174:b96e65c34a4d 210 #define CLK_PLLCTL_NR_8 0x200 /*!< For PLL input divider is 8 */
AnnaBridge 174:b96e65c34a4d 211 #define CLK_PLLCTL_NR_16 0x300 /*!< For PLL input divider is 16 */
AnnaBridge 174:b96e65c34a4d 212 #define CLK_PLLCON_NF(x) ((x)-32) /*!< x must be constant and 32 <= x <= 95.) */
AnnaBridge 174:b96e65c34a4d 213
AnnaBridge 174:b96e65c34a4d 214 #define CLK_PLLCON_NO_1 0x0000UL /*!< For PLL output divider is 1 */
AnnaBridge 174:b96e65c34a4d 215 #define CLK_PLLCON_NO_2 0x1000UL /*!< For PLL output divider is 2 */
AnnaBridge 174:b96e65c34a4d 216
AnnaBridge 174:b96e65c34a4d 217 #if (__HXT == 12000000)
AnnaBridge 174:b96e65c34a4d 218 #define CLK_PLLCTL_120MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) /*!< Predefined PLLCTL setting for 120MHz PLL output with 12MHz X'tal */
AnnaBridge 174:b96e65c34a4d 219 #define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 96MHz PLL output with 12MHz X'tal */
AnnaBridge 174:b96e65c34a4d 220 #define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz X'tal */
AnnaBridge 174:b96e65c34a4d 221 #define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz X'tal */
AnnaBridge 174:b96e65c34a4d 222 #define CLK_PLLCTL_42MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 42MHz PLL output with 12MHz X'tal */
AnnaBridge 174:b96e65c34a4d 223 #else
AnnaBridge 174:b96e65c34a4d 224 # error "The PLL pre-definitions are only valid when external crystal is 12MHz"
AnnaBridge 174:b96e65c34a4d 225 #endif
AnnaBridge 174:b96e65c34a4d 226 #define CLK_PLLCTL_120MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) /*!< Predefined PLLCTL setting for 120MHz PLL output with 12MHz IRC */
AnnaBridge 174:b96e65c34a4d 227 #define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 96MHz PLL output with 12MHz IRC */
AnnaBridge 174:b96e65c34a4d 228 #define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz IRC */
AnnaBridge 174:b96e65c34a4d 229 #define CLK_PLLCTL_84MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz IRC */
AnnaBridge 174:b96e65c34a4d 230 #define CLK_PLLCTL_42MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) /*!< Predefined PLLCTL setting for 42MHz PLL output with 12MHz IRC */
AnnaBridge 174:b96e65c34a4d 231
AnnaBridge 174:b96e65c34a4d 232 /********************* Bit definition of FRQDIV register **********************/
AnnaBridge 174:b96e65c34a4d 233 #define CLK_FRQDIV_EN (0x1UL<<CLK_FRQDIV_FDIV_EN_Pos) /*!<Frequency divider enable bit */
AnnaBridge 174:b96e65c34a4d 234
AnnaBridge 174:b96e65c34a4d 235 /********************* Bit definition of WK_INTSTS register **********************/
AnnaBridge 174:b96e65c34a4d 236 #define CLK_WK_INTSTS_IS (0x1UL<<CLK_WK_INTSTS_PD_WK_IS_Pos) /*!<Wake-up Interrupt Status in chip Power-down Mode */
AnnaBridge 174:b96e65c34a4d 237
AnnaBridge 174:b96e65c34a4d 238 /********************* Bit definition of MCLKO register **********************/
AnnaBridge 174:b96e65c34a4d 239 #define CLK_MCLKO_MCLK_SEL_ISP_CLK (0x00<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output ISP_CLK */
AnnaBridge 174:b96e65c34a4d 240 #define CLK_MCLKO_MCLK_SEL_HIRC (0x01<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HIRC clock */
AnnaBridge 174:b96e65c34a4d 241 #define CLK_MCLKO_MCLK_SEL_HXT (0x02<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HXT clock */
AnnaBridge 174:b96e65c34a4d 242 #define CLK_MCLKO_MCLK_SEL_LXT (0x03<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LXT clock */
AnnaBridge 174:b96e65c34a4d 243 #define CLK_MCLKO_MCLK_SEL_LIRC (0x04<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LIRC clock */
AnnaBridge 174:b96e65c34a4d 244 #define CLK_MCLKO_MCLK_SEL_PLLO (0x05<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PLL input */
AnnaBridge 174:b96e65c34a4d 245 #define CLK_MCLKO_MCLK_SEL_PLLI (0x06<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PLL input */
AnnaBridge 174:b96e65c34a4d 246 #define CLK_MCLKO_MCLK_SEL_SYSTICK (0x07<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output system tick */
AnnaBridge 174:b96e65c34a4d 247 #define CLK_MCLKO_MCLK_SEL_HCLK (0x08<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output HCLK clock */
AnnaBridge 174:b96e65c34a4d 248 #define CLK_MCLKO_MCLK_SEL_PCLK (0x0A<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PCLK clock */
AnnaBridge 174:b96e65c34a4d 249 #define CLK_MCLKO_MCLK_SEL_TMR0 (0x20<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR0 clock */
AnnaBridge 174:b96e65c34a4d 250 #define CLK_MCLKO_MCLK_SEL_TMR1 (0x21<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR1 clock */
AnnaBridge 174:b96e65c34a4d 251 #define CLK_MCLKO_MCLK_SEL_UART0 (0x22<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output UART0 clock */
AnnaBridge 174:b96e65c34a4d 252 #define CLK_MCLKO_MCLK_SEL_USB (0x23<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output USB clock */
AnnaBridge 174:b96e65c34a4d 253 #define CLK_MCLKO_MCLK_SEL_ADC (0x24<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output ADC clock */
AnnaBridge 174:b96e65c34a4d 254 #define CLK_MCLKO_MCLK_SEL_WDT (0x25<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output WDT clock */
AnnaBridge 174:b96e65c34a4d 255 #define CLK_MCLKO_MCLK_SEL_PWM0CH01 (0x26<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM0CH01 clock */
AnnaBridge 174:b96e65c34a4d 256 #define CLK_MCLKO_MCLK_SEL_PWM0CH23 (0x27<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM0CH23 clock */
AnnaBridge 174:b96e65c34a4d 257 #define CLK_MCLKO_MCLK_SEL_LCD (0x29<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output LCD clock */
AnnaBridge 174:b96e65c34a4d 258 #define CLK_MCLKO_MCLK_SEL_TMR2 (0x38<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR2 clock */
AnnaBridge 174:b96e65c34a4d 259 #define CLK_MCLKO_MCLK_SEL_TMR3 (0x39<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output TMR3 clock */
AnnaBridge 174:b96e65c34a4d 260 #define CLK_MCLKO_MCLK_SEL_UART1 (0x3A<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output UART1 clock */
AnnaBridge 174:b96e65c34a4d 261 #define CLK_MCLKO_MCLK_SEL_PWM1CH01 (0x3B<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM1CH01 clock */
AnnaBridge 174:b96e65c34a4d 262 #define CLK_MCLKO_MCLK_SEL_PWM1CH23 (0x3C<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output PWM1CH23 clock */
AnnaBridge 174:b96e65c34a4d 263 #define CLK_MCLKO_MCLK_SEL_I2S (0x3D<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output I2S clock */
AnnaBridge 174:b96e65c34a4d 264 #define CLK_MCLKO_MCLK_SEL_SC0 (0x3E<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output SC0 clock */
AnnaBridge 174:b96e65c34a4d 265 #define CLK_MCLKO_MCLK_SEL_SC1 (0x3F<<CLK_MCLKO_MCLK_SEL_Pos) /*!<Select MCLK clock output SC1 clock */
AnnaBridge 174:b96e65c34a4d 266
AnnaBridge 174:b96e65c34a4d 267
AnnaBridge 174:b96e65c34a4d 268 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 174:b96e65c34a4d 269 /* MODULE constant definitions. */
AnnaBridge 174:b96e65c34a4d 270 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 174:b96e65c34a4d 271 #define MODULE_APBCLK(x) ((x >>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 272 #define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 273 #define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 274 #define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 275 #define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */
AnnaBridge 174:b96e65c34a4d 276 #define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 277 #define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 278 #define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 279 #define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
AnnaBridge 174:b96e65c34a4d 280 #define NA MODULE_NoMsk /*!< Not Available */
AnnaBridge 174:b96e65c34a4d 281
AnnaBridge 174:b96e65c34a4d 282 #define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK */
AnnaBridge 174:b96e65c34a4d 283 #define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2*/
AnnaBridge 174:b96e65c34a4d 284 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) /*!< CLKSEL mask offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 285 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 286 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV */
AnnaBridge 174:b96e65c34a4d 287 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 288 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 289 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< APBCLK offset on MODULE index */
AnnaBridge 174:b96e65c34a4d 290 /*-------------------------------------------------------------------------------------------------------------------------------*/
AnnaBridge 174:b96e65c34a4d 291 /* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5) */
AnnaBridge 174:b96e65c34a4d 292 /*-------------------------------------------------------------------------------------------------------------------------------*/
AnnaBridge 174:b96e65c34a4d 293 #define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) /*!< TICK Module */
AnnaBridge 174:b96e65c34a4d 294 #define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) /*!< SRAM Module */
AnnaBridge 174:b96e65c34a4d 295 #define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) /*!< EBI Module */
AnnaBridge 174:b96e65c34a4d 296 #define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) /*!< ISP Module */
AnnaBridge 174:b96e65c34a4d 297 #define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) /*!< DMA Module */
AnnaBridge 174:b96e65c34a4d 298 #define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) /*!< GPIO Module */
AnnaBridge 174:b96e65c34a4d 299
AnnaBridge 174:b96e65c34a4d 300 #define SC2_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_SC2_EN_Pos ) /*!< SmartCard2 Module */
AnnaBridge 174:b96e65c34a4d 301 #define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) /*!< SmartCard1 Module */
AnnaBridge 174:b96e65c34a4d 302 #define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) /*!< SmartCard0 Module */
AnnaBridge 174:b96e65c34a4d 303 #define I2S_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(16<<20)|(0<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_I2S_EN_Pos ) /*!< I2S Module */
AnnaBridge 174:b96e65c34a4d 304 #define ADC_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) /*!< ADC Module */
AnnaBridge 174:b96e65c34a4d 305 #define USBD_MODULE ((1UL<<31)|(1<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_USBD_EN_Pos ) /*!< USBD Module */
AnnaBridge 174:b96e65c34a4d 306 #define PWM1_CH23_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH23_EN_Pos) /*!< PWM1 Channel2 and Channel3 Module */
AnnaBridge 174:b96e65c34a4d 307 #define PWM1_CH01_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH01_EN_Pos) /*!< PWM1 Channel0 and Channel1 Module */
AnnaBridge 174:b96e65c34a4d 308 #define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) /*!< PWM0 Channel2 and Channel3 Module */
AnnaBridge 174:b96e65c34a4d 309 #define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) /*!< PWM0 Channel0 and Channel1 Module */
AnnaBridge 174:b96e65c34a4d 310 #define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) /*!< UART1 Module */
AnnaBridge 174:b96e65c34a4d 311 #define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) /*!< UART0 Module */
AnnaBridge 174:b96e65c34a4d 312 #define SPI2_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(22<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI2_EN_Pos ) /*!< SPI0 Module */
AnnaBridge 174:b96e65c34a4d 313 #define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) /*!< SPI1 Module */
AnnaBridge 174:b96e65c34a4d 314 #define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) /*!< SPI0 Module */
AnnaBridge 174:b96e65c34a4d 315 #define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) /*!< I2C1 Module */
AnnaBridge 174:b96e65c34a4d 316 #define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) /*!< I2C0 Module */
AnnaBridge 174:b96e65c34a4d 317 #define FDIV_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV_EN_Pos ) /*!< Frequency Divider0 Output Module */
AnnaBridge 174:b96e65c34a4d 318 #define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) /*!< Timer3 Module */
AnnaBridge 174:b96e65c34a4d 319 #define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) /*!< Timer2 Module */
AnnaBridge 174:b96e65c34a4d 320 #define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) /*!< Timer1 Module */
AnnaBridge 174:b96e65c34a4d 321 #define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) /*!< Timer0 Module */
AnnaBridge 174:b96e65c34a4d 322 #define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) /*!< Real-Time-Clock Module */
AnnaBridge 174:b96e65c34a4d 323 #define WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) /*!< Watchdog Timer Module */
AnnaBridge 174:b96e65c34a4d 324 #define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) /*!< LCD Module */
AnnaBridge 174:b96e65c34a4d 325 #define DAC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_DAC_EN_Pos ) /*!< DAC Module */
AnnaBridge 174:b96e65c34a4d 326 /*@}*/ /* end of group NANO100_CLK_EXPORTED_CONSTANTS */
AnnaBridge 174:b96e65c34a4d 327
AnnaBridge 174:b96e65c34a4d 328
AnnaBridge 174:b96e65c34a4d 329 /** @addtogroup NANO100_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
AnnaBridge 174:b96e65c34a4d 330 @{
AnnaBridge 174:b96e65c34a4d 331 */
AnnaBridge 174:b96e65c34a4d 332 void CLK_DisableCKO(void);
AnnaBridge 174:b96e65c34a4d 333 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
AnnaBridge 174:b96e65c34a4d 334 void CLK_PowerDown(void);
AnnaBridge 174:b96e65c34a4d 335 void CLK_Idle(void);
AnnaBridge 174:b96e65c34a4d 336 uint32_t CLK_GetHXTFreq(void);
AnnaBridge 174:b96e65c34a4d 337 uint32_t CLK_GetLXTFreq(void);
AnnaBridge 174:b96e65c34a4d 338 uint32_t CLK_GetHCLKFreq(void);
AnnaBridge 174:b96e65c34a4d 339 uint32_t CLK_GetCPUFreq(void);
AnnaBridge 174:b96e65c34a4d 340 uint32_t CLK_GetPLLClockFreq(void);
AnnaBridge 174:b96e65c34a4d 341 uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
AnnaBridge 174:b96e65c34a4d 342 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
AnnaBridge 174:b96e65c34a4d 343 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
AnnaBridge 174:b96e65c34a4d 344 void CLK_EnableXtalRC(uint32_t u32ClkMask);
AnnaBridge 174:b96e65c34a4d 345 void CLK_DisableXtalRC(uint32_t u32ClkMask);
AnnaBridge 174:b96e65c34a4d 346 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
AnnaBridge 174:b96e65c34a4d 347 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
AnnaBridge 174:b96e65c34a4d 348 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
AnnaBridge 174:b96e65c34a4d 349 void CLK_DisablePLL(void);
AnnaBridge 174:b96e65c34a4d 350 void CLK_SysTickDelay(uint32_t us);
AnnaBridge 174:b96e65c34a4d 351 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
AnnaBridge 174:b96e65c34a4d 352 void CLK_DisableSysTick(void);
AnnaBridge 174:b96e65c34a4d 353 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
AnnaBridge 174:b96e65c34a4d 354
AnnaBridge 174:b96e65c34a4d 355 /*@}*/ /* end of group NANO100_CLK_EXPORTED_FUNCTIONS */
AnnaBridge 174:b96e65c34a4d 356
AnnaBridge 174:b96e65c34a4d 357 /*@}*/ /* end of group NANO100_CLK_Driver */
AnnaBridge 174:b96e65c34a4d 358
AnnaBridge 174:b96e65c34a4d 359 /*@}*/ /* end of group NANO100_Device_Driver */
AnnaBridge 174:b96e65c34a4d 360
AnnaBridge 174:b96e65c34a4d 361 #ifdef __cplusplus
AnnaBridge 174:b96e65c34a4d 362 }
AnnaBridge 174:b96e65c34a4d 363 #endif
AnnaBridge 174:b96e65c34a4d 364
AnnaBridge 174:b96e65c34a4d 365 #endif //__CLK_H__
AnnaBridge 174:b96e65c34a4d 366
AnnaBridge 174:b96e65c34a4d 367 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/