mbed official
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
Revision 77:869cf507173a, committed 2014-02-14
- Comitter:
- emilmont
- Date:
- Fri Feb 14 14:36:43 2014 +0000
- Parent:
- 76:824293ae5e43
- Child:
- 78:ed8466a608b4
- Commit message:
- Release 77 of the mbed library
Main changes:
* Add target NUCLEO_F030R8
* Add target NUCLEO_F401RE
* Add target NUCLEO_F103RB
* Add target NUCLEO_L152RE
Changed in this revision
--- a/TARGET_KL25Z/PeripheralNames.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_KL25Z/PeripheralNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -23,6 +23,11 @@
#endif
typedef enum {
+ OSC32KCLK = 0,
+ RTC_CLKIN = 2
+} RTCName;
+
+typedef enum {
UART_0 = (int)UART0_BASE,
UART_1 = (int)UART1_BASE,
UART_2 = (int)UART2_BASE
@@ -52,7 +57,7 @@
PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1
} PWMName;
-#define CHANNELS_A_SHIFT 5
+#define CHANNELS_A_SHIFT 5
typedef enum {
ADC0_SE0 = 0,
ADC0_SE3 = 3,
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KL25Z/PeripheralPins.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/system_MKL25Z4.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_GCC_ARM/libmbed.a has changed
Binary file TARGET_KL25Z/TOOLCHAIN_GCC_ARM/retarget.o has changed
--- a/TARGET_KL25Z/clk_freqs.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_KL25Z/clk_freqs.h Fri Feb 14 14:36:43 2014 +0000
@@ -20,6 +20,8 @@
extern "C" {
#endif
+#include "PeripheralPins.h"
+
//Get the peripheral bus clock frequency
static inline uint32_t bus_frequency(void) {
return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
@@ -32,9 +34,11 @@
if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
return MCGClock;
+ uint32_t divider, multiplier;
+ #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
- uint32_t divider, multiplier;
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
+ #endif
if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
@@ -70,12 +74,14 @@
return MCGClock * divider / multiplier;
}
+ #ifdef MCG_C5_PLLCLKEN0_MASK
} else { //PLL is selected
divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
- multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
- return MCGClock * divider / multiplier;
+ multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ return MCGClock * divider / multiplier;
}
}
+ #endif
//In all other cases either there is no crystal or we cannot determine it
//For example when the FLL is running on the internal reference, and there is also an
@@ -83,6 +89,27 @@
return 0;
}
+//Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
+static uint32_t mcgpllfll_frequency(void) {
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
+ return 0;
+
+ uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
+ #ifdef MCG_C5_PLLCLKEN0_MASK
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
+ SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
+ #endif
+ return MCGClock;
+ #ifdef MCG_C5_PLLCLKEN0_MASK
+ } else { //PLL is selected
+ SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
+ return (MCGClock >> 1);
+ }
+ #endif
+
+ //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
+ //for the peripherals, this is however an unlikely setup
+}
#ifdef __cplusplus
}
--- a/TARGET_KL25Z/objects.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_KL25Z/objects.h Fri Feb 14 14:36:43 2014 +0000
@@ -25,6 +25,10 @@
extern "C" {
#endif
+#ifdef TARGET_KL46Z
+#define UARTLP_Type UART0_Type
+#endif
+
struct gpio_irq_s {
uint32_t port;
uint32_t pin;
--- a/TARGET_KL46Z/PeripheralNames.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_KL46Z/PeripheralNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -23,6 +23,11 @@
#endif
typedef enum {
+ OSC32KCLK = 0,
+ RTC_CLKIN = 2
+} RTCName;
+
+typedef enum {
UART_0 = (int)UART0_BASE,
UART_1 = (int)UART1_BASE,
UART_2 = (int)UART2_BASE
@@ -52,7 +57,7 @@
PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1
} PWMName;
-#define CHANNELS_A_SHIFT 5
+#define CHANNELS_A_SHIFT 5
typedef enum {
ADC0_SE0 = 0,
ADC0_SE3 = 3,
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_KL46Z/PeripheralPins.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif
--- a/TARGET_KL46Z/PinNames.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_KL46Z/PinNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -197,13 +197,13 @@
// mbed original LED naming
LED1 = LED_GREEN,
LED2 = LED_RED,
- LED3 = LED_GREEN,
+ LED3 = LED_GREEN,
LED4 = LED_RED,
//Push buttons
SW1 = PTC3,
SW3 = PTC12,
-
+
// USB Pins
USBTX = PTA2,
USBRX = PTA1,
Binary file TARGET_KL46Z/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_KL46Z/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_KL46Z/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.o has changed
Binary file TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_KL46Z/TOOLCHAIN_ARM_STD/system_MKL46Z4.o has changed
Binary file TARGET_KL46Z/TOOLCHAIN_GCC_ARM/libmbed.a has changed
Binary file TARGET_KL46Z/TOOLCHAIN_GCC_ARM/retarget.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_KL46Z/clk_freqs.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CLK_FREQS_H
+#define MBED_CLK_FREQS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "PeripheralPins.h"
+
+//Get the peripheral bus clock frequency
+static inline uint32_t bus_frequency(void) {
+ return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
+}
+
+//Get external oscillator (crystal) frequency
+static uint32_t extosc_frequency(void) {
+ uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
+ return MCGClock;
+
+ uint32_t divider, multiplier;
+ #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
+ #endif
+ if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
+ divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
+ divider <<= 5u;
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ multiplier = 640u;
+ break;
+ case 0x20u:
+ multiplier = 1280u;
+ break;
+ case 0x40u:
+ multiplier = 1920u;
+ break;
+ case 0x60u:
+ multiplier = 2560u;
+ break;
+ case 0x80u:
+ multiplier = 732u;
+ break;
+ case 0xA0u:
+ multiplier = 1464u;
+ break;
+ case 0xC0u:
+ multiplier = 2197u;
+ break;
+ case 0xE0u:
+ default:
+ multiplier = 2929u;
+ break;
+ }
+
+ return MCGClock * divider / multiplier;
+ }
+ #ifdef MCG_C5_PLLCLKEN0_MASK
+ } else { //PLL is selected
+ divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ return MCGClock * divider / multiplier;
+ }
+ }
+ #endif
+
+ //In all other cases either there is no crystal or we cannot determine it
+ //For example when the FLL is running on the internal reference, and there is also an
+ //external crystal. However these are unlikely situations
+ return 0;
+}
+
+//Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
+static uint32_t mcgpllfll_frequency(void) {
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
+ return 0;
+
+ uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
+ #ifdef MCG_C5_PLLCLKEN0_MASK
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
+ SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
+ #endif
+ return MCGClock;
+ #ifdef MCG_C5_PLLCLKEN0_MASK
+ } else { //PLL is selected
+ SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
+ return (MCGClock >> 1);
+ }
+ #endif
+
+ //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
+ //for the peripherals, this is however an unlikely setup
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_KL46Z/objects.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_KL46Z/objects.h Fri Feb 14 14:36:43 2014 +0000
@@ -25,6 +25,10 @@
extern "C" {
#endif
+#ifdef TARGET_KL46Z
+#define UARTLP_Type UART0_Type
+#endif
+
struct gpio_irq_s {
uint32_t port;
uint32_t pin;
@@ -46,7 +50,7 @@
};
struct serial_s {
- UART0_Type *uart;
+ UARTLP_Type *uart;
int index;
};
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/system_LPC11xx.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/system_LPC11Uxx.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/startup_LPC11xx.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/system_LPC11Uxx.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_MICRO/system_LPC11Uxx.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_STD/startup_LPC11xx.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC11U35_401/TOOLCHAIN_ARM_STD/system_LPC11Uxx.o has changed
--- a/TARGET_LPC11U35_401/device.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_LPC11U35_401/device.h Fri Feb 14 14:36:43 2014 +0000 @@ -41,8 +41,8 @@ #define DEVICE_PWMOUT 1 -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 #define DEVICE_ID_LENGTH 32 #define DEVICE_MAC_OFFSET 20 @@ -50,7 +50,7 @@ #define DEVICE_DEBUG_AWARENESS 0 -#define DEVICE_STDIO_MESSAGES 1 +#define DEVICE_STDIO_MESSAGES 0 #define DEVICE_ERROR_PATTERN 1
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/startup_LPC13xx.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/system_LPC13Uxx.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/startup_LPC17xx.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/system_LPC17xx.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_ARM/libmbed.a has changed
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_ARM/retarget.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_CR/libmbed.a has changed
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_CR/retarget.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_CS/libmbed.a has changed
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_CS/retarget.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/cmsis_nvic.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/mbed.a has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/retarget.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/startup_LPC17xx.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/system_LPC17xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1768/reserved_pins.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,8 @@
+// List of reserved pins for MBED LPC1768
+
+#ifndef RESERVED_PINS_H
+#define RESERVED_PINS_H
+
+#define TARGET_RESERVED_PINS {}
+
+#endif
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/core_arm7.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/system_LPC23xx.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/vector_functions.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/vector_realmonitor.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/vector_table.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/startup_LPC407x_8x_177x_8x.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/sys_helper.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/system_LPC407x_8x_177x_8x.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_GCC_ARM/libmbed.a has changed
Binary file TARGET_LPC4088/TOOLCHAIN_GCC_ARM/retarget.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_GCC_CR/libmbed.a has changed
Binary file TARGET_LPC4088/TOOLCHAIN_GCC_CR/retarget.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/system_LPC8xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/PeripheralNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+ TIM_3 = (int)TIM3_BASE,
+ TIM_14 = (int)TIM14_BASE,
+ TIM_16 = (int)TIM16_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/PinNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,175 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// MODE (see GPIOMode_TypeDef structure)
+// OTYPE (see GPIOOType_TypeDef structure)
+// PUPD (see GPIOPuPd_TypeDef structure)
+// AFNUM (see AF_mapping constant table, 0xFF is not used)
+#define STM_PIN_DATA(MODE, OTYPE, PUPD, AFNUM) (((AFNUM)<<8)|((PUPD)<<4)|((OTYPE)<<2)|((MODE)<<0))
+#define STM_PIN_MODE(X) (((X)>>0) & 0x3)
+#define STM_PIN_OTYPE(X) (((X)>>2) & 0x1)
+#define STM_PIN_PUPD(X) (((X)>>4) & 0x3)
+#define STM_PIN_AFNUM(X) (((X)>>8) & 0xF)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ USER_BUTTON = PC_13,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/PortNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortF = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/startup_stm32f030.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F030R8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
+
+ LR_IROM1 0x08000000 0x10000 { ; load region size_region
+ ER_IROM1 0x08000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 45 vectors = 180 bytes (0xB4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB4) (0x2000-0xB4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_adc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_can.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_cec.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_comp.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_crc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_crs.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_dac.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_dma.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_exti.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_flash.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_gpio.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_i2c.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_iwdg.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_misc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_pwr.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_rcc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_rtc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_spi.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_syscfg.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_tim.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_usart.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_wwdg.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/system_stm32f0xx.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/startup_stm32f030.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F030R8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
+
+ LR_IROM1 0x08000000 0x10000 { ; load region size_region
+ ER_IROM1 0x08000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 45 vectors = 180 bytes (0xB4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB4) (0x2000-0xB4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_adc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_can.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_cec.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_comp.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_crc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_crs.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_dac.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_dma.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_exti.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_flash.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_gpio.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_i2c.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_iwdg.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_misc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_pwr.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_rcc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_rtc.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_spi.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_syscfg.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_tim.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_usart.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_wwdg.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/system_stm32f0xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_F030R8/cmsis.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f0xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/cmsis_nvic.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F030R8
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 29 vectors = 116 bytes from 0x40 to 0xB3
+// Total: 45 vectors = 180 bytes (0xB4) to be reserved in RAM (see scatter file)
+#define NVIC_NUM_VECTORS 45
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/core_cm0.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/core_cm0plus.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/core_cm3.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/core_cm4.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/core_cm4_simd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/core_cmFunc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/core_cmInstr.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_F030R8/device.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 0 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +//#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/gpio_object.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint16_t *reg_in;
+ __IO uint32_t *reg_set;
+ __IO uint16_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value) {
+ *obj->reg_set = obj->mask;
+ }
+ else {
+ *obj->reg_clr = obj->mask;
+ }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/objects.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint16_t *reg_in;
+ __IO uint16_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct dac_s {
+ DACName dac;
+ PinName channel;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+};
+
+struct i2c_s {
+ I2CName i2c;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,5111 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V1.3.1
+ * @date 17-January-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F0xx devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripheralâs drivers in application code(i.e.
+ * code will be based on direct access to peripheralâs registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheralâs registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0XX_H
+#define __STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32F0 device used in your
+ application
+ */
+
+#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
+#define STM32F030
+ /* #define STM32F031 */
+ /* #define STM32F051 */
+ /* #define STM32F072 */
+ /* #define STM32F042 */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+/* Old STM32F0XX definition, maintained for legacy purpose */
+#if defined(STM32F0XX) || defined(STM32F0XX_MD)
+ #define STM32F051
+#endif /* STM32F0XX */
+
+/* Old STM32F0XX_LD definition, maintained for legacy purpose */
+#ifdef STM32F0XX_LD
+ #define STM32F031
+#endif /* STM32F0XX_LD */
+
+/* Old STM32F0XX_HD definition, maintained for legacy purpose */
+#ifdef STM32F0XX_HD
+ #define STM32F072
+#endif /* STM32F0XX_HD */
+
+/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
+#if defined (STM32F030X8) || defined (STM32F030X6)
+ #define STM32F030
+#endif /* STM32F030X8 or STM32F030X6 */
+
+
+#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_STDPERIPH_DRIVER
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif /* HSI_VALUE */
+
+#if !defined (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif /* HSI14_VALUE */
+
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif /* HSI48_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif /* LSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief STM32F0xx Standard Peripheral Library version number V1.3.1
+ */
+#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief STM32F0xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+#if defined (STM32F051)
+/****** STM32F051 specific Interrupt Numbers *************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TS_IRQn = 8, /*!< Touch sense controller Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM14_IRQn = 19, /*!< TIM14 Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ CEC_IRQn = 30 /*!< CEC Interrupt */
+#elif defined (STM32F031)
+/****** STM32F031 specific Interrupt Numbers *************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupt */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART1_IRQn = 27 /*!< USART1 Interrupt */
+#elif defined (STM32F030)
+/****** STM32F030 specific Interrupt Numbers *************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupt */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28 /*!< USART2 Interrupt */
+#elif defined (STM32F072)
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM7_IRQn = 18, /*!< TIM7 Interrupts */
+ TIM14_IRQn = 19, /*!< TIM14 Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */
+ CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
+ USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
+#elif defined (STM32F042)
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupts */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
+ USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
+#endif /* STM32F051 */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h"
+#include "system_stm32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief HDMI-CEC
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+ __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
+ __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ uint16_t RESERVED1; /*!< Reserved, 0x12 */
+ __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ uint16_t RESERVED2; /*!< Reserved, 0x16 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ uint16_t RESERVED3; /*!< Reserved, 0x2A */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register,(only for STM32F072 devices) Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+/* Old register name definition maintained for legacy purpose */
+#define CAL CALR
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ uint16_t RESERVED10; /*!< Reserved, 0x2A */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ uint16_t RESERVED12; /*!< Reserved, 0x32 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ uint16_t RESERVED17; /*!< Reserved, 0x26 */
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ uint16_t RESERVED18; /*!< Reserved, 0x4A */
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ uint16_t RESERVED19; /*!< Reserved, 0x4E */
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
+ uint16_t RESERVED20; /*!< Reserved, 0x52 */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ __IO uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ uint16_t RESERVED2; /*!< Reserved, 0x12 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ uint16_t RESERVED3; /*!< Reserved, 0x1A */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED4; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED5; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
+#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
+#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN ((CAN_TypeDef *) CAN_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LREGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIEIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/*********************** Bit definition for COMP_CSR register ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits (only for STM32F072 devices)*/
+#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for STM32F072 devices) */
+#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for STM32F072 devices) */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for STM32F072 devices) */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/* (Available only for STM32F072 devices) */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
+#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
+#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
+#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
+#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
+#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
+#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
+#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
+#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
+#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
+#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
+#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
+#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
+#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
+#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
+#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
+#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Underrun Interrupt enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA Underrun Interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted (only for STM32F072 devices) */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted (only for STM32F072 devices) */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag (only for STM32F072 devices) */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag (only for STM32F072 devices) */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag (only for STM32F072 devices) */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag (only for STM32F072 devices) */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag (only for STM32F072 devices) */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag (only for STM32F072 devices) */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag (only for STM32F072 devices) */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag (only for STM32F072 devices) */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear (only for STM32F072 devices) */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear (only for STM32F072 devices) */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear (only for STM32F072 devices) */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear (only for STM32F072 devices) */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear (only for STM32F072 devices) */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear (only for STM32F072 devices) */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear (only for STM32F072 devices) */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear (only for STM32F072 devices) */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level bit 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level bit 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT0 ((uint32_t)0x00000800) /*!< nBOOT0 */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM Parity Check */
+#define FLASH_OBR_nBOOT0_SW ((uint32_t)0x00008000) /*!< nBOOT0 SW (available only in the STM32F042 devices)*/
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< DATA0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< DATA0 */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP1 register *********************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP2 register *********************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
+
+/****************** Bit definition for OB_WRP3 register *********************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFR0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFR1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFR2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFR3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFR4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFR5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFR6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFR7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFR8 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFR9 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFR10 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFR11 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFR12 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFR13 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFR14 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFR15 ((uint32_t)0xF0000000)
+
+/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFR0
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFR1
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFR2
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFR3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFR4
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFR5
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFR6
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFR7
+
+/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFR8
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFR9
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFR10
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFR11
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFR12
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFR13
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFR14
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFR15
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+/* PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define PWR_CR_LPSDSR PWR_CR_LPDS /*!< Low-power deepsleep */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDY ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready */
+
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
+#define PWR_CSR_EWUP4 ((uint16_t)0x0800) /*!< Enable WKUP pin 4 */
+#define PWR_CSR_EWUP5 ((uint16_t)0x1000) /*!< Enable WKUP pin 5 */
+#define PWR_CSR_EWUP6 ((uint16_t)0x2000) /*!< Enable WKUP pin 6 */
+#define PWR_CSR_EWUP7 ((uint16_t)0x4000) /*!< Enable WKUP pin 7 */
+#define PWR_CSR_EWUP8 ((uint16_t)0x8000) /*!< Enable WKUP pin 8 */
+
+/* Old Bit definition maintained for legacy purpose ****/
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDY /*!< Internal voltage reference (VREFINT) ready flag */
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+/* SW configuration */
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
+
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+/* SWS configuration */
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 used as system clock */
+
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+/* HPRE configuration */
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+/* PPRE configuration */
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
+ done inside the ADC_CFGR2 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_0 ((uint32_t)0x00008000) /*!< Bit 0 (available only in the STM32F072 devices) */
+#define RCC_CFGR_PLLSRC_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+
+#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source;
+ Old PREDIV1 bit definition, maintained for legacy purpose */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI PREDIV clock selected as PLL entry clock source
+ (This bit and configuration is only available for STM32F072 devices)*/
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE PREDIV clock selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48 PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+/*!< Old bit definition maintained for legacy purposes */
+#define RCC_CFGR_PLLSRC_HSI_Div2 RCC_CFGR_PLLSRC_HSI_DIV2
+
+/* PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/* Old PLLMUL configuration bit definition maintained for legacy purposes */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMUL /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 RCC_CFGR_PLLMUL_0 /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 RCC_CFGR_PLLMUL_1 /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 RCC_CFGR_PLLMUL_2 /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 RCC_CFGR_PLLMUL_3 /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMULL2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMUL10 /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
+
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+/* MCO configuration */
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (these bits are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)*/
+#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)*/
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) */
+
+/******************* Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/* Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
+#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
+#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
+#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
+#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/* RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00020000) /*!< GPIOE clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00100000) /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/* PREDIV1 configuration */
+#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register ******************/
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
+#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
+#define RCC_CFGR3_ADCSW ((uint32_t)0x00000100) /*!< ADCSW bits */
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+/******************* Bit definition for RCC_CR2 register ********************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
+#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
+#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BKP ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_CR_BCK RTC_CR_BKP
+#define RTC_CR_CALSEL RTC_CR_COSEL
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0003FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
+
+/******************** Bits definition for RTC_CALR register ******************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_PC15MODE ((uint32_t)0x00800000)
+#define RTC_TAFCR_PC15VALUE ((uint32_t)0x00400000)
+#define RTC_TAFCR_PC14MODE ((uint32_t)0x00200000)
+#define RTC_TAFCR_PC14VALUE ((uint32_t)0x00100000)
+#define RTC_TAFCR_PC13MODE ((uint32_t)0x00080000)
+#define RTC_TAFCR_PC13VALUE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/* Old bit definition maintained for legacy purpose */
+#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */
+#define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)*/
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for STM32F072) */
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for STM32F072) */
+#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
+#define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for STM32F072) */
+#define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for STM32F072) */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF
+/******************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM14_OR_TI1_RMP ((uint16_t)0x0003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_adc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,450 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_adc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_ADC_H
+#define __STM32F0XX_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief ADC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
+ This parameter can be a value of @ref ADC_Resolution */
+
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
+ trigger of a regular group. This parameter can be a value
+ of @ref ADC_external_trigger_edge_conversion */
+
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
+
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned
+ in the sequence.
+ This parameter can be a value of @ref ADC_Scan_Direction */
+}ADC_InitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
+
+/** @defgroup ADC_JitterOff
+ * @{
+ */
+/* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */
+#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2
+#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4
+
+#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_ClockMode
+ * @{
+ */
+#define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
+#define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */
+#define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */
+#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\
+ ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\
+ ((CLOCK) == ADC_ClockMode_SynClkDiv4))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Resolution
+ * @{
+ */
+#define ADC_Resolution_12b ((uint32_t)0x00000000)
+#define ADC_Resolution_10b ADC_CFGR1_RES_0
+#define ADC_Resolution_8b ADC_CFGR1_RES_1
+#define ADC_Resolution_6b ADC_CFGR1_RES
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+ ((RESOLUTION) == ADC_Resolution_10b) || \
+ ((RESOLUTION) == ADC_Resolution_8b) || \
+ ((RESOLUTION) == ADC_Resolution_6b))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_edge_conversion
+ * @{
+ */
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0
+#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1
+#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_channels_conversion
+ * @{
+ */
+
+/* TIM1 */
+#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0
+
+/* TIM2 */
+#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1
+
+/* TIM3 */
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))
+
+/* TIM15 */
+#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2
+
+#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
+ ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \
+ ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \
+ ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \
+ ((CONV) == ADC_ExternalTrigConv_T15_TRGO))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ADC_CFGR1_ALIGN
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_Direction
+ * @{
+ */
+
+#define ADC_ScanDirection_Upward ((uint32_t)0x00000000)
+#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR
+
+#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
+ ((DIRECTION) == ADC_ScanDirection_Backward))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_DMA_Mode
+ * @{
+ */
+
+#define ADC_DMAMode_OneShot ((uint32_t)0x00000000)
+#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG
+
+#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \
+ ((MODE) == ADC_DMAMode_Circular))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000)
+#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000)
+#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000)
+#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000)
+#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000)
+#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000)
+#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000)
+#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000)
+#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000)
+#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000)
+#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) /*!< Not available for STM32F031 devices */
+#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000)
+#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000)
+#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000)
+
+
+#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times
+ * @{
+ */
+
+#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000)
+#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001)
+#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002)
+#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003)
+#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004)
+#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005)
+#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006)
+#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \
+ ((TIME) == ADC_SampleTime_7_5Cycles) || \
+ ((TIME) == ADC_SampleTime_13_5Cycles) || \
+ ((TIME) == ADC_SampleTime_28_5Cycles) || \
+ ((TIME) == ADC_SampleTime_41_5Cycles) || \
+ ((TIME) == ADC_SampleTime_55_5Cycles) || \
+ ((TIME) == ADC_SampleTime_71_5Cycles) || \
+ ((TIME) == ADC_SampleTime_239_5Cycles))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+
+#define ADC_Channel_0 ADC_CHSELR_CHSEL0
+#define ADC_Channel_1 ADC_CHSELR_CHSEL1
+#define ADC_Channel_2 ADC_CHSELR_CHSEL2
+#define ADC_Channel_3 ADC_CHSELR_CHSEL3
+#define ADC_Channel_4 ADC_CHSELR_CHSEL4
+#define ADC_Channel_5 ADC_CHSELR_CHSEL5
+#define ADC_Channel_6 ADC_CHSELR_CHSEL6
+#define ADC_Channel_7 ADC_CHSELR_CHSEL7
+#define ADC_Channel_8 ADC_CHSELR_CHSEL8
+#define ADC_Channel_9 ADC_CHSELR_CHSEL9
+#define ADC_Channel_10 ADC_CHSELR_CHSEL10 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_11 ADC_CHSELR_CHSEL11 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_12 ADC_CHSELR_CHSEL12 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_13 ADC_CHSELR_CHSEL13 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_14 ADC_CHSELR_CHSEL14 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_15 ADC_CHSELR_CHSEL15 /*!< Not available for STM32F031 devices */
+#define ADC_Channel_16 ADC_CHSELR_CHSEL16
+#define ADC_Channel_17 ADC_CHSELR_CHSEL17
+#define ADC_Channel_18 ADC_CHSELR_CHSEL18 /*!< Not available for STM32F030 devices */
+
+#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17)
+#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18) /*!< Not available for STM32F030 devices */
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_IT_ADRDY ADC_IER_ADRDYIE
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE
+#define ADC_IT_EOC ADC_IER_EOCIE
+#define ADC_IT_EOSEQ ADC_IER_EOSEQIE
+#define ADC_IT_OVR ADC_IER_OVRIE
+#define ADC_IT_AWD ADC_IER_AWDIE
+
+#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
+ ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \
+ ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD))
+
+#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_ADRDY ADC_ISR_ADRDY
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP
+#define ADC_FLAG_EOC ADC_ISR_EOC
+#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ
+#define ADC_FLAG_OVR ADC_ISR_OVR
+#define ADC_FLAG_AWD ADC_ISR_AWD
+
+#define ADC_FLAG_ADEN ((uint32_t)0x01000001)
+#define ADC_FLAG_ADDIS ((uint32_t)0x01000002)
+#define ADC_FLAG_ADSTART ((uint32_t)0x01000004)
+#define ADC_FLAG_ADSTP ((uint32_t)0x01000010)
+#define ADC_FLAG_ADCAL ((uint32_t)0x81000000)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET))
+
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
+ ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \
+ ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \
+ ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \
+ ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \
+ ((FLAG) == ADC_FLAG_ADCAL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+/* This Function is obsolete and maintained for legacy purpose only.
+ ADC_ClockModeConfig() function should be used instead */
+void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
+
+/* Power saving functions *****************************************************/
+void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
+void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Temperature Sensor , Vrefint and Vbat management function ******************/
+void ADC_TempSensorCmd(FunctionalState NewState);
+void ADC_VrefintCmd(FunctionalState NewState);
+void ADC_VbatCmd(FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
+
+/* Channels Configuration functions *******************************************/
+void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
+void ADC_StopOfConversion(ADC_TypeDef* ADCx);
+void ADC_StartOfConversion(ADC_TypeDef* ADCx);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_ADC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_can.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,643 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_can.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the CAN firmware
+ * library, applicable only for STM32F072 devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_CAN_H
+#define __STM32F0xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+typedef struct
+{
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMsg;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CAN_InitStatus
+ * @{
+ */
+
+#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+
+/* Legacy defines */
+#define CANINITFAILED CAN_InitStatus_Failed
+#define CANINITOK CAN_InitStatus_Success
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode
+ * @{
+ */
+
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+ ((MODE) == CAN_Mode_LoopBack)|| \
+ ((MODE) == CAN_Mode_Silent) || \
+ ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+ * @}
+ */
+
+
+ /**
+ * @defgroup CAN_operating_mode
+ * @{
+ */
+#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+ ((MODE) == CAN_OperatingMode_Normal)|| \
+ ((MODE) == CAN_OperatingMode_Sleep))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_operating_mode_status
+ * @{
+ */
+
+#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+ ((MODE) == CAN_FilterMode_IdList))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+ ((SCALE) == CAN_FilterScale_32bit))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+ ((FIFO) == CAN_FilterFIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx
+ * @{
+ */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+ ((IDTYPE) == CAN_Id_Extended))
+
+/* Legacy defines */
+#define CAN_ID_STD CAN_Id_Standard
+#define CAN_ID_EXT CAN_Id_Extended
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/* Legacy defines */
+#define CAN_RTR_DATA CAN_RTR_Data
+#define CAN_RTR_REMOTE CAN_RTR_Remote
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
+ an empty mailbox */
+/* Legacy defines */
+#define CANTXFAILED CAN_TxStatus_Failed
+#define CANTXOK CAN_TxStatus_Ok
+#define CANTXPENDING CAN_TxStatus_Pending
+#define CAN_NO_MB CAN_TxStatus_NoMailBox
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/* Legacy defines */
+#define CANSLEEPFAILED CAN_Sleep_Failed
+#define CANSLEEPOK CAN_Sleep_Ok
+/**
+ * @}
+ */
+
+/** @defgroup CAN_wake_up_constants
+ * @{
+ */
+#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/* Legacy defines */
+#define CANWAKEUPFAILED CAN_WakeUp_Failed
+#define CANWAKEUPOK CAN_WakeUp_Ok
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Error_Code_constants
+ * @{
+ */
+#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
+#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* CAN Frames Transmission functions ******************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* CAN Frames Reception functions *********************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* CAN Bus Error management functions *****************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_CAN_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_cec.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,300 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_cec.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the CEC firmware
+ * library, applicable only for STM32F051, STM32F042 and STM32F072 devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CEC_H
+#define __STM32F0XX_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CEC Init structure definition
+ */
+typedef struct
+{
+ uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration.
+ This parameter can be a value of @ref CEC_Signal_Free_Time */
+ uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance.
+ This parameter can be a value of @ref CEC_RxTolerance */
+ uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception.
+ This parameter can be a value of @ref CEC_Stop_Reception */
+ uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation.
+ This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
+ uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
+ This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
+ uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation.
+ This parameter can be a value of @ref CEC_BDR_No_Gen */
+ uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option.
+ This parameter can be a value of @ref CEC_SFT_Option */
+
+}CEC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CEC_Signal_Free_Time
+ * @{
+ */
+#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */
+#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */
+#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */
+#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */
+#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */
+#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */
+#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */
+#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */
+
+#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
+ ((TIME) == CEC_SignalFreeTime_1T)|| \
+ ((TIME) == CEC_SignalFreeTime_2T)|| \
+ ((TIME) == CEC_SignalFreeTime_3T)|| \
+ ((TIME) == CEC_SignalFreeTime_4T)|| \
+ ((TIME) == CEC_SignalFreeTime_5T)|| \
+ ((TIME) == CEC_SignalFreeTime_6T)|| \
+ ((TIME) == CEC_SignalFreeTime_7T))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_RxTolerance
+ * @{
+ */
+#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */
+#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */
+
+#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
+ ((TOLERANCE) == CEC_RxTolerance_Extended))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Stop_Reception
+ * @{
+ */
+#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
+#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */
+
+#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
+ ((RECEPTION) == CEC_StopReception_Off))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Bit_Rising_Error_Generation
+ * @{
+ */
+#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
+#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */
+
+#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
+ ((ERROR) == CEC_BitRisingError_On))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Long_Bit_Error_Generation
+ * @{
+ */
+#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */
+#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */
+
+#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
+ ((ERROR) == CEC_LongBitPeriodError_On))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BDR_No_Gen
+ * @{
+ */
+
+#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */
+#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */
+
+#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
+ ((ERROR) == CEC_BRDNoGen_On))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_SFT_Option
+ * @{
+ */
+#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */
+#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */
+
+#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
+ ((OPTION) == CEC_SFTOption_On))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Own_Address
+ * @{
+ */
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Interrupt_Configuration_definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE
+#define CEC_IT_TXERR CEC_IER_TXERRIE
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE
+#define CEC_IT_TXEND CEC_IER_TXENDIE
+#define CEC_IT_TXBR CEC_IER_TXBRIE
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE
+#define CEC_IT_LBPE CEC_IER_LBPEIE
+#define CEC_IT_SBPE CEC_IER_SBPEIE
+#define CEC_IT_BRE CEC_IER_BREIEIE
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE
+#define CEC_IT_RXEND CEC_IER_RXENDIE
+#define CEC_IT_RXBR CEC_IER_RXBRIE
+
+#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
+
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
+ ((IT) == CEC_IT_TXERR)|| \
+ ((IT) == CEC_IT_TXUDR)|| \
+ ((IT) == CEC_IT_TXEND)|| \
+ ((IT) == CEC_IT_TXBR)|| \
+ ((IT) == CEC_IT_ARBLST)|| \
+ ((IT) == CEC_IT_RXACKE)|| \
+ ((IT) == CEC_IT_LBPE)|| \
+ ((IT) == CEC_IT_SBPE)|| \
+ ((IT) == CEC_IT_BRE)|| \
+ ((IT) == CEC_IT_RXOVR)|| \
+ ((IT) == CEC_IT_RXEND)|| \
+ ((IT) == CEC_IT_RXBR))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_ISR_register_flags_definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND CEC_ISR_TXEND
+#define CEC_FLAG_TXBR CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE CEC_ISR_LBPE
+#define CEC_FLAG_SBPE CEC_ISR_SBPE
+#define CEC_FLAG_BRE CEC_ISR_BRE
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND CEC_ISR_RXEND
+#define CEC_FLAG_RXBR CEC_ISR_RXBR
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
+ ((FLAG) == CEC_FLAG_TXERR)|| \
+ ((FLAG) == CEC_FLAG_TXUDR)|| \
+ ((FLAG) == CEC_FLAG_TXEND)|| \
+ ((FLAG) == CEC_FLAG_TXBR)|| \
+ ((FLAG) == CEC_FLAG_ARBLST)|| \
+ ((FLAG) == CEC_FLAG_RXACKE)|| \
+ ((FLAG) == CEC_FLAG_LBPE)|| \
+ ((FLAG) == CEC_FLAG_SBPE)|| \
+ ((FLAG) == CEC_FLAG_BRE)|| \
+ ((FLAG) == CEC_FLAG_RXOVR)|| \
+ ((FLAG) == CEC_FLAG_RXEND)|| \
+ ((FLAG) == CEC_FLAG_RXBR))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the CEC configuration to the default reset state *****/
+void CEC_DeInit(void);
+
+/* CEC_Initialization and Configuration functions *****************************/
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ListenModeCmd(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_OwnAddressClear(void);
+
+/* CEC_Data transfers functions ***********************************************/
+void CEC_SendData(uint8_t Data);
+uint8_t CEC_ReceiveData(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessage(void);
+
+/* CEC_Interrupts and flags management functions ******************************/
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint16_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_CEC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_comp.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,245 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_comp.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the COMP firmware
+ * library, applicable only for STM32F051 and STM32F072 devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_COMP_H
+#define __STM32F0XX_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief COMP Init structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
+ This parameter can be a value of @ref COMP_InvertingInput */
+
+ uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
+ This parameter can be a value of @ref COMP_Output */
+
+ uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
+ This parameter can be a value of @ref COMP_OutputPolarity */
+
+ uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
+ This parameter can be a value of @ref COMP_Hysteresis */
+
+ uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
+ and allows to adjust the speed/consumption.
+ This parameter can be a value of @ref COMP_Mode */
+
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup COMP_Selection
+ * @{
+ */
+
+#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
+#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+ ((PERIPH) == COMP_Selection_COMP2))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_InvertingInput
+ * @{
+ */
+
+#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */
+#define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */
+#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_DAC1) || \
+ ((INPUT) == COMP_InvertingInput_DAC2) || \
+ ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_IO))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Output
+ * @{
+ */
+
+#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
+#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */
+
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
+ ((OUTPUT) == COMP_Output_TIM1BKIN) || \
+ ((OUTPUT) == COMP_Output_TIM1IC1) || \
+ ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM2IC4) || \
+ ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_Output_TIM3IC1) || \
+ ((OUTPUT) == COMP_Output_TIM3OCREFCLR))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputPolarity
+ * @{
+ */
+#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
+#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
+ ((POL) == COMP_OutputPol_Inverted))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Hysteresis
+ * @{
+ */
+/* Please refer to the electrical characteristics in the device datasheet for
+ the hysteresis level */
+#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
+#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
+#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
+#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
+ ((HYSTERESIS) == COMP_Hysteresis_Low) || \
+ ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
+ ((HYSTERESIS) == COMP_Hysteresis_High))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Mode
+ * @{
+ */
+/* Please refer to the electrical characteristics in the device datasheet for
+ the power consumption values */
+#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
+#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
+#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */
+#define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
+ ((MODE) == COMP_Mode_LowPower) || \
+ ((MODE) == COMP_Mode_MediumSpeed) || \
+ ((MODE) == COMP_Mode_HighSpeed))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputLevel
+ * @{
+ */
+/* When output polarity is not inverted, comparator output is high when
+ the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputLevel_High COMP_CSR_COMP1OUT
+/* When output polarity is not inverted, comparator output is low when
+ the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+void COMP_SwitchCmd(FunctionalState NewState);
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_COMP_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_F030R8/stm32f0xx_conf.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h + * @author MCD Application Team + * @version V1.3.1 + * @date 17-January-2014 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CONF_H +#define __STM32F0XX_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Comment the line below to disable peripheral header file inclusion */ +#include "stm32f0xx_adc.h" +#include "stm32f0xx_can.h" +#include "stm32f0xx_cec.h" +#include "stm32f0xx_crc.h" +#include "stm32f0xx_crs.h" +#include "stm32f0xx_comp.h" +#include "stm32f0xx_dac.h" +#include "stm32f0xx_dbgmcu.h" +#include "stm32f0xx_dma.h" +#include "stm32f0xx_exti.h" +#include "stm32f0xx_flash.h" +#include "stm32f0xx_gpio.h" +#include "stm32f0xx_syscfg.h" +#include "stm32f0xx_i2c.h" +#include "stm32f0xx_iwdg.h" +#include "stm32f0xx_pwr.h" +#include "stm32f0xx_rcc.h" +#include "stm32f0xx_rtc.h" +#include "stm32f0xx_spi.h" +#include "stm32f0xx_tim.h" +#include "stm32f0xx_usart.h" +#include "stm32f0xx_wwdg.h" +#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F0XX_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_crc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_crc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the CRC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CRC_H
+#define __STM32F0XX_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_ReverseInputData
+ * @{
+ */
+#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
+#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
+#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
+#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
+
+#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
+ ((DATA) == CRC_ReverseInputData_8bits) || \
+ ((DATA) == CRC_ReverseInputData_16bits) || \
+ ((DATA) == CRC_ReverseInputData_32bits))
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_PolynomialSize
+ * @brief Only applicable for STM32F042 and STM32F072 devices
+ * @{
+ */
+#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
+#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
+#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
+#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
+
+#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
+ ((SIZE) == CRC_PolSize_8) || \
+ ((SIZE) == CRC_PolSize_16) || \
+ ((SIZE) == CRC_PolSize_32))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRC computation unit **********************************/
+void CRC_DeInit(void);
+void CRC_ResetDR(void);
+void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
+void CRC_ReverseOutputDataCmd(FunctionalState NewState);
+void CRC_SetInitRegister(uint32_t CRC_InitValue);
+void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */
+
+/* CRC computation ************************************************************/
+uint32_t CRC_CalcCRC(uint32_t CRC_Data);
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+
+/* Independent register (IDR) access (write/read) *****************************/
+void CRC_SetIDRegister(uint8_t CRC_IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_CRC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_crs.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,183 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_crs.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the CRS firmware
+ * library, applicable only for STM32F042 and STM32F072 devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CRS_H
+#define __STM32F0XX_CRS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRS_Interrupt_Sources
+ * @{
+ */
+#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
+#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
+#define CRS_IT_ERR CRS_ISR_ERRF /*!< error */
+#define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
+#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
+#define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
+#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
+
+#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
+ ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC))
+
+#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
+ ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \
+ ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \
+ ((IT) == CRS_IT_SYNCMISS))
+
+#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00)
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_Flags
+ * @{
+ */
+#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
+#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
+#define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */
+#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
+#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
+#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
+#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
+
+#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \
+ ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \
+ ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \
+ ((FLAG) == CRS_FLAG_SYNCMISS))
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_Synchro_Source
+ * @{
+ */
+#define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
+#define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
+#define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */
+
+#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \
+ ((SOURCE) == CRS_SYNCSource_LSE) ||\
+ ((SOURCE) == CRS_SYNCSource_USB))
+/**
+ * @}
+ */
+
+/** @defgroup CRS_SynchroDivider
+ * @{
+ */
+#define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */
+#define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
+#define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
+#define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
+#define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
+
+#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\
+ ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \
+ ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
+ ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
+/**
+ * @}
+ */
+
+/** @defgroup CRS_SynchroPolarity
+ * @{
+ */
+#define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */
+#define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
+
+#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \
+ ((POLARITY) == CRS_SYNCPolarity_Falling))
+/**
+ * @}
+ */
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRS **********************************/
+void CRS_DeInit(void);
+void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue);
+void CRS_FrequencyErrorCounterCmd(FunctionalState NewState);
+void CRS_AutomaticCalibrationCmd(FunctionalState NewState);
+void CRS_SoftwareSynchronizationGenerate(void);
+void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue);
+void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue);
+void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler);
+void CRS_SynchronizationSourceConfig(uint32_t CRS_Source);
+void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity);
+uint32_t CRS_GetReloadValue(void);
+uint32_t CRS_GetHSI48CalibrationValue(void);
+uint32_t CRS_GetFrequencyErrorValue(void);
+uint32_t CRS_GetFrequencyErrorDirection(void);
+
+/* Interrupts and flags management functions **********************************/
+void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState);
+FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG);
+void CRS_ClearFlag(uint32_t CRS_FLAG);
+ITStatus CRS_GetITStatus(uint32_t CRS_IT);
+void CRS_ClearITPendingBit(uint32_t CRS_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_CRS_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_dac.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,312 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_dac.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library, applicable only for STM32F051 and STM32F072 devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_DAC_H
+#define __STM32F0XX_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation
+ This parameter is only applicable for STM32F072 devices */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude
+ This parameter is only applicable for STM32F072 devices */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DAC_Trigger
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel1,
+ applicable only for STM32F072 devices */
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel1 */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channels */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channels */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @brief This parameters are only applicable for STM32F072 devices.
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @brief These parameters are only applicable for STM32F072 devices.
+ * @{
+ */
+
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_OutputBuffer
+ * @{
+ */
+
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable DAC_CR_BOFF1
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+ ((STATE) == DAC_OutputBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010) /*!< Only applicable for STM32F072 devices */
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @brief These parameters are only applicable for STM32F072 devices.
+ * @{
+ */
+
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_interrupts_definition
+ * @{
+ */
+
+#define DAC_IT_DMAUDR DAC_SR_DMAUDR1
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+
+#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1
+
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DAC configuration to the default reset state *****/
+void DAC_DeInit(void);
+
+/* DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); /*!< Only applicable for STM32F072 devices */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); /*!< Only applicable for STM32F072 devices */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_DAC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_dbgmcu.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,107 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_dbgmcu.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the DBGMCU firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_DBGMCU_H
+#define __STM32F0XX_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBGMCU
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBGMCU_STOP DBGMCU_CR_DBG_STOP
+#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */
+#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
+#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
+#define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */
+#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
+#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
+#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
+#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
+#define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP
+#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
+#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
+#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Device and Revision ID management functions ********************************/
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+/* Peripherals Configuration functions ****************************************/
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_DBGMCU_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_dma.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,377 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_dma.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_DMA_H
+#define __STM32F0XX_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Init structures definition
+ */
+typedef struct
+{
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define DMA_DIR_PeripheralDST DMA_CCR_DIR
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
+ ((DIR) == DMA_DIR_PeripheralDST))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define DMA_PeripheralInc_Enable DMA_CCR_PINC
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
+ ((STATE) == DMA_PeripheralInc_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define DMA_MemoryInc_Enable DMA_CCR_MINC
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
+ ((STATE) == DMA_MemoryInc_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
+#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
+#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define DMA_Mode_Circular DMA_CCR_CIRC
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh DMA_CCR_PL
+#define DMA_Priority_High DMA_CCR_PL_1
+#define DMA_Priority_Medium DMA_CCR_PL_0
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define DMA_M2M_Enable DMA_CCR_MEM2MEM
+
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC DMA_CCR_TCIE
+#define DMA_IT_HT DMA_CCR_HTIE
+#define DMA_IT_TE DMA_CCR_TEIE
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1 DMA_ISR_GIF1
+#define DMA1_IT_TC1 DMA_ISR_TCIF1
+#define DMA1_IT_HT1 DMA_ISR_HTIF1
+#define DMA1_IT_TE1 DMA_ISR_TEIF1
+#define DMA1_IT_GL2 DMA_ISR_GIF2
+#define DMA1_IT_TC2 DMA_ISR_TCIF2
+#define DMA1_IT_HT2 DMA_ISR_HTIF2
+#define DMA1_IT_TE2 DMA_ISR_TEIF2
+#define DMA1_IT_GL3 DMA_ISR_GIF3
+#define DMA1_IT_TC3 DMA_ISR_TCIF3
+#define DMA1_IT_HT3 DMA_ISR_HTIF3
+#define DMA1_IT_TE3 DMA_ISR_TEIF3
+#define DMA1_IT_GL4 DMA_ISR_GIF4
+#define DMA1_IT_TC4 DMA_ISR_TCIF4
+#define DMA1_IT_HT4 DMA_ISR_HTIF4
+#define DMA1_IT_TE4 DMA_ISR_TEIF4
+#define DMA1_IT_GL5 DMA_ISR_GIF5
+#define DMA1_IT_TC5 DMA_ISR_TCIF5
+#define DMA1_IT_HT5 DMA_ISR_HTIF5
+#define DMA1_IT_TE5 DMA_ISR_TEIF5
+#define DMA1_IT_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_IT_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_IT_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_IT_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_IT_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */
+#define DMA1_IT_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */
+#define DMA1_IT_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */
+#define DMA1_IT_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */
+
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+#define DMA1_FLAG_GL1 DMA_ISR_GIF1
+#define DMA1_FLAG_TC1 DMA_ISR_TCIF1
+#define DMA1_FLAG_HT1 DMA_ISR_HTIF1
+#define DMA1_FLAG_TE1 DMA_ISR_TEIF1
+#define DMA1_FLAG_GL2 DMA_ISR_GIF2
+#define DMA1_FLAG_TC2 DMA_ISR_TCIF2
+#define DMA1_FLAG_HT2 DMA_ISR_HTIF2
+#define DMA1_FLAG_TE2 DMA_ISR_TEIF2
+#define DMA1_FLAG_GL3 DMA_ISR_GIF3
+#define DMA1_FLAG_TC3 DMA_ISR_TCIF3
+#define DMA1_FLAG_HT3 DMA_ISR_HTIF3
+#define DMA1_FLAG_TE3 DMA_ISR_TEIF3
+#define DMA1_FLAG_GL4 DMA_ISR_GIF4
+#define DMA1_FLAG_TC4 DMA_ISR_TCIF4
+#define DMA1_FLAG_HT4 DMA_ISR_HTIF4
+#define DMA1_FLAG_TE4 DMA_ISR_TEIF4
+#define DMA1_FLAG_GL5 DMA_ISR_GIF5
+#define DMA1_FLAG_TC5 DMA_ISR_TCIF5
+#define DMA1_FLAG_HT5 DMA_ISR_HTIF5
+#define DMA1_FLAG_TE5 DMA_ISR_TEIF5
+#define DMA1_FLAG_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_FLAG_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_FLAG_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_FLAG_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */
+#define DMA1_FLAG_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */
+#define DMA1_FLAG_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */
+#define DMA1_FLAG_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */
+#define DMA1_FLAG_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DMA configuration to the default reset state ******/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+
+/* Data Counter functions******************************************************/
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+void DMA_ClearFlag(uint32_t DMA_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_DMA_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_exti.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,216 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_exti.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the EXTI
+ * firmware library
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_EXTI_H
+#define __STM32F0XX_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
+ Connected to the PVD Output,
+ not applicable for STM32F030 devices */
+#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17
+ Connected to the RTC Alarm
+ event */
+#define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18
+ Connected to the USB
+ event, only applicable for
+ STM32F072 devices */
+#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19
+ Connected to the RTC Tamper
+ and Time Stamp events */
+#define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20
+ Connected to the RTC wakeup
+ event, only applicable for
+ STM32F072 devices */
+#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21
+ Connected to the Comparator 1
+ event, only applicable for STM32F051
+ ans STM32F072 devices */
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22
+ Connected to the Comparator 2
+ event, only applicable for STM32F051
+ and STM32F072 devices */
+#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23
+ Connected to the I2C1 wakeup
+ event, not applicable for STM32F030 devices */
+#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25
+ Connected to the USART1 wakeup
+ event, not applicable for STM32F030 devices */
+#define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26
+ Connected to the USART2 wakeup
+ event, applicable only for
+ STM32F072 devices */
+#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27
+ Connected to the CEC wakeup
+ event, applicable only for STM32F051
+ and STM32F072 devices */
+#define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31
+ Connected to the VDD USB monitor
+ event, applicable only for
+ STM32F072 devices */
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+ ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \
+ ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \
+ ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_EXTI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_flash.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,430 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_flash.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_FLASH_H
+#define __STM32F0XX_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief FLASH Status
+ */
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_WRP,
+ FLASH_ERROR_PROGRAM,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Latency
+ * @{
+ */
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
+
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Address
+ * @{
+ */
+#ifndef STM32F072
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
+#else
+ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
+#endif /* STM32F072 */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_DATA_ADDRESS
+ * @{
+ */
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_Write_Protection
+ * @{
+ */
+
+#ifndef STM32F072
+
+#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
+#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
+#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
+#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
+#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
+#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
+#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
+#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
+#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
+#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
+#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
+#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
+#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
+#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
+#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
+#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
+
+#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#else
+
+#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+#define OB_WRP_Pages62to63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */
+
+#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#endif /* STM32F072 */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_Read_Protection
+ * @{
+ */
+
+/**
+ * @brief FLASH_Read Protection Level
+ */
+#define OB_RDP_Level_0 ((uint8_t)0xAA)
+#define OB_RDP_Level_1 ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+ ((LEVEL) == OB_RDP_Level_1))/*||\
+ ((LEVEL) == OB_RDP_Level_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_BOOT1
+ * @{
+ */
+
+#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_BOOT0
+ * @{
+ */
+
+#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */
+#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */
+#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_BOOT0SW
+ * @{
+ */
+
+#define OB_BOOT0_SW ((uint8_t)0x00) /*!< BOOT0 pin disabled */
+#define OB_BOOT0_HW ((uint8_t)0x80) /*!< BOOT0 pin bonded with GPIO */
+#define IS_OB_BOOT0SW(BOOT0) (((BOOT0) == OB_BOOT0_SW) || ((BOOT0) == OB_BOOT0_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
+ * @{
+ */
+
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
+ * @{
+ */
+
+#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
+#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Timeout_definition
+ * @{
+ */
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Legacy
+ * @{
+ */
+#define FLASH_WRProt_Pages0to3 OB_WRP_Pages0to3
+#define FLASH_WRProt_Pages4to7 OB_WRP_Pages4to7
+#define FLASH_WRProt_Pages8to11 OB_WRP_Pages8to11
+#define FLASH_WRProt_Pages12to15 OB_WRP_Pages12to15
+#define FLASH_WRProt_Pages16to19 OB_WRP_Pages16to19
+#define FLASH_WRProt_Pages20to23 OB_WRP_Pages20to23
+#define FLASH_WRProt_Pages24to27 OB_WRP_Pages24to27
+#define FLASH_WRProt_Pages28to31 OB_WRP_Pages28to31
+#define FLASH_WRProt_Pages32to35 OB_WRP_Pages32to35
+#define FLASH_WRProt_Pages36to39 OB_WRP_Pages36to39
+#define FLASH_WRProt_Pages40to43 OB_WRP_Pages40to21
+#define FLASH_WRProt_Pages44to47 OB_WRP_Pages44to23
+#define FLASH_WRProt_Pages48to51 OB_WRP_Pages48to51
+#define FLASH_WRProt_Pages52to55 OB_WRP_Pages52to55
+#define FLASH_WRProt_Pages56to59 OB_WRP_Pages56to59
+#define FLASH_WRProt_Pages60to63 OB_WRP_Pages60to63
+
+
+#define FLASH_WRProt_AllPages OB_WRP_AllPages
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/**
+ * @brief FLASH memory functions that can be executed from FLASH.
+ */
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+
+/* FLASH Memory Programming functions *****************************************/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+
+/* FLASH Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_Erase(void);
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0);
+FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW);
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+FlagStatus FLASH_OB_GetRDP(void);
+
+/* FLASH Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/** @defgroup FLASH_Legacy
+ * @{
+ */
+#define FLASH_EraseOptionBytes FLASH_OB_Erase
+#define FLASH_EnableWriteProtection FLASH_OB_EnableWRP
+#define FLASH_UserOptionByteConfig FLASH_OB_UserConfig
+#define FLASH_ProgramOptionByteData FLASH_OB_ProgramData
+#define FLASH_GetUserOptionByte FLASH_OB_GetUser
+#define FLASH_GetWriteProtectionOptionByte FLASH_OB_GetWRP
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_FLASH_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_gpio.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,358 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_gpio.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_GPIO_H
+#define __STM32F0XX_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF))
+
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB))
+
+/** @defgroup Configuration_Mode_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+ * @}
+ */
+
+/** @defgroup Output_type_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_OType_PP = 0x00,
+ GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+ * @}
+ */
+
+/** @defgroup Output_Maximum_frequency_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */
+ GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */
+ GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: High 50 MHz */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+ ((SPEED) == GPIO_Speed_Level_3))
+/**
+ * @}
+ */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_PuPd_NOPULL = 0x00,
+ GPIO_PuPd_UP = 0x01,
+ GPIO_PuPd_DOWN = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+ ((PUPD) == GPIO_PuPd_DOWN))
+/**
+ * @}
+ */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+ * @{
+ */
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIOOType_TypeDef */
+
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Alternate_function_selection_define
+ * @{
+ */
+
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
+ MCO, SWDAT, SWCLK, TIM14, BOOT,
+ USART1, CEC, IR_OUT, SPI2, TS, TIM3,
+ USART4, CAN, TIM3, USART2, USART3,
+ CRS, TIM16, TIM1 */
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR,
+ EVENTOUT, I2C1, I2C2, TIM15, SPI2,
+ USART3, TS, SPI1 */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17,
+ USB */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN,
+ I2C1 */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2,
+ MCO, I2C1, USB */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
+ ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
+ ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
+ ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Speed_Legacy
+ * @{
+ */
+
+#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */
+#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< I/O output speed: High 50 MHz */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_GPIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_i2c.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,478 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_i2c.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_I2C_H
+#define __STM32F0XX_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
+ This parameter must be set by referring to I2C_Timing_Config_Tool*/
+
+ uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref I2C_Analog_Filter*/
+
+ uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between 0x00 and 0x0F*/
+
+ uint32_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode*/
+
+ uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter can be a 7-bit or 10-bit address*/
+
+ uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement*/
+
+ uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address*/
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+
+#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1)
+
+/** @defgroup I2C_Analog_Filter
+ * @{
+ */
+
+#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
+#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
+ ((FILTER) == I2C_AnalogFilter_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Digital_Filter
+ * @{
+ */
+
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint32_t)0x00000000)
+#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
+#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
+
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_Ack_Enable ((uint32_t)0x00000000)
+#define I2C_Ack_Disable I2C_CR2_NACK
+
+#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
+ ((ACK) == I2C_Ack_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
+#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_Direction_Transmitter ((uint16_t)0x0000)
+#define I2C_Direction_Receiver ((uint16_t)0x0400)
+
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_DMA_transfer_requests
+ * @{
+ */
+
+#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
+#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
+
+#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_slave_address
+ * @{
+ */
+
+#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_own_address2
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address2_mask
+ * @{
+ */
+
+#define I2C_OA2_NoMask ((uint8_t)0x00)
+#define I2C_OA2_Mask01 ((uint8_t)0x01)
+#define I2C_OA2_Mask02 ((uint8_t)0x02)
+#define I2C_OA2_Mask03 ((uint8_t)0x03)
+#define I2C_OA2_Mask04 ((uint8_t)0x04)
+#define I2C_OA2_Mask05 ((uint8_t)0x05)
+#define I2C_OA2_Mask06 ((uint8_t)0x06)
+#define I2C_OA2_Mask07 ((uint8_t)0x07)
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
+ ((MASK) == I2C_OA2_Mask01) || \
+ ((MASK) == I2C_OA2_Mask02) || \
+ ((MASK) == I2C_OA2_Mask03) || \
+ ((MASK) == I2C_OA2_Mask04) || \
+ ((MASK) == I2C_OA2_Mask05) || \
+ ((MASK) == I2C_OA2_Mask06) || \
+ ((MASK) == I2C_OA2_Mask07))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_timeout
+ * @{
+ */
+
+#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_registers
+ * @{
+ */
+
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_TIMINGR ((uint8_t)0x10)
+#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
+#define I2C_Register_ISR ((uint8_t)0x18)
+#define I2C_Register_ICR ((uint8_t)0x1C)
+#define I2C_Register_PECR ((uint8_t)0x20)
+#define I2C_Register_RXDR ((uint8_t)0x24)
+#define I2C_Register_TXDR ((uint8_t)0x28)
+
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_TIMINGR) || \
+ ((REGISTER) == I2C_Register_TIMEOUTR) || \
+ ((REGISTER) == I2C_Register_ISR) || \
+ ((REGISTER) == I2C_Register_ICR) || \
+ ((REGISTER) == I2C_Register_PECR) || \
+ ((REGISTER) == I2C_Register_RXDR) || \
+ ((REGISTER) == I2C_Register_TXDR))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_ERRI I2C_CR1_ERRIE
+#define I2C_IT_TCI I2C_CR1_TCIE
+#define I2C_IT_STOPI I2C_CR1_STOPIE
+#define I2C_IT_NACKI I2C_CR1_NACKIE
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE
+#define I2C_IT_RXI I2C_CR1_RXIE
+#define I2C_IT_TXI I2C_CR1_TXIE
+
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_NACKF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
+ ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
+ ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
+ ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
+ ((FLAG) == I2C_FLAG_BUSY))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_TXIS I2C_ISR_TXIS
+#define I2C_IT_RXNE I2C_ISR_RXNE
+#define I2C_IT_ADDR I2C_ISR_ADDR
+#define I2C_IT_NACKF I2C_ISR_NACKF
+#define I2C_IT_STOPF I2C_ISR_STOPF
+#define I2C_IT_TC I2C_ISR_TC
+#define I2C_IT_TCR I2C_ISR_TCR
+#define I2C_IT_BERR I2C_ISR_BERR
+#define I2C_IT_ARLO I2C_ISR_ARLO
+#define I2C_IT_OVR I2C_ISR_OVR
+#define I2C_IT_PECERR I2C_ISR_PECERR
+#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_IT_ALERT I2C_ISR_ALERT
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
+ ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
+ ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
+ ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_ALERT))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ReloadEndMode_definition
+ * @{
+ */
+
+#define I2C_Reload_Mode I2C_CR2_RELOAD
+#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
+#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
+
+
+#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
+ ((MODE) == I2C_AutoEnd_Mode) || \
+ ((MODE) == I2C_SoftEnd_Mode))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_StartStopMode_definition
+ * @{
+ */
+
+#define I2C_No_StartStop ((uint32_t)0x00000000)
+#define I2C_Generate_Stop I2C_CR2_STOP
+#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_Generate_Start_Write I2C_CR2_START
+
+
+#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
+ ((MODE) == I2C_Generate_Start_Read) || \
+ ((MODE) == I2C_Generate_Start_Write) || \
+ ((MODE) == I2C_No_StartStop))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+/* Initialization and Configuration functions *********************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /*!< not applicable for STM32F030 devices */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Communications handling functions ******************************************/
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
+
+/* SMBUS management functions ************************************************/
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* I2C registers management functions *****************************************/
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
+/* Data transfers management functions ****************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_I2C_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_iwdg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,140 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_iwdg.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_IWDG_H
+#define __STM32F0XX_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_FLAG_PVU IWDG_SR_PVU
+#define IWDG_FLAG_RVU IWDG_SR_RVU
+#define IWDG_FLAG_WVU IWDG_SR_WVU
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
+ ((FLAG) == IWDG_FLAG_WVU))
+
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_SetWindowValue(uint16_t WindowValue);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_IWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_misc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,143 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_misc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_MISC_H
+#define __STM32F0XX_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete STM32 Devices IRQ Channels list,
+ please refer to stm32f0xx.h file) */
+
+ uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 3. */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ *
+@verbatim
+
+@endverbatim
+*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup MISC_System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Preemption_Priority_Group
+ * @{
+ */
+#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04)
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_pwr.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,197 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_pwr.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the PWR firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_PWR_H
+#define __STM32F0XX_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level
+ * @brief This parameters are only applicable for STM32F051 and STM32F072 devices
+ * @{
+ */
+
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pins
+ * @{
+ */
+
+#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
+#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
+#define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */
+#define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \
+ ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \
+ ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \
+ ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8))
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
+ * @{
+ */
+
+#define PWR_Regulator_ON ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+ ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry
+ * @{
+ */
+
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)
+#define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\
+ ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */
+void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */
+
+/* WakeUp pins configuration functions ****************************************/
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_PWR_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_rcc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,608 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_rcc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the RCC
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_RCC_H
+#define __STM32F0XX_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+ uint32_t SYSCLK_Frequency;
+ uint32_t HCLK_Frequency;
+ uint32_t PCLK_Frequency;
+ uint32_t ADCCLK_Frequency;
+ uint32_t CECCLK_Frequency;
+ uint32_t I2C1CLK_Frequency;
+ uint32_t USART1CLK_Frequency;
+ uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 devices */
+ uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCC_HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint8_t)0x00)
+#define RCC_HSE_ON ((uint8_t)0x01)
+#define RCC_HSE_Bypass ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
+#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */
+#define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */
+#define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */
+#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */
+
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_HSI48) || \
+ ((SOURCE) == RCC_PLLSource_HSI) || \
+ ((SOURCE) == RCC_PLLSource_HSE) || \
+ ((SOURCE) == RCC_PLLSource_PREDIV1))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Multiplication_Factor
+ * @{
+ */
+
+#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
+#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
+#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
+#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
+#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
+#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
+#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
+#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
+#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
+#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
+#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
+#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
+#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
+#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
+#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PREDIV1_division_factor
+ * @{
+ */
+#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
+#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
+#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
+#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
+#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
+#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
+#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
+#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
+#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
+#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
+#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
+#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
+#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
+#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
+#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
+#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
+
+#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
+#define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */
+
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSI48) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB_Clock_Source
+ * @{
+ */
+
+#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1
+#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2
+#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4
+#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8
+#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_ADC_clock_source
+ * @{
+ */
+/* These defines are obsolete and kept for legacy purpose only.
+Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */
+#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000)
+#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000)
+#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000)
+
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
+ ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_CEC_clock_source
+ * @{
+ */
+
+#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)
+#define RCC_CECCLK_LSE RCC_CFGR3_CECSW
+
+#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2C_clock_source
+ * @{
+ */
+
+#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
+#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
+
+#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USB_clock_source
+ * @brief Applicable only for STM32F072 devices
+ * @{
+ */
+
+#define RCC_USBCLK_HSI48 ((uint32_t)0x00000000)
+#define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW
+
+#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USART_clock_source
+ * @{
+ */
+
+#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
+#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
+#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
+#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
+
+#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 devices */
+#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 devices */
+#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 devices */
+#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 devices */
+
+#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \
+ ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART1CLK_LSE) || \
+ ((USARTCLK) == RCC_USART1CLK_HSI) || \
+ ((USARTCLK) == RCC_USART2CLK_PCLK) || \
+ ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
+ ((USARTCLK) == RCC_USART2CLK_LSE) || \
+ ((USARTCLK) == RCC_USART2CLK_HSI))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt_Source
+ * @{
+ */
+
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_HSI14RDY ((uint8_t)0x20)
+#define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
+ ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY))
+
+#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration
+ * @{
+ */
+
+#define RCC_LSE_OFF ((uint32_t)0x00000000)
+#define RCC_LSE_ON RCC_BDCR_LSEON
+#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source
+ * @{
+ */
+
+#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
+#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
+#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Drive_Configuration
+ * @{
+ */
+
+#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
+#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
+#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
+#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
+ ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripherals
+ * @{
+ */
+
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 devices */
+#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
+#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
+#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFAA) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFFF) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripherals
+ * @{
+ */
+
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
+#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
+#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
+#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
+#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
+#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripherals
+ * @{
+ */
+
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051 and STM32F072 devices */
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN /*!< Only applicable for STM32F072 devices */
+#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN /*!< Only applicable for STM32F072 devices */
+#define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN /*!< Only applicable for STM32F072 devices */
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN /*!< Only applicable for STM32F072 and STM32F042 devices */
+#define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN /*!< Only applicable for STM32F072 and STM32F042 devices */
+#define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN /*!< Only applicable for STM32F072 and STM32F042 devices*/
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN /*!< Only applicable for STM32F051 and STM32F072 devices */
+#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN /*!< Only applicable for STM32F051, STM32F042 and STM32F072 devices */
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8511B6CC) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Clock_Source
+ * @{
+ */
+
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)
+#define RCC_MCOSource_HSI14 ((uint8_t)0x01)
+#define RCC_MCOSource_LSI ((uint8_t)0x02)
+#define RCC_MCOSource_LSE ((uint8_t)0x03)
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
+#define RCC_MCOSource_HSI ((uint8_t)0x05)
+#define RCC_MCOSource_HSE ((uint8_t)0x06)
+#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
+#define RCC_MCOSource_HSI48 ((uint8_t)0x08) /*!< Only applicable for STM32F072 devices */
+#define RCC_MCOSource_PLLCLK ((uint8_t)0x87)
+
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \
+ ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \
+ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \
+ ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOPrescaler
+ * @{
+ */
+#if !defined (STM32F051)
+#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
+#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
+#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
+#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
+#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
+#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
+#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
+#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
+
+#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
+ ((PRESCALER) == RCC_MCOPrescaler_2) || \
+ ((PRESCALER) == RCC_MCOPrescaler_4) || \
+ ((PRESCALER) == RCC_MCOPrescaler_8) || \
+ ((PRESCALER) == RCC_MCOPrescaler_16) || \
+ ((PRESCALER) == RCC_MCOPrescaler_32) || \
+ ((PRESCALER) == RCC_MCOPrescaler_64) || \
+ ((PRESCALER) == RCC_MCOPrescaler_128))
+#endif /* STM32F051 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
+#define RCC_FLAG_HSERDY ((uint8_t)0x11)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
+#define RCC_FLAG_LSERDY ((uint8_t)0x21)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
+#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57)
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
+#define RCC_FLAG_HSI14RDY ((uint8_t)0x61)
+#define RCC_FLAG_HSI48RDY ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \
+ ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \
+ ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \
+ ((FLAG) == RCC_FLAG_V18PWRRSTF))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);
+void RCC_HSI14Cmd(FunctionalState NewState);
+void RCC_HSI14ADCRequestCmd(FunctionalState NewState);
+void RCC_LSEConfig(uint32_t RCC_LSE);
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
+uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+#ifdef STM32F051
+void RCC_MCOConfig(uint8_t RCC_MCOSource);
+#else
+void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
+#endif /* STM32F051 */
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLKConfig(uint32_t RCC_HCLK);
+void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete.
+ For proper ADC clock selection, refer to
+ ADC_ClockModeConfig() in the ADC driver */
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_RCC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_rtc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,807 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_rtc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the RTC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_RTC_H
+#define __STM32F0XX_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be set to a value lower than 0x7F */
+
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be set to a value lower than 0x1FFF */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be set to a value in the 0-12 range
+ if the RTC_HourFormat_12 is selected or 0-23 range if
+ the RTC_HourFormat_24 is selected. */
+
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t RTC_Month; /*!< Specifies the RTC Date Month.
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.
+ This parameter must be set to a value in the 1-31 range. */
+
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
+ This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ This parameter must be set to a value in the 1-31 range
+ if the Alarm Date is selected.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions
+ if the Alarm WeekDay is selected. */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
+ ((FORMAT) == RTC_HourFormat_24))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_H12_AM ((uint8_t)0x00)
+#define RTC_H12_PM ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions
+ * @{
+ */
+#define RTC_Month_January ((uint8_t)0x01)
+#define RTC_Month_February ((uint8_t)0x02)
+#define RTC_Month_March ((uint8_t)0x03)
+#define RTC_Month_April ((uint8_t)0x04)
+#define RTC_Month_May ((uint8_t)0x05)
+#define RTC_Month_June ((uint8_t)0x06)
+#define RTC_Month_July ((uint8_t)0x07)
+#define RTC_Month_August ((uint8_t)0x08)
+#define RTC_Month_September ((uint8_t)0x09)
+#define RTC_Month_October ((uint8_t)0x10)
+#define RTC_Month_November ((uint8_t)0x11)
+#define RTC_Month_December ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_Weekday_Monday ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday ((uint8_t)0x03)
+#define RTC_Weekday_Thursday ((uint8_t)0x04)
+#define RTC_Weekday_Friday ((uint8_t)0x05)
+#define RTC_Weekday_Saturday ((uint8_t)0x6)
+#define RTC_Weekday_Sunday ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \
+ ((WEEKDAY) == RTC_Weekday_Friday) || \
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \
+ ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \
+ ((WEEKDAY) == RTC_Weekday_Friday) || \
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \
+ ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_Alarm_A ((uint32_t)0x00000100)
+#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A)
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.
+ * @{
+ */
+#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+ ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Wakeup_Timer_Definitions
+ * @brief These parameters are only available for STM32F072 devices
+ * @{
+ */
+#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+ ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_Output_Disable ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)
+#define RTC_Output_WakeUp ((uint32_t)0x00600000) /*!< available only for STM32F072 devices */
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+ ((OUTPUT) == RTC_Output_AlarmA) || \
+ ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+ ((POL) == RTC_OutputPolarity_Low))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
+#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+ ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+ ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0].
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \
+ ((SAVING) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+ ((OPERATION) == RTC_StoreOperation_Set))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+ ((FILTER) == RTC_TamperFilter_2Sample) || \
+ ((FILTER) == RTC_TamperFilter_4Sample) || \
+ ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
+ input tamper 1 */
+#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
+ input tamper 2 */
+#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
+ input tamper 3, available only
+ for STM32F072 devices */
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+ ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+ ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Backup_Registers_Definitions
+ * @{
+ */
+
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_Format_BIN ((uint32_t)0x000000000)
+#define RTC_Format_BCD ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
+#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Only available for STM32F072 devices */
+#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
+#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
+#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
+#define RTC_FLAG_TSF RTC_ISR_TSF
+#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Only available for STM32F072 devices */
+#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
+#define RTC_FLAG_INITF RTC_ISR_INITF
+#define RTC_FLAG_RSF RTC_ISR_RSF
+#define RTC_FLAG_INITS RTC_ISR_INITS
+#define RTC_FLAG_SHPF RTC_ISR_SHPF
+#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< Only available for STM32F072 devices */
+#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
+
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
+ ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+ ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_IT_TS ((uint32_t)0x00008000)
+#define RTC_IT_WUT ((uint32_t)0x00004000) /* Available only for STM32F072 devices */
+#define RTC_IT_ALRA ((uint32_t)0x00001000)
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /* Available only for STM32F072 devices */
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \
+ ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT) || \
+ ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3))
+
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A) configuration functions **********************************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); /*!< available only for STM32F072 devices */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); /*!< available only for STM32F072 devices */
+uint32_t RTC_GetWakeUpCounter(void); /*!< available only for STM32F072 devices */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /*!< available only for STM32F072 devices */
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Digital Calibration configuration functions ********************************/
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_RTC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_spi.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,588 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_spi.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the SPI
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_SPI_H
+#define __STM32F0XX_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+
+/**
+ * @brief I2S Init structure definition
+ * @note These parameters are not available for STM32F030 devices.
+ */
+
+typedef struct
+{
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref SPI_I2S_Mode */
+
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref SPI_I2S_Standard */
+
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref SPI_I2S_Data_Format */
+
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref SPI_I2S_MCLK_Output */
+
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
+
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2))
+
+#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
+
+/** @defgroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+ ((MODE) == SPI_Direction_1Line_Rx) || \
+ ((MODE) == SPI_Direction_1Line_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+ ((MODE) == SPI_Mode_Slave))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DataSize_4b ((uint16_t)0x0300)
+#define SPI_DataSize_5b ((uint16_t)0x0400)
+#define SPI_DataSize_6b ((uint16_t)0x0500)
+#define SPI_DataSize_7b ((uint16_t)0x0600)
+#define SPI_DataSize_8b ((uint16_t)0x0700)
+#define SPI_DataSize_9b ((uint16_t)0x0800)
+#define SPI_DataSize_10b ((uint16_t)0x0900)
+#define SPI_DataSize_11b ((uint16_t)0x0A00)
+#define SPI_DataSize_12b ((uint16_t)0x0B00)
+#define SPI_DataSize_13b ((uint16_t)0x0C00)
+#define SPI_DataSize_14b ((uint16_t)0x0D00)
+#define SPI_DataSize_15b ((uint16_t)0x0E00)
+#define SPI_DataSize_16b ((uint16_t)0x0F00)
+#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
+ ((SIZE) == SPI_DataSize_5b) || \
+ ((SIZE) == SPI_DataSize_6b) || \
+ ((SIZE) == SPI_DataSize_7b) || \
+ ((SIZE) == SPI_DataSize_8b) || \
+ ((SIZE) == SPI_DataSize_9b) || \
+ ((SIZE) == SPI_DataSize_10b) || \
+ ((SIZE) == SPI_DataSize_11b) || \
+ ((SIZE) == SPI_DataSize_12b) || \
+ ((SIZE) == SPI_DataSize_13b) || \
+ ((SIZE) == SPI_DataSize_14b) || \
+ ((SIZE) == SPI_DataSize_15b) || \
+ ((SIZE) == SPI_DataSize_16b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length
+ * @{
+ */
+
+#define SPI_CRCLength_8b ((uint16_t)0x0000)
+#define SPI_CRCLength_16b SPI_CR1_CRCL
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
+ ((LENGTH) == SPI_CRCLength_16b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High SPI_CR1_CPOL
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+ ((CPOL) == SPI_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge SPI_CR1_CPHA
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+ ((CPHA) == SPI_CPHA_2Edge))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_Soft SPI_CR1_SSM
+#define SPI_NSS_Hard ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+ ((NSS) == SPI_NSS_Hard))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+ ((BIT) == SPI_FirstBit_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Mode
+ * @{
+ */
+
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+ ((MODE) == I2S_Mode_SlaveRx) || \
+ ((MODE) == I2S_Mode_MasterTx)|| \
+ ((MODE) == I2S_Mode_MasterRx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Standard
+ * @{
+ */
+
+#define I2S_Standard_Phillips ((uint16_t)0x0000)
+#define I2S_Standard_MSB ((uint16_t)0x0010)
+#define I2S_Standard_LSB ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+ ((STANDARD) == I2S_Standard_MSB) || \
+ ((STANDARD) == I2S_Standard_LSB) || \
+ ((STANDARD) == I2S_Standard_PCMShort) || \
+ ((STANDARD) == I2S_Standard_PCMLong))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DataFormat_16b ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+#define I2S_DataFormat_24b ((uint16_t)0x0003)
+#define I2S_DataFormat_32b ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+ ((FORMAT) == I2S_DataFormat_16bextended) || \
+ ((FORMAT) == I2S_DataFormat_24b) || \
+ ((FORMAT) == I2S_DataFormat_32b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+ ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AudioFreq_192k ((uint32_t)192000)
+#define I2S_AudioFreq_96k ((uint32_t)96000)
+#define I2S_AudioFreq_48k ((uint32_t)48000)
+#define I2S_AudioFreq_44k ((uint32_t)44100)
+#define I2S_AudioFreq_32k ((uint32_t)32000)
+#define I2S_AudioFreq_22k ((uint32_t)22050)
+#define I2S_AudioFreq_16k ((uint32_t)16000)
+#define I2S_AudioFreq_11k ((uint32_t)11025)
+#define I2S_AudioFreq_8k ((uint32_t)8000)
+#define I2S_AudioFreq_Default ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+ ((FREQ) <= I2S_AudioFreq_192k)) || \
+ ((FREQ) == I2S_AudioFreq_Default))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CPOL_Low ((uint16_t)0x0000)
+#define I2S_CPOL_High SPI_I2SCFGR_CKPOL
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+ ((CPOL) == I2S_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_FIFO_reception_threshold
+ * @{
+ */
+
+#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
+#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
+#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
+ ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
+#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
+#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_last_DMA_transfers
+ * @{
+ */
+
+#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
+#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
+#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
+#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
+#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
+ ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
+ ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
+ ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
+/**
+ * @}
+ */
+/** @defgroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSSInternalSoft_Set SPI_CR1_SSI
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+ ((DIRECTION) == SPI_Direction_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_RXNE) || \
+ ((IT) == SPI_I2S_IT_ERR))
+
+#define I2S_IT_UDR ((uint8_t)0x53)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_I2S_IT_FRE ((uint8_t)0x58)
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
+ ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_transmission_fifo_status_level
+ * @{
+ */
+
+#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
+#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
+#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
+#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level
+ * @{
+ */
+#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
+#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
+#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
+#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
+#define SPI_I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR
+#define SPI_FLAG_MODF SPI_SR_MODF
+#define SPI_I2S_FLAG_OVR SPI_SR_OVR
+#define SPI_I2S_FLAG_BSY SPI_SR_BSY
+#define SPI_I2S_FLAG_FRE SPI_SR_FRE
+
+
+
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+ ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
+ ((FLAG) == I2S_FLAG_UDR))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_SPI_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_syscfg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,262 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_syscfg.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the SYSCFG firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/*!< Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_SYSCFG_H
+#define __STM32F0XX_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SYSCFG
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SYSCFG_EXTI_Port_Sources
+ * @{
+ */
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03) /*!< not available for STM32F031 devices */
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04) /*!< only available for STM32F072 devices */
+#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOF))
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_EXTI_Pin_sources
+ * @{
+ */
+#define EXTI_PinSource0 ((uint8_t)0x00)
+#define EXTI_PinSource1 ((uint8_t)0x01)
+#define EXTI_PinSource2 ((uint8_t)0x02)
+#define EXTI_PinSource3 ((uint8_t)0x03)
+#define EXTI_PinSource4 ((uint8_t)0x04)
+#define EXTI_PinSource5 ((uint8_t)0x05)
+#define EXTI_PinSource6 ((uint8_t)0x06)
+#define EXTI_PinSource7 ((uint8_t)0x07)
+#define EXTI_PinSource8 ((uint8_t)0x08)
+#define EXTI_PinSource9 ((uint8_t)0x09)
+#define EXTI_PinSource10 ((uint8_t)0x0A)
+#define EXTI_PinSource11 ((uint8_t)0x0B)
+#define EXTI_PinSource12 ((uint8_t)0x0C)
+#define EXTI_PinSource13 ((uint8_t)0x0D)
+#define EXTI_PinSource14 ((uint8_t)0x0E)
+#define EXTI_PinSource15 ((uint8_t)0x0F)
+
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+ ((PINSOURCE) == EXTI_PinSource1) || \
+ ((PINSOURCE) == EXTI_PinSource2) || \
+ ((PINSOURCE) == EXTI_PinSource3) || \
+ ((PINSOURCE) == EXTI_PinSource4) || \
+ ((PINSOURCE) == EXTI_PinSource5) || \
+ ((PINSOURCE) == EXTI_PinSource6) || \
+ ((PINSOURCE) == EXTI_PinSource7) || \
+ ((PINSOURCE) == EXTI_PinSource8) || \
+ ((PINSOURCE) == EXTI_PinSource9) || \
+ ((PINSOURCE) == EXTI_PinSource10) || \
+ ((PINSOURCE) == EXTI_PinSource11) || \
+ ((PINSOURCE) == EXTI_PinSource12) || \
+ ((PINSOURCE) == EXTI_PinSource13) || \
+ ((PINSOURCE) == EXTI_PinSource14) || \
+ ((PINSOURCE) == EXTI_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Memory_Remap_Config
+ * @{
+ */
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
+
+
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_DMA_Remap_Config
+ * @{
+ */
+#define SYSCFG_DMARemap_TIM3 SYSCFG_CFGR1_TIM3_DMA_RMP /* Remap TIM3 DMA requests from channel4 to channel6,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM2 SYSCFG_CFGR1_TIM2_DMA_RMP /* Remap TIM2 DMA requests from channel3/4 to channel7,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM1 SYSCFG_CFGR1_TIM1_DMA_RMP /* Remap TIM1 DMA requests from channel2/3/4 to channel6,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_I2C1 SYSCFG_CFGR1_I2C1_DMA_RMP /* Remap I2C1 DMA requests from channel3/2 to channel7/6,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_USART2 SYSCFG_CFGR1_USART2_DMA_RMP /* Remap USART2 DMA requests from channel4/5 to channel6/7,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_SPI2 SYSCFG_CFGR1_SPI2_DMA_RMP /* Remap SPI2 DMA requests from channel4/5 to channel6/7,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM17_2 SYSCFG_CFGR1_TIM17_DMA_RMP2 /* Remap TIM17 DMA requests from channel1/2 to channel7,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM16_2 SYSCFG_CFGR1_TIM16_DMA_RMP2 /* Remap TIM16 DMA requests from channel3/4 to channel6,
+ available only for STM32F072 devices */
+#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
+#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
+#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
+#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
+#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */
+
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
+ ((REMAP) == SYSCFG_DMARemap_TIM16) || \
+ ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
+ ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
+ ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
+ ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
+ ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
+ ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
+ ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \
+ ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \
+ ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
+ ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
+ ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
+ ((REMAP) == SYSCFG_DMARemap_ADC1))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_I2C_FastModePlus_Config
+ * @{
+ */
+#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
+#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
+#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
+#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
+#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0031 and STM32F030 devices) */
+#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins, available only for STM32F072 devices */
+#define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for STM32F031 and STM32F030 devices) */
+#define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for STM32F031 and STM32F030 devices) */
+
+#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \
+ ((PIN) == SYSCFG_I2CFastModePlus_PA10))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Lock_Config
+ * @{
+ */
+#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices */
+#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */
+#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
+
+#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
+ ((CONFIG) == SYSCFG_Break_SRAMParity) || \
+ ((CONFIG) == SYSCFG_Break_Lockup))
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_flags_definition
+ * @{
+ */
+
+#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
+
+#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the SYSCFG configuration to the default reset state **/
+void SYSCFG_DeInit(void);
+
+/* SYSCFG configuration functions *********************************************/
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_SYSCFG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_tim.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1186 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_tim.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the TIM
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_TIM_H
+#define __STM32F0XX_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This sturcture is used with all TIMx.
+ */
+
+typedef struct
+{
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1. */
+} TIM_TimeBaseInitTypeDef;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1. */
+
+ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF
+ for TIM2) */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1. */
+
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1. */
+
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1. */
+} TIM_OCInitTypeDef;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/**
+ * @brief TIM_BDTR structure definition
+ * @note This sturcture is used only with TIM1.
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_Lock_level */
+
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_Break_Polarity */
+
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM14)|| \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST1: TIM 1 */
+#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)
+
+/* LIST2: TIM 1, 15, 16 and 17 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST3: TIM 1, 2 and 3 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3))
+
+/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM14) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST6: TIM 1, 2, 3 and 15 */
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM15))
+
+/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM14))
+
+/* LIST8: TIM 1, 2, 3 and 14 */
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM14))
+
+/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */
+#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM15))
+
+/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */
+#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST1: TIM 11 */
+#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMode_Timing ((uint16_t)0x0000)
+#define TIM_OCMode_Active ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_ForcedAction_Active) || \
+ ((MODE) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+ ((MODE) == TIM_OPMode_Repetitive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
+
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3) || \
+ ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+ ((DIV) == TIM_CKD_DIV2) || \
+ ((DIV) == TIM_CKD_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+ ((MODE) == TIM_CounterMode_Down) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+ ((POLARITY) == TIM_OCPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+ ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+ ((STATE) == TIM_OutputState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+ ((STATE) == TIM_OutputNState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+ ((CCX) == TIM_CCx_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CCxN_Enable ((uint16_t)0x0004)
+#define TIM_CCxN_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+ ((CCXN) == TIM_CCxN_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break_Enable ((uint16_t)0x1000)
+#define TIM_Break_Disable ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+ ((STATE) == TIM_Break_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity
+ * @{
+ */
+
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+ ((POLARITY) == TIM_BreakPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+ ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Lock_level
+ * @{
+ */
+
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+ ((LEVEL) == TIM_LOCKLevel_1) || \
+ ((LEVEL) == TIM_LOCKLevel_2) || \
+ ((LEVEL) == TIM_LOCKLevel_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+ ((STATE) == TIM_OSSIState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+ ((STATE) == TIM_OSSRState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+ ((STATE) == TIM_OCIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+ ((STATE) == TIM_OCNIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \
+ ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+ ((SELECTION) == TIM_ICSelection_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_COM ((uint16_t)0x0020)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define TIM_IT_Break ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_Trigger) || \
+ ((IT) == TIM_IT_Break))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_RCR ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
+#define TIM_DMABase_OR ((uint16_t)0x0013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR) || \
+ ((BASE) == TIM_DMABase_OR))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+ ((ACTION) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+ ((MODE) == TIM_EncoderMode_TI2) || \
+ ((MODE) == TIM_EncoderMode_TI12))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_COM ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define TIM_EventSource_Break ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+ ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+ ((STATE) == TIM_OCPreload_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+ ((STATE) == TIM_OCFast_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+ ((STATE) == TIM_OCClear_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+ ((SOURCE) == TIM_TRGOSource_Enable) || \
+ ((SOURCE) == TIM_TRGOSource_Update) || \
+ ((SOURCE) == TIM_TRGOSource_OC1) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+ ((MODE) == TIM_SlaveMode_Gated) || \
+ ((MODE) == TIM_SlaveMode_Trigger) || \
+ ((MODE) == TIM_SlaveMode_External1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_Update ((uint16_t)0x0001)
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)
+#define TIM_FLAG_COM ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)
+#define TIM_FLAG_Break ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_Trigger) || \
+ ((FLAG) == TIM_FLAG_Break) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OCReferenceClear
+ * @{
+ */
+#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
+#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
+ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Remap
+ * @{
+ */
+#define TIM14_GPIO ((uint16_t)0x0000)
+#define TIM14_RTC_CLK ((uint16_t)0x0001)
+#define TIM14_HSEDiv32 ((uint16_t)0x0002)
+#define TIM14_MCO ((uint16_t)0x0003)
+
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \
+ ((TIM_REMAP) == TIM14_RTC_CLK) || \
+ ((TIM_REMAP) == TIM14_HSEDiv32) || \
+ ((TIM_REMAP) == TIM14_MCO))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Advanced-control timers (TIM1) specific features*******************/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0XX_TIM_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_usart.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,599 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_usart.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the USART
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_USART_H
+#define __STM32F0XX_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+
+
+/**
+ * @brief USART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+ uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint32_t USART_Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control*/
+} USART_InitTypeDef;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_Clock */
+
+ uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == USART4))
+
+#define IS_USART_12_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2))
+
+/** @defgroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WordLength_8b ((uint32_t)0x00000000)
+#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */
+#define USART_WordLength_7b ((uint32_t)0x10001000) /*!< only available for STM32F072 and STM32F030 devices */
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+ ((LENGTH) == USART_WordLength_9b) || \
+ ((LENGTH) == USART_WordLength_7b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_StopBits_1 ((uint32_t)0x00000000)
+#define USART_StopBits_2 USART_CR2_STOP_1
+#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+ ((STOPBITS) == USART_StopBits_2) || \
+ ((STOPBITS) == USART_StopBits_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+
+#define USART_Parity_No ((uint32_t)0x00000000)
+#define USART_Parity_Even USART_CR1_PCE
+#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+ ((PARITY) == USART_Parity_Even) || \
+ ((PARITY) == USART_Parity_Odd))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+
+#define USART_Mode_Rx USART_CR1_RE
+#define USART_Mode_Tx USART_CR1_TE
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
+ ((MODE) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Hardware_Flow_Control
+ * @{
+ */
+
+#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
+#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
+#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
+#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == USART_HardwareFlowControl_None) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+
+#define USART_Clock_Disable ((uint32_t)0x00000000)
+#define USART_Clock_Enable USART_CR2_CLKEN
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+ ((CLOCK) == USART_Clock_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CPOL_Low ((uint32_t)0x00000000)
+#define USART_CPOL_High USART_CR2_CPOL
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CPHA_1Edge ((uint32_t)0x00000000)
+#define USART_CPHA_2Edge USART_CR2_CPHA
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_LastBit_Disable ((uint32_t)0x00000000)
+#define USART_LastBit_Enable USART_CR2_LBCL
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+ ((LASTBIT) == USART_LastBit_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAReq_Tx USART_CR3_DMAT
+#define USART_DMAReq_Rx USART_CR3_DMAR
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
+ ((DMAREQ) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Recception_Error
+ * @{
+ */
+
+#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
+#define USART_DMAOnError_Disable USART_CR3_DDRE
+#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
+ ((DMAERROR) == USART_DMAOnError_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_MuteMode_WakeUp_methods
+ * @{
+ */
+
+#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
+#define USART_WakeUp_AddressMark USART_CR1_WAKE
+#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+ ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Address_Detection
+ * @{
+ */
+
+#define USART_AddressLength_4b ((uint32_t)0x00000000)
+#define USART_AddressLength_7b USART_CR2_ADDM7
+#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
+ ((ADDRESS) == USART_AddressLength_7b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_StopMode_WakeUp_methods
+ * @note These parameters are only available for STM32F051 and STM32F072 devices
+ * @{
+ */
+
+#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
+#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
+#define USART_WakeUpSource_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
+#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
+ ((SOURCE) == USART_WakeUpSource_StartBit) || \
+ ((SOURCE) == USART_WakeUpSource_RXNE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
+#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+ ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IrDAMode_LowPower USART_CR3_IRLP
+#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+ ((MODE) == USART_IrDAMode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DE_Polarity
+ * @{
+ */
+
+#define USART_DEPolarity_High ((uint32_t)0x00000000)
+#define USART_DEPolarity_Low USART_CR3_DEP
+#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
+ ((POLARITY) == USART_DEPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Inversion_Pins
+ * @{
+ */
+
+#define USART_InvPin_Tx USART_CR2_TXINV
+#define USART_InvPin_Rx USART_CR2_RXINV
+#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
+ ((PIN) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_AutoBaudRate_Mode
+ * @{
+ */
+
+#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
+#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
+#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
+ ((MODE) == USART_AutoBaudRate_FallingEdge))
+/**
+ * @}
+ */
+
+/** @defgroup USART_OVR_DETECTION
+ * @{
+ */
+
+#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
+#define USART_OVRDetection_Disable USART_CR3_OVRDIS
+#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
+ ((OVR) == USART_OVRDetection_Disable))
+/**
+ * @}
+ */
+/** @defgroup USART_Request
+ * @{
+ */
+
+#define USART_Request_ABRRQ USART_RQR_ABRRQ
+#define USART_Request_SBKRQ USART_RQR_SBKRQ
+#define USART_Request_MMRQ USART_RQR_MMRQ
+#define USART_Request_RXFRQ USART_RQR_RXFRQ
+#define USART_Request_TXFRQ USART_RQR_TXFRQ
+
+#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
+ ((REQUEST) == USART_Request_RXFRQ) || \
+ ((REQUEST) == USART_Request_MMRQ) || \
+ ((REQUEST) == USART_Request_SBKRQ) || \
+ ((REQUEST) == USART_Request_ABRRQ))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags
+ * @{
+ */
+#define USART_FLAG_REACK USART_ISR_REACK
+#define USART_FLAG_TEACK USART_ISR_TEACK
+#define USART_FLAG_WU USART_ISR_WUF /*!< Not available for STM32F030 devices */
+#define USART_FLAG_RWU USART_ISR_RWU /*!< Not available for STM32F030 devices */
+#define USART_FLAG_SBK USART_ISR_SBKF
+#define USART_FLAG_CM USART_ISR_CMF
+#define USART_FLAG_BUSY USART_ISR_BUSY
+#define USART_FLAG_ABRF USART_ISR_ABRF
+#define USART_FLAG_ABRE USART_ISR_ABRE
+#define USART_FLAG_EOB USART_ISR_EOBF /*!< Not available for STM32F030 devices */
+#define USART_FLAG_RTO USART_ISR_RTOF
+#define USART_FLAG_nCTSS USART_ISR_CTS
+#define USART_FLAG_CTS USART_ISR_CTSIF
+#define USART_FLAG_LBD USART_ISR_LBD /*!< Not available for STM32F030 devices */
+#define USART_FLAG_TXE USART_ISR_TXE
+#define USART_FLAG_TC USART_ISR_TC
+#define USART_FLAG_RXNE USART_ISR_RXNE
+#define USART_FLAG_IDLE USART_ISR_IDLE
+#define USART_FLAG_ORE USART_ISR_ORE
+#define USART_FLAG_NE USART_ISR_NE
+#define USART_FLAG_FE USART_ISR_FE
+#define USART_FLAG_PE USART_ISR_PE
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+ ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
+ ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
+ ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
+ ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
+ ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
+ ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
+
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+ ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
+ ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
+ ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * @brief USART Interrupt definition
+ * USART_IT possible values
+ * Elements values convention: 0xZZZZYYXX
+ * XX: Position of the corresponding Interrupt
+ * YY: Register index
+ * ZZZZ: Flag position
+ * @{
+ */
+
+#define USART_IT_WU ((uint32_t)0x00140316) /*!< Not available for STM32F030 devices */
+#define USART_IT_CM ((uint32_t)0x0011010E)
+#define USART_IT_EOB ((uint32_t)0x000C011B) /*!< Not available for STM32F030 devices */
+#define USART_IT_RTO ((uint32_t)0x000B011A)
+#define USART_IT_PE ((uint32_t)0x00000108)
+#define USART_IT_TXE ((uint32_t)0x00070107)
+#define USART_IT_TC ((uint32_t)0x00060106)
+#define USART_IT_RXNE ((uint32_t)0x00050105)
+#define USART_IT_IDLE ((uint32_t)0x00040104)
+#define USART_IT_LBD ((uint32_t)0x00080206) /*!< Not available for STM32F030 devices */
+#define USART_IT_CTS ((uint32_t)0x0009030A)
+#define USART_IT_ERR ((uint32_t)0x00000300)
+#define USART_IT_ORE ((uint32_t)0x00030300)
+#define USART_IT_NE ((uint32_t)0x00020300)
+#define USART_IT_FE ((uint32_t)0x00010300)
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
+ ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
+ ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Global_definition
+ * @{
+ */
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
+#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
+#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
+#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); /* Not available for STM32F030 devices */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
+
+/* STOP Mode functions ********************************************************/
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); /* Not available for STM32F030 devices */
+
+/* AutoBaudRate functions *****************************************************/
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
+
+/* Data transfers functions ***************************************************/
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
+
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); /* Not available for STM32F030 devices */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* Not available for STM32F030 devices */
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); /* Not available for STM32F030 devices */
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); /* Not available for STM32F030 devices */
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); /* Not available for STM32F030 devices */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
+
+/* RS485 mode functions *******************************************************/
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_USART_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_wwdg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,109 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_wwdg.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 16-January-2014
+ * @brief This file contains all the functions prototypes for the WWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_WWDG_H
+#define __STM32F0XX_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/** @addtogroup STM32F0xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+ ((PRESCALER) == WWDG_Prescaler_2) || \
+ ((PRESCALER) == WWDG_Prescaler_4) || \
+ ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the WWDG configuration to the default reset state ****/
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation functions **************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F030R8/system_stm32f0xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,104 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V1.3.1
+ * @date 17-January-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/PeripheralNames.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_NUCLEO_F103RB/PeripheralNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -62,13 +62,10 @@
typedef enum {
PWM_2 = (int)TIM2_BASE,
- PWM_3 = (int)TIM3_BASE
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE
} PWMName;
-typedef enum {
- CAN_1 = (int)CAN1_BASE
-} CANName;
-
#ifdef __cplusplus
}
#endif
--- a/TARGET_NUCLEO_F103RB/PinNames.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_NUCLEO_F103RB/PinNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -42,15 +42,17 @@
#define STM_PIN_MODE(X) ((X) >> 8)
#define STM_PIN_AFNUM(X) ((X) & 0xFF)
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
-
- // high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F)
- // low nibble = pin number
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
@@ -102,8 +104,9 @@
PC_14 = 0x2E,
PC_15 = 0x2F,
+ PD_0 = 0x30,
+ PD_1 = 0x31,
PD_2 = 0x32,
- PD_8 = 0x38,
// Arduino connector namings
A0 = PA_0,
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/misc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/startup_stm32f10x_md.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LR_IROM1 0x08000000 0x20000 { ; load region size_region (128K)
+
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
+ RW_IRAM1 (0x20000000+0xEC) (0x5000-0xEC) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_adc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_bkp.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_can.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_cec.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_crc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_dac.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_dma.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_exti.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_flash.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_fsmc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_gpio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_i2c.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_iwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_pwr.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_rcc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_rtc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_sdio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_spi.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_tim.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_usart.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_wwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/system_stm32f10x.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/misc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/startup_stm32f10x_md.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_adc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_bkp.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_can.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_cec.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_crc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_dac.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_dma.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_exti.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_flash.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_fsmc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_gpio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_i2c.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_iwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_pwr.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_rcc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_rtc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_sdio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_spi.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_tim.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_usart.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_wwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/system_stm32f10x.o has changed
--- a/TARGET_NUCLEO_F103RB/misc.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/misc.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file misc.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ******************************************************************************* @@ -232,4 +232,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/objects.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_NUCLEO_F103RB/objects.h Fri Feb 14 14:36:43 2014 +0000
@@ -40,9 +40,9 @@
#endif
struct gpio_irq_s {
- uint32_t ch;
IRQn_Type irq_n;
- uint32_t event; // 0=none, 1=rise, 2=fall, 3=rise+fall
+ uint32_t irq_index;
+ uint32_t event;
};
struct port_s {
--- a/TARGET_NUCLEO_F103RB/stm32f10x.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_NUCLEO_F103RB/stm32f10x.h Fri Feb 14 14:36:43 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x.h
* @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
+ * @version V3.6.2
+ * @date 28-February-2013
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F10x Connectivity line,
@@ -67,7 +67,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
@@ -79,11 +79,11 @@
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
- /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
-#define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */
- /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
+ /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
+#define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */
+ /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
- /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
+ /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
/* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
#endif
@@ -111,14 +111,14 @@
#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
#endif
-#if !defined USE_STDPERIPH_DRIVER
+#if !defined (USE_STDPERIPH_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
#define USE_STDPERIPH_DRIVER
-#endif
+#endif /* USE_STDPERIPH_DRIVER */
/**
* @brief In the following line adjust the value of External High Speed oscillator (HSE)
@@ -135,23 +135,26 @@
#endif /* STM32F10X_CL */
#endif /* HSE_VALUE */
-
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value
*/
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
-
-#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
/**
* @brief STM32F10x Standard Peripheral Library version number
*/
-#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
+#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
|(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
|(__STM32F10X_STDPERIPH_VERSION_RC))
@@ -168,12 +171,13 @@
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
#ifdef STM32F10X_XL
- #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
+ #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
#else
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
#endif /* STM32F10X_XL */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* @brief STM32F10x Interrupt Number Definition, according to the selected device
@@ -231,7 +235,7 @@
USART2_IRQn = 38, /*!< USART2 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
#endif /* STM32F10X_LD */
#ifdef STM32F10X_LD_VL
@@ -252,7 +256,7 @@
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
- TIM7_IRQn = 55 /*!< TIM7 Interrupt */
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */
#endif /* STM32F10X_LD_VL */
#ifdef STM32F10X_MD
@@ -280,7 +284,7 @@
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
#endif /* STM32F10X_MD */
#ifdef STM32F10X_MD_VL
@@ -306,7 +310,7 @@
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
- TIM7_IRQn = 55 /*!< TIM7 Interrupt */
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */
#endif /* STM32F10X_MD_VL */
#ifdef STM32F10X_HD
@@ -382,16 +386,16 @@
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
mapped at position 60 only if the MISC_REMAP bit in
- the AFIO_MAPR2 register is set) */
+ the AFIO_MAPR2 register is set) */
#endif /* STM32F10X_HD_VL */
#ifdef STM32F10X_XL
@@ -483,7 +487,7 @@
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
-#endif /* STM32F10X_CL */
+#endif /* STM32F10X_CL */
} IRQn_Type;
/**
@@ -2036,7 +2040,7 @@
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
#endif
@@ -3628,7 +3632,7 @@
#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
-#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
@@ -4106,6 +4110,11 @@
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */
+ #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */
+#endif
+
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
@@ -4706,6 +4715,10 @@
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
@@ -4747,6 +4760,10 @@
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
@@ -4788,6 +4805,10 @@
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
@@ -4829,6 +4850,10 @@
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
@@ -4870,6 +4895,10 @@
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
@@ -4905,6 +4934,10 @@
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
@@ -4940,6 +4973,10 @@
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
@@ -4975,6 +5012,10 @@
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
@@ -7803,7 +7844,7 @@
/******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY ((uint8_t)0x07) /*!< LATENCY[2:0] bits (Latency) */
#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */
#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */
#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */
@@ -7815,6 +7856,11 @@
/****************** Bit definition for FLASH_KEYR register ******************/
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+/****************** FLASH Keys **********************************************/
+#define RDP_Key ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
/***************** Bit definition for FLASH_OPTKEYR register ****************/
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
@@ -8336,7 +8382,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* __STM32F10x_H */
@@ -8348,4 +8394,4 @@
* @}
*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_adc.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_adc.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_adc.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the ADC firmware * library. ******************************************************************************* @@ -495,4 +495,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_bkp.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_bkp.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_bkp.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the BKP firmware * library. ******************************************************************************* @@ -207,4 +207,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_can.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_can.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_can.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the CAN firmware * library. ******************************************************************************* @@ -709,4 +709,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_cec.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_cec.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_cec.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the CEC firmware * library. ******************************************************************************* @@ -222,4 +222,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_conf.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_conf.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h * @author MCD Application Team - * @version V3.5.0 - * @date 08-April-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief Library configuration file. ******************************************************************************* * Copyright (c) 2014, STMicroelectronics @@ -89,4 +89,4 @@ #endif /* __STM32F10x_CONF_H */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_crc.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_crc.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_crc.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the CRC firmware * library. ******************************************************************************* @@ -106,4 +106,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_dac.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_dac.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dac.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the DAC firmware * library. ******************************************************************************* @@ -329,4 +329,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_dbgmcu.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_dbgmcu.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dbgmcu.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the DBGMCU * firmware library. ******************************************************************************* @@ -131,4 +131,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_dma.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_dma.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_dma.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the DMA firmware * library. ******************************************************************************* @@ -451,4 +451,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_exti.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_NUCLEO_F103RB/stm32f10x_exti.h Fri Feb 14 14:36:43 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_exti.h
* @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
+ * @version V3.6.1
+ * @date 05-March-2012
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
*******************************************************************************
@@ -97,7 +97,7 @@
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
+ This parameter can be a value of @ref EXTITrigger_TypeDef */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
@@ -196,4 +196,4 @@
* @}
*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_flash.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_flash.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_flash.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ******************************************************************************* @@ -438,4 +438,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_fsmc.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_fsmc.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_fsmc.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ******************************************************************************* @@ -745,4 +745,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_gpio.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_gpio.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_gpio.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the GPIO * firmware library. ******************************************************************************* @@ -397,4 +397,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_i2c.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_i2c.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_i2c.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the I2C firmware * library. ******************************************************************************* @@ -696,4 +696,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_iwdg.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_iwdg.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_iwdg.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ******************************************************************************* @@ -152,4 +152,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_pwr.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_pwr.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_pwr.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the PWR firmware * library. ******************************************************************************* @@ -168,4 +168,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_rcc.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_rcc.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_rcc.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the RCC firmware * library. ******************************************************************************* @@ -739,4 +739,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_rtc.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_rtc.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_rtc.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the RTC firmware * library. ******************************************************************************* @@ -147,4 +147,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_sdio.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_sdio.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_sdio.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ******************************************************************************* @@ -543,4 +543,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_spi.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_spi.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_spi.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the SPI firmware * library. ******************************************************************************* @@ -499,4 +499,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_tim.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_tim.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_tim.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the TIM firmware * library. ******************************************************************************* @@ -1176,4 +1176,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_usart.h Mon Jan 13 15:31:11 2014 +0200
+++ b/TARGET_NUCLEO_F103RB/stm32f10x_usart.h Fri Feb 14 14:36:43 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f10x_usart.h
* @author MCD Application Team
- * @version V3.5.0
- * @date 11-March-2011
+ * @version V3.6.1
+ * @date 05-March-2012
* @brief This file contains all the functions prototypes for the USART
* firmware library.
*******************************************************************************
@@ -258,22 +258,35 @@
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
-#define USART_IT_ORE ((uint16_t)0x0360)
+#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
+
+/** @defgroup USART_Legacy
+ * @{
+ */
+#define USART_IT_ORE USART_IT_ORE_ER
+/**
+ * @}
+ */
+
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+ ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
/**
@@ -350,9 +363,7 @@
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
-#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
- ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
- || ((USART_FLAG) != USART_FLAG_CTS))
+
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
@@ -424,4 +435,4 @@
* @}
*/
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/stm32f10x_wwdg.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/stm32f10x_wwdg.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f10x_wwdg.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.1 + * @date 05-March-2012 * @brief This file contains all the functions prototypes for the WWDG firmware * library. ******************************************************************************* @@ -127,4 +127,4 @@ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/TARGET_NUCLEO_F103RB/system_stm32f10x.h Mon Jan 13 15:31:11 2014 +0200 +++ b/TARGET_NUCLEO_F103RB/system_stm32f10x.h Fri Feb 14 14:36:43 2014 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 + * @version V3.6.2 + * @date 28-February-2013 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ******************************************************************************* * Copyright (c) 2014, STMicroelectronics @@ -110,4 +110,4 @@ /** * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/PeripheralNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/PinNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,179 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ USER_BUTTON = PC_13,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/PortNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortH = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f401xe.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LR_IROM1 0x08000000 0x80000 { ; load region size_region (512K)
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x194) (0x18000-0x194) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cryp_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dcmi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma2d.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_eth.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_ltdc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_nand.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_nor.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pccard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sai.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sdram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_fmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_fsmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_sdmmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_usb.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/system_stm32f4xx.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/startup_stm32f401xe.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f401xe.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LR_IROM1 0x08000000 0x80000 { ; load region size_region (512K)
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x194) (0x18000-0x194) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cryp_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dcmi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma2d.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_eth.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_ltdc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_nand.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_nor.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pccard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sai.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sdram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_fmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_fsmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_sdmmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_usb.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/system_stm32f4xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_F401RE/cmsis.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/cmsis_nvic.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F401RE
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
+// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+#define NVIC_NUM_VECTORS 101
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/core_cm0.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/core_cm0plus.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/core_cm3.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/core_cm4.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/core_cm4_simd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/core_cmFunc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/core_cmInstr.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_F401RE/device.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 0 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +//#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/gpio_object.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint32_t *reg_in;
+ __IO uint16_t *reg_set;
+ __IO uint16_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value) {
+ *obj->reg_set = obj->mask;
+ }
+ else {
+ *obj->reg_clr = obj->mask;
+ }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/objects.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+};
+
+struct i2c_s {
+ I2CName i2c;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f401xe.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,4773 @@
+/**
+ ******************************************************************************
+ * @file stm32f401xe.h
+ * @author MCD Application Team
+ * @version V2.0.0RC6
+ * @date 03-February-2014
+ * @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f401xe
+ * @{
+ */
+
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)
+#define RNG_CR_IE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY ((uint32_t)0x00000001)
+#define RNG_SR_CECS ((uint32_t)0x00000002)
+#define RNG_SR_SECS ((uint32_t)0x00000004)
+#define RNG_SR_CEIS ((uint32_t)0x00000020)
+#define RNG_SR_SEIS ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F401xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,216 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.0.0RC6
+ * @date 03-February-2014
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+#define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE, STM32F401VE Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.0.0RC6
+ */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x06) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,191 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_H
+#define __STM32F4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_conf.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Freeze/Unfreeze Peripherals in Debug mode
+ */
+#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_FREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_FREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_FREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_FREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_UNFREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_UNFREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_UNFREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_UNFREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+/** @brief Main Flash memory mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FLASH (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+
+/** @brief System Flash memory mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_SYSTEMFLASH do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+ }while(0);
+
+/** @brief Embedded SRAM mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_SRAM do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FSMC do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FMC do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+
+/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FMC_SDRAM do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
+ }while(0);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+__weak void HAL_MspInit(void);
+__weak void HAL_MspDeInit(void);
+
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+void HAL_EnableMemorySwappingBank(void);
+void HAL_DisableMemorySwappingBank(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,738 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of ADC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_H
+#define __STM32F4xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
+ HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
+ HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
+ HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
+ HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
+ HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
+ HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
+ HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
+ HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
+ HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
+ HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
+
+}HAL_ADC_StateTypeDef;
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
+ all the ADCs.
+ This parameter can be a value of @ref ADC_ClockPrescaler */
+ uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
+ This parameter can be a value of @ref ADC_Resolution */
+ uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+ uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
+ Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
+ at the end of single channel conversion or at the end of all conversions.
+ This parameter can be a value of @ref ADC_EOCSelection */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
+ regular channel group.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
+ for regular channels.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
+ using the sequencer for regular channel group.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+ uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+}ADC_InitTypeDef;
+
+/**
+ * @brief ADC handle Structure definition
+ */
+typedef struct
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+}ADC_HandleTypeDef;
+
+/**
+ * @brief ADC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< The ADC channel to configure
+ This parameter can be a value of @ref ADC_channels */
+ uint32_t Rank; /*!< The rank in the regular group sequencer
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+ uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
+ This parameter can be a value of @ref ADC_sampling_times */
+ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief ADC Configuration multi-mode structure definition
+ */
+typedef struct
+{
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
+ This parameter can be a value of @ref ADC_analog_watchdog_selection. */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a 12-bit value. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a 12-bit value. */
+ uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
+ This parameter has an effect only if watchdog mode is configured on single channel
+ This parameter can be a value of @ref ADC_channels. */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
+ is interrupt mode or in polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+}ADC_AnalogWDGConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup ADC_Error_Code
+ * @{
+ */
+
+#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_ClockPrescaler
+ * @{
+ */
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_delay_between_2_sampling_phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
+#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
+#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
+#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
+#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
+#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
+
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Resolution
+ * @{
+ */
+#define ADC_RESOLUTION12b ((uint32_t)0x00000000)
+#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0)
+#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1)
+#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES)
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
+ ((RESOLUTION) == ADC_RESOLUTION10b) || \
+ ((RESOLUTION) == ADC_RESOLUTION8b) || \
+ ((RESOLUTION) == ADC_RESOLUTION6b))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_edge_Regular
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_Source_Regular
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
+#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
+#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
+
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
+#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
+#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_16) || \
+ ((CHANNEL) == ADC_CHANNEL_17) || \
+ ((CHANNEL) == ADC_CHANNEL_18))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times
+ * @{
+ */
+#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
+#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
+#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
+#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
+#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_480CYCLES))
+/**
+ * @}
+ */
+
+ /** @defgroup ADC_EOCSelection
+ * @{
+ */
+#define EOC_SEQ_CONV ((uint32_t)0x00000000)
+#define EOC_SINGLE_CONV ((uint32_t)0x00000001)
+#define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
+
+#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) || \
+ ((EOCSelection) == EOC_SEQ_CONV) || \
+ ((EOCSelection) == EOC_SINGLE_SEQ_CONV))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type
+ * @{
+ */
+#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
+#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
+ ((EVENT) == OVR_EVENT))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
+#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
+#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
+#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
+
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
+#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
+#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
+#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
+#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
+#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels_type
+ * @{
+ */
+#define ALL_CHANNELS ((uint32_t)0x00000001)
+#define REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
+#define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
+
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
+ ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
+ ((CHANNEL_TYPE) == INJECTED_CHANNELS))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_range_verification
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief Enable the ADC peripheral.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
+
+/**
+ * @brief Disable the ADC peripheral.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
+
+/**
+ * @brief Set ADC Regular channel sequence length.
+ * @param _NbrOfConversion_: Regular channel sequence length.
+ * @retval None
+ */
+#define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
+
+/**
+ * @brief Enable ADC scan mode.
+ * @param _SCANCONV_MODE_: Scan conversion mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
+
+/**
+ * @brief Enable the ADC end of conversion selection.
+ * @param _EOCSelection_MODE_: End of conversion selection mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMAContReq_MODE_: DMA continuous request mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: ADC Interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: ADC interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
+
+/** @brief Check if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: specifies the ADC interrupt source to check.
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Clear the ADC's pending flags.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __FLAG__: ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __FLAG__: ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Return resolution bits in CR1 register.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
+
+/* Include ADC HAL Extension module */
+#include "stm32f4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+
+/* Peripheral State functions ***************************************************/
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,288 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_EX_H
+#define __STM32F4xx_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief ADC Configuration injected Channel structure definition
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Configure the ADC injected channel
+ This parameter can be a value of @ref ADC_channels. */
+ uint32_t InjectedRank; /*!< The rank in the injected group sequencer
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
+ uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
+ This parameter can be a value of @ref ADC_sampling_times */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
+ injected channel group.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group
+ conversion after regular one */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Injected. */
+ uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Injected */
+}ADC_InjectionConfTypeDef;
+
+/**
+ * @brief ADC Configuration multi-mode structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+ This parameter can be a value of @ref ADC_Common_mode */
+ uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
+ This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
+}ADC_MultiModeTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup ADCEx_Common_mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERL) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
+ ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_INTERL) || \
+ ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode
+ * @{
+ */
+#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */
+#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((MODE) == ADC_DMAACCESSMODE_1) || \
+ ((MODE) == ADC_DMAACCESSMODE_2) || \
+ ((MODE) == ADC_DMAACCESSMODE_3))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
+
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_Source_Injected
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_channel_selection
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_length
+ * @{
+ */
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_rank
+ * @{
+ */
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define __HAL_ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) \
+((_CHANNELNB_) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,775 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CAN_H
+#define __STM32F4xx_HAL_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint32_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code */
+
+}CAN_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HAL CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */
+#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
+#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */
+#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */
+#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR 0x10 /*!< Form error */
+#define HAL_CAN_ERROR_ACK 0x20 /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR 0x40 /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD 0x80 /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode
+ * @{
+ */
+#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx
+ * @{
+ */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
+#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
+#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
+
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+ ((FLAG) == CAN_FLAG_WKU))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+ * @}
+ */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__: CAN handle
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__: CAN Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__: CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->ESR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__: CAN Handle
+ * @param __INTERRUPT__: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__: CAN Handle
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__: CAN handle
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__: CAN Handle
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disable the DBG Freeze for CAN.
+ * @param __HANDLE__: CAN Handle
+ * @param __NEWSTATE__: new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+
+/* Peripheral State functions ***************************************************/
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,391 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f4xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,163 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cortex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CORTEX_H
+#define __STM32F4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/** @brief Configures the SysTick clock source.
+ * @param __CLKSRC__: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
+ do { \
+ if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
+ { \
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
+ } \
+ else \
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+/* Peripheral Control functions *************************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+__weak void HAL_SYSTICK_Callback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,124 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_crc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRC_H
+#define __STM32F4xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
+
+}HAL_CRC_StateTypeDef;
+
+/**
+ * @brief CRC handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< CRC locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+}CRC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Resets CRC Data Register.
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+
+/* Peripheral Control functions ************************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+
+/* Peripheral State functions **************************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,402 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of CRYP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_H
+#define __STM32F4xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CRYP Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+
+ uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
+ This parameter can be a value of @ref CRYP_Key_Size */
+
+ uint8_t* pKey; /*!< The key used for encryption/decryption */
+
+ uint8_t* pInitVect; /*!< The initialization vector used also as initialization
+ counter in CTR mode */
+
+ uint8_t IVSize; /*!< The size of initialization vector.
+ This parameter (called nonce size in CCM) is used only
+ in AES-128/192/256 encryption/decryption CCM mode */
+
+ uint8_t TagSize; /*!< The size of returned authentication TAG.
+ This parameter is used only in AES-128/192/256
+ encryption/decryption CCM mode */
+
+ uint8_t* Header; /*!< The header used in GCM and CCM modes */
+
+ uint16_t HeaderSize; /*!< The size of header buffer in bytes */
+
+ uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
+ This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
+
+}CRYP_InitTypeDef;
+
+/**
+ * @brief HAL CRYP State structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
+ HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
+ HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
+ HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
+ HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
+
+}HAL_CRYP_STATETypeDef;
+
+/**
+ * @brief HAL CRYP phase structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
+ HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
+ HAL_CRYP_PHASE_FINAL = 0x03 /*!< CRYP peripheral is in final phase
+ This is relevant only with CCM and GCM modes */
+}HAL_PhaseTypeDef;
+
+/**
+ * @brief CRYP handle Structure definition
+ */
+typedef struct
+{
+ CRYP_InitTypeDef Init; /*!< CRYP required parameters */
+
+ uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ __IO uint16_t CrypInCount; /*!< Counter of inputed data */
+
+ __IO uint16_t CrypOutCount; /*!< Counter of outputed data */
+
+ HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
+
+ HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+}CRYP_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CRYP_Key_Size
+ * @{
+ */
+#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
+#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
+#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
+
+#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_256B))
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Data_Type
+ * @{
+ */
+#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
+#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
+
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
+ ((DATATYPE) == CRYP_DATATYPE_16B) || \
+ ((DATATYPE) == CRYP_DATATYPE_8B) || \
+ ((DATATYPE) == CRYP_DATATYPE_1B))
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_AlgoModeDirection
+ * @{
+ */
+#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003C)
+#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004)
+#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000C)
+#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014)
+#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018)
+#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001C)
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024)
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028)
+#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002C)
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030)
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034)
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Interrupt
+ * @{
+ */
+#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI ((uint32_t)CRYP_IMSCR_OUTIM) /*!< Output FIFO Interrupt */
+/**
+ * @}
+ */
+
+
+/** @defgroup CRYP_Flags
+ * @{
+ */
+
+#define CRYP_FLAG_BUSY ((uint32_t)0x00000010) /*!< The CRYP core is currently
+ processing a block of data
+ or a key preparation (for
+ AES decryption). */
+#define CRYP_FLAG_IFEM ((uint32_t)0x00000001) /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF ((uint32_t)0x00000002) /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE ((uint32_t)0x00000004) /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU ((uint32_t)0x00000008) /*!< Output FIFO is Full */
+#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002) /*!< Output FIFO service raw
+ interrupt status */
+#define CRYP_FLAG_INRIS ((uint32_t)0x01000001) /*!< Input FIFO service raw
+ interrupt status */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enable/Disable the CRYP peripheral.
+ * @param None
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE() (CRYP->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE() (CRYP->CR &= ~CRYP_CR_CRYPEN)
+
+/**
+ * @brief Flush the data FIFO.
+ * @param None
+ * @retval None
+ */
+#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)
+
+/**
+ * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
+ * @param MODE: The algorithm mode.
+ * @retval None
+ */
+#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)
+
+
+/** @brief Check whether the specified CRYP flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_IFEM: Input FIFO is empty
+ * @arg CRYP_FLAG_IFNF: Input FIFO is not full
+ * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
+ * @arg CRYP_FLAG_OFFU: Output FIFO is full
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)
+#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+
+/** @brief Check whether the specified CRYP interrupt is set or not.
+ * @param __INTERRUPT__: specifies the interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Enable the CRYP interrupt.
+ * @param __INTERRUPT__: CRYP Interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the CRYP interrupt.
+ * @param __INTERRUPT__: CRYP interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))
+
+/* Include CRYP HAL Extension module */
+#include "stm32f4xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+
+/* DES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using polling **********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* TDES encryption/decryption using interrupt ********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using DMA **************************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* Processing functions ********************************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/* Peripheral State functions **************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+
+/* MSP functions *************************************************************/
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/* CallBack functions ********************************************************/
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,146 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of CRYP HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_EX_H
+#define __STM32F4xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYPEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYPEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CRYPEx_AlgoModeDirection
+ * @{
+ */
+#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004)
+#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008)
+#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000C)
+/**
+ * @}
+ */
+
+/** @defgroup CRYPEx_PhaseConfig
+ * The phases are relevant only to AES-GCM and AES-CCM
+ * @{
+ */
+#define CRYP_PHASE_INIT ((uint32_t)0x00000000)
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Set the phase: Init, header, payload, final.
+ * This is relevant only for GCM and CCM modes.
+ * @param PHASE: The phase.
+ * @retval None
+ */
+#define __HAL_CRYP_SET_PHASE(PHASE) do{CRYP->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+ CRYP->CR |= (uint32_t)(PHASE);\
+ }while(0)
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+
+/* Processing functions ********************************************************/
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+#endif /* STM32F437xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_H
+#define __STM32F4xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+
+}DAC_ChannelConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Error_Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement
+ * @{
+ */
+#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
+ ((FLAG) == DAC_FLAG_DMAUDR2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_IT_definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
+ ((IT) == DAC_IT_DMAUDR2))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Enable the DAC peripheral */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/* Disable the DAC peripheral */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+/* Set DHR12R1 alignment */
+#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
+
+/* Set DHR12R2 alignment */
+#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
+
+/* Set DHR12RD alignment */
+#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
+
+/* Enable the DAC interrupt */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/* Disable the DAC interrupt */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/* Get the selected DAC's flag status */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/* Clear the DAC's flag */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
+
+/* Include DAC HAL Extension module */
+#include "stm32f4xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+/* Peripheral State functions ***************************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,183 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of DAC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_EX_H
+#define __STM32F4xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_wave_generation
+ * @{
+ */
+#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
+ ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
+ ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_wave_generation
+ * @{
+ */
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Extension features functions ***********************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,499 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of DCMI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DCMI_H
+#define __STM32F4xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCMI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DCMI Error source
+ */
+typedef enum
+{
+ DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */
+ DCMI_OVERRUN = 2, /*!< DCMI Overrun */
+
+}DCMI_ErrorTypeDef;
+
+/**
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
+
+}DCMI_CodesInitTypeDef;
+
+/**
+ * @brief DCMI Init structure definition
+ */
+typedef struct
+{
+ uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+ This parameter can be a value of @ref DCMI_Capture_Rate */
+
+ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+
+ DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
+
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+
+}DCMI_InitTypeDef;
+
+
+/**
+ * @brief HAL DCMI State structures definition
+ */
+typedef enum
+{
+ HAL_DCMI_STATE_RESET = 0x00, /*!< DCMI not yet initialized or disabled */
+ HAL_DCMI_STATE_READY = 0x01, /*!< DCMI initialized and ready for use */
+ HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */
+ HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */
+ HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */
+
+}HAL_DCMI_StateTypeDef;
+
+/**
+ * @brief DCMI handle Structure definition
+ */
+typedef struct
+{
+ DCMI_TypeDef *Instance; /*!< DCMI Register base address */
+
+ DCMI_InitTypeDef Init; /*!< DCMI parameters */
+
+ HAL_LockTypeDef Lock; /*!< DCMI locking object */
+
+ __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
+
+ __IO uint32_t XferCount; /*!< DMA transfer counter */
+
+ __IO uint32_t XferSize; /*!< DMA transfer size */
+
+ uint32_t XferTransferNumber; /*!< DMA transfer number */
+
+ uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
+
+ __IO uint32_t ErrorCode; /*!< DCMI Error code */
+
+}DCMI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DCMI_Error_Code
+ * @{
+ */
+#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */
+#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Mode
+ * @{
+ */
+#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
+ into the destination memory through the DMA */
+#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
+ frame and then transfers a single frame through the DMA */
+
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+ ((MODE) == DCMI_MODE_SNAPSHOT))
+/**
+ * @}
+ */
+
+
+/** @defgroup DCMI_Synchronization_Mode
+ * @{
+ */
+#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop)
+ is synchronized with the HSYNC/VSYNC signals */
+#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
+ synchronization codes embedded in the data flow */
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+ ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+/**
+ * @}
+ */
+
+
+/** @defgroup DCMI_PIXCK_Polarity
+ * @{
+ */
+#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+ ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+/**
+ * @}
+ */
+
+
+/** @defgroup DCMI_VSYNC_Polarity
+ * @{
+ */
+#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
+#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+/**
+ * @}
+ */
+
+
+/** @defgroup DCMI_HSYNC_Polarity
+ * @{
+ */
+#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
+#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_MODE_JPEG
+ * @{
+ */
+#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */
+#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+ ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Rate
+ * @{
+ */
+#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
+#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+/**
+ * @}
+ */
+
+
+/** @defgroup DCMI_Extended_Data_Mode
+ * @{
+ */
+#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
+ ((DATA) == DCMI_EXTEND_DATA_10B) || \
+ ((DATA) == DCMI_EXTEND_DATA_12B) || \
+ ((DATA) == DCMI_EXTEND_DATA_14B))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Coordinate
+ * @{
+ */
+#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Height
+ * @{
+ */
+#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_interrupt_sources
+ * @{
+ */
+#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
+#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
+#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
+#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
+#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
+
+#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
+ ((IT) == DCMI_IT_OVF) || \
+ ((IT) == DCMI_IT_ERR) || \
+ ((IT) == DCMI_IT_VSYNC) || \
+ ((IT) == DCMI_IT_LINE))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Flags
+ * @{
+ */
+/**
+ * @brief DCMI SR register
+ */
+#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)
+#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)
+#define DCMI_FLAG_FNE ((uint32_t)0x2004)
+/**
+ * @brief DCMI RISR register
+ */
+#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS)
+#define DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS)
+#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS)
+#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS)
+#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS)
+/**
+ * @brief DCMI MISR register
+ */
+#define DCMI_FLAG_FRAMEMI ((uint32_t)0x1001)
+#define DCMI_FLAG_OVFMI ((uint32_t)0x1002)
+#define DCMI_FLAG_ERRMI ((uint32_t)0x1004)
+#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)
+#define DCMI_FLAG_LINEMI ((uint32_t)0x1010)
+#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
+ ((FLAG) == DCMI_FLAG_VSYNC) || \
+ ((FLAG) == DCMI_FLAG_FNE) || \
+ ((FLAG) == DCMI_FLAG_FRAMERI) || \
+ ((FLAG) == DCMI_FLAG_OVFRI) || \
+ ((FLAG) == DCMI_FLAG_ERRRI) || \
+ ((FLAG) == DCMI_FLAG_VSYNCRI) || \
+ ((FLAG) == DCMI_FLAG_LINERI) || \
+ ((FLAG) == DCMI_FLAG_FRAMEMI) || \
+ ((FLAG) == DCMI_FLAG_OVFMI) || \
+ ((FLAG) == DCMI_FLAG_ERRMI) || \
+ ((FLAG) == DCMI_FLAG_VSYNCMI) || \
+ ((FLAG) == DCMI_FLAG_LINEMI))
+
+#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief Enable the DCMI.
+ * @param __HANDLE__: DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+ * @brief Disable the DCMI.
+ * @param __HANDLE__: DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DCMI pending flags.
+ * @param __HANDLE__: DCMI handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVFRI: Overflow flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @retval The state of FLAG.
+ */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
+ (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+ * @brief Clear the DCMI pending flags.
+ * @param __HANDLE__: DCMI handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVFRI: Overflow flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @retval None
+ */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/**
+ * @brief Enable the specified DCMI interrupts.
+ * @param __HANDLE__: DCMI handle
+ * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DCMI interrupts.
+ * @param __HANDLE__: DCMI handle
+ * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified DCMI interrupt has occurred or not.
+ * @param __HANDLE__: DCMI handle
+ * @param __INTERRUPT__: specifies the DCMI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval The state of INTERRUPT.
+ */
+#define __HAL_DCMI_IT_STATUS(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
+
+/* Peripheral State functions ***************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,125 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_def.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DEF
+#define __STM32F4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef NULL
+ #define NULL (void *) 0
+#endif
+
+#define HAL_MAX_DELAY 0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
+ (__DMA_HANDLE_).Parent = (__HANDLE__); \
+ } while(0)
+
+#if (USE_RTOS == 1)
+ /* Reserved for future use */
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F4xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,695 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_H
+#define __STM32F4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel used for the specified stream.
+ This parameter can be a value of @ref DMA_Channel_selection */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Stream */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
+ This parameter can be a value of @ref DMA_Priority_level */
+
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+ This parameter can be a value of @ref DMA_FIFO_direct_mode
+ @note The Direct mode (FIFO mode disabled) cannot be used if the
+ memory-to-memory data transfer is configured on the selected stream */
+
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */
+
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction.
+ This parameter can be a value of @ref DMA_Memory_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction.
+ This parameter can be a value of @ref DMA_Peripheral_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+
+}DMA_InitTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
+ HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
+ HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
+ HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
+ HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+
+}HAL_DMA_LevelCompleteTypeDef;
+
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+}DMA_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
+#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Channel_selection
+ * @{
+ */
+#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
+
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+ ((CHANNEL) == DMA_CHANNEL_1) || \
+ ((CHANNEL) == DMA_CHANNEL_2) || \
+ ((CHANNEL) == DMA_CHANNEL_3) || \
+ ((CHANNEL) == DMA_CHANNEL_4) || \
+ ((CHANNEL) == DMA_CHANNEL_5) || \
+ ((CHANNEL) == DMA_CHANNEL_6) || \
+ ((CHANNEL) == DMA_CHANNEL_7))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_buffer_size
+ * @{
+ */
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_Memory_data_size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR) || \
+ ((MODE) == DMA_PFCTRL))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_direct_mode
+ * @{
+ */
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == DMA_FIFOMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_threshold_level
+ * @{
+ */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_burst
+ * @{
+ */
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+ ((BURST) == DMA_MBURST_INC4) || \
+ ((BURST) == DMA_MBURST_INC8) || \
+ ((BURST) == DMA_MBURST_INC16))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_burst
+ * @{
+ */
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+ ((BURST) == DMA_PBURST_INC4) || \
+ ((BURST) == DMA_PBURST_INC8) || \
+ ((BURST) == DMA_PBURST_INC16))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupt_enable_definitions
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE ((uint32_t)0x00000080)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions
+ * @{
+ */
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief Return the current DMA Stream FIFO filled level.
+ * @param __HANDLE__: DMA handle
+ * @retval The FIFO filling state.
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+ * and not empty.
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+ * - DMA_FIFOStatus_Empty: when FIFO is empty
+ * - DMA_FIFOStatus_Full: when FIFO is full
+ */
+#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
+
+/**
+ * @brief Enable the specified DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
+
+/**
+ * @brief Disable the specified DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Return the current DMA Stream transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ DMA_FLAG_TCIF3_7)
+
+/**
+ * @brief Return the current DMA Stream half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ DMA_FLAG_HTIF3_7)
+
+/**
+ * @brief Return the current DMA Stream transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ DMA_FLAG_TEIF3_7)
+
+/**
+ * @brief Return the current DMA Stream FIFO error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified FIFO error flag index.
+ */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ DMA_FLAG_FEIF3_7)
+
+/**
+ * @brief Return the current DMA Stream direct mode error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified direct mode error flag index.
+ */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ DMA_FLAG_DMEIF3_7)
+
+/**
+ * @brief Get the DMA Stream pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+ * @brief Clear the DMA Stream pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__)))
+
+/**
+ * @brief Enable the specified DMA Stream interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the specified DMA Stream interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Check whether the specified DMA Stream interrupt has occurred or not.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval The state of DMA_IT.
+ */
+#define __HAL_DMA_IT_STATUS(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+ ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
+ ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
+
+/**
+ * @brief Writes the number of data units to be transferred on the DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+ * Number of data items depends only on the Peripheral data format.
+ *
+ * @note If Peripheral data format is Bytes: number of data units is equal
+ * to total number of bytes to be transferred.
+ *
+ * @note If Peripheral data format is Half-Word: number of data units is
+ * equal to total number of bytes to be transferred / 2.
+ *
+ * @note If Peripheral data format is Word: number of data units is equal
+ * to total number of bytes to be transferred / 4.
+ *
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.
+ */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
+ * @param __HANDLE__: DMA handle
+ *
+ * @retval The number of remaining data units in the current DMA Stream transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
+
+
+/* Include DMA HAL Extension module */
+#include "stm32f4xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,501 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma2d.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of DMA2D HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA2D_H
+#define __STM32F4xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA2D
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define MAX_DMA2D_LAYER 2
+
+/**
+ * @brief DMA2D color Structure definition
+ */
+typedef struct
+{
+ uint32_t Blue; /*!< Configures the blue value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Green; /*!< Configures the green value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Red; /*!< Configures the red value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+} DMA2D_ColorTypeDef;
+
+/**
+ * @brief DMA2D CLUT Structure definition
+ */
+typedef struct
+{
+ uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address. */
+
+ uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
+ This parameter can be one value of @ref DMA2D_CLUT_CM */
+
+ uint32_t Size; /*!< configures the DMA2D CLUT size.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+} DMA2D_CLUTCfgTypeDef;
+
+/**
+ * @brief DMA2D Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< configures the DMA2D transfer mode.
+ This parameter can be one value of @ref DMA2D_Mode */
+
+ uint32_t ColorMode; /*!< configures the color format of the output image.
+ This parameter can be one value of @ref DMA2D_Color_Mode */
+
+ uint32_t OutputOffset; /*!< Specifies the Offset value.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+} DMA2D_InitTypeDef;
+
+/**
+ * @brief DMA2D Layer structure definition
+ */
+typedef struct
+{
+
+
+ uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+ uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
+ This parameter can be one value of @ref DMA2D_Input_Color_Mode */
+
+ uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
+ This parameter can be one value of @ref DMA2D_ALPHA_MODE */
+
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+} DMA2D_LayerCfgTypeDef;
+
+/**
+ * @brief HAL DMA2D State structures definition
+ */
+typedef enum
+{
+ HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
+ HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
+ HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
+
+}HAL_DMA2D_StateTypeDef;
+
+/**
+ * @brief DMA2D handle Structure definition
+ */
+typedef struct __DMA2D_HandleTypeDef
+{
+ DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
+
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
+
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
+
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
+
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA2D Lock */
+
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
+
+ __IO uint32_t ErrorCode; /*!< DMA2D Error code */
+
+} DMA2D_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA2D_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_Layer
+ * @{
+ */
+#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Error_Code
+ * @{
+ */
+#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
+#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
+#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Mode
+ * @{
+ */
+#define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
+
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Color_Mode
+ * @{
+ */
+#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
+#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
+#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
+
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
+ ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
+ ((MODE_ARGB) == DMA2D_ARGB4444))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_COLOR_VALUE
+ * @{
+ */
+
+#define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
+
+#define IS_DMA2D_ALPHA_VALUE(ALPHA_VALUE) ((ALPHA_VALUE) <= COLOR_VALUE)
+#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_SIZE
+ * @{
+ */
+#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
+#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
+
+#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_OFFSET
+ * @{
+ */
+#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
+
+#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Input_Color_Mode
+ * @{
+ */
+#define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
+#define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
+#define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
+#define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
+#define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
+#define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
+#define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
+#define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
+#define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
+#define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
+#define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
+
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
+ ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
+ ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
+ ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
+ ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
+ ((INPUT_CM) == CM_A4))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_ALPHA_MODE
+ * @{
+ */
+#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
+ with original alpha channel value */
+
+#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
+ ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_CLUT_CM
+ * @{
+ */
+#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
+#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_CLUT_SIZE
+ * @{
+ */
+#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
+
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_DeadTime
+ * @{
+ */
+#define LINE_WATERMARK DMA2D_LWR_LW
+
+#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Interrupts
+ * @{
+ */
+#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
+#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
+
+#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Flag
+ * @{
+ */
+#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
+
+#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief Enable the DMA2D.
+ * @param __HANDLE__: DMA2D handle
+ * @retval None.
+ */
+#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+/**
+ * @brief Disable the DMA2D.
+ * @param __HANDLE__: DMA2D handle
+ * @retval None.
+ */
+#define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DMA2D pending flags.
+ * @param __HANDLE__: DMA2D handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: C-LUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval The state of FLAG.
+ */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA2D pending flags.
+ * @param __HANDLE__: DMA2D handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: C-LUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval None
+ */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR |= (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA2D interrupts.
+ * @param __HANDLE__: DMA2D handle
+ * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified DMA2D interrupts.
+ * @param __HANDLE__: DMA2D handle
+ * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified DMA2D interrupt has occurred or not.
+ * @param __HANDLE__: DMA2D handle
+ * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval The state of INTERRUPT.
+ */
+#define __HAL_DMA2D_IT_STATUS(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+#endif /* STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA2D_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,92 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_EX_H
+#define __STM32F4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL DMA Memory definition
+ */
+typedef enum
+{
+ MEMORY0 = 0x00, /*!< Memory 0 */
+ MEMORY1 = 0x01, /*!< Memory 1 */
+
+}HAL_DMA_MemoryTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,2186 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_eth.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of ETH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_ETH_H
+#define __STM32F4xx_HAL_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ETH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
+ HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
+ HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
+ HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_ETH_StateTypeDef;
+
+/**
+ * @brief ETH Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+ and the mode (half/full-duplex).
+ This parameter can be a value of @ref ETH_AutoNegotiation */
+
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
+ This parameter can be a value of @ref ETH_Speed */
+
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref ETH_Duplex_Mode */
+
+ uint16_t PhyAddress; /*!< Ethernet PHY address
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode
+ This parameter can be a value of @ref ETH_Rx_Mode */
+
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software
+ This parameter can be a value of @ref ETH_Checksum_Mode */
+
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface
+ This parameter can be a value of @ref ETH_Media_Interface */
+
+} ETH_InitTypeDef;
+
+
+ /**
+ * @brief ETH MAC Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes.
+ This parameter can be a value of @ref ETH_watchdog */
+
+ uint32_t Jabber; /*!< Selects or not Jabber timer
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Jabber */
+
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense
+ This parameter can be a value of @ref ETH_Carrier_Sense */
+
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+ in Half-Duplex mode
+ This parameter can be a value of @ref ETH_Receive_Own */
+
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
+
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+ This parameter can be a value of @ref ETH_Checksum_Offload */
+
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+ when a collision occurs (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Retry_Transmission */
+
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Deferral_Check */
+
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering)
+ This parameter can be a value of @ref ETH_Receive_All */
+
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
+
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
+
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
+ automatic retransmission of PAUSE Frame
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+ unicast address and unique multicast address)
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
+ disable its transmitter for a specified time (Pause Time)
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+ or the MAC back-pressure operation (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+ comparison and filtering
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
+
+} ETH_MACInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
+
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
+
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes) including pad-bytes and CRC)
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining the status for the first frame.
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
+ This parameter can be a value of @ref ETH_Fixed_Burst */
+
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
+
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
+} ETH_DMAInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Descriptors data structure definition
+ */
+
+typedef struct
+{
+ __IO uint32_t Status; /*!< Status */
+
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
+
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
+
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
+
+ /*!< Enhanced ETHERNET DMA PTP Descriptors */
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
+
+ uint32_t Reserved1; /*!< Reserved */
+
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
+
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
+
+} ETH_DMADescTypeDef;
+
+
+/**
+ * @brief Received Frame Informations structure definition
+ */
+typedef struct
+{
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
+
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
+
+ uint32_t SegCount; /*!< Segment count */
+
+ uint32_t length; /*!< Frame length */
+
+ uint32_t buffer; /*!< Frame buffer */
+
+} ETH_DMARxFrameInfos;
+
+
+/**
+ * @brief ETH Handle Structure definition
+ */
+
+typedef struct
+{
+ ETH_TypeDef *Instance; /*!< Register base address */
+
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
+
+ uint32_t LinkStatus; /*!< Ethernet link status */
+
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
+
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
+
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
+
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
+
+ HAL_LockTypeDef Lock; /*!< ETH Lock */
+
+} ETH_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+
+
+/* ETHERNET Errors */
+#define ETH_SUCCESS ((uint32_t)0)
+#define ETH_ERROR ((uint32_t)1)
+
+/** @defgroup ETH_Buffers_setting
+ * @{
+ */
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
+#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
+#define VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
+
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+ to the driver receive buffers memory.
+
+ Depending on the size of the received ethernet packet and the size of
+ each ethernet driver receive buffer, the received packet can take one or more
+ ethernet driver receive buffer.
+
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+ and the total count of the driver receive buffers ETH_RXBUFNB.
+
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_RX_BUF_SIZE
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
+#ifndef ETH_RXBUFNB
+ #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#endif
+
+
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+ driver transmit buffers memory to the TxFIFO.
+
+ Depending on the size of the Ethernet packet to be transmitted and the size of
+ each ethernet driver transmit buffer, the packet to be transmitted can take
+ one or more ethernet driver transmit buffer.
+
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+ and the total count of the driver transmit buffers ETH_TXBUFNB.
+
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_TX_BUF_SIZE
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
+#ifndef ETH_TXBUFNB
+ #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+#endif
+
+
+/*
+ DMA Tx Desciptor
+ -----------------------------------------------------------------------------------------------
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Buffer1 Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
+ */
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
+
+/**
+ * @brief Bit definition of TDES1 register
+ */
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
+
+/**
+ * @brief Bit definition of TDES2 register
+ */
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of TDES3 register
+ */
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+ /*---------------------------------------------------------------------------------------------
+ TDES6 | Transmit Time Stamp Low [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES7 | Transmit Time Stamp High [31:0] |
+ ----------------------------------------------------------------------------------------------*/
+
+/* Bit definition of TDES6 register */
+ #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
+
+/* Bit definition of TDES7 register */
+ #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_Rx_descriptor
+ * @{
+ */
+
+/*
+ DMA Rx Descriptor
+ --------------------------------------------------------------------------------------------------------------------
+ RDES0 | OWN(31) | Status [30:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | Buffer1 Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
+ */
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
+ * @brief Bit definition of RDES1 register
+ */
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
+
+/**
+ * @brief Bit definition of RDES2 register
+ */
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of RDES3 register
+ */
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+/*---------------------------------------------------------------------------------------------------------------------
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES5 | Reserved[31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES6 | Receive Time Stamp Low [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES7 | Receive Time Stamp High [31:0] |
+ --------------------------------------------------------------------------------------------------------------------*/
+
+/* Bit definition of RDES4 register */
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
+ #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
+
+/* Bit definition of RDES6 register */
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
+
+/* Bit definition of RDES7 register */
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
+
+
+ /** @defgroup ETH_AutoNegotiation
+ * @{
+ */
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup ETH_Speed
+ * @{
+ */
+#define ETH_SPEED_10M ((uint32_t)0x00000000)
+#define ETH_SPEED_100M ((uint32_t)0x00004000)
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M))
+/**
+ * @}
+ */
+/** @defgroup ETH_Duplex_Mode
+ * @{
+ */
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+/**
+ * @}
+ */
+/** @defgroup ETH_Rx_Mode
+ * @{
+ */
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Mode
+ * @{
+ */
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Media_Interface
+ * @{
+ */
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_watchdog
+ * @{
+ */
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+ ((CMD) == ETH_WATCHDOG_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Jabber
+ * @{
+ */
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+ ((CMD) == ETH_JABBER_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Frame_Gap
+ * @{
+ */
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Carrier_Sense
+ * @{
+ */
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Own
+ * @{
+ */
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Loop_Back_Mode
+ * @{
+ */
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Offload
+ * @{
+ */
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Retry_Transmission
+ * @{
+ */
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip
+ * @{
+ */
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit
+ * @{
+ */
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Deferral_Check
+ * @{
+ */
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_All
+ * @{
+ */
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEAll_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Filter
+ * @{
+ */
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pass_Control_Frames
+ * @{
+ */
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Broadcast_Frames_Reception
+ * @{
+ */
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Destination_Addr_Filter
+ * @{
+ */
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Promiscuous_Mode
+ * @{
+ */
+#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
+#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) || \
+ ((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Multicast_Frames_Filter
+ * @{
+ */
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Frames_Filter
+ * @{
+ */
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Time
+ * @{
+ */
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Zero_Quanta_Pause
+ * @{
+ */
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect
+ * @{
+ */
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Flow_Control
+ * @{
+ */
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Flow_Control
+ * @{
+ */
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison
+ * @{
+ */
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses
+ * @{
+ */
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
+ * @{
+ */
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
+ * @{
+ */
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Debug_flags
+ * @{
+ */
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
+
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
+
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
+
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
+
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
+
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
+
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
+
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
+
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
+
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
+
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
+ * @{
+ */
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Store_Forward
+ * @{
+ */
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Flush_Received_Frame
+ * @{
+ */
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Store_Forward
+ * @{
+ */
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Threshold_Control
+ * @{
+ */
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Error_Frames
+ * @{
+ */
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames
+ * @{
+ */
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Threshold_Control
+ * @{
+ */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Second_Frame_Operate
+ * @{
+ */
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Address_Aligned_Beats
+ * @{
+ */
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Fixed_Burst
+ * @{
+ */
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+ ((CMD) == ETH_FIXEDBURST_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length
+ * @{
+ */
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length
+ * @{
+ */
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+
+/**
+ * @brief ETH_DMA_Enhanced_descriptor_format
+ */
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
+
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
+
+/**
+ * @}
+ */
+
+/**
+ * @brief ETH DMA Descriptor SkipLength
+ */
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+
+/** @defgroup ETH_DMA_Arbitration
+ * @{
+ */
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_flags
+ * @{
+ */
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment
+ * @{
+ */
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+ * @{
+ */
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+/**
+ * @brief ETH DMA Tx Desciptor buffer size
+ */
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_flags
+ * @{
+ */
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
+
+/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
+#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_PTPFT) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_PTPMT) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPCB) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPPE) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPHE) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPPT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_
+ * @{
+ */
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PMT_Flags
+ * @{
+ */
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Tx_Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Rx_Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+ ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Registers
+ * @{
+ */
+#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
+#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
+#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
+#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
+#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
+#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
+#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
+#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
+
+/**
+ * @brief ETH MMC registers
+ */
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
+ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
+ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+ ((REG) == ETH_MMCRGUFCR))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Flags
+ * @{
+ */
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Flags
+ * @{
+ */
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts
+ * @{
+ */
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts
+ * @{
+ */
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_transmit_process_state_
+ * @{
+ */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_receive_process_state_
+ * @{
+ */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_overflow_
+ * @{
+ */
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+/**
+ * @}
+ */
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
+
+/**
+ * @brief Disables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
+
+/**
+ * @brief Set the specified DMA Rx Desc Own bit.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
+
+/**
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
+ * @param __HANDLE__: ETH Handle
+ * @retval The Transmit descriptor collision counter value.
+ */
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
+
+/**
+ * @brief Set the specified DMA Tx Desc Own bit.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
+
+/**
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
+
+/**
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
+
+/**
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+ * @param __HANDLE__: ETH Handle
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
+
+/**
+ * @brief Enables the DMA Tx Desc CRC.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
+
+/**
+ * @brief Disables the DMA Tx Desc CRC.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
+
+/**
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
+
+/**
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
+
+/**
+ * @brief Enables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Initiate a Pause Control Frame (Full-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @retval The new state of flow control busy status bit (SET or RESET).
+ */
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval The state of ETHERNET MAC flag.
+ */
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Clears the specified ETHERNET MAC flag.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval None.
+ */
+#define __HAL_ETH_MAC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACSR &= ~(__FLAG__))
+
+/**
+ * @brief Enables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * enabled @defgroup ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * disabled. @defgroup ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Clears the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_CLEAR_IT_PENDING_BIT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+* @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR &= ~(__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
+ * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
+
+/**
+ * @brief Set the DMA Receive status watchdog timer register value
+ * @param __HANDLE__: ETH Handle
+ * @param __VALUE__: DMA Receive status watchdog timer register value
+ * @retval None
+ */
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
+
+/**
+ * @brief Enables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Disables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Enables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Disables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Magic Packet Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
+
+/**
+ * @brief Disables the MAC Magic Packet Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Power Down.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Disables the MAC Power Down.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.
+ * @param __HANDLE__: ETH Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+
+/**
+ * @brief Enables the MMC Counter Freeze.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
+
+/**
+ * @brief Disables the MMC Counter Freeze.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
+
+/**
+ * @brief Enables the MMC Reset On Read.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
+
+/**
+ * @brief Disables the MMC Reset On Read.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
+
+/**
+ * @brief Enables the MMC Counter Stop Rollover.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
+
+/**
+ * @brief Disables the MMC Counter Stop Rollover.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
+
+/**
+ * @brief Resets the MMC Counters.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
+
+/**
+ * @brief Enables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+ * @brief Disables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+ * @brief Enables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+
+ /* Callback in non blocking modes (Interrupt) */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+
+/* Cmmunication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+
+/* Peripheral State functions ************************************************/
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_ETH_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,362 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of FLASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_H
+#define __STM32F4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief FLASH Error structure definition
+ */
+typedef enum
+{
+ FLASH_ERROR_RD = 0x01,
+ FLASH_ERROR_PGS = 0x02,
+ FLASH_ERROR_PGP = 0x04,
+ FLASH_ERROR_PGA = 0x08,
+ FLASH_ERROR_WRP = 0x10,
+ FLASH_ERROR_OPERATION = 0x20
+}FLASH_ErrorTypeDef;
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_SECTERASE,
+ FLASH_PROC_MASSERASE,
+ FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
+
+ __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
+
+ __IO uint8_t VoltageForErase; /*Internal variable to provide voltange range selected by user in IT context*/
+
+ __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
+
+ __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
+
+ __IO uint32_t Address; /*Internal variable to save address selected for program*/
+
+ HAL_LockTypeDef Lock; /* FLASH locking object */
+
+ __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
+
+}FLASH_ProcessTypeDef;
+
+/**
+ * @brief FLASH Error source
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */
+#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */
+#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */
+#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */
+
+#define IS_TYPEPROGRAM(VALUE)(((VALUE) == TYPEPROGRAM_BYTE) || \
+ ((VALUE) == TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == TYPEPROGRAM_WORD) || \
+ ((VALUE) == TYPEPROGRAM_DOUBLEWORD))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+ * @brief Flag definition
+ * @{
+ */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
+#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
+#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
+#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+ * @{
+ */
+#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
+#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
+#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
+#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
+#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Keys FLASH Keys
+ * @{
+ */
+#define RDP_KEY ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
+#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
+/**
+ * @}
+ */
+
+/**
+ * @brief ACR register byte 0 (Bits[7:0]) base address
+ */
+#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+/**
+ * @brief OPTCR register byte 0 (Bits[7:0]) base address
+ */
+#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
+/**
+ * @brief OPTCR register byte 1 (Bits[15:8]) base address
+ */
+#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
+/**
+ * @brief OPTCR register byte 2 (Bits[23:16]) base address
+ */
+#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
+/**
+ * @brief OPTCR register byte 3 (Bits[31:24]) base address
+ */
+#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__: FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @retval none
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+ * @brief Enable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
+
+/**
+ * @brief Disable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
+
+/**
+ * @brief Enable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
+
+/**
+ * @brief Disable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
+
+/**
+ * @brief Resets the FLASH instruction Cache.
+ * @note This function must be used only when the Instruction Cache is disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_ICRST)
+
+/**
+ * @brief Resets the FLASH data Cache.
+ * @note This function must be used only when the data Cache is disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_DATA_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_DCRST)
+
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+
+/* Include FLASH HAL Extension module */
+#include "stm32f4xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Program operation functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/* Peripheral State functions ************************************************/
+FLASH_ErrorTypeDef HAL_FLASH_GetError(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,736 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of FLASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_EX_H
+#define __STM32F4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t Banks; /*!< Banks: Select banks to erase when Mass erase is enabled
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t Sector; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled
+ This parameter must be a value of @ref FLASHEx_Sectors */
+
+ uint32_t NbSectors; /*!< NbSectors: Number of sectors to be erased.
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+ uint32_t VoltageRange;/*!< VoltageRange: The device voltage range which defines the erase parallelism
+ This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Option Bytes Program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_Option_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_WRP_State */
+
+ uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected
+ The value of this parameter depend on device used within the same series */
+
+ uint32_t Banks; /*!< Banks: Select banks for WRP activation/deactivation of all sectors
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+ uint32_t BORLevel; /*!< BORLevel: Set the BOR Level.
+ This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @brief FLASH Advanced Option Bytes Program structure definition
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
+ This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
+
+ uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_PCROP_State */
+
+#if defined (STM32F401xC) || defined (STM32F401xE)
+ uint16_t Sectors; /*!< Sectors: specifies the sector(s) set for PCROP
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+#endif /* STM32F401xC || STM32F401xE */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ uint32_t Banks; /*!< Banks: Select banks for PCROP activation/deactivation of all sectors
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint16_t SectorsBank1; /*!< SectorsBank1: specifies the sector(s) set for PCROP for Bank1
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+ uint16_t SectorsBank2; /*!< SectorsBank2: specifies the sector(s) set for PCROP for Bank2
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+ uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
+ This parameter can be a value of @ref FLASHEx_Dual_Boot */
+
+#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+} FLASH_AdvOBProgramInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
+#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
+
+#define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \
+ ((VALUE) == TYPEERASE_MASSERASE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+ * @{
+ */
+#define VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
+#define VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
+#define VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
+#define VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \
+ ((RANGE) == VOLTAGE_RANGE_2) || \
+ ((RANGE) == VOLTAGE_RANGE_3) || \
+ ((RANGE) == VOLTAGE_RANGE_4))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+ * @{
+ */
+#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
+#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \
+ ((VALUE) == WRPSTATE_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+ * @{
+ */
+#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
+#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
+#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
+/*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
+ it s no more possible to go back to level 1 or 0 */
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+ ((LEVEL) == OB_RDP_LEVEL_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+ * @{
+ */
+#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+/**
+ * @}
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
+ * @{
+ */
+#define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable PCROP */
+#define PCROPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable PCROP */
+
+#define IS_PCROPSTATE(VALUE)(((VALUE) == PCROPSTATE_DISABLE) || \
+ ((VALUE) == PCROPSTATE_ENABLE))
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define OBEX_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */
+#define OBEX_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */
+
+#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP) || \
+ ((VALUE) == OBEX_BOOTCONFIG))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#define OBEX_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */
+
+#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP))
+
+#endif /* STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
+#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
+#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
+#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7) || \
+ ((LATENCY) == FLASH_LATENCY_8) || \
+ ((LATENCY) == FLASH_LATENCY_9) || \
+ ((LATENCY) == FLASH_LATENCY_10) || \
+ ((LATENCY) == FLASH_LATENCY_11) || \
+ ((LATENCY) == FLASH_LATENCY_12) || \
+ ((LATENCY) == FLASH_LATENCY_13) || \
+ ((LATENCY) == FLASH_LATENCY_14) || \
+ ((LATENCY) == FLASH_LATENCY_15))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
+#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Sectors FLASH Sectors
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
+#define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */
+#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
+#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
+#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
+#define FLASH_SECTOR_12 ((uint32_t)12) /*!< Sector Number 12 */
+#define FLASH_SECTOR_13 ((uint32_t)13) /*!< Sector Number 13 */
+#define FLASH_SECTOR_14 ((uint32_t)14) /*!< Sector Number 14 */
+#define FLASH_SECTOR_15 ((uint32_t)15) /*!< Sector Number 15 */
+#define FLASH_SECTOR_16 ((uint32_t)16) /*!< Sector Number 16 */
+#define FLASH_SECTOR_17 ((uint32_t)17) /*!< Sector Number 17 */
+#define FLASH_SECTOR_18 ((uint32_t)18) /*!< Sector Number 18 */
+#define FLASH_SECTOR_19 ((uint32_t)19) /*!< Sector Number 19 */
+#define FLASH_SECTOR_20 ((uint32_t)20) /*!< Sector Number 20 */
+#define FLASH_SECTOR_21 ((uint32_t)21) /*!< Sector Number 21 */
+#define FLASH_SECTOR_22 ((uint32_t)22) /*!< Sector Number 22 */
+#define FLASH_SECTOR_23 ((uint32_t)23) /*!< Sector Number 23 */
+
+#define FLASH_SECTOR_TOTAL 24
+
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
+ ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
+ ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
+ ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
+ ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
+ ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
+ ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
+#define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */
+#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
+#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
+#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
+
+#define FLASH_SECTOR_TOTAL 12
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+
+#define FLASH_SECTOR_TOTAL 6
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
+
+#define FLASH_SECTOR_TOTAL 8
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F401xE */
+
+#define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_12 ((uint32_t)0x00000001 << 12) /*!< Write protection of Sector12 */
+#define OB_WRP_SECTOR_13 ((uint32_t)0x00000002 << 12) /*!< Write protection of Sector13 */
+#define OB_WRP_SECTOR_14 ((uint32_t)0x00000004 << 12) /*!< Write protection of Sector14 */
+#define OB_WRP_SECTOR_15 ((uint32_t)0x00000008 << 12) /*!< Write protection of Sector15 */
+#define OB_WRP_SECTOR_16 ((uint32_t)0x00000010 << 12) /*!< Write protection of Sector16 */
+#define OB_WRP_SECTOR_17 ((uint32_t)0x00000020 << 12) /*!< Write protection of Sector17 */
+#define OB_WRP_SECTOR_18 ((uint32_t)0x00000040 << 12) /*!< Write protection of Sector18 */
+#define OB_WRP_SECTOR_19 ((uint32_t)0x00000080 << 12) /*!< Write protection of Sector19 */
+#define OB_WRP_SECTOR_20 ((uint32_t)0x00000100 << 12) /*!< Write protection of Sector20 */
+#define OB_WRP_SECTOR_21 ((uint32_t)0x00000200 << 12) /*!< Write protection of Sector21 */
+#define OB_WRP_SECTOR_22 ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22 */
+#define OB_WRP_SECTOR_23 ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
+#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
+#define OB_PCROP_SECTOR_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
+#define OB_PCROP_SECTOR_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
+#define OB_PCROP_SECTOR_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
+#define OB_PCROP_SECTOR_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
+#define OB_PCROP_SECTOR_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
+#define OB_PCROP_SECTOR_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
+#define OB_PCROP_SECTOR_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
+#define OB_PCROP_SECTOR_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
+#define OB_PCROP_SECTOR_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
+#define OB_PCROP_SECTOR_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
+#define OB_PCROP_SECTOR_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
+#define OB_PCROP_SECTOR_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
+#define OB_PCROP_SECTOR_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
+#define OB_PCROP_SECTOR_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
+#define OB_PCROP_SECTOR_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
+#define OB_PCROP_SECTOR_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
+#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F401xC)
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
+#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
+#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
+#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/**
+ * @brief OPTCR1 register byte 2 (Bits[23:16]) base address
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Extension Program operation functions *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,277 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_gpio.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_H
+#define __STM32F4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode_define */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed_define */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIO_Alternat_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint32_t)0x00) == 0x00) && ((PIN) != (uint32_t)0x00))
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_0) || \
+ ((PIN) == GPIO_PIN_1) || \
+ ((PIN) == GPIO_PIN_2) || \
+ ((PIN) == GPIO_PIN_3) || \
+ ((PIN) == GPIO_PIN_4) || \
+ ((PIN) == GPIO_PIN_5) || \
+ ((PIN) == GPIO_PIN_6) || \
+ ((PIN) == GPIO_PIN_7) || \
+ ((PIN) == GPIO_PIN_8) || \
+ ((PIN) == GPIO_PIN_9) || \
+ ((PIN) == GPIO_PIN_10) || \
+ ((PIN) == GPIO_PIN_11) || \
+ ((PIN) == GPIO_PIN_12) || \
+ ((PIN) == GPIO_PIN_13) || \
+ ((PIN) == GPIO_PIN_14) || \
+ ((PIN) == GPIO_PIN_15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode_define
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed_define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
+#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
+#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */
+#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
+/**
+ * @}
+ */
+
+ /** @defgroup GPIO_pull_define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
+#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.
+ * This parameter can be EXTI_Linex where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be EXTI_Linex where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/* Include GPIO HAL Extension module */
+#include "stm32f4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/* IO operation functions *******************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,712 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_EX_H
+#define __STM32F4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_Alternat_function_selection
+ * @{
+ */
+
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+#if defined (STM32F429xx) || defined (STM32F439xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF14_LTDC))
+
+#endif /* STM32F429xx || STM32F439xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/
+#if defined (STM32F427xx) || defined (STM32F437xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1))
+
+#endif /* STM32F427xx || STM32F437xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/
+#if defined (STM32F407xx) || defined (STM32F417xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F407xx || STM32F417xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/
+#if defined (STM32F405xx) || defined (STM32F415xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F405xx || STM32F415xx */
+
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx--------------------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
+ ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,329 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of HASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_H
+#define __STM32F4xx_HAL_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HASH Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref HASH_Data_Type */
+
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation */
+
+ uint8_t* pKey; /*!< The key is used only in HMAC operation */
+
+}HASH_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */
+ HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
+ HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */
+ HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */
+
+}HAL_HASH_STATETypeDef;
+
+/**
+ * @brief HAL phase structures definition
+ */
+typedef enum
+{
+ HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */
+ HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */
+
+}HAL_HASHPhaseTypeDef;
+
+/**
+ * @brief HASH Handle Structure definition
+ */
+typedef struct
+{
+ HASH_InitTypeDef Init; /*!< HASH required parameters */
+
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
+
+ __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+
+ __IO uint32_t HashInCount; /*!< Counter of inputed data */
+
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
+
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */
+
+ HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< HASH locking object */
+
+ __IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */
+
+} HASH_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HASH_Algo_Selection
+ * @{
+ */
+#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
+#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
+#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
+#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+
+#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
+ ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
+ ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
+ ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Algorithm_Mode
+ * @{
+ */
+#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
+#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
+
+#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
+ ((ALGOMODE) == HASH_AlgoMode_HMAC))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Data_Type
+ * @{
+ */
+#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
+#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
+#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
+#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
+
+#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DATATYPE_32B)|| \
+ ((DATATYPE) == HASH_DATATYPE_16B)|| \
+ ((DATATYPE) == HASH_DATATYPE_8B) || \
+ ((DATATYPE) == HASH_DATATYPE_1B))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
+ * @{
+ */
+#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
+
+#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
+ ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_flags_definition
+ * @{
+ */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_interrupts_definition
+ * @{
+ */
+#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Check whether the specified HASH flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
+ * @arg HASH_FLAG_DCIS: Digest calculation complete
+ * @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
+ * @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
+ * @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Macros for HMAC finish.
+ * @param None
+ * @retval None
+ */
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/**
+ * @brief Enable the multiple DMA mode.
+ * This feature is available only in STM32F429x and STM32F439x devices.
+ * @param None
+ * @retval None
+ */
+#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
+
+/**
+ * @brief Disable the multiple DMA mode.
+ * @param None
+ * @retval None
+ */
+#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
+
+/**
+ * @brief Start the digest computation
+ * @param None
+ * @retval None
+ */
+#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
+
+/**
+ * @brief Set the number of valid bits in last word written in Data register
+ * @param SIZE: size in byte of last data written in Data register.
+ * @retval None
+*/
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
+ HASH->STR |= 8 * ((SIZE) % 4);\
+ }while(0)
+
+/* Include HASH HAL Extension module */
+#include "stm32f4xx_hal_hash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+
+/* HASH processing using polling *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* HASH-MAC processing using polling *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH processing using interrupt *******************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/* HASH processing using DMA *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH-HMAC processing using DMA ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* Processing functions ******************************************************/
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+
+/* Peripheral State functions ************************************************/
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_HASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,105 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of HASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_EX_H
+#define __STM32F4xx_HAL_HASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* HASH processing using polling *********************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* HASH-MAC processing using polling *****************************************/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH processing using interrupt *******************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/* HASH processing using DMA *************************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH-HMAC processing using DMA ********************************************/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* Processing functions ******************************************************/
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
+
+#endif /* STM32F437xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,226 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hcd.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of HCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HCD_H
+#define __STM32F4xx_HAL_HCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+ /**
+ * @brief HCD Status structures structure definition
+ */
+typedef enum
+{
+ HCD_READY = 0x00,
+ HCD_ERROR = 0x01,
+ HCD_BUSY = 0x02,
+ HCD_TIMEOUT = 0x03
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
+typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
+
+/**
+ * @brief HCD Handle Structure definition
+ */
+typedef struct
+{
+ HCD_TypeDef *Instance; /*!< Register base address */
+ HCD_InitTypeDef Init; /*!< HCD required parameters */
+ HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
+ HAL_LockTypeDef Lock; /*!< HCD peripheral status */
+ __IO HCD_StateTypeDef State; /*!< HCD communication state */
+ void *pData; /*!< Pointer Stack Handler */
+
+} HCD_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HCD_Instance_definition
+ * @{
+ */
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Speed
+ * @{
+ */
+#define HCD_SPEED_HIGH 0
+#define HCD_SPEED_FULL 1
+#define HCD_SPEED_LOW 2
+/**
+ * @}
+ */
+
+ /** @defgroup HCD_PHY_Module
+ * @{
+ */
+#define HCD_PHY_ULPI 1
+#define HCD_PHY_EMBEDDED 2
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup HCD_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num);
+
+__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t pipe,
+ uint8_t direction ,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping);
+
+ /* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+
+/* Peripheral State functions **************************************************/
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,454 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_H
+#define __STM32F4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief I2C Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
+ HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */
+ HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */
+
+}HAL_I2C_StateTypeDef;
+
+/**
+ * @brief HAL I2C Error Code structure definition
+ */
+typedef enum
+{
+ HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
+ HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
+ HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
+ HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
+ HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
+ HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
+ HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */
+
+}HAL_I2C_ErrorTypeDef;
+
+/**
+ * @brief I2C handle Structure definition
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
+
+}I2C_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
+
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+ ((CYCLE) == I2C_DUTYCYCLE_16_9))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_addressing_mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
+
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
+ ((CALL) == I2C_GENERALCALL_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition
+ * @{
+ */
+#define I2C_IT_BUF I2C_CR2_ITBUFEN
+#define I2C_IT_EVT I2C_CR2_ITEVTEN
+#define I2C_IT_ERR I2C_CR2_ITERREN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition
+ * @{
+ */
+#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000)
+#define I2C_FLAG_PECERR ((uint32_t)0x00011000)
+#define I2C_FLAG_OVR ((uint32_t)0x00010800)
+#define I2C_FLAG_AF ((uint32_t)0x00010400)
+#define I2C_FLAG_ARLO ((uint32_t)0x00010200)
+#define I2C_FLAG_BERR ((uint32_t)0x00010100)
+#define I2C_FLAG_TXE ((uint32_t)0x00010080)
+#define I2C_FLAG_RXNE ((uint32_t)0x00010040)
+#define I2C_FLAG_STOPF ((uint32_t)0x00010010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x00010008)
+#define I2C_FLAG_BTF ((uint32_t)0x00010004)
+#define I2C_FLAG_ADDR ((uint32_t)0x00010002)
+#define I2C_FLAG_SB ((uint32_t)0x00010001)
+#define I2C_FLAG_DUALF ((uint32_t)0x00100080)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100010)
+#define I2C_FLAG_TRA ((uint32_t)0x00100004)
+#define I2C_FLAG_BUSY ((uint32_t)0x00100002)
+#define I2C_FLAG_MSL ((uint32_t)0x00100001)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enable or disable the specified I2C interrupts.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __INTERRUPT__: specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2C flag is set or not.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag
+ * @arg I2C_FLAG_RXNE: Data register not empty flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag
+ * Address matched flag
+ * @arg I2C_FLAG_SB: Start bit flag
+ * @arg I2C_FLAG_DUALF: Dual flag
+ * @arg I2C_FLAG_SMBHOST: SMBus host header
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
+ * @arg I2C_FLAG_GENCALL: General call header flag
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+
+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 &= ~((__FLAG__) & I2C_FLAG_MASK))
+
+/** @brief Clears the I2C ADDR pending flag.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
+ (__HANDLE__)->Instance->SR2;}while(0)
+
+/** @brief Clears the I2C STOPF pending flag.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;}while(0)
+
+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+
+#define __HAL_I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
+#define __HAL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
+#define __HAL_I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
+#define __HAL_I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
+#define __HAL_I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (__HAL_I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+ ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define __HAL_I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define __HAL_I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define __HAL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define __HAL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+#define __HAL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+
+/* Include I2C HAL Extension module */
+#include "stm32f4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* I/O operation functions *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Peripheral Control and State functions **************************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,111 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of I2C HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_EX_H
+#define __STM32F4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup I2CEx_Analog_Filter
+ * @{
+ */
+#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLED I2C_FLTR_ANOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Digital_Filter
+ * @{
+ */
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_I2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,430 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_H
+#define __STM32F4xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+
+ uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
+ This parameter can be a value of @ref I2S_Clock_Source */
+
+ uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
+ This parameter can be a value of @ref I2S_FullDuplex_Mode */
+
+}I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
+
+}HAL_I2S_StateTypeDef;
+
+/**
+ * @brief HAL I2S Error Code structure definition
+ */
+typedef enum
+{
+ HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
+ HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
+ HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
+ HAL_I2SEX_ERROR_UDR = 0x04, /*!< I2S extended Underrun error */
+ HAL_I2SEX_ERROR_OVR = 0x08, /*!< I2S extended Overrun error */
+ HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
+ HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
+}HAL_I2S_ErrorTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+typedef struct
+{
+ SPI_TypeDef *Instance; /* I2S registers base address */
+
+ I2S_InitTypeDef Init; /* I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /* I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /* I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /* I2S Rx transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /* I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
+
+ __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
+
+}I2S_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Constants
+ * @{
+ */
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+
+/** @defgroup I2S_Clock_Source
+ * @{
+ */
+#define I2S_CLOCK_PLL ((uint32_t)0x00000000)
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
+
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+ ((CLOCK) == I2S_CLOCK_PLL))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
+#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
+#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
+#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX) || \
+ ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS ((uint32_t)0x00000000)
+#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
+#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
+#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILLIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
+#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
+#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_FullDuplex_Mode
+ * @{
+ */
+#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
+#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
+
+#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
+ ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupt_configuration_definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flag_definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+
+/** @brief Enable or disable the specified I2S interrupts.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
+ (__HANDLE__)->Instance->SR;}while(0)
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
+
+/* Include I2S Extension module */
+#include "stm32f4xx_hal_i2s_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* I/O operation functions *****************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Peripheral Control and State functions **************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+
+void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMAError(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,86 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_EX_H
+#define __STM32F4xx_HAL_I2S_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2SEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Extended features functions **************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+
+HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,384 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_irda.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of IRDA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IRDA_H
+#define __STM32F4xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDA_Word_Length */
+
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler */
+
+ uint32_t IrDAMode; /*!< Specifies the IrDA mode
+ This parameter can be a value of @ref IrDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
+}HAL_IRDA_StateTypeDef;
+
+/**
+ * @brief HAL IRDA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
+ HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
+ HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_IRDA_ErrorTypeDef;
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ IRDA_InitTypeDef Init; /* IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* IRDA Tx Transfer size */
+
+ uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* IRDA Rx Transfer size */
+
+ uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */
+
+ __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */
+
+}IRDA_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IRDA_Word_Length
+ * @{
+ */
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE ((uint32_t)0x00000000)
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Mode
+ * @{
+ */
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+ * @}
+ */
+
+/** @defgroup IrDA_Low_Power
+ * @{
+ */
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
+#define IRDA_FLAG_TC ((uint32_t)0x00000040)
+#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
+#define IRDA_FLAG_IDLE ((uint32_t)0x00000010)
+#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
+#define IRDA_FLAG_NE ((uint32_t)0x00000004)
+#define IRDA_FLAG_FE ((uint32_t)0x00000002)
+#define IRDA_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ *
+ * @{
+ */
+
+#define IRDA_IT_PE ((uint32_t)0x10000100)
+#define IRDA_IT_TXE ((uint32_t)0x10000080)
+#define IRDA_IT_TC ((uint32_t)0x10000040)
+#define IRDA_IT_RXNE ((uint32_t)0x10000020)
+#define IRDA_IT_IDLE ((uint32_t)0x10000010)
+
+#define IRDA_IT_LBD ((uint32_t)0x20000040)
+
+#define IRDA_IT_CTS ((uint32_t)0x30000400)
+#define IRDA_IT_ERR ((uint32_t)0x30000001)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Checks whether the specified IRDA flag is set or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_FLAG_TXE: Transmit data register empty flag
+ * @arg IRDA_FLAG_TC: Transmission Complete flag
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
+ * @arg IRDA_FLAG_IDLE: Idle Line detection flag
+ * @arg IRDA_FLAG_ORE: OverRun Error flag
+ * @arg IRDA_FLAG_NE: Noise Error flag
+ * @arg IRDA_FLAG_FE: Framing Error flag
+ * @arg IRDA_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified IRDA pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg IRDA_FLAG_TC: Transmission Complete flag.
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/** @brief Enables or disables the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified IRDA interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define IRDA_IT_MASK ((uint32_t)0x0000FFFF)
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
+
+/** @brief Checks whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __IT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
+
+
+
+#define __IRDA_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __IRDA_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __IRDA_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+
+/* Peripheral State functions **************************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,250 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IWDG_H
+#define __STM32F4xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief IWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
+ HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
+ HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
+ HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
+
+}HAL_IWDG_StateTypeDef;
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+}IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG handle Structure definition
+ */
+typedef struct
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< IWDG locking object */
+
+ __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
+
+}IWDG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Registers_BitMask
+ * @{
+ */
+/* --- KR Register ---*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG reload counter enable */
+#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG peripheral enable */
+#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR write Access enable */
+#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR write Access disable */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag_definition
+ * @{
+ */
+#define IWDG_FLAG_PVU ((uint32_t)0x0001) /*!< Watchdog counter prescaler value update flag */
+#define IWDG_FLAG_RVU ((uint32_t)0x0002) /*!< Watchdog counter reload value update flag */
+
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
+ ((FLAG) == IWDG_FLAG_RVU))
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 ((uint8_t)0x01) /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 ((uint8_t)0x02) /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 ((uint8_t)0x03) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 ((uint8_t)0x04) /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 ((uint8_t)0x05) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 ((uint8_t)0x06) /*!< IWDG prescaler set to 256 */
+
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \
+ ((PRESCALER) == IWDG_PRESCALER_8) || \
+ ((PRESCALER) == IWDG_PRESCALER_16) || \
+ ((PRESCALER) == IWDG_PRESCALER_32) || \
+ ((PRESCALER) == IWDG_PRESCALER_64) || \
+ ((PRESCALER) == IWDG_PRESCALER_128)|| \
+ ((PRESCALER) == IWDG_PRESCALER_256))
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Reload_Value
+ * @{
+ */
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enables the IWDG peripheral.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) ((__HANDLE__)->Instance->KR |= KR_KEY_ENABLE)
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_RELOAD)
+
+/**
+ * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_EWA)
+
+/**
+ * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_DWA)
+
+/**
+ * @brief Gets the selected IWDG's flag status.
+ * @param __HANDLE__: IWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the IWDG's pending flags.
+ * @param __HANDLE__: IWDG handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+ * @retval None
+ */
+#define __HAL_IWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+__weak void HAL_IWDG_MspDeInit(IWDG_HandleTypeDef *hiwdg);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+
+/* Peripheral State functions **************************************************/
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,579 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of LTDC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LTDC_H
+#define __STM32F4xx_HAL_LTDC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup LTDC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define MAX_LAYER 2
+
+/**
+ * @brief LTDC color structure definition
+ */
+typedef struct
+{
+ uint8_t Blue; /*!< Configures the blue value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Green; /*!< Configures the green value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Red; /*!< Configures the red value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Reserved; /*!< Reserved 0xFF */
+} LTDC_ColorTypeDef;
+
+/**
+ * @brief LTDC Init structure definition
+ */
+typedef struct
+{
+ uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
+ This parameter can be one value of @ref LTDC_HS_POLARITY */
+
+ uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
+ This parameter can be one value of @ref LTDC_VS_POLARITY */
+
+ uint32_t DEPolarity; /*!< configures the data enable polarity.
+ This parameter can be one of value of @ref LTDC_DE_POLARITY */
+
+ uint32_t PCPolarity; /*!< configures the pixel clock polarity.
+ This parameter can be one of value of @ref LTDC_PC_POLARITY */
+
+ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization heigh.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
+ This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+
+ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh.
+ This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+
+ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. This parameter
+ This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+
+ uint32_t AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter
+ This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+
+ uint32_t TotalWidth; /*!< configures the total width. This parameter
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+
+ uint32_t TotalHeigh; /*!< configures the total heigh. This parameter
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
+
+} LTDC_InitTypeDef;
+
+
+/**
+ * @brief LTDC Layer structure definition
+ */
+typedef struct
+{
+ uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t PixelFormat; /*!< Specifies the pixel format.
+ This parameter can be one of value of @ref LTDC_Pixelformat */
+
+ uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Alpha0; /*!< Configures the default alpha value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t BlendingFactor1; /*!< Select the blending factor 1.
+ This parameter can be one of value of @ref LTDC_BlendingFactor1 */
+
+ uint32_t BlendingFactor2; /*!< Select the blending factor 2.
+ This parameter can be one of value of @ref LTDC_BlendingFactor2 */
+
+ uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
+
+ uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+
+ uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
+
+} LTDC_LayerCfgTypeDef;
+
+/**
+ * @brief HAL LTDC State structures definition
+ */
+typedef enum
+{
+ HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */
+ HAL_LTDC_STATE_READY = 0x01, /*!< LTDC initialized and ready for use */
+ HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */
+ HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */
+ HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */
+
+}HAL_LTDC_StateTypeDef;
+
+/**
+ * @brief LTDC handle Structure definition
+ */
+typedef struct
+{
+ LTDC_TypeDef *Instance; /*!< LTDC Register base address */
+
+ LTDC_InitTypeDef Init; /*!< LTDC parameters */
+
+ LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
+
+ HAL_LockTypeDef Lock; /*!< LTDC Lock */
+
+ __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
+
+ __IO uint32_t ErrorCode; /*!< LTDC Error code */
+
+} LTDC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup LTDC_Layer
+ * @{
+ */
+#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC Error Code
+ * @{
+ */
+#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000) /*!< LTDC No error */
+#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001) /*!< LTDC Transfer error */
+#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002) /*!< LTDC FIFO Underrun */
+#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< LTDC Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_HS_POLARITY
+ * @{
+ */
+#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
+
+#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
+ ((HSPOL) == LTDC_HSPOLARITY_AH))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_VS_POLARITY
+ * @{
+ */
+#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
+
+#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \
+ ((VSPOL) == LTDC_VSPOLARITY_AH))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_DE_POLARITY
+ * @{
+ */
+#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
+
+#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || \
+ ((DEPOL) == LTDC_DEPOLARITY_AH))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_PC_POLARITY
+ * @{
+ */
+#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
+
+#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || \
+ ((PCPOL) == LTDC_PCPOLARITY_IIPC))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_SYNC
+ * @{
+ */
+#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
+#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization heigh. */
+
+#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BACK_COLOR
+ * @{
+ */
+#define LTDC_COLOR ((uint32_t)0x000000FF) /*!< Color mask */
+
+#define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BlendingFactor1
+ * @{
+ */
+#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400) /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+
+#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
+ ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BlendingFactor2
+ * @{
+ */
+#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005) /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+
+#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
+ ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Pixelformat
+ * @{
+ */
+#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001) /*!< RGB888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006) /*!< AL44 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007) /*!< AL88 LTDC pixel format */
+
+#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Alpha
+ * @{
+ */
+#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */
+
+#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_LAYER_Config
+ * @{
+ */
+#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */
+#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
+
+#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
+#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
+
+#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)
+
+#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
+
+#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_LIPosition
+ * @{
+ */
+#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Interrupts
+ * @{
+ */
+#define LTDC_IT_LI LTDC_IER_LIE
+#define LTDC_IT_FU LTDC_IER_FUIE
+#define LTDC_IT_TE LTDC_IER_TERRIE
+#define LTDC_IT_RR LTDC_IER_RRIE
+
+#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Flag
+ * @{
+ */
+#define LTDC_FLAG_LI LTDC_ISR_LIF
+#define LTDC_FLAG_FU LTDC_ISR_FUIF
+#define LTDC_FLAG_TE LTDC_ISR_TERRIF
+#define LTDC_FLAG_RR LTDC_ISR_RRIF
+
+#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
+ ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief Enable the LTDC.
+ * @param __HANDLE__: LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
+
+/**
+ * @brief Disable the LTDC.
+ * @param __HANDLE__: LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
+
+/**
+ * @brief Enable the LTDC Layer.
+ * @param __HANDLE__: LTDC handle
+ * @param __LAYER__: Specify the layer to be enabled
+ This parameter can be 0 or 1
+ * @retval None.
+ */
+#define __HAL_LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))
+
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+
+
+/**
+ * @brief Disable the LTDC Layer.
+ * @param __HANDLE__: LTDC handle
+ * @param __LAYER__: Specify the layer to be disabled
+ This parameter can be 0 or 1
+ * @retval None.
+ */
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+
+/**
+ * @brief Reload Layer Configuration.
+ * @param __HANDLE__: LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the LTDC pending flags.
+ * @param __HANDLE__: LTDC handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_FLAG_LI: Line Interrupt flag
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the LTDC pending flags.
+ * @param __HANDLE__: LTDC handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_FLAG_LI: Line Interrupt flag
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/**
+ * @brief Enables the specified LTDC interrupts.
+ * @param __HANDLE__: LTDC handle
+ * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified LTDC interrupts.
+ * @param __HANDLE__: LTDC handle
+ * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified LTDC interrupt has occurred or not.
+ * @param __HANDLE__: LTDC handle
+ * @param __INTERRUPT__: specifies the LTDC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval The state of INTERRUPT (SET or RESET).
+ */
+#define __HAL_LTDC_IT_STATUS(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
+__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
+__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
+
+/* IO operation functions *******************************************************/
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+
+/* Peripheral State functions ***************************************************/
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
+
+#endif /* STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LTDC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,236 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nand.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NAND_H
+#define __STM32F4xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NAND
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
+
+}HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*<! NAND memory electronic signature maker and device IDs */
+
+ uint8_t Maker_Id;
+
+ uint8_t Device_Id;
+
+ uint8_t Third_Id;
+
+ uint8_t Fourth_Id;
+
+}NAND_IDTypeDef;
+
+/**
+ * @brief NAND Memory address Structure definition
+ */
+typedef struct
+{
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Zone; /*!< NAND memory Zone address */
+
+ uint16_t Block; /*!< NAND memory Block address */
+
+}NAND_AddressTypedef;
+
+/**
+ * @brief NAND Memory info Structure definition
+ */
+typedef struct
+{
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
+
+ uint32_t BlockSize; /*!< NAND memory block size number of pages */
+
+ uint32_t BlockNbr; /*!< NAND memory number of blocks */
+
+ uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
+
+}NAND_InfoTypeDef;
+
+/**
+ * @brief NAND handle Structure definition
+ */
+typedef struct
+{
+ FMC_NAND_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
+
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+
+ NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
+
+}NAND_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup NAND_Exported_Constants
+ * @{
+ */
+#define NAND_DEVICE1 ((uint32_t)0x70000000)
+#define NAND_DEVICE2 ((uint32_t)0x80000000)
+#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
+
+#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
+#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
+#define NAND_BUSY ((uint32_t)0x00000000)
+#define NAND_ERROR ((uint32_t)0x00000001)
+#define NAND_READY ((uint32_t)0x00000040)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__: NAND memory address.
+ * @param __HANDLE__ : NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize)))
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8) /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16) /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
+
+/* NAND Control functions ******************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/* NAND State functions *********************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,240 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nor.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NOR_H
+#define __STM32F4xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NOR
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+
+}HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FMC NOR Status typedef
+ */
+typedef enum
+{
+ NOR_SUCCESS = 0,
+ NOR_ONGOING,
+ NOR_ERROR,
+ NOR_TIMEOUT
+
+}NOR_StatusTypedef;
+
+/**
+ * @brief FMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command */
+
+}NOR_IDTypeDef;
+
+
+/**
+ * @brief FMC NOR CFI typedef
+ */
+typedef struct
+{
+ /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory */
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
+
+}NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+}NOR_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Constants
+ * @{
+ */
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x61)
+#define CFI2_ADDRESS ((uint16_t)0x62)
+#define CFI3_ADDRESS ((uint16_t)0x63)
+#define CFI4_ADDRESS ((uint16_t)0x64)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT ((uint16_t)0xFFFF)
+
+/* #define NOR_MEMORY_16B */
+#define NOR_MEMORY_8B
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS ((uint32_t)0x60000000)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief NOR memory address shifting.
+ * @param __ADDRESS__: NOR memory address
+ * @retval NOR shifted address value
+ */
+#ifdef NOR_MEMORY_8B
+ #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (2 * (__ADDRESS__)))
+#else /* NOR_MEMORY_16B */
+ #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (__ADDRESS__))
+#endif /* NOR_MEMORY_8B */
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param __ADDRESS__: NOR memory address
+ * @param __DATA__: Data to write
+ * @retval None
+ */
+#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint32_t *)(__ADDRESS__) = (__DATA__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/* NOR Control functions *******************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/* NOR State functions **********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,178 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pccard.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of PCCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCCARD_H
+#define __STM32F4xx_HAL_PCCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCCARD
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
+}HAL_PCCARD_StateTypeDef;
+
+typedef enum
+{
+ CF_SUCCESS = 0,
+ CF_ONGOING,
+ CF_ERROR,
+ CF_TIMEOUT
+}CF_StatusTypedef;
+
+/**
+ * @brief FMC_PCCARD handle Structure definition
+ */
+typedef struct
+{
+ FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
+
+ FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
+
+ __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
+
+ HAL_LockTypeDef Lock; /*!< PCCARD Lock */
+
+}PCCARD_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Constants
+ * @{
+ */
+
+#define CF_DEVICE_ADDRESS ((uint32_t)0x90000000)
+#define CF_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
+#define CF_COMMON_SPACE_ADDRESS CF_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define CF_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
+#define CF_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ((uint8_t)0x00) /* Data register */
+#define CF_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
+#define CF_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
+#define CF_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
+#define CF_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
+#define CF_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
+#define CF_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
+#define CF_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
+#define CF_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ((uint8_t)0x20)
+#define CF_WRITE_SECTOR_CMD ((uint8_t)0x30)
+#define CF_ERASE_SECTOR_CMD ((uint8_t)0xC0)
+#define CF_IDENTIFY_CMD ((uint8_t)0xEC)
+
+/* Compact Flash status */
+#define CF_TIMEOUT_ERROR ((uint8_t)0x60)
+#define CF_BUSY ((uint8_t)0x80)
+#define CF_PROGR ((uint8_t)0x01)
+#define CF_READY ((uint8_t)0x40)
+
+#define CF_SECTOR_SIZE ((uint32_t)255) /* In half words */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard);
+CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_PCCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,209 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pcd.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCD_H
+#define __STM32F4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+ /**
+ * @brief PCD State structures definition
+ */
+typedef enum
+{
+ PCD_READY = 0x00,
+ PCD_ERROR = 0x01,
+ PCD_BUSY = 0x02,
+ PCD_TIMEOUT = 0x03
+} PCD_StateTypeDef;
+
+
+typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+typedef struct
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+} PCD_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PCD_Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH 0
+#define PCD_SPEED_HIGH_IN_FULL 1
+#define PCD_SPEED_LOW 2
+#define PCD_SPEED_FULL 3
+/**
+ * @}
+ */
+
+ /** @defgroup PCD_PHY_Module
+ * @{
+ */
+#define PCD_PHY_ULPI 1
+#define PCD_PHY_EMBEDDED 2
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Instance_definition
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PCD_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+/* I/O operation functions *****************************************************/
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+
+/* Peripheral State functions **************************************************/
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,333 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_H
+#define __STM32F4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
+ This parameter can be a value of @ref PWR_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* Alias word address of FPDS bit */
+#define FPDS_BitNumber 0x09
+#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
+
+/* Alias word address of PMODE bit */
+#define PMODE_BitNumber 0x0E
+#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber 0x08
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* Alias word address of BRE bit */
+#define BRE_BitNumber 0x09
+#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PWR_WakeUp_Pins
+ * @{
+ */
+
+#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_detection_level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode
+ * @{
+ */
+#define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
+#define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
+ ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_Voltage_Scale
+ * @{
+ */
+#define PWR_REGULATOR_VOLTAGE_SCALE1 ((uint32_t)0x0000C000)
+#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00008000)
+#define PWR_REGULATOR_VOLTAGE_SCALE3 ((uint32_t)0x00004000)
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+#define PWR_FLAG_BRR PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief macros configure the main internal regulator output voltage.
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption when the device does
+ * not operate at the maximum frequency (refer to the datasheets for more details).
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm (Alarm A
+ * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+ * An additional wakeup event is detected if the WKUP pin is enabled
+ * (by setting the EWUP bit) when the WKUP pin level is already high.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * For this reason, this bit is equal to 0 after Standby or reset
+ * until the PVDE bit is set.
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
+ * when the device wakes up from Standby mode or by a system reset
+ * or power reset.
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
+ * scaling output selection is ready.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the PWR's pending flags.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
+
+#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+ * @brief Enable the PVD Exti Line.
+ * @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval None.
+ */
+#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+
+/**
+ * @brief Disable the PVD EXTI Line.
+ * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval None.
+ */
+#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+
+/**
+ * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+ * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
+
+/**
+ * @brief Clear the PVD Exti flag.
+ * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval None.
+ */
+#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
+
+
+/* Include PWR HAL Extension module */
+#include "stm32f4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/* Peripheral Control functions ************************************************/
+void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_PVD_IRQHandler(void);
+__weak void HAL_PWR_PVDCallback(void);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,161 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of PWR HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_EX_H
+#define __STM32F4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+
+/* Alias word address of ODEN bit */
+#define ODEN_BitNumber 0x10
+#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
+
+/* Alias word address of ODSWEN bit */
+#define ODSWEN_BitNumber 0x11
+#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
+
+
+/** @defgroup PWREx_Over_Under_Drive_Flag
+ * @{
+ */
+#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
+#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
+#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Macros to enable or disable the Over drive mode.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Over drive switching.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Under drive mode.
+ * @note This mode is enabled only with STOP low power mode.
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
+ * mode is only available when the main regulator or the low power regulator
+ * is in low voltage mode.
+ * @note If the Under-drive mode was enabled, it is automatically disabled after
+ * exiting Stop mode.
+ * When the voltage regulator operates in Under-drive mode, an additional
+ * startup delay is induced when waking up from Stop mode.
+ */
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
+
+/** @brief Check PWR flag is set or not.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
+ * is ready
+ * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
+ * switching is ready
+ * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
+ * is enabled in Stop mode
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the Under-Drive Ready flag.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1173 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_H
+#define __STM32F4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK)
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider. */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+
+}RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+}RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+/* Alias word address of PLLI2SON bit */
+#define PLLI2SON_BitNumber 0x1A
+#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of I2SSRC bit */
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
+#define I2SSRC_BitNumber 0x17
+#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+/* BDCR register base address */
+#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config
+ * @{
+ */
+#define RCC_HSE_OFF ((uint8_t)0x00)
+#define RCC_HSE_ON ((uint8_t)0x01)
+#define RCC_HSE_BYPASS ((uint8_t)0x05)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config
+ * @{
+ */
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_BYPASS ((uint8_t)0x05)
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint8_t)0x00)
+#define RCC_HSI_ON ((uint8_t)0x01)
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint8_t)0x00)
+#define RCC_LSI_ON ((uint8_t)0x01)
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint8_t)0x00)
+#define RCC_PLL_OFF ((uint8_t)0x01)
+#define RCC_PLL_ON ((uint8_t)0x02)
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLP_Clock_Divider
+ * @{
+ */
+#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
+#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
+#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
+#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
+#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+ ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+ ((PCLK) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
+#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
+#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
+#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
+#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
+#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
+#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
+#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
+#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
+#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
+#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
+#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
+#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
+#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
+#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
+#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
+#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
+#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
+#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2S_Clock_Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
+#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Index
+ * @{
+ */
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO2 ((uint32_t)0x00000001)
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO1_Clock_Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO2_Clock_Source
+ * @{
+ */
+#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
+#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler
+ * @{
+ */
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+ ((DIV) == RCC_MCODIV_5))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
+#define RCC_IT_CSS ((uint8_t)0x80)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * Elements values convention: 0XXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - 0XX : Register index
+ * - 01: CR register
+ * - 10: BDCR register
+ * - 11: CSR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_BORRST ((uint8_t)0x79)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
+#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
+#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
+#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
+#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
+#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
+#define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
+#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
+#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
+#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
+#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
+
+#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+
+/** @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __SYSCFG_CLK_ENABLE();\
+ }while(0)
+
+
+#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __SYSCFG_CLK_DISABLE();\
+ }while(0)
+
+#define __RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
+#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
+#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
+#define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
+#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
+#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+#define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
+#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
+#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
+#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+#define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
+#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+
+#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
+#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
+#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
+#define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
+#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
+#define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
+#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
+#define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
+#define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
+#define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
+
+#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+
+/** @brief Force or release AHB1 peripheral reset.
+ */
+#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
+#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+
+#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
+#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+
+/** @brief Force or release AHB2 peripheral reset.
+ */
+#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+
+/** @brief Force or release APB1 peripheral reset.
+ */
+#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+
+/** @brief Force or release APB2 peripheral reset.
+ */
+#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+
+/** @brief Force or release AHB3 peripheral reset.
+ */
+#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+
+#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+
+#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+
+#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICalibrationValue__: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
+ RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator.
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
+
+/** @brief Macros to enable or disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
+
+/** @brief Macros to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+ * a Power On Reset (POR).
+ * @param __RTCCLKSource__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+ * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : 0
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
+ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
+ } while (0)
+
+/** @brief Macros to force or release the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
+
+/** @brief Macros to enable or disable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
+
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 192 and 432 MHz.
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
+ * the System clock frequency.
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
+ (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __SOURCE__: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source.
+ */
+#define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
+
+/** @brief Macros to enable or disable the PLLI2S.
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
+
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * - RCC_CFGR_SWS_HSI: HSI used as system clock.
+ * - RCC_CFGR_SWS_HSE: HSE used as system clock.
+ * - RCC_CFGR_SWS_PLL: PLL used as system clock.
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+/** @brief Macro to get the oscillator used as PLL clock source.
+ * @retval The oscillator used as PLL clock source. The returned value can be one
+ * of the following:
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+
+/** @defgroup RCC_Flags_Interrupts_Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+ * bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+ */
+#define __HAL_RCC_CLEAR_FLAG() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
+ * @arg RCC_FLAG_PINRST: Pin reset.
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.
+ * @arg RCC_FLAG_SFTRST: Software reset.
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
+/**
+ * @}
+ */
+
+#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
+
+
+/* Include RCC HAL Extension module */
+#include "stm32f4xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+__weak void HAL_RCC_CCSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,874 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_EX_H
+#define __STM32F4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief PLLSAI Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7
+ This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
+
+}RCC_PLLSAIInitTypeDef;
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
+ This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+}RCC_PLLI2SInitTypeDef;
+
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint8_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_BitAddress_AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+/* --- CR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/* Alias word address of PLLSAION bit */
+#define PLLSAION_BitNumber 0x1C
+#define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
+
+/* --- DCKCFGR Register ---*/
+/* Alias word address of TIMPRE bit */
+#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
+#define TIMPRE_BitNumber 0x18
+#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLI2S_Clock_Source
+ * @{
+ */
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAI_Clock_Source
+ * @{
+ */
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAI_DIVQ
+ * @{
+ */
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLI2S_DIVQ
+ * @{
+ */
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAI_DIVR
+ * @{
+ */
+#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
+#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
+#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
+#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_4) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_8) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_16))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI_BlockA_Clock_Source
+ * @{
+ */
+#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
+#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI_BlockB_Clock_Source
+ * @{
+ */
+#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
+#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM_PRescaler_Selection
+ * @{
+ */
+#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
+#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
+#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
+#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
+#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
+#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
+#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
+#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
+#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
+
+#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
+#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
+#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
+
+#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+/**
+ * @brief Enable ETHERNET clock.
+ */
+#define __ETH_CLK_ENABLE() do { \
+ __ETHMAC_CLK_ENABLE(); \
+ __ETHMACTX_CLK_ENABLE(); \
+ __ETHMACRX_CLK_ENABLE(); \
+ } while(0)
+
+/**
+ * @brief Disable ETHERNET clock.
+ */
+#define __ETH_CLK_DISABLE() do { \
+ __ETHMACTX_CLK_DISABLE(); \
+ __ETHMACRX_CLK_DISABLE(); \
+ __ETHMAC_CLK_DISABLE(); \
+ } while(0)
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+/** @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
+#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
+#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
+
+#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
+#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
+#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
+#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
+#define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
+#define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
+#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
+#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
+#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
+#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
+#define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
+#define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
+#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+
+#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
+#define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
+
+#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
+#define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
+#define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
+
+#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
+#define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
+#define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
+#define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
+
+#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release AHB1 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+
+#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+
+#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release AHB2 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Force or release AHB3 peripheral reset
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release APB1 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+
+#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release APB2 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+
+#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+
+#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
+#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+
+#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+
+#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+
+#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+
+#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+
+/** @brief Macro to configure the Timers clocks prescalers
+ * @note This feature is only available with STM32F429x/439x Devices.
+ * @param __PRESC__ : specifies the Timers clocks prescalers selection
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2,
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
+ * division by 4 or more.
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
+ * to division by 8 or more.
+ */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
+
+/** @brief Macros to Enable or Disable the PLLISAI.
+ * @note The PLLSAI is only available with STM32F429x/439x Devices.
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
+#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
+
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ * @note The PLLSAI is only available with STM32F429x/439x Devices.
+ * @note This function must be used only when the PLLSAI is disabled.
+ * @note PLLSAI clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
+
+/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API)
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
+ * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
+
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling the PLLI2S.
+ * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
+ */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
+
+/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+ * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
+
+/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
+ *
+ * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+ * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
+
+/** @brief Macro to configure SAI1BlockA clock source selection.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block A clock.
+ */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief Macro to configure SAI1BlockB clock source selection.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block B clock.
+ */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+
+/** @brief Enable PLLSAI_RDY interrupt.
+ */
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Disable PLLSAI_RDY interrupt.
+ */
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Clear the PLLSAI RDY interrupt pending bits.
+ */
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
+
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.
+ * @retval The new state (TRUE or FALSE).
+ */
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Check PLLSAI RDY flag is set or not.
+ * @retval The new state (TRUE or FALSE).
+ */
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rng.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,212 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rng.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of RNG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RNG_H
+#define __STM32F4xx_HAL_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RNG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RNG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */
+ HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */
+ HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */
+ HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */
+ HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */
+
+}HAL_RNG_StateTypeDef;
+
+/**
+ * @brief RNG Handle Structure definition
+ */
+typedef struct
+{
+ RNG_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< RNG locking object */
+
+ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+
+}RNG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RNG_Interrupt_definition
+ * @{
+ */
+#define RNG_IT_CEI ((uint32_t)0x20) /*!< Clock error interrupt */
+#define RNG_IT_SEI ((uint32_t)0x40) /*!< Seed error interrupt */
+
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+ ((IT) == RNG_IT_SEI))
+/**
+ * @}
+ */
+
+
+/** @defgroup RNG_Flag_definition
+ * @{
+ */
+#define RNG_FLAG_DRDY ((uint32_t)0x0001) /*!< Data ready */
+#define RNG_FLAG_CECS ((uint32_t)0x0002) /*!< Clock error current status */
+#define RNG_FLAG_SECS ((uint32_t)0x0004) /*!< Seed error current status */
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enables the RNG peripheral.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
+
+/**
+ * @brief Disables the RNG peripheral.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+ * @brief Gets the selected RNG's flag status.
+ * @param __HANDLE__: RNG Handle
+ * @param __FLAG__: RNG flag
+ * @retval The new state of RNG_FLAG (SET or RESET).
+ */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the RNG's pending flags.
+ * @param __HANDLE__: RNG Handle
+ * @param __FLAG__: RNG flag
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+ * @brief Enables the RNG interrupts.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
+
+/**
+ * @brief Disables the RNG interrupts.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+ * @brief Checks whether the specified RNG interrupt has occurred or not.
+ * @param __HANDLE__: RNG Handle
+ * @param __INTERRUPT__: specifies the RNG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RNG_FLAG_DRDY: Data ready interrupt
+ * @arg RNG_FLAG_CECS: Clock error interrupt
+ * @arg RNG_FLAG_SECS: Seed error interrupt
+ * @retval The new state of RNG_FLAG (SET or RESET).
+ */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+
+/* Peripheral Control functions ************************************************/
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng);
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+
+/* Peripheral State functions **************************************************/
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,739 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_H
+#define __STM32F4xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
+
+}HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter can be a value of @ref RTC_Output_selection_Definitions */
+
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+ uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+ This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+ in CR register to store the operation.
+ This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/**
+ * @brief Time Handle Structure definition
+ */
+typedef struct
+{
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+/** @defgroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_StoreOperation_Definitions
+ * @{
+ */
+#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define FORMAT_BIN ((uint32_t)0x000000000)
+#define FORMAT_BCD ((uint32_t)0x000000001)
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
+
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_ALARM_A RTC_CR_ALRAE
+#define RTC_ALARM_B RTC_CR_ALRBE
+
+#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_None))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_IT_TS ((uint32_t)0x00008000)
+#define RTC_IT_WUT ((uint32_t)0x00004000)
+#define RTC_IT_ALRB ((uint32_t)0x00002000)
+#define RTC_IT_ALRA ((uint32_t)0x00001000)
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xCA; \
+ (__HANDLE__)->Instance->WPR = 0x53; \
+ } while(0)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xFF; \
+ } while(0)
+
+/**
+ * @brief Enable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+ * @brief Disable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+ * @brief Enable the RTC ALARMB peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+ * @brief Disable the RTC ALARMB peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @arg RTC_FLAG_ALRAWF
+ * @arg RTC_FLAG_ALRBWF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+
+/**
+ * @brief Enable the RTC Exti line.
+ * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+
+/**
+ * @brief Disable the RTC Exti line.
+ * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+
+/**
+ * @brief Clear the RTC Exti flags.
+ * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+
+/* Include RTC HAL Extension module */
+#include "stm32f4xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t Value);
+uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,691 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of RTC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_EX_H
+#define __STM32F4xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RTC Tamper structure definition
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+
+ uint32_t PinSelection; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+
+ uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
+ This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
+ This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
+}RTC_TamperTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Backup_Registers_Definitions
+ * @{
+ */
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)
+
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4) || \
+ ((BKP) == RTC_BKP_DR5) || \
+ ((BKP) == RTC_BKP_DR6) || \
+ ((BKP) == RTC_BKP_DR7) || \
+ ((BKP) == RTC_BKP_DR8) || \
+ ((BKP) == RTC_BKP_DR9) || \
+ ((BKP) == RTC_BKP_DR10) || \
+ ((BKP) == RTC_BKP_DR11) || \
+ ((BKP) == RTC_BKP_DR12) || \
+ ((BKP) == RTC_BKP_DR13) || \
+ ((BKP) == RTC_BKP_DR14) || \
+ ((BKP) == RTC_BKP_DR15) || \
+ ((BKP) == RTC_BKP_DR16) || \
+ ((BKP) == RTC_BKP_DR17) || \
+ ((BKP) == RTC_BKP_DR18) || \
+ ((BKP) == RTC_BKP_DR19))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
+#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
+
+#define IS_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Selection
+ * @{
+ */
+#define RTC_TAMPERPIN_PC13 ((uint32_t)0x00000000)
+#define RTC_TAMPERPIN_PI8 ((uint32_t)0x00010000)
+
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
+ ((PIN) == RTC_TAMPERPIN_PI8))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00020000)
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
+ ((PIN) == RTC_TIMESTAMPPIN_PI8))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
+
+#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+
+#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+
+#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+
+#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
+
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions
+ * @{
+ */
+#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
+
+#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
+
+#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Digital_Calibration_Definitions
+ * @{
+ */
+#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000)
+#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080)
+
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
+ ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
+
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+/**
+ * @}
+ */
+
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
+#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
+
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+ * @brief Disable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the Coarse calibration process.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
+
+/**
+ * @brief Disable the Coarse calibration process.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC shift operation's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* RTC TimeStamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/* RTC Wake-up functions ******************************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/* Extension Control functions ************************************************/
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+
+/* Extension RTC features functions *******************************************/
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,763 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of SAI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_H
+#define __STM32F4xx_HAL_SAI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SAI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SAI Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Protocol; /*!< Specifies the SAI Block protocol.
+ This parameter can be a value of @ref SAI_Block_Protocol */
+
+ uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
+ This parameter can be a value of @ref SAI_Block_Mode */
+
+ uint32_t DataSize; /*!< Specifies the SAI Block data size.
+ This parameter can be a value of @ref SAI_Block_Data_Size */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+ uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
+ This parameter can be a value of @ref SAI_Block_Clock_Strobing */
+
+ uint32_t Synchro; /*!< Specifies SAI Block synchronization
+ This parameter can be a value of @ref SAI_Block_Synchronization */
+
+ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
+ This parameter can be a value of @ref SAI_Block_Output_Drive
+ @note this value has to be set before enabling the audio block
+ but after the audio block configuration. */
+
+ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
+ This parameter can be a value of @ref SAI_Block_NoDivider
+ @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+ should be aligned to a number equal to a power of 2, from 8 to 256.
+ If bit NODIV in the SAI_xCR1 register is set, the frame length can
+ take any of the values without constraint since the input clock of
+ the audio block should be equal to the bit clock.
+ There is no MCLK_x clock which can be output. */
+
+ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
+ This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+ uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
+ This parameter can be a value of @ref SAI_Clock_Source
+ @note: If ClockSource is equal to SAI_CLKSource_Ext, the PLLI2S
+ and PLLSAI divisions factors will be ignored. */
+
+ uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
+ This parameter can be a value of @ref SAI_Audio_Frequency */
+
+}SAI_InitTypeDef;
+
+/**
+ * @brief SAI Block Frame Init structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+ This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+ @note: If master clock MCLK_x pin is declared as an output, the frame length
+ should be aligned to a number equal to power of 2 in order to keep
+ in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+ uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
+ This Parameter specifies the length in number of bit clock (SCK + 1)
+ of the active level of FS signal in audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+ uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
+ This parameter can be a value of @ref SAI_Block_FS_Definition */
+
+ uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
+ This parameter can be a value of @ref SAI_Block_FS_Polarity */
+
+ uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
+ This parameter can be a value of @ref SAI_Block_FS_Offset */
+
+}SAI_FrameInitTypeDef;
+
+/**
+ * @brief SAI Block Slot Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+ uint32_t SlotSize; /*!< Specifies the Slot Size.
+ This parameter can be a value of @ref SAI_Block_Slot_Size */
+
+ uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
+ This parameter can be a value of @ref SAI_Block_Slot_Active */
+}SAI_SlotInitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SAI_STATE_RESET = 0x00, /*!< SAI not yet initialized or disabled */
+ HAL_SAI_STATE_READY = 0x01, /*!< SAI initialized and ready for use */
+ HAL_SAI_STATE_BUSY = 0x02, /*!< SAI internal process is ongoing */
+ HAL_SAI_STATE_BUSY_TX = 0x12, /*!< Data transmission process is ongoing */
+ HAL_SAI_STATE_BUSY_RX = 0x22, /*!< Data reception process is ongoing */
+ HAL_SAI_STATE_TIMEOUT = 0x03, /*!< SAI timeout state */
+ HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */
+
+}HAL_SAI_StateTypeDef;
+
+/**
+ * @brief SAI handle Structure definition
+ */
+typedef struct
+{
+ SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
+
+ SAI_InitTypeDef Init; /*!< SAI communication parameters */
+
+ SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
+
+ SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SAI Tx transfer size */
+
+ uint16_t TxXferCount; /*!< SAI Tx transfer counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */
+
+ uint16_t RxXferSize; /*!< SAI Rx transfer size */
+
+ uint16_t RxXferCount; /*!< SAI Rx transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< SAI locking object */
+
+ __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SAI Error code */
+
+}SAI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Constants
+ * @{
+ */
+/** @defgroup SAI Error Code
+ * @{
+ */
+#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
+#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Clock_Source
+ * @{
+ */
+#define SAI_CLKSOURCE_PLLSAI ((uint32_t)RCC_SAIACLKSOURCE_PLLSAI)
+#define SAI_CLKSOURCE_PLLI2S ((uint32_t)RCC_SAIACLKSOURCE_PLLI2S)
+#define SAI_CLKSOURCE_EXT ((uint32_t)RCC_SAIACLKSOURCE_EXT)
+
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == SAI_CLKSOURCE_EXT))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Audio_Frequency
+ * @{
+ */
+#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000)
+#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000)
+#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000)
+#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100)
+#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000)
+#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)
+#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)
+#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)
+#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mode
+ * @{
+ */
+#define SAI_MODEMASTER_TX ((uint32_t)0x00000000)
+#define SAI_MODEMASTER_RX ((uint32_t)0x00000001)
+#define SAI_MODESLAVE_TX ((uint32_t)0x00000002)
+#define SAI_MODESLAVE_RX ((uint32_t)0x00000003)
+#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
+ ((MODE) == SAI_MODEMASTER_RX) || \
+ ((MODE) == SAI_MODESLAVE_TX) || \
+ ((MODE) == SAI_MODESLAVE_RX))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Protocol
+ * @{
+ */
+
+#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000)
+#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
+ ((PROTOCOL) == SAI_AC97_PROTOCOL))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Data_Size
+ * @{
+ */
+#define SAI_DATASIZE_8 ((uint32_t)0x00000040)
+#define SAI_DATASIZE_10 ((uint32_t)0x00000060)
+#define SAI_DATASIZE_16 ((uint32_t)0x00000080)
+#define SAI_DATASIZE_20 ((uint32_t)0x000000A0)
+#define SAI_DATASIZE_24 ((uint32_t)0x000000C0)
+#define SAI_DATASIZE_32 ((uint32_t)0x000000E0)
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
+ ((DATASIZE) == SAI_DATASIZE_10) || \
+ ((DATASIZE) == SAI_DATASIZE_16) || \
+ ((DATASIZE) == SAI_DATASIZE_20) || \
+ ((DATASIZE) == SAI_DATASIZE_24) || \
+ ((DATASIZE) == SAI_DATASIZE_32))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission
+ * @{
+ */
+
+#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+ ((BIT) == SAI_FIRSTBIT_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Clock_Strobing
+ * @{
+ */
+#define SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000)
+#define SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)SAI_xCR1_CKSTR)
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Synchronization
+ * @{
+ */
+#define SAI_ASYNCHRONOUS ((uint32_t)0x00000000)
+#define SAI_SYNCHRONOUS ((uint32_t)SAI_xCR1_SYNCEN_0)
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Output_Drive
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED ((uint32_t)0x00000000)
+#define SAI_OUTPUTDRIVE_ENABLED ((uint32_t)SAI_xCR1_OUTDRIV)
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLED) || \
+ ((DRIVE) == SAI_OUTPUTDRIVE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_NoDivider
+ * @{
+ */
+#define SAI_MASTERDIVIDER_ENABLED ((uint32_t)0x00000000)
+#define SAI_MASTERDIVIDER_DISABLED ((uint32_t)SAI_xCR1_NODIV)
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLED) || \
+ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Master_Divider
+ * @{
+ */
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Frame_Length
+ * @{
+ */
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Active_FrameLength
+ * @{
+ */
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Definition
+ * @{
+ */
+#define SAI_FS_STARTFRAME ((uint32_t)0x00000000)
+#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Polarity
+ * @{
+ */
+#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000)
+#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO)
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+ ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Offset
+ * @{
+ */
+#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000)
+#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_FirstBit_Offset
+ * @{
+ */
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+/**
+ * @}
+ */
+
+ /** @defgroup SAI_Block_Slot_Size
+ * @{
+ */
+#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000)
+#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+ ((SIZE) == SAI_SLOTSIZE_16B) || \
+ ((SIZE) == SAI_SLOTSIZE_32B))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Number
+ * @{
+ */
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Active
+ * @{
+ */
+#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)
+#define SAI_SLOTACTIVE_0 ((uint32_t)0x00010000)
+#define SAI_SLOTACTIVE_1 ((uint32_t)0x00020000)
+#define SAI_SLOTACTIVE_2 ((uint32_t)0x00040000)
+#define SAI_SLOTACTIVE_3 ((uint32_t)0x00080000)
+#define SAI_SLOTACTIVE_4 ((uint32_t)0x00100000)
+#define SAI_SLOTACTIVE_5 ((uint32_t)0x00200000)
+#define SAI_SLOTACTIVE_6 ((uint32_t)0x00400000)
+#define SAI_SLOTACTIVE_7 ((uint32_t)0x00800000)
+#define SAI_SLOTACTIVE_8 ((uint32_t)0x01000000)
+#define SAI_SLOTACTIVE_9 ((uint32_t)0x02000000)
+#define SAI_SLOTACTIVE_10 ((uint32_t)0x04000000)
+#define SAI_SLOTACTIVE_11 ((uint32_t)0x08000000)
+#define SAI_SLOTACTIVE_12 ((uint32_t)0x10000000)
+#define SAI_SLOTACTIVE_13 ((uint32_t)0x20000000)
+#define SAI_SLOTACTIVE_14 ((uint32_t)0x40000000)
+#define SAI_SLOTACTIVE_15 ((uint32_t)0x80000000)
+#define SAI_SLOTACTIVE_ALL ((uint32_t)0xFFFF0000)
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Mono_Stereo_Mode
+ * @{
+ */
+#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
+#define SAI_STREOMODE ((uint32_t)0x00000000)
+
+#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+ ((MODE) == SAI_STREOMODE))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_TRIState_Management
+ * @{
+ */
+#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000)
+#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+ ((STATE) == SAI_OUTPUT_RELEASED))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Threshold
+ * @{
+ */
+#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)
+#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)0x00000001)
+#define SAI_FIFOTHRESHOLD_HF ((uint32_t)0x00000002)
+#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)0x00000003)
+#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)0x00000004)
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Companding_Mode
+ * @{
+ */
+#define SAI_NOCOMPANDING ((uint32_t)0x00000000)
+#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)0x00008000)
+#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)0x0000C000)
+#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)0x0000A000)
+#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)0x0000E000)
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
+ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mute_Value
+ * @{
+ */
+#define SAI_ZERO_VALUE ((uint32_t)0x00000000)
+#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
+ ((VALUE) == SAI_LAST_SENT_VALUE))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mute_Frame_Counter
+ * @{
+ */
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Interrupts_Definition
+ * @{
+ */
+#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
+#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
+#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
+#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
+#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
+#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
+#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
+
+#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \
+ ((IT) == SAI_IT_MUTEDET) || \
+ ((IT) == SAI_IT_WCKCFG) || \
+ ((IT) == SAI_IT_FREQ) || \
+ ((IT) == SAI_IT_CNRDY) || \
+ ((IT) == SAI_IT_AFSDET) || \
+ ((IT) == SAI_IT_LFSDET))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Flags_Definition
+ * @{
+ */
+#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
+#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
+#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
+#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
+#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
+#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
+#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
+
+#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
+ ((FLAG) == SAI_FLAG_MUTEDET) || \
+ ((FLAG) == SAI_FLAG_WCKCFG) || \
+ ((FLAG) == SAI_FLAG_FREQ) || \
+ ((FLAG) == SAI_FLAG_CNRDY) || \
+ ((FLAG) == SAI_FLAG_AFSDET) || \
+ ((FLAG) == SAI_FLAG_LFSDET))
+
+#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
+ ((FLAG) == SAI_FLAG_MUTEDET) || \
+ ((FLAG) == SAI_FLAG_WCKCFG) || \
+ ((FLAG) == SAI_FLAG_FREQ) || \
+ ((FLAG) == SAI_FLAG_CNRDY) || \
+ ((FLAG) == SAI_FLAG_AFSDET) || \
+ ((FLAG) == SAI_FLAG_LFSDET))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Status_Level
+ * @{
+ */
+#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000)
+#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000)
+#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000)
+#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000)
+#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000)
+#define SAI_FIFOStatus_Full ((uint32_t)0x00050000)
+
+#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
+ ((STATUS) == SAI_FIFOStatus_HalfFull) || \
+ ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
+ ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
+ ((STATUS) == SAI_FIFOStatus_Full) || \
+ ((STATUS) == SAI_FIFOStatus_Empty))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enable or disable the specified SAI interrupts.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
+ * @retval None
+ */
+
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief Check if the specified SAI interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
+ * @param __INTERRUPT__: specifies the SAI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_TXE: Tx buffer empty interrupt enable.
+ * @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable.
+ * @arg SAI_IT_ERR: Error interrupt enable.
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SAI flag is set or not.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+ * @arg SAI_FLAG_MUTEDET: Mute detection flag.
+ * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+ * @arg SAI_FLAG_FREQ: FIFO request flag.
+ * @arg SAI_FLAG_CNRDY: Codec not ready flag.
+ * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+ * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified SAI pending flag.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+ * @arg SAI_FLAG_MUTEDET: Clear Mute detection
+ * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+ * @arg SAI_FLAG_FREQ: Clear FIFO request
+ * @arg SAI_FLAG_CNRDY: Clear Codec not ready
+ * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+ * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+ *
+ * @retval None
+ */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR |= (__FLAG__))
+
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+/* I/O operation functions *****************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+
+/* Peripheral State functions **************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,665 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sd.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of SD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SD_H
+#define __STM32F4xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#define SD_InitTypeDef SDIO_InitTypeDef
+#define SD_TypeDef SDIO_TypeDef
+
+/**
+ * @brief SDIO Handle Structure definition
+ */
+typedef struct
+{
+ SD_TypeDef *Instance; /*!< SDIO register base address */
+
+ SD_InitTypeDef Init; /*!< SD required parameters */
+
+ HAL_LockTypeDef Lock; /*!< SD locking object */
+
+ uint32_t CardType; /*!< SD card type */
+
+ uint32_t RCA; /*!< SD relative card address */
+
+ uint32_t CSD[4]; /*!< SD card specific data table */
+
+ uint32_t CID[4]; /*!< SD card identification number table */
+
+ __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
+
+ __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
+
+ __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
+
+ __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+
+}SD_HandleTypeDef;
+
+/**
+ * @brief Card Specific Data: CSD Register
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+}HAL_SD_CSDTypedef;
+
+/**
+ * @brief Card Identification Data: CID Register
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+}HAL_SD_CIDTypedef;
+
+/**
+ * @brief SD Card Status returned by ACMD13
+ */
+typedef struct
+{
+ __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
+ __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
+ __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
+ __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
+
+}HAL_SD_CardStatusTypedef;
+
+/**
+ * @brief SD Card information structure
+ */
+typedef struct
+{
+ HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
+ HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
+ uint64_t CardCapacity; /*!< Card capacity */
+ uint32_t CardBlockSize; /*!< Card block size */
+ uint16_t RCA; /*!< SD relative card address */
+ uint8_t CardType; /*!< SD card type */
+
+}HAL_SD_CardInfoTypedef;
+
+/**
+ * @brief SD Error status enumeration Structure definition
+ */
+typedef enum
+{
+/**
+ * @brief SD specific error defines
+ */
+ SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
+ SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */
+ SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
+ SD_DATA_TIMEOUT = (4), /*!< Data timeout */
+ SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
+ SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
+ SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
+ SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
+ SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+ SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */
+ SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */
+ SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
+ SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+ SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
+ SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
+ SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
+ SD_CC_ERROR = (18), /*!< Internal card controller error */
+ SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */
+ SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
+ SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
+ SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
+ SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */
+ SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
+ SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+ SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
+ SD_INVALID_VOLTRANGE = (27),
+ SD_ADDR_OUT_OF_RANGE = (28),
+ SD_SWITCH_ERROR = (29),
+ SD_SDIO_DISABLED = (30),
+ SD_SDIO_FUNCTION_BUSY = (31),
+ SD_SDIO_FUNCTION_FAILED = (32),
+ SD_SDIO_UNKNOWN_FUNCTION = (33),
+
+/**
+ * @brief Standard error defines
+ */
+ SD_INTERNAL_ERROR = (34),
+ SD_NOT_CONFIGURED = (35),
+ SD_REQUEST_PENDING = (36),
+ SD_REQUEST_NOT_APPLICABLE = (37),
+ SD_INVALID_PARAMETER = (38),
+ SD_UNSUPPORTED_FEATURE = (39),
+ SD_UNSUPPORTED_HW = (40),
+ SD_ERROR = (41),
+ SD_OK = (0)
+
+}HAL_SD_ErrorTypedef;
+
+/**
+ * @brief SD Transfer state enumeration structure
+ */
+typedef enum
+{
+ SD_TRANSFER_OK = 0, /*!< Transfer success */
+ SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */
+ SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
+
+}HAL_SD_TransferStateTypedef;
+
+/**
+ * @brief SD Card State enumeration structure
+ */
+typedef enum
+{
+ SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
+ SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */
+ SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */
+ SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */
+ SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */
+ SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */
+ SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */
+ SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */
+ SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
+
+}HAL_SD_CardStateTypedef;
+
+/**
+ * @brief SD Operation enumeration structure
+ */
+typedef enum
+{
+ SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
+ SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */
+ SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */
+ SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
+
+}HAL_SD_OperationTypedef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants
+ * @{
+ */
+
+/**
+ * @brief SD Commands Index
+ */
+#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
+#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
+#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
+#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
+#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
+#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
+#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
+#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
+ for SDHS and SDXC. */
+#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
+ STOP_TRANSMISSION command. */
+#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
+#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
+#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
+#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
+#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
+#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
+#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
+#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
+ system set by switch function command (CMD6). */
+#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
+ Reserved for each command system set by switch function command (CMD6). */
+#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
+#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
+#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
+#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+ the SET_BLOCK_LEN command. */
+#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
+ than a standard command. */
+#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
+ for general purpose/application specific commands. */
+#define SD_CMD_NO_CMD ((uint8_t)64)
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDIO_APP_CMD should be sent before sending these commands.
+ */
+#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+ widths are given in SCR register. */
+#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+ 32bit+CRC data block. */
+#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+ send its operating condition register (OCR) content in the response on the CMD line. */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
+#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
+#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
+#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
+
+/**
+ * @brief Following commands are SD Card Specific security commands.
+ * SD_CMD_APP_CMD should be sent before sending these commands.
+ */
+#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */
+
+/**
+ * @brief Supported SD Memory Cards
+ */
+#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
+#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
+#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
+#define MULTIMEDIA_CARD ((uint32_t)0x00000003)
+#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
+#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
+#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
+#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SD_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SD device.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
+
+/**
+ * @brief Disable the SD device.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
+
+/**
+ * @brief Enable the SDIO DMA transfer.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
+
+/**
+ * @brief Disable the SDIO DMA transfer.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DMA_DISABLE() __SDIO_DMA_DISABLE()
+
+/**
+ * @brief Enable the SD device interrupt.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the SD device interrupt.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified SD flag is set or not.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SD FLAG (SET or RESET).
+ */
+#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the SD's pending flags.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified SD interrupt has occurred or not.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SD IT (SET or RESET).
+ */
+#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)
+
+/**
+ * @brief Clear the SD's interrupt pending bits.
+ * @param __HANDLE__ : SD Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+
+/* I/O operation functions *****************************************************/
+/* Blocking mode: Polling */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
+__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
+__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
+__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
+__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
+__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
+
+/* Non-Blocking mode: DMA */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+
+/* Peripheral Control functions ************************************************/
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
+
+/* Peripheral State functions **************************************************/
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,144 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sdram.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of SDRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SDRAM_H
+#define __STM32F4xx_HAL_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_fmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SDRAM
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/**
+ * @brief HAL SDRAM State structure definition
+ */
+typedef enum
+{
+ HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */
+ HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */
+ HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */
+ HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */
+ HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */
+ HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */
+
+}HAL_SDRAM_StateTypeDef;
+
+/**
+ * @brief SDRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
+
+ __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
+
+ HAL_LockTypeDef Lock; /*!< SDRAM locking object */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SDRAM_HandleTypeDef;
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
+__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
+__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
+
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
+__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
+__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/* SDRAM Control functions *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
+
+/* SDRAM State functions ********************************************************/
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SDRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,445 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SMARTCARD_H
+#define __STM32F4xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref SMARTCARD_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits).*/
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler
+ This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time
+ This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state
+ This parameter can be a value of @ref SmartCard_NACK_State */
+}SMARTCARD_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief HAL SMARTCARD Error Code structure definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
+ HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
+ HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_SMARTCARD_ErrorTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SmartCard Tx Transfer size */
+
+ uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SmartCard Rx Transfer size */
+
+ uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
+
+ __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SMARTCARD Error code */
+}SMARTCARD_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Word_Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) (((LENGTH) == SMARTCARD_WORDLENGTH_8B) || \
+ ((LENGTH) == SMARTCARD_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_1) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_2))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_NONE) || \
+ ((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_NACK_State
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000)
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
+ ((NACK) == SMARTCARD_NACK_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_DMA_Requests
+ * @{
+ */
+
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
+
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+
+#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
+#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
+#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
+#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)
+#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
+#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
+#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
+#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR3 register
+
+ *
+ * @{
+ */
+#define SMARTCARD_IT_PE ((uint32_t)0x10000100)
+#define SMARTCARD_IT_TXE ((uint32_t)0x10000080)
+#define SMARTCARD_IT_TC ((uint32_t)0x10000040)
+#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020)
+#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010)
+#define SMARTCARD_IT_ERR ((uint32_t)0x20000001)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Flushs the Smartcard DR register
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Checks whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+ * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
+ * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
+ * @arg SMARTCARD_FLAG_NE: Noise Error flag
+ * @arg SMARTCARD_FLAG_FE: Framing Error flag
+ * @arg SMARTCARD_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified Smartcard pending flags.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
+ * error) flags are cleared by software sequence: a read operation to
+ * USART_SR register followed by a read operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+/** @brief Enables or disables the specified SmartCard interrupts.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ */
+#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF)
+#define __SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+
+/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ * @param __IT__: specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+
+/** @brief Macros to enable or disable the SmartCard interface.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ */
+#define __SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Macros to enable or disable the SmartCard DMA request.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ * @param __REQUEST__: specifies the SmartCard DMA request.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+ * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ */
+#define __SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
+#define __SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
+
+#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __SMARTCARD_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+
+/* Peripheral State functions **************************************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,474 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spi.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SPI_H
+#define __STM32F4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint32_t Direction; /*!< Specifies the SPI Directional mode state.
+ This parameter can be a value of @ref SPI_Direction_mode */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+}SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
+ HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
+
+}HAL_SPI_StateTypeDef;
+
+/**
+ * @brief HAL SPI Error Code structure definition
+ */
+typedef enum
+{
+ HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
+ HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
+ HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
+ HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
+ HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
+ HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
+ HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
+
+}HAL_SPI_ErrorTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /* SPI registers base address */
+
+ SPI_InitTypeDef Init; /* SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SPI Tx transfer size */
+
+ uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SPI Rx transfer size */
+
+ uint16_t RxXferCount; /* SPI Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
+
+ HAL_LockTypeDef Lock; /* SPI locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
+
+ __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
+
+}SPI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction_mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
+#define SPI_DATASIZE_16BIT SPI_CR1_DFF
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLED SPI_CR2_FRF
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
+ ((MODE) == SPI_TIMODE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_configuration_definition
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flag_definition
+ * @{
+ */
+#define SPI_FLAG_RXNE SPI_SR_RXNE
+#define SPI_FLAG_TXE SPI_SR_TXE
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR
+#define SPI_FLAG_MODF SPI_SR_MODF
+#define SPI_FLAG_OVR SPI_SR_OVR
+#define SPI_FLAG_BSY SPI_SR_BSY
+#define SPI_FLAG_FRE SPI_SR_FRE
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enable or disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Check if the specified SPI interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR))
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
+ (__HANDLE__)->Instance->SR;}while(0)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
+
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
+
+#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+
+/* Peripheral State and Control functions **************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,145 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sram.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of SRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SRAM_H
+#define __STM32F4xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SRAM
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
+
+}HAL_SRAM_StateTypeDef;
+
+/**
+ * @brief SRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */
+
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SRAM_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/* SRAM Control functions ******************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/* SRAM State functions *********************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1454 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_H
+#define __STM32F4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+ * @brief Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a value of @ref TIM_Clock_Filter */
+}TIM_ClockConfigTypeDef;
+
+/**
+ * @brief Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a value of @ref TIM_ClearInput_Filter */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a value of @ref TIM_Trigger_Filter */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+typedef struct
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+}TIM_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants
+ * @{
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision
+ * @{
+ */
+
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State
+ * @{
+ */
+
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Output_Fast_State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Output_Compare_N_State
+ * @{
+ */
+
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define TIM_CHANNEL_3 ((uint32_t)0x0008)
+#define TIM_CHANNEL_4 ((uint32_t)0x000C)
+#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+/**
+ * @}
+ */
+/** @defgroup TIM_Interrupt_definition
+ * @{
+ */
+#define TIM_IT_UPDATE (TIM_DIER_UIE)
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)
+#define TIM_IT_COM (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)
+#define TIM_IT_BREAK (TIM_DIER_BIE)
+
+#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_TRIGGER) || \
+ ((IT) == TIM_IT_BREAK))
+/**
+ * @}
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
+#define TIM_DMA_COM (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update TIM_EGR_UG
+#define TIM_EventSource_CC1 TIM_EGR_CC1G
+#define TIM_EventSource_CC2 TIM_EGR_CC2G
+#define TIM_EventSource_CC3 TIM_EGR_CC3G
+#define TIM_EventSource_CC4 TIM_EGR_CC4G
+#define TIM_EventSource_COM TIM_EGR_COMG
+#define TIM_EventSource_Trigger TIM_EGR_TG
+#define TIM_EventSource_Break TIM_EGR_BG
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition
+ * @{
+ */
+
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
+#define TIM_FLAG_COM (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
+#define TIM_FLAG_BREAK (TIM_SR_BIF)
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+
+#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_TRIGGER) || \
+ ((FLAG) == TIM_FLAG_BREAK) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Clock_Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+/**
+ * @}
+ */
+/** @defgroup TIM_Clock_Filter
+ * @{
+ */
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Filter
+ * @{
+ */
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Lock_level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+/**
+ * @}
+ */
+/** @defgroup TIM_Break_Input_enable_disable
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Break_Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+/**
+ * @}
+ */
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection
+ * @{
+ */
+#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
+#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
+#define TIM_TS_ETRF ((uint32_t)0x0070)
+#define TIM_TS_NONE ((uint32_t)0xFFFF)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+ /** @defgroup TIM_TI1_Selection
+ * @{
+ */
+
+#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1 (0x00000000)
+#define TIM_DMABase_CR2 (0x00000001)
+#define TIM_DMABase_SMCR (0x00000002)
+#define TIM_DMABase_DIER (0x00000003)
+#define TIM_DMABase_SR (0x00000004)
+#define TIM_DMABase_EGR (0x00000005)
+#define TIM_DMABase_CCMR1 (0x00000006)
+#define TIM_DMABase_CCMR2 (0x00000007)
+#define TIM_DMABase_CCER (0x00000008)
+#define TIM_DMABase_CNT (0x00000009)
+#define TIM_DMABase_PSC (0x0000000A)
+#define TIM_DMABase_ARR (0x0000000B)
+#define TIM_DMABase_RCR (0x0000000C)
+#define TIM_DMABase_CCR1 (0x0000000D)
+#define TIM_DMABase_CCR2 (0x0000000E)
+#define TIM_DMABase_CCR3 (0x0000000F)
+#define TIM_DMABase_CCR4 (0x00000010)
+#define TIM_DMABase_BDTR (0x00000011)
+#define TIM_DMABase_DCR (0x00000012)
+#define TIM_DMABase_OR (0x00000013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR) || \
+ ((BASE) == TIM_DMABase_OR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer (0x00000000)
+#define TIM_DMABurstLength_2Transfers (0x00000100)
+#define TIM_DMABurstLength_3Transfers (0x00000200)
+#define TIM_DMABurstLength_4Transfers (0x00000300)
+#define TIM_DMABurstLength_5Transfers (0x00000400)
+#define TIM_DMABurstLength_6Transfers (0x00000500)
+#define TIM_DMABurstLength_7Transfers (0x00000600)
+#define TIM_DMABurstLength_8Transfers (0x00000700)
+#define TIM_DMABurstLength_9Transfers (0x00000800)
+#define TIM_DMABurstLength_10Transfers (0x00000900)
+#define TIM_DMABurstLength_11Transfers (0x00000A00)
+#define TIM_DMABurstLength_12Transfers (0x00000B00)
+#define TIM_DMABurstLength_13Transfers (0x00000C00)
+#define TIM_DMABurstLength_14Transfers (0x00000D00)
+#define TIM_DMABurstLength_15Transfers (0x00000E00)
+#define TIM_DMABurstLength_16Transfers (0x00000F00)
+#define TIM_DMABurstLength_17Transfers (0x00001000)
+#define TIM_DMABurstLength_18Transfers (0x00001100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Handle_index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup Channel_CC_State
+ * @{
+ */
+#define TIM_CCx_ENABLE ((uint32_t)0x0001)
+#define TIM_CCx_DISABLE ((uint32_t)0x0000)
+#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
+#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+
+/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
+
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__))
+
+#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC |= (__PRESC__))
+
+#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+
+/**
+ * @brief Sets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __COUNTER__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __AUTORELOAD__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+
+/**
+ * @brief Sets the TIM Clock Division value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CKD__: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1
+ * @arg TIM_CLOCKDIVISION_DIV2
+ * @arg TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+
+/**
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
+ __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/* Include TIM HAL Extension module */
+#include "stm32f4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Interrupt Handler functions **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Peripheral State functions **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,233 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of TIM HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_EX_H
+#define __STM32F4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+}TIM_BreakDeadTimeConfigTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Remap
+ * @{
+ */
+
+#define TIM_TIM2_TIM8_TRGO (0x00000000)
+#define TIM_TIM2_ETH_PTP (0x00000400)
+#define TIM_TIM2_USBFS_SOF (0x00000800)
+#define TIM_TIM2_USBHS_SOF (0x00000C00)
+#define TIM_TIM5_GPIO (0x00000000)
+#define TIM_TIM5_LSI (0x00000040)
+#define TIM_TIM5_LSE (0x00000080)
+#define TIM_TIM5_RTC (0x000000C0)
+#define TIM_TIM11_GPIO (0x00000000)
+#define TIM_TIM11_HSE (0x00000002)
+
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+
+/* Extnsion Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+
+/* Extension Callback *********************************************************/
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+
+/* Extension Peripheral State functions **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,480 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_uart.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_UART_H
+#define __STM32F4xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
+ Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode */
+
+ uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+ uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling */
+}UART_InitTypeDef;
+
+/**
+ * @brief HAL UART State structures definition
+ */
+typedef enum
+{
+ HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_UART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_UART_StateTypeDef;
+
+/**
+ * @brief HAL UART Error Code structure definition
+ */
+typedef enum
+{
+ HAL_UART_ERROR_NONE = 0x00, /*!< No error */
+ HAL_UART_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_UART_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_UART_ERROR_FE = 0x04, /*!< frame error */
+ HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_UART_ErrorTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* UART registers base address */
+
+ UART_InitTypeDef Init; /* UART communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* UART Tx Transfer size */
+
+ uint16_t TxXferCount; /* UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* UART Rx Transfer size */
+
+ uint16_t RxXferCount; /* UART Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_UART_StateTypeDef State; /* UART communication state */
+
+ __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */
+
+}UART_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants
+ * @{
+ */
+
+/** @defgroup UART_Word_Length
+ * @{
+ */
+#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits
+ * @{
+ */
+#define UART_STOPBITS_1 ((uint32_t)0x00000000)
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity
+ * @{
+ */
+#define UART_PARITY_NONE ((uint32_t)0x00000000)
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+ ((PARITY) == UART_PARITY_EVEN) || \
+ ((PARITY) == UART_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode
+ * @{
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+ * @}
+ */
+
+ /** @defgroup UART_State
+ * @{
+ */
+#define UART_STATE_DISABLE ((uint32_t)0x00000000)
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+ ((SAMPLING) == UART_OVERSAMPLING_8))
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection_Length
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020)
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_functions
+ * @{
+ */
+#define UART_WAKEUPMETHODE_IDLELINE ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHODE_ADDRESSMARK ((uint32_t)0x00000800)
+#define IS_UART_WAKEUPMETHODE(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHODE_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHODE_ADDRESSMARK))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define UART_FLAG_CTS ((uint32_t)0x00000200)
+#define UART_FLAG_LBD ((uint32_t)0x00000100)
+#define UART_FLAG_TXE ((uint32_t)0x00000080)
+#define UART_FLAG_TC ((uint32_t)0x00000040)
+#define UART_FLAG_RXNE ((uint32_t)0x00000020)
+#define UART_FLAG_IDLE ((uint32_t)0x00000010)
+#define UART_FLAG_ORE ((uint32_t)0x00000008)
+#define UART_FLAG_NE ((uint32_t)0x00000004)
+#define UART_FLAG_FE ((uint32_t)0x00000002)
+#define UART_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ *
+ * @{
+ */
+#define UART_IT_PE ((uint32_t)0x10000100)
+#define UART_IT_TXE ((uint32_t)0x10000080)
+#define UART_IT_TC ((uint32_t)0x10000040)
+#define UART_IT_RXNE ((uint32_t)0x10000020)
+#define UART_IT_IDLE ((uint32_t)0x10000010)
+
+#define UART_IT_LBD ((uint32_t)0x20000040)
+#define UART_IT_CTS ((uint32_t)0x30000400)
+
+#define UART_IT_ERR ((uint32_t)0x30000001)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Checks whether the specified UART flag is set or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg UART_FLAG_LBD: LIN Break detection flag
+ * @arg UART_FLAG_TXE: Transmit data register empty flag
+ * @arg UART_FLAG_TC: Transmission Complete flag
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag
+ * @arg UART_FLAG_IDLE: Idle Line detection flag
+ * @arg UART_FLAG_ORE: OverRun Error flag
+ * @arg UART_FLAG_NE: Noise Error flag
+ * @arg UART_FLAG_FE: Framing Error flag
+ * @arg UART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified UART pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg UART_FLAG_LBD: LIN Break detection flag.
+ * @arg UART_FLAG_TC: Transmission Complete flag.
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+/** @brief Enables or disables the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified UART interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define UART_IT_MASK ((uint32_t)0x0000FFFF)
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief Checks whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __IT__: specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
+
+/** @brief macros to enables or disables the UART's one bit sampling method
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (__DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((__DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
+#define __DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (__DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((__DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/* Peripheral State functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,454 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_usart.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_USART_H
+#define __STM32F4xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+}USART_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_USART_StateTypeDef;
+
+/**
+ * @brief HAL USART Error Code structure definition
+ */
+typedef enum
+{
+ HAL_USART_ERROR_NONE = 0x00, /*!< No error */
+ HAL_USART_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_USART_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_USART_ERROR_FE = 0x04, /*!< frame error */
+ HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_USART_ErrorTypeDef;
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ USART_InitTypeDef Init; /* Usart communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to Usart Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* Usart Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /* Usart Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to Usart Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* Usart Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /* Usart Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* Usart Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* Usart Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /* Usart communication state */
+
+ __IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */
+
+}USART_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+/** @defgroup USART_Word_Length
+ * @{
+ */
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+#define USART_STOPBITS_1 ((uint32_t)0x00000000)
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+#define USART_PARITY_NONE ((uint32_t)0x00000000)
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLED ((uint32_t)0x00000000)
+#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
+ ((CLOCK) == USART_CLOCK_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW ((uint32_t)0x00000000)
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup Usart_NACK_State
+ * @{
+ */
+#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK)
+#define USARTNACK_DISABLED ((uint32_t)0x00000000)
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \
+ ((NACK) == USARTNACK_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup Usart_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+
+#define USART_FLAG_TXE ((uint32_t)0x00000080)
+#define USART_FLAG_TC ((uint32_t)0x00000040)
+#define USART_FLAG_RXNE ((uint32_t)0x00000020)
+#define USART_FLAG_IDLE ((uint32_t)0x00000010)
+#define USART_FLAG_ORE ((uint32_t)0x00000008)
+#define USART_FLAG_NE ((uint32_t)0x00000004)
+#define USART_FLAG_FE ((uint32_t)0x00000002)
+#define USART_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ *
+ * @{
+ */
+#define USART_IT_PE ((uint32_t)0x10000100)
+#define USART_IT_TXE ((uint32_t)0x10000080)
+#define USART_IT_TC ((uint32_t)0x10000040)
+#define USART_IT_RXNE ((uint32_t)0x10000020)
+#define USART_IT_IDLE ((uint32_t)0x10000010)
+
+#define USART_IT_LBD ((uint32_t)0x20000040)
+#define USART_IT_CTS ((uint32_t)0x30000400)
+
+#define USART_IT_ERR ((uint32_t)0x30000001)
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Checks whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified Smartcard pending flags.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/** @brief Enables or disables the specified Usart interrupts.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified Usart interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define USART_IT_MASK ((uint32_t)0x0000FFFF)
+#define __USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
+#define __USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
+
+
+/** @brief Checks whether the specified Usart interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __IT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
+
+#define __USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __USART_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+
+/* Peripheral State functions **************************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,252 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_wwdg.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of WWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_WWDG_H
+#define __STM32F4xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief WWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */
+ HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */
+ HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */
+ HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */
+ HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */
+
+}HAL_WWDG_StateTypeDef;
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number lower than Max_Data = 0x80 */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+}WWDG_InitTypeDef;
+
+/**
+ * @brief WWDG handle Structure definition
+ */
+typedef struct
+{
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< WWDG locking object */
+
+ __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
+
+}WWDG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_BitAddress_AliasRegion
+ * @{
+ */
+
+/* --- CFR Register ---*/
+/* Alias word address of EWI bit */
+#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Interrupt_definition
+ * @{
+ */
+#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI)
+
+#define IS_WWDG_IT(IT) ((IT) == WWDG_IT_EWI)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF ((uint32_t)0x0001) /*!< Early wakeup interrupt flag */
+
+#define IS_WWDG_FLAG(FLAG) ((FLAG) == WWDG_FLAG_EWIF))
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 ((uint32_t)0x00000080) /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 ((uint32_t)0x00000100) /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 ((uint32_t)0x00000180) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_PRESCALER_1) || \
+ ((PRESCALER) == WWDG_PRESCALER_2) || \
+ ((PRESCALER) == WWDG_PRESCALER_4) || \
+ ((PRESCALER) == WWDG_PRESCALER_8))
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Window
+ * @{
+ */
+#define IS_WWDG_WINDOW(WINDOW) ((WINDOW) <= 0x7F)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Counter
+ * @{
+ */
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA)
+
+/**
+ * @brief Gets the selected WWDG's flag status.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the WWDG's pending flags.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+ * @brief Enables the WWDG early wakeup interrupt.
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
+__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+
+/* Peripheral State functions **************************************************/
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1388 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of FMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FMC_H
+#define __STM32F4xx_LL_FMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMC
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
+#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
+#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
+
+#define FMC_NORSRAM_DEVICE FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+#define FMC_NAND_DEVICE FMC_Bank2_3
+#define FMC_PCCARD_DEVICE FMC_Bank4
+#define FMC_SDRAM_DEVICE FMC_Bank5_6
+
+
+/**
+ * @brief FMC_NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FMC_Wrap_Mode */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+ This parameter can be a value of @ref FMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FMC_Write_Burst */
+
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
+
+}FMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FMC_NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FMC_Access_Mode */
+
+}FMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_NAND_InitTypeDef;
+
+/**
+ * @brief FMC_NAND_PCCARD Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_PCCARD_InitTypeDef;
+
+/**
+ * @brief FMC_SDRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_SDRAM_Bank */
+
+ uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
+ This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
+
+ uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
+ This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
+
+ uint32_t MemoryDataWidth; /*!< Defines the memory device width.
+ This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
+
+ uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
+ This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
+
+ uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
+ This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
+
+ uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
+ This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
+
+ uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
+ to disable the clock before changing frequency.
+ This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
+
+ uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
+ commands during the CAS latency and stores data in the Read FIFO.
+ This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
+
+ uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
+ This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
+
+}FMC_SDRAM_InitTypeDef;
+
+/**
+ * @brief FMC_SDRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
+ an active or Refresh command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
+ issuing the Activate command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
+ cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
+ and the delay between two consecutive Refresh commands in number of
+ memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
+ in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
+ command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+}FMC_SDRAM_TimingTypeDef;
+
+/**
+ * @brief SDRAM command parameters structure definition
+ */
+typedef struct
+{
+ uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
+ This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
+
+ uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
+ This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
+
+ uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
+ in auto refresh mode.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
+
+}FMC_SDRAM_CommandTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMC_NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Bank
+ * @{
+ */
+#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+
+#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
+ ((BANK) == FMC_NORSRAM_BANK2) || \
+ ((BANK) == FMC_NORSRAM_BANK3) || \
+ ((BANK) == FMC_NORSRAM_BANK4))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Memory_Type
+ * @{
+ */
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
+
+#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
+ ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((MEMORY) == FMC_MEMORY_TYPE_NOR))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Data_Width
+ * @{
+ */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Flash_Access
+ * @{
+ */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Burst_Access_Mode
+ * @{
+ */
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
+
+#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_Wait_Signal_Polarity
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
+
+#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wrap_Mode
+ * @{
+ */
+#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
+
+#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
+ ((MODE) == FMC_WRAP_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Timing
+ * @{
+ */
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation
+ * @{
+ */
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
+
+#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+
+#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Extended_Mode
+ * @{
+ */
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+
+#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((MODE) == FMC_EXTENDED_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait
+ * @{
+ */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+
+#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst
+ * @{
+ */
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
+
+#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
+ ((BURST) == FMC_WRITE_BURST_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Continous_Clock
+ * @{
+ */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+
+#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Setup_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Hold_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Setup_Time
+ * @{
+ */
+#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Bus_Turn_around_Duration
+ * @{
+ */
+#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_CLK_Division
+ * @{
+ */
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Latency
+ * @{
+ */
+#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Access_Mode
+ * @{
+ */
+#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
+#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
+#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+
+#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
+ ((MODE) == FMC_ACCESS_MODE_B) || \
+ ((MODE) == FMC_ACCESS_MODE_C) || \
+ ((MODE) == FMC_ACCESS_MODE_D))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Controller
+ * @{
+ */
+
+/** @defgroup FMC_NAND_Bank
+ * @{
+ */
+#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+
+#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
+ ((BANK) == FMC_NAND_BANK3))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_feature
+ * @{
+ */
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCR_Memory_Type
+ * @{
+ */
+#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Data_Width
+ * @{
+ */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+
+#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC
+ * @{
+ */
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
+
+#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FMC_NAND_ECC_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC_Page_Size
+ * @{
+ */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
+
+#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Setup_Time
+ * @{
+ */
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Controller
+ * @{
+ */
+
+/** @defgroup FMC_SDRAM_Bank
+ * @{
+ */
+#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
+
+#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
+ ((BANK) == FMC_SDRAM_BANK2))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Column_Bits_number
+ * @{
+ */
+#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
+
+#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Row_Bits_number
+ * @{
+ */
+#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
+#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
+#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
+
+#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Memory_Bus_Width
+ * @{
+ */
+#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+
+#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Internal_Banks_Number
+ * @{
+ */
+#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
+
+#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
+ ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_CAS_Latency
+ * @{
+ */
+#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
+#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
+#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
+
+#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Write_Protection
+ * @{
+ */
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
+
+#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
+ ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Clock_Period
+ * @{
+ */
+#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
+#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
+
+#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Read_Burst
+ * @{
+ */
+#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
+
+#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
+ ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay
+ * @{
+ */
+#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
+#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
+#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
+
+#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_LoadToActive_Delay
+ * @{
+ */
+#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
+ * @{
+ */
+#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_SelfRefresh_Time
+ * @{
+ */
+#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_RowCycle_Delay
+ * @{
+ */
+#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Write_Recovery_Time
+ * @{
+ */
+#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_RP_Delay
+ * @{
+ */
+#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_RCD_Delay
+ * @{
+ */
+#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Command_Mode
+ * @{
+ */
+#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
+#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
+#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
+#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
+
+#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
+ ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Command_Target
+ * @{
+ */
+#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
+#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
+#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
+
+#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_AutoRefresh_Number
+ * @{
+ */
+#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_ModeRegister_Definition
+ * @{
+ */
+#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Refresh_rate
+ * @{
+ */
+#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Mode_Status
+ * @{
+ */
+#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
+#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
+#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Device_Instance
+ * @{
+ */
+#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
+ * @{
+ */
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Device_Instance
+ * @{
+ */
+#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Device_Instance
+ * @{
+ */
+#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Device_Instance
+ * @{
+ */
+#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt_definition
+ * @brief FMC Interrupt definition
+ * @{
+ */
+#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
+#define FMC_IT_LEVEL ((uint32_t)0x00000010)
+#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
+#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
+
+#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
+ ((IT) == FMC_IT_LEVEL) || \
+ ((IT) == FMC_IT_FALLING_EDGE) || \
+ ((IT) == FMC_IT_REFRESH_ERROR))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Flag_definition
+ * @brief FMC Flag definition
+ * @{
+ */
+#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
+#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
+#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
+#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
+#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
+
+#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
+ ((FLAG) == FMC_FLAG_LEVEL) || \
+ ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
+ ((FLAG) == FMC_FLAG_FEMPT) || \
+ ((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) || \
+ ((FLAG) == FMC_SDRAM_FLAG_BUSY))
+
+#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FMC_NOR_Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__: FMC_NORSRAM Instance
+ * @param __BANK__: FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__: FMC_NORSRAM Instance
+ * @param __BANK__: FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt
+ * @brief macros to handle FMC interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND handle
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND handle
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND handle
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __FLAG__: FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __FLAG__: FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
+/**
+ * @brief Enable the SDRAM device interrupt.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+ * @retval None
+ */
+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the SDRAM device interrupt.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+ * @retval None
+ */
+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the SDRAM device.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __FLAG__: FMC_SDRAM flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
+ * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the SDRAM device.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __FLAG__: FMC_SDRAM flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
+ * @retval None
+ */
+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* FMC_NORSRAM Controller functions *******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/* FMC_NORSRAM Control functions */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/* FMC_NAND Controller functions **********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/* FMC_NAND Control functions */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/* FMC_PCCARD Controller functions ********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+
+/* FMC_SDRAM Controller functions *********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+
+/* FMC_SDRAM Control functions */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1045 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fsmc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of FSMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FSMC_H
+#define __STM32F4xx_LL_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
+#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
+
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
+
+/**
+ * @brief FSMC_NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+}FSMC_NORSRAM_InitTypeDef;
+
+
+/**
+ * @brief FSMC_NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
+
+}FSMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FSMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FSMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FSMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_NAND_InitTypeDef;
+
+/**
+ * @brief FSMC_NAND_PCCARD Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FSMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_PCCARD_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_NORSRAM_Bank
+ * @{
+ */
+#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
+#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
+#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
+ ((BANK) == FSMC_NORSRAM_BANK2) || \
+ ((BANK) == FSMC_NORSRAM_BANK3) || \
+ ((BANK) == FSMC_NORSRAM_BANK4))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+
+#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Memory_Type
+ * @{
+ */
+
+#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
+#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
+
+
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
+ ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((MEMORY) == FSMC_MEMORY_TYPE_NOR))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_Data_Width
+ * @{
+ */
+
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_Flash_Access
+ * @{
+ */
+#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
+
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_Wait_Signal_Polarity
+ * @{
+ */
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
+
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode
+ * @{
+ */
+#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
+
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
+ ((MODE) == FSMC_WRAP_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing
+ * @{
+ */
+#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+ ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation
+ * @{
+ */
+#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
+
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
+ ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal
+ * @{
+ */
+#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
+ ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode
+ * @{
+ */
+#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
+ ((MODE) == FSMC_EXTENDED_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_AsynchronousWait
+ * @{
+ */
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst
+ * @{
+ */
+
+#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
+
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
+ ((BURST) == FSMC_WRITE_BURST_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Continous_Clock
+ * @{
+ */
+
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+
+#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Setup_Time
+ * @{
+ */
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time
+ * @{
+ */
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time
+ * @{
+ */
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration
+ * @{
+ */
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_CLK_Division
+ * @{
+ */
+#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Latency
+ * @{
+ */
+#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Access_Mode
+ * @{
+ */
+#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
+#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
+#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
+ ((MODE) == FSMC_ACCESS_MODE_B) || \
+ ((MODE) == FSMC_ACCESS_MODE_C) || \
+ ((MODE) == FSMC_ACCESS_MODE_D))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_NAND_Bank
+ * @{
+ */
+#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
+ ((BANK) == FSMC_NAND_BANK3))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_feature
+ * @{
+ */
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCR_Memory_Type
+ * @{
+ */
+#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Data_Width
+ * @{
+ */
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC
+ * @{
+ */
+#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
+
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FSMC_NAND_ECC_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC_Page_Size
+ * @{
+ */
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
+#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
+#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
+#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
+#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
+
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Setup_Time
+ * @{
+ */
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_NORSRAM_Device_Instance
+ * @{
+ */
+#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
+ * @{
+ */
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+ * @}
+ */
+
+ /** @defgroup FSMC_NAND_Device_Instance
+ * @{
+ */
+#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Device_Instance
+ * @{
+ */
+#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Interrupt_definition
+ * @brief FSMC Interrupt definition
+ * @{
+ */
+#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
+#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
+#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
+#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
+
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \
+ ((IT) == FSMC_IT_LEVEL) || \
+ ((IT) == FSMC_IT_FALLING_EDGE) || \
+ ((IT) == FSMC_IT_REFRESH_ERROR))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Flag_definition
+ * @brief FSMC Flag definition
+ * @{
+ */
+#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
+#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
+#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
+
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \
+ ((FLAG) == FSMC_FLAG_LEVEL) || \
+ ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
+ ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/** @defgroup FSMC_NOR_Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_NAND_Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Interrupt
+ * @brief macros to handle FSMC interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __FLAG__: FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __FLAG__: FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* FSMC_NORSRAM Controller functions ******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/* FSMC_NORSRAM Control functions */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/* FSMC_NAND Controller functions *********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/* FSMC_NAND Control functions */
+HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/* FSMC_PCCARD Controller functions *******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
+
+/* FSMC APIs, macros and typedefs redefinition */
+#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
+#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
+
+#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
+#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
+#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
+#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
+#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
+#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
+
+#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
+#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
+
+#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
+#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
+#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
+
+#define FMC_NAND_Init FSMC_NAND_Init
+#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
+#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
+#define FMC_NAND_DeInit FSMC_NAND_DeInit
+#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
+#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
+#define FMC_NAND_GetECC FSMC_NAND_GetECC
+#define FMC_PCCARD_Init FSMC_PCCARD_Init
+#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
+#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
+#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
+#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
+
+#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
+#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
+#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
+#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
+#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
+#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
+#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
+#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
+#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
+#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
+#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
+#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
+
+#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
+#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
+
+#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
+#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
+#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
+#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
+
+#define FMC_NAND_BANK2 FSMC_NAND_BANK2
+
+#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
+#define FMC_IT_LEVEL FSMC_IT_LEVEL
+#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
+#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
+
+#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
+#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
+#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
+#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FSMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,940 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_sdmmc.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of SDMMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SDMMC_H
+#define __STM32F4xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_Driver
+ * @{
+ */
+
+/** @addtogroup SDMMC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SDMMC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t BusWide; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+}SDIO_InitTypeDef;
+
+
+/**
+ * @brief SDIO Command Control structure
+ */
+typedef struct
+{
+ uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register. */
+
+ uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
+ Max_Data = 64 */
+
+ uint32_t Response; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
+}SDIO_CmdInitTypeDef;
+
+
+/**
+ * @brief SDIO Data Control structure
+ */
+typedef struct
+{
+ uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
+}SDIO_DataInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SDIO_Clock_Edge
+ * @{
+ */
+#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
+#define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
+
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
+ ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Bypass
+ * @{
+ */
+#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
+
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
+ ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Power_Save
+ * @{
+ */
+#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
+
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
+ ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Bus_Wide
+ * @{
+ */
+#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
+#define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
+#define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
+
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
+ ((WIDE) == SDIO_BUS_WIDE_4B) || \
+ ((WIDE) == SDIO_BUS_WIDE_8B))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
+#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
+
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
+ ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Division
+ * @{
+ */
+#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Command_Index
+ * @{
+ */
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Type
+ * @{
+ */
+#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
+#define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
+#define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
+
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
+ ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDIO_RESPONSE_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+#define SDIO_WAIT_NO ((uint32_t)0x00000000)
+#define SDIO_WAIT_IT ((uint32_t)0x00000100)
+#define SDIO_WAIT_PEND ((uint32_t)0x00000200)
+
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
+ ((WAIT) == SDIO_WAIT_IT) || \
+ ((WAIT) == SDIO_WAIT_PEND))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_CPSM_State
+ * @{
+ */
+#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
+
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
+ ((CPSM) == SDIO_CPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Registers
+ * @{
+ */
+#define SDIO_RESP1 ((uint32_t)0x00000000)
+#define SDIO_RESP2 ((uint32_t)0x00000004)
+#define SDIO_RESP3 ((uint32_t)0x00000008)
+#define SDIO_RESP4 ((uint32_t)0x0000000C)
+
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
+ ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || \
+ ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Length
+ * @{
+ */
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Block_Size
+ * @{
+ */
+#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
+#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
+#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
+#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
+#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
+#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
+#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
+#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
+#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
+#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
+#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
+#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
+#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
+#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
+#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
+
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Direction
+ * @{
+ */
+#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
+
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
+ ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Type
+ * @{
+ */
+#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
+
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
+ ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_DPSM_State
+ * @{
+ */
+#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
+
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
+ ((DPSM) == SDIO_DPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Read_Wait_Mode
+ * @{
+ */
+#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
+#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
+
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
+ ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Interrupt_sources
+ * @{
+ */
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Flags
+ * @{
+ */
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
+
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \
+ ((FLAG) == SDIO_FLAG_CMDREND) || \
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \
+ ((FLAG) == SDIO_FLAG_DATAEND) || \
+ ((FLAG) == SDIO_FLAG_STBITERR) || \
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \
+ ((FLAG) == SDIO_FLAG_CMDACT) || \
+ ((FLAG) == SDIO_FLAG_TXACT) || \
+ ((FLAG) == SDIO_FLAG_RXACT) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \
+ ((FLAG) == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+ ((IT) == SDIO_IT_DCRCFAIL) || \
+ ((IT) == SDIO_IT_CTIMEOUT) || \
+ ((IT) == SDIO_IT_DTIMEOUT) || \
+ ((IT) == SDIO_IT_TXUNDERR) || \
+ ((IT) == SDIO_IT_RXOVERR) || \
+ ((IT) == SDIO_IT_CMDREND) || \
+ ((IT) == SDIO_IT_CMDSENT) || \
+ ((IT) == SDIO_IT_DATAEND) || \
+ ((IT) == SDIO_IT_STBITERR) || \
+ ((IT) == SDIO_IT_DBCKEND) || \
+ ((IT) == SDIO_IT_CMDACT) || \
+ ((IT) == SDIO_IT_TXACT) || \
+ ((IT) == SDIO_IT_RXACT) || \
+ ((IT) == SDIO_IT_TXFIFOHE) || \
+ ((IT) == SDIO_IT_RXFIFOHF) || \
+ ((IT) == SDIO_IT_TXFIFOF) || \
+ ((IT) == SDIO_IT_RXFIFOF) || \
+ ((IT) == SDIO_IT_TXFIFOE) || \
+ ((IT) == SDIO_IT_RXFIFOE) || \
+ ((IT) == SDIO_IT_TXDAVL) || \
+ ((IT) == SDIO_IT_RXDAVL) || \
+ ((IT) == SDIO_IT_SDIOIT) || \
+ ((IT) == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SDIO_Instance_definition
+ * @{
+ */
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* ------------ SDIO registers bit address in the alias region -------------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+
+/* --- PWRCTRL Register ---*/
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
+
+/* SD FLASH SDIO Interface */
+#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
+
+/* SDIO Intialization Frequency (400KHz max) */
+#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
+
+/* SDIO Data Transfer Frequency (25MHz max) */
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+
+/** @defgroup SDIO_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SDIO device.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SDIO device.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SDIO DMA transfer.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SDIO DMA transfer.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SDIO device interrupt.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the SDIO device interrupt.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SDIO_FLAG (SET or RESET).
+ */
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+
+
+/**
+ * @brief Clears the SDIO's pending flags.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SDIO_IT (SET or RESET).
+ */
+#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clears the SDIO's interrupt pending bits.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
+
+/**
+ * @brief Disable Start the SD I/O Read Wait operations.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
+
+/**
+ * @brief Disable Stop the SD I/O Read Wait operations.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
+
+/**
+ * @brief Enable the SD I/O Mode Operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SD I/O Mode Operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SD I/O Suspend command sending.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
+
+/**
+ * @brief Disable the SD I/O Suspend command sending.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
+
+/**
+ * @brief Enable the command completion signal.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
+
+/**
+ * @brief Disable the command completion signal.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
+
+/**
+ * @brief Enable the CE-ATA interrupt.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
+
+/**
+ * @brief Disable the CE-ATA interrupt.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
+
+/**
+ * @brief Enable send CE-ATA command (CMD61).
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
+
+/**
+ * @brief Disable send CE-ATA command (CMD61).
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
+
+/* I/O operation functions *****************************************************/
+/* Blocking mode: Polling */
+uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
+
+/* SDIO IO Cards mode management functions */
+HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SDMMC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,459 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_usb.h
+ * @author MCD Application Team
+ * @version V1.0.0RC2
+ * @date 04-February-2014
+ * @brief Header file of USB Core HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_USB_H
+#define __STM32F4xx_LL_USB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+ * @{
+ */
+
+/** @addtogroup USB_Core
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief USB Mode definition
+ */
+typedef enum
+{
+ USB_OTG_DEVICE_MODE = 0,
+ USB_OTG_HOST_MODE = 1,
+ USB_OTG_DRD_MODE = 2
+
+}USB_OTG_ModeTypeDef;
+
+/**
+ * @brief URB States definition
+ */
+typedef enum {
+ URB_IDLE = 0,
+ URB_DONE,
+ URB_NOTREADY,
+ URB_NYET,
+ URB_ERROR,
+ URB_STALL
+
+}USB_OTG_URBStateTypeDef;
+
+/**
+ * @brief Host channel States definition
+ */
+typedef enum {
+ HC_IDLE = 0,
+ HC_XFRC,
+ HC_HALTED,
+ HC_NAK,
+ HC_NYET,
+ HC_STALL,
+ HC_XACTERR,
+ HC_BBLERR,
+ HC_DATATGLERR
+
+}USB_OTG_HCStateTypeDef;
+
+/**
+ * @brief PCD Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t Host_channels; /*!< Host Channels number.
+ This parameter Depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
+
+ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
+ This parameter can be any value of @ref USB_EP0_MPS_ */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref USB_Core_PHY_ */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+
+ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+
+ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+
+ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+
+}USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_EP_Type_ */
+
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t even_odd_frame; /*!< IFrame parity
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint16_t tx_fifo_num; /*!< Transmission FIFO number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+
+}USB_OTG_EPTypeDef;
+
+typedef struct
+{
+ uint8_t dev_addr ; /*!< USB device address.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
+
+ uint8_t ch_num; /*!< Host channel number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_num; /*!< Endpoint number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t speed; /*!< USB Host speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
+
+ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
+
+ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
+
+ uint8_t ep_type; /*!< Endpoint Type.
+ This parameter can be any value of @ref USB_EP_Type_ */
+
+ uint16_t max_packet; /*!< Endpoint Max packet size.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t data_pid; /*!< Initial data PID.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+
+ uint32_t xfer_len; /*!< Current transfer length. */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
+
+ uint8_t toggle_in; /*!< IN transfer current toggle flag.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t toggle_out; /*!< OUT transfer current toggle flag
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
+
+ uint32_t ErrCnt; /*!< Host channel error count.*/
+
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+
+}USB_OTG_HCTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup USB_Core_Mode_
+ * @{
+ */
+#define USB_OTG_MODE_DEVICE 0
+#define USB_OTG_MODE_HOST 1
+#define USB_OTG_MODE_DRD 2
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_Speed_
+ * @{
+ */
+#define USB_OTG_SPEED_HIGH 0
+#define USB_OTG_SPEED_HIGH_IN_FULL 1
+#define USB_OTG_SPEED_LOW 2
+#define USB_OTG_SPEED_FULL 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_PHY_
+ * @{
+ */
+#define USB_OTG_ULPI_PHY 1
+#define USB_OTG_EMBEDDED_PHY 2
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_MPS_
+ * @{
+ */
+#define USB_OTG_HS_MAX_PACKET_SIZE 512
+#define USB_OTG_FS_MAX_PACKET_SIZE 64
+#define USB_OTG_MAX_EP0_SIZE 64
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_Phy_Frequency_
+ * @{
+ */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)
+/**
+ * @}
+ */
+
+/** @defgroup USB_CORE_Frame_Interval_
+ * @{
+ */
+#define DCFG_FRAME_INTERVAL_80 0
+#define DCFG_FRAME_INTERVAL_85 1
+#define DCFG_FRAME_INTERVAL_90 2
+#define DCFG_FRAME_INTERVAL_95 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP0_MPS_
+ * @{
+ */
+#define DEP0CTL_MPS_64 0
+#define DEP0CTL_MPS_32 1
+#define DEP0CTL_MPS_16 2
+#define DEP0CTL_MPS_8 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP_Speed_
+ * @{
+ */
+#define EP_SPEED_LOW 0
+#define EP_SPEED_FULL 1
+#define EP_SPEED_HIGH 2
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP_Type_
+ * @{
+ */
+#define EP_TYPE_CTRL 0
+#define EP_TYPE_ISOC 1
+#define EP_TYPE_BULK 2
+#define EP_TYPE_INTR 3
+#define EP_TYPE_MSK 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_STS_Defines_
+ * @{
+ */
+#define STS_GOUT_NAK 1
+#define STS_DATA_UPDT 2
+#define STS_XFER_COMP 3
+#define STS_SETUP_COMP 4
+#define STS_SETUP_UPDT 6
+/**
+ * @}
+ */
+
+/** @defgroup HCFG_SPEED_Defines_
+ * @{
+ */
+#define HCFG_30_60_MHZ 0
+#define HCFG_48_MHZ 1
+#define HCFG_6_MHZ 2
+/**
+ * @}
+ */
+
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_
+ * @{
+ */
+#define HPRT0_PRTSPD_HIGH_SPEED 0
+#define HPRT0_PRTSPD_FULL_SPEED 1
+#define HPRT0_PRTSPD_LOW_SPEED 2
+/**
+ * @}
+ */
+
+#define HCCHAR_CTRL 0
+#define HCCHAR_ISOC 1
+#define HCCHAR_BULK 2
+#define HCCHAR_INTR 3
+
+#define HC_PID_DATA0 0
+#define HC_PID_DATA2 1
+#define HC_PID_DATA1 2
+#define HC_PID_SETUP 3
+
+#define GRXSTS_PKTSTS_IN 2
+#define GRXSTS_PKTSTS_IN_XFER_COMP 3
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
+#define GRXSTS_PKTSTS_CH_HALTED 7
+
+#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
+#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+
+#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+
+/* Exported macro ------------------------------------------------------------*/
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F401RE/system_stm32f4xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.0.0RC6
+ * @date 03-February-2014
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/PeripheralNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/PinNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,171 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// MODE (see GPIOMode_TypeDef structure)
+// OTYPE (see GPIOOType_TypeDef structure)
+// PUPD (see GPIOPuPd_TypeDef structure)
+// AFNUM (see AF_mapping constant table, 0xFF is not used)
+#define STM_PIN_DATA(MODE, OTYPE, PUPD, AFNUM) (((AFNUM)<<8)|((PUPD)<<4)|((OTYPE)<<2)|((MODE)<<0))
+#define STM_PIN_MODE(X) (((X)>>0) & 0x3)
+#define STM_PIN_OTYPE(X) (((X)>>2) & 0x1)
+#define STM_PIN_PUPD(X) (((X)>>4) & 0x3)
+#define STM_PIN_AFNUM(X) (((X)>>8) & 0xF)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = PC_1,
+ A5 = PC_0,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = PC_7,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ USER_BUTTON = PC_13,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/PortNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortH = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/misc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l1xx_hd.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LR_IROM1 0x08000000 0x80000 { ; load region size_region (512 KB)
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x124) (0x14000-0x124) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_adc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_aes.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_aes_util.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_comp.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_crc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_dac.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_dbgmcu.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_dma.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_exti.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_flash.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_flash_ramfunc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_fsmc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_gpio.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_i2c.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_iwdg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_lcd.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_opamp.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_pwr.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_rcc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_rtc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_sdio.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_spi.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_syscfg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_tim.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_usart.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_wwdg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/system_stm32l1xx.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/misc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l1xx_hd.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LR_IROM1 0x08000000 0x80000 { ; load region size_region (512 KB)
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x124) (0x14000-0x124) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_adc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_aes.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_aes_util.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_comp.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_crc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_dac.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_dbgmcu.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_dma.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_exti.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_flash.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_flash_ramfunc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_fsmc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_gpio.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_i2c.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_iwdg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_lcd.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_opamp.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_pwr.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_rcc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_rtc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_sdio.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_spi.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_syscfg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_tim.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_usart.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_wwdg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/system_stm32l1xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_L152RE/cmsis.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l1xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/cmsis_nvic.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F152RE
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
+// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM (see scatter file)
+#define NVIC_NUM_VECTORS 73
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/core_cm0.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/core_cm0plus.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/core_cm3.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/core_cm4.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/core_cm4_simd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/core_cmFunc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/core_cmInstr.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_L152RE/device.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 0 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +//#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/gpio_object.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint16_t *reg_in;
+ __IO uint16_t *reg_set;
+ __IO uint16_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value) {
+ *obj->reg_set = obj->mask;
+ }
+ else {
+ *obj->reg_clr = obj->mask;
+ }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/misc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,202 @@
+/**
+ ******************************************************************************
+ * @file misc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete STM32 Devices IRQ Channels list, please
+ refer to stm32l1xx.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ *
+@verbatim
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endverbatim
+*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/objects.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint16_t *reg_in;
+ __IO uint16_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct dac_s {
+ DACName dac;
+ PinName channel;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+};
+
+struct i2c_s {
+ I2CName i2c;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,6677 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32L1xx High-density, Medium-density,
+ * Medium-density and XL-density Plus devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx
+ * @{
+ */
+
+#ifndef __STM32L1XX_H
+#define __STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
+
+/* #define STM32L1XX_MD */ /*!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
+ STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx,
+ STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA,
+ STM32L152x8xxA and STM32L152xBxxA.
+ - Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
+ STM32L100x8xx and STM32L100xBxx. */
+
+/* #define STM32L1XX_MDP */ /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx
+ - Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */
+
+/* #define STM32L1XX_HD */ /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
+
+#define STM32L1XX_XL /*!< Ultra Low Power XL-density devices: STM32L151xExx, STM32L152xExx and STM32L162xExx */
+#endif
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#endif
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_STDPERIPH_DRIVER
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif
+
+/**
+ * @brief STM32L1xx Standard Peripheral Library version number V1.3.0
+ */
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32L1XX_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
+#define __MPU_PRESENT 1 /*!< STM32L1 provides MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32L1 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32L specific Interrupt Numbers ***********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
+ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
+ DAC_IRQn = 21, /*!< DAC Interrupt */
+ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ LCD_IRQn = 24, /*!< LCD Interrupt */
+ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
+ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
+ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
+
+#ifdef STM32L1XX_MD
+ TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
+#endif /* STM32L1XX_MD */
+
+#ifdef STM32L1XX_MDP
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif /* STM32L1XX_MDP */
+
+#ifdef STM32L1XX_HD
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ SDIO_IRQn = 45, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 48, /*!< UART4 global Interrupt */
+ UART5_IRQn = 49, /*!< UART5 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif /* STM32L1XX_HD */
+
+#ifdef STM32L1XX_XL
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 48, /*!< UART4 global Interrupt */
+ UART5_IRQn = 49, /*!< UART5 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif /* STM32L1XX_XL */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32l1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM )
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+ dialog.
+*/
+ #define __RAM_FUNC FLASH_Status
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+ #define __RAM_FUNC __ramfunc FLASH_Status
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".data")))".
+*/
+ #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
+
+#elif defined ( __TASKING__ )
+/* TASKING Compiler
+ ----------------
+ RAM functions are defined using a specific toolchain pragma. This pragma is
+ defined in the stm32l1xx_flash_ramfunc.c
+*/
+ #define __RAM_FUNC FLASH_Status
+
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
+ __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+ uint32_t RESERVED[23]; /*!< Reserved, 0x24 */
+ __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
+ __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
+ __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
+ __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
+ __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
+ __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
+} OB_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ uint16_t RESERVED1; /*!< Reserved, 0x12 */
+ __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ uint16_t RESERVED2; /*!< Reserved, 0x16 */
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+#if defined (STM32L1XX_HD) || defined (STM32L1XX_XL)
+ __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ uint16_t RESERVED3; /*!< Reserved, 0x2A */
+#endif
+} GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief LCD
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
+ __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
+} RCC_TypeDef;
+
+/**
+ * @brief Routing Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x04 */
+ __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x08 */
+ __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x0C */
+ __IO uint32_t HYSCR1; /*!< RI hysteresis control register 1, Address offset: 0x10 */
+ __IO uint32_t HYSCR2; /*!< RI Hysteresis control register 2, Address offset: 0x14 */
+ __IO uint32_t HYSCR3; /*!< RI Hysteresis control register 3, Address offset: 0x18 */
+ __IO uint32_t HYSCR4; /*!< RI Hysteresis control register 4, Address offset: 0x1C */
+ __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x20 */
+ __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x24 */
+ __IO uint32_t CICR1; /*!< RI Channel identification for capture register 1, Address offset: 0x28 */
+ __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x2C */
+ __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x30 */
+ __IO uint32_t CICR2; /*!< RI Channel identification for capture register 2, Address offset: 0x34 */
+ __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x38 */
+ __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x3C */
+ __IO uint32_t CICR3; /*!< RI Channel identification for capture register3 , Address offset: 0x40 */
+ __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x44 */
+ __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x48 */
+ __IO uint32_t CICR4; /*!< RI Channel identification for capture register 4, Address offset: 0x4C */
+ __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x50 */
+ __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x54 */
+ __IO uint32_t CICR5; /*!< RI Channel identification for capture register 5, Address offset: 0x58 */
+} RI_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ uint16_t RESERVED10; /*!< Reserved, 0x2A */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12; /*!< Reserved, 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17; /*!< Reserved, 0x44 */
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ uint16_t RESERVED18; /*!< Reserved, 0x4A */
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ uint16_t RESERVED19; /*!< Reserved, 0x4E */
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
+ uint16_t RESERVED20; /*!< Reserved, 0x52 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)
+#define RI_BASE (APB1PERIPH_BASE + 0x7C04)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)
+
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2700)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800)
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define RCC_BASE (AHBPERIPH_BASE + 0x3800)
+
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
+
+#define DMA2_BASE (AHBPERIPH_BASE + 0x6400)
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
+
+#define AES_BASE ((uint32_t)0x50060000)
+
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define LCD ((LCD_TypeDef *) LCD_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define RI ((RI_TypeDef *) RI_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+
+#define AES ((AES_TypeDef *) AES_BASE)
+
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
+#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
+#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
+#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
+#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
+
+#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
+#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
+#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
+#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
+#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
+#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
+#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
+#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
+#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
+#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
+#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
+#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
+#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR3 register *******************/
+#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
+#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
+#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
+#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
+#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
+#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
+#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
+#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
+#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
+#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
+#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
+#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
+#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR4 register *******************/
+#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR5 register *******************/
+#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/****************** Bit definition for ADC_SMPR0 register *******************/
+#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
+#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
+#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
+#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */
+#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */
+#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */
+#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */
+
+#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+
+#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */
+#define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */
+#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */
+#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for COMP_CSR register ********************/
+#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
+#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
+#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
+#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
+
+#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
+#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */
+#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
+
+#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
+#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
+
+#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
+#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
+
+#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
+#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
+#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
+#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
+#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
+
+#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
+#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
+#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for OPAMP_CSR register ******************/
+#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
+#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
+#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
+#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
+#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
+#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
+#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
+#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
+#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
+#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
+#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
+#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
+#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */
+#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */
+#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */
+#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */
+#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */
+#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */
+#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
+#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
+#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */
+#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
+#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
+#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
+#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
+#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */
+
+/******************* Bit definition for OPAMP_OTR register ******************/
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
+
+/******************* Bit definition for OPAMP_LPOTR register ****************/
+#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */
+#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */
+#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun interrupt enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR1 register *******************/
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR2 register *******************/
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR3 register *******************/
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CCR4 register *******************/
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CCR5 register *******************/
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CCR6 register *******************/
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR7 register *******************/
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/****************** Bit definition for DMA_CNDTR1 register ******************/
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR2 register ******************/
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR3 register ******************/
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR4 register ******************/
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR5 register ******************/
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR6 register ******************/
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR7 register ******************/
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR1 register *******************/
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR2 register *******************/
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR3 register *******************/
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR4 register *******************/
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR5 register *******************/
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR6 register *******************/
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR7 register *******************/
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR1 register *******************/
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR2 register *******************/
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR3 register *******************/
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+
+/****************** Bit definition for DMA_CMAR4 register *******************/
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR5 register *******************/
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR6 register *******************/
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR7 register *******************/
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH, DATA EEPROM and Option Bytes Registers */
+/* (FLASH, DATA_EEPROM, OB) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
+#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
+#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
+#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */
+#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
+#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
+#define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_RDPRT ((uint32_t)0x000000AA) /*!< Read Protection */
+#define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPRi bits
+ (available only in STM32L1xx Medium-density Plus devices) */
+#define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
+#define FLASH_OBR_BFB2 ((uint32_t)0x00800000) /*!< BFB2(available only in STM32L1xx High-density devices) */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits */
+
+/****************** Bit definition for FLASH_WRPR1 register *****************/
+#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
+ Medium-density Plus and High-density devices) */
+
+/****************** Bit definition for FLASH_WRPR2 register *****************/
+#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
+ High-density devices) */
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/******************* Bit definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_LCKR register ******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************* Bit definition for GPIO_AFRL register ******************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/******************* Bit definition for GPIO_AFRH register ******************/
+#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* LCD Controller (LCD) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CR register *********************/
+#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
+#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
+
+#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
+
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
+
+/******************* Bit definition for LCD_FCR register ********************/
+#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
+
+#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
+
+/******************* Bit definition for LCD_SR register *********************/
+#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
+#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
+#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
+
+/******************* Bit definition for LCD_CLR register ********************/
+#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
+
+/******************* Bit definition for LCD_RAM register ********************/
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */
+#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */
+
+#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */
+#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control (RCC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
+
+#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+/*!< SW configuration */
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
+
+
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
+
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
+
+
+#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+
+/*!< MCO Prescaler configuration */
+#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
+#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
+#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
+#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
+#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
+#define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
+#define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
+#define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_AHBRSTR register ******************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /*!< GPIO port F reset */
+#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /*!< GPIO port G reset */
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
+#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
+#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
+#define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */
+#define RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) /*!< AES reset */
+#define RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) /*!< FSMC reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) /*!< SDIO reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /*!< GPIO port F clock enable */
+#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /*!< GPIO port G clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
+ the Flash memory is in power down mode) */
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */
+#define RCC_AHBENR_AESEN ((uint32_t)0x08000000) /*!< AES clock enable */
+#define RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) /*!< FSMC clock enable */
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) /*!< SDIO clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
+
+/****************** Bit definition for RCC_AHBLPENR register ****************/
+#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /*!< GPIO port F clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /*!< GPIO port G clock enabled in sleep mode */
+#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
+ (has effect only when the Flash memory is
+ in power down mode) */
+#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */
+#define RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) /*!< AES clock enabled in sleep mode */
+#define RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) /*!< FSMC clock enabled in sleep mode */
+
+/****************** Bit definition for RCC_APB2LPENR register ***************/
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) /*!< SDIO clock enabled in sleep mode */
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1LPENR register ****************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
+#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /*!< UART 4 clock enabled in sleep mode */
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /*!< UART 5 clock enabled in sleep mode */
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
+#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
+#define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */
+
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
+
+#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
+#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
+
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP20R register ***************/
+#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP21R register ***************/
+#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP22R register ***************/
+#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP23R register ***************/
+#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP24R register ***************/
+#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP25R register ***************/
+#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP26R register ***************/
+#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP27R register ***************/
+#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP28R register ***************/
+#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP29R register ***************/
+#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP30R register ***************/
+#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP31R register ***************/
+#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CR2_FRF ((uint8_t)0x08) /*!< Frame format */
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_MEMRMP register ****************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */
+#define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/***************** Bit definition for SYSCFG_PMC register *******************/
+#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) /*!< PG[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) /*!< PG[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) /*!< PG[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) /*!< PG[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) /*!< PG[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) /*!< PG[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) /*!< PG[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) /*!< PG[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) /*!< PG[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) /*!< PG[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) /*!< PG[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) /*!< PG[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) /*!< PG[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) /*!< PG[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) /*!< PG[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) /*!< PG[15] pin */
+
+/******************************************************************************/
+/* */
+/* Routing Interface (RI) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RI_ICR register ********************/
+#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
+#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
+#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
+#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */
+#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+
+#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
+#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
+#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
+#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
+#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
+
+/******************** Bit definition for RI_ASCR1 register ********************/
+#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
+#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+#define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */
+#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
+#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
+#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
+#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
+#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
+#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
+#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
+#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
+#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
+#define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */
+#define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */
+#define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */
+#define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */
+#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
+
+/******************** Bit definition for RI_ASCR2 register ********************/
+#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
+#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
+#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
+#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
+#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
+#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
+#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
+#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
+#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
+#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
+#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
+#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
+#define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
+#define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */
+#define RI_ASCR2_CH1b ((uint32_t)0x00020000) /*!< CH1b selection bit */
+#define RI_ASCR2_CH2b ((uint32_t)0x00040000) /*!< CH2b selection bit */
+#define RI_ASCR2_CH3b ((uint32_t)0x00080000) /*!< CH3b selection bit */
+#define RI_ASCR2_CH6b ((uint32_t)0x00100000) /*!< CH6b selection bit */
+#define RI_ASCR2_CH7b ((uint32_t)0x00200000) /*!< CH7b selection bit */
+#define RI_ASCR2_CH8b ((uint32_t)0x00400000) /*!< CH8b selection bit */
+#define RI_ASCR2_CH9b ((uint32_t)0x00800000) /*!< CH9b selection bit */
+#define RI_ASCR2_CH10b ((uint32_t)0x01000000) /*!< CH10b selection bit */
+#define RI_ASCR2_CH11b ((uint32_t)0x02000000) /*!< CH11b selection bit */
+#define RI_ASCR2_CH12b ((uint32_t)0x04000000) /*!< CH12b selection bit */
+#define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
+#define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
+#define RI_ASCR2_GR5_4 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */
+
+/******************** Bit definition for RI_HYSCR1 register ********************/
+#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
+#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
+#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_HYSCR2 register ********************/
+#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
+#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
+#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_HYSCR3 register ********************/
+#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
+#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
+#define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_HYSCR4 register ********************/
+#define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
+#define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR1 register ********************/
+#define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A analog switch mode selection */
+#define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR1 register ********************/
+#define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel masking */
+#define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR1 register ********************/
+#define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel identification for capture */
+#define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR2 register ********************/
+#define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B analog switch mode selection */
+#define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR2 register ********************/
+#define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel masking */
+#define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR2 register ********************/
+#define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel identification for capture */
+#define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR3 register ********************/
+#define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C analog switch mode selection */
+#define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR3 register ********************/
+#define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel masking */
+#define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR3 register ********************/
+#define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel identification for capture */
+#define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR4 register ********************/
+#define RI_ASMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F analog switch mode selection */
+#define RI_ASMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR4 register ********************/
+#define RI_CMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel masking */
+#define RI_CMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR4 register ********************/
+#define RI_CICR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel identification for capture */
+#define RI_CICR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_ASMR5 register ********************/
+#define RI_ASMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G analog switch mode selection */
+#define RI_ASMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CMR5 register ********************/
+#define RI_CMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel masking */
+#define RI_CMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_CICR5 register ********************/
+#define RI_CICR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel identification for capture */
+#define RI_CICR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_CICR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_CICR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_CICR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_CICR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_CICR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_CICR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_CICR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_CICR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_CICR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_CICR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_CICR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_CICR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_CICR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_CICR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_CICR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */
+
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */
+#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling by 8-bit mode */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Universal Serial Bus (USB) */
+/* */
+/******************************************************************************/
+
+/*!<Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/*!<Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
+
+#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* SystemTick (SysTick) */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller (NVIC) */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32l1xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1XX_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_adc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,650 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_adc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_ADC_H
+#define __STM32L1xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief ADC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
+ This parameter can be a value of @ref ADC_Resolution */
+
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
+ Scan (multichannel) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
+ trigger of a regular group. This parameter can be a value
+ of @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 27. */
+}ADC_InitTypeDef;
+
+typedef struct
+{
+ uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.
+ This parameter can be a value
+ of @ref ADC_Prescaler */
+}ADC_CommonInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
+#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)
+
+/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase
+ * @{
+ */
+#define ADC_PowerDown_Delay ((uint32_t)0x00010000)
+#define ADC_PowerDown_Idle ((uint32_t)0x00020000)
+#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)
+
+#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \
+ ((DWON) == ADC_PowerDown_Idle) || \
+ ((DWON) == ADC_PowerDown_Idle_Delay))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Prescaler
+ * @{
+ */
+#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)
+#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)
+#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)
+
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \
+ ((PRESCALER) == ADC_Prescaler_Div2) || \
+ ((PRESCALER) == ADC_Prescaler_Div4))
+/**
+ * @}
+ */
+
+
+
+/** @defgroup ADC_Resolution
+ * @{
+ */
+#define ADC_Resolution_12b ((uint32_t)0x00000000)
+#define ADC_Resolution_10b ((uint32_t)0x01000000)
+#define ADC_Resolution_8b ((uint32_t)0x02000000)
+#define ADC_Resolution_6b ((uint32_t)0x03000000)
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+ ((RESOLUTION) == ADC_Resolution_10b) || \
+ ((RESOLUTION) == ADC_Resolution_8b) || \
+ ((RESOLUTION) == ADC_Resolution_6b))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
+#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+/* TIM2 */
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
+
+/* TIM3 */
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
+#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)
+
+/* TIM4 */
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)
+#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)
+
+/* TIM6 */
+#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)
+
+/* TIM9 */
+#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)
+
+/* EXTI */
+#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+/* ADC Bank A Channels -------------------------------------------------------*/
+#define ADC_Channel_0 ((uint8_t)0x00)
+#define ADC_Channel_1 ((uint8_t)0x01)
+#define ADC_Channel_2 ((uint8_t)0x02)
+#define ADC_Channel_3 ((uint8_t)0x03)
+
+#define ADC_Channel_6 ((uint8_t)0x06)
+#define ADC_Channel_7 ((uint8_t)0x07)
+#define ADC_Channel_8 ((uint8_t)0x08)
+#define ADC_Channel_9 ((uint8_t)0x09)
+#define ADC_Channel_10 ((uint8_t)0x0A)
+#define ADC_Channel_11 ((uint8_t)0x0B)
+#define ADC_Channel_12 ((uint8_t)0x0C)
+
+
+/* ADC Bank B Channels -------------------------------------------------------*/
+#define ADC_Channel_0b ADC_Channel_0
+#define ADC_Channel_1b ADC_Channel_1
+#define ADC_Channel_2b ADC_Channel_2
+#define ADC_Channel_3b ADC_Channel_3
+
+#define ADC_Channel_6b ADC_Channel_6
+#define ADC_Channel_7b ADC_Channel_7
+#define ADC_Channel_8b ADC_Channel_8
+#define ADC_Channel_9b ADC_Channel_9
+#define ADC_Channel_10b ADC_Channel_10
+#define ADC_Channel_11b ADC_Channel_11
+#define ADC_Channel_12b ADC_Channel_12
+
+/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/
+#define ADC_Channel_4 ((uint8_t)0x04)
+#define ADC_Channel_5 ((uint8_t)0x05)
+
+#define ADC_Channel_13 ((uint8_t)0x0D)
+#define ADC_Channel_14 ((uint8_t)0x0E)
+#define ADC_Channel_15 ((uint8_t)0x0F)
+#define ADC_Channel_16 ((uint8_t)0x10)
+#define ADC_Channel_17 ((uint8_t)0x11)
+#define ADC_Channel_18 ((uint8_t)0x12)
+#define ADC_Channel_19 ((uint8_t)0x13)
+#define ADC_Channel_20 ((uint8_t)0x14)
+#define ADC_Channel_21 ((uint8_t)0x15)
+#define ADC_Channel_22 ((uint8_t)0x16)
+#define ADC_Channel_23 ((uint8_t)0x17)
+#define ADC_Channel_24 ((uint8_t)0x18)
+#define ADC_Channel_25 ((uint8_t)0x19)
+
+#define ADC_Channel_27 ((uint8_t)0x1B)
+#define ADC_Channel_28 ((uint8_t)0x1C)
+#define ADC_Channel_29 ((uint8_t)0x1D)
+#define ADC_Channel_30 ((uint8_t)0x1E)
+#define ADC_Channel_31 ((uint8_t)0x1F)
+
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \
+ ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \
+ ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \
+ ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \
+ ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \
+ ((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \
+ ((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \
+ ((CHANNEL) == ADC_Channel_31))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times
+ * @{
+ */
+
+#define ADC_SampleTime_4Cycles ((uint8_t)0x00)
+#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
+#define ADC_SampleTime_16Cycles ((uint8_t)0x02)
+#define ADC_SampleTime_24Cycles ((uint8_t)0x03)
+#define ADC_SampleTime_48Cycles ((uint8_t)0x04)
+#define ADC_SampleTime_96Cycles ((uint8_t)0x05)
+#define ADC_SampleTime_192Cycles ((uint8_t)0x06)
+#define ADC_SampleTime_384Cycles ((uint8_t)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \
+ ((TIME) == ADC_SampleTime_9Cycles) || \
+ ((TIME) == ADC_SampleTime_16Cycles) || \
+ ((TIME) == ADC_SampleTime_24Cycles) || \
+ ((TIME) == ADC_SampleTime_48Cycles) || \
+ ((TIME) == ADC_SampleTime_96Cycles) || \
+ ((TIME) == ADC_SampleTime_192Cycles) || \
+ ((TIME) == ADC_SampleTime_384Cycles))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Delay_length
+ * @{
+ */
+
+#define ADC_DelayLength_None ((uint8_t)0x00)
+#define ADC_DelayLength_Freeze ((uint8_t)0x10)
+#define ADC_DelayLength_7Cycles ((uint8_t)0x20)
+#define ADC_DelayLength_15Cycles ((uint8_t)0x30)
+#define ADC_DelayLength_31Cycles ((uint8_t)0x40)
+#define ADC_DelayLength_63Cycles ((uint8_t)0x50)
+#define ADC_DelayLength_127Cycles ((uint8_t)0x60)
+#define ADC_DelayLength_255Cycles ((uint8_t)0x70)
+
+#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \
+ ((LENGTH) == ADC_DelayLength_Freeze) || \
+ ((LENGTH) == ADC_DelayLength_7Cycles) || \
+ ((LENGTH) == ADC_DelayLength_15Cycles) || \
+ ((LENGTH) == ADC_DelayLength_31Cycles) || \
+ ((LENGTH) == ADC_DelayLength_63Cycles) || \
+ ((LENGTH) == ADC_DelayLength_127Cycles) || \
+ ((LENGTH) == ADC_DelayLength_255Cycles))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
+#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
+
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+
+/* TIM2 */
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)
+
+/* TIM3 */
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)
+
+/* TIM4 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)
+#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
+#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
+
+/* TIM7 */
+#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)
+
+/* TIM9 */
+#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)
+
+/* TIM10 */
+#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)
+
+/* EXTI */
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_channel_selection
+ * @{
+ */
+#define ADC_InjectedChannel_1 ((uint8_t)0x18)
+#define ADC_InjectedChannel_2 ((uint8_t)0x1C)
+#define ADC_InjectedChannel_3 ((uint8_t)0x20)
+#define ADC_InjectedChannel_4 ((uint8_t)0x24)
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+ ((CHANNEL) == ADC_InjectedChannel_2) || \
+ ((CHANNEL) == ADC_InjectedChannel_3) || \
+ ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_IT_AWD ((uint16_t)0x0106)
+#define ADC_IT_EOC ((uint16_t)0x0205)
+#define ADC_IT_JEOC ((uint16_t)0x0407)
+#define ADC_IT_OVR ((uint16_t)0x201A)
+
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWD ((uint16_t)0x0001)
+#define ADC_FLAG_EOC ((uint16_t)0x0002)
+#define ADC_FLAG_JEOC ((uint16_t)0x0004)
+#define ADC_FLAG_JSTRT ((uint16_t)0x0008)
+#define ADC_FLAG_STRT ((uint16_t)0x0010)
+#define ADC_FLAG_OVR ((uint16_t)0x0020)
+#define ADC_FLAG_ADONS ((uint16_t)0x0040)
+#define ADC_FLAG_RCNR ((uint16_t)0x0100)
+#define ADC_FLAG_JCNR ((uint16_t)0x0200)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+ ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \
+ ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \
+ ((FLAG) == ADC_FLAG_JCNR))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_offset
+ * @{
+ */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_length
+ * @{
+ */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_rank
+ * @{
+ */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Bank_Selection
+ * @{
+ */
+#define ADC_Bank_A ((uint8_t)0x00)
+#define ADC_Bank_B ((uint8_t)0x01)
+#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);
+
+/* Power saving functions *****************************************************/
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+
+/* Regular Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_ADC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_aes.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,236 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_aes.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the AES firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_AES_H
+#define __STM32L1xx_AES_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup AES
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief AES Init structure definition
+ */
+typedef struct
+{
+ uint32_t AES_Operation; /*!< Specifies the AES mode of operation.
+ This parameter can be a value of @ref AES_possible_Operation_modes */
+ uint32_t AES_Chaining; /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.
+ This parameter can be a value of @ref AES_possible_chaining_modes */
+ uint32_t AES_DataType; /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.
+ This parameter can be a value of @ref AES_Data_Types */
+}AES_InitTypeDef;
+
+/**
+ * @brief AES Key(s) structure definition
+ */
+typedef struct
+{
+ uint32_t AES_Key0; /*!< Key[31:0] */
+ uint32_t AES_Key1; /*!< Key[63:32] */
+ uint32_t AES_Key2; /*!< Key[95:64] */
+ uint32_t AES_Key3; /*!< Key[127:96] */
+}AES_KeyInitTypeDef;
+
+/**
+ * @brief AES Initialization Vectors (IV) structure definition
+ */
+typedef struct
+{
+ uint32_t AES_IV0; /*!< Init Vector IV[31:0] */
+ uint32_t AES_IV1; /*!< Init Vector IV[63:32] */
+ uint32_t AES_IV2; /*!< Init Vector IV[95:64] */
+ uint32_t AES_IV3; /*!< Init Vector IV[127:96] */
+}AES_IVInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup AES_Exported_Constants
+ * @{
+ */
+
+/** @defgroup AES_possible_Operation_modes
+ * @{
+ */
+#define AES_Operation_Encryp ((uint32_t)0x00000000) /*!< AES in Encryption mode */
+#define AES_Operation_KeyDeriv AES_CR_MODE_0 /*!< AES in Key Derivation mode */
+#define AES_Operation_Decryp AES_CR_MODE_1 /*!< AES in Decryption mode */
+#define AES_Operation_KeyDerivAndDecryp AES_CR_MODE /*!< AES in Key Derivation and Decryption mode */
+
+#define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp) || \
+ ((OPERATION) == AES_Operation_KeyDeriv) || \
+ ((OPERATION) == AES_Operation_Decryp) || \
+ ((OPERATION) == AES_Operation_KeyDerivAndDecryp))
+
+/**
+ * @}
+ */
+
+/** @defgroup AES_possible_chaining_modes
+ * @{
+ */
+#define AES_Chaining_ECB ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */
+#define AES_Chaining_CBC AES_CR_CHMOD_0 /*!< AES in CBC chaining mode */
+#define AES_Chaining_CTR AES_CR_CHMOD_1 /*!< AES in CTR chaining mode */
+
+#define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \
+ ((CHAINING) == AES_Chaining_CBC) || \
+ ((CHAINING) == AES_Chaining_CTR))
+/**
+ * @}
+ */
+
+/** @defgroup AES_Data_Types
+ * @{
+ */
+#define AES_DataType_32b ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */
+#define AES_DataType_16b AES_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
+#define AES_DataType_8b AES_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
+#define AES_DataType_1b AES_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
+
+#define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \
+ ((DATATYPE) == AES_DataType_16b)|| \
+ ((DATATYPE) == AES_DataType_8b) || \
+ ((DATATYPE) == AES_DataType_1b))
+/**
+ * @}
+ */
+
+/** @defgroup AES_Flags
+ * @{
+ */
+#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */
+#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */
+#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */
+
+#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \
+ ((FLAG) == AES_FLAG_RDERR) || \
+ ((FLAG) == AES_FLAG_WRERR))
+/**
+ * @}
+ */
+
+/** @defgroup AES_Interrupts
+ * @{
+ */
+#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */
+#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */
+
+#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))
+#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
+
+/**
+ * @}
+ */
+
+/** @defgroup AES_DMA_Transfer_modes
+ * @{
+ */
+#define AES_DMATransfer_In AES_CR_DMAINEN /*!< DMA requests enabled for input transfer phase */
+#define AES_DMATransfer_Out AES_CR_DMAOUTEN /*!< DMA requests enabled for input transfer phase */
+#define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */
+
+#define IS_AES_DMA_TRANSFER(TRANSFER) (((TRANSFER) == AES_DMATransfer_In) || \
+ ((TRANSFER) == AES_DMATransfer_Out) || \
+ ((TRANSFER) == AES_DMATransfer_InOut))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and configuration functions *********************************/
+void AES_DeInit(void);
+void AES_Init(AES_InitTypeDef* AES_InitStruct);
+void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
+void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);
+void AES_Cmd(FunctionalState NewState);
+
+/* Structures initialization functions ****************************************/
+void AES_StructInit(AES_InitTypeDef* AES_InitStruct);
+void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
+void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);
+
+/* AES Read and Write functions **********************************************/
+void AES_WriteSubData(uint32_t Data);
+uint32_t AES_ReadSubData(void);
+void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);
+void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);
+
+/* DMA transfers management function ******************************************/
+void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);
+FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);
+void AES_ClearFlag(uint32_t AES_FLAG);
+ITStatus AES_GetITStatus(uint32_t AES_IT);
+void AES_ClearITPendingBit(uint32_t AES_IT);
+
+/* High Level AES functions **************************************************/
+ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_AES_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_comp.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,187 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_comp.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the COMP firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_COMP_H
+#define __STM32L1xx_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief COMP Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.
+ This parameter can be a value of @ref COMP_Speed */
+ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.
+ This parameter can be a value of @ref COMP_InvertingInput */
+ uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.
+ This parameter can be a value of @ref COMP_OutputSelect */
+
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Constants
+ * @{
+ */
+
+#define COMP_OutputLevel_High ((uint32_t)0x00000001)
+#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
+
+/** @defgroup COMP_Selection
+ * @{
+ */
+
+#define COMP_Selection_COMP1 ((uint32_t)0x00000001)
+#define COMP_Selection_COMP2 ((uint32_t)0x00000002)
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+ ((PERIPH) == COMP_Selection_COMP2))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_InvertingInput
+ * @{
+ */
+
+#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */
+#define COMP_InvertingInput_IO ((uint32_t)0x00040000)
+#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)
+#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)
+#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)
+#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)
+#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)
+#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \
+ ((INPUT) == COMP_InvertingInput_IO) || \
+ ((INPUT) == COMP_InvertingInput_VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+ ((INPUT) == COMP_InvertingInput_DAC1) || \
+ ((INPUT) == COMP_InvertingInput_DAC2))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputSelect
+ * @{
+ */
+
+#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)
+#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)
+#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)
+#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)
+#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)
+#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)
+#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)
+#define COMP_OutputSelect_None ((uint32_t)0x00E00000)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \
+ ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \
+ ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \
+ ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \
+ ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \
+ ((OUTPUT) == COMP_OutputSelect_None))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Speed
+ * @{
+ */
+
+#define COMP_Speed_Slow ((uint32_t)0x00000000)
+#define COMP_Speed_Fast ((uint32_t)0x00001000)
+
+#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \
+ ((SPEED) == COMP_Speed_Fast))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(FunctionalState NewState);
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+void COMP_SW1SwitchConfig(FunctionalState NewState);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+
+/* Internal Reference Voltage (VREFINT) output function ***********************/
+void COMP_VrefintOutputCmd(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_COMP_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_NUCLEO_L152RE/stm32l1xx_conf.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,85 @@ +/** + ****************************************************************************** + * @file Project/STM32L1xx_StdPeriph_Templates/stm32l1xx_conf.h + * @author MCD Application Team + * @version V1.1.1 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_CONF_H +#define __STM32L1xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ +#include "stm32l1xx_adc.h" +//#include "stm32l1xx_aes.h" +//#include "stm32l1xx_comp.h" +//#include "stm32l1xx_crc.h" +#include "stm32l1xx_dac.h" +#include "stm32l1xx_dbgmcu.h" +//#include "stm32l1xx_dma.h" +#include "stm32l1xx_exti.h" +//#include "stm32l1xx_flash.h" +//#include "stm32l1xx_fsmc.h" +#include "stm32l1xx_gpio.h" +#include "stm32l1xx_i2c.h" +//#include "stm32l1xx_iwdg.h" +//#include "stm32l1xx_lcd.h" +//#include "stm32l1xx_opamp.h" +#include "stm32l1xx_pwr.h" +#include "stm32l1xx_rcc.h" +#include "stm32l1xx_rtc.h" +#include "stm32l1xx_sdio.h" +#include "stm32l1xx_spi.h" +#include "stm32l1xx_syscfg.h" +#include "stm32l1xx_tim.h" +#include "stm32l1xx_usart.h" +//#include "stm32l1xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32L1xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_crc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,83 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_crc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the CRC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_CRC_H
+#define __STM32L1xx_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_CRC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_dac.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,305 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_dac.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_DAC_H
+#define __STM32L1xx_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T9_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+ ((STATE) == DAC_OutputBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_interrupts_definition
+ * @{
+ */
+
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
+
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DAC configuration to the default reset state *****/
+void DAC_DeInit(void);
+
+/* DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_DAC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_dbgmcu.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,105 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_dbgmcu.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the DBGMCU
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_DBGMCU_H
+#define __STM32L1xx_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBGMCU
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)
+#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)
+#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_DBGMCU_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_dma.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,435 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_dma.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_DMA_H
+#define __STM32L1xx_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+ ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+ ((STATE) == DMA_PeripheralInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+ ((STATE) == DMA_MemoryInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Circular ((uint32_t)0x00000020)
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
+#define DMA_Priority_High ((uint32_t)0x00002000)
+#define DMA_Priority_Medium ((uint32_t)0x00001000)
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Enable ((uint32_t)0x00004000)
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DMA configuration to the default reset state *****/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+
+/* Data Counter functions *****************************************************/
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_DMA_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_exti.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_exti.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the EXTI firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_EXTI_H
+#define __STM32L1xx_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
+ Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17
+ Connected to the RTC Alarm
+ event */
+#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18
+ Connected to the USB Device
+ FS Wakeup from suspend event */
+#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19
+ Connected to the RTC Tamper
+ and Time Stamp events */
+#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20
+ Connected to the RTC Wakeup
+ event */
+#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21
+ Connected to the Comparator 1
+ event */
+
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22
+ Connected to the Comparator 2
+ event */
+
+#define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23
+ Comparator channel acquisition event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+ ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_EXTI_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_flash.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,482 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_flash.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_FLASH_H
+#define __STM32L1xx_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief FLASH Status
+ */
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_WRP,
+ FLASH_ERROR_PROGRAM,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Latency
+ * @{
+ */
+#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
+
+#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */
+#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Address
+ * @{
+ */
+
+#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08083FFF))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+
+#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
+#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
+#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
+#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
+#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
+#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
+#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
+#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
+#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
+#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
+#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
+#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
+#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
+#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
+#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
+#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
+#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
+#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
+#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
+#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
+#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
+#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
+#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
+#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
+#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
+#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
+#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
+#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
+#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
+#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
+#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
+#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */
+
+#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define OB_WRP1_Pages512to527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
+#define OB_WRP1_Pages528to543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
+#define OB_WRP1_Pages544to559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
+#define OB_WRP1_Pages560to575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
+#define OB_WRP1_Pages576to591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
+#define OB_WRP1_Pages592to607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
+#define OB_WRP1_Pages608to623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
+#define OB_WRP1_Pages624to639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
+#define OB_WRP1_Pages640to655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
+#define OB_WRP1_Pages656to671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
+#define OB_WRP1_Pages672to687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
+#define OB_WRP1_Pages688to703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
+#define OB_WRP1_Pages704to719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
+#define OB_WRP1_Pages720to735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
+#define OB_WRP1_Pages736to751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
+#define OB_WRP1_Pages752to767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
+#define OB_WRP1_Pages768to783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
+#define OB_WRP1_Pages784to799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
+#define OB_WRP1_Pages800to815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
+#define OB_WRP1_Pages816to831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
+#define OB_WRP1_Pages832to847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
+#define OB_WRP1_Pages848to863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
+#define OB_WRP1_Pages864to879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
+#define OB_WRP1_Pages880to895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
+#define OB_WRP1_Pages896to911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
+#define OB_WRP1_Pages912to927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
+#define OB_WRP1_Pages928to943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
+#define OB_WRP1_Pages944to959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
+#define OB_WRP1_Pages960to975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
+#define OB_WRP1_Pages976to991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
+#define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
+#define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */
+
+#define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
+#define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
+#define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
+#define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
+#define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
+#define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
+#define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
+#define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
+#define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
+#define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
+#define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
+#define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
+#define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
+#define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
+#define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
+#define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
+#define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
+#define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
+#define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
+#define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
+#define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
+#define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
+#define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
+#define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
+#define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
+#define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
+#define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
+#define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
+#define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
+#define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
+#define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
+#define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */
+
+#define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup Selection_Protection_Mode
+ * @{
+ */
+#define OB_PcROP_Enable ((uint16_t)0x0100) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PcROP_Disable ((uint16_t)0x0000) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
+#define IS_OB_PCROP_SELECT(OB_PcROP) (((OB_PcROP) == OB_PcROP_Enable) || ((OB_PcROP) == OB_PcROP_Disable))
+/**
+ * @}
+ */
+
+
+/** @defgroup Option_Bytes_Read_Protection
+ * @{
+ */
+
+/**
+ * @brief Read Protection Level
+ */
+#define OB_RDP_Level_0 ((uint8_t)0xAA)
+#define OB_RDP_Level_1 ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+ ((LEVEL) == OB_RDP_Level_1))/*||\
+ ((LEVEL) == OB_RDP_Level_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_BOOT
+ * @{
+ */
+
+#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
+ and this parameter is selected the device will boot from Bank 2
+ or Bank 1, depending on the activation of the bank */
+#define OB_BOOT_BANK1 ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position
+ and this parameter is selected the device will boot from Bank1(Default) */
+#define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_BOR_Level
+ * @{
+ */
+
+#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
+ power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
+#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
+#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
+#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
+#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \
+ ((LEVEL) == OB_BOR_LEVEL1) || \
+ ((LEVEL) == OB_BOR_LEVEL2) || \
+ ((LEVEL) == OB_BOR_LEVEL3) || \
+ ((LEVEL) == OB_BOR_LEVEL4) || \
+ ((LEVEL) == OB_BOR_LEVEL5))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
+#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */
+#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
+#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
+#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
+#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
+#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag
+ (available only in STM32L1XX_MDP devices) */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFC0FD) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
+ ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
+ ((FLAG) == FLASH_FLAG_OPTVERRUSR) || ((FLAG) == FLASH_FLAG_RDERR))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Keys
+ * @{
+ */
+
+#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
+#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
+ to unlock the RUN_PD bit in FLASH_ACR */
+
+#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
+#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
+ to unlock the write access to the FLASH_PECR register and
+ data EEPROM */
+
+#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
+#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
+ to unlock the program memory */
+
+#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+/**
+ * @}
+ */
+
+/** @defgroup Timeout_definition
+ * @{
+ */
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)
+
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_Legacy
+ * @{
+ */
+#if defined ( __ICCARM__ )
+#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk
+#endif
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/**
+ * @brief FLASH memory functions that can be executed from FLASH.
+ */
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+void FLASH_ReadAccess64Cmd(FunctionalState NewState);
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
+
+/* FLASH Memory Programming functions *****************************************/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
+
+/* DATA EEPROM Programming functions ******************************************/
+void DATA_EEPROM_Unlock(void);
+void DATA_EEPROM_Lock(void);
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);
+FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
+FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
+
+/* Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
+FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState);
+FLASH_Status FLASH_OB_PCROP1Config(uint32_t OB_WRP1, FunctionalState NewState);
+FLASH_Status FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
+FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+uint32_t FLASH_OB_GetWRP1(void);
+uint32_t FLASH_OB_GetWRP2(void);
+FlagStatus FLASH_OB_GetRDP(void);
+FlagStatus FLASH_OB_GetSPRMOD(void);
+uint8_t FLASH_OB_GetBOR(void);
+
+/* Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+ * @brief FLASH memory functions that should be executed from internal SRAM.
+ * These functions are defined inside the "stm32l1xx_flash_ramfunc.c"
+ * file.
+ */
+__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);
+__RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
+__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);
+__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
+__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);
+__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_FLASH_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,438 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_fsmc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the FSMC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_FSMC_H
+#define __STM32L1xx_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief Timing parameters For NOR/SRAM Banks
+ */
+
+typedef struct
+{
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between 0 and 0xF.
+ @note It is not used with synchronous NOR Flash memories. */
+
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between 0 and 0xF.
+ @note It is not used with synchronous NOR Flash memories.*/
+
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between 0 and 0xFF.
+ @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between 0 and 0xF.
+ @note It is only used for multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+ This parameter can be a value between 1 and 0xF.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between 0 and 0xF in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/**
+ * @brief FSMC NOR/SRAM Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the databus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory bank.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
+}FSMC_NORSRAMInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FSMC_NORSRAM_Bank
+ * @{
+ */
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \
+ ((BANK) == FSMC_Bank1_NORSRAM4))
+/**
+ * @}
+ */
+
+/** @defgroup NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+ ((MUX) == FSMC_DataAddressMux_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Memory_Type
+ * @{
+ */
+
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+ ((MEMORY) == FSMC_MemoryType_NOR))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Width
+ * @{
+ */
+
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+ ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_AsynchronousWait
+ * @{
+ */
+#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+ ((STATE) == FSMC_AsynchronousWait_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal_Polarity
+ * @{
+ */
+
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+ ((POLARITY) == FSMC_WaitSignalPolarity_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode
+ * @{
+ */
+
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+ ((MODE) == FSMC_WrapMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing
+ * @{
+ */
+
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation
+ * @{
+ */
+
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+ ((OPERATION) == FSMC_WriteOperation_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal
+ * @{
+ */
+
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+ ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode
+ * @{
+ */
+
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+ ((MODE) == FSMC_ExtendedMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst
+ * @{
+ */
+
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+ ((BURST) == FSMC_WriteBurst_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration
+ * @{
+ */
+
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_CLK_Division
+ * @{
+ */
+
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Latency
+ * @{
+ */
+
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Access_Mode
+ * @{
+ */
+
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B ((uint32_t)0x10000000)
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+ ((MODE) == FSMC_AccessMode_B) || \
+ ((MODE) == FSMC_AccessMode_C) || \
+ ((MODE) == FSMC_AccessMode_D))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* NOR/SRAM Controller functions **********************************************/
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_FSMC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_gpio.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,391 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_gpio.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_GPIO_H
+#define __STM32L1xx_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOH) || \
+ ((PERIPH) == GPIOF) || \
+ ((PERIPH) == GPIOG))
+
+/** @defgroup Configuration_Mode_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
+}GPIOMode_TypeDef;
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+ * @}
+ */
+
+/** @defgroup Output_type_enumeration
+ * @{
+ */
+typedef enum
+{ GPIO_OType_PP = 0x00,
+ GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+ * @}
+ */
+
+/** @defgroup Output_Maximum_frequency_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */
+ GPIO_Speed_2MHz = 0x01, /*!< Low Speed */
+ GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */
+ GPIO_Speed_40MHz = 0x03 /*!< High Speed */
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+ ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz))
+/**
+ * @}
+ */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
+ * @{
+ */
+typedef enum
+{ GPIO_PuPd_NOPULL = 0x00,
+ GPIO_PuPd_UP = 0x01,
+ GPIO_PuPd_DOWN = 0x02
+}GPIOPuPd_TypeDef;
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+ ((PUPD) == GPIO_PuPd_DOWN))
+/**
+ * @}
+ */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+ * @{
+ */
+typedef enum
+{ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIOOType_TypeDef */
+
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Alternat_function_selection_define
+ * @{
+ */
+
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */
+#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
+#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */
+#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */
+#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */
+#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */
+#define GPIO_AF_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */
+#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */
+#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
+#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */
+#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */
+#define GPIO_AF_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */
+#define GPIO_AF_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \
+ ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+ ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \
+ ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \
+ ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+ ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \
+ ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \
+ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_SPI3) || \
+ ((AF) == GPIO_AF_UART4) || ((AF) == GPIO_AF_UART5) || \
+ ((AF) == GPIO_AF_FSMC) || ((AF) == GPIO_AF_SDIO) || \
+ ((AF) == GPIO_AF_EVENTOUT))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Legacy
+ * @{
+ */
+
+#define GPIO_Mode_AIN GPIO_Mode_AN
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the GPIO configuration to the default reset state ****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_GPIO_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_i2c.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,703 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_i2c.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_I2C_H
+#define __STM32L1xx_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+ ((CYCLE) == I2C_DutyCycle_2))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_Ack_Enable ((uint16_t)0x0400)
+#define I2C_Ack_Disable ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+ ((STATE) == I2C_Ack_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_Direction_Transmitter ((uint8_t)0x00)
+#define I2C_Direction_Receiver ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_registers
+ * @{
+ */
+
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_DR ((uint8_t)0x10)
+#define I2C_Register_SR1 ((uint8_t)0x14)
+#define I2C_Register_SR2 ((uint8_t)0x18)
+#define I2C_Register_CCR ((uint8_t)0x1C)
+#define I2C_Register_TRISE ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_DR) || \
+ ((REGISTER) == I2C_Register_SR1) || \
+ ((REGISTER) == I2C_Register_SR2) || \
+ ((REGISTER) == I2C_Register_CCR) || \
+ ((REGISTER) == I2C_Register_TRISE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+ ((ALERT) == I2C_SMBusAlert_High))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PECPosition_Next ((uint16_t)0x0800)
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+ ((POSITION) == I2C_PECPosition_Current))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_NACK_position
+ * @{
+ */
+
+#define I2C_NACKPosition_Next ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
+ ((POSITION) == I2C_NACKPosition_Current))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_BUF ((uint16_t)0x0400)
+#define I2C_IT_EVT ((uint16_t)0x0200)
+#define I2C_IT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
+#define I2C_IT_PECERR ((uint32_t)0x01001000)
+#define I2C_IT_OVR ((uint32_t)0x01000800)
+#define I2C_IT_AF ((uint32_t)0x01000400)
+#define I2C_IT_ARLO ((uint32_t)0x01000200)
+#define I2C_IT_BERR ((uint32_t)0x01000100)
+#define I2C_IT_TXE ((uint32_t)0x06000080)
+#define I2C_IT_RXNE ((uint32_t)0x06000040)
+#define I2C_IT_STOPF ((uint32_t)0x02000010)
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)
+#define I2C_IT_BTF ((uint32_t)0x02000004)
+#define I2C_IT_ADDR ((uint32_t)0x02000002)
+#define I2C_IT_SB ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief SR2 register flags
+ */
+
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)
+
+/**
+ * @brief SR1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)
+#define I2C_FLAG_AF ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
+#define I2C_FLAG_SB ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Events
+ * @{
+ */
+
+/**
+ ===============================================================================
+ I2C Master Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+/**
+ * @brief Communication start
+ *
+ * After sending the START condition (I2C_GenerateSTART() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* --EV5 */
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ * function). Then master should wait on EV9. It means that the 10-bit addressing
+ * header has been correctly sent on the bus. Then master should send the second part of
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
+ * should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ * the data received from the slave (I2C_ReceiveData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ * function) then to wait on event EV8 or EV8_2.
+ * These two events are similar:
+ * - EV8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EV8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EV8 is sufficient for the application.
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ * (before Stop condition generation).
+ *
+ * @note In case the user software does not guarantee that this event EV7 is
+ * managed before the current byte end of transfer, then user may check on EV7
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/**
+ ===============================================================================
+ I2C Slave Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+
+/**
+ * @brief Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_AcknowledgeConfig()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
+ *
+ */
+
+/* --EV1 (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ * - EV2: When the application is expecting a data byte to be received.
+ * - EV4: When the application is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
+ * used when the user software doesn't guarantee the EV3 is managed before the
+ * current byte end of transfer.
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ * shall end (before sending the STOP condition). In this case slave has to stop sending
+ * data bytes and expect a Stop condition on the bus.
+ *
+ * @note In case the user software does not guarantee that the event EV2 is
+ * managed before the current byte end of transfer, then user may check on EV2
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+/* --EV4 */
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
+
+/*
+ ===============================================================================
+ End of Events Description
+ ===============================================================================
+ */
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_clock_speed
+ * @{
+ */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the I2C configuration to the default reset state *****/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+
+/* Initialization and Configuration functions *********************************/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+
+/* Data transfers functions ***************************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+
+/* PEC management functions ***************************************************/
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+
+/* Interrupts, events and flags management functions **************************/
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/*
+
+ ===============================================================================
+ I2C State Monitoring Functions
+ ===============================================================================
+ This I2C driver provides three different ways for I2C state monitoring
+ depending on the application requirements and constraints:
+
+
+ 1. Basic state monitoring (Using I2C_CheckEvent() function)
+ -----------------------------------------------------------
+ It compares the status registers (SR1 and SR2) content to a given event
+ (can be the combination of one or more flags).
+ It returns SUCCESS if the current status includes the given flags
+ and returns ERROR if one or more flags are missing in the current status.
+
+ - When to use
+ - This function is suitable for most applications as well as for startup
+ activity since the events are fully described in the product reference
+ manual (RM0038).
+ - It is also suitable for users who need to define their own events.
+
+ - Limitations
+ - If an error occurs (ie. error flags are set besides to the monitored
+ flags), the I2C_CheckEvent() function may return SUCCESS despite
+ the communication hold or corrupted real state.
+ In this case, it is advised to use error interrupts to monitor
+ the error events and handle them in the interrupt IRQ handler.
+
+ Note
+ For error management, it is advised to use the following functions:
+ - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ Where x is the peripheral instance (I2C1, I2C2 ...)
+ - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
+ I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+ - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ and/or I2C_GenerateStop() in order to clear the error flag and source
+ and return to correct communciation status.
+
+
+ 2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+ --------------------------------------------------------------------
+ Using the function I2C_GetLastEvent() which returns the image of both status
+ registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ by 16 bits and concatenated to Status Register 1).
+
+ - When to use
+ - This function is suitable for the same applications above but it
+ allows to overcome the mentioned limitation of I2C_GetFlagStatus()
+ function.
+ - The returned value could be compared to events already defined in
+ the library (stm32l1xx_i2c.h) or to custom values defined by user.
+ This function is suitable when multiple flags are monitored at the
+ same time.
+ - At the opposite of I2C_CheckEvent() function, this function allows
+ user to choose when an event is accepted (when all events flags are
+ set and no other flags are set or just when the needed flags are set
+ like I2C_CheckEvent() function.
+
+ - Limitations
+ - User may need to define his own events.
+ - Same remark concerning the error management is applicable for this
+ function if user decides to check only regular communication flags
+ (and ignores error flags).
+
+
+ 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+ -----------------------------------------------------------------------
+
+ Using the function I2C_GetFlagStatus() which simply returns the status of
+ one single flag (ie. I2C_FLAG_RXNE ...).
+
+ - When to use
+ - This function could be used for specific applications or in debug
+ phase.
+ - It is suitable when only one flag checking is needed (most I2C
+ events are monitored through multiple flags).
+ - Limitations:
+ - When calling this function, the Status register is accessed.
+ Some flags are cleared when the status register is accessed.
+ So checking the status of one Flag, may clear other ones.
+ - Function may need to be called twice or more in order to monitor
+ one single event.
+
+ For detailed description of Events, please refer to section I2C_Events in
+ stm32l1xx_i2c.h file.
+
+*/
+
+/*
+ ===============================================================================
+ 1. Basic state monitoring
+ ===============================================================================
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/*
+ ===============================================================================
+ 2. Advanced state monitoring
+ ===============================================================================
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/*
+ ===============================================================================
+ 3. Flag-based state monitoring
+ ===============================================================================
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_I2C_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_iwdg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,134 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_iwdg.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_IWDG_H
+#define __STM32L1xx_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_IWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_lcd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,452 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_lcd.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the LCD firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_LCD_H
+#define __STM32L1xx_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief LCD Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler.
+ This parameter can be one value of @ref LCD_Prescaler */
+ uint32_t LCD_Divider; /*!< Configures the LCD Divider.
+ This parameter can be one value of @ref LCD_Divider */
+ uint32_t LCD_Duty; /*!< Configures the LCD Duty.
+ This parameter can be one value of @ref LCD_Duty */
+ uint32_t LCD_Bias; /*!< Configures the LCD Bias.
+ This parameter can be one value of @ref LCD_Bias */
+ uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source.
+ This parameter can be one value of @ref LCD_Voltage_Source */
+}LCD_InitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup LCD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup LCD_Prescaler
+ * @{
+ */
+
+#define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */
+#define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */
+#define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */
+#define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */
+#define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */
+#define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */
+#define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */
+#define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */
+#define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */
+#define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */
+#define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */
+#define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */
+#define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */
+#define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */
+#define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */
+#define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */
+
+#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \
+ ((PRESCALER) == LCD_Prescaler_2) || \
+ ((PRESCALER) == LCD_Prescaler_4) || \
+ ((PRESCALER) == LCD_Prescaler_8) || \
+ ((PRESCALER) == LCD_Prescaler_16) || \
+ ((PRESCALER) == LCD_Prescaler_32) || \
+ ((PRESCALER) == LCD_Prescaler_64) || \
+ ((PRESCALER) == LCD_Prescaler_128) || \
+ ((PRESCALER) == LCD_Prescaler_256) || \
+ ((PRESCALER) == LCD_Prescaler_512) || \
+ ((PRESCALER) == LCD_Prescaler_1024) || \
+ ((PRESCALER) == LCD_Prescaler_2048) || \
+ ((PRESCALER) == LCD_Prescaler_4096) || \
+ ((PRESCALER) == LCD_Prescaler_8192) || \
+ ((PRESCALER) == LCD_Prescaler_16384) || \
+ ((PRESCALER) == LCD_Prescaler_32768))
+
+/**
+ * @}
+ */
+
+/** @defgroup LCD_Divider
+ * @{
+ */
+
+#define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */
+#define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */
+#define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */
+#define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */
+#define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */
+#define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */
+#define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */
+#define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */
+#define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */
+#define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */
+#define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */
+#define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */
+#define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */
+#define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */
+#define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */
+#define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */
+
+#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \
+ ((DIVIDER) == LCD_Divider_17) || \
+ ((DIVIDER) == LCD_Divider_18) || \
+ ((DIVIDER) == LCD_Divider_19) || \
+ ((DIVIDER) == LCD_Divider_20) || \
+ ((DIVIDER) == LCD_Divider_21) || \
+ ((DIVIDER) == LCD_Divider_22) || \
+ ((DIVIDER) == LCD_Divider_23) || \
+ ((DIVIDER) == LCD_Divider_24) || \
+ ((DIVIDER) == LCD_Divider_25) || \
+ ((DIVIDER) == LCD_Divider_26) || \
+ ((DIVIDER) == LCD_Divider_27) || \
+ ((DIVIDER) == LCD_Divider_28) || \
+ ((DIVIDER) == LCD_Divider_29) || \
+ ((DIVIDER) == LCD_Divider_30) || \
+ ((DIVIDER) == LCD_Divider_31))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LCD_Duty
+ * @{
+ */
+
+#define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */
+#define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */
+#define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */
+#define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */
+#define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */
+
+#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \
+ ((DUTY) == LCD_Duty_1_2) || \
+ ((DUTY) == LCD_Duty_1_3) || \
+ ((DUTY) == LCD_Duty_1_4) || \
+ ((DUTY) == LCD_Duty_1_8))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LCD_Bias
+ * @{
+ */
+
+#define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */
+#define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
+#define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
+
+#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \
+ ((BIAS) == LCD_Bias_1_2) || \
+ ((BIAS) == LCD_Bias_1_3))
+/**
+ * @}
+ */
+
+/** @defgroup LCD_Voltage_Source
+ * @{
+ */
+
+#define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */
+#define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */
+
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \
+ ((SOURCE) == LCD_VoltageSource_External))
+
+/**
+ * @}
+ */
+
+/** @defgroup LCD_Interrupts
+ * @{
+ */
+#define LCD_IT_SOF LCD_FCR_SOFIE
+#define LCD_IT_UDD LCD_FCR_UDDIE
+
+#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))
+
+#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))
+
+/**
+ * @}
+ */
+
+/** @defgroup LCD_PulseOnDuration
+ * @{
+ */
+
+#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */
+#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */
+#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */
+#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */
+#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */
+#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */
+#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */
+#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */
+
+#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \
+ ((DURATION) == LCD_PulseOnDuration_1) || \
+ ((DURATION) == LCD_PulseOnDuration_2) || \
+ ((DURATION) == LCD_PulseOnDuration_3) || \
+ ((DURATION) == LCD_PulseOnDuration_4) || \
+ ((DURATION) == LCD_PulseOnDuration_5) || \
+ ((DURATION) == LCD_PulseOnDuration_6) || \
+ ((DURATION) == LCD_PulseOnDuration_7))
+/**
+ * @}
+ */
+
+
+/** @defgroup LCD_DeadTime
+ * @{
+ */
+
+#define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */
+#define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */
+#define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */
+#define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */
+#define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */
+#define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */
+#define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */
+#define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */
+
+#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \
+ ((TIME) == LCD_DeadTime_1) || \
+ ((TIME) == LCD_DeadTime_2) || \
+ ((TIME) == LCD_DeadTime_3) || \
+ ((TIME) == LCD_DeadTime_4) || \
+ ((TIME) == LCD_DeadTime_5) || \
+ ((TIME) == LCD_DeadTime_6) || \
+ ((TIME) == LCD_DeadTime_7))
+/**
+ * @}
+ */
+
+/** @defgroup LCD_BlinkMode
+ * @{
+ */
+
+#define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */
+#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
+#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to
+ 8 pixels according to the programmed duty) */
+#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */
+
+#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \
+ ((MODE) == LCD_BlinkMode_SEG0_COM0) || \
+ ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \
+ ((MODE) == LCD_BlinkMode_AllSEG_AllCOM))
+/**
+ * @}
+ */
+
+/** @defgroup LCD_BlinkFrequency
+ * @{
+ */
+
+#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */
+#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */
+#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */
+#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */
+#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */
+#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */
+#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */
+#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */
+
+#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \
+ ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \
+ ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \
+ ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \
+ ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \
+ ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \
+ ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \
+ ((FREQUENCY) == LCD_BlinkFrequency_Div1024))
+/**
+ * @}
+ */
+
+/** @defgroup LCD_Contrast
+ * @{
+ */
+
+#define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */
+#define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */
+#define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */
+#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */
+#define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */
+#define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */
+#define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */
+#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */
+
+#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \
+ ((CONTRAST) == LCD_Contrast_Level_1) || \
+ ((CONTRAST) == LCD_Contrast_Level_2) || \
+ ((CONTRAST) == LCD_Contrast_Level_3) || \
+ ((CONTRAST) == LCD_Contrast_Level_4) || \
+ ((CONTRAST) == LCD_Contrast_Level_5) || \
+ ((CONTRAST) == LCD_Contrast_Level_6) || \
+ ((CONTRAST) == LCD_Contrast_Level_7))
+/**
+ * @}
+ */
+
+/** @defgroup LCD_Flag
+ * @{
+ */
+
+#define LCD_FLAG_ENS LCD_SR_ENS
+#define LCD_FLAG_SOF LCD_SR_SOF
+#define LCD_FLAG_UDR LCD_SR_UDR
+#define LCD_FLAG_UDD LCD_SR_UDD
+#define LCD_FLAG_RDY LCD_SR_RDY
+#define LCD_FLAG_FCRSF LCD_SR_FCRSR
+
+#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \
+ ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \
+ ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))
+
+#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup LCD_RAMRegister
+ * @{
+ */
+
+#define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */
+#define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */
+#define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */
+#define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */
+#define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */
+#define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */
+#define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */
+#define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */
+#define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */
+#define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */
+#define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
+#define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
+#define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
+#define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
+#define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
+#define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
+
+#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \
+ ((REGISTER) == LCD_RAMRegister_1) || \
+ ((REGISTER) == LCD_RAMRegister_2) || \
+ ((REGISTER) == LCD_RAMRegister_3) || \
+ ((REGISTER) == LCD_RAMRegister_4) || \
+ ((REGISTER) == LCD_RAMRegister_5) || \
+ ((REGISTER) == LCD_RAMRegister_6) || \
+ ((REGISTER) == LCD_RAMRegister_7) || \
+ ((REGISTER) == LCD_RAMRegister_8) || \
+ ((REGISTER) == LCD_RAMRegister_9) || \
+ ((REGISTER) == LCD_RAMRegister_10) || \
+ ((REGISTER) == LCD_RAMRegister_11) || \
+ ((REGISTER) == LCD_RAMRegister_12) || \
+ ((REGISTER) == LCD_RAMRegister_13) || \
+ ((REGISTER) == LCD_RAMRegister_14) || \
+ ((REGISTER) == LCD_RAMRegister_15))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the LCD configuration to the default reset state *****/
+void LCD_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct);
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct);
+void LCD_Cmd(FunctionalState NewState);
+void LCD_WaitForSynchro(void);
+void LCD_HighDriveCmd(FunctionalState NewState);
+void LCD_MuxSegmentCmd(FunctionalState NewState);
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration);
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime);
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency);
+void LCD_ContrastConfig(uint32_t LCD_Contrast);
+
+/* LCD RAM memory write functions *********************************************/
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data);
+void LCD_UpdateDisplayRequest(void);
+
+/* Interrupts and flags management functions **********************************/
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState);
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG);
+void LCD_ClearFlag(uint32_t LCD_FLAG);
+ITStatus LCD_GetITStatus(uint32_t LCD_IT);
+void LCD_ClearITPendingBit(uint32_t LCD_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_LCD_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_opamp.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,187 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_opamp.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the operational
+ * amplifiers (opamp) firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_OPAMP_H
+#define __STM32L1xx_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_Selection
+ * @{
+ */
+
+#define OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD
+#define OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD
+#define OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD
+
+#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP2) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP3))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Switches
+ * @{
+ */
+
+/* OPAMP1 Switches */
+#define OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */
+#define OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */
+#define OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */
+#define OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */
+#define OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */
+
+/* OPAMP2 Switches */
+#define OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */
+#define OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */
+#define OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */
+#define OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */
+#define OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */
+#define OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */
+
+/* OPAMP3 Switches */
+#define OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */
+#define OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */
+#define OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */
+#define OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */
+#define OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */
+
+#define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Trimming
+ * @{
+ */
+
+#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
+#define OPAMP_Trimming_User OPAMP_OTR_OT_USER /*!< User trimming */
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
+ ((TRIMMING) == OPAMP_Trimming_User))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Input
+ * @{
+ */
+
+#define OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H /*!< NMOS input */
+#define OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L /*!< PMOS input */
+
+#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \
+ ((INPUT) == OPAMP_Input_PMOS))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_TrimValue
+ * @{
+ */
+
+#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PowerRange
+ * @{
+ */
+
+#define OPAMP_PowerRange_Low ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */
+#define OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE /*!< High power range is selected (VDDA is higher than 2.4V) */
+
+#define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \
+ ((RANGE) == OPAMP_PowerRange_High))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Initialization and Configuration functions *********************************/
+void OPAMP_DeInit(void);
+void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState);
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange);
+
+/* Calibration functions ******************************************************/
+void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming);
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
+void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
+FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_OPAMP_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_pwr.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,213 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_pwr.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the PWR firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_PWR_H
+#define __STM32L1xx_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage
+ (Compare internally to VREFINT) */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pins
+ * @{
+ */
+
+#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)
+#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)
+#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
+ ((PIN) == PWR_WakeUpPin_2) || \
+ ((PIN) == PWR_WakeUpPin_3))
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_Voltage_Scaling_Ranges
+ * @{
+ */
+
+#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0
+#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1
+#define PWR_VoltageScaling_Range3 PWR_CR_VOS
+
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \
+ ((RANGE) == PWR_VoltageScaling_Range2) || \
+ ((RANGE) == PWR_VoltageScaling_Range3))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
+ * @{
+ */
+
+#define PWR_Regulator_ON ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+ ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry
+ * @{
+ */
+
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
+#define PWR_FLAG_VOS PWR_CSR_VOSF
+#define PWR_FLAG_REGLP PWR_CSR_REGLPF
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
+ ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/
+void PWR_DeInit(void);
+
+/* RTC Domain Access function *************************************************/
+void PWR_RTCAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration functions ****************************************/
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
+
+/* Ultra Low Power mode configuration functions *******************************/
+void PWR_FastWakeUpCmd(FunctionalState NewState);
+void PWR_UltraLowPowerCmd(FunctionalState NewState);
+
+/* Voltage Scaling configuration functions ************************************/
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);
+
+/* Low Power modes configuration functions ************************************/
+void PWR_EnterLowPowerRunMode(FunctionalState NewState);
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_PWR_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_rcc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,488 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_rcc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the RCC
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_RCC_H
+#define __STM32L1xx_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+ uint32_t SYSCLK_Frequency;
+ uint32_t HCLK_Frequency;
+ uint32_t PCLK1_Frequency;
+ uint32_t PCLK2_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCC_HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint8_t)0x00)
+#define RCC_HSE_ON ((uint8_t)0x01)
+#define RCC_HSE_Bypass ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MSI_Clock_Range
+ * @{
+ */
+
+#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
+#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
+#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
+#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
+#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
+#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
+#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
+
+#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \
+ ((RANGE) == RCC_MSIRange_1) || \
+ ((RANGE) == RCC_MSIRange_2) || \
+ ((RANGE) == RCC_MSIRange_3) || \
+ ((RANGE) == RCC_MSIRange_4) || \
+ ((RANGE) == RCC_MSIRange_5) || \
+ ((RANGE) == RCC_MSIRange_6))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI ((uint8_t)0x00)
+#define RCC_PLLSource_HSE ((uint8_t)0x01)
+
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
+ ((SOURCE) == RCC_PLLSource_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Multiplication_Factor
+ * @{
+ */
+
+#define RCC_PLLMul_3 ((uint8_t)0x00)
+#define RCC_PLLMul_4 ((uint8_t)0x04)
+#define RCC_PLLMul_6 ((uint8_t)0x08)
+#define RCC_PLLMul_8 ((uint8_t)0x0C)
+#define RCC_PLLMul_12 ((uint8_t)0x10)
+#define RCC_PLLMul_16 ((uint8_t)0x14)
+#define RCC_PLLMul_24 ((uint8_t)0x18)
+#define RCC_PLLMul_32 ((uint8_t)0x1C)
+#define RCC_PLLMul_48 ((uint8_t)0x20)
+
+
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \
+ ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \
+ ((MUL) == RCC_PLLMul_48))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Divider_Factor
+ * @{
+ */
+
+#define RCC_PLLDiv_2 ((uint8_t)0x40)
+#define RCC_PLLDiv_3 ((uint8_t)0x80)
+#define RCC_PLLDiv_4 ((uint8_t)0xC0)
+
+
+#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \
+ ((DIV) == RCC_PLLDiv_4))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source
+ * @{
+ */
+
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source
+ * @{
+ */
+
+#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_Interrupt_Source
+ * @{
+ */
+
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_MSIRDY ((uint8_t)0x20)
+#define RCC_IT_LSECSS ((uint8_t)0x40)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
+ ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_LSECSS))
+
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration
+ * @{
+ */
+
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_Bypass ((uint8_t)0x05)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source
+ * @{
+ */
+
+#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE
+#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI
+#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE
+#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
+#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
+#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripherals
+ * @{
+ */
+
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
+#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
+#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
+#define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
+#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
+#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
+#define RCC_AHBPeriph_AES RCC_AHBENR_AESEN
+#define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripherals
+ * @{
+ */
+
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
+#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN
+#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN
+#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
+#define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripherals
+ * @{
+ */
+
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
+#define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
+#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
+#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
+#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
+#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
+#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN
+
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Clock_Source
+ * @{
+ */
+
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)
+#define RCC_MCOSource_HSI ((uint8_t)0x02)
+#define RCC_MCOSource_MSI ((uint8_t)0x03)
+#define RCC_MCOSource_HSE ((uint8_t)0x04)
+#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)
+#define RCC_MCOSource_LSI ((uint8_t)0x06)
+#define RCC_MCOSource_LSE ((uint8_t)0x07)
+
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \
+ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Output_Divider
+ * @{
+ */
+
+#define RCC_MCODiv_1 ((uint8_t)0x00)
+#define RCC_MCODiv_2 ((uint8_t)0x10)
+#define RCC_MCODiv_4 ((uint8_t)0x20)
+#define RCC_MCODiv_8 ((uint8_t)0x30)
+#define RCC_MCODiv_16 ((uint8_t)0x40)
+
+#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \
+ ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \
+ ((DIV) == RCC_MCODiv_16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY ((uint8_t)0x49)
+#define RCC_FLAG_LSECSS ((uint8_t)0x4A)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \
+ ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
+ ((FLAG) == RCC_FLAG_OBLRST)|| ((FLAG) == RCC_FLAG_LSECSS))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);
+void RCC_MSICmd(FunctionalState NewState);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_RTCResetCmd(FunctionalState NewState);
+
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_RCC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_rtc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,896 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_rtc.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the RTC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_RTC_H
+#define __STM32L1xx_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be set to a value lower than 0x7F */
+
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be set to a value lower than 0x7FFF */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be set to a value in the 0-12 range
+ if the RTC_HourFormat_12 is selected or 0-23 range if
+ the RTC_HourFormat_24 is selected. */
+
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.
+ This parameter must be set to a value in the 1-31 range. */
+
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
+ This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter
+ must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this
+ parameter can be a value of @ref RTC_WeekDay_Definitions */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
+ ((FORMAT) == RTC_HourFormat_24))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_H12_AM ((uint8_t)0x00)
+#define RTC_H12_PM ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_Month_January ((uint8_t)0x01)
+#define RTC_Month_February ((uint8_t)0x02)
+#define RTC_Month_March ((uint8_t)0x03)
+#define RTC_Month_April ((uint8_t)0x04)
+#define RTC_Month_May ((uint8_t)0x05)
+#define RTC_Month_June ((uint8_t)0x06)
+#define RTC_Month_July ((uint8_t)0x07)
+#define RTC_Month_August ((uint8_t)0x08)
+#define RTC_Month_September ((uint8_t)0x09)
+#define RTC_Month_October ((uint8_t)0x10)
+#define RTC_Month_November ((uint8_t)0x11)
+#define RTC_Month_December ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_Weekday_Monday ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday ((uint8_t)0x03)
+#define RTC_Weekday_Thursday ((uint8_t)0x04)
+#define RTC_Weekday_Friday ((uint8_t)0x05)
+#define RTC_Weekday_Saturday ((uint8_t)0x06)
+#define RTC_Weekday_Sunday ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \
+ ((WEEKDAY) == RTC_Weekday_Friday) || \
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \
+ ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \
+ ((WEEKDAY) == RTC_Weekday_Friday) || \
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \
+ ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_Alarm_A ((uint32_t)0x00000100)
+#define RTC_Alarm_B ((uint32_t)0x00000200)
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+ ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+ ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_Output_Disable ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)
+#define RTC_Output_AlarmB ((uint32_t)0x00400000)
+#define RTC_Output_WakeUp ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+ ((OUTPUT) == RTC_Output_AlarmA) || \
+ ((OUTPUT) == RTC_Output_AlarmB) || \
+ ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+ ((POL) == RTC_OutputPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Coarse_Calibration_Definitions
+ * @{
+ */
+#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
+#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
+ ((SIGN) == RTC_CalibSign_Negative))
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
+#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+ ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+ ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0].
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
+ ((SAVE) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+ ((OPERATION) == RTC_StoreOperation_Set))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+ ((FILTER) == RTC_TamperFilter_2Sample) || \
+ ((FILTER) == RTC_TamperFilter_4Sample) || \
+ ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
+ input tamper 1 */
+#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
+ input tamper 2 */
+#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
+ input tamper 3 */
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+ ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+ ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Backup_Registers_Definitions
+ * @{
+ */
+
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)
+#define RTC_BKP_DR20 ((uint32_t)0x00000014)
+#define RTC_BKP_DR21 ((uint32_t)0x00000015)
+#define RTC_BKP_DR22 ((uint32_t)0x00000016)
+#define RTC_BKP_DR23 ((uint32_t)0x00000017)
+#define RTC_BKP_DR24 ((uint32_t)0x00000018)
+#define RTC_BKP_DR25 ((uint32_t)0x00000019)
+#define RTC_BKP_DR26 ((uint32_t)0x0000001A)
+#define RTC_BKP_DR27 ((uint32_t)0x0000001B)
+#define RTC_BKP_DR28 ((uint32_t)0x0000001C)
+#define RTC_BKP_DR29 ((uint32_t)0x0000001D)
+#define RTC_BKP_DR30 ((uint32_t)0x0000001E)
+#define RTC_BKP_DR31 ((uint32_t)0x0000001F)
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4) || \
+ ((BKP) == RTC_BKP_DR5) || \
+ ((BKP) == RTC_BKP_DR6) || \
+ ((BKP) == RTC_BKP_DR7) || \
+ ((BKP) == RTC_BKP_DR8) || \
+ ((BKP) == RTC_BKP_DR9) || \
+ ((BKP) == RTC_BKP_DR10) || \
+ ((BKP) == RTC_BKP_DR11) || \
+ ((BKP) == RTC_BKP_DR12) || \
+ ((BKP) == RTC_BKP_DR13) || \
+ ((BKP) == RTC_BKP_DR14) || \
+ ((BKP) == RTC_BKP_DR15) || \
+ ((BKP) == RTC_BKP_DR16) || \
+ ((BKP) == RTC_BKP_DR17) || \
+ ((BKP) == RTC_BKP_DR18) || \
+ ((BKP) == RTC_BKP_DR19) || \
+ ((BKP) == RTC_BKP_DR20) || \
+ ((BKP) == RTC_BKP_DR21) || \
+ ((BKP) == RTC_BKP_DR22) || \
+ ((BKP) == RTC_BKP_DR23) || \
+ ((BKP) == RTC_BKP_DR24) || \
+ ((BKP) == RTC_BKP_DR25) || \
+ ((BKP) == RTC_BKP_DR26) || \
+ ((BKP) == RTC_BKP_DR27) || \
+ ((BKP) == RTC_BKP_DR28) || \
+ ((BKP) == RTC_BKP_DR29) || \
+ ((BKP) == RTC_BKP_DR30) || \
+ ((BKP) == RTC_BKP_DR31))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_Format_BIN ((uint32_t)0x000000000)
+#define RTC_Format_BCD ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
+ ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+ ((FLAG) == RTC_FLAG_SHPF)|| ((FLAG) == RTC_FLAG_INITS))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_IT_TS ((uint32_t)0x00008000)
+#define RTC_IT_WUT ((uint32_t)0x00004000)
+#define RTC_IT_ALRB ((uint32_t)0x00002000)
+#define RTC_IT_ALRA ((uint32_t)0x00001000)
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
+
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
+ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
+ ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
+ ((IT) == RTC_IT_TAMP3))
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Legacy
+ * @{
+ */
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Coarse and Smooth Calibration configuration functions **********************/
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
+ RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_RTC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_sdio.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,535 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_sdio.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the SDIO firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_SDIO_H
+#define __STM32L1xx_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between 0x00 and 0xFF. */
+
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register */
+
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SDIO_Clock_Edge
+ * @{
+ */
+
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+ ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Bypass
+ * @{
+ */
+
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+ ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Power_Save
+ * @{
+ */
+
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+ ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Bus_Wide
+ * @{
+ */
+
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+ ((WIDE) == SDIO_BusWide_8b))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Power_State
+ * @{
+ */
+
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+/**
+ * @}
+ */
+
+
+/** @defgroup SDIO_Interrupt_soucres
+ * @{
+ */
+
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Command_Index
+ * @{
+ */
+
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Type
+ * @{
+ */
+
+#define SDIO_Response_No ((uint32_t)0x00000000)
+#define SDIO_Response_Short ((uint32_t)0x00000040)
+#define SDIO_Response_Long ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+ ((RESPONSE) == SDIO_Response_Short) || \
+ ((RESPONSE) == SDIO_Response_Long))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+ ((WAIT) == SDIO_Wait_Pend))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_CPSM_State
+ * @{
+ */
+
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Registers
+ * @{
+ */
+
+#define SDIO_RESP1 ((uint32_t)0x00000000)
+#define SDIO_RESP2 ((uint32_t)0x00000004)
+#define SDIO_RESP3 ((uint32_t)0x00000008)
+#define SDIO_RESP4 ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Length
+ * @{
+ */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Block_Size
+ * @{
+ */
+
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+ ((SIZE) == SDIO_DataBlockSize_2b) || \
+ ((SIZE) == SDIO_DataBlockSize_4b) || \
+ ((SIZE) == SDIO_DataBlockSize_8b) || \
+ ((SIZE) == SDIO_DataBlockSize_16b) || \
+ ((SIZE) == SDIO_DataBlockSize_32b) || \
+ ((SIZE) == SDIO_DataBlockSize_64b) || \
+ ((SIZE) == SDIO_DataBlockSize_128b) || \
+ ((SIZE) == SDIO_DataBlockSize_256b) || \
+ ((SIZE) == SDIO_DataBlockSize_512b) || \
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \
+ ((SIZE) == SDIO_DataBlockSize_16384b))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Direction
+ * @{
+ */
+
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+ ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Type
+ * @{
+ */
+
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+ ((MODE) == SDIO_TransferMode_Block))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_DPSM_State
+ * @{
+ */
+
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Flags
+ * @{
+ */
+
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \
+ ((FLAG) == SDIO_FLAG_CMDREND) || \
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \
+ ((FLAG) == SDIO_FLAG_DATAEND) || \
+ ((FLAG) == SDIO_FLAG_STBITERR) || \
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \
+ ((FLAG) == SDIO_FLAG_CMDACT) || \
+ ((FLAG) == SDIO_FLAG_TXACT) || \
+ ((FLAG) == SDIO_FLAG_RXACT) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \
+ ((FLAG) == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+ ((IT) == SDIO_IT_DCRCFAIL) || \
+ ((IT) == SDIO_IT_CTIMEOUT) || \
+ ((IT) == SDIO_IT_DTIMEOUT) || \
+ ((IT) == SDIO_IT_TXUNDERR) || \
+ ((IT) == SDIO_IT_RXOVERR) || \
+ ((IT) == SDIO_IT_CMDREND) || \
+ ((IT) == SDIO_IT_CMDSENT) || \
+ ((IT) == SDIO_IT_DATAEND) || \
+ ((IT) == SDIO_IT_STBITERR) || \
+ ((IT) == SDIO_IT_DBCKEND) || \
+ ((IT) == SDIO_IT_CMDACT) || \
+ ((IT) == SDIO_IT_TXACT) || \
+ ((IT) == SDIO_IT_RXACT) || \
+ ((IT) == SDIO_IT_TXFIFOHE) || \
+ ((IT) == SDIO_IT_RXFIFOHF) || \
+ ((IT) == SDIO_IT_TXFIFOF) || \
+ ((IT) == SDIO_IT_RXFIFOF) || \
+ ((IT) == SDIO_IT_TXFIFOE) || \
+ ((IT) == SDIO_IT_RXFIFOE) || \
+ ((IT) == SDIO_IT_TXDAVL) || \
+ ((IT) == SDIO_IT_RXDAVL) || \
+ ((IT) == SDIO_IT_SDIOIT) || \
+ ((IT) == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Read_Wait_Mode
+ * @{
+ */
+
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+ ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the SDIO configuration to the default reset state ****/
+void SDIO_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+
+/* DMA transfers management functions *****************************************/
+void SDIO_DMACmd(FunctionalState NewState);
+
+/* Command path state machine (CPSM) management functions *********************/
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+
+/* Data path state machine (DPSM) management functions ************************/
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+
+/* SDIO IO Cards mode management functions ************************************/
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+
+/* CE-ATA mode management functions *******************************************/
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_SDIO_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_spi.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,524 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_spi.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the SPI
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_SPI_H
+#define __STM32L1xx_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref SPI_I2S_Mode */
+
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref SPI_I2S_Standard */
+
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref SPI_I2S_Data_Format */
+
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref SPI_I2S_MCLK_Output */
+
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
+
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+ ((MODE) == SPI_Direction_1Line_Rx) || \
+ ((MODE) == SPI_Direction_1Line_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+ ((MODE) == SPI_Mode_Slave))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DataSize_16b ((uint16_t)0x0800)
+#define SPI_DataSize_8b ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+ ((DATASIZE) == SPI_DataSize_8b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+ ((CPOL) == SPI_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+ ((CPHA) == SPI_CPHA_2Edge))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_Soft ((uint16_t)0x0200)
+#define SPI_NSS_Hard ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+ ((NSS) == SPI_NSS_Hard))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+ ((BIT) == SPI_FirstBit_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Mode
+ * @{
+ */
+
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+ ((MODE) == I2S_Mode_SlaveRx) || \
+ ((MODE) == I2S_Mode_MasterTx)|| \
+ ((MODE) == I2S_Mode_MasterRx))
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_I2S_Standard
+ * @{
+ */
+
+#define I2S_Standard_Phillips ((uint16_t)0x0000)
+#define I2S_Standard_MSB ((uint16_t)0x0010)
+#define I2S_Standard_LSB ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+ ((STANDARD) == I2S_Standard_MSB) || \
+ ((STANDARD) == I2S_Standard_LSB) || \
+ ((STANDARD) == I2S_Standard_PCMShort) || \
+ ((STANDARD) == I2S_Standard_PCMLong))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DataFormat_16b ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+#define I2S_DataFormat_24b ((uint16_t)0x0003)
+#define I2S_DataFormat_32b ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+ ((FORMAT) == I2S_DataFormat_16bextended) || \
+ ((FORMAT) == I2S_DataFormat_24b) || \
+ ((FORMAT) == I2S_DataFormat_32b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+ ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AudioFreq_192k ((uint32_t)192000)
+#define I2S_AudioFreq_96k ((uint32_t)96000)
+#define I2S_AudioFreq_48k ((uint32_t)48000)
+#define I2S_AudioFreq_44k ((uint32_t)44100)
+#define I2S_AudioFreq_32k ((uint32_t)32000)
+#define I2S_AudioFreq_22k ((uint32_t)22050)
+#define I2S_AudioFreq_16k ((uint32_t)16000)
+#define I2S_AudioFreq_11k ((uint32_t)11025)
+#define I2S_AudioFreq_8k ((uint32_t)8000)
+#define I2S_AudioFreq_Default ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+ ((FREQ) <= I2S_AudioFreq_192k)) || \
+ ((FREQ) == I2S_AudioFreq_Default))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CPOL_Low ((uint16_t)0x0000)
+#define I2S_CPOL_High ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+ ((CPOL) == I2S_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+ ((DIRECTION) == SPI_Direction_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
+#define I2S_IT_UDR ((uint8_t)0x53)
+#define SPI_I2S_IT_FRE ((uint8_t)0x58)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_RXNE) || \
+ ((IT) == SPI_I2S_IT_ERR))
+
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_IT_CRCERR ((uint8_t)0x54)
+
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
+ ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
+ ((IT) == SPI_I2S_IT_FRE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+#define I2S_FLAG_UDR ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+#define SPI_FLAG_MODF ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
+#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
+
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+ ((FLAG) == SPI_I2S_FLAG_FRE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_Legacy
+ * @{
+ */
+
+#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
+#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
+#define SPI_IT_TXE SPI_I2S_IT_TXE
+#define SPI_IT_RXNE SPI_I2S_IT_RXNE
+#define SPI_IT_ERR SPI_I2S_IT_ERR
+#define SPI_IT_OVR SPI_I2S_IT_OVR
+#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
+#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
+#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
+#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
+#define SPI_DeInit SPI_I2S_DeInit
+#define SPI_ITConfig SPI_I2S_ITConfig
+#define SPI_DMACmd SPI_I2S_DMACmd
+#define SPI_SendData SPI_I2S_SendData
+#define SPI_ReceiveData SPI_I2S_ReceiveData
+#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
+#define SPI_ClearFlag SPI_I2S_ClearFlag
+#define SPI_GetITStatus SPI_I2S_GetITStatus
+#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the SPI configuration to the default reset state *****/
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+
+/* Initialization and Configuration functions *********************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_SPI_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_syscfg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,476 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_syscfg.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the SYSCFG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/*!< Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_SYSCFG_H
+#define __STM32L1xx_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SYSCFG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Port_Sources
+ * @{
+ */
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOH ((uint8_t)0x05)
+#define EXTI_PortSourceGPIOF ((uint8_t)0x06)
+#define EXTI_PortSourceGPIOG ((uint8_t)0x07)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOH))
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Pin_sources
+ * @{
+ */
+#define EXTI_PinSource0 ((uint8_t)0x00)
+#define EXTI_PinSource1 ((uint8_t)0x01)
+#define EXTI_PinSource2 ((uint8_t)0x02)
+#define EXTI_PinSource3 ((uint8_t)0x03)
+#define EXTI_PinSource4 ((uint8_t)0x04)
+#define EXTI_PinSource5 ((uint8_t)0x05)
+#define EXTI_PinSource6 ((uint8_t)0x06)
+#define EXTI_PinSource7 ((uint8_t)0x07)
+#define EXTI_PinSource8 ((uint8_t)0x08)
+#define EXTI_PinSource9 ((uint8_t)0x09)
+#define EXTI_PinSource10 ((uint8_t)0x0A)
+#define EXTI_PinSource11 ((uint8_t)0x0B)
+#define EXTI_PinSource12 ((uint8_t)0x0C)
+#define EXTI_PinSource13 ((uint8_t)0x0D)
+#define EXTI_PinSource14 ((uint8_t)0x0E)
+#define EXTI_PinSource15 ((uint8_t)0x0F)
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+ ((PINSOURCE) == EXTI_PinSource1) || \
+ ((PINSOURCE) == EXTI_PinSource2) || \
+ ((PINSOURCE) == EXTI_PinSource3) || \
+ ((PINSOURCE) == EXTI_PinSource4) || \
+ ((PINSOURCE) == EXTI_PinSource5) || \
+ ((PINSOURCE) == EXTI_PinSource6) || \
+ ((PINSOURCE) == EXTI_PinSource7) || \
+ ((PINSOURCE) == EXTI_PinSource8) || \
+ ((PINSOURCE) == EXTI_PinSource9) || \
+ ((PINSOURCE) == EXTI_PinSource10) || \
+ ((PINSOURCE) == EXTI_PinSource11) || \
+ ((PINSOURCE) == EXTI_PinSource12) || \
+ ((PINSOURCE) == EXTI_PinSource13) || \
+ ((PINSOURCE) == EXTI_PinSource14) || \
+ ((PINSOURCE) == EXTI_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Memory_Remap_Config
+ * @{
+ */
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
+
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+ ((REMAP) == SYSCFG_MemoryRemap_FSMC) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+ * @}
+ */
+
+/** @defgroup RI_Resistor
+ * @{
+ */
+
+#define RI_Resistor_10KPU COMP_CSR_10KPU
+#define RI_Resistor_400KPU COMP_CSR_400KPU
+#define RI_Resistor_10KPD COMP_CSR_10KPD
+#define RI_Resistor_400KPD COMP_CSR_400KPD
+
+#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \
+ ((RESISTOR) == COMP_CSR_400KPU) || \
+ ((RESISTOR) == COMP_CSR_10KPD) || \
+ ((RESISTOR) == COMP_CSR_400KPD))
+
+/**
+ * @}
+ */
+
+/** @defgroup RI_Channel
+ * @{
+ */
+
+#define RI_Channel_3 ((uint32_t)0x04000000)
+#define RI_Channel_8 ((uint32_t)0x08000000)
+#define RI_Channel_13 ((uint32_t)0x10000000)
+
+#define IS_RI_CHANNEL(CHANNEL) (((CHANNEL) == RI_Channel_3) || \
+ ((CHANNEL) == RI_Channel_8) || \
+ ((CHANNEL) == RI_Channel_13))
+
+/**
+ * @}
+ */
+
+/** @defgroup RI_ChannelSpeed
+ * @{
+ */
+
+#define RI_ChannelSpeed_Fast ((uint32_t)0x00000000)
+#define RI_ChannelSpeed_Slow ((uint32_t)0x00000001)
+
+#define IS_RI_CHANNELSPEED(SPEED) (((SPEED) == RI_ChannelSpeed_Fast) || \
+ ((SPEED) == RI_ChannelSpeed_Slow))
+
+/**
+ * @}
+ */
+
+/** @defgroup RI_InputCapture
+ * @{
+ */
+
+#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
+#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
+#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
+#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
+
+#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Select
+ * @{
+ */
+
+#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */
+#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */
+#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */
+#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */
+
+#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \
+ ((TIM) == TIM_Select_TIM2) || \
+ ((TIM) == TIM_Select_TIM3) || \
+ ((TIM) == TIM_Select_TIM4))
+
+/**
+ * @}
+ */
+
+/** @defgroup RI_InputCaptureRouting
+ * @{
+ */
+ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
+#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */
+#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */
+#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */
+#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */
+#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */
+#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */
+#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */
+#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */
+#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */
+#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */
+#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */
+#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */
+#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */
+#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */
+#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */
+#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */
+
+#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \
+ ((ROUTING) == RI_InputCaptureRouting_1) || \
+ ((ROUTING) == RI_InputCaptureRouting_2) || \
+ ((ROUTING) == RI_InputCaptureRouting_3) || \
+ ((ROUTING) == RI_InputCaptureRouting_4) || \
+ ((ROUTING) == RI_InputCaptureRouting_5) || \
+ ((ROUTING) == RI_InputCaptureRouting_6) || \
+ ((ROUTING) == RI_InputCaptureRouting_7) || \
+ ((ROUTING) == RI_InputCaptureRouting_8) || \
+ ((ROUTING) == RI_InputCaptureRouting_9) || \
+ ((ROUTING) == RI_InputCaptureRouting_10) || \
+ ((ROUTING) == RI_InputCaptureRouting_11) || \
+ ((ROUTING) == RI_InputCaptureRouting_12) || \
+ ((ROUTING) == RI_InputCaptureRouting_13) || \
+ ((ROUTING) == RI_InputCaptureRouting_14) || \
+ ((ROUTING) == RI_InputCaptureRouting_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup RI_IOSwitch
+ * @{
+ */
+
+/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
+#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)
+#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)
+#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)
+#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)
+#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)
+#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)
+#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)
+#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)
+#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)
+#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)
+#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)
+#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)
+#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)
+#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)
+#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)
+#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)
+#define RI_IOSwitch_CH31 ((uint32_t)0x80010000)
+#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)
+#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)
+#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)
+#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)
+#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)
+#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)
+#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)
+#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)
+#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect
+ selected channel to COMP1 non inverting input */
+#define RI_IOSwitch_CH27 ((uint32_t)0x88000000)
+#define RI_IOSwitch_CH28 ((uint32_t)0x90000000)
+#define RI_IOSwitch_CH29 ((uint32_t)0xA0000000)
+#define RI_IOSwitch_CH30 ((uint32_t)0xC0000000)
+
+/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
+#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)
+#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)
+#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)
+#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)
+#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)
+#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)
+#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)
+#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)
+#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)
+#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)
+#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)
+#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)
+#define RI_IOSwitch_GR4_4 ((uint32_t)0x00008000)
+#define RI_IOSwitch_CH0b ((uint32_t)0x00010000)
+#define RI_IOSwitch_CH1b ((uint32_t)0x00020000)
+#define RI_IOSwitch_CH2b ((uint32_t)0x00040000)
+#define RI_IOSwitch_CH3b ((uint32_t)0x00080000)
+#define RI_IOSwitch_CH6b ((uint32_t)0x00100000)
+#define RI_IOSwitch_CH7b ((uint32_t)0x00200000)
+#define RI_IOSwitch_CH8b ((uint32_t)0x00400000)
+#define RI_IOSwitch_CH9b ((uint32_t)0x00800000)
+#define RI_IOSwitch_CH10b ((uint32_t)0x01000000)
+#define RI_IOSwitch_CH11b ((uint32_t)0x02000000)
+#define RI_IOSwitch_CH12b ((uint32_t)0x04000000)
+#define RI_IOSwitch_GR6_3 ((uint32_t)0x08000000)
+#define RI_IOSwitch_GR6_4 ((uint32_t)0x10000000)
+#define RI_IOSwitch_GR5_4 ((uint32_t)0x20000000)
+
+
+#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \
+ ((IOSWITCH) == RI_IOSwitch_CH1) || \
+ ((IOSWITCH) == RI_IOSwitch_CH2) || \
+ ((IOSWITCH) == RI_IOSwitch_CH3) || \
+ ((IOSWITCH) == RI_IOSwitch_CH4) || \
+ ((IOSWITCH) == RI_IOSwitch_CH5) || \
+ ((IOSWITCH) == RI_IOSwitch_CH6) || \
+ ((IOSWITCH) == RI_IOSwitch_CH7) || \
+ ((IOSWITCH) == RI_IOSwitch_CH8) || \
+ ((IOSWITCH) == RI_IOSwitch_CH9) || \
+ ((IOSWITCH) == RI_IOSwitch_CH10) || \
+ ((IOSWITCH) == RI_IOSwitch_CH11) || \
+ ((IOSWITCH) == RI_IOSwitch_CH12) || \
+ ((IOSWITCH) == RI_IOSwitch_CH13) || \
+ ((IOSWITCH) == RI_IOSwitch_CH14) || \
+ ((IOSWITCH) == RI_IOSwitch_CH15) || \
+ ((IOSWITCH) == RI_IOSwitch_CH18) || \
+ ((IOSWITCH) == RI_IOSwitch_CH19) || \
+ ((IOSWITCH) == RI_IOSwitch_CH20) || \
+ ((IOSWITCH) == RI_IOSwitch_CH21) || \
+ ((IOSWITCH) == RI_IOSwitch_CH22) || \
+ ((IOSWITCH) == RI_IOSwitch_CH23) || \
+ ((IOSWITCH) == RI_IOSwitch_CH24) || \
+ ((IOSWITCH) == RI_IOSwitch_CH25) || \
+ ((IOSWITCH) == RI_IOSwitch_VCOMP) || \
+ ((IOSWITCH) == RI_IOSwitch_CH27) || \
+ ((IOSWITCH) == RI_IOSwitch_CH28) || \
+ ((IOSWITCH) == RI_IOSwitch_CH29) || \
+ ((IOSWITCH) == RI_IOSwitch_CH30) || \
+ ((IOSWITCH) == RI_IOSwitch_CH31) || \
+ ((IOSWITCH) == RI_IOSwitch_GR10_1) || \
+ ((IOSWITCH) == RI_IOSwitch_GR10_2) || \
+ ((IOSWITCH) == RI_IOSwitch_GR10_3) || \
+ ((IOSWITCH) == RI_IOSwitch_GR10_4) || \
+ ((IOSWITCH) == RI_IOSwitch_GR6_1) || \
+ ((IOSWITCH) == RI_IOSwitch_GR6_2) || \
+ ((IOSWITCH) == RI_IOSwitch_GR6_3) || \
+ ((IOSWITCH) == RI_IOSwitch_GR6_4) || \
+ ((IOSWITCH) == RI_IOSwitch_GR5_1) || \
+ ((IOSWITCH) == RI_IOSwitch_GR5_2) || \
+ ((IOSWITCH) == RI_IOSwitch_GR5_3) || \
+ ((IOSWITCH) == RI_IOSwitch_GR5_4) || \
+ ((IOSWITCH) == RI_IOSwitch_GR4_1) || \
+ ((IOSWITCH) == RI_IOSwitch_GR4_2) || \
+ ((IOSWITCH) == RI_IOSwitch_GR4_3) || \
+ ((IOSWITCH) == RI_IOSwitch_GR4_4) || \
+ ((IOSWITCH) == RI_IOSwitch_CH0b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH1b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH2b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH3b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH6b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH7b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH8b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH9b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH10b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH11b) || \
+ ((IOSWITCH) == RI_IOSwitch_CH12b))
+
+/**
+ * @}
+ */
+
+/** @defgroup RI_Port
+ * @{
+ */
+
+#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */
+#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */
+#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */
+#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */
+#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */
+#define RI_PortF ((uint8_t)0x06) /*!< GPIOF selected */
+#define RI_PortG ((uint8_t)0x07) /*!< GPIOG selected */
+
+#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \
+ ((PORT) == RI_PortB) || \
+ ((PORT) == RI_PortC) || \
+ ((PORT) == RI_PortD) || \
+ ((PORT) == RI_PortE) || \
+ ((PORT) == RI_PortF) || \
+ ((PORT) == RI_PortG))
+/**
+ * @}
+ */
+
+/** @defgroup RI_Pin define
+ * @{
+ */
+#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the SYSCFG and RI configuration to the default reset state **/
+void SYSCFG_DeInit(void);
+void SYSCFG_RIDeInit(void);
+
+/* SYSCFG Initialization and Configuration functions **************************/
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
+uint32_t SYSCFG_GetBootMode(void);
+void SYSCFG_USBPuCmd(FunctionalState NewState);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+
+/* RI Initialization and Configuration functions ******************************/
+void SYSCFG_RITIMSelect(uint32_t TIM_Select);
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);
+void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed);
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_SYSCFG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_tim.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,982 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_tim.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the TIM firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_TIM_H
+#define __STM32L1xx_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+} TIM_TimeBaseInitTypeDef;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+} TIM_OCInitTypeDef;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM10) || \
+ ((PERIPH) == TIM11))
+
+/* LIST1: TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11 */
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM10) || \
+ ((PERIPH) == TIM11))
+
+/* LIST3: TIM2, TIM3, TIM4 and TIM5 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5))
+
+/* LIST2: TIM2, TIM3, TIM4, TIM5 and TIM9 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM9))
+
+/* LIST5: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM9 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) ||\
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) ||\
+ ((PERIPH) == TIM9))
+
+/* LIST4: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) ||\
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7))
+
+/* LIST6: TIM2, TIM3, TIM9, TIM10 and TIM11 */
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM10) || \
+ ((PERIPH) == TIM11))
+
+/* LIST3: TIM2, TIM3, TIM4, TIM5 and TIM9 */
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM9))
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMode_Timing ((uint16_t)0x0000)
+#define TIM_OCMode_Active ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_ForcedAction_Active) || \
+ ((MODE) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+ ((MODE) == TIM_OPMode_Repetitive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
+
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3) || \
+ ((CHANNEL) == TIM_Channel_4))
+
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+ ((DIV) == TIM_CKD_DIV2) || \
+ ((DIV) == TIM_CKD_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+ ((MODE) == TIM_CounterMode_Down) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+ ((POLARITY) == TIM_OCPolarity_Low))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+ ((STATE) == TIM_OutputState_Enable))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+ ((CCX) == TIM_CCx_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \
+ ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+ ((SELECTION) == TIM_ICSelection_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_Trigger))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
+#define TIM_DMABase_OR ((uint16_t)0x0013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_DCR) || \
+ ((BASE) == TIM_DMABase_OR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+ ((ACTION) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+ ((MODE) == TIM_EncoderMode_TI2) || \
+ ((MODE) == TIM_EncoderMode_TI12))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+ ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+ ((STATE) == TIM_OCPreload_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+ ((STATE) == TIM_OCFast_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+ ((STATE) == TIM_OCClear_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+ ((SOURCE) == TIM_TRGOSource_Enable) || \
+ ((SOURCE) == TIM_TRGOSource_Update) || \
+ ((SOURCE) == TIM_TRGOSource_OC1) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+ ((MODE) == TIM_SlaveMode_Gated) || \
+ ((MODE) == TIM_SlaveMode_Trigger) || \
+ ((MODE) == TIM_SlaveMode_External1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_Update ((uint16_t)0x0001)
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_Trigger) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OCReferenceClear
+ * @{
+ */
+#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
+#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
+ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Remap
+ * @{
+ */
+
+#define TIM2_TIM10_OC ((uint32_t)0xFFFE0000)
+#define TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001)
+
+#define TIM3_TIM11_OC ((uint32_t)0xFFFE0000)
+#define TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001)
+
+#define TIM9_GPIO ((uint32_t)0xFFFC0000)
+#define TIM9_LSE ((uint32_t)0xFFFC0001)
+
+#define TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000)
+#define TIM9_TS_IO ((uint32_t)0xFFFB0004)
+
+#define TIM10_GPIO ((uint32_t)0xFFF40000)
+#define TIM10_LSI ((uint32_t)0xFFF40001)
+#define TIM10_LSE ((uint32_t)0xFFF40002)
+#define TIM10_RTC ((uint32_t)0xFFF40003)
+#define TIM10_RI ((uint32_t)0xFFF40008)
+
+#define TIM10_ETR_LSE ((uint32_t)0xFFFB0000)
+#define TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
+
+#define TIM11_GPIO ((uint32_t)0xFFF40000)
+#define TIM11_MSI ((uint32_t)0xFFF40001)
+#define TIM11_HSE_RTC ((uint32_t)0xFFF40002)
+#define TIM11_RI ((uint32_t)0xFFF40008)
+
+#define TIM11_ETR_LSE ((uint32_t)0xFFFB0000)
+#define TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
+
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM10_OC)|| \
+ ((TIM_REMAP) == TIM2_TIM5_TRGO)|| \
+ ((TIM_REMAP) == TIM3_TIM11_OC)|| \
+ ((TIM_REMAP) == TIM3_TIM5_TRGO)|| \
+ ((TIM_REMAP) == TIM9_GPIO)|| \
+ ((TIM_REMAP) == TIM9_LSE)|| \
+ ((TIM_REMAP) == TIM9_TIM3_TRGO)|| \
+ ((TIM_REMAP) == TIM9_TS_IO)|| \
+ ((TIM_REMAP) == TIM10_GPIO)|| \
+ ((TIM_REMAP) == TIM10_LSI)|| \
+ ((TIM_REMAP) == TIM10_LSE)|| \
+ ((TIM_REMAP) == TIM10_RTC)|| \
+ ((TIM_REMAP) == TIM10_RI)|| \
+ ((TIM_REMAP) == TIM10_ETR_LSE)|| \
+ ((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)|| \
+ ((TIM_REMAP) == TIM11_GPIO)|| \
+ ((TIM_REMAP) == TIM11_MSI)|| \
+ ((TIM_REMAP) == TIM11_HSE_RTC)|| \
+ ((TIM_REMAP) == TIM11_RI)|| \
+ ((TIM_REMAP) == TIM11_ETR_LSE)|| \
+ ((TIM_REMAP) == TIM11_ETR_TIM9_TRGO))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_TIM_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_usart.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,427 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_usart.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the USART
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_USART_H
+#define __STM32L1xx_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief USART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
+ Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t USART_Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_Clock */
+
+ uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4) || \
+ ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3))
+
+/** @defgroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WordLength_8b ((uint16_t)0x0000)
+#define USART_WordLength_9b ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+ ((LENGTH) == USART_WordLength_9b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_StopBits_1 ((uint16_t)0x0000)
+#define USART_StopBits_0_5 ((uint16_t)0x1000)
+#define USART_StopBits_2 ((uint16_t)0x2000)
+#define USART_StopBits_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+ ((STOPBITS) == USART_StopBits_0_5) || \
+ ((STOPBITS) == USART_StopBits_2) || \
+ ((STOPBITS) == USART_StopBits_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+
+#define USART_Parity_No ((uint16_t)0x0000)
+#define USART_Parity_Even ((uint16_t)0x0400)
+#define USART_Parity_Odd ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+ ((PARITY) == USART_Parity_Even) || \
+ ((PARITY) == USART_Parity_Odd))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+
+#define USART_Mode_Rx ((uint16_t)0x0004)
+#define USART_Mode_Tx ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == USART_HardwareFlowControl_None) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+#define USART_Clock_Disable ((uint16_t)0x0000)
+#define USART_Clock_Enable ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+ ((CLOCK) == USART_Clock_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CPOL_Low ((uint16_t)0x0000)
+#define USART_CPOL_High ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CPHA_1Edge ((uint16_t)0x0000)
+#define USART_CPHA_2Edge ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_LastBit_Disable ((uint16_t)0x0000)
+#define USART_LastBit_Enable ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+ ((LASTBIT) == USART_LastBit_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028)
+#define USART_IT_TXE ((uint16_t)0x0727)
+#define USART_IT_TC ((uint16_t)0x0626)
+#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_IDLE ((uint16_t)0x0424)
+#define USART_IT_LBD ((uint16_t)0x0846)
+#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
+#define USART_IT_CTS ((uint16_t)0x096A)
+#define USART_IT_ERR ((uint16_t)0x0060)
+#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
+#define USART_IT_NE ((uint16_t)0x0260)
+#define USART_IT_FE ((uint16_t)0x0160)
+
+/** @defgroup USART_Legacy
+ * @{
+ */
+#define USART_IT_ORE USART_IT_ORE_ER
+/**
+ * @}
+ */
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \
+ ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \
+ ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAReq_Tx ((uint16_t)0x0080)
+#define USART_DMAReq_Rx ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+ ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+ * @}
+ */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+ ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+ ((MODE) == USART_IrDAMode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTS ((uint16_t)0x0200)
+#define USART_FLAG_LBD ((uint16_t)0x0100)
+#define USART_FLAG_TXE ((uint16_t)0x0080)
+#define USART_FLAG_TC ((uint16_t)0x0040)
+#define USART_FLAG_RXNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLE ((uint16_t)0x0010)
+#define USART_FLAG_ORE ((uint16_t)0x0008)
+#define USART_FLAG_NE ((uint16_t)0x0004)
+#define USART_FLAG_FE ((uint16_t)0x0002)
+#define USART_FLAG_PE ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the USART configuration to the default reset state ***/
+void USART_DeInit(USART_TypeDef* USARTx);
+
+/* Initialization and Configuration functions *********************************/
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendBreak(USART_TypeDef* USARTx);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_USART_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_wwdg.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,110 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx_wwdg.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 31-January-2014
+ * @brief This file contains all the functions prototypes for the WWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_WWDG_H
+#define __STM32L1xx_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+ ((PRESCALER) == WWDG_Prescaler_2) || \
+ ((PRESCALER) == WWDG_Prescaler_4) || \
+ ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the WWDG configuration to the default reset state ****/
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation functions **************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_L152RE/system_stm32l1xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,104 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l1xx.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 22-February-2013
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32L1XX_H
+#define __SYSTEM_STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L1xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32L1xx_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L1XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/LPC17xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1035 @@
+/**************************************************************************//**
+ * @file LPC17xx.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * NXP LPC17xx Device Series
+ * @version: V1.09
+ * @date: 17. March 2010
+
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ SPI_IRQn = 13, /*!< SPI Interrupt */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /* USB Activity interrupt */
+ CANActivity_IRQn = 34, /* CAN Activity interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system_LPC17xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON;
+ __IO uint32_t PLL1CFG;
+ __I uint32_t PLL1STAT;
+ __O uint32_t PLL1FEED;
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ __IO uint32_t CANSLEEPCLR;
+ __IO uint32_t CANWAKEFLAGS;
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ uint32_t RESERVED5;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ __IO uint32_t DMAREQSEL;
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+ __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ union {
+ __IO uint32_t FIODIR;
+ struct {
+ __IO uint16_t FIODIRL;
+ __IO uint16_t FIODIRH;
+ };
+ struct {
+ __IO uint8_t FIODIR0;
+ __IO uint8_t FIODIR1;
+ __IO uint8_t FIODIR2;
+ __IO uint8_t FIODIR3;
+ };
+ };
+ uint32_t RESERVED0[3];
+ union {
+ __IO uint32_t FIOMASK;
+ struct {
+ __IO uint16_t FIOMASKL;
+ __IO uint16_t FIOMASKH;
+ };
+ struct {
+ __IO uint8_t FIOMASK0;
+ __IO uint8_t FIOMASK1;
+ __IO uint8_t FIOMASK2;
+ __IO uint8_t FIOMASK3;
+ };
+ };
+ union {
+ __IO uint32_t FIOPIN;
+ struct {
+ __IO uint16_t FIOPINL;
+ __IO uint16_t FIOPINH;
+ };
+ struct {
+ __IO uint8_t FIOPIN0;
+ __IO uint8_t FIOPIN1;
+ __IO uint8_t FIOPIN2;
+ __IO uint8_t FIOPIN3;
+ };
+ };
+ union {
+ __IO uint32_t FIOSET;
+ struct {
+ __IO uint16_t FIOSETL;
+ __IO uint16_t FIOSETH;
+ };
+ struct {
+ __IO uint8_t FIOSET0;
+ __IO uint8_t FIOSET1;
+ __IO uint8_t FIOSET2;
+ __IO uint8_t FIOSET3;
+ };
+ };
+ union {
+ __O uint32_t FIOCLR;
+ struct {
+ __O uint16_t FIOCLRL;
+ __O uint16_t FIOCLRH;
+ };
+ struct {
+ __O uint8_t FIOCLR0;
+ __O uint8_t FIOCLR1;
+ __O uint8_t FIOCLR2;
+ __O uint8_t FIOCLR3;
+ };
+ };
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART0_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __IO uint32_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __IO uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t RICOMPVAL;
+ __IO uint32_t RIMASK;
+ __IO uint8_t RICTRL;
+ uint8_t RESERVED0[3];
+ __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t MCCON;
+ __O uint32_t MCCON_SET;
+ __O uint32_t MCCON_CLR;
+ __I uint32_t MCCAPCON;
+ __O uint32_t MCCAPCON_SET;
+ __O uint32_t MCCAPCON_CLR;
+ __IO uint32_t MCTIM0;
+ __IO uint32_t MCTIM1;
+ __IO uint32_t MCTIM2;
+ __IO uint32_t MCPER0;
+ __IO uint32_t MCPER1;
+ __IO uint32_t MCPER2;
+ __IO uint32_t MCPW0;
+ __IO uint32_t MCPW1;
+ __IO uint32_t MCPW2;
+ __IO uint32_t MCDEADTIME;
+ __IO uint32_t MCCCP;
+ __IO uint32_t MCCR0;
+ __IO uint32_t MCCR1;
+ __IO uint32_t MCCR2;
+ __I uint32_t MCINTEN;
+ __O uint32_t MCINTEN_SET;
+ __O uint32_t MCINTEN_CLR;
+ __I uint32_t MCCNTCON;
+ __O uint32_t MCCNTCON_SET;
+ __O uint32_t MCCNTCON_CLR;
+ __I uint32_t MCINTFLAG;
+ __O uint32_t MCINTFLAG_SET;
+ __O uint32_t MCINTFLAG_CLR;
+ __O uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t QEICON;
+ __I uint32_t QEISTAT;
+ __IO uint32_t QEICONF;
+ __I uint32_t QEIPOS;
+ __IO uint32_t QEIMAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP;
+ __IO uint32_t QEILOAD;
+ __I uint32_t QEITIME;
+ __I uint32_t QEIVEL;
+ __I uint32_t QEICAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTER;
+ uint32_t RESERVED0[998];
+ __O uint32_t QEIIEC;
+ __O uint32_t QEIIES;
+ __I uint32_t QEIINTSTAT;
+ __I uint32_t QEIIE;
+ __O uint32_t QEICLR;
+ __O uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+ __IO uint32_t FCANIE;
+ __IO uint32_t FCANIC0;
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_GPIO_BASE (0x2009C000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
+#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+
+#endif // __LPC17xx_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/PeripheralNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_UART2_BASE,
+ UART_3 = (int)LPC_UART3_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE,
+ I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = 1,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+// Default peripherals
+#define MBED_SPI0 p5, p6, p7, p8
+#define MBED_SPI1 p11, p12, p13, p14
+
+#define MBED_UART0 p9, p10
+#define MBED_UART1 p13, p14
+#define MBED_UART2 p28, p27
+#define MBED_UARTUSB USBTX, USBRX
+
+#define MBED_I2C0 p28, p27
+#define MBED_I2C1 p9, p10
+
+#define MBED_CAN0 p30, p29
+
+#define MBED_ANALOGOUT0 p18
+
+#define MBED_ANALOGIN0 p15
+#define MBED_ANALOGIN1 p16
+#define MBED_ANALOGIN2 p17
+#define MBED_ANALOGIN3 p18
+#define MBED_ANALOGIN4 p19
+#define MBED_ANALOGIN5 p20
+
+#define MBED_PWMOUT0 p26
+#define MBED_PWMOUT1 p25
+#define MBED_PWMOUT2 p24
+#define MBED_PWMOUT3 p23
+#define MBED_PWMOUT4 p22
+#define MBED_PWMOUT5 p21
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/PinNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,188 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC Pin Names
+ P0_0 = LPC_GPIO0_BASE,
+ P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+ P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+ P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+ P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+ P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+
+ // Arduino Pin Names
+
+ // PIN header connector
+ // for standard-based form factor with expansion board
+ // -----------------------------------------------------------
+ // PMW = Pulswidth Modulator
+ // EINT = External Interrupt
+ // AOUT = Analog Output
+
+ // Analog Ports (A0-A5)
+ A0 = P0_23, // I2S_CLK
+ A1 = P0_24, // I2S_WS
+ A2 = P0_25, // I2S_SDA
+ A3 = P0_26, // AOUT
+ A4 = P1_30, //
+ A5 = P1_31, //
+ // Digital Port (D0-D7)
+ D0 = P4_29, // TXD
+ D1 = P4_28, // RXD
+ D2 = P2_13, // EINT
+ D3 = P2_0, // PWM
+ D4 = P2_12, // EINT
+ D5 = P2_1, // PWM
+ D6 = P2_2, // PWM
+ D7 = P2_11, // EINT
+ // Digital Port (D8-D13)
+ D8 = P2_4, // PWM
+ D9 = P2_3, // PWM
+ D10 = P1_21, // PWM SSEL
+ D11 = P1_24, // PWM MOSI
+ D12 = P1_23, // PWM MISO
+ D13 = P1_20, // PWM SCK
+ // GND
+ // AREF
+ SDA = P0_0,
+ D14 = SDA,
+ SCL = P0_1,
+ D15 = SCL,
+
+ // I2C (shared with LISA/SARA)
+ GPSSDA = P0_27,
+ GPSSCL = P0_28,
+ // UART
+ GPSTXD = P0_10,
+ GPSRXD = P0_11,
+ // Control
+ GPSRST = P1_18, // Reset (input to GPS, active low)
+ GPSPPS = P1_19, // 1PPS Timepulse (output from GPS)
+ GPSINT = P1_22, // Interrupt (input to GPS)
+ GPSEN = P1_29, // Supply Control (high = enabled)
+
+ // u-blox LISA/SARA cellular modem
+ // http://www.u-blox.com/wireless-modules.html
+ // -----------------------------------------------------------
+ // UART (LPC1768 = DTE, LISA/SARA = DCE)
+ MDMTXD = P0_15, // Transmit Data
+ MDMRXD = P0_16, // Receive Data
+ MDMCTS = P0_17, // Clear to Send
+ MDMDCD = P0_18, // Data Carrier Detect
+ MDMDSR = P0_19, // Data Set Ready
+ MDMDTR = P0_20, // Data Terminal Ready (set high or use handshake)
+ MDMRI = P0_21, // Ring Indicator
+ MDMRTS = P0_22, // Request to Send (set high or use handshake)
+
+ // USB (not available on C27-G35)
+ MDMUSBDP = P0_29, // USB D+
+ MDMUSBDN = P0_30, // USB D-
+ MDMUSBCON = P2_9, // USB Connect
+ MDMUSBDET = P0_7, // USB Detect (n/a on REV.A board)
+ // Control
+ MDMEN = P2_5, // Supply Control (high = enabled)
+ MDMPWRON = P2_6, //
+ MDMGPIO1 = P2_7, // GPIO1, Network status
+ MDMRST = P2_8, // Reset (active low, set as open drain!)
+ MDMLVLOE = P0_9, // Serial/GPIO Level Shifter Output Enable (n/a on REV.A board)
+ MDMILVLOE = P0_8, // I2C Level Shifter Output Enable (n/a on REV.A board)
+
+ // CAN (TJA1040)
+ // -----------------------------------------------------------
+ CANRD = P0_4,
+ CANTD = P0_5,
+ CANS = P0_6, // standby (low=normal, high=standby/rxonly)
+
+ // Ethernet (DP83848)
+ // -----------------------------------------------------------
+ ETHTXD0 = P1_0,
+ ETHTXD1 = P1_1,
+ ETHTXEN = P1_4,
+ ETHCRS = P1_8,
+ ETHRXD0 = P1_9,
+ ETHRXD1 = P1_10,
+ ETHRXEN = P1_14,
+ ETHREFCLK = P1_15,
+ ETHMDC = P1_16,
+ ETHMDIO = P1_17,
+ ETHOSCEN = P1_27,
+ ETHRST = P1_28,
+ ETHLINK = P1_25, // LED_LINK
+ ETHSPEED = P1_26, // LED_SPEED
+
+ // ISP port
+ // -----------------------------------------------------------
+ ISP = P2_10,
+
+ // Other mbed Pin Names
+ LED = P3_25,
+ LED1 = LED,
+ LED_RED = LED,
+
+ // mbed / debug IF (LPC11)
+ // -----------------------------------------------------------
+ // Serial Port
+ USBTX = P0_2,
+ USBRX = P0_3,
+ USBTXD = USBTX, // identical USBTX
+ USBRXD = USBRX, // identical USBRX
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullUp = 0,
+ PullDown = 3,
+ PullNone = 2,
+ OpenDrain = 4
+} PinMode;
+
+// version of PINCON_TypeDef using register arrays
+typedef struct {
+ __IO uint32_t PINSEL[11];
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE[10];
+ __IO uint32_t PINMODE_OD[5];
+} PINCONARRAY_TypeDef;
+
+#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
+
+//Additional C027 stuff
+#define GPSADR (66<<1) // GPS I2C Address
+#define GPSBAUD 9600 // Default GPS Baud Rate
+#define MDMBAUD 115200 // Default Modem Baud Rate
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/PortNames.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3,
+ Port4 = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/TOOLCHAIN_ARM_STD/LPC1768.sct Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,22 @@
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
+ ; 32KB - 0xC8 = 0x7F38
+ RW_IRAM1 0x100000C8 0x7F38 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
+ .ANY (CANRAM)
+ }
+}
Binary file TARGET_UBLOX_C027/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_ARM_STD/startup_LPC17xx.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_ARM_STD/system_LPC17xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/TOOLCHAIN_GCC_ARM/LPC1768.ld Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,172 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)
+
+ USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+ ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ Image$$RW_IRAM1$$Base = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$RW_IRAM1$$ZI$$Limit = . ;
+ } > RAM
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Code can explicitly ask for data to be
+ placed in these higher RAM banks where
+ they will be left uninitialized.
+ */
+ .AHBSRAM0 (NOLOAD):
+ {
+ Image$$RW_IRAM2$$Base = . ;
+ *(AHBSRAM0)
+ Image$$RW_IRAM2$$ZI$$Limit = .;
+ } > USB_RAM
+
+ .AHBSRAM1 (NOLOAD):
+ {
+ Image$$RW_IRAM3$$Base = . ;
+ *(AHBSRAM1)
+ Image$$RW_IRAM3$$ZI$$Limit = .;
+ } > ETH_RAM
+}
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_ARM/cmsis_nvic.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_ARM/libmbed.a has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_ARM/retarget.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_ARM/startup_LPC17xx.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_ARM/system_LPC17xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/TOOLCHAIN_GCC_CR/LPC1768.ld Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,154 @@
+/* mbed - LPC1768 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc32 = 0x10000000 + 0x8000;
+ __top_RamAHB32 = 0x2007c000 + 0x8000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc32
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc32 AT>MFlash512
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CR/cmsis_nvic.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CR/libmbed.a has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CR/retarget.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CR/startup_LPC17xx.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CR/system_LPC17xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/TOOLCHAIN_GCC_CS/LPC1768.ld Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,212 @@
+/* Linker script for mbed LPC1768
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(__cs3_reset_cortex_m)
+SEARCH_DIR(.)
+
+/*
+ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
+ram LENGTH: 32KB - 0xC8 = 0x7F38
+*/
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+
+ ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
+
+ ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+ ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ }
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ /* This used for USB RAM section */
+ .usb_ram (NOLOAD):
+ {
+ *.o (USB_RAM)
+ } > ram2
+ .heap (NOLOAD) :
+ {
+ *(.heap)
+ } >ram
+ .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
+ {
+ *(.stack)
+ _estack = .;
+ PROVIDE(estack = .);
+ } >ram
+
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CS/cmsis_nvic.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CS/libmbed.a has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CS/retarget.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CS/startup_LPC17xx.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CS/sys.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_GCC_CS/system_LPC17xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/TOOLCHAIN_IAR/LPC17xx.icf Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,40 @@
+/* [ROM] */
+define symbol __intvec_start__ = 0x00000000;
+define symbol __region_ROM_start__ = 0x00000000;
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+define symbol __region_ROM_end__ = 0x0007FFFF;
+
+/* [RAM] Vector table dynamic copy: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8*/
+define symbol __NVIC_start__ = 0x10000000;
+define symbol __NVIC_end__ = 0x100000C7;
+define symbol __region_RAM_start__ = 0x100000C8;
+define symbol __region_RAM_end__ = 0x1000FFDF;
+define symbol _AHB_RAM_start__ = 0x2007C000;
+define symbol _AHB_RAM_end__ = 0x20083FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__ = 0x800;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { section .intvec };
+place at address mem:0x2FC { section CRPKEY };
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
+place in AHB_RAM_region { section USB_RAM };
+place in CRP_region { section .crp };
Binary file TARGET_UBLOX_C027/TOOLCHAIN_IAR/cmsis_nvic.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_IAR/mbed.a has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_IAR/retarget.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_IAR/startup_LPC17xx.o has changed
Binary file TARGET_UBLOX_C027/TOOLCHAIN_IAR/system_LPC17xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_UBLOX_C027/cmsis.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC17xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/cmsis_nvic.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 33)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/core_cm0.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/core_cm0plus.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/core_cm3.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/core_cm4.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/core_cm4_simd.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/core_cmFunc.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/core_cmInstr.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_UBLOX_C027/device.h Fri Feb 14 14:36:43 2014 +0000 @@ -0,0 +1,62 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 1 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 0 +#define DEVICE_MAC_OFFSET 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 1 + +#define DEVICE_STDIO_MESSAGES 1 + +// should only enable one or the other, not both +#define DEVICE_ERROR_PATTERN 0 +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/gpio_object.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/objects.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ __IO uint32_t *MR;
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_UART_TypeDef *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct can_s {
+ LPC_CAN_TypeDef *dev;
+ int index;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+ LPC_SSP_TypeDef *spi;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/reserved_pins.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,8 @@
+// List of reserved pins for C027 LPC1768
+
+#ifndef RESERVED_PINS_H
+#define RESERVED_PINS_H
+
+#define TARGET_RESERVED_PINS {P3_26}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UBLOX_C027/system_LPC17xx.h Fri Feb 14 14:36:43 2014 +0000
@@ -0,0 +1,60 @@
+/******************************************************************************
+ * @file: system_LPC17xx.h
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC17xx Device Series
+ * @version: V1.02
+ * @date: 27. July 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC17xx_H */
