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TARGET_NUCLEO_F030R8/stm32f0xx_adc.h@77:869cf507173a, 2014-02-14 (annotated)
- Committer:
- emilmont
- Date:
- Fri Feb 14 14:36:43 2014 +0000
- Revision:
- 77:869cf507173a
- Child:
- 81:7d30d6019079
Release 77 of the mbed library
Main changes:
* Add target NUCLEO_F030R8
* Add target NUCLEO_F401RE
* Add target NUCLEO_F103RB
* Add target NUCLEO_L152RE
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f0xx_adc.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V1.3.0 |
| emilmont | 77:869cf507173a | 6 | * @date 16-January-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief This file contains all the functions prototypes for the ADC firmware |
| emilmont | 77:869cf507173a | 8 | * library |
| emilmont | 77:869cf507173a | 9 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 10 | * @attention |
| emilmont | 77:869cf507173a | 11 | * |
| emilmont | 77:869cf507173a | 12 | * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 13 | * |
| emilmont | 77:869cf507173a | 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
| emilmont | 77:869cf507173a | 15 | * You may not use this file except in compliance with the License. |
| emilmont | 77:869cf507173a | 16 | * You may obtain a copy of the License at: |
| emilmont | 77:869cf507173a | 17 | * |
| emilmont | 77:869cf507173a | 18 | * http://www.st.com/software_license_agreement_liberty_v2 |
| emilmont | 77:869cf507173a | 19 | * |
| emilmont | 77:869cf507173a | 20 | * Unless required by applicable law or agreed to in writing, software |
| emilmont | 77:869cf507173a | 21 | * distributed under the License is distributed on an "AS IS" BASIS, |
| emilmont | 77:869cf507173a | 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| emilmont | 77:869cf507173a | 23 | * See the License for the specific language governing permissions and |
| emilmont | 77:869cf507173a | 24 | * limitations under the License. |
| emilmont | 77:869cf507173a | 25 | * |
| emilmont | 77:869cf507173a | 26 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 27 | */ |
| emilmont | 77:869cf507173a | 28 | |
| emilmont | 77:869cf507173a | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 30 | #ifndef __STM32F0XX_ADC_H |
| emilmont | 77:869cf507173a | 31 | #define __STM32F0XX_ADC_H |
| emilmont | 77:869cf507173a | 32 | |
| emilmont | 77:869cf507173a | 33 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 34 | extern "C" { |
| emilmont | 77:869cf507173a | 35 | #endif |
| emilmont | 77:869cf507173a | 36 | |
| emilmont | 77:869cf507173a | 37 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 38 | #include "stm32f0xx.h" |
| emilmont | 77:869cf507173a | 39 | |
| emilmont | 77:869cf507173a | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver |
| emilmont | 77:869cf507173a | 41 | * @{ |
| emilmont | 77:869cf507173a | 42 | */ |
| emilmont | 77:869cf507173a | 43 | |
| emilmont | 77:869cf507173a | 44 | /** @addtogroup ADC |
| emilmont | 77:869cf507173a | 45 | * @{ |
| emilmont | 77:869cf507173a | 46 | */ |
| emilmont | 77:869cf507173a | 47 | |
| emilmont | 77:869cf507173a | 48 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 49 | |
| emilmont | 77:869cf507173a | 50 | /** |
| emilmont | 77:869cf507173a | 51 | * @brief ADC Init structure definition |
| emilmont | 77:869cf507173a | 52 | */ |
| emilmont | 77:869cf507173a | 53 | |
| emilmont | 77:869cf507173a | 54 | typedef struct |
| emilmont | 77:869cf507173a | 55 | { |
| emilmont | 77:869cf507173a | 56 | uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. |
| emilmont | 77:869cf507173a | 57 | This parameter can be a value of @ref ADC_Resolution */ |
| emilmont | 77:869cf507173a | 58 | |
| emilmont | 77:869cf507173a | 59 | FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in |
| emilmont | 77:869cf507173a | 60 | Continuous or Single mode. |
| emilmont | 77:869cf507173a | 61 | This parameter can be set to ENABLE or DISABLE. */ |
| emilmont | 77:869cf507173a | 62 | |
| emilmont | 77:869cf507173a | 63 | uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the |
| emilmont | 77:869cf507173a | 64 | trigger of a regular group. This parameter can be a value |
| emilmont | 77:869cf507173a | 65 | of @ref ADC_external_trigger_edge_conversion */ |
| emilmont | 77:869cf507173a | 66 | |
| emilmont | 77:869cf507173a | 67 | uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog |
| emilmont | 77:869cf507173a | 68 | to digital conversion of regular channels. This parameter |
| emilmont | 77:869cf507173a | 69 | can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */ |
| emilmont | 77:869cf507173a | 70 | |
| emilmont | 77:869cf507173a | 71 | uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. |
| emilmont | 77:869cf507173a | 72 | This parameter can be a value of @ref ADC_data_align */ |
| emilmont | 77:869cf507173a | 73 | |
| emilmont | 77:869cf507173a | 74 | uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned |
| emilmont | 77:869cf507173a | 75 | in the sequence. |
| emilmont | 77:869cf507173a | 76 | This parameter can be a value of @ref ADC_Scan_Direction */ |
| emilmont | 77:869cf507173a | 77 | }ADC_InitTypeDef; |
| emilmont | 77:869cf507173a | 78 | |
| emilmont | 77:869cf507173a | 79 | |
| emilmont | 77:869cf507173a | 80 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 81 | |
| emilmont | 77:869cf507173a | 82 | /** @defgroup ADC_Exported_Constants |
| emilmont | 77:869cf507173a | 83 | * @{ |
| emilmont | 77:869cf507173a | 84 | */ |
| emilmont | 77:869cf507173a | 85 | #define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) |
| emilmont | 77:869cf507173a | 86 | |
| emilmont | 77:869cf507173a | 87 | /** @defgroup ADC_JitterOff |
| emilmont | 77:869cf507173a | 88 | * @{ |
| emilmont | 77:869cf507173a | 89 | */ |
| emilmont | 77:869cf507173a | 90 | /* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */ |
| emilmont | 77:869cf507173a | 91 | #define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2 |
| emilmont | 77:869cf507173a | 92 | #define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4 |
| emilmont | 77:869cf507173a | 93 | |
| emilmont | 77:869cf507173a | 94 | #define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET) |
| emilmont | 77:869cf507173a | 95 | |
| emilmont | 77:869cf507173a | 96 | /** |
| emilmont | 77:869cf507173a | 97 | * @} |
| emilmont | 77:869cf507173a | 98 | */ |
| emilmont | 77:869cf507173a | 99 | |
| emilmont | 77:869cf507173a | 100 | /** @defgroup ADC_ClockMode |
| emilmont | 77:869cf507173a | 101 | * @{ |
| emilmont | 77:869cf507173a | 102 | */ |
| emilmont | 77:869cf507173a | 103 | #define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */ |
| emilmont | 77:869cf507173a | 104 | #define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */ |
| emilmont | 77:869cf507173a | 105 | #define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */ |
| emilmont | 77:869cf507173a | 106 | #define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\ |
| emilmont | 77:869cf507173a | 107 | ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\ |
| emilmont | 77:869cf507173a | 108 | ((CLOCK) == ADC_ClockMode_SynClkDiv4)) |
| emilmont | 77:869cf507173a | 109 | |
| emilmont | 77:869cf507173a | 110 | /** |
| emilmont | 77:869cf507173a | 111 | * @} |
| emilmont | 77:869cf507173a | 112 | */ |
| emilmont | 77:869cf507173a | 113 | |
| emilmont | 77:869cf507173a | 114 | /** @defgroup ADC_Resolution |
| emilmont | 77:869cf507173a | 115 | * @{ |
| emilmont | 77:869cf507173a | 116 | */ |
| emilmont | 77:869cf507173a | 117 | #define ADC_Resolution_12b ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 118 | #define ADC_Resolution_10b ADC_CFGR1_RES_0 |
| emilmont | 77:869cf507173a | 119 | #define ADC_Resolution_8b ADC_CFGR1_RES_1 |
| emilmont | 77:869cf507173a | 120 | #define ADC_Resolution_6b ADC_CFGR1_RES |
| emilmont | 77:869cf507173a | 121 | |
| emilmont | 77:869cf507173a | 122 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ |
| emilmont | 77:869cf507173a | 123 | ((RESOLUTION) == ADC_Resolution_10b) || \ |
| emilmont | 77:869cf507173a | 124 | ((RESOLUTION) == ADC_Resolution_8b) || \ |
| emilmont | 77:869cf507173a | 125 | ((RESOLUTION) == ADC_Resolution_6b)) |
| emilmont | 77:869cf507173a | 126 | |
| emilmont | 77:869cf507173a | 127 | /** |
| emilmont | 77:869cf507173a | 128 | * @} |
| emilmont | 77:869cf507173a | 129 | */ |
| emilmont | 77:869cf507173a | 130 | |
| emilmont | 77:869cf507173a | 131 | /** @defgroup ADC_external_trigger_edge_conversion |
| emilmont | 77:869cf507173a | 132 | * @{ |
| emilmont | 77:869cf507173a | 133 | */ |
| emilmont | 77:869cf507173a | 134 | #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 135 | #define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0 |
| emilmont | 77:869cf507173a | 136 | #define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1 |
| emilmont | 77:869cf507173a | 137 | #define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN |
| emilmont | 77:869cf507173a | 138 | |
| emilmont | 77:869cf507173a | 139 | #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ |
| emilmont | 77:869cf507173a | 140 | ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ |
| emilmont | 77:869cf507173a | 141 | ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ |
| emilmont | 77:869cf507173a | 142 | ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) |
| emilmont | 77:869cf507173a | 143 | /** |
| emilmont | 77:869cf507173a | 144 | * @} |
| emilmont | 77:869cf507173a | 145 | */ |
| emilmont | 77:869cf507173a | 146 | |
| emilmont | 77:869cf507173a | 147 | /** @defgroup ADC_external_trigger_sources_for_channels_conversion |
| emilmont | 77:869cf507173a | 148 | * @{ |
| emilmont | 77:869cf507173a | 149 | */ |
| emilmont | 77:869cf507173a | 150 | |
| emilmont | 77:869cf507173a | 151 | /* TIM1 */ |
| emilmont | 77:869cf507173a | 152 | #define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 153 | #define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0 |
| emilmont | 77:869cf507173a | 154 | |
| emilmont | 77:869cf507173a | 155 | /* TIM2 */ |
| emilmont | 77:869cf507173a | 156 | #define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1 |
| emilmont | 77:869cf507173a | 157 | |
| emilmont | 77:869cf507173a | 158 | /* TIM3 */ |
| emilmont | 77:869cf507173a | 159 | #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)) |
| emilmont | 77:869cf507173a | 160 | |
| emilmont | 77:869cf507173a | 161 | /* TIM15 */ |
| emilmont | 77:869cf507173a | 162 | #define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2 |
| emilmont | 77:869cf507173a | 163 | |
| emilmont | 77:869cf507173a | 164 | #define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \ |
| emilmont | 77:869cf507173a | 165 | ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \ |
| emilmont | 77:869cf507173a | 166 | ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \ |
| emilmont | 77:869cf507173a | 167 | ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \ |
| emilmont | 77:869cf507173a | 168 | ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) |
| emilmont | 77:869cf507173a | 169 | /** |
| emilmont | 77:869cf507173a | 170 | * @} |
| emilmont | 77:869cf507173a | 171 | */ |
| emilmont | 77:869cf507173a | 172 | |
| emilmont | 77:869cf507173a | 173 | /** @defgroup ADC_data_align |
| emilmont | 77:869cf507173a | 174 | * @{ |
| emilmont | 77:869cf507173a | 175 | */ |
| emilmont | 77:869cf507173a | 176 | |
| emilmont | 77:869cf507173a | 177 | #define ADC_DataAlign_Right ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 178 | #define ADC_DataAlign_Left ADC_CFGR1_ALIGN |
| emilmont | 77:869cf507173a | 179 | |
| emilmont | 77:869cf507173a | 180 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ |
| emilmont | 77:869cf507173a | 181 | ((ALIGN) == ADC_DataAlign_Left)) |
| emilmont | 77:869cf507173a | 182 | /** |
| emilmont | 77:869cf507173a | 183 | * @} |
| emilmont | 77:869cf507173a | 184 | */ |
| emilmont | 77:869cf507173a | 185 | |
| emilmont | 77:869cf507173a | 186 | /** @defgroup ADC_Scan_Direction |
| emilmont | 77:869cf507173a | 187 | * @{ |
| emilmont | 77:869cf507173a | 188 | */ |
| emilmont | 77:869cf507173a | 189 | |
| emilmont | 77:869cf507173a | 190 | #define ADC_ScanDirection_Upward ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 191 | #define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR |
| emilmont | 77:869cf507173a | 192 | |
| emilmont | 77:869cf507173a | 193 | #define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \ |
| emilmont | 77:869cf507173a | 194 | ((DIRECTION) == ADC_ScanDirection_Backward)) |
| emilmont | 77:869cf507173a | 195 | /** |
| emilmont | 77:869cf507173a | 196 | * @} |
| emilmont | 77:869cf507173a | 197 | */ |
| emilmont | 77:869cf507173a | 198 | |
| emilmont | 77:869cf507173a | 199 | /** @defgroup ADC_DMA_Mode |
| emilmont | 77:869cf507173a | 200 | * @{ |
| emilmont | 77:869cf507173a | 201 | */ |
| emilmont | 77:869cf507173a | 202 | |
| emilmont | 77:869cf507173a | 203 | #define ADC_DMAMode_OneShot ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 204 | #define ADC_DMAMode_Circular ADC_CFGR1_DMACFG |
| emilmont | 77:869cf507173a | 205 | |
| emilmont | 77:869cf507173a | 206 | #define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \ |
| emilmont | 77:869cf507173a | 207 | ((MODE) == ADC_DMAMode_Circular)) |
| emilmont | 77:869cf507173a | 208 | /** |
| emilmont | 77:869cf507173a | 209 | * @} |
| emilmont | 77:869cf507173a | 210 | */ |
| emilmont | 77:869cf507173a | 211 | |
| emilmont | 77:869cf507173a | 212 | /** @defgroup ADC_analog_watchdog_selection |
| emilmont | 77:869cf507173a | 213 | * @{ |
| emilmont | 77:869cf507173a | 214 | */ |
| emilmont | 77:869cf507173a | 215 | |
| emilmont | 77:869cf507173a | 216 | #define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 217 | #define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000) |
| emilmont | 77:869cf507173a | 218 | #define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000) |
| emilmont | 77:869cf507173a | 219 | #define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000) |
| emilmont | 77:869cf507173a | 220 | #define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000) |
| emilmont | 77:869cf507173a | 221 | #define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000) |
| emilmont | 77:869cf507173a | 222 | #define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000) |
| emilmont | 77:869cf507173a | 223 | #define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000) |
| emilmont | 77:869cf507173a | 224 | #define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000) |
| emilmont | 77:869cf507173a | 225 | #define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000) |
| emilmont | 77:869cf507173a | 226 | #define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 227 | #define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 228 | #define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 229 | #define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 230 | #define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 231 | #define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 232 | #define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000) |
| emilmont | 77:869cf507173a | 233 | #define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000) |
| emilmont | 77:869cf507173a | 234 | #define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000) |
| emilmont | 77:869cf507173a | 235 | |
| emilmont | 77:869cf507173a | 236 | |
| emilmont | 77:869cf507173a | 237 | #define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ |
| emilmont | 77:869cf507173a | 238 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \ |
| emilmont | 77:869cf507173a | 239 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \ |
| emilmont | 77:869cf507173a | 240 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \ |
| emilmont | 77:869cf507173a | 241 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \ |
| emilmont | 77:869cf507173a | 242 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \ |
| emilmont | 77:869cf507173a | 243 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \ |
| emilmont | 77:869cf507173a | 244 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \ |
| emilmont | 77:869cf507173a | 245 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \ |
| emilmont | 77:869cf507173a | 246 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \ |
| emilmont | 77:869cf507173a | 247 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \ |
| emilmont | 77:869cf507173a | 248 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \ |
| emilmont | 77:869cf507173a | 249 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \ |
| emilmont | 77:869cf507173a | 250 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \ |
| emilmont | 77:869cf507173a | 251 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \ |
| emilmont | 77:869cf507173a | 252 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \ |
| emilmont | 77:869cf507173a | 253 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \ |
| emilmont | 77:869cf507173a | 254 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \ |
| emilmont | 77:869cf507173a | 255 | ((CHANNEL) == ADC_AnalogWatchdog_Channel_18)) |
| emilmont | 77:869cf507173a | 256 | /** |
| emilmont | 77:869cf507173a | 257 | * @} |
| emilmont | 77:869cf507173a | 258 | */ |
| emilmont | 77:869cf507173a | 259 | |
| emilmont | 77:869cf507173a | 260 | /** @defgroup ADC_sampling_times |
| emilmont | 77:869cf507173a | 261 | * @{ |
| emilmont | 77:869cf507173a | 262 | */ |
| emilmont | 77:869cf507173a | 263 | |
| emilmont | 77:869cf507173a | 264 | #define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 265 | #define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) |
| emilmont | 77:869cf507173a | 266 | #define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) |
| emilmont | 77:869cf507173a | 267 | #define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) |
| emilmont | 77:869cf507173a | 268 | #define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) |
| emilmont | 77:869cf507173a | 269 | #define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) |
| emilmont | 77:869cf507173a | 270 | #define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) |
| emilmont | 77:869cf507173a | 271 | #define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) |
| emilmont | 77:869cf507173a | 272 | |
| emilmont | 77:869cf507173a | 273 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \ |
| emilmont | 77:869cf507173a | 274 | ((TIME) == ADC_SampleTime_7_5Cycles) || \ |
| emilmont | 77:869cf507173a | 275 | ((TIME) == ADC_SampleTime_13_5Cycles) || \ |
| emilmont | 77:869cf507173a | 276 | ((TIME) == ADC_SampleTime_28_5Cycles) || \ |
| emilmont | 77:869cf507173a | 277 | ((TIME) == ADC_SampleTime_41_5Cycles) || \ |
| emilmont | 77:869cf507173a | 278 | ((TIME) == ADC_SampleTime_55_5Cycles) || \ |
| emilmont | 77:869cf507173a | 279 | ((TIME) == ADC_SampleTime_71_5Cycles) || \ |
| emilmont | 77:869cf507173a | 280 | ((TIME) == ADC_SampleTime_239_5Cycles)) |
| emilmont | 77:869cf507173a | 281 | /** |
| emilmont | 77:869cf507173a | 282 | * @} |
| emilmont | 77:869cf507173a | 283 | */ |
| emilmont | 77:869cf507173a | 284 | |
| emilmont | 77:869cf507173a | 285 | /** @defgroup ADC_thresholds |
| emilmont | 77:869cf507173a | 286 | * @{ |
| emilmont | 77:869cf507173a | 287 | */ |
| emilmont | 77:869cf507173a | 288 | |
| emilmont | 77:869cf507173a | 289 | #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) |
| emilmont | 77:869cf507173a | 290 | |
| emilmont | 77:869cf507173a | 291 | /** |
| emilmont | 77:869cf507173a | 292 | * @} |
| emilmont | 77:869cf507173a | 293 | */ |
| emilmont | 77:869cf507173a | 294 | |
| emilmont | 77:869cf507173a | 295 | /** @defgroup ADC_channels |
| emilmont | 77:869cf507173a | 296 | * @{ |
| emilmont | 77:869cf507173a | 297 | */ |
| emilmont | 77:869cf507173a | 298 | |
| emilmont | 77:869cf507173a | 299 | #define ADC_Channel_0 ADC_CHSELR_CHSEL0 |
| emilmont | 77:869cf507173a | 300 | #define ADC_Channel_1 ADC_CHSELR_CHSEL1 |
| emilmont | 77:869cf507173a | 301 | #define ADC_Channel_2 ADC_CHSELR_CHSEL2 |
| emilmont | 77:869cf507173a | 302 | #define ADC_Channel_3 ADC_CHSELR_CHSEL3 |
| emilmont | 77:869cf507173a | 303 | #define ADC_Channel_4 ADC_CHSELR_CHSEL4 |
| emilmont | 77:869cf507173a | 304 | #define ADC_Channel_5 ADC_CHSELR_CHSEL5 |
| emilmont | 77:869cf507173a | 305 | #define ADC_Channel_6 ADC_CHSELR_CHSEL6 |
| emilmont | 77:869cf507173a | 306 | #define ADC_Channel_7 ADC_CHSELR_CHSEL7 |
| emilmont | 77:869cf507173a | 307 | #define ADC_Channel_8 ADC_CHSELR_CHSEL8 |
| emilmont | 77:869cf507173a | 308 | #define ADC_Channel_9 ADC_CHSELR_CHSEL9 |
| emilmont | 77:869cf507173a | 309 | #define ADC_Channel_10 ADC_CHSELR_CHSEL10 /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 310 | #define ADC_Channel_11 ADC_CHSELR_CHSEL11 /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 311 | #define ADC_Channel_12 ADC_CHSELR_CHSEL12 /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 312 | #define ADC_Channel_13 ADC_CHSELR_CHSEL13 /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 313 | #define ADC_Channel_14 ADC_CHSELR_CHSEL14 /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 314 | #define ADC_Channel_15 ADC_CHSELR_CHSEL15 /*!< Not available for STM32F031 devices */ |
| emilmont | 77:869cf507173a | 315 | #define ADC_Channel_16 ADC_CHSELR_CHSEL16 |
| emilmont | 77:869cf507173a | 316 | #define ADC_Channel_17 ADC_CHSELR_CHSEL17 |
| emilmont | 77:869cf507173a | 317 | #define ADC_Channel_18 ADC_CHSELR_CHSEL18 /*!< Not available for STM32F030 devices */ |
| emilmont | 77:869cf507173a | 318 | |
| emilmont | 77:869cf507173a | 319 | #define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16) |
| emilmont | 77:869cf507173a | 320 | #define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17) |
| emilmont | 77:869cf507173a | 321 | #define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18) /*!< Not available for STM32F030 devices */ |
| emilmont | 77:869cf507173a | 322 | |
| emilmont | 77:869cf507173a | 323 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET)) |
| emilmont | 77:869cf507173a | 324 | |
| emilmont | 77:869cf507173a | 325 | /** |
| emilmont | 77:869cf507173a | 326 | * @} |
| emilmont | 77:869cf507173a | 327 | */ |
| emilmont | 77:869cf507173a | 328 | |
| emilmont | 77:869cf507173a | 329 | /** @defgroup ADC_interrupts_definition |
| emilmont | 77:869cf507173a | 330 | * @{ |
| emilmont | 77:869cf507173a | 331 | */ |
| emilmont | 77:869cf507173a | 332 | |
| emilmont | 77:869cf507173a | 333 | #define ADC_IT_ADRDY ADC_IER_ADRDYIE |
| emilmont | 77:869cf507173a | 334 | #define ADC_IT_EOSMP ADC_IER_EOSMPIE |
| emilmont | 77:869cf507173a | 335 | #define ADC_IT_EOC ADC_IER_EOCIE |
| emilmont | 77:869cf507173a | 336 | #define ADC_IT_EOSEQ ADC_IER_EOSEQIE |
| emilmont | 77:869cf507173a | 337 | #define ADC_IT_OVR ADC_IER_OVRIE |
| emilmont | 77:869cf507173a | 338 | #define ADC_IT_AWD ADC_IER_AWDIE |
| emilmont | 77:869cf507173a | 339 | |
| emilmont | 77:869cf507173a | 340 | #define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) |
| emilmont | 77:869cf507173a | 341 | |
| emilmont | 77:869cf507173a | 342 | #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \ |
| emilmont | 77:869cf507173a | 343 | ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \ |
| emilmont | 77:869cf507173a | 344 | ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD)) |
| emilmont | 77:869cf507173a | 345 | |
| emilmont | 77:869cf507173a | 346 | #define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) |
| emilmont | 77:869cf507173a | 347 | |
| emilmont | 77:869cf507173a | 348 | /** |
| emilmont | 77:869cf507173a | 349 | * @} |
| emilmont | 77:869cf507173a | 350 | */ |
| emilmont | 77:869cf507173a | 351 | |
| emilmont | 77:869cf507173a | 352 | /** @defgroup ADC_flags_definition |
| emilmont | 77:869cf507173a | 353 | * @{ |
| emilmont | 77:869cf507173a | 354 | */ |
| emilmont | 77:869cf507173a | 355 | |
| emilmont | 77:869cf507173a | 356 | #define ADC_FLAG_ADRDY ADC_ISR_ADRDY |
| emilmont | 77:869cf507173a | 357 | #define ADC_FLAG_EOSMP ADC_ISR_EOSMP |
| emilmont | 77:869cf507173a | 358 | #define ADC_FLAG_EOC ADC_ISR_EOC |
| emilmont | 77:869cf507173a | 359 | #define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ |
| emilmont | 77:869cf507173a | 360 | #define ADC_FLAG_OVR ADC_ISR_OVR |
| emilmont | 77:869cf507173a | 361 | #define ADC_FLAG_AWD ADC_ISR_AWD |
| emilmont | 77:869cf507173a | 362 | |
| emilmont | 77:869cf507173a | 363 | #define ADC_FLAG_ADEN ((uint32_t)0x01000001) |
| emilmont | 77:869cf507173a | 364 | #define ADC_FLAG_ADDIS ((uint32_t)0x01000002) |
| emilmont | 77:869cf507173a | 365 | #define ADC_FLAG_ADSTART ((uint32_t)0x01000004) |
| emilmont | 77:869cf507173a | 366 | #define ADC_FLAG_ADSTP ((uint32_t)0x01000010) |
| emilmont | 77:869cf507173a | 367 | #define ADC_FLAG_ADCAL ((uint32_t)0x81000000) |
| emilmont | 77:869cf507173a | 368 | |
| emilmont | 77:869cf507173a | 369 | #define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET)) |
| emilmont | 77:869cf507173a | 370 | |
| emilmont | 77:869cf507173a | 371 | #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ |
| emilmont | 77:869cf507173a | 372 | ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \ |
| emilmont | 77:869cf507173a | 373 | ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \ |
| emilmont | 77:869cf507173a | 374 | ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \ |
| emilmont | 77:869cf507173a | 375 | ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \ |
| emilmont | 77:869cf507173a | 376 | ((FLAG) == ADC_FLAG_ADCAL)) |
| emilmont | 77:869cf507173a | 377 | /** |
| emilmont | 77:869cf507173a | 378 | * @} |
| emilmont | 77:869cf507173a | 379 | */ |
| emilmont | 77:869cf507173a | 380 | |
| emilmont | 77:869cf507173a | 381 | /** |
| emilmont | 77:869cf507173a | 382 | * @} |
| emilmont | 77:869cf507173a | 383 | */ |
| emilmont | 77:869cf507173a | 384 | |
| emilmont | 77:869cf507173a | 385 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 386 | /* Exported functions ------------------------------------------------------- */ |
| emilmont | 77:869cf507173a | 387 | |
| emilmont | 77:869cf507173a | 388 | /* Function used to set the ADC configuration to the default reset state *****/ |
| emilmont | 77:869cf507173a | 389 | void ADC_DeInit(ADC_TypeDef* ADCx); |
| emilmont | 77:869cf507173a | 390 | |
| emilmont | 77:869cf507173a | 391 | /* Initialization and Configuration functions *********************************/ |
| emilmont | 77:869cf507173a | 392 | void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); |
| emilmont | 77:869cf507173a | 393 | void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); |
| emilmont | 77:869cf507173a | 394 | void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode); |
| emilmont | 77:869cf507173a | 395 | void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 396 | /* This Function is obsolete and maintained for legacy purpose only. |
| emilmont | 77:869cf507173a | 397 | ADC_ClockModeConfig() function should be used instead */ |
| emilmont | 77:869cf507173a | 398 | void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 399 | |
| emilmont | 77:869cf507173a | 400 | /* Power saving functions *****************************************************/ |
| emilmont | 77:869cf507173a | 401 | void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 402 | void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 403 | |
| emilmont | 77:869cf507173a | 404 | /* Analog Watchdog configuration functions ************************************/ |
| emilmont | 77:869cf507173a | 405 | void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 406 | void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); |
| emilmont | 77:869cf507173a | 407 | void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel); |
| emilmont | 77:869cf507173a | 408 | void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 409 | |
| emilmont | 77:869cf507173a | 410 | /* Temperature Sensor , Vrefint and Vbat management function ******************/ |
| emilmont | 77:869cf507173a | 411 | void ADC_TempSensorCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 412 | void ADC_VrefintCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 413 | void ADC_VbatCmd(FunctionalState NewState); /*!< Not applicable for STM32F030 devices */ |
| emilmont | 77:869cf507173a | 414 | |
| emilmont | 77:869cf507173a | 415 | /* Channels Configuration functions *******************************************/ |
| emilmont | 77:869cf507173a | 416 | void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime); |
| emilmont | 77:869cf507173a | 417 | void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 418 | void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 419 | void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 420 | uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx); |
| emilmont | 77:869cf507173a | 421 | void ADC_StopOfConversion(ADC_TypeDef* ADCx); |
| emilmont | 77:869cf507173a | 422 | void ADC_StartOfConversion(ADC_TypeDef* ADCx); |
| emilmont | 77:869cf507173a | 423 | uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); |
| emilmont | 77:869cf507173a | 424 | |
| emilmont | 77:869cf507173a | 425 | /* Regular Channels DMA Configuration functions *******************************/ |
| emilmont | 77:869cf507173a | 426 | void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 427 | void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode); |
| emilmont | 77:869cf507173a | 428 | |
| emilmont | 77:869cf507173a | 429 | /* Interrupts and flags management functions **********************************/ |
| emilmont | 77:869cf507173a | 430 | void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 431 | FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); |
| emilmont | 77:869cf507173a | 432 | void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); |
| emilmont | 77:869cf507173a | 433 | ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); |
| emilmont | 77:869cf507173a | 434 | void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); |
| emilmont | 77:869cf507173a | 435 | |
| emilmont | 77:869cf507173a | 436 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 437 | } |
| emilmont | 77:869cf507173a | 438 | #endif |
| emilmont | 77:869cf507173a | 439 | |
| emilmont | 77:869cf507173a | 440 | #endif /*__STM32F0XX_ADC_H */ |
| emilmont | 77:869cf507173a | 441 | |
| emilmont | 77:869cf507173a | 442 | /** |
| emilmont | 77:869cf507173a | 443 | * @} |
| emilmont | 77:869cf507173a | 444 | */ |
| emilmont | 77:869cf507173a | 445 | |
| emilmont | 77:869cf507173a | 446 | /** |
| emilmont | 77:869cf507173a | 447 | * @} |
| emilmont | 77:869cf507173a | 448 | */ |
| emilmont | 77:869cf507173a | 449 | |
| emilmont | 77:869cf507173a | 450 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
