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TARGET_NUCLEO_L152RE/stm32l1xx_tim.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:: emilmont
Date:: Fri Feb 14 14:36:43 2014 +0000
Revision:: 77:869cf507173a
Child:: 81:7d30d6019079

Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32l1xx_tim.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.3.0
emilmont	77:869cf507173a	6	* @date 31-January-2014
emilmont	77:869cf507173a	7	* @brief This file contains all the functions prototypes for the TIM firmware
emilmont	77:869cf507173a	8	* library.
emilmont	77:869cf507173a	9	******************************************************************************
emilmont	77:869cf507173a	10	* @attention
emilmont	77:869cf507173a	11	*
emilmont	77:869cf507173a	12	* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	13	*
emilmont	77:869cf507173a	14	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
emilmont	77:869cf507173a	15	* You may not use this file except in compliance with the License.
emilmont	77:869cf507173a	16	* You may obtain a copy of the License at:
emilmont	77:869cf507173a	17	*
emilmont	77:869cf507173a	18	* http://www.st.com/software_license_agreement_liberty_v2
emilmont	77:869cf507173a	19	*
emilmont	77:869cf507173a	20	* Unless required by applicable law or agreed to in writing, software
emilmont	77:869cf507173a	21	* distributed under the License is distributed on an "AS IS" BASIS,
emilmont	77:869cf507173a	22	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont	77:869cf507173a	23	* See the License for the specific language governing permissions and
emilmont	77:869cf507173a	24	* limitations under the License.
emilmont	77:869cf507173a	25	*
emilmont	77:869cf507173a	26	******************************************************************************
emilmont	77:869cf507173a	27	*/
emilmont	77:869cf507173a	28
emilmont	77:869cf507173a	29	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	30	#ifndef __STM32L1xx_TIM_H
emilmont	77:869cf507173a	31	#define __STM32L1xx_TIM_H
emilmont	77:869cf507173a	32
emilmont	77:869cf507173a	33	#ifdef __cplusplus
emilmont	77:869cf507173a	34	extern "C" {
emilmont	77:869cf507173a	35	#endif
emilmont	77:869cf507173a	36
emilmont	77:869cf507173a	37	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	38	#include "stm32l1xx.h"
emilmont	77:869cf507173a	39
emilmont	77:869cf507173a	40	/** @addtogroup STM32L1xx_StdPeriph_Driver
emilmont	77:869cf507173a	41	* @{
emilmont	77:869cf507173a	42	*/
emilmont	77:869cf507173a	43
emilmont	77:869cf507173a	44	/** @addtogroup TIM
emilmont	77:869cf507173a	45	* @{
emilmont	77:869cf507173a	46	*/
emilmont	77:869cf507173a	47
emilmont	77:869cf507173a	48	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	49
emilmont	77:869cf507173a	50	/**
emilmont	77:869cf507173a	51	* @brief TIM Time Base Init structure definition
emilmont	77:869cf507173a	52	* @note This structure is used with all TIMx except for TIM6 and TIM7.
emilmont	77:869cf507173a	53	*/
emilmont	77:869cf507173a	54
emilmont	77:869cf507173a	55	typedef struct
emilmont	77:869cf507173a	56	{
emilmont	77:869cf507173a	57	uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
emilmont	77:869cf507173a	58	This parameter can be a number between 0x0000 and 0xFFFF */
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
emilmont	77:869cf507173a	61	This parameter can be a value of @ref TIM_Counter_Mode */
emilmont	77:869cf507173a	62
emilmont	77:869cf507173a	63	uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
emilmont	77:869cf507173a	64	Auto-Reload Register at the next update event.
emilmont	77:869cf507173a	65	This parameter must be a number between 0x0000 and 0xFFFF. */
emilmont	77:869cf507173a	66
emilmont	77:869cf507173a	67	uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
emilmont	77:869cf507173a	68	This parameter can be a value of @ref TIM_Clock_Division_CKD */
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	} TIM_TimeBaseInitTypeDef;
emilmont	77:869cf507173a	71
emilmont	77:869cf507173a	72	/**
emilmont	77:869cf507173a	73	* @brief TIM Output Compare Init structure definition
emilmont	77:869cf507173a	74	*/
emilmont	77:869cf507173a	75
emilmont	77:869cf507173a	76	typedef struct
emilmont	77:869cf507173a	77	{
emilmont	77:869cf507173a	78	uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
emilmont	77:869cf507173a	79	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
emilmont	77:869cf507173a	80
emilmont	77:869cf507173a	81	uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
emilmont	77:869cf507173a	82	This parameter can be a value of @ref TIM_Output_Compare_state */
emilmont	77:869cf507173a	83
emilmont	77:869cf507173a	84	uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
emilmont	77:869cf507173a	85	This parameter can be a number between 0x0000 and 0xFFFF */
emilmont	77:869cf507173a	86
emilmont	77:869cf507173a	87	uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
emilmont	77:869cf507173a	88	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
emilmont	77:869cf507173a	89
emilmont	77:869cf507173a	90	} TIM_OCInitTypeDef;
emilmont	77:869cf507173a	91
emilmont	77:869cf507173a	92	/**
emilmont	77:869cf507173a	93	* @brief TIM Input Capture Init structure definition
emilmont	77:869cf507173a	94	*/
emilmont	77:869cf507173a	95
emilmont	77:869cf507173a	96	typedef struct
emilmont	77:869cf507173a	97	{
emilmont	77:869cf507173a	98
emilmont	77:869cf507173a	99	uint16_t TIM_Channel; /*!< Specifies the TIM channel.
emilmont	77:869cf507173a	100	This parameter can be a value of @ref TIM_Channel */
emilmont	77:869cf507173a	101
emilmont	77:869cf507173a	102	uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
emilmont	77:869cf507173a	103	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
emilmont	77:869cf507173a	104
emilmont	77:869cf507173a	105	uint16_t TIM_ICSelection; /*!< Specifies the input.
emilmont	77:869cf507173a	106	This parameter can be a value of @ref TIM_Input_Capture_Selection */
emilmont	77:869cf507173a	107
emilmont	77:869cf507173a	108	uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
emilmont	77:869cf507173a	109	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
emilmont	77:869cf507173a	110
emilmont	77:869cf507173a	111	uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
emilmont	77:869cf507173a	112	This parameter can be a number between 0x0 and 0xF */
emilmont	77:869cf507173a	113	} TIM_ICInitTypeDef;
emilmont	77:869cf507173a	114
emilmont	77:869cf507173a	115	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	116
emilmont	77:869cf507173a	117
emilmont	77:869cf507173a	118	/** @defgroup TIM_Exported_constants
emilmont	77:869cf507173a	119	* @{
emilmont	77:869cf507173a	120	*/
emilmont	77:869cf507173a	121
emilmont	77:869cf507173a	122	#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	123	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	124	((PERIPH) == TIM4) \|\| \
emilmont	77:869cf507173a	125	((PERIPH) == TIM5) \|\| \
emilmont	77:869cf507173a	126	((PERIPH) == TIM6) \|\| \
emilmont	77:869cf507173a	127	((PERIPH) == TIM7) \|\| \
emilmont	77:869cf507173a	128	((PERIPH) == TIM9) \|\| \
emilmont	77:869cf507173a	129	((PERIPH) == TIM10) \|\| \
emilmont	77:869cf507173a	130	((PERIPH) == TIM11))
emilmont	77:869cf507173a	131
emilmont	77:869cf507173a	132	/* LIST1: TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11 */
emilmont	77:869cf507173a	133	#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	134	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	135	((PERIPH) == TIM4) \|\| \
emilmont	77:869cf507173a	136	((PERIPH) == TIM5) \|\| \
emilmont	77:869cf507173a	137	((PERIPH) == TIM9) \|\| \
emilmont	77:869cf507173a	138	((PERIPH) == TIM10) \|\| \
emilmont	77:869cf507173a	139	((PERIPH) == TIM11))
emilmont	77:869cf507173a	140
emilmont	77:869cf507173a	141	/* LIST3: TIM2, TIM3, TIM4 and TIM5 */
emilmont	77:869cf507173a	142	#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	143	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	144	((PERIPH) == TIM4) \|\| \
emilmont	77:869cf507173a	145	((PERIPH) == TIM5))
emilmont	77:869cf507173a	146
emilmont	77:869cf507173a	147	/* LIST2: TIM2, TIM3, TIM4, TIM5 and TIM9 */
emilmont	77:869cf507173a	148	#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	149	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	150	((PERIPH) == TIM4) \|\| \
emilmont	77:869cf507173a	151	((PERIPH) == TIM5) \|\| \
emilmont	77:869cf507173a	152	((PERIPH) == TIM9))
emilmont	77:869cf507173a	153
emilmont	77:869cf507173a	154	/* LIST5: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM9 */
emilmont	77:869cf507173a	155	#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	156	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	157	((PERIPH) == TIM4) \|\| \
emilmont	77:869cf507173a	158	((PERIPH) == TIM5) \|\|\
emilmont	77:869cf507173a	159	((PERIPH) == TIM6) \|\| \
emilmont	77:869cf507173a	160	((PERIPH) == TIM7) \|\|\
emilmont	77:869cf507173a	161	((PERIPH) == TIM9))
emilmont	77:869cf507173a	162
emilmont	77:869cf507173a	163	/* LIST4: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 */
emilmont	77:869cf507173a	164	#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	165	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	166	((PERIPH) == TIM4) \|\| \
emilmont	77:869cf507173a	167	((PERIPH) == TIM5) \|\|\
emilmont	77:869cf507173a	168	((PERIPH) == TIM6) \|\| \
emilmont	77:869cf507173a	169	((PERIPH) == TIM7))
emilmont	77:869cf507173a	170
emilmont	77:869cf507173a	171	/* LIST6: TIM2, TIM3, TIM9, TIM10 and TIM11 */
emilmont	77:869cf507173a	172	#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	173	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	174	((PERIPH) == TIM9) \|\| \
emilmont	77:869cf507173a	175	((PERIPH) == TIM10) \|\| \
emilmont	77:869cf507173a	176	((PERIPH) == TIM11))
emilmont	77:869cf507173a	177
emilmont	77:869cf507173a	178	/* LIST3: TIM2, TIM3, TIM4, TIM5 and TIM9 */
emilmont	77:869cf507173a	179	#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM2) \|\| \
emilmont	77:869cf507173a	180	((PERIPH) == TIM3) \|\| \
emilmont	77:869cf507173a	181	((PERIPH) == TIM4) \|\| \
emilmont	77:869cf507173a	182	((PERIPH) == TIM5) \|\| \
emilmont	77:869cf507173a	183	((PERIPH) == TIM9))
emilmont	77:869cf507173a	184
emilmont	77:869cf507173a	185	/** @defgroup TIM_Output_Compare_and_PWM_modes
emilmont	77:869cf507173a	186	* @{
emilmont	77:869cf507173a	187	*/
emilmont	77:869cf507173a	188
emilmont	77:869cf507173a	189	#define TIM_OCMode_Timing ((uint16_t)0x0000)
emilmont	77:869cf507173a	190	#define TIM_OCMode_Active ((uint16_t)0x0010)
emilmont	77:869cf507173a	191	#define TIM_OCMode_Inactive ((uint16_t)0x0020)
emilmont	77:869cf507173a	192	#define TIM_OCMode_Toggle ((uint16_t)0x0030)
emilmont	77:869cf507173a	193	#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
emilmont	77:869cf507173a	194	#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
emilmont	77:869cf507173a	195	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
emilmont	77:869cf507173a	196	((MODE) == TIM_OCMode_Active) \|\| \
emilmont	77:869cf507173a	197	((MODE) == TIM_OCMode_Inactive) \|\| \
emilmont	77:869cf507173a	198	((MODE) == TIM_OCMode_Toggle)\|\| \
emilmont	77:869cf507173a	199	((MODE) == TIM_OCMode_PWM1) \|\| \
emilmont	77:869cf507173a	200	((MODE) == TIM_OCMode_PWM2))
emilmont	77:869cf507173a	201	#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
emilmont	77:869cf507173a	202	((MODE) == TIM_OCMode_Active) \|\| \
emilmont	77:869cf507173a	203	((MODE) == TIM_OCMode_Inactive) \|\| \
emilmont	77:869cf507173a	204	((MODE) == TIM_OCMode_Toggle)\|\| \
emilmont	77:869cf507173a	205	((MODE) == TIM_OCMode_PWM1) \|\| \
emilmont	77:869cf507173a	206	((MODE) == TIM_OCMode_PWM2) \|\| \
emilmont	77:869cf507173a	207	((MODE) == TIM_ForcedAction_Active) \|\| \
emilmont	77:869cf507173a	208	((MODE) == TIM_ForcedAction_InActive))
emilmont	77:869cf507173a	209	/**
emilmont	77:869cf507173a	210	* @}
emilmont	77:869cf507173a	211	*/
emilmont	77:869cf507173a	212
emilmont	77:869cf507173a	213	/** @defgroup TIM_One_Pulse_Mode
emilmont	77:869cf507173a	214	* @{
emilmont	77:869cf507173a	215	*/
emilmont	77:869cf507173a	216
emilmont	77:869cf507173a	217	#define TIM_OPMode_Single ((uint16_t)0x0008)
emilmont	77:869cf507173a	218	#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
emilmont	77:869cf507173a	219	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) \|\| \
emilmont	77:869cf507173a	220	((MODE) == TIM_OPMode_Repetitive))
emilmont	77:869cf507173a	221	/**
emilmont	77:869cf507173a	222	* @}
emilmont	77:869cf507173a	223	*/
emilmont	77:869cf507173a	224
emilmont	77:869cf507173a	225	/** @defgroup TIM_Channel
emilmont	77:869cf507173a	226	* @{
emilmont	77:869cf507173a	227	*/
emilmont	77:869cf507173a	228
emilmont	77:869cf507173a	229	#define TIM_Channel_1 ((uint16_t)0x0000)
emilmont	77:869cf507173a	230	#define TIM_Channel_2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	231	#define TIM_Channel_3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	232	#define TIM_Channel_4 ((uint16_t)0x000C)
emilmont	77:869cf507173a	233
emilmont	77:869cf507173a	234	#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
emilmont	77:869cf507173a	235	((CHANNEL) == TIM_Channel_2) \|\| \
emilmont	77:869cf507173a	236	((CHANNEL) == TIM_Channel_3) \|\| \
emilmont	77:869cf507173a	237	((CHANNEL) == TIM_Channel_4))
emilmont	77:869cf507173a	238
emilmont	77:869cf507173a	239	#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
emilmont	77:869cf507173a	240	((CHANNEL) == TIM_Channel_2))
emilmont	77:869cf507173a	241
emilmont	77:869cf507173a	242	/**
emilmont	77:869cf507173a	243	* @}
emilmont	77:869cf507173a	244	*/
emilmont	77:869cf507173a	245
emilmont	77:869cf507173a	246	/** @defgroup TIM_Clock_Division_CKD
emilmont	77:869cf507173a	247	* @{
emilmont	77:869cf507173a	248	*/
emilmont	77:869cf507173a	249
emilmont	77:869cf507173a	250	#define TIM_CKD_DIV1 ((uint16_t)0x0000)
emilmont	77:869cf507173a	251	#define TIM_CKD_DIV2 ((uint16_t)0x0100)
emilmont	77:869cf507173a	252	#define TIM_CKD_DIV4 ((uint16_t)0x0200)
emilmont	77:869cf507173a	253	#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) \|\| \
emilmont	77:869cf507173a	254	((DIV) == TIM_CKD_DIV2) \|\| \
emilmont	77:869cf507173a	255	((DIV) == TIM_CKD_DIV4))
emilmont	77:869cf507173a	256	/**
emilmont	77:869cf507173a	257	* @}
emilmont	77:869cf507173a	258	*/
emilmont	77:869cf507173a	259
emilmont	77:869cf507173a	260	/** @defgroup TIM_Counter_Mode
emilmont	77:869cf507173a	261	* @{
emilmont	77:869cf507173a	262	*/
emilmont	77:869cf507173a	263
emilmont	77:869cf507173a	264	#define TIM_CounterMode_Up ((uint16_t)0x0000)
emilmont	77:869cf507173a	265	#define TIM_CounterMode_Down ((uint16_t)0x0010)
emilmont	77:869cf507173a	266	#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
emilmont	77:869cf507173a	267	#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
emilmont	77:869cf507173a	268	#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
emilmont	77:869cf507173a	269	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) \|\| \
emilmont	77:869cf507173a	270	((MODE) == TIM_CounterMode_Down) \|\| \
emilmont	77:869cf507173a	271	((MODE) == TIM_CounterMode_CenterAligned1) \|\| \
emilmont	77:869cf507173a	272	((MODE) == TIM_CounterMode_CenterAligned2) \|\| \
emilmont	77:869cf507173a	273	((MODE) == TIM_CounterMode_CenterAligned3))
emilmont	77:869cf507173a	274	/**
emilmont	77:869cf507173a	275	* @}
emilmont	77:869cf507173a	276	*/
emilmont	77:869cf507173a	277
emilmont	77:869cf507173a	278	/** @defgroup TIM_Output_Compare_Polarity
emilmont	77:869cf507173a	279	* @{
emilmont	77:869cf507173a	280	*/
emilmont	77:869cf507173a	281
emilmont	77:869cf507173a	282	#define TIM_OCPolarity_High ((uint16_t)0x0000)
emilmont	77:869cf507173a	283	#define TIM_OCPolarity_Low ((uint16_t)0x0002)
emilmont	77:869cf507173a	284	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) \|\| \
emilmont	77:869cf507173a	285	((POLARITY) == TIM_OCPolarity_Low))
emilmont	77:869cf507173a	286	/**
emilmont	77:869cf507173a	287	* @}
emilmont	77:869cf507173a	288	*/
emilmont	77:869cf507173a	289
emilmont	77:869cf507173a	290
emilmont	77:869cf507173a	291	/** @defgroup TIM_Output_Compare_state
emilmont	77:869cf507173a	292	* @{
emilmont	77:869cf507173a	293	*/
emilmont	77:869cf507173a	294
emilmont	77:869cf507173a	295	#define TIM_OutputState_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	296	#define TIM_OutputState_Enable ((uint16_t)0x0001)
emilmont	77:869cf507173a	297	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) \|\| \
emilmont	77:869cf507173a	298	((STATE) == TIM_OutputState_Enable))
emilmont	77:869cf507173a	299	/**
emilmont	77:869cf507173a	300	* @}
emilmont	77:869cf507173a	301	*/
emilmont	77:869cf507173a	302
emilmont	77:869cf507173a	303
emilmont	77:869cf507173a	304	/** @defgroup TIM_Capture_Compare_state
emilmont	77:869cf507173a	305	* @{
emilmont	77:869cf507173a	306	*/
emilmont	77:869cf507173a	307
emilmont	77:869cf507173a	308	#define TIM_CCx_Enable ((uint16_t)0x0001)
emilmont	77:869cf507173a	309	#define TIM_CCx_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	310	#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) \|\| \
emilmont	77:869cf507173a	311	((CCX) == TIM_CCx_Disable))
emilmont	77:869cf507173a	312	/**
emilmont	77:869cf507173a	313	* @}
emilmont	77:869cf507173a	314	*/
emilmont	77:869cf507173a	315
emilmont	77:869cf507173a	316	/** @defgroup TIM_Input_Capture_Polarity
emilmont	77:869cf507173a	317	* @{
emilmont	77:869cf507173a	318	*/
emilmont	77:869cf507173a	319
emilmont	77:869cf507173a	320	#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
emilmont	77:869cf507173a	321	#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
emilmont	77:869cf507173a	322	#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
emilmont	77:869cf507173a	323	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
emilmont	77:869cf507173a	324	((POLARITY) == TIM_ICPolarity_Falling)\|\| \
emilmont	77:869cf507173a	325	((POLARITY) == TIM_ICPolarity_BothEdge))
emilmont	77:869cf507173a	326	/**
emilmont	77:869cf507173a	327	* @}
emilmont	77:869cf507173a	328	*/
emilmont	77:869cf507173a	329
emilmont	77:869cf507173a	330	/** @defgroup TIM_Input_Capture_Selection
emilmont	77:869cf507173a	331	* @{
emilmont	77:869cf507173a	332	*/
emilmont	77:869cf507173a	333
emilmont	77:869cf507173a	334	#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
emilmont	77:869cf507173a	335	connected to IC1, IC2, IC3 or IC4, respectively */
emilmont	77:869cf507173a	336	#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
emilmont	77:869cf507173a	337	connected to IC2, IC1, IC4 or IC3, respectively. */
emilmont	77:869cf507173a	338	#define TIM_ICSelection_TRC ((uint16_t)0x0003) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. /
emilmont	77:869cf507173a	339	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) \|\| \
emilmont	77:869cf507173a	340	((SELECTION) == TIM_ICSelection_IndirectTI) \|\| \
emilmont	77:869cf507173a	341	((SELECTION) == TIM_ICSelection_TRC))
emilmont	77:869cf507173a	342	/**
emilmont	77:869cf507173a	343	* @}
emilmont	77:869cf507173a	344	*/
emilmont	77:869cf507173a	345
emilmont	77:869cf507173a	346	/** @defgroup TIM_Input_Capture_Prescaler
emilmont	77:869cf507173a	347	* @{
emilmont	77:869cf507173a	348	*/
emilmont	77:869cf507173a	349
emilmont	77:869cf507173a	350	#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /!< Capture performed each time an edge is detected on the capture input. /
emilmont	77:869cf507173a	351	#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /!< Capture performed once every 2 events. /
emilmont	77:869cf507173a	352	#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /!< Capture performed once every 4 events. /
emilmont	77:869cf507173a	353	#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /!< Capture performed once every 8 events. /
emilmont	77:869cf507173a	354	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
emilmont	77:869cf507173a	355	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
emilmont	77:869cf507173a	356	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
emilmont	77:869cf507173a	357	((PRESCALER) == TIM_ICPSC_DIV8))
emilmont	77:869cf507173a	358	/**
emilmont	77:869cf507173a	359	* @}
emilmont	77:869cf507173a	360	*/
emilmont	77:869cf507173a	361
emilmont	77:869cf507173a	362	/** @defgroup TIM_interrupt_sources
emilmont	77:869cf507173a	363	* @{
emilmont	77:869cf507173a	364	*/
emilmont	77:869cf507173a	365
emilmont	77:869cf507173a	366	#define TIM_IT_Update ((uint16_t)0x0001)
emilmont	77:869cf507173a	367	#define TIM_IT_CC1 ((uint16_t)0x0002)
emilmont	77:869cf507173a	368	#define TIM_IT_CC2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	369	#define TIM_IT_CC3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	370	#define TIM_IT_CC4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	371	#define TIM_IT_Trigger ((uint16_t)0x0040)
emilmont	77:869cf507173a	372	#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
emilmont	77:869cf507173a	373
emilmont	77:869cf507173a	374	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) \|\| \
emilmont	77:869cf507173a	375	((IT) == TIM_IT_CC1) \|\| \
emilmont	77:869cf507173a	376	((IT) == TIM_IT_CC2) \|\| \
emilmont	77:869cf507173a	377	((IT) == TIM_IT_CC3) \|\| \
emilmont	77:869cf507173a	378	((IT) == TIM_IT_CC4) \|\| \
emilmont	77:869cf507173a	379	((IT) == TIM_IT_Trigger))
emilmont	77:869cf507173a	380	/**
emilmont	77:869cf507173a	381	* @}
emilmont	77:869cf507173a	382	*/
emilmont	77:869cf507173a	383
emilmont	77:869cf507173a	384	/** @defgroup TIM_DMA_Base_address
emilmont	77:869cf507173a	385	* @{
emilmont	77:869cf507173a	386	*/
emilmont	77:869cf507173a	387
emilmont	77:869cf507173a	388	#define TIM_DMABase_CR1 ((uint16_t)0x0000)
emilmont	77:869cf507173a	389	#define TIM_DMABase_CR2 ((uint16_t)0x0001)
emilmont	77:869cf507173a	390	#define TIM_DMABase_SMCR ((uint16_t)0x0002)
emilmont	77:869cf507173a	391	#define TIM_DMABase_DIER ((uint16_t)0x0003)
emilmont	77:869cf507173a	392	#define TIM_DMABase_SR ((uint16_t)0x0004)
emilmont	77:869cf507173a	393	#define TIM_DMABase_EGR ((uint16_t)0x0005)
emilmont	77:869cf507173a	394	#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
emilmont	77:869cf507173a	395	#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
emilmont	77:869cf507173a	396	#define TIM_DMABase_CCER ((uint16_t)0x0008)
emilmont	77:869cf507173a	397	#define TIM_DMABase_CNT ((uint16_t)0x0009)
emilmont	77:869cf507173a	398	#define TIM_DMABase_PSC ((uint16_t)0x000A)
emilmont	77:869cf507173a	399	#define TIM_DMABase_ARR ((uint16_t)0x000B)
emilmont	77:869cf507173a	400	#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
emilmont	77:869cf507173a	401	#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
emilmont	77:869cf507173a	402	#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
emilmont	77:869cf507173a	403	#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	404	#define TIM_DMABase_DCR ((uint16_t)0x0012)
emilmont	77:869cf507173a	405	#define TIM_DMABase_OR ((uint16_t)0x0013)
emilmont	77:869cf507173a	406	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
emilmont	77:869cf507173a	407	((BASE) == TIM_DMABase_CR2) \|\| \
emilmont	77:869cf507173a	408	((BASE) == TIM_DMABase_SMCR) \|\| \
emilmont	77:869cf507173a	409	((BASE) == TIM_DMABase_DIER) \|\| \
emilmont	77:869cf507173a	410	((BASE) == TIM_DMABase_SR) \|\| \
emilmont	77:869cf507173a	411	((BASE) == TIM_DMABase_EGR) \|\| \
emilmont	77:869cf507173a	412	((BASE) == TIM_DMABase_CCMR1) \|\| \
emilmont	77:869cf507173a	413	((BASE) == TIM_DMABase_CCMR2) \|\| \
emilmont	77:869cf507173a	414	((BASE) == TIM_DMABase_CCER) \|\| \
emilmont	77:869cf507173a	415	((BASE) == TIM_DMABase_CNT) \|\| \
emilmont	77:869cf507173a	416	((BASE) == TIM_DMABase_PSC) \|\| \
emilmont	77:869cf507173a	417	((BASE) == TIM_DMABase_ARR) \|\| \
emilmont	77:869cf507173a	418	((BASE) == TIM_DMABase_CCR1) \|\| \
emilmont	77:869cf507173a	419	((BASE) == TIM_DMABase_CCR2) \|\| \
emilmont	77:869cf507173a	420	((BASE) == TIM_DMABase_CCR3) \|\| \
emilmont	77:869cf507173a	421	((BASE) == TIM_DMABase_CCR4) \|\| \
emilmont	77:869cf507173a	422	((BASE) == TIM_DMABase_DCR) \|\| \
emilmont	77:869cf507173a	423	((BASE) == TIM_DMABase_OR))
emilmont	77:869cf507173a	424	/**
emilmont	77:869cf507173a	425	* @}
emilmont	77:869cf507173a	426	*/
emilmont	77:869cf507173a	427
emilmont	77:869cf507173a	428	/** @defgroup TIM_DMA_Burst_Length
emilmont	77:869cf507173a	429	* @{
emilmont	77:869cf507173a	430	*/
emilmont	77:869cf507173a	431
emilmont	77:869cf507173a	432	#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
emilmont	77:869cf507173a	433	#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
emilmont	77:869cf507173a	434	#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
emilmont	77:869cf507173a	435	#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
emilmont	77:869cf507173a	436	#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
emilmont	77:869cf507173a	437	#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
emilmont	77:869cf507173a	438	#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
emilmont	77:869cf507173a	439	#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
emilmont	77:869cf507173a	440	#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
emilmont	77:869cf507173a	441	#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
emilmont	77:869cf507173a	442	#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
emilmont	77:869cf507173a	443	#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
emilmont	77:869cf507173a	444	#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
emilmont	77:869cf507173a	445	#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
emilmont	77:869cf507173a	446	#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
emilmont	77:869cf507173a	447	#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
emilmont	77:869cf507173a	448	#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
emilmont	77:869cf507173a	449	#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
emilmont	77:869cf507173a	450	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
emilmont	77:869cf507173a	451	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
emilmont	77:869cf507173a	452	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
emilmont	77:869cf507173a	453	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
emilmont	77:869cf507173a	454	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
emilmont	77:869cf507173a	455	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
emilmont	77:869cf507173a	456	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
emilmont	77:869cf507173a	457	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
emilmont	77:869cf507173a	458	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
emilmont	77:869cf507173a	459	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
emilmont	77:869cf507173a	460	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
emilmont	77:869cf507173a	461	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
emilmont	77:869cf507173a	462	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
emilmont	77:869cf507173a	463	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
emilmont	77:869cf507173a	464	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
emilmont	77:869cf507173a	465	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
emilmont	77:869cf507173a	466	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
emilmont	77:869cf507173a	467	((LENGTH) == TIM_DMABurstLength_18Transfers))
emilmont	77:869cf507173a	468	/**
emilmont	77:869cf507173a	469	* @}
emilmont	77:869cf507173a	470	*/
emilmont	77:869cf507173a	471
emilmont	77:869cf507173a	472	/** @defgroup TIM_DMA_sources
emilmont	77:869cf507173a	473	* @{
emilmont	77:869cf507173a	474	*/
emilmont	77:869cf507173a	475
emilmont	77:869cf507173a	476	#define TIM_DMA_Update ((uint16_t)0x0100)
emilmont	77:869cf507173a	477	#define TIM_DMA_CC1 ((uint16_t)0x0200)
emilmont	77:869cf507173a	478	#define TIM_DMA_CC2 ((uint16_t)0x0400)
emilmont	77:869cf507173a	479	#define TIM_DMA_CC3 ((uint16_t)0x0800)
emilmont	77:869cf507173a	480	#define TIM_DMA_CC4 ((uint16_t)0x1000)
emilmont	77:869cf507173a	481	#define TIM_DMA_Trigger ((uint16_t)0x4000)
emilmont	77:869cf507173a	482	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
emilmont	77:869cf507173a	483
emilmont	77:869cf507173a	484	/**
emilmont	77:869cf507173a	485	* @}
emilmont	77:869cf507173a	486	*/
emilmont	77:869cf507173a	487
emilmont	77:869cf507173a	488	/** @defgroup TIM_External_Trigger_Prescaler
emilmont	77:869cf507173a	489	* @{
emilmont	77:869cf507173a	490	*/
emilmont	77:869cf507173a	491
emilmont	77:869cf507173a	492	#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
emilmont	77:869cf507173a	493	#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
emilmont	77:869cf507173a	494	#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
emilmont	77:869cf507173a	495	#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
emilmont	77:869cf507173a	496	#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) \|\| \
emilmont	77:869cf507173a	497	((PRESCALER) == TIM_ExtTRGPSC_DIV2) \|\| \
emilmont	77:869cf507173a	498	((PRESCALER) == TIM_ExtTRGPSC_DIV4) \|\| \
emilmont	77:869cf507173a	499	((PRESCALER) == TIM_ExtTRGPSC_DIV8))
emilmont	77:869cf507173a	500	/**
emilmont	77:869cf507173a	501	* @}
emilmont	77:869cf507173a	502	*/
emilmont	77:869cf507173a	503
emilmont	77:869cf507173a	504	/** @defgroup TIM_Internal_Trigger_Selection
emilmont	77:869cf507173a	505	* @{
emilmont	77:869cf507173a	506	*/
emilmont	77:869cf507173a	507
emilmont	77:869cf507173a	508	#define TIM_TS_ITR0 ((uint16_t)0x0000)
emilmont	77:869cf507173a	509	#define TIM_TS_ITR1 ((uint16_t)0x0010)
emilmont	77:869cf507173a	510	#define TIM_TS_ITR2 ((uint16_t)0x0020)
emilmont	77:869cf507173a	511	#define TIM_TS_ITR3 ((uint16_t)0x0030)
emilmont	77:869cf507173a	512	#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
emilmont	77:869cf507173a	513	#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
emilmont	77:869cf507173a	514	#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
emilmont	77:869cf507173a	515	#define TIM_TS_ETRF ((uint16_t)0x0070)
emilmont	77:869cf507173a	516	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
emilmont	77:869cf507173a	517	((SELECTION) == TIM_TS_ITR1) \|\| \
emilmont	77:869cf507173a	518	((SELECTION) == TIM_TS_ITR2) \|\| \
emilmont	77:869cf507173a	519	((SELECTION) == TIM_TS_ITR3) \|\| \
emilmont	77:869cf507173a	520	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
emilmont	77:869cf507173a	521	((SELECTION) == TIM_TS_TI1FP1) \|\| \
emilmont	77:869cf507173a	522	((SELECTION) == TIM_TS_TI2FP2) \|\| \
emilmont	77:869cf507173a	523	((SELECTION) == TIM_TS_ETRF))
emilmont	77:869cf507173a	524	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
emilmont	77:869cf507173a	525	((SELECTION) == TIM_TS_ITR1) \|\| \
emilmont	77:869cf507173a	526	((SELECTION) == TIM_TS_ITR2) \|\| \
emilmont	77:869cf507173a	527	((SELECTION) == TIM_TS_ITR3))
emilmont	77:869cf507173a	528	/**
emilmont	77:869cf507173a	529	* @}
emilmont	77:869cf507173a	530	*/
emilmont	77:869cf507173a	531
emilmont	77:869cf507173a	532	/** @defgroup TIM_TIx_External_Clock_Source
emilmont	77:869cf507173a	533	* @{
emilmont	77:869cf507173a	534	*/
emilmont	77:869cf507173a	535
emilmont	77:869cf507173a	536	#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
emilmont	77:869cf507173a	537	#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
emilmont	77:869cf507173a	538	#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
emilmont	77:869cf507173a	539
emilmont	77:869cf507173a	540	/**
emilmont	77:869cf507173a	541	* @}
emilmont	77:869cf507173a	542	*/
emilmont	77:869cf507173a	543
emilmont	77:869cf507173a	544	/** @defgroup TIM_External_Trigger_Polarity
emilmont	77:869cf507173a	545	* @{
emilmont	77:869cf507173a	546	*/
emilmont	77:869cf507173a	547	#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
emilmont	77:869cf507173a	548	#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
emilmont	77:869cf507173a	549	#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) \|\| \
emilmont	77:869cf507173a	550	((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
emilmont	77:869cf507173a	551	/**
emilmont	77:869cf507173a	552	* @}
emilmont	77:869cf507173a	553	*/
emilmont	77:869cf507173a	554
emilmont	77:869cf507173a	555	/** @defgroup TIM_Prescaler_Reload_Mode
emilmont	77:869cf507173a	556	* @{
emilmont	77:869cf507173a	557	*/
emilmont	77:869cf507173a	558
emilmont	77:869cf507173a	559	#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
emilmont	77:869cf507173a	560	#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
emilmont	77:869cf507173a	561	#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) \|\| \
emilmont	77:869cf507173a	562	((RELOAD) == TIM_PSCReloadMode_Immediate))
emilmont	77:869cf507173a	563	/**
emilmont	77:869cf507173a	564	* @}
emilmont	77:869cf507173a	565	*/
emilmont	77:869cf507173a	566
emilmont	77:869cf507173a	567	/** @defgroup TIM_Forced_Action
emilmont	77:869cf507173a	568	* @{
emilmont	77:869cf507173a	569	*/
emilmont	77:869cf507173a	570
emilmont	77:869cf507173a	571	#define TIM_ForcedAction_Active ((uint16_t)0x0050)
emilmont	77:869cf507173a	572	#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
emilmont	77:869cf507173a	573	#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) \|\| \
emilmont	77:869cf507173a	574	((ACTION) == TIM_ForcedAction_InActive))
emilmont	77:869cf507173a	575	/**
emilmont	77:869cf507173a	576	* @}
emilmont	77:869cf507173a	577	*/
emilmont	77:869cf507173a	578
emilmont	77:869cf507173a	579	/** @defgroup TIM_Encoder_Mode
emilmont	77:869cf507173a	580	* @{
emilmont	77:869cf507173a	581	*/
emilmont	77:869cf507173a	582
emilmont	77:869cf507173a	583	#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
emilmont	77:869cf507173a	584	#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
emilmont	77:869cf507173a	585	#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
emilmont	77:869cf507173a	586	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) \|\| \
emilmont	77:869cf507173a	587	((MODE) == TIM_EncoderMode_TI2) \|\| \
emilmont	77:869cf507173a	588	((MODE) == TIM_EncoderMode_TI12))
emilmont	77:869cf507173a	589	/**
emilmont	77:869cf507173a	590	* @}
emilmont	77:869cf507173a	591	*/
emilmont	77:869cf507173a	592
emilmont	77:869cf507173a	593
emilmont	77:869cf507173a	594	/** @defgroup TIM_Event_Source
emilmont	77:869cf507173a	595	* @{
emilmont	77:869cf507173a	596	*/
emilmont	77:869cf507173a	597
emilmont	77:869cf507173a	598	#define TIM_EventSource_Update ((uint16_t)0x0001)
emilmont	77:869cf507173a	599	#define TIM_EventSource_CC1 ((uint16_t)0x0002)
emilmont	77:869cf507173a	600	#define TIM_EventSource_CC2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	601	#define TIM_EventSource_CC3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	602	#define TIM_EventSource_CC4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	603	#define TIM_EventSource_Trigger ((uint16_t)0x0040)
emilmont	77:869cf507173a	604	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
emilmont	77:869cf507173a	605
emilmont	77:869cf507173a	606	/**
emilmont	77:869cf507173a	607	* @}
emilmont	77:869cf507173a	608	*/
emilmont	77:869cf507173a	609
emilmont	77:869cf507173a	610	/** @defgroup TIM_Update_Source
emilmont	77:869cf507173a	611	* @{
emilmont	77:869cf507173a	612	*/
emilmont	77:869cf507173a	613
emilmont	77:869cf507173a	614	#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
emilmont	77:869cf507173a	615	or the setting of UG bit, or an update generation
emilmont	77:869cf507173a	616	through the slave mode controller. */
emilmont	77:869cf507173a	617	#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /!< Source of update is counter overflow/underflow. /
emilmont	77:869cf507173a	618	#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) \|\| \
emilmont	77:869cf507173a	619	((SOURCE) == TIM_UpdateSource_Regular))
emilmont	77:869cf507173a	620	/**
emilmont	77:869cf507173a	621	* @}
emilmont	77:869cf507173a	622	*/
emilmont	77:869cf507173a	623
emilmont	77:869cf507173a	624	/** @defgroup TIM_Output_Compare_Preload_State
emilmont	77:869cf507173a	625	* @{
emilmont	77:869cf507173a	626	*/
emilmont	77:869cf507173a	627
emilmont	77:869cf507173a	628	#define TIM_OCPreload_Enable ((uint16_t)0x0008)
emilmont	77:869cf507173a	629	#define TIM_OCPreload_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	630	#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) \|\| \
emilmont	77:869cf507173a	631	((STATE) == TIM_OCPreload_Disable))
emilmont	77:869cf507173a	632	/**
emilmont	77:869cf507173a	633	* @}
emilmont	77:869cf507173a	634	*/
emilmont	77:869cf507173a	635
emilmont	77:869cf507173a	636	/** @defgroup TIM_Output_Compare_Fast_State
emilmont	77:869cf507173a	637	* @{
emilmont	77:869cf507173a	638	*/
emilmont	77:869cf507173a	639
emilmont	77:869cf507173a	640	#define TIM_OCFast_Enable ((uint16_t)0x0004)
emilmont	77:869cf507173a	641	#define TIM_OCFast_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	642	#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) \|\| \
emilmont	77:869cf507173a	643	((STATE) == TIM_OCFast_Disable))
emilmont	77:869cf507173a	644
emilmont	77:869cf507173a	645	/**
emilmont	77:869cf507173a	646	* @}
emilmont	77:869cf507173a	647	*/
emilmont	77:869cf507173a	648
emilmont	77:869cf507173a	649	/** @defgroup TIM_Output_Compare_Clear_State
emilmont	77:869cf507173a	650	* @{
emilmont	77:869cf507173a	651	*/
emilmont	77:869cf507173a	652
emilmont	77:869cf507173a	653	#define TIM_OCClear_Enable ((uint16_t)0x0080)
emilmont	77:869cf507173a	654	#define TIM_OCClear_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	655	#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) \|\| \
emilmont	77:869cf507173a	656	((STATE) == TIM_OCClear_Disable))
emilmont	77:869cf507173a	657	/**
emilmont	77:869cf507173a	658	* @}
emilmont	77:869cf507173a	659	*/
emilmont	77:869cf507173a	660
emilmont	77:869cf507173a	661	/** @defgroup TIM_Trigger_Output_Source
emilmont	77:869cf507173a	662	* @{
emilmont	77:869cf507173a	663	*/
emilmont	77:869cf507173a	664
emilmont	77:869cf507173a	665	#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
emilmont	77:869cf507173a	666	#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
emilmont	77:869cf507173a	667	#define TIM_TRGOSource_Update ((uint16_t)0x0020)
emilmont	77:869cf507173a	668	#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
emilmont	77:869cf507173a	669	#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
emilmont	77:869cf507173a	670	#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
emilmont	77:869cf507173a	671	#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
emilmont	77:869cf507173a	672	#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
emilmont	77:869cf507173a	673	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) \|\| \
emilmont	77:869cf507173a	674	((SOURCE) == TIM_TRGOSource_Enable) \|\| \
emilmont	77:869cf507173a	675	((SOURCE) == TIM_TRGOSource_Update) \|\| \
emilmont	77:869cf507173a	676	((SOURCE) == TIM_TRGOSource_OC1) \|\| \
emilmont	77:869cf507173a	677	((SOURCE) == TIM_TRGOSource_OC1Ref) \|\| \
emilmont	77:869cf507173a	678	((SOURCE) == TIM_TRGOSource_OC2Ref) \|\| \
emilmont	77:869cf507173a	679	((SOURCE) == TIM_TRGOSource_OC3Ref) \|\| \
emilmont	77:869cf507173a	680	((SOURCE) == TIM_TRGOSource_OC4Ref))
emilmont	77:869cf507173a	681	/**
emilmont	77:869cf507173a	682	* @}
emilmont	77:869cf507173a	683	*/
emilmont	77:869cf507173a	684
emilmont	77:869cf507173a	685	/** @defgroup TIM_Slave_Mode
emilmont	77:869cf507173a	686	* @{
emilmont	77:869cf507173a	687	*/
emilmont	77:869cf507173a	688
emilmont	77:869cf507173a	689	#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
emilmont	77:869cf507173a	690	#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
emilmont	77:869cf507173a	691	#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
emilmont	77:869cf507173a	692	#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
emilmont	77:869cf507173a	693	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) \|\| \
emilmont	77:869cf507173a	694	((MODE) == TIM_SlaveMode_Gated) \|\| \
emilmont	77:869cf507173a	695	((MODE) == TIM_SlaveMode_Trigger) \|\| \
emilmont	77:869cf507173a	696	((MODE) == TIM_SlaveMode_External1))
emilmont	77:869cf507173a	697	/**
emilmont	77:869cf507173a	698	* @}
emilmont	77:869cf507173a	699	*/
emilmont	77:869cf507173a	700
emilmont	77:869cf507173a	701	/** @defgroup TIM_Master_Slave_Mode
emilmont	77:869cf507173a	702	* @{
emilmont	77:869cf507173a	703	*/
emilmont	77:869cf507173a	704
emilmont	77:869cf507173a	705	#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
emilmont	77:869cf507173a	706	#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
emilmont	77:869cf507173a	707	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) \|\| \
emilmont	77:869cf507173a	708	((STATE) == TIM_MasterSlaveMode_Disable))
emilmont	77:869cf507173a	709	/**
emilmont	77:869cf507173a	710	* @}
emilmont	77:869cf507173a	711	*/
emilmont	77:869cf507173a	712
emilmont	77:869cf507173a	713	/** @defgroup TIM_Flags
emilmont	77:869cf507173a	714	* @{
emilmont	77:869cf507173a	715	*/
emilmont	77:869cf507173a	716
emilmont	77:869cf507173a	717	#define TIM_FLAG_Update ((uint16_t)0x0001)
emilmont	77:869cf507173a	718	#define TIM_FLAG_CC1 ((uint16_t)0x0002)
emilmont	77:869cf507173a	719	#define TIM_FLAG_CC2 ((uint16_t)0x0004)
emilmont	77:869cf507173a	720	#define TIM_FLAG_CC3 ((uint16_t)0x0008)
emilmont	77:869cf507173a	721	#define TIM_FLAG_CC4 ((uint16_t)0x0010)
emilmont	77:869cf507173a	722	#define TIM_FLAG_Trigger ((uint16_t)0x0040)
emilmont	77:869cf507173a	723	#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
emilmont	77:869cf507173a	724	#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
emilmont	77:869cf507173a	725	#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
emilmont	77:869cf507173a	726	#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
emilmont	77:869cf507173a	727	#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) \|\| \
emilmont	77:869cf507173a	728	((FLAG) == TIM_FLAG_CC1) \|\| \
emilmont	77:869cf507173a	729	((FLAG) == TIM_FLAG_CC2) \|\| \
emilmont	77:869cf507173a	730	((FLAG) == TIM_FLAG_CC3) \|\| \
emilmont	77:869cf507173a	731	((FLAG) == TIM_FLAG_CC4) \|\| \
emilmont	77:869cf507173a	732	((FLAG) == TIM_FLAG_Trigger) \|\| \
emilmont	77:869cf507173a	733	((FLAG) == TIM_FLAG_CC1OF) \|\| \
emilmont	77:869cf507173a	734	((FLAG) == TIM_FLAG_CC2OF) \|\| \
emilmont	77:869cf507173a	735	((FLAG) == TIM_FLAG_CC3OF) \|\| \
emilmont	77:869cf507173a	736	((FLAG) == TIM_FLAG_CC4OF))
emilmont	77:869cf507173a	737	#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
emilmont	77:869cf507173a	738
emilmont	77:869cf507173a	739	/**
emilmont	77:869cf507173a	740	* @}
emilmont	77:869cf507173a	741	*/
emilmont	77:869cf507173a	742
emilmont	77:869cf507173a	743	/** @defgroup TIM_Input_Capture_Filer_Value
emilmont	77:869cf507173a	744	* @{
emilmont	77:869cf507173a	745	*/
emilmont	77:869cf507173a	746
emilmont	77:869cf507173a	747	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
emilmont	77:869cf507173a	748	/**
emilmont	77:869cf507173a	749	* @}
emilmont	77:869cf507173a	750	*/
emilmont	77:869cf507173a	751
emilmont	77:869cf507173a	752	/** @defgroup TIM_External_Trigger_Filter
emilmont	77:869cf507173a	753	* @{
emilmont	77:869cf507173a	754	*/
emilmont	77:869cf507173a	755
emilmont	77:869cf507173a	756	#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
emilmont	77:869cf507173a	757	/**
emilmont	77:869cf507173a	758	* @}
emilmont	77:869cf507173a	759	*/
emilmont	77:869cf507173a	760
emilmont	77:869cf507173a	761	/** @defgroup TIM_OCReferenceClear
emilmont	77:869cf507173a	762	* @{
emilmont	77:869cf507173a	763	*/
emilmont	77:869cf507173a	764	#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
emilmont	77:869cf507173a	765	#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
emilmont	77:869cf507173a	766	#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) \|\| \
emilmont	77:869cf507173a	767	((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
emilmont	77:869cf507173a	768
emilmont	77:869cf507173a	769	/**
emilmont	77:869cf507173a	770	* @}
emilmont	77:869cf507173a	771	*/
emilmont	77:869cf507173a	772
emilmont	77:869cf507173a	773	/** @defgroup TIM_Remap
emilmont	77:869cf507173a	774	* @{
emilmont	77:869cf507173a	775	*/
emilmont	77:869cf507173a	776
emilmont	77:869cf507173a	777	#define TIM2_TIM10_OC ((uint32_t)0xFFFE0000)
emilmont	77:869cf507173a	778	#define TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001)
emilmont	77:869cf507173a	779
emilmont	77:869cf507173a	780	#define TIM3_TIM11_OC ((uint32_t)0xFFFE0000)
emilmont	77:869cf507173a	781	#define TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001)
emilmont	77:869cf507173a	782
emilmont	77:869cf507173a	783	#define TIM9_GPIO ((uint32_t)0xFFFC0000)
emilmont	77:869cf507173a	784	#define TIM9_LSE ((uint32_t)0xFFFC0001)
emilmont	77:869cf507173a	785
emilmont	77:869cf507173a	786	#define TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000)
emilmont	77:869cf507173a	787	#define TIM9_TS_IO ((uint32_t)0xFFFB0004)
emilmont	77:869cf507173a	788
emilmont	77:869cf507173a	789	#define TIM10_GPIO ((uint32_t)0xFFF40000)
emilmont	77:869cf507173a	790	#define TIM10_LSI ((uint32_t)0xFFF40001)
emilmont	77:869cf507173a	791	#define TIM10_LSE ((uint32_t)0xFFF40002)
emilmont	77:869cf507173a	792	#define TIM10_RTC ((uint32_t)0xFFF40003)
emilmont	77:869cf507173a	793	#define TIM10_RI ((uint32_t)0xFFF40008)
emilmont	77:869cf507173a	794
emilmont	77:869cf507173a	795	#define TIM10_ETR_LSE ((uint32_t)0xFFFB0000)
emilmont	77:869cf507173a	796	#define TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
emilmont	77:869cf507173a	797
emilmont	77:869cf507173a	798	#define TIM11_GPIO ((uint32_t)0xFFF40000)
emilmont	77:869cf507173a	799	#define TIM11_MSI ((uint32_t)0xFFF40001)
emilmont	77:869cf507173a	800	#define TIM11_HSE_RTC ((uint32_t)0xFFF40002)
emilmont	77:869cf507173a	801	#define TIM11_RI ((uint32_t)0xFFF40008)
emilmont	77:869cf507173a	802
emilmont	77:869cf507173a	803	#define TIM11_ETR_LSE ((uint32_t)0xFFFB0000)
emilmont	77:869cf507173a	804	#define TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
emilmont	77:869cf507173a	805
emilmont	77:869cf507173a	806	#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM10_OC)\|\| \
emilmont	77:869cf507173a	807	((TIM_REMAP) == TIM2_TIM5_TRGO)\|\| \
emilmont	77:869cf507173a	808	((TIM_REMAP) == TIM3_TIM11_OC)\|\| \
emilmont	77:869cf507173a	809	((TIM_REMAP) == TIM3_TIM5_TRGO)\|\| \
emilmont	77:869cf507173a	810	((TIM_REMAP) == TIM9_GPIO)\|\| \
emilmont	77:869cf507173a	811	((TIM_REMAP) == TIM9_LSE)\|\| \
emilmont	77:869cf507173a	812	((TIM_REMAP) == TIM9_TIM3_TRGO)\|\| \
emilmont	77:869cf507173a	813	((TIM_REMAP) == TIM9_TS_IO)\|\| \
emilmont	77:869cf507173a	814	((TIM_REMAP) == TIM10_GPIO)\|\| \
emilmont	77:869cf507173a	815	((TIM_REMAP) == TIM10_LSI)\|\| \
emilmont	77:869cf507173a	816	((TIM_REMAP) == TIM10_LSE)\|\| \
emilmont	77:869cf507173a	817	((TIM_REMAP) == TIM10_RTC)\|\| \
emilmont	77:869cf507173a	818	((TIM_REMAP) == TIM10_RI)\|\| \
emilmont	77:869cf507173a	819	((TIM_REMAP) == TIM10_ETR_LSE)\|\| \
emilmont	77:869cf507173a	820	((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)\|\| \
emilmont	77:869cf507173a	821	((TIM_REMAP) == TIM11_GPIO)\|\| \
emilmont	77:869cf507173a	822	((TIM_REMAP) == TIM11_MSI)\|\| \
emilmont	77:869cf507173a	823	((TIM_REMAP) == TIM11_HSE_RTC)\|\| \
emilmont	77:869cf507173a	824	((TIM_REMAP) == TIM11_RI)\|\| \
emilmont	77:869cf507173a	825	((TIM_REMAP) == TIM11_ETR_LSE)\|\| \
emilmont	77:869cf507173a	826	((TIM_REMAP) == TIM11_ETR_TIM9_TRGO))
emilmont	77:869cf507173a	827
emilmont	77:869cf507173a	828	/**
emilmont	77:869cf507173a	829	* @}
emilmont	77:869cf507173a	830	*/
emilmont	77:869cf507173a	831
emilmont	77:869cf507173a	832	/** @defgroup TIM_Legacy
emilmont	77:869cf507173a	833	* @{
emilmont	77:869cf507173a	834	*/
emilmont	77:869cf507173a	835
emilmont	77:869cf507173a	836	#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
emilmont	77:869cf507173a	837	#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
emilmont	77:869cf507173a	838	#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
emilmont	77:869cf507173a	839	#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
emilmont	77:869cf507173a	840	#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
emilmont	77:869cf507173a	841	#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
emilmont	77:869cf507173a	842	#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
emilmont	77:869cf507173a	843	#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
emilmont	77:869cf507173a	844	#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
emilmont	77:869cf507173a	845	#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
emilmont	77:869cf507173a	846	#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
emilmont	77:869cf507173a	847	#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
emilmont	77:869cf507173a	848	#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
emilmont	77:869cf507173a	849	#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
emilmont	77:869cf507173a	850	#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
emilmont	77:869cf507173a	851	#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
emilmont	77:869cf507173a	852	#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
emilmont	77:869cf507173a	853	#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
emilmont	77:869cf507173a	854	/**
emilmont	77:869cf507173a	855	* @}
emilmont	77:869cf507173a	856	*/
emilmont	77:869cf507173a	857
emilmont	77:869cf507173a	858	/**
emilmont	77:869cf507173a	859	* @}
emilmont	77:869cf507173a	860	*/
emilmont	77:869cf507173a	861
emilmont	77:869cf507173a	862	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	863	/* Exported functions ------------------------------------------------------- */
emilmont	77:869cf507173a	864
emilmont	77:869cf507173a	865	/* TimeBase management ********************************************************/
emilmont	77:869cf507173a	866	void TIM_DeInit(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	867	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
emilmont	77:869cf507173a	868	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
emilmont	77:869cf507173a	869	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
emilmont	77:869cf507173a	870	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
emilmont	77:869cf507173a	871	void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
emilmont	77:869cf507173a	872	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
emilmont	77:869cf507173a	873	uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	874	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	875	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	876	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
emilmont	77:869cf507173a	877	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	878	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
emilmont	77:869cf507173a	879	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
emilmont	77:869cf507173a	880	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	881
emilmont	77:869cf507173a	882	/* Output Compare management **************************************************/
emilmont	77:869cf507173a	883	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	884	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	885	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	886	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	887	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
emilmont	77:869cf507173a	888	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
emilmont	77:869cf507173a	889	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
emilmont	77:869cf507173a	890	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
emilmont	77:869cf507173a	891	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
emilmont	77:869cf507173a	892	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
emilmont	77:869cf507173a	893	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	894	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	895	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	896	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
emilmont	77:869cf507173a	897	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	898	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	899	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	900	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
emilmont	77:869cf507173a	901	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	902	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	903	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	904	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
emilmont	77:869cf507173a	905	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	906	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	907	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	908	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
emilmont	77:869cf507173a	909	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	910	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	911	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	912	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
emilmont	77:869cf507173a	913	void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
emilmont	77:869cf507173a	914	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
emilmont	77:869cf507173a	915
emilmont	77:869cf507173a	916	/* Input Capture management ***************************************************/
emilmont	77:869cf507173a	917	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
emilmont	77:869cf507173a	918	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
emilmont	77:869cf507173a	919	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
emilmont	77:869cf507173a	920	uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	921	uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	922	uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	923	uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	924	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	925	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	926	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	927	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
emilmont	77:869cf507173a	928
emilmont	77:869cf507173a	929	/* Interrupts, DMA and flags management ***************************************/
emilmont	77:869cf507173a	930	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
emilmont	77:869cf507173a	931	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
emilmont	77:869cf507173a	932	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
emilmont	77:869cf507173a	933	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
emilmont	77:869cf507173a	934	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
emilmont	77:869cf507173a	935	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
emilmont	77:869cf507173a	936	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
emilmont	77:869cf507173a	937	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
emilmont	77:869cf507173a	938	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	939
emilmont	77:869cf507173a	940	/* Clocks management **********************************************************/
emilmont	77:869cf507173a	941	void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
emilmont	77:869cf507173a	942	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
emilmont	77:869cf507173a	943	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
emilmont	77:869cf507173a	944	uint16_t TIM_ICPolarity, uint16_t ICFilter);
emilmont	77:869cf507173a	945	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
emilmont	77:869cf507173a	946	uint16_t ExtTRGFilter);
emilmont	77:869cf507173a	947	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
emilmont	77:869cf507173a	948	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
emilmont	77:869cf507173a	949
emilmont	77:869cf507173a	950
emilmont	77:869cf507173a	951	/* Synchronization management *************************************************/
emilmont	77:869cf507173a	952	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
emilmont	77:869cf507173a	953	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
emilmont	77:869cf507173a	954	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
emilmont	77:869cf507173a	955	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
emilmont	77:869cf507173a	956	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
emilmont	77:869cf507173a	957	uint16_t ExtTRGFilter);
emilmont	77:869cf507173a	958
emilmont	77:869cf507173a	959	/* Specific interface management **********************************************/
emilmont	77:869cf507173a	960	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
emilmont	77:869cf507173a	961	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
emilmont	77:869cf507173a	962	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
emilmont	77:869cf507173a	963
emilmont	77:869cf507173a	964	/* Specific remapping management **********************************************/
emilmont	77:869cf507173a	965	void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap);
emilmont	77:869cf507173a	966
emilmont	77:869cf507173a	967
emilmont	77:869cf507173a	968	#ifdef __cplusplus
emilmont	77:869cf507173a	969	}
emilmont	77:869cf507173a	970	#endif
emilmont	77:869cf507173a	971
emilmont	77:869cf507173a	972	#endif /__STM32L1xx_TIM_H /
emilmont	77:869cf507173a	973
emilmont	77:869cf507173a	974	/**
emilmont	77:869cf507173a	975	* @}
emilmont	77:869cf507173a	976	*/
emilmont	77:869cf507173a	977
emilmont	77:869cf507173a	978	/**
emilmont	77:869cf507173a	979	* @}
emilmont	77:869cf507173a	980	*/
emilmont	77:869cf507173a	981
emilmont	77:869cf507173a	982	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/