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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L152RE/stm32l1xx_dma.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32l1xx_dma.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 31-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the DMA firmware
emilmont 77:869cf507173a 8 * library.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
emilmont 77:869cf507173a 12 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
emilmont 77:869cf507173a 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
emilmont 77:869cf507173a 15 * You may not use this file except in compliance with the License.
emilmont 77:869cf507173a 16 * You may obtain a copy of the License at:
emilmont 77:869cf507173a 17 *
emilmont 77:869cf507173a 18 * http://www.st.com/software_license_agreement_liberty_v2
emilmont 77:869cf507173a 19 *
emilmont 77:869cf507173a 20 * Unless required by applicable law or agreed to in writing, software
emilmont 77:869cf507173a 21 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 77:869cf507173a 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 77:869cf507173a 23 * See the License for the specific language governing permissions and
emilmont 77:869cf507173a 24 * limitations under the License.
emilmont 77:869cf507173a 25 *
emilmont 77:869cf507173a 26 ******************************************************************************
emilmont 77:869cf507173a 27 */
emilmont 77:869cf507173a 28
emilmont 77:869cf507173a 29 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 30 #ifndef __STM32L1xx_DMA_H
emilmont 77:869cf507173a 31 #define __STM32L1xx_DMA_H
emilmont 77:869cf507173a 32
emilmont 77:869cf507173a 33 #ifdef __cplusplus
emilmont 77:869cf507173a 34 extern "C" {
emilmont 77:869cf507173a 35 #endif
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 38 #include "stm32l1xx.h"
emilmont 77:869cf507173a 39
emilmont 77:869cf507173a 40 /** @addtogroup STM32L1xx_StdPeriph_Driver
emilmont 77:869cf507173a 41 * @{
emilmont 77:869cf507173a 42 */
emilmont 77:869cf507173a 43
emilmont 77:869cf507173a 44 /** @addtogroup DMA
emilmont 77:869cf507173a 45 * @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /**
emilmont 77:869cf507173a 51 * @brief DMA Init structure definition
emilmont 77:869cf507173a 52 */
emilmont 77:869cf507173a 53
emilmont 77:869cf507173a 54 typedef struct
emilmont 77:869cf507173a 55 {
emilmont 77:869cf507173a 56 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
emilmont 77:869cf507173a 61 This parameter can be a value of @ref DMA_data_transfer_direction */
emilmont 77:869cf507173a 62
emilmont 77:869cf507173a 63 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
emilmont 77:869cf507173a 64 The data unit is equal to the configuration set in DMA_PeripheralDataSize
emilmont 77:869cf507173a 65 or DMA_MemoryDataSize members depending in the transfer direction. */
emilmont 77:869cf507173a 66
emilmont 77:869cf507173a 67 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
emilmont 77:869cf507173a 68 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
emilmont 77:869cf507173a 69
emilmont 77:869cf507173a 70 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
emilmont 77:869cf507173a 71 This parameter can be a value of @ref DMA_memory_incremented_mode */
emilmont 77:869cf507173a 72
emilmont 77:869cf507173a 73 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
emilmont 77:869cf507173a 74 This parameter can be a value of @ref DMA_peripheral_data_size */
emilmont 77:869cf507173a 75
emilmont 77:869cf507173a 76 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
emilmont 77:869cf507173a 77 This parameter can be a value of @ref DMA_memory_data_size */
emilmont 77:869cf507173a 78
emilmont 77:869cf507173a 79 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
emilmont 77:869cf507173a 80 This parameter can be a value of @ref DMA_circular_normal_mode
emilmont 77:869cf507173a 81 @note: The circular buffer mode cannot be used if the memory-to-memory
emilmont 77:869cf507173a 82 data transfer is configured on the selected Channel */
emilmont 77:869cf507173a 83
emilmont 77:869cf507173a 84 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
emilmont 77:869cf507173a 85 This parameter can be a value of @ref DMA_priority_level */
emilmont 77:869cf507173a 86
emilmont 77:869cf507173a 87 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
emilmont 77:869cf507173a 88 This parameter can be a value of @ref DMA_memory_to_memory */
emilmont 77:869cf507173a 89 }DMA_InitTypeDef;
emilmont 77:869cf507173a 90
emilmont 77:869cf507173a 91 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 92
emilmont 77:869cf507173a 93 /** @defgroup DMA_Exported_Constants
emilmont 77:869cf507173a 94 * @{
emilmont 77:869cf507173a 95 */
emilmont 77:869cf507173a 96
emilmont 77:869cf507173a 97 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
emilmont 77:869cf507173a 98 ((PERIPH) == DMA1_Channel2) || \
emilmont 77:869cf507173a 99 ((PERIPH) == DMA1_Channel3) || \
emilmont 77:869cf507173a 100 ((PERIPH) == DMA1_Channel4) || \
emilmont 77:869cf507173a 101 ((PERIPH) == DMA1_Channel5) || \
emilmont 77:869cf507173a 102 ((PERIPH) == DMA1_Channel6) || \
emilmont 77:869cf507173a 103 ((PERIPH) == DMA1_Channel7) || \
emilmont 77:869cf507173a 104 ((PERIPH) == DMA2_Channel1) || \
emilmont 77:869cf507173a 105 ((PERIPH) == DMA2_Channel2) || \
emilmont 77:869cf507173a 106 ((PERIPH) == DMA2_Channel3) || \
emilmont 77:869cf507173a 107 ((PERIPH) == DMA2_Channel4) || \
emilmont 77:869cf507173a 108 ((PERIPH) == DMA2_Channel5))
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 /** @defgroup DMA_data_transfer_direction
emilmont 77:869cf507173a 111 * @{
emilmont 77:869cf507173a 112 */
emilmont 77:869cf507173a 113
emilmont 77:869cf507173a 114 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
emilmont 77:869cf507173a 115 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
emilmont 77:869cf507173a 116 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
emilmont 77:869cf507173a 117 ((DIR) == DMA_DIR_PeripheralSRC))
emilmont 77:869cf507173a 118 /**
emilmont 77:869cf507173a 119 * @}
emilmont 77:869cf507173a 120 */
emilmont 77:869cf507173a 121
emilmont 77:869cf507173a 122 /** @defgroup DMA_peripheral_incremented_mode
emilmont 77:869cf507173a 123 * @{
emilmont 77:869cf507173a 124 */
emilmont 77:869cf507173a 125
emilmont 77:869cf507173a 126 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
emilmont 77:869cf507173a 127 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 128 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
emilmont 77:869cf507173a 129 ((STATE) == DMA_PeripheralInc_Disable))
emilmont 77:869cf507173a 130 /**
emilmont 77:869cf507173a 131 * @}
emilmont 77:869cf507173a 132 */
emilmont 77:869cf507173a 133
emilmont 77:869cf507173a 134 /** @defgroup DMA_memory_incremented_mode
emilmont 77:869cf507173a 135 * @{
emilmont 77:869cf507173a 136 */
emilmont 77:869cf507173a 137
emilmont 77:869cf507173a 138 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
emilmont 77:869cf507173a 139 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 140 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
emilmont 77:869cf507173a 141 ((STATE) == DMA_MemoryInc_Disable))
emilmont 77:869cf507173a 142 /**
emilmont 77:869cf507173a 143 * @}
emilmont 77:869cf507173a 144 */
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 /** @defgroup DMA_peripheral_data_size
emilmont 77:869cf507173a 147 * @{
emilmont 77:869cf507173a 148 */
emilmont 77:869cf507173a 149
emilmont 77:869cf507173a 150 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
emilmont 77:869cf507173a 151 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
emilmont 77:869cf507173a 152 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
emilmont 77:869cf507173a 153 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
emilmont 77:869cf507173a 154 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
emilmont 77:869cf507173a 155 ((SIZE) == DMA_PeripheralDataSize_Word))
emilmont 77:869cf507173a 156 /**
emilmont 77:869cf507173a 157 * @}
emilmont 77:869cf507173a 158 */
emilmont 77:869cf507173a 159
emilmont 77:869cf507173a 160 /** @defgroup DMA_memory_data_size
emilmont 77:869cf507173a 161 * @{
emilmont 77:869cf507173a 162 */
emilmont 77:869cf507173a 163
emilmont 77:869cf507173a 164 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
emilmont 77:869cf507173a 165 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
emilmont 77:869cf507173a 166 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
emilmont 77:869cf507173a 167 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
emilmont 77:869cf507173a 168 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
emilmont 77:869cf507173a 169 ((SIZE) == DMA_MemoryDataSize_Word))
emilmont 77:869cf507173a 170 /**
emilmont 77:869cf507173a 171 * @}
emilmont 77:869cf507173a 172 */
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174 /** @defgroup DMA_circular_normal_mode
emilmont 77:869cf507173a 175 * @{
emilmont 77:869cf507173a 176 */
emilmont 77:869cf507173a 177
emilmont 77:869cf507173a 178 #define DMA_Mode_Circular ((uint32_t)0x00000020)
emilmont 77:869cf507173a 179 #define DMA_Mode_Normal ((uint32_t)0x00000000)
emilmont 77:869cf507173a 180 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
emilmont 77:869cf507173a 181 /**
emilmont 77:869cf507173a 182 * @}
emilmont 77:869cf507173a 183 */
emilmont 77:869cf507173a 184
emilmont 77:869cf507173a 185 /** @defgroup DMA_priority_level
emilmont 77:869cf507173a 186 * @{
emilmont 77:869cf507173a 187 */
emilmont 77:869cf507173a 188
emilmont 77:869cf507173a 189 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
emilmont 77:869cf507173a 190 #define DMA_Priority_High ((uint32_t)0x00002000)
emilmont 77:869cf507173a 191 #define DMA_Priority_Medium ((uint32_t)0x00001000)
emilmont 77:869cf507173a 192 #define DMA_Priority_Low ((uint32_t)0x00000000)
emilmont 77:869cf507173a 193 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
emilmont 77:869cf507173a 194 ((PRIORITY) == DMA_Priority_High) || \
emilmont 77:869cf507173a 195 ((PRIORITY) == DMA_Priority_Medium) || \
emilmont 77:869cf507173a 196 ((PRIORITY) == DMA_Priority_Low))
emilmont 77:869cf507173a 197 /**
emilmont 77:869cf507173a 198 * @}
emilmont 77:869cf507173a 199 */
emilmont 77:869cf507173a 200
emilmont 77:869cf507173a 201 /** @defgroup DMA_memory_to_memory
emilmont 77:869cf507173a 202 * @{
emilmont 77:869cf507173a 203 */
emilmont 77:869cf507173a 204
emilmont 77:869cf507173a 205 #define DMA_M2M_Enable ((uint32_t)0x00004000)
emilmont 77:869cf507173a 206 #define DMA_M2M_Disable ((uint32_t)0x00000000)
emilmont 77:869cf507173a 207 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
emilmont 77:869cf507173a 208
emilmont 77:869cf507173a 209 /**
emilmont 77:869cf507173a 210 * @}
emilmont 77:869cf507173a 211 */
emilmont 77:869cf507173a 212
emilmont 77:869cf507173a 213 /** @defgroup DMA_interrupts_definition
emilmont 77:869cf507173a 214 * @{
emilmont 77:869cf507173a 215 */
emilmont 77:869cf507173a 216
emilmont 77:869cf507173a 217 #define DMA_IT_TC ((uint32_t)0x00000002)
emilmont 77:869cf507173a 218 #define DMA_IT_HT ((uint32_t)0x00000004)
emilmont 77:869cf507173a 219 #define DMA_IT_TE ((uint32_t)0x00000008)
emilmont 77:869cf507173a 220 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
emilmont 77:869cf507173a 221
emilmont 77:869cf507173a 222 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 223 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 224 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 225 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 226 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 227 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 228 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 229 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 230 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 231 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 232 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 233 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 234 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 235 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 236 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 237 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 238 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 239 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 240 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 241 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 242 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 243 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 244 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 245 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 246 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 247 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 248 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 249 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 250
emilmont 77:869cf507173a 251 #define DMA2_IT_GL1 ((uint32_t)0x10000001)
emilmont 77:869cf507173a 252 #define DMA2_IT_TC1 ((uint32_t)0x10000002)
emilmont 77:869cf507173a 253 #define DMA2_IT_HT1 ((uint32_t)0x10000004)
emilmont 77:869cf507173a 254 #define DMA2_IT_TE1 ((uint32_t)0x10000008)
emilmont 77:869cf507173a 255 #define DMA2_IT_GL2 ((uint32_t)0x10000010)
emilmont 77:869cf507173a 256 #define DMA2_IT_TC2 ((uint32_t)0x10000020)
emilmont 77:869cf507173a 257 #define DMA2_IT_HT2 ((uint32_t)0x10000040)
emilmont 77:869cf507173a 258 #define DMA2_IT_TE2 ((uint32_t)0x10000080)
emilmont 77:869cf507173a 259 #define DMA2_IT_GL3 ((uint32_t)0x10000100)
emilmont 77:869cf507173a 260 #define DMA2_IT_TC3 ((uint32_t)0x10000200)
emilmont 77:869cf507173a 261 #define DMA2_IT_HT3 ((uint32_t)0x10000400)
emilmont 77:869cf507173a 262 #define DMA2_IT_TE3 ((uint32_t)0x10000800)
emilmont 77:869cf507173a 263 #define DMA2_IT_GL4 ((uint32_t)0x10001000)
emilmont 77:869cf507173a 264 #define DMA2_IT_TC4 ((uint32_t)0x10002000)
emilmont 77:869cf507173a 265 #define DMA2_IT_HT4 ((uint32_t)0x10004000)
emilmont 77:869cf507173a 266 #define DMA2_IT_TE4 ((uint32_t)0x10008000)
emilmont 77:869cf507173a 267 #define DMA2_IT_GL5 ((uint32_t)0x10010000)
emilmont 77:869cf507173a 268 #define DMA2_IT_TC5 ((uint32_t)0x10020000)
emilmont 77:869cf507173a 269 #define DMA2_IT_HT5 ((uint32_t)0x10040000)
emilmont 77:869cf507173a 270 #define DMA2_IT_TE5 ((uint32_t)0x10080000)
emilmont 77:869cf507173a 271
emilmont 77:869cf507173a 272 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
emilmont 77:869cf507173a 273
emilmont 77:869cf507173a 274 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
emilmont 77:869cf507173a 275 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
emilmont 77:869cf507173a 276 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
emilmont 77:869cf507173a 277 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
emilmont 77:869cf507173a 278 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
emilmont 77:869cf507173a 279 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
emilmont 77:869cf507173a 280 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
emilmont 77:869cf507173a 281 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
emilmont 77:869cf507173a 282 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
emilmont 77:869cf507173a 283 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
emilmont 77:869cf507173a 284 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
emilmont 77:869cf507173a 285 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
emilmont 77:869cf507173a 286 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
emilmont 77:869cf507173a 287 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
emilmont 77:869cf507173a 288 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
emilmont 77:869cf507173a 289 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
emilmont 77:869cf507173a 290 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
emilmont 77:869cf507173a 291 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
emilmont 77:869cf507173a 292 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
emilmont 77:869cf507173a 293 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
emilmont 77:869cf507173a 294 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
emilmont 77:869cf507173a 295 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
emilmont 77:869cf507173a 296 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
emilmont 77:869cf507173a 297 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
emilmont 77:869cf507173a 298 /**
emilmont 77:869cf507173a 299 * @}
emilmont 77:869cf507173a 300 */
emilmont 77:869cf507173a 301
emilmont 77:869cf507173a 302 /** @defgroup DMA_flags_definition
emilmont 77:869cf507173a 303 * @{
emilmont 77:869cf507173a 304 */
emilmont 77:869cf507173a 305 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 306 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 307 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 308 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 309 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 310 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 311 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 312 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 313 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 314 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 315 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 316 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 317 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 318 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 319 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 320 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 321 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 322 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 323 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 324 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 325 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 326 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 327 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 328 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 329 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 330 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 331 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 332 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 333
emilmont 77:869cf507173a 334 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
emilmont 77:869cf507173a 335 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
emilmont 77:869cf507173a 336 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
emilmont 77:869cf507173a 337 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
emilmont 77:869cf507173a 338 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
emilmont 77:869cf507173a 339 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
emilmont 77:869cf507173a 340 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
emilmont 77:869cf507173a 341 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
emilmont 77:869cf507173a 342 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
emilmont 77:869cf507173a 343 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
emilmont 77:869cf507173a 344 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
emilmont 77:869cf507173a 345 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
emilmont 77:869cf507173a 346 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
emilmont 77:869cf507173a 347 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
emilmont 77:869cf507173a 348 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
emilmont 77:869cf507173a 349 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
emilmont 77:869cf507173a 350 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
emilmont 77:869cf507173a 351 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
emilmont 77:869cf507173a 352 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
emilmont 77:869cf507173a 353 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
emilmont 77:869cf507173a 354
emilmont 77:869cf507173a 355 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
emilmont 77:869cf507173a 356
emilmont 77:869cf507173a 357 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
emilmont 77:869cf507173a 358 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
emilmont 77:869cf507173a 359 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
emilmont 77:869cf507173a 360 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
emilmont 77:869cf507173a 361 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
emilmont 77:869cf507173a 362 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
emilmont 77:869cf507173a 363 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
emilmont 77:869cf507173a 364 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
emilmont 77:869cf507173a 365 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
emilmont 77:869cf507173a 366 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
emilmont 77:869cf507173a 367 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
emilmont 77:869cf507173a 368 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
emilmont 77:869cf507173a 369 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
emilmont 77:869cf507173a 370 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
emilmont 77:869cf507173a 371 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
emilmont 77:869cf507173a 372 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
emilmont 77:869cf507173a 373 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
emilmont 77:869cf507173a 374 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
emilmont 77:869cf507173a 375 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
emilmont 77:869cf507173a 376 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
emilmont 77:869cf507173a 377 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
emilmont 77:869cf507173a 378 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
emilmont 77:869cf507173a 379 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
emilmont 77:869cf507173a 380 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
emilmont 77:869cf507173a 381 /**
emilmont 77:869cf507173a 382 * @}
emilmont 77:869cf507173a 383 */
emilmont 77:869cf507173a 384
emilmont 77:869cf507173a 385 /** @defgroup DMA_Buffer_Size
emilmont 77:869cf507173a 386 * @{
emilmont 77:869cf507173a 387 */
emilmont 77:869cf507173a 388
emilmont 77:869cf507173a 389 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
emilmont 77:869cf507173a 390
emilmont 77:869cf507173a 391 /**
emilmont 77:869cf507173a 392 * @}
emilmont 77:869cf507173a 393 */
emilmont 77:869cf507173a 394
emilmont 77:869cf507173a 395 /**
emilmont 77:869cf507173a 396 * @}
emilmont 77:869cf507173a 397 */
emilmont 77:869cf507173a 398
emilmont 77:869cf507173a 399 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 400 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 401
emilmont 77:869cf507173a 402 /* Function used to set the DMA configuration to the default reset state *****/
emilmont 77:869cf507173a 403 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
emilmont 77:869cf507173a 404
emilmont 77:869cf507173a 405 /* Initialization and Configuration functions *********************************/
emilmont 77:869cf507173a 406 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
emilmont 77:869cf507173a 407 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
emilmont 77:869cf507173a 408 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
emilmont 77:869cf507173a 409
emilmont 77:869cf507173a 410 /* Data Counter functions *****************************************************/
emilmont 77:869cf507173a 411 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
emilmont 77:869cf507173a 412 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
emilmont 77:869cf507173a 413
emilmont 77:869cf507173a 414 /* Interrupts and flags management functions **********************************/
emilmont 77:869cf507173a 415 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
emilmont 77:869cf507173a 416 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
emilmont 77:869cf507173a 417 void DMA_ClearFlag(uint32_t DMAy_FLAG);
emilmont 77:869cf507173a 418 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
emilmont 77:869cf507173a 419 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
emilmont 77:869cf507173a 420
emilmont 77:869cf507173a 421 #ifdef __cplusplus
emilmont 77:869cf507173a 422 }
emilmont 77:869cf507173a 423 #endif
emilmont 77:869cf507173a 424
emilmont 77:869cf507173a 425 #endif /*__STM32L1xx_DMA_H */
emilmont 77:869cf507173a 426
emilmont 77:869cf507173a 427 /**
emilmont 77:869cf507173a 428 * @}
emilmont 77:869cf507173a 429 */
emilmont 77:869cf507173a 430
emilmont 77:869cf507173a 431 /**
emilmont 77:869cf507173a 432 * @}
emilmont 77:869cf507173a 433 */
emilmont 77:869cf507173a 434
emilmont 77:869cf507173a 435 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/