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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.
Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.
If you are looking for a stable and tested release, please import one of the official mbed library releases:
Import librarymbed
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Last commit 20 Feb 2019 by 
mbed official
Revision 579:53297373a894, committed 2015-07-01
- Comitter:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Parent:
- 578:dd2bc6eabbef
- Child:
- 580:3c14cb9b87c5
- Commit message:
- Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,201 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD21
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21j18a.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+ (void*) (&_estack),
+
+ (void*) Reset_Handler,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
+ (void*) AC_Handler, /* 24 Analog Comparators */
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+ (void*) I2S_Handler /* 27 Inter-IC Sound Interface */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+
+ /* Initialize the relocate segment */
+ pSrc = &_etext;
+ pDest = &_srelocate;
+
+ if (pSrc != pDest) {
+ for (; pDest < &_erelocate;) {
+ *pDest++ = *pSrc++;
+ }
+ }
+
+ /* Clear the zero segment */
+ for (pDest = &_szero; pDest < &_ezero;) {
+ *pDest++ = 0;
+ }
+
+ /* Set the vector table base address */
+ pSrc = (uint32_t *) & _sfixed;
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+ /* Initialize the C library */
+ __libc_init_array();
+
+ /* Branch to main function */ // expected to be done by MBED OS
+ main();
+
+ /* Infinite loop */
+ while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ while (1) {
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,214 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+void Dummy_Handler(void);
+void Reset_Handler(void);
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ while (1) {
+ }
+}
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/* Cortex-M0+ core handlers */
+#pragma weak NMI_Handler = Dummy_Handler
+#pragma weak HardFault_Handler = Dummy_Handler
+#pragma weak SVC_Handler = Dummy_Handler
+#pragma weak PendSV_Handler = Dummy_Handler
+#pragma weak SysTick_Handler = Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak PM_Handler = Dummy_Handler
+#pragma weak SYSCTRL_Handler = Dummy_Handler
+#pragma weak WDT_Handler = Dummy_Handler
+#pragma weak RTC_Handler = Dummy_Handler
+#pragma weak EIC_Handler = Dummy_Handler
+#pragma weak NVMCTRL_Handler = Dummy_Handler
+#pragma weak DMAC_Handler = Dummy_Handler
+#pragma weak USB_Handler = Dummy_Handler
+#pragma weak EVSYS_Handler = Dummy_Handler
+#pragma weak SERCOM0_Handler = Dummy_Handler
+#pragma weak SERCOM1_Handler = Dummy_Handler
+#pragma weak SERCOM2_Handler = Dummy_Handler
+#pragma weak SERCOM3_Handler = Dummy_Handler
+#pragma weak SERCOM4_Handler = Dummy_Handler
+#pragma weak SERCOM5_Handler = Dummy_Handler
+#pragma weak TCC0_Handler = Dummy_Handler
+#pragma weak TCC1_Handler = Dummy_Handler
+#pragma weak TCC2_Handler = Dummy_Handler
+#pragma weak TC3_Handler = Dummy_Handler
+#pragma weak TC4_Handler = Dummy_Handler
+#pragma weak TC5_Handler = Dummy_Handler
+#pragma weak TC6_Handler = Dummy_Handler
+#pragma weak TC7_Handler = Dummy_Handler
+#pragma weak ADC_Handler = Dummy_Handler
+#pragma weak AC_Handler = Dummy_Handler
+#pragma weak DAC_Handler = Dummy_Handler
+#pragma weak PTC_Handler = Dummy_Handler
+#pragma weak I2S_Handler = Dummy_Handler
+
+/* Exception Table */
+#pragma language=extended
+#pragma segment="CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+//! [startup_vector_table]
+const DeviceVectors __vector_table[] = {
+ __sfe("CSTACK"),
+ (void*) Reset_Handler,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
+ (void*) AC_Handler, /* 24 Analog Comparators */
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+ (void*) I2S_Handler /* 27 Inter-IC Sound Interface */
+};
+//! [startup_vector_table]
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+ uint32_t *pSrc = __section_begin(".intvec");
+
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+ return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __iar_program_start();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in samd21j18a specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "samd21j18a.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 +29) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,81 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+//#include "samd21.h"
+#include "samd21j18a.h"
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ * the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+ // Keep the default device state after reset
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+ // Not implemented
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,65 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SYSTEM_SAMD21_H_INCLUDED_
+#define _SYSTEM_SAMD21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD21_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,170 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMR21G18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .dvectors (NOLOAD) :
+ {
+ _sdvectors = .;
+ . = . + 0xB0;
+ _edvectors = .;
+ } > ram
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __end__ = . ;
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,258 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMR21
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "samr21g18a.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef USB_IRQn
+void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef SERCOM4_IRQn
+void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef SERCOM5_IRQn
+void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef TC6_IRQn
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef TC7_IRQn
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ADC_IRQn
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef AC_IRQn
+void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef DAC_IRQn
+void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef PTC_IRQn
+void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+ (void*) (&_estack),
+
+ (void*) Reset_Handler,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+#ifdef USB_IRQn
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+#ifdef SERCOM4_IRQn
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef SERCOM5_IRQn
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+#ifdef TC6_IRQn
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef TC7_IRQn
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ADC_IRQn
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef AC_IRQn
+ (void*) AC_Handler, /* 24 Analog Comparators */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef DAC_IRQn
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef PTC_IRQn
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+ (void*) I2S_Handler /* 27 Inter-IC Sound Interface */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+
+ /* Initialize the relocate segment */
+ pSrc = &_etext;
+ pDest = &_srelocate;
+
+ if (pSrc != pDest) {
+ for (; pDest < &_erelocate;) {
+ *pDest++ = *pSrc++;
+ }
+ }
+
+ /* Clear the zero segment */
+ for (pDest = &_szero; pDest < &_ezero;) {
+ *pDest++ = 0;
+ }
+
+ /* Set the vector table base address */
+ pSrc = (uint32_t *) & _sfixed;
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+ /* Initialize the C library */
+ __libc_init_array();
+
+ /* Branch to main function */
+ main();
+
+ /* Infinite loop */
+ while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ while (1) {
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in samr21j18a specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "samr21g18a.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+//#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+extern uint32_t _sdvectors;
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)&_sdvectors;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)&_sdvectors;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 +28) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,81 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "samr21g18a.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ * the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+ // Keep the default device state after reset
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+ // Not implemented
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,65 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SYSTEM_SAMR21_H_INCLUDED_
+#define _SYSTEM_SAMR21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMR21_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_ac.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,562 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_AC_COMPONENT_
+#define _SAMD21_AC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC 0x111
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
+#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
+#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
+#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
+#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
+#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
+#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
+#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
+#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
+#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
+#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
+#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
+#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
+#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */
+#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */
+#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
+#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE 0x00ul /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
+#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
+#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */
+#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */
+#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK 0x33ul /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
+#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
+#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */
+#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
+#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
+#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */
+#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */
+#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
+#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
+#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
+#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */
+#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK 0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
+#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_AC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,702 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_ADC_COMPONENT_
+#define _SAMD21_ADC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC 0x120
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
+#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
+#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */
+#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */
+#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */
+#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */
+#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */
+#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */
+#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */
+#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */
+#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */
+#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
+#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
+#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
+#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */
+#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */
+#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */
+#define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
+#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
+#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
+#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
+#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
+#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
+#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */
+#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */
+#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */
+#define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */
+#define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */
+#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
+#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
+#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
+#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
+#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
+#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
+#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
+#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_ADC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,289 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_DAC_COMPONENT_
+#define _SAMD21_DAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC 0x110
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
+ uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
+ uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
+ uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
+ uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
+#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
+#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */
+#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
+ uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
+#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
+#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
+#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
+ RoReg8 Reserved2[0x2];
+ __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DAC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1089 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_DMAC_COMPONENT_
+#define _SAMD21_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2223
+#define REV_DMAC 0x100
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
+#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)))
+#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)))
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)))
+#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)))
+#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */
+#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)))
+#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)))
+#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
+ uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */
+#define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
+
+#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
+#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS(value) ((DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)))
+#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
+#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS(value) ((DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)))
+#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
+#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS(value) ((DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)))
+#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)))
+#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)))
+#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)))
+#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)))
+#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)))
+#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)))
+#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)))
+#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)))
+#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)))
+#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)))
+#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
+#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */
+
+#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
+#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)))
+#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+
+#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
+#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)))
+#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
+#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
+#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
+#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)))
+#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */
+#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)))
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
+#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)))
+#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)))
+#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
+#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+
+#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
+#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)))
+#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)))
+#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
+#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)))
+#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)))
+#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */
+#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */
+#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */
+#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */
+#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */
+#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */
+#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */
+#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)))
+#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)))
+#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
+
+#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)))
+#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)))
+#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
+ RoReg8 Reserved1[0x1];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x3];
+ __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
+ RoReg8 Reserved5[0x3];
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+ RoReg8 Reserved6[0x4];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
+ __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+__attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_DMAC_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAMD21_DMAC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,554 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_DSU_COMPONENT_
+#define _SAMD21_DSU_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU 0x200
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
+ uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
+#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
+#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
+#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAILURE:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
+#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
+#define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
+#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
+#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
+#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
+ uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
+#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
+#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
+#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
+#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
+#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
+#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
+#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
+#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
+#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
+#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ENTRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+
+#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
+#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
+#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
+#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
+#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
+#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
+#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
+#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
+#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
+#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
+#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
+#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
+#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
+#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
+#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
+#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
+#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
+#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
+#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
+#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
+#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
+#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ RoReg8 Reserved2[0xFE4];
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
+ RoReg8 Reserved3[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ RoReg8 Reserved4[0xC];
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DSU_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_EIC_COMPONENT_
+#define _SAMD21_EIC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2217
+#define REV_EIC 0x101
+
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
+#define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */
+
+#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
+#define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
+#define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */
+
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
+#define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */
+
+#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
+#define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
+#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))
+#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */
+#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */
+#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
+ uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
+ uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
+ uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
+ uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
+ uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
+ uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
+ uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
+ uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
+ uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
+ uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
+ uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
+ uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
+ uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
+ uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
+ uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
+#define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
+#define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
+#define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
+#define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
+#define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
+#define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
+#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
+#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
+#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
+#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
+#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
+#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
+#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
+#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
+#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
+#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))
+#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
+#define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
+#define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
+#define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
+#define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
+#define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
+#define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
+#define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
+#define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
+#define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
+#define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
+#define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
+#define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
+#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
+#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
+#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
+#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
+#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
+#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
+#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
+#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
+#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
+#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
+#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
+#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
+#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
+#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
+#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
+#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
+#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
+#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
+#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
+#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
+#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))
+#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
+#define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
+#define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
+#define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
+#define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
+#define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
+#define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
+#define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
+#define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
+#define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
+#define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
+#define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
+#define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
+#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
+#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
+#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
+#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
+#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
+#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
+#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
+#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
+#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
+#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
+#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
+#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
+#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
+#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
+#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
+#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
+#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
+#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
+#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
+#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
+#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))
+#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
+#define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
+#define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
+#define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
+#define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
+#define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
+#define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
+#define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
+#define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
+#define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
+#define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
+#define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
+#define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
+#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
+#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
+#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
+#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
+#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
+#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
+#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
+#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
+#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
+#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
+#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
+#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
+#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
+#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
+#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
+#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
+#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
+#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
+#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
+#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
+#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))
+#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
+ uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
+ uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
+ uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
+ uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
+ uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
+ uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
+ uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
+ uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
+ uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
+ uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
+ uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
+ uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
+ uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
+ uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
+ uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_WAKEUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+
+#define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
+#define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
+#define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
+#define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
+#define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
+#define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
+#define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
+#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
+#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
+#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
+#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
+#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
+#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
+#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
+#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
+#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))
+#define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
+#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))
+#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */
+#define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */
+#define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */
+#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
+#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
+#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))
+#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
+#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
+#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))
+#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
+#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
+#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))
+#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
+#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
+#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))
+#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
+#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
+#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))
+#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
+#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
+#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))
+#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
+#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
+#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))
+#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
+#define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EIC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,607 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_EVSYS_COMPONENT_
+#define _SAMD21_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS 0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
+#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
+#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
+#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
+#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
+ uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
+ uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
+ uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
+ uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
+ uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
+ uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
+ uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
+ uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
+ uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
+ uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
+ uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
+ uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
+ uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
+ uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
+ uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
+ uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
+ uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
+ uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
+ uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
+ uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
+ uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
+ uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
+ uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
+ uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
+#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
+#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
+#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
+#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
+#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
+#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
+#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
+#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
+#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
+#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
+#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
+#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
+#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
+#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
+#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
+#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
+#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+ RoReg8 Reserved2[0x2];
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,313 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_GCLK_COMPONENT_
+#define _SAMD21_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMD21_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2102
+#define REV_GCLK 0x210
+
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
+#define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */
+
+#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
+#define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */
+
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
+#define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */
+
+#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
+#define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */
+
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} GCLK_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+
+#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
+#define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
+#define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */
+#define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */
+#define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */
+#define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */
+#define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */
+#define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */
+#define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */
+#define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
+#define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
+#define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
+#define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
+#define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
+#define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
+#define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
+#define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
+#define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
+#define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
+#define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
+#define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
+#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
+#define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
+#define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
+#define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
+#define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */
+#define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */
+#define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */
+#define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */
+#define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */
+#define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */
+#define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */
+#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
+#define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
+#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
+#define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
+#define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SRC:5; /*!< bit: 8..12 Source Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */
+ uint32_t OE:1; /*!< bit: 19 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
+#define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
+#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
+#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */
+#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+
+#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
+#define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
+#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
+#define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
+#define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_GCLK_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_hmatrixb.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,121 @@
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_HMATRIXB_COMPONENT_
+#define _SAMD21_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB 0x212
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_SFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */
+#define HMATRIXB_SFR_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */
+
+#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
+#define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
+#define HMATRIXB_SFR_SFR(value) ((HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos)))
+#define HMATRIXB_SFR_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+ RoReg8 Reserved2[0x10];
+ __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,642 @@
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_I2S_COMPONENT_
+#define _SAMD21_I2S_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S 0x102
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
+ uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
+ uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
+ uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
+ uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE 0x00ul /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST (0x1ul << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE (0x1ul << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk (0x3ul << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
+#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
+#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
+#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
+#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
+#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
+#define I2S_CTRLA_SEREN_Msk (0x3ul << I2S_CTRLA_SEREN_Pos)
+#define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
+#define I2S_CTRLA_MASK 0x3Ful /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
+ uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
+ uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
+ uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
+ uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
+ uint32_t :2; /*!< bit: 9..10 Reserved */
+ uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
+ uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
+ uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
+ uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
+ uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
+ uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
+ uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
+#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0ul /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1ul /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2ul /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3ul /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
+#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
+#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3ul /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0ul /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1ul /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV (0x1ul << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0ul /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
+#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MASK 0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE 0x0000ul /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk (0x3ul << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
+#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk (0x3ul << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
+#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk (0x3ul << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
+#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk (0x3ul << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
+#define I2S_INTENCLR_MASK 0x3333ul /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE 0x0000ul /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk (0x3ul << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
+#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk (0x3ul << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
+#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk (0x3ul << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
+#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk (0x3ul << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
+#define I2S_INTENSET_MASK 0x3333ul /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE 0x0000ul /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk (0x3ul << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
+#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk (0x3ul << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
+#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk (0x3ul << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
+#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk (0x3ul << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
+#define I2S_INTFLAG_MASK 0x3333ul /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
+ uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
+ uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
+ uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
+ uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
+ uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
+ uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
+#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
+#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
+#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN_Msk (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
+#define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
+#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
+#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
+#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
+#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
+#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
+#define I2S_SYNCBUSY_DATA_Msk (0x3ul << I2S_SYNCBUSY_DATA_Pos)
+#define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
+#define I2S_SYNCBUSY_MASK 0x033Ful /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
+ uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
+ uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
+ uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_SERCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
+#define I2S_SERCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
+
+#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
+#define I2S_SERCTRL_SERMODE_Msk (0x3ul << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
+#define I2S_SERCTRL_SERMODE_RX_Val 0x0ul /**< \brief (I2S_SERCTRL) Receive */
+#define I2S_SERCTRL_SERMODE_TX_Val 0x1ul /**< \brief (I2S_SERCTRL) Transmit */
+#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2ul /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
+#define I2S_SERCTRL_TXDEFAULT_Msk (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
+#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
+#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
+#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3ul /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
+#define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
+#define I2S_SERCTRL_TXSAME (0x1ul << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_SAME_Val 0x1ul /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
+#define I2S_SERCTRL_CLKSEL (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0ul /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
+#define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1ul /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
+#define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
+#define I2S_SERCTRL_SLOTADJ (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
+#define I2S_SERCTRL_DATASIZE_Msk (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
+#define I2S_SERCTRL_DATASIZE_32_Val 0x0ul /**< \brief (I2S_SERCTRL) 32 bits */
+#define I2S_SERCTRL_DATASIZE_24_Val 0x1ul /**< \brief (I2S_SERCTRL) 24 bits */
+#define I2S_SERCTRL_DATASIZE_20_Val 0x2ul /**< \brief (I2S_SERCTRL) 20 bits */
+#define I2S_SERCTRL_DATASIZE_18_Val 0x3ul /**< \brief (I2S_SERCTRL) 18 bits */
+#define I2S_SERCTRL_DATASIZE_16_Val 0x4ul /**< \brief (I2S_SERCTRL) 16 bits */
+#define I2S_SERCTRL_DATASIZE_16C_Val 0x5ul /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_8_Val 0x6ul /**< \brief (I2S_SERCTRL) 8 bits */
+#define I2S_SERCTRL_DATASIZE_8C_Val 0x7ul /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
+#define I2S_SERCTRL_WORDADJ (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
+#define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
+#define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
+#define I2S_SERCTRL_EXTEND_Msk (0x3ul << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
+#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Extend with zeroes */
+#define I2S_SERCTRL_EXTEND_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Extend with ones */
+#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2ul /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
+#define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3ul /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
+#define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
+#define I2S_SERCTRL_BITREV (0x1ul << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_MSBIT_Val 0x0ul /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define I2S_SERCTRL_BITREV_LSBIT_Val 0x1ul /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
+#define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
+#define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
+#define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
+#define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
+#define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
+#define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
+#define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
+#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS_Msk (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
+#define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
+#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
+#define I2S_SERCTRL_MONO (0x1ul << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_STEREO_Val 0x0ul /**< \brief (I2S_SERCTRL) Normal mode */
+#define I2S_SERCTRL_MONO_MONO_Val 0x1ul /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
+#define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
+#define I2S_SERCTRL_DMA (0x1ul << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_SINGLE_Val 0x0ul /**< \brief (I2S_SERCTRL) Single DMA channel */
+#define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1ul /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
+#define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
+#define I2S_SERCTRL_RXLOOP (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
+#define I2S_SERCTRL_MASK 0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
+
+/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
+#define I2S_DATA_RESETVALUE 0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
+
+#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
+#define I2S_DATA_DATA_Msk (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
+#define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
+#define I2S_DATA_MASK 0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+ __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x2];
+ __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+ RoReg8 Reserved3[0x2];
+ __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x2];
+ __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
+ RoReg8 Reserved5[0x6];
+ __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+ RoReg8 Reserved6[0x8];
+ __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_I2S_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,399 @@
+/**
+ * \file
+ *
+ * \brief Component description for MTB
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_MTB_COMPONENT_
+#define _SAMD21_MTB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR MTB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
+/*@{*/
+
+#define MTB_U2002
+#define REV_MTB 0x100
+
+/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
+ uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_POSITION_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
+
+#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
+#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
+#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
+#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
+
+/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
+ uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
+ uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
+ uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
+ uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
+ uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_MASTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
+#define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
+
+#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
+#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
+#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
+#define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
+#define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
+#define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
+
+/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
+ uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_FLOW_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
+#define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
+
+#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
+#define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
+#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
+#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
+#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
+
+/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_BASE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
+#define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
+
+/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_ITCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
+#define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
+
+/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CLAIMSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
+#define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
+
+/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CLAIMCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
+#define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
+
+/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_LOCKACCESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
+#define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
+
+/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_LOCKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
+#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
+
+/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_AUTHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
+#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
+
+/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVARCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
+#define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
+
+/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
+#define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
+
+/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
+#define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
+
+/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
+#define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
+
+/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
+#define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
+
+/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
+#define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
+
+/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
+#define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
+
+/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
+#define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
+
+/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
+#define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
+
+/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
+#define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
+
+/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
+#define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
+
+/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
+#define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
+
+/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
+#define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
+
+/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
+#define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
+
+/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
+#define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
+
+/** \brief MTB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+ __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+ __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+ __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
+ RoReg8 Reserved1[0xEF0];
+ __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+ RoReg8 Reserved2[0x9C];
+ __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+ __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+ RoReg8 Reserved3[0x8];
+ __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+ __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
+ __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
+ __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
+ RoReg8 Reserved4[0x8];
+ __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
+ __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
+ __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
+ __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
+ __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
+ __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
+ __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
+ __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
+ __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
+ __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
+ __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
+ __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
+ __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
+ __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
+} Mtb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_MTB_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,610 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_NVMCTRL_COMPONENT_
+#define _SAMD21_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL 0x106
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))
+#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))
+#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))
+#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))
+#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))
+#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready */
+ uint8_t ERROR:1; /*!< bit: 1 Error */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))
+#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))
+#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x3];
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
+ RoReg8 Reserved3[0x3];
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x3];
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
+ RoReg8 Reserved5[0x2];
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_NVMCTRL_CAL
+#define SECTION_NVMCTRL_LOCKBIT
+#define SECTION_NVMCTRL_OTP1
+#define SECTION_NVMCTRL_OTP2
+#define SECTION_NVMCTRL_OTP4
+#define SECTION_NVMCTRL_TEMP_LOG
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))
+
+#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))
+
+#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))
+
+#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)))
+
+#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)))
+
+#define FUSES_BOD33_EN_ADDR NVMCTRL_USER
+#define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos)
+
+#define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL(value) ((FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos)))
+
+#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
+#define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
+#define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL(value) ((FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos)))
+
+#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL(value) ((FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos)))
+
+#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value) ((FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) ((FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos)))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) ((FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos)))
+
+#define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos)
+#define FUSES_OSC32K_CAL(value) ((FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos)))
+
+#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL(value) ((FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos)))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) ((FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos)))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) ((FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos)))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) ((FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos)))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))
+
+/* Compabible definition for previous driver (begin 1) */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
+/* Compabible definition for previous driver (end 1) */
+
+#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
+#define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos)
+#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))
+
+#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
+#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
+#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))
+
+#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
+#define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos)
+#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))
+
+/* Compabible definition for previous driver (begin 2) */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
+
+#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
+#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
+#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define SYSCTRL_FUSES_BOD33_EN_Msk (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
+
+#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
+#define SYSCTRL_FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
+
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
+
+#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
+#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
+/* Compabible definition for previous driver (end 2) */
+
+#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)))
+
+#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)))
+
+#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)))
+
+#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))
+
+#define WDT_FUSES_PER_ADDR NVMCTRL_USER
+#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))
+
+#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))
+
+/*@}*/
+
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pac.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,107 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_PAC_COMPONENT_
+#define _SAMD21_PAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2211
+#define REV_PAC 0x101
+
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WPCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE 0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+
+#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
+#define PAC_WPCLR_WP_Msk (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP(value) ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)))
+#define PAC_WPCLR_MASK 0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
+
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WPSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */
+#define PAC_WPSET_RESETVALUE 0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+
+#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
+#define PAC_WPSET_WP_Msk (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP(value) ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)))
+#define PAC_WPSET_MASK 0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PAC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,536 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_PM_COMPONENT_
+#define _SAMD21_PM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM 0x201
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint8_t reg; /*!< Type used for register access */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
+#define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
+#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */
+#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */
+#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */
+#define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */
+#define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */
+#define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */
+#define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */
+#define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
+#define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */
+#define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */
+#define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */
+#define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */
+#define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */
+#define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */
+#define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */
+#define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
+#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */
+#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */
+#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */
+#define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */
+#define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */
+#define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */
+#define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */
+#define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
+#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */
+#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */
+#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */
+#define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */
+#define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */
+#define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */
+#define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */
+#define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
+#define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
+#define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
+ uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
+ uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
+#define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
+#define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
+#define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos)
+#define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
+ uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
+ uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
+ uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
+ uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
+ uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
+ uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
+ uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
+ uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
+#define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
+#define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
+#define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6 (0x1ul << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7 (0x1ul << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC (0x1ul << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
+#define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_MASK 0x001FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
+ uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
+ RoReg8 Reserved1[0x6];
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
+ RoReg8 Reserved2[0x8];
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+ RoReg8 Reserved3[0x10];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PM_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,398 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_PORT_COMPONENT_
+#define _SAMD21_PORT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT 0x100
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
+#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
+#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
+#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
+#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
+#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
+#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
+#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
+#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
+#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
+#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
+#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
+#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
+#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
+#define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define PORT_PMUX_PMUXE_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define PORT_PMUX_PMUXE_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define PORT_PMUX_PMUXE_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define PORT_PMUX_PMUXE_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define PORT_PMUX_PMUXE_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
+#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
+#define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define PORT_PMUX_PMUXO_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define PORT_PMUX_PMUXO_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define PORT_PMUX_PMUXO_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define PORT_PMUX_PMUXO_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define PORT_PMUX_PMUXO_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ RoReg8 Reserved1[0x4];
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
+ RoReg8 Reserved2[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_PORT_IOBUS
+
+/*@}*/
+
+#endif /* _SAMD21_PORT_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rfctrl.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,107 @@
+/**
+ * \file
+ *
+ * \brief Component description for RFCTRL
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMR21_RFCTRL_COMPONENT_
+#define _SAMR21_RFCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RFCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMR21_RFCTRL RF233 control module */
+/*@{*/
+
+#define RFCTRL_U2233
+#define REV_RFCTRL 0x100
+
+/* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
+ uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
+ uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
+ uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
+ uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
+ uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RFCTRL_FECFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RFCTRL_FECFG_OFFSET 0x0 /**< \brief (RFCTRL_FECFG offset) Front-end control bus configuration */
+#define RFCTRL_FECFG_RESETVALUE 0x0000ul /**< \brief (RFCTRL_FECFG reset_value) Front-end control bus configuration */
+
+#define RFCTRL_FECFG_F0CFG_Pos 0 /**< \brief (RFCTRL_FECFG) Front-end control signal 0 configuration */
+#define RFCTRL_FECFG_F0CFG_Msk (0x3ul << RFCTRL_FECFG_F0CFG_Pos)
+#define RFCTRL_FECFG_F0CFG(value) ((RFCTRL_FECFG_F0CFG_Msk & ((value) << RFCTRL_FECFG_F0CFG_Pos)))
+#define RFCTRL_FECFG_F1CFG_Pos 2 /**< \brief (RFCTRL_FECFG) Front-end control signal 1 configuration */
+#define RFCTRL_FECFG_F1CFG_Msk (0x3ul << RFCTRL_FECFG_F1CFG_Pos)
+#define RFCTRL_FECFG_F1CFG(value) ((RFCTRL_FECFG_F1CFG_Msk & ((value) << RFCTRL_FECFG_F1CFG_Pos)))
+#define RFCTRL_FECFG_F2CFG_Pos 4 /**< \brief (RFCTRL_FECFG) Front-end control signal 2 configuration */
+#define RFCTRL_FECFG_F2CFG_Msk (0x3ul << RFCTRL_FECFG_F2CFG_Pos)
+#define RFCTRL_FECFG_F2CFG(value) ((RFCTRL_FECFG_F2CFG_Msk & ((value) << RFCTRL_FECFG_F2CFG_Pos)))
+#define RFCTRL_FECFG_F3CFG_Pos 6 /**< \brief (RFCTRL_FECFG) Front-end control signal 3 configuration */
+#define RFCTRL_FECFG_F3CFG_Msk (0x3ul << RFCTRL_FECFG_F3CFG_Pos)
+#define RFCTRL_FECFG_F3CFG(value) ((RFCTRL_FECFG_F3CFG_Msk & ((value) << RFCTRL_FECFG_F3CFG_Pos)))
+#define RFCTRL_FECFG_F4CFG_Pos 8 /**< \brief (RFCTRL_FECFG) Front-end control signal 4 configuration */
+#define RFCTRL_FECFG_F4CFG_Msk (0x3ul << RFCTRL_FECFG_F4CFG_Pos)
+#define RFCTRL_FECFG_F4CFG(value) ((RFCTRL_FECFG_F4CFG_Msk & ((value) << RFCTRL_FECFG_F4CFG_Pos)))
+#define RFCTRL_FECFG_F5CFG_Pos 10 /**< \brief (RFCTRL_FECFG) Front-end control signal 5 configuration */
+#define RFCTRL_FECFG_F5CFG_Msk (0x3ul << RFCTRL_FECFG_F5CFG_Pos)
+#define RFCTRL_FECFG_F5CFG(value) ((RFCTRL_FECFG_F5CFG_Msk & ((value) << RFCTRL_FECFG_F5CFG_Pos)))
+#define RFCTRL_FECFG_MASK 0x0FFFul /**< \brief (RFCTRL_FECFG) MASK Register */
+
+/** \brief RFCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
+} Rfctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR21_RFCTRL_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1065 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_RTC_COMPONENT_
+#define _SAMD21_RTC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2202
+#define REV_RTC 0x101
+
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
+#define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
+
+#define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */
+#define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
+#define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */
+#define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
+#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
+#define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))
+#define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */
+#define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
+#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))
+#define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */
+
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
+#define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
+
+#define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */
+#define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
+#define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */
+#define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
+#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
+#define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))
+#define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
+#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))
+#define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */
+
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
+#define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
+
+#define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */
+#define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
+#define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */
+#define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
+#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
+#define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))
+#define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */
+#define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */
+#define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
+#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))
+#define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */
+
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */
+#define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */
+
+#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
+#define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos)
+#define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))
+#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
+#define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos)
+#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
+#define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos)
+#define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))
+#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint16_t :5; /*!< bit: 10..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))
+#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))
+#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
+#define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
+#define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
+#define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */
+#define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */
+
+#define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */
+#define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
+#define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))
+#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))
+#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))
+#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))
+#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))
+#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))
+#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
+#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))
+#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))
+#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))
+#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))
+#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))
+#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))
+#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))
+#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))
+#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))
+#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))
+#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))
+#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))
+#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))
+#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_RTC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1511 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_SERCOM_COMPONENT_
+#define _SAMD21_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM 0x200
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
+#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
+#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
+#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :4; /*!< bit: 9..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)))
+#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
+#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
+#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)))
+#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
+#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
+#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)))
+#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)))
+#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)))
+#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)))
+#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
+#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)))
+#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
+#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
+#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
+#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
+#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
+#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
+#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved2[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
+ RoReg8 Reserved7[0x7];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ RoReg8 Reserved1[0xC];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved2[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved2[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
+ RoReg8 Reserved6[0x8];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
+ RoReg8 Reserved7[0x6];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SERCOM_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,951 @@
+/**
+ * \file
+ *
+ * \brief Component description for SYSCTRL
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_SYSCTRL_COMPONENT_
+#define _SAMD21_SYSCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SYSCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SYSCTRL System Control */
+/*@{*/
+
+#define SYSCTRL_U2100
+#define REV_SYSCTRL 0x201
+
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos)
+#define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
+
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
+#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos)
+#define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
+
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
+#define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
+#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
+#define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
+#define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
+#define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
+#define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
+#define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
+#define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
+#define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
+#define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
+#define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
+#define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
+#define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
+#define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos)
+#define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
+
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_PCLKSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
+#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
+
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
+#define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
+#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
+#define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
+#define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
+#define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
+#define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
+#define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
+#define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
+#define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
+#define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
+#define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
+#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
+#define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
+#define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
+#define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
+#define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos)
+#define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
+
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_XOSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
+
+#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
+#define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
+#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
+#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */
+#define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */
+#define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
+#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
+#define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
+#define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */
+#define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */
+#define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */
+#define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */
+#define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */
+#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
+#define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
+#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
+#define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
+#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
+#define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */
+
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
+#define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
+#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
+#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
+#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
+#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
+#define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
+#define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
+#define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
+#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
+#define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
+#define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
+#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
+
+#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
+#define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
+#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
+#define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
+#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
+#define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */
+#define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */
+#define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
+#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
+#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
+#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
+#define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
+#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
+#define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
+#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
+#define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
+#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
+#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
+#define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
+#define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
+
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_OSC8M_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
+#define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
+
+#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
+#define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */
+#define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
+#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */
+#define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
+#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
+#define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
+#define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */
+#define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */
+#define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */
+#define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */
+#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
+#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
+#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
+#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
+#define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
+#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
+#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
+#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
+#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
+#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
+
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
+ uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
+ uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
+ uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
+#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
+
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
+#define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
+#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
+#define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
+#define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
+#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
+#define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
+#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
+#define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos)
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
+#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
+#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
+#define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
+#define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
+#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
+#define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
+#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
+#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
+#define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
+
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
+#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
+#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
+#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
+#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
+#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
+#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
+#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
+#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
+#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
+
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
+#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
+#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
+#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
+#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
+#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
+#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
+#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
+#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
+#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
+
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t READREQ:1; /*!< bit: 7 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
+#define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
+#define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
+
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MODE:1; /*!< bit: 8 Operation Mode */
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
+#define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
+
+#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */
+#define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
+#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */
+#define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos)
+#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
+#define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
+#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */
+#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
+#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
+#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */
+#define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
+#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */
+#define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos)
+#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */
+#define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos)
+#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
+#define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
+#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
+#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
+#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
+#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
+#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
+#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
+#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
+#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
+#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
+#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
+#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
+#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
+#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
+#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
+#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
+#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
+#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
+#define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
+#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
+#define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
+
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t :6; /*!< bit: 7..12 Reserved */
+ uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
+#define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
+
+#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
+#define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
+#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
+#define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
+#define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */
+
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
+#define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
+
+#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
+#define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos)
+#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
+#define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
+#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
+#define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
+#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
+#define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
+#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
+#define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
+#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
+#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
+#define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
+#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
+ uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
+ uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
+ uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
+#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
+#define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos)
+#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
+#define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
+#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
+#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
+#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
+#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
+#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
+ uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
+ uint8_t DIV:1; /*!< bit: 3 Divider Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
+#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
+#define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos)
+#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
+#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
+#define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
+#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
+#define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos)
+#define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief SYSCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+ RoReg8 Reserved1[0x2];
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ RoReg8 Reserved2[0x2];
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+ RoReg8 Reserved3[0x3];
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+ RoReg8 Reserved4[0x2];
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved5[0x3];
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+ RoReg8 Reserved6[0x4];
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+ RoReg8 Reserved7[0x2];
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+ __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
+ RoReg8 Reserved8[0x3];
+ __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+ __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+ __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
+} Sysctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,687 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_TC_COMPONENT_
+#define _SAMD21_TC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2212
+#define REV_TC 0x121
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
+#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
+#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
+#define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
+#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
+#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
+#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
+#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
+ uint16_t :9; /*!< bit: 5..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
+#define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */
+
+#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
+#define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos)
+#define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
+#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
+#define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos)
+#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
+#define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos)
+#define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
+#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
+#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */
+#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
+#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
+#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */
+#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
+ uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
+#define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */
+
+#define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
+#define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
+#define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
+#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
+#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
+#define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos)
+#define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
+#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
+#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
+#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
+#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
+#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
+#define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos)
+#define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
+#define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
+#define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
+#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */
+#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */
+#define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */
+#define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
+#define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
+#define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
+#define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
+#define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
+#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
+#define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
+#define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
+#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
+#define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
+#define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
+#define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
+#define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos)
+#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
+#define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow */
+ uint8_t ERR:1; /*!< bit: 1 Error */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
+#define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
+#define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
+#define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
+#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
+#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
+#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
+#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
+#define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */
+ uint8_t STOP:1; /*!< bit: 3 Stop */
+ uint8_t SLAVE:1; /*!< bit: 4 Slave */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
+#define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
+#define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
+#define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos)
+#define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
+#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
+
+#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
+#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
+#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
+#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
+
+#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
+#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
+#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
+#define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
+
+#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
+#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
+#define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
+
+#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
+#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
+#define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
+
+#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
+#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
+#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
+#define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
+
+#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
+#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
+#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
+#define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
+
+#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
+#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
+#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
+ RoReg8 Reserved3[0x3];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
+ RoReg8 Reserved4[0x3];
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+ RoReg8 Reserved3[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1820 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC 0x101
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)))
+#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)))
+#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */
+#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */
+#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */
+#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */
+#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */
+#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */
+#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */
+#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)))
+#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)))
+#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)))
+#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)))
+#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */
+#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */
+#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)))
+#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)))
+#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */
+#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */
+#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)))
+#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)))
+#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)))
+#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)))
+#define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */
+#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)))
+#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */
+#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)))
+#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)))
+#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */
+#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */
+#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */
+#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */
+#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)))
+#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)))
+#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)))
+#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)))
+#define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */
+#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)))
+#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */
+#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)))
+#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)))
+#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */
+#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */
+#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */
+#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */
+#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)))
+#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)))
+#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)))
+#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)))
+#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)))
+#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)))
+#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)))
+#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)))
+#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)))
+#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)))
+#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)))
+#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)))
+#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */
+#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */
+#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)))
+#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */
+#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)))
+#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)))
+#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)))
+#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)))
+#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)))
+#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)))
+#define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)))
+#define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ uint32_t CNT:1; /*!< bit: 2 Counter */
+ uint32_t ERR:1; /*!< bit: 3 Error */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)))
+#define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)))
+#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)))
+#define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)))
+#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)))
+#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)))
+#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)))
+#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)))
+#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)))
+#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)))
+#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */
+#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */
+#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */
+#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */
+#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)))
+#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */
+#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)))
+#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)))
+#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)))
+#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) ((TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)))
+#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)))
+#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) ((TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)))
+#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)))
+#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) ((TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)))
+#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)))
+#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)))
+#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) ((TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)))
+#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)))
+#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) ((TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)))
+#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)))
+#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) ((TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)))
+#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)))
+#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)))
+#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)))
+#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)))
+#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)))
+#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */
+#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */
+#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)))
+#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)))
+#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)))
+#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)))
+#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) ((TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)))
+#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value) ((TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)))
+#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) ((TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)))
+#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value) ((TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)))
+#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) ((TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)))
+#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value) ((TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)))
+#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)))
+#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) ((TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)))
+#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value) ((TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)))
+#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) ((TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)))
+#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value) ((TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)))
+#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) ((TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)))
+#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value) ((TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)))
+#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)))
+#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_usb.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1807 @@
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_USB_COMPONENT_
+#define _SAMD21_USB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB 0x101
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */
+#define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE 0x05ul /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value) ((USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)))
+#define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define USB_QOSCTRL_CQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value) ((USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)))
+#define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define USB_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_MASK 0x0Ful /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)))
+#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)))
+#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)))
+#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK 0x0F6Eul /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)))
+#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)))
+#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)))
+#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)))
+#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)))
+#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)))
+#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)))
+#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)))
+#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)))
+#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)))
+#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)))
+#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)))
+#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)))
+#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)))
+#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)))
+#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)))
+#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)))
+#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)))
+#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)))
+#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)))
+#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)))
+#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)))
+#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)))
+#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
+#define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)))
+#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)))
+#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)))
+#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
+#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)))
+#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)))
+#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)))
+#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)))
+#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_USB_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,306 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_WDT_COMPONENT_
+#define _SAMD21_WDT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2203
+#define REV_WDT 0x200
+
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
+#define WDT_CTRL_RESETVALUE 0x00ul /**< \brief (WDT_CTRL reset_value) Control */
+
+#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
+#define WDT_CTRL_ENABLE (0x1ul << WDT_CTRL_ENABLE_Pos)
+#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
+#define WDT_CTRL_WEN (0x1ul << WDT_CTRL_WEN_Pos)
+#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
+#define WDT_CTRL_ALWAYSON (0x1ul << WDT_CTRL_ALWAYSON_Pos)
+#define WDT_CTRL_MASK 0x86ul /**< \brief (WDT_CTRL) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
+#define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_PER_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_PER_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_PER_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_PER_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_PER_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_PER_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_PER_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_PER_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_PER_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
+#define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_WINDOW_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_WINDOW_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_WINDOW_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_WINDOW_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_WINDOW_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_WINDOW_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_WINDOW_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_WINDOW_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_WINDOW_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
+#define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_1K_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_2K_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_4K_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8K_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_16K_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
+#define WDT_STATUS_RESETVALUE 0x00ul /**< \brief (WDT_STATUS reset_value) Status */
+
+#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
+#define WDT_STATUS_SYNCBUSY (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
+#define WDT_STATUS_MASK 0x80ul /**< \brief (WDT_STATUS) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
+#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_WDT_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_ac.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,90 @@ +/** + * \file + * + * \brief Instance description for AC + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_AC_INSTANCE_ +#define _SAMD21_AC_INSTANCE_ + +/* ========== Register definition for AC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */ +#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */ +#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */ +#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */ +#else +#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */ +#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */ +#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */ +#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC peripheral ========== */ +#define AC_CMP_NUM 2 // Number of comparators +#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog +#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital +#define AC_NUM_CMP 2 +#define AC_PAIRS 1 // Number of pairs of comparators + +#endif /* _SAMD21_AC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief Instance description for ADC + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_ADC_INSTANCE_ +#define _SAMD21_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */ +#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */ +#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */ +#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */ +#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */ +#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */ +#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */ +#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */ +#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */ +#else +#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */ +#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */ +#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */ +#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */ +#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */ +#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */ +#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */ +#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */ +#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for ADC peripheral ========== */ +#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger +#define ADC_EXTCHANNEL_MSB 19 // Number of external channels +#define ADC_GCLK_ID 30 // Index of Generic Clock +#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield +#define ADC_RESULT_MSB 15 // Size of Result + +#endif /* _SAMD21_ADC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dac.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,77 @@ +/** + * \file + * + * \brief Instance description for DAC + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_DAC_INSTANCE_ +#define _SAMD21_DAC_INSTANCE_ + +/* ========== Register definition for DAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status */ +#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data */ +#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer */ +#else +#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */ +#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */ +#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DAC peripheral ========== */ +#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger +#define DAC_GCLK_ID 33 // Index of Generic Clock + +#endif /* _SAMD21_DAC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,112 @@ +/** + * \file + * + * \brief Instance description for DMAC + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_DMAC_INSTANCE_ +#define _SAMD21_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */ +#define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */ +#else +#define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */ +#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DMAC peripheral ========== */ +#define DMAC_CH_BITS 4 // Number of bits to select channel +#define DMAC_CH_NUM 12 // Number of channels +#define DMAC_CLK_AHB_ID 5 // AHB clock index +#define DMAC_EVIN_NUM 4 // Number of input events +#define DMAC_EVOUT_NUM 4 // Number of output events +#define DMAC_LVL_BITS 2 // Number of bit to select level priority +#define DMAC_LVL_NUM 4 // Enable priority level number +#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source +#define DMAC_TRIG_NUM 45 // Number of peripheral triggers + +#endif /* _SAMD21_DMAC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief Instance description for DSU + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_DSU_INSTANCE_ +#define _SAMD21_DSU_INSTANCE_ + +/* ========== Register definition for DSU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ +#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ +#else +#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ +#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DSU peripheral ========== */ +#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register + +#endif /* _SAMD21_DSU_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_eic.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief Instance description for EIC + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_EIC_INSTANCE_ +#define _SAMD21_EIC_INSTANCE_ + +/* ========== Register definition for EIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control */ +#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status */ +#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ +#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ +#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */ +#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */ +#else +#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */ +#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */ +#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ +#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ +#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */ +#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EIC peripheral ========== */ +#define EIC_CONFIG_NUM 2 // Number of CONFIG registers +#define EIC_GCLK_ID 5 // Index of Generic Clock + +#endif /* _SAMD21_EIC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_evsys.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,200 @@ +/** + * \file + * + * \brief Instance description for EVSYS + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_EVSYS_INSTANCE_ +#define _SAMD21_EVSYS_INSTANCE_ + +/* ========== Register definition for EVSYS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel */ +#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Multiplexer */ +#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#else +#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel */ +#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */ +#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EVSYS peripheral ========== */ +#define EVSYS_CHANNELS 12 // Number of Channels +#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel +#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1 +#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators +#define EVSYS_GCLK_ID_0 7 +#define EVSYS_GCLK_ID_1 8 +#define EVSYS_GCLK_ID_2 9 +#define EVSYS_GCLK_ID_3 10 +#define EVSYS_GCLK_ID_4 11 +#define EVSYS_GCLK_ID_5 12 +#define EVSYS_GCLK_ID_6 13 +#define EVSYS_GCLK_ID_7 14 +#define EVSYS_GCLK_ID_8 15 +#define EVSYS_GCLK_ID_9 16 +#define EVSYS_GCLK_ID_10 17 +#define EVSYS_GCLK_ID_11 18 +#define EVSYS_GCLK_ID_LSB 7 +#define EVSYS_GCLK_ID_MSB 18 +#define EVSYS_GCLK_ID_SIZE 12 +#define EVSYS_GENERATORS 73 // Total Number of Event Generators +#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator +#define EVSYS_USERS 29 // Total Number of Event Users +#define EVSYS_USERS_BITS 5 // Number of bits to select Event User + +// GENERATORS +#define EVSYS_ID_GEN_RTC_CMP_0 1 +#define EVSYS_ID_GEN_RTC_CMP_1 2 +#define EVSYS_ID_GEN_RTC_OVF 3 +#define EVSYS_ID_GEN_RTC_PER_0 4 +#define EVSYS_ID_GEN_RTC_PER_1 5 +#define EVSYS_ID_GEN_RTC_PER_2 6 +#define EVSYS_ID_GEN_RTC_PER_3 7 +#define EVSYS_ID_GEN_RTC_PER_4 8 +#define EVSYS_ID_GEN_RTC_PER_5 9 +#define EVSYS_ID_GEN_RTC_PER_6 10 +#define EVSYS_ID_GEN_RTC_PER_7 11 +#define EVSYS_ID_GEN_EIC_EXTINT_0 12 +#define EVSYS_ID_GEN_EIC_EXTINT_1 13 +#define EVSYS_ID_GEN_EIC_EXTINT_2 14 +#define EVSYS_ID_GEN_EIC_EXTINT_3 15 +#define EVSYS_ID_GEN_EIC_EXTINT_4 16 +#define EVSYS_ID_GEN_EIC_EXTINT_5 17 +#define EVSYS_ID_GEN_EIC_EXTINT_6 18 +#define EVSYS_ID_GEN_EIC_EXTINT_7 19 +#define EVSYS_ID_GEN_EIC_EXTINT_8 20 +#define EVSYS_ID_GEN_EIC_EXTINT_9 21 +#define EVSYS_ID_GEN_EIC_EXTINT_10 22 +#define EVSYS_ID_GEN_EIC_EXTINT_11 23 +#define EVSYS_ID_GEN_EIC_EXTINT_12 24 +#define EVSYS_ID_GEN_EIC_EXTINT_13 25 +#define EVSYS_ID_GEN_EIC_EXTINT_14 26 +#define EVSYS_ID_GEN_EIC_EXTINT_15 27 +#define EVSYS_ID_GEN_EIC_EXTINT_16 28 +#define EVSYS_ID_GEN_EIC_EXTINT_17 29 +#define EVSYS_ID_GEN_DMAC_CH_0 30 +#define EVSYS_ID_GEN_DMAC_CH_1 31 +#define EVSYS_ID_GEN_DMAC_CH_2 32 +#define EVSYS_ID_GEN_DMAC_CH_3 33 +#define EVSYS_ID_GEN_TCC0_OVF 34 +#define EVSYS_ID_GEN_TCC0_TRG 35 +#define EVSYS_ID_GEN_TCC0_CNT 36 +#define EVSYS_ID_GEN_TCC0_MCX_0 37 +#define EVSYS_ID_GEN_TCC0_MCX_1 38 +#define EVSYS_ID_GEN_TCC0_MCX_2 39 +#define EVSYS_ID_GEN_TCC0_MCX_3 40 +#define EVSYS_ID_GEN_TCC1_OVF 41 +#define EVSYS_ID_GEN_TCC1_TRG 42 +#define EVSYS_ID_GEN_TCC1_CNT 43 +#define EVSYS_ID_GEN_TCC1_MCX_0 44 +#define EVSYS_ID_GEN_TCC1_MCX_1 45 +#define EVSYS_ID_GEN_TCC2_OVF 46 +#define EVSYS_ID_GEN_TCC2_TRG 47 +#define EVSYS_ID_GEN_TCC2_CNT 48 +#define EVSYS_ID_GEN_TCC2_MCX_0 49 +#define EVSYS_ID_GEN_TCC2_MCX_1 50 +#define EVSYS_ID_GEN_TC3_OVF 51 +#define EVSYS_ID_GEN_TC3_MCX_0 52 +#define EVSYS_ID_GEN_TC3_MCX_1 53 +#define EVSYS_ID_GEN_TC4_OVF 54 +#define EVSYS_ID_GEN_TC4_MCX_0 55 +#define EVSYS_ID_GEN_TC4_MCX_1 56 +#define EVSYS_ID_GEN_TC5_OVF 57 +#define EVSYS_ID_GEN_TC5_MCX_0 58 +#define EVSYS_ID_GEN_TC5_MCX_1 59 +#define EVSYS_ID_GEN_TC6_OVF 60 +#define EVSYS_ID_GEN_TC6_MCX_0 61 +#define EVSYS_ID_GEN_TC6_MCX_1 62 +#define EVSYS_ID_GEN_TC7_OVF 63 +#define EVSYS_ID_GEN_TC7_MCX_0 64 +#define EVSYS_ID_GEN_TC7_MCX_1 65 +#define EVSYS_ID_GEN_ADC_RESRDY 66 +#define EVSYS_ID_GEN_ADC_WINMON 67 +#define EVSYS_ID_GEN_AC_COMP_0 68 +#define EVSYS_ID_GEN_AC_COMP_1 69 +#define EVSYS_ID_GEN_AC_WIN_0 70 +#define EVSYS_ID_GEN_DAC_EMPTY 71 +#define EVSYS_ID_GEN_PTC_EOC 72 +#define EVSYS_ID_GEN_PTC_WCOMP 73 + +// USERS +#define EVSYS_ID_USER_DMAC_CH_0 0 +#define EVSYS_ID_USER_DMAC_CH_1 1 +#define EVSYS_ID_USER_DMAC_CH_2 2 +#define EVSYS_ID_USER_DMAC_CH_3 3 +#define EVSYS_ID_USER_TCC0_EV_0 4 +#define EVSYS_ID_USER_TCC0_EV_1 5 +#define EVSYS_ID_USER_TCC0_MC_0 6 +#define EVSYS_ID_USER_TCC0_MC_1 7 +#define EVSYS_ID_USER_TCC0_MC_2 8 +#define EVSYS_ID_USER_TCC0_MC_3 9 +#define EVSYS_ID_USER_TCC1_EV_0 10 +#define EVSYS_ID_USER_TCC1_EV_1 11 +#define EVSYS_ID_USER_TCC1_MC_0 12 +#define EVSYS_ID_USER_TCC1_MC_1 13 +#define EVSYS_ID_USER_TCC2_EV_0 14 +#define EVSYS_ID_USER_TCC2_EV_1 15 +#define EVSYS_ID_USER_TCC2_MC_0 16 +#define EVSYS_ID_USER_TCC2_MC_1 17 +#define EVSYS_ID_USER_TC3_EVU 18 +#define EVSYS_ID_USER_TC4_EVU 19 +#define EVSYS_ID_USER_TC5_EVU 20 +#define EVSYS_ID_USER_TC6_EVU 21 +#define EVSYS_ID_USER_TC7_EVU 22 +#define EVSYS_ID_USER_ADC_START 23 +#define EVSYS_ID_USER_ADC_SYNC 24 +#define EVSYS_ID_USER_AC_SOC_0 25 +#define EVSYS_ID_USER_AC_SOC_1 26 +#define EVSYS_ID_USER_DAC_START 27 +#define EVSYS_ID_USER_PTC_STCONV 28 + +#endif /* _SAMD21_EVSYS_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,82 @@ +/** + * \file + * + * \brief Instance description for GCLK + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_GCLK_INSTANCE_ +#define _SAMD21_GCLK_INSTANCE_ + +/* ========== Register definition for GCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */ +#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */ +#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ +#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ +#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ +#else +#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */ +#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */ +#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ +#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ +#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for GCLK peripheral ========== */ +#define GCLK_GENDIV_BITS 16 +#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators +#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 +#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 +#define GCLK_NUM 37 // Number of Generic Clock Users +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC8M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 + +#endif /* _SAMD21_GCLK_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Instance description for I2S + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_I2S_INSTANCE_ +#define _SAMD21_I2S_INSTANCE_ + +/* ========== Register definition for I2S peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_I2S_CTRLA (0x42005000U) /**< \brief (I2S) Control A */ +#define REG_I2S_CLKCTRL0 (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */ +#define REG_I2S_CLKCTRL1 (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */ +#define REG_I2S_INTENCLR (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */ +#define REG_I2S_INTENSET (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */ +#define REG_I2S_INTFLAG (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */ +#define REG_I2S_SYNCBUSY (0x42005018U) /**< \brief (I2S) Synchronization Status */ +#define REG_I2S_SERCTRL0 (0x42005020U) /**< \brief (I2S) Serializer 0 Control */ +#define REG_I2S_SERCTRL1 (0x42005024U) /**< \brief (I2S) Serializer 1 Control */ +#define REG_I2S_DATA0 (0x42005030U) /**< \brief (I2S) Data 0 */ +#define REG_I2S_DATA1 (0x42005034U) /**< \brief (I2S) Data 1 */ +#else +#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */ +#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */ +#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */ +#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */ +#define REG_I2S_INTENSET (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */ +#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */ +#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */ +#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */ +#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */ +#define REG_I2S_DATA0 (*(RwReg *)0x42005030U) /**< \brief (I2S) Data 0 */ +#define REG_I2S_DATA1 (*(RwReg *)0x42005034U) /**< \brief (I2S) Data 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for I2S peripheral ========== */ +#define I2S_CLK_NUM 2 // Number of clock units +#define I2S_DMAC_ID_RX_0 41 +#define I2S_DMAC_ID_RX_1 42 +#define I2S_DMAC_ID_RX_LSB 41 +#define I2S_DMAC_ID_RX_MSB 42 +#define I2S_DMAC_ID_RX_SIZE 2 +#define I2S_DMAC_ID_TX_0 43 +#define I2S_DMAC_ID_TX_1 44 +#define I2S_DMAC_ID_TX_LSB 43 +#define I2S_DMAC_ID_TX_MSB 44 +#define I2S_DMAC_ID_TX_SIZE 2 +#define I2S_GCLK_ID_0 35 +#define I2S_GCLK_ID_1 36 +#define I2S_GCLK_ID_LSB 35 +#define I2S_GCLK_ID_MSB 36 +#define I2S_GCLK_ID_SIZE 2 +#define I2S_MAX_SLOTS 8 // Max number of data slots in frame +#define I2S_SER_NUM 2 // Number of serializers + +#endif /* _SAMD21_I2S_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_mtb.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for MTB + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_MTB_INSTANCE_ +#define _SAMD21_MTB_INSTANCE_ + +/* ========== Register definition for MTB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */ +#else +#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */ +#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAMD21_MTB_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief Instance description for NVMCTRL + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_NVMCTRL_INSTANCE_ +#define _SAMD21_NVMCTRL_INSTANCE_ + +/* ========== Register definition for NVMCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ +#else +#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for NVMCTRL peripheral ========== */ +#define NVMCTRL_AUX0_ADDRESS 0x00804000 +#define NVMCTRL_AUX1_ADDRESS 0x00806000 +#define NVMCTRL_AUX2_ADDRESS 0x00808000 +#define NVMCTRL_AUX3_ADDRESS 0x0080A000 +#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register +#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF +#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 +#define NVMCTRL_PAGES 4096 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 +#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 +#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 +#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF + +#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac0.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief Instance description for PAC0 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_PAC0_INSTANCE_ +#define _SAMD21_PAC0_INSTANCE_ + +/* ========== Register definition for PAC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear */ +#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set */ +#else +#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */ +#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC0 peripheral ========== */ +#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset + +#endif /* _SAMD21_PAC0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac1.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief Instance description for PAC1 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_PAC1_INSTANCE_ +#define _SAMD21_PAC1_INSTANCE_ + +/* ========== Register definition for PAC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear */ +#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set */ +#else +#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */ +#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC1 peripheral ========== */ +#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset + +#endif /* _SAMD21_PAC1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac2.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief Instance description for PAC2 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_PAC2_INSTANCE_ +#define _SAMD21_PAC2_INSTANCE_ + +/* ========== Register definition for PAC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear */ +#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set */ +#else +#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */ +#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC2 peripheral ========== */ +#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset + +#endif /* _SAMD21_PAC2_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,90 @@ +/** + * \file + * + * \brief Instance description for PM + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_PM_INSTANCE_ +#define _SAMD21_PM_INSTANCE_ + +/* ========== Register definition for PM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */ +#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */ +#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ +#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ +#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ +#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ +#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ +#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ +#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ +#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ +#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */ +#else +#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */ +#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */ +#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ +#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ +#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ +#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ +#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ +#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ +#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ +#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ +#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PM peripheral ========== */ +#define PM_CTRL_MCSEL_DFLL48M 3 +#define PM_CTRL_MCSEL_GCLK 0 +#define PM_CTRL_MCSEL_OSC8M 1 +#define PM_CTRL_MCSEL_XOSC 2 +#define PM_PM_CLK_APB_NUM 2 + +#endif /* _SAMD21_PM_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,139 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21_PORT_INSTANCE_
+#define _SAMD21_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS 84 // Number of PORT pins
+#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
+#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
+#define PORT_DRVSTR 1 // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
+#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
+#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
+#define PORT_ODRAIN 0 // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
+#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
+#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
+#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
+#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
+#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
+#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
+#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
+#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
+#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
+#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
+#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
+#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
+#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
+#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
+#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
+#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
+#define PORT_SLEWLIM 0 // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
+#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+
+#endif /* _SAMD21_PORT_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rfctrl.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,60 @@ +/** + * \file + * + * \brief Instance description for RFCTRL + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMR21_RFCTRL_INSTANCE_ +#define _SAMR21_RFCTRL_INSTANCE_ + +/* ========== Register definition for RFCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RFCTRL_FECFG (0x42005400U) /**< \brief (RFCTRL) Front-end control bus configuration */ +#else +#define REG_RFCTRL_FECFG (*(RwReg16*)0x42005400U) /**< \brief (RFCTRL) Front-end control bus configuration */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RFCTRL peripheral ========== */ +#define RFCTRL_FBUSMSB 5 + +#endif /* _SAMR21_RFCTRL_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Instance description for RTC + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_RTC_INSTANCE_ +#define _SAMD21_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */ +#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */ +#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */ +#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */ +#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */ +#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#else +#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */ +#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */ +#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */ +#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */ +#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */ +#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RTC peripheral ========== */ +#define RTC_ALARM_NUM 1 // Number of Alarms +#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators +#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators +#define RTC_GCLK_ID 4 // Index of Generic Clock +#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete) +#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete) +#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete) + +#endif /* _SAMD21_RTC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sbmatrix.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,168 @@ +/** + * \file + * + * \brief Instance description for SBMATRIX + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SBMATRIX_INSTANCE_ +#define _SAMD21_SBMATRIX_INSTANCE_ + +/* ========== Register definition for SBMATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SBMATRIX_PRAS0 (0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */ +#define REG_SBMATRIX_PRBS0 (0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */ +#define REG_SBMATRIX_PRAS1 (0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */ +#define REG_SBMATRIX_PRBS1 (0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */ +#define REG_SBMATRIX_PRAS2 (0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */ +#define REG_SBMATRIX_PRBS2 (0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */ +#define REG_SBMATRIX_PRAS3 (0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */ +#define REG_SBMATRIX_PRBS3 (0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */ +#define REG_SBMATRIX_PRAS4 (0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */ +#define REG_SBMATRIX_PRBS4 (0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */ +#define REG_SBMATRIX_PRAS5 (0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */ +#define REG_SBMATRIX_PRBS5 (0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */ +#define REG_SBMATRIX_PRAS6 (0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */ +#define REG_SBMATRIX_PRBS6 (0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */ +#define REG_SBMATRIX_PRAS7 (0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */ +#define REG_SBMATRIX_PRBS7 (0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */ +#define REG_SBMATRIX_PRAS8 (0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */ +#define REG_SBMATRIX_PRBS8 (0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */ +#define REG_SBMATRIX_PRAS9 (0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */ +#define REG_SBMATRIX_PRBS9 (0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */ +#define REG_SBMATRIX_PRAS10 (0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */ +#define REG_SBMATRIX_PRBS10 (0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */ +#define REG_SBMATRIX_PRAS11 (0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */ +#define REG_SBMATRIX_PRBS11 (0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */ +#define REG_SBMATRIX_PRAS12 (0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */ +#define REG_SBMATRIX_PRBS12 (0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */ +#define REG_SBMATRIX_PRAS13 (0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */ +#define REG_SBMATRIX_PRBS13 (0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */ +#define REG_SBMATRIX_PRAS14 (0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */ +#define REG_SBMATRIX_PRBS14 (0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */ +#define REG_SBMATRIX_PRAS15 (0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */ +#define REG_SBMATRIX_PRBS15 (0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */ +#define REG_SBMATRIX_SFR0 (0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */ +#define REG_SBMATRIX_SFR1 (0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */ +#define REG_SBMATRIX_SFR2 (0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */ +#define REG_SBMATRIX_SFR3 (0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */ +#define REG_SBMATRIX_SFR4 (0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */ +#define REG_SBMATRIX_SFR5 (0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */ +#define REG_SBMATRIX_SFR6 (0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */ +#define REG_SBMATRIX_SFR7 (0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */ +#define REG_SBMATRIX_SFR8 (0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */ +#define REG_SBMATRIX_SFR9 (0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */ +#define REG_SBMATRIX_SFR10 (0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */ +#define REG_SBMATRIX_SFR11 (0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */ +#define REG_SBMATRIX_SFR12 (0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */ +#define REG_SBMATRIX_SFR13 (0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */ +#define REG_SBMATRIX_SFR14 (0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */ +#define REG_SBMATRIX_SFR15 (0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */ +#else +#define REG_SBMATRIX_PRAS0 (*(RwReg *)0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */ +#define REG_SBMATRIX_PRBS0 (*(RwReg *)0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */ +#define REG_SBMATRIX_PRAS1 (*(RwReg *)0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */ +#define REG_SBMATRIX_PRBS1 (*(RwReg *)0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */ +#define REG_SBMATRIX_PRAS2 (*(RwReg *)0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */ +#define REG_SBMATRIX_PRBS2 (*(RwReg *)0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */ +#define REG_SBMATRIX_PRAS3 (*(RwReg *)0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */ +#define REG_SBMATRIX_PRBS3 (*(RwReg *)0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */ +#define REG_SBMATRIX_PRAS4 (*(RwReg *)0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */ +#define REG_SBMATRIX_PRBS4 (*(RwReg *)0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */ +#define REG_SBMATRIX_PRAS5 (*(RwReg *)0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */ +#define REG_SBMATRIX_PRBS5 (*(RwReg *)0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */ +#define REG_SBMATRIX_PRAS6 (*(RwReg *)0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */ +#define REG_SBMATRIX_PRBS6 (*(RwReg *)0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */ +#define REG_SBMATRIX_PRAS7 (*(RwReg *)0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */ +#define REG_SBMATRIX_PRBS7 (*(RwReg *)0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */ +#define REG_SBMATRIX_PRAS8 (*(RwReg *)0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */ +#define REG_SBMATRIX_PRBS8 (*(RwReg *)0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */ +#define REG_SBMATRIX_PRAS9 (*(RwReg *)0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */ +#define REG_SBMATRIX_PRBS9 (*(RwReg *)0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */ +#define REG_SBMATRIX_PRAS10 (*(RwReg *)0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */ +#define REG_SBMATRIX_PRBS10 (*(RwReg *)0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */ +#define REG_SBMATRIX_PRAS11 (*(RwReg *)0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */ +#define REG_SBMATRIX_PRBS11 (*(RwReg *)0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */ +#define REG_SBMATRIX_PRAS12 (*(RwReg *)0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */ +#define REG_SBMATRIX_PRBS12 (*(RwReg *)0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */ +#define REG_SBMATRIX_PRAS13 (*(RwReg *)0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */ +#define REG_SBMATRIX_PRBS13 (*(RwReg *)0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */ +#define REG_SBMATRIX_PRAS14 (*(RwReg *)0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */ +#define REG_SBMATRIX_PRBS14 (*(RwReg *)0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */ +#define REG_SBMATRIX_PRAS15 (*(RwReg *)0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */ +#define REG_SBMATRIX_PRBS15 (*(RwReg *)0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */ +#define REG_SBMATRIX_SFR0 (*(RwReg *)0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */ +#define REG_SBMATRIX_SFR1 (*(RwReg *)0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */ +#define REG_SBMATRIX_SFR2 (*(RwReg *)0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */ +#define REG_SBMATRIX_SFR3 (*(RwReg *)0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */ +#define REG_SBMATRIX_SFR4 (*(RwReg *)0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */ +#define REG_SBMATRIX_SFR5 (*(RwReg *)0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */ +#define REG_SBMATRIX_SFR6 (*(RwReg *)0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */ +#define REG_SBMATRIX_SFR7 (*(RwReg *)0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */ +#define REG_SBMATRIX_SFR8 (*(RwReg *)0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */ +#define REG_SBMATRIX_SFR9 (*(RwReg *)0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */ +#define REG_SBMATRIX_SFR10 (*(RwReg *)0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */ +#define REG_SBMATRIX_SFR11 (*(RwReg *)0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */ +#define REG_SBMATRIX_SFR12 (*(RwReg *)0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */ +#define REG_SBMATRIX_SFR13 (*(RwReg *)0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */ +#define REG_SBMATRIX_SFR14 (*(RwReg *)0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */ +#define REG_SBMATRIX_SFR15 (*(RwReg *)0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SBMATRIX peripheral ========== */ +#define SBMATRIX_DEFINED +/* ========== Instance parameters for SBMATRIX ========== */ +#define SBMATRIX_SLAVE_FLASH 0 +#define SBMATRIX_SLAVE_HPB0 1 +#define SBMATRIX_SLAVE_HPB1 2 +#define SBMATRIX_SLAVE_HPB2 3 +#define SBMATRIX_SLAVE_HMCRAMC0 4 +#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5 +#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6 +#define SBMATRIX_SLAVE_NUM 7 + +#define SBMATRIX_MASTER_CM0PLUS 0 +#define SBMATRIX_MASTER_DSU 1 +#define SBMATRIX_MASTER_DMAC 2 +#define SBMATRIX_MASTER_NUM 3 + +#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Instance description for SERCOM0 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SERCOM0_INSTANCE_ +#define _SAMD21_SERCOM0_INSTANCE_ + +/* ========== Register definition for SERCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ +#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ +#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ +#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ +#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ +#else +#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */ +#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */ +#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */ +#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */ +#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM0 peripheral ========== */ +#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger +#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger +#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core +#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM0_INT_MSB 6 + +#endif /* _SAMD21_SERCOM0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom1.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Instance description for SERCOM1 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SERCOM1_INSTANCE_ +#define _SAMD21_SERCOM1_INSTANCE_ + +/* ========== Register definition for SERCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */ +#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */ +#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */ +#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */ +#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ +#else +#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */ +#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */ +#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */ +#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */ +#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM1 peripheral ========== */ +#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger +#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger +#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core +#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM1_INT_MSB 6 + +#endif /* _SAMD21_SERCOM1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom2.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Instance description for SERCOM2 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SERCOM2_INSTANCE_ +#define _SAMD21_SERCOM2_INSTANCE_ + +/* ========== Register definition for SERCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */ +#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */ +#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */ +#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */ +#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ +#else +#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */ +#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */ +#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */ +#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */ +#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM2 peripheral ========== */ +#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger +#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger +#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core +#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM2_INT_MSB 6 + +#endif /* _SAMD21_SERCOM2_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom3.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Instance description for SERCOM3 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SERCOM3_INSTANCE_ +#define _SAMD21_SERCOM3_INSTANCE_ + +/* ========== Register definition for SERCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */ +#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */ +#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */ +#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */ +#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ +#else +#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */ +#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */ +#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */ +#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */ +#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM3 peripheral ========== */ +#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger +#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger +#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core +#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM3_INT_MSB 6 + +#endif /* _SAMD21_SERCOM3_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom4.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Instance description for SERCOM4 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SERCOM4_INSTANCE_ +#define _SAMD21_SERCOM4_INSTANCE_ + +/* ========== Register definition for SERCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */ +#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */ +#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */ +#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */ +#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ +#else +#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */ +#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */ +#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */ +#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */ +#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM4 peripheral ========== */ +#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger +#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger +#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core +#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM4_INT_MSB 6 + +#endif /* _SAMD21_SERCOM4_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom5.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Instance description for SERCOM5 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SERCOM5_INSTANCE_ +#define _SAMD21_SERCOM5_INSTANCE_ + +/* ========== Register definition for SERCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */ +#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */ +#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */ +#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */ +#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ +#else +#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */ +#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */ +#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */ +#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */ +#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM5 peripheral ========== */ +#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger +#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger +#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core +#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM5_INT_MSB 6 + +#endif /* _SAMD21_SERCOM5_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Instance description for SYSCTRL + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_SYSCTRL_INSTANCE_ +#define _SAMD21_SYSCTRL_INSTANCE_ + +/* ========== Register definition for SYSCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ +#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ +#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ +#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ +#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ +#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ +#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ +#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ +#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ +#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ +#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ +#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ +#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ +#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ +#define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ +#define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ +#else +#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ +#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ +#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ +#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ +#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ +#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ +#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ +#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ +#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ +#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ +#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ +#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ +#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ +#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ +#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ +#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SYSCTRL peripheral ========== */ +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 +#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL +#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x111 +#define SYSCTRL_BOD33_VERSION 0x111 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x1101 +#define SYSCTRL_VREF_VERSION 0x200 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x1111 +#define SYSCTRL_XOSC32K_VERSION 0x1111 + +#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc3.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TC3_INSTANCE_ +#define _SAMD21_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */ +#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */ +#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */ +#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ +#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ +#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ +#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ +#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ +#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ +#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC8_NUM 2 // Number of 8-bit Counters +#define TC3_CC16_NUM 2 // Number of 16-bit Counters +#define TC3_CC32_NUM 2 // Number of 32-bit Counters +#define TC3_DITHERING_EXT 0 // Dithering feature implemented +#define TC3_DMAC_ID_MC_0 25 +#define TC3_DMAC_ID_MC_1 26 +#define TC3_DMAC_ID_MC_LSB 25 +#define TC3_DMAC_ID_MC_MSB 26 +#define TC3_DMAC_ID_MC_SIZE 2 +#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger +#define TC3_GCLK_ID 27 // Index of Generic Clock +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 // Number of Output Waveforms +#define TC3_PERIOD_EXT 0 // Period feature implemented +#define TC3_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC3_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc4.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Instance description for TC4 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TC4_INSTANCE_ +#define _SAMD21_TC4_INSTANCE_ + +/* ========== Register definition for TC4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */ +#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */ +#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */ +#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */ +#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */ +#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ +#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ +#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ +#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ +#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ +#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ +#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ +#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ +#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ +#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */ +#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */ +#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */ +#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */ +#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */ +#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ +#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ +#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ +#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ +#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ +#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ +#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ +#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ +#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ +#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC4 peripheral ========== */ +#define TC4_CC8_NUM 2 // Number of 8-bit Counters +#define TC4_CC16_NUM 2 // Number of 16-bit Counters +#define TC4_CC32_NUM 2 // Number of 32-bit Counters +#define TC4_DITHERING_EXT 0 // Dithering feature implemented +#define TC4_DMAC_ID_MC_0 28 +#define TC4_DMAC_ID_MC_1 29 +#define TC4_DMAC_ID_MC_LSB 28 +#define TC4_DMAC_ID_MC_MSB 29 +#define TC4_DMAC_ID_MC_SIZE 2 +#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger +#define TC4_GCLK_ID 28 // Index of Generic Clock +#define TC4_MASTER 1 +#define TC4_OW_NUM 2 // Number of Output Waveforms +#define TC4_PERIOD_EXT 0 // Period feature implemented +#define TC4_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC4_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Instance description for TC5 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TC5_INSTANCE_ +#define _SAMD21_TC5_INSTANCE_ + +/* ========== Register definition for TC5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */ +#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */ +#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */ +#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */ +#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */ +#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */ +#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */ +#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ +#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ +#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ +#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */ +#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ +#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ +#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ +#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ +#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ +#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ +#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ +#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ +#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ +#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */ +#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */ +#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */ +#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */ +#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */ +#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */ +#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */ +#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ +#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ +#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ +#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */ +#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ +#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ +#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ +#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ +#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ +#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ +#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ +#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ +#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ +#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC5 peripheral ========== */ +#define TC5_CC8_NUM 2 // Number of 8-bit Counters +#define TC5_CC16_NUM 2 // Number of 16-bit Counters +#define TC5_CC32_NUM 2 // Number of 32-bit Counters +#define TC5_DITHERING_EXT 0 // Dithering feature implemented +#define TC5_DMAC_ID_MC_0 31 +#define TC5_DMAC_ID_MC_1 32 +#define TC5_DMAC_ID_MC_LSB 31 +#define TC5_DMAC_ID_MC_MSB 32 +#define TC5_DMAC_ID_MC_SIZE 2 +#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger +#define TC5_GCLK_ID 28 // Index of Generic Clock +#define TC5_MASTER 0 +#define TC5_OW_NUM 2 // Number of Output Waveforms +#define TC5_PERIOD_EXT 0 // Period feature implemented +#define TC5_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC5_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc6.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Instance description for TC6 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TC6_INSTANCE_ +#define _SAMD21_TC6_INSTANCE_ + +/* ========== Register definition for TC6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A */ +#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request */ +#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear */ +#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set */ +#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C */ +#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Control */ +#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control */ +#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */ +#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */ +#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */ +#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status */ +#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */ +#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ +#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ +#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */ +#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ +#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ +#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */ +#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */ +#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ +#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */ +#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */ +#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */ +#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */ +#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */ +#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */ +#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */ +#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */ +#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */ +#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */ +#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */ +#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */ +#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ +#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ +#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */ +#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ +#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ +#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */ +#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */ +#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ +#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC6 peripheral ========== */ +#define TC6_CC8_NUM 2 // Number of 8-bit Counters +#define TC6_CC16_NUM 2 // Number of 16-bit Counters +#define TC6_CC32_NUM 2 // Number of 32-bit Counters +#define TC6_DITHERING_EXT 0 // Dithering feature implemented +#define TC6_DMAC_ID_MC_0 34 +#define TC6_DMAC_ID_MC_1 35 +#define TC6_DMAC_ID_MC_LSB 34 +#define TC6_DMAC_ID_MC_MSB 35 +#define TC6_DMAC_ID_MC_SIZE 2 +#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger +#define TC6_GCLK_ID 29 // Index of Generic Clock +#define TC6_MASTER 1 +#define TC6_OW_NUM 2 // Number of Output Waveforms +#define TC6_PERIOD_EXT 0 // Period feature implemented +#define TC6_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC6_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc7.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Instance description for TC7 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TC7_INSTANCE_ +#define _SAMD21_TC7_INSTANCE_ + +/* ========== Register definition for TC7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A */ +#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request */ +#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear */ +#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set */ +#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C */ +#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Control */ +#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control */ +#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */ +#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */ +#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */ +#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status */ +#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */ +#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ +#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ +#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */ +#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ +#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ +#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */ +#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */ +#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ +#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */ +#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */ +#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */ +#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */ +#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */ +#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */ +#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */ +#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */ +#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */ +#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */ +#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */ +#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */ +#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ +#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ +#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */ +#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ +#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ +#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */ +#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */ +#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ +#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC7 peripheral ========== */ +#define TC7_CC8_NUM 2 // Number of 8-bit Counters +#define TC7_CC16_NUM 2 // Number of 16-bit Counters +#define TC7_CC32_NUM 2 // Number of 32-bit Counters +#define TC7_DITHERING_EXT 0 // Dithering feature implemented +#define TC7_DMAC_ID_MC_0 37 +#define TC7_DMAC_ID_MC_1 38 +#define TC7_DMAC_ID_MC_LSB 37 +#define TC7_DMAC_ID_MC_MSB 38 +#define TC7_DMAC_ID_MC_SIZE 2 +#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger +#define TC7_GCLK_ID 29 // Index of Generic Clock +#define TC7_MASTER 0 +#define TC7_OW_NUM 2 // Number of Output Waveforms +#define TC7_PERIOD_EXT 0 // Period feature implemented +#define TC7_SHADOW_EXT 0 // Shadow feature implemented + +#endif /* _SAMD21_TC7_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief Instance description for TCC0 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TCC0_INSTANCE_ +#define _SAMD21_TCC0_INSTANCE_ + +/* ========== Register definition for TCC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#else +#define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC0 peripheral ========== */ +#define TCC0_CC_NUM 4 // Number of Compare/Capture units +#define TCC0_DITHERING 1 // Dithering feature implemented +#define TCC0_DMAC_ID_MC_0 14 +#define TCC0_DMAC_ID_MC_1 15 +#define TCC0_DMAC_ID_MC_2 16 +#define TCC0_DMAC_ID_MC_3 17 +#define TCC0_DMAC_ID_MC_LSB 14 +#define TCC0_DMAC_ID_MC_MSB 17 +#define TCC0_DMAC_ID_MC_SIZE 4 +#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger +#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented +#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) +#define TCC0_GCLK_ID 26 // Index of Generic Clock +#define TCC0_OTMX 1 // Output Matrix feature implemented +#define TCC0_OW_NUM 8 // Number of Output Waveforms +#define TCC0_PG 1 // Pattern Generation feature implemented +#define TCC0_SIZE 24 +#define TCC0_SWAP 1 // DTI outputs swap feature implemented +#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAMD21_TCC0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,122 @@ +/** + * \file + * + * \brief Instance description for TCC1 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TCC1_INSTANCE_ +#define _SAMD21_TCC1_INSTANCE_ + +/* ========== Register definition for TCC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#else +#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC1 peripheral ========== */ +#define TCC1_CC_NUM 2 // Number of Compare/Capture units +#define TCC1_DITHERING 1 // Dithering feature implemented +#define TCC1_DMAC_ID_MC_0 19 +#define TCC1_DMAC_ID_MC_1 20 +#define TCC1_DMAC_ID_MC_LSB 19 +#define TCC1_DMAC_ID_MC_MSB 20 +#define TCC1_DMAC_ID_MC_SIZE 2 +#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger +#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC1_EXT 24 // Coding of implemented extended features +#define TCC1_GCLK_ID 26 // Index of Generic Clock +#define TCC1_OTMX 0 // Output Matrix feature implemented +#define TCC1_OW_NUM 4 // Number of Output Waveforms +#define TCC1_PG 1 // Pattern Generation feature implemented +#define TCC1_SIZE 24 +#define TCC1_SWAP 0 // DTI outputs swap feature implemented +#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAMD21_TCC1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief Instance description for TCC2 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_TCC2_INSTANCE_ +#define _SAMD21_TCC2_INSTANCE_ + +/* ========== Register definition for TCC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#else +#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC2 peripheral ========== */ +#define TCC2_CC_NUM 2 // Number of Compare/Capture units +#define TCC2_DITHERING 0 // Dithering feature implemented +#define TCC2_DMAC_ID_MC_0 22 +#define TCC2_DMAC_ID_MC_1 23 +#define TCC2_DMAC_ID_MC_LSB 22 +#define TCC2_DMAC_ID_MC_MSB 23 +#define TCC2_DMAC_ID_MC_SIZE 2 +#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger +#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC2_EXT 0 // Coding of implemented extended features +#define TCC2_GCLK_ID 27 // Index of Generic Clock +#define TCC2_OTMX 0 // Output Matrix feature implemented +#define TCC2_OW_NUM 2 // Number of Output Waveforms +#define TCC2_PG 0 // Pattern Generation feature implemented +#define TCC2_SIZE 16 +#define TCC2_SWAP 0 // DTI outputs swap feature implemented +#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAMD21_TCC2_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_usb.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,347 @@ +/** + * \file + * + * \brief Instance description for USB + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_USB_INSTANCE_ +#define _SAMD21_USB_INSTANCE_ + +/* ========== Register definition for USB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USB_CTRLA (0x41005000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (0x41005002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (0x41005003U) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (0x4100500DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (0x41005024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (0x41005028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (0x41005008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (0x4100500AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (0x4100500CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#else +#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (*(RwReg *)0x41005024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for USB peripheral ========== */ +#define USB_EPT_NBR 8 // Number of USB end points (obsolete) +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 6 // Index of Generic Clock +#define USB_PIPE_NUM 8 // Number of USB pipes + +#endif /* _SAMD21_USB_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_wdt.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_WDT_INSTANCE_ +#define _SAMD21_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status */ +#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for WDT peripheral ========== */ +#define WDT_GCLK_ID 3 // Index of Generic Clock + +#endif /* _SAMD21_WDT_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,931 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMR21G18A + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMR21G18A_PIO_ +#define _SAMR21G18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ +#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */ +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ +#define MUX_PA28H_GCLK_IO0 7L +#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) +#define PORT_PA28H_GCLK_IO0 (1ul << 28) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PC16F_GCLK_IO1 80L /**< \brief GCLK signal: IO1 on PC16 mux F */ +#define MUX_PC16F_GCLK_IO1 5L +#define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) +#define PORT_PC16F_GCLK_IO1 (1ul << 16) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ +#define MUX_PA28A_EIC_EXTINT8 0L +#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) +#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA28F_SERCOM3_PAD1 28L /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ +#define MUX_PA28F_SERCOM3_PAD1 5L +#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) +#define PORT_PA28F_SERCOM3_PAD1 (1ul << 28) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PC19F_SERCOM4_PAD0 83L /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ +#define MUX_PC19F_SERCOM4_PAD0 5L +#define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) +#define PORT_PC19F_SERCOM4_PAD0 (1ul << 19) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ +#define MUX_PB31F_SERCOM4_PAD1 5L +#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) +#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 2L +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ +#define MUX_PB30F_SERCOM4_PAD2 5L +#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) +#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 2L +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) +#define PIN_PC18F_SERCOM4_PAD3 82L /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ +#define MUX_PC18F_SERCOM4_PAD3 5L +#define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) +#define PORT_PC18F_SERCOM4_PAD3 (1ul << 18) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 4L +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (1ul << 18) +#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 4L +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (1ul << 14) +#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 4L +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (1ul << 19) +#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 4L +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (1ul << 15) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 4L +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (1ul << 22) +#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 4L +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (1ul << 8) +#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 4L +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (1ul << 23) +#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 4L +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (1ul << 9) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 4L +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (1ul << 24) +#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 4L +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (1ul << 14) +#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 4L +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (1ul << 25) +#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 4L +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for RFCTRL peripheral ========== */ +#define PIN_PA08F_RFCTRL_FECTRL0 8L /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ +#define MUX_PA08F_RFCTRL_FECTRL0 5L +#define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) +#define PORT_PA08F_RFCTRL_FECTRL0 (1ul << 8) +#define PIN_PA09F_RFCTRL_FECTRL1 9L /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ +#define MUX_PA09F_RFCTRL_FECTRL1 5L +#define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) +#define PORT_PA09F_RFCTRL_FECTRL1 (1ul << 9) +#define PIN_PA12F_RFCTRL_FECTRL2 12L /**< \brief RFCTRL signal: FECTRL2 on PA12 mux F */ +#define MUX_PA12F_RFCTRL_FECTRL2 5L +#define PINMUX_PA12F_RFCTRL_FECTRL2 ((PIN_PA12F_RFCTRL_FECTRL2 << 16) | MUX_PA12F_RFCTRL_FECTRL2) +#define PORT_PA12F_RFCTRL_FECTRL2 (1ul << 12) +#define PIN_PA13F_RFCTRL_FECTRL3 13L /**< \brief RFCTRL signal: FECTRL3 on PA13 mux F */ +#define MUX_PA13F_RFCTRL_FECTRL3 5L +#define PINMUX_PA13F_RFCTRL_FECTRL3 ((PIN_PA13F_RFCTRL_FECTRL3 << 16) | MUX_PA13F_RFCTRL_FECTRL3) +#define PORT_PA13F_RFCTRL_FECTRL3 (1ul << 13) +#define PIN_PA14F_RFCTRL_FECTRL4 14L /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ +#define MUX_PA14F_RFCTRL_FECTRL4 5L +#define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) +#define PORT_PA14F_RFCTRL_FECTRL4 (1ul << 14) +#define PIN_PA15F_RFCTRL_FECTRL5 15L /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ +#define MUX_PA15F_RFCTRL_FECTRL5 5L +#define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) +#define PORT_PA15F_RFCTRL_FECTRL5 (1ul << 15) + +#endif /* _SAMR21G18A_PIO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Top header file for SAMD21 + * + * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMD21_ +#define _SAMD21_ + +/** + * \defgroup SAMD21_definitions SAMD21 Device Definitions + * \brief SAMD21 CMSIS Definitions. + */ + +#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__) +#include "samd21e15a.h" +#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__) +#include "samd21e16a.h" +#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__) +#include "samd21e17a.h" +#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__) +#include "samd21e18a.h" +#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__) +#include "samd21g15a.h" +#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__) +#include "samd21g16a.h" +#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__) +#include "samd21g17a.h" +#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__) +#include "samd21g18a.h" +#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__) +#include "samd21j15a.h" +#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__) +#include "samd21j16a.h" +#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__) +#include "samd21j17a.h" +#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__) +#include "samd21j18a.h" +#else +#error Library does not support the specified device. +#endif + +#endif /* _SAMD21_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21j18a.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,578 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMD21J18A_
+#define _SAMD21J18A_
+
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
+ * This file defines all structures and symbols for SAMD21J18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_api Peripheral Software API */
+/*@{*/
+
+#include "comp_ac.h"
+#include "comp_adc.h"
+#include "comp_dac.h"
+#include "comp_dmac.h"
+#include "comp_dsu.h"
+#include "comp_eic.h"
+#include "comp_evsys.h"
+#include "comp_gclk.h"
+#include "comp_hmatrixb.h"
+#include "comp_i2s.h"
+#include "comp_mtb.h"
+#include "comp_nvmctrl.h"
+#include "comp_pac.h"
+#include "comp_pm.h"
+#include "comp_port.h"
+#include "comp_rtc.h"
+#include "comp_sercom.h"
+#include "comp_sysctrl.h"
+#include "comp_tc.h"
+#include "comp_tcc.h"
+#include "comp_usb.h"
+#include "comp_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "ins_ac.h"
+#include "ins_adc.h"
+#include "ins_dac.h"
+#include "ins_dmac.h"
+#include "ins_dsu.h"
+#include "ins_eic.h"
+#include "ins_evsys.h"
+#include "ins_gclk.h"
+#include "ins_sbmatrix.h"
+#include "ins_i2s.h"
+#include "ins_mtb.h"
+#include "ins_nvmctrl.h"
+#include "ins_pac0.h"
+#include "ins_pac1.h"
+#include "ins_pac2.h"
+#include "ins_pm.h"
+#include "ins_port.h"
+#include "ins_rtc.h"
+#include "ins_sercom0.h"
+#include "ins_sercom1.h"
+#include "ins_sercom2.h"
+#include "ins_sercom3.h"
+#include "ins_sercom4.h"
+#include "ins_sercom5.h"
+#include "ins_sysctrl.h"
+#include "ins_tc3.h"
+#include "ins_tc4.h"
+#include "ins_tc5.h"
+#include "ins_tc6.h"
+#include "ins_tc7.h"
+#include "ins_tcc0.h"
+#include "ins_tcc1.h"
+#include "ins_tcc2.h"
+#include "ins_usb.h"
+#include "ins_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio_samd21j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
+#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010000UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J18A_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief Top header file for SAMR21 + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAMR21_ +#define _SAMR21_ + +/** + * \defgroup SAMR21_definitions SAMR21 Device Definitions + * \brief SAMR21 CMSIS Definitions. + */ + +#if defined(__SAMR21E16A__) || defined(__ATSAMR21E16A__) +#include "samr21e16a.h" +#elif defined(__SAMR21E17A__) || defined(__ATSAMR21E17A__) +#include "samr21e17a.h" +#elif defined(__SAMR21E18A__) || defined(__ATSAMR21E18A__) +#include "samr21e18a.h" +#elif defined(__SAMR21G16A__) || defined(__ATSAMR21G16A__) +#include "samr21g16a.h" +#elif defined(__SAMR21G17A__) || defined(__ATSAMR21G17A__) +#include "samr21g17a.h" +#elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__) +#include "samr21g18a.h" +#else +#error Library does not support the specified device. +#endif + +#endif /* _SAMR21_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,561 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMR21G18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _SAMR21G18A_
+#define _SAMR21G18A_
+
+/**
+ * \ingroup SAMR21_definitions
+ * \addtogroup SAMR21G18A_definitions SAMR21G18A definitions
+ * This file defines all structures and symbols for SAMR21G18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMR21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMR21G18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samr21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMR21G18A_api Peripheral Software API */
+/*@{*/
+
+#include "comp_ac.h"
+#include "comp_adc.h"
+#include "comp_dmac.h"
+#include "comp_dsu.h"
+#include "comp_eic.h"
+#include "comp_evsys.h"
+#include "comp_gclk.h"
+#include "comp_hmatrixb.h"
+#include "comp_mtb.h"
+#include "comp_nvmctrl.h"
+#include "comp_pac.h"
+#include "comp_pm.h"
+#include "comp_port.h"
+#include "comp_rfctrl.h"
+#include "comp_rtc.h"
+#include "comp_sercom.h"
+#include "comp_sysctrl.h"
+#include "comp_tc.h"
+#include "comp_tcc.h"
+#include "comp_usb.h"
+#include "comp_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMR21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMR21G18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "ins_ac.h"
+#include "ins_adc.h"
+#include "ins_dmac.h"
+#include "ins_dsu.h"
+#include "ins_eic.h"
+#include "ins_evsys.h"
+#include "ins_gclk.h"
+#include "ins_sbmatrix.h"
+#include "ins_mtb.h"
+#include "ins_nvmctrl.h"
+#include "ins_pac0.h"
+#include "ins_pac1.h"
+#include "ins_pac2.h"
+#include "ins_pm.h"
+#include "ins_port.h"
+#include "ins_rfctrl.h"
+#include "ins_rtc.h"
+#include "ins_sercom0.h"
+#include "ins_sercom1.h"
+#include "ins_sercom2.h"
+#include "ins_sercom3.h"
+#include "ins_sercom4.h"
+#include "ins_sercom5.h"
+#include "ins_sysctrl.h"
+#include "ins_tc3.h"
+#include "ins_tc4.h"
+#include "ins_tc5.h"
+#include "ins_tcc0.h"
+#include "ins_tcc1.h"
+#include "ins_tcc2.h"
+#include "ins_usb.h"
+#include "ins_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMR21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMR21G18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_RFCTRL 85 /**< \brief RF233 control module (RFCTRL) */
+
+#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMR21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMR21G18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RFCTRL (0x42005400UL) /**< \brief (RFCTRL) APB Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RFCTRL ((Rfctrl *)0x42005400UL) /**< \brief (RFCTRL) APB Base Address */
+#define RFCTRL_INST_NUM 1 /**< \brief (RFCTRL) Number of instances */
+#define RFCTRL_INSTS { RFCTRL } /**< \brief (RFCTRL) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMR21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMR21G18A_port PORT Definitions */
+/*@{*/
+
+#include "pio_samr21g18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMR21G18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
+#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010019UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 3
+#define SIP_CONFIG RF233
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMR21G18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMR21G18A_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/compiler.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1156 @@
+/**
+ * \file
+ *
+ * \brief Commonly used includes, types and macros.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef UTILS_COMPILER_H_INCLUDED
+#define UTILS_COMPILER_H_INCLUDED
+
+/**
+ * \defgroup group_sam0_utils Compiler abstraction layer and code utilities
+ *
+ * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices.
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.
+ *
+ * @{
+ */
+
+#if (defined __ICCARM__)
+# include <intrinsics.h>
+#endif
+
+#include <stddef.h>
+#include <parts.h>
+#include <status_codes.h>
+#include <preprocessor.h>
+#include <io.h>
+
+#ifndef __ASSEMBLY__
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * \def UNUSED
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define UNUSED(v) (void)(v)
+
+/**
+ * \def barrier
+ * \brief Memory barrier
+ */
+#ifdef __GNUC__
+# define barrier() asm volatile("" ::: "memory")
+#else
+# define barrier() asm ("")
+#endif
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param[in] arg The pragma directive as it would appear after \e \#pragma
+ * (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union definitions.
+ */
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
+
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#elif (defined __ICCARM__)
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
+#endif
+
+/**
+ * \brief Set word-aligned boundary.
+ */
+#if (defined __GNUC__) || defined(__CC_ARM)
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
+#elif (defined __ICCARM__)
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
+#endif
+
+/**
+ * \def __always_inline
+ * \brief The function should always be inlined.
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and inline the function no matter how big it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+# define __always_inline __forceinline
+#elif (defined __GNUC__)
+# define __always_inline __attribute__((__always_inline__))
+#elif (defined __ICCARM__)
+# define __always_inline _Pragma("inline=forced")
+#endif
+
+/**
+ * \def __no_inline
+ * \brief The function should never be inlined
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and not inline the function no matter how small it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+# define __no_inline __attribute__((noinline))
+#elif (defined __GNUC__)
+# define __no_inline __attribute__((noinline))
+#elif (defined __ICCARM__)
+# define __no_inline _Pragma("inline=never")
+#endif
+
+
+/** \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is false. If it is, a fatal error is
+ * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO
+ * is defined, a unit test version of the macro is used, to allow execution
+ * of further tests after a false expression.
+ *
+ * \param[in] expr Expression to evaluate and supposed to be nonzero.
+ */
+#if defined(_ASSERT_ENABLE_)
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
+# include "unit_test/suite.h"
+# else
+# undef TEST_SUITE_DEFINE_ASSERT_MACRO
+# define Assert(expr) \
+ {\
+ if (!(expr)) asm("BKPT #0");\
+ }
+# endif
+#else
+# define Assert(expr) ((void) 0)
+#endif
+
+/* Define WEAK attribute */
+#if defined ( __CC_ARM )
+# define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ )
+# define WEAK __weak
+#elif defined ( __GNUC__ )
+# define WEAK __attribute__ ((weak))
+#endif
+
+/* Define NO_INIT attribute */
+#if defined ( __CC_ARM )
+# define NO_INIT __attribute__((zero_init))
+#elif defined ( __ICCARM__ )
+# define NO_INIT __no_init
+#elif defined ( __GNUC__ )
+# define NO_INIT __attribute__((section(".no_init")))
+#endif
+
+#include "interrupt.h"
+
+/** \name Usual Types
+ * @{ */
+#ifndef __cplusplus
+# if !defined(__bool_true_false_are_defined)
+typedef unsigned char bool;
+# endif
+#endif
+typedef uint16_t le16_t;
+typedef uint16_t be16_t;
+typedef uint32_t le32_t;
+typedef uint32_t be32_t;
+typedef uint32_t iram_size_t;
+/** @} */
+
+/** \name Aliasing Aggregate Types
+ * @{ */
+
+/** 16-bit union. */
+typedef union {
+ int16_t s16;
+ uint16_t u16;
+ int8_t s8[2];
+ uint8_t u8[2];
+} Union16;
+
+/** 32-bit union. */
+typedef union {
+ int32_t s32;
+ uint32_t u32;
+ int16_t s16[2];
+ uint16_t u16[2];
+ int8_t s8[4];
+ uint8_t u8[4];
+} Union32;
+
+/** 64-bit union. */
+typedef union {
+ int64_t s64;
+ uint64_t u64;
+ int32_t s32[2];
+ uint32_t u32[2];
+ int16_t s16[4];
+ uint16_t u16[4];
+ int8_t s8[8];
+ uint8_t u8[8];
+} Union64;
+
+/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union {
+ int64_t *s64ptr;
+ uint64_t *u64ptr;
+ int32_t *s32ptr;
+ uint32_t *u32ptr;
+ int16_t *s16ptr;
+ uint16_t *u16ptr;
+ int8_t *s8ptr;
+ uint8_t *u8ptr;
+} UnionPtr;
+
+/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union {
+ volatile int64_t *s64ptr;
+ volatile uint64_t *u64ptr;
+ volatile int32_t *s32ptr;
+ volatile uint32_t *u32ptr;
+ volatile int16_t *s16ptr;
+ volatile uint16_t *u16ptr;
+ volatile int8_t *s8ptr;
+ volatile uint8_t *u8ptr;
+} UnionVPtr;
+
+/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union {
+ const int64_t *s64ptr;
+ const uint64_t *u64ptr;
+ const int32_t *s32ptr;
+ const uint32_t *u32ptr;
+ const int16_t *s16ptr;
+ const uint16_t *u16ptr;
+ const int8_t *s8ptr;
+ const uint8_t *u8ptr;
+} UnionCPtr;
+
+/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union {
+ const volatile int64_t *s64ptr;
+ const volatile uint64_t *u64ptr;
+ const volatile int32_t *s32ptr;
+ const volatile uint32_t *u32ptr;
+ const volatile int16_t *s16ptr;
+ const volatile uint16_t *u16ptr;
+ const volatile int8_t *s8ptr;
+ const volatile uint8_t *u8ptr;
+} UnionCVPtr;
+
+/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct {
+ int64_t *s64ptr;
+ uint64_t *u64ptr;
+ int32_t *s32ptr;
+ uint32_t *u32ptr;
+ int16_t *s16ptr;
+ uint16_t *u16ptr;
+ int8_t *s8ptr;
+ uint8_t *u8ptr;
+} StructPtr;
+
+/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct {
+ volatile int64_t *s64ptr;
+ volatile uint64_t *u64ptr;
+ volatile int32_t *s32ptr;
+ volatile uint32_t *u32ptr;
+ volatile int16_t *s16ptr;
+ volatile uint16_t *u16ptr;
+ volatile int8_t *s8ptr;
+ volatile uint8_t *u8ptr;
+} StructVPtr;
+
+/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct {
+ const int64_t *s64ptr;
+ const uint64_t *u64ptr;
+ const int32_t *s32ptr;
+ const uint32_t *u32ptr;
+ const int16_t *s16ptr;
+ const uint16_t *u16ptr;
+ const int8_t *s8ptr;
+ const uint8_t *u8ptr;
+} StructCPtr;
+
+/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct {
+ const volatile int64_t *s64ptr;
+ const volatile uint64_t *u64ptr;
+ const volatile int32_t *s32ptr;
+ const volatile uint32_t *u32ptr;
+ const volatile int16_t *s16ptr;
+ const volatile uint16_t *u16ptr;
+ const volatile int8_t *s8ptr;
+ const volatile uint8_t *u8ptr;
+} StructCVPtr;
+
+/** @} */
+
+#endif /* #ifndef __ASSEMBLY__ */
+
+/** \name Usual Constants
+ * @{ */
+#define DISABLE 0
+#define ENABLE 1
+
+#ifndef __cplusplus
+# if !defined(__bool_true_false_are_defined)
+# define false 0
+# define true 1
+# endif
+#endif
+/** @} */
+
+#ifndef __ASSEMBLY__
+
+/** \name Optimization Control
+ * @{ */
+
+/**
+ * \def likely(exp)
+ * \brief The expression \a exp is likely to be true
+ */
+#if !defined(likely) || defined(__DOXYGEN__)
+# define likely(exp) (exp)
+#endif
+
+/**
+ * \def unlikely(exp)
+ * \brief The expression \a exp is unlikely to be true
+ */
+#if !defined(unlikely) || defined(__DOXYGEN__)
+# define unlikely(exp) (exp)
+#endif
+
+/**
+ * \def is_constant(exp)
+ * \brief Determine if an expression evaluates to a constant value.
+ *
+ * \param[in] exp Any expression
+ *
+ * \return true if \a exp is constant, false otherwise.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define is_constant(exp) __builtin_constant_p(exp)
+#else
+# define is_constant(exp) (0)
+#endif
+
+/** @} */
+
+/** \name Bit-Field Handling
+ * @{ */
+
+/** \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read bits from.
+ * \param[in] mask Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask) ((value) & (mask))
+
+/** \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue to write bits to.
+ * \param[in] mask Bit-mask indicating bits to write.
+ * \param[in] bits Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\
+ ((bits ) & (mask)))
+
+/** \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value of which to test bits.
+ * \param[in] mask Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)
+
+/** \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue of which to clear bits.
+ * \param[in] mask Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
+
+/** \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue of which to set bits.
+ * \param[in] mask Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))
+
+/** \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue of which to toggle bits.
+ * \param[in] mask Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
+
+/** \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read a bit-field from.
+ * \param[in] mask Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))
+
+/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue to write a bit-field to.
+ * \param[in] mask Bit-mask indicating the bit-field to write.
+ * \param[in] bitfield Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask)))
+
+/** @} */
+
+
+/** \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ *
+ * @{ */
+
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define clz(u) __builtin_clz(u)
+#else
+# define clz(u) (((u) == 0) ? 32 : \
+ ((u) & (1ul << 31)) ? 0 : \
+ ((u) & (1ul << 30)) ? 1 : \
+ ((u) & (1ul << 29)) ? 2 : \
+ ((u) & (1ul << 28)) ? 3 : \
+ ((u) & (1ul << 27)) ? 4 : \
+ ((u) & (1ul << 26)) ? 5 : \
+ ((u) & (1ul << 25)) ? 6 : \
+ ((u) & (1ul << 24)) ? 7 : \
+ ((u) & (1ul << 23)) ? 8 : \
+ ((u) & (1ul << 22)) ? 9 : \
+ ((u) & (1ul << 21)) ? 10 : \
+ ((u) & (1ul << 20)) ? 11 : \
+ ((u) & (1ul << 19)) ? 12 : \
+ ((u) & (1ul << 18)) ? 13 : \
+ ((u) & (1ul << 17)) ? 14 : \
+ ((u) & (1ul << 16)) ? 15 : \
+ ((u) & (1ul << 15)) ? 16 : \
+ ((u) & (1ul << 14)) ? 17 : \
+ ((u) & (1ul << 13)) ? 18 : \
+ ((u) & (1ul << 12)) ? 19 : \
+ ((u) & (1ul << 11)) ? 20 : \
+ ((u) & (1ul << 10)) ? 21 : \
+ ((u) & (1ul << 9)) ? 22 : \
+ ((u) & (1ul << 8)) ? 23 : \
+ ((u) & (1ul << 7)) ? 24 : \
+ ((u) & (1ul << 6)) ? 25 : \
+ ((u) & (1ul << 5)) ? 26 : \
+ ((u) & (1ul << 4)) ? 27 : \
+ ((u) & (1ul << 3)) ? 28 : \
+ ((u) & (1ul << 2)) ? 29 : \
+ ((u) & (1ul << 1)) ? 30 : \
+ 31)
+#endif
+
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define ctz(u) __builtin_ctz(u)
+#else
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \
+ (u) & (1ul << 1) ? 1 : \
+ (u) & (1ul << 2) ? 2 : \
+ (u) & (1ul << 3) ? 3 : \
+ (u) & (1ul << 4) ? 4 : \
+ (u) & (1ul << 5) ? 5 : \
+ (u) & (1ul << 6) ? 6 : \
+ (u) & (1ul << 7) ? 7 : \
+ (u) & (1ul << 8) ? 8 : \
+ (u) & (1ul << 9) ? 9 : \
+ (u) & (1ul << 10) ? 10 : \
+ (u) & (1ul << 11) ? 11 : \
+ (u) & (1ul << 12) ? 12 : \
+ (u) & (1ul << 13) ? 13 : \
+ (u) & (1ul << 14) ? 14 : \
+ (u) & (1ul << 15) ? 15 : \
+ (u) & (1ul << 16) ? 16 : \
+ (u) & (1ul << 17) ? 17 : \
+ (u) & (1ul << 18) ? 18 : \
+ (u) & (1ul << 19) ? 19 : \
+ (u) & (1ul << 20) ? 20 : \
+ (u) & (1ul << 21) ? 21 : \
+ (u) & (1ul << 22) ? 22 : \
+ (u) & (1ul << 23) ? 23 : \
+ (u) & (1ul << 24) ? 24 : \
+ (u) & (1ul << 25) ? 25 : \
+ (u) & (1ul << 26) ? 26 : \
+ (u) & (1ul << 27) ? 27 : \
+ (u) & (1ul << 28) ? 28 : \
+ (u) & (1ul << 29) ? 29 : \
+ (u) & (1ul << 30) ? 30 : \
+ (u) & (1ul << 31) ? 31 : \
+ 32)
+#endif
+
+/** @} */
+
+
+/** \name Bit Reversing
+ * @{ */
+
+/** \brief Reverses the bits of \a u8.
+ *
+ * \param[in] u8 U8 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u8 with reversed bits.
+ */
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
+
+/** \brief Reverses the bits of \a u16.
+ *
+ * \param[in] u16 U16 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u16 with reversed bits.
+ */
+#define bit_reverse16(u16) ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16))
+
+/** \brief Reverses the bits of \a u32.
+ *
+ * \param[in] u32 U32 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u32 with reversed bits.
+ */
+#define bit_reverse32(u32) __RBIT(u32)
+
+/** \brief Reverses the bits of \a u64.
+ *
+ * \param[in] u64 U64 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u64 with reversed bits.
+ */
+#define bit_reverse64(u64) ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\
+ ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32)))
+
+/** @} */
+
+
+/** \name Alignment
+ * @{ */
+
+/** \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n) (!Tst_bits( val, (n) - 1 ) )
+
+/** \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align(val, n) ( Rd_bits( val, (n) - 1 ) )
+
+/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param[in] lval Input/output lvalue.
+ * \param[in] n Boundary.
+ * \param[in] alg Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )
+
+/** \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up( val, n) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/** \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n) ( (val) & ~((n) - 1))
+
+/** @} */
+
+
+/** \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ * - Abs, Min and Max to apply to constant expressions (values known at
+ * compile time);
+ * - abs, min and max to apply to non-constant expressions (values unknown at
+ * compile time), abs is found in stdlib.h.
+ *
+ * @{ */
+
+/** \brief Takes the absolute value of \a a.
+ *
+ * \param[in] a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))
+
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b) (((a) < (b)) ? (a) : (b))
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b) (((a) > (b)) ? (a) : (b))
+
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define min(a, b) Min(a, b)
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define max(a, b) Max(a, b)
+
+/** @} */
+
+
+/** \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param[in] addr Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr) ((*(void (*)(void))(addr))())
+
+
+/** \name MCU Endianism Handling
+ * ARM is MCU little endian.
+ *
+ * @{ */
+#define BE16(x) Swap16(x)
+#define LE16(x) (x)
+
+#define le16_to_cpu(x) (x)
+#define cpu_to_le16(x) (x)
+#define LE16_TO_CPU(x) (x)
+#define CPU_TO_LE16(x) (x)
+
+#define be16_to_cpu(x) Swap16(x)
+#define cpu_to_be16(x) Swap16(x)
+#define BE16_TO_CPU(x) Swap16(x)
+#define CPU_TO_BE16(x) Swap16(x)
+
+#define le32_to_cpu(x) (x)
+#define cpu_to_le32(x) (x)
+#define LE32_TO_CPU(x) (x)
+#define CPU_TO_LE32(x) (x)
+
+#define be32_to_cpu(x) swap32(x)
+#define cpu_to_be32(x) swap32(x)
+#define BE32_TO_CPU(x) swap32(x)
+#define CPU_TO_BE32(x) swap32(x)
+/** @} */
+
+
+/** \name Endianism Conversion
+ *
+ * The same considerations as for clz and ctz apply here but GCC's
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ * at compile time);
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ * unknown at compile time).
+ *
+ * @{ */
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\
+ ((uint16_t)(u16) << 8)))
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\
+ ((uint32_t)Swap16((uint32_t)(u32)) << 16)))
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\
+ ((uint64_t)Swap32((uint64_t)(u64)) << 32)))
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap16(u16) Swap16(u16)
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+# define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32)))
+#else
+# define swap32(u32) Swap32(u32)
+#endif
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+# define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64)))
+#else
+# define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\
+ ((uint64_t)swap32((uint64_t)(u64)) << 32)))
+#endif
+
+/** @} */
+
+
+/** \name Target Abstraction
+ *
+ * @{ */
+
+#define _GLOBEXT_ extern /**< extern storage-class specifier. */
+#define _CONST_TYPE_ const /**< const type qualifier. */
+#define _MEM_TYPE_SLOW_ /**< Slow memory type. */
+#define _MEM_TYPE_MEDFAST_ /**< Fairly fast memory type. */
+#define _MEM_TYPE_FAST_ /**< Fast memory type. */
+
+#define memcmp_ram2ram memcmp /**< Target-specific memcmp of RAM to RAM. */
+#define memcmp_code2ram memcmp /**< Target-specific memcmp of RAM to NVRAM. */
+#define memcpy_ram2ram memcpy /**< Target-specific memcpy from RAM to RAM. */
+#define memcpy_code2ram memcpy /**< Target-specific memcpy from NVRAM to RAM. */
+
+/** @} */
+
+/**
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
+ * integer arithmetic.
+ *
+ * \param[in] a An integer
+ * \param[in] b Another integer
+ *
+ * \return (\a a / \a b) rounded up to the nearest integer.
+ */
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))
+
+#endif /* #ifndef __ASSEMBLY__ */
+#ifdef __ICCARM__
+/** \name Compiler Keywords
+ *
+ * Port of some keywords from GCC to IAR Embedded Workbench.
+ *
+ * @{ */
+
+#define __asm__ asm
+#define __inline__ inline
+#define __volatile__
+
+/** @} */
+
+#endif
+
+#define FUNC_PTR void *
+/**
+ * \def unused
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define unused(v) do { (void)(v); } while(0)
+
+/* Define RAMFUNC attribute */
+#if defined ( __CC_ARM ) /* Keil uVision 4 */
+# define RAMFUNC __attribute__ ((section(".ramfunc")))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+# define RAMFUNC __ramfunc
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
+# define RAMFUNC __attribute__ ((section(".ramfunc")))
+#endif
+
+/* Define OPTIMIZE_HIGH attribute */
+#if defined ( __CC_ARM ) /* Keil uVision 4 */
+# define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+# define OPTIMIZE_HIGH _Pragma("optimize=high")
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
+# define OPTIMIZE_HIGH __attribute__((optimize(s)))
+#endif
+#define PASS 0
+#define FAIL 1
+#define LOW 0
+#define HIGH 1
+
+typedef int8_t S8 ; //!< 8-bit signed integer.
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.
+typedef int16_t S16; //!< 16-bit signed integer.
+typedef uint16_t U16; //!< 16-bit unsigned integer.
+typedef int32_t S32; //!< 32-bit signed integer.
+typedef uint32_t U32; //!< 32-bit unsigned integer.
+typedef int64_t S64; //!< 64-bit signed integer.
+typedef uint64_t U64; //!< 64-bit unsigned integer.
+typedef float F32; //!< 32-bit floating-point number.
+typedef double F64; //!< 64-bit floating-point number.
+
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
+
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
+
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
+
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
+
+#if defined(__ICCARM__)
+#define SHORTENUM __packed
+#elif defined(__GNUC__)
+#define SHORTENUM __attribute__((packed))
+#endif
+
+/* No operation */
+#if defined(__ICCARM__)
+#define nop() __no_operation()
+#elif defined(__GNUC__)
+#define nop() (__NOP())
+#endif
+
+#define FLASH_DECLARE(x) const x
+#define FLASH_EXTERN(x) extern const x
+#define PGM_READ_BYTE(x) *(x)
+#define PGM_READ_WORD(x) *(x)
+#define MEMCPY_ENDIAN memcpy
+#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
+
+/*Defines the Flash Storage for the request and response of MAC*/
+#define CMD_ID_OCTET (0)
+
+/* Converting of values from CPU endian to little endian. */
+#define CPU_ENDIAN_TO_LE16(x) (x)
+#define CPU_ENDIAN_TO_LE32(x) (x)
+#define CPU_ENDIAN_TO_LE64(x) (x)
+
+/* Converting of values from little endian to CPU endian. */
+#define LE16_TO_CPU_ENDIAN(x) (x)
+#define LE32_TO_CPU_ENDIAN(x) (x)
+#define LE64_TO_CPU_ENDIAN(x) (x)
+
+/* Converting of constants from little endian to CPU endian. */
+#define CLE16_TO_CPU_ENDIAN(x) (x)
+#define CLE32_TO_CPU_ENDIAN(x) (x)
+#define CLE64_TO_CPU_ENDIAN(x) (x)
+
+/* Converting of constants from CPU endian to little endian. */
+#define CCPU_ENDIAN_TO_LE16(x) (x)
+#define CCPU_ENDIAN_TO_LE32(x) (x)
+#define CCPU_ENDIAN_TO_LE64(x) (x)
+
+#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))
+#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))
+
+/**
+ * @brief Converts a 64-Bit value into a 8 Byte array
+ *
+ * @param[in] value 64-Bit value
+ * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
+{
+ uint8_t index = 0;
+
+ while (index < 8) {
+ data[index++] = value & 0xFF;
+ value = value >> 8;
+ }
+}
+
+/**
+ * @brief Converts a 16-Bit value into a 2 Byte array
+ *
+ * @param[in] value 16-Bit value
+ * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/*
+ * @brief Converts a 2 Byte array into a 16-Bit value
+ *
+ * @param data Specifies the pointer to the 2 Byte array
+ *
+ * @return 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
+{
+ return (data[0] | ((uint16_t)data[1] << 8));
+}
+
+/* Converts a 4 Byte array into a 32-Bit value */
+static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
+{
+ union {
+ uint32_t u32;
+ uint8_t u8[4];
+ } long_addr;
+ uint8_t index;
+ for (index = 0; index < 4; index++) {
+ long_addr.u8[index] = *data++;
+ }
+ return long_addr.u32;
+}
+
+/**
+ * @brief Converts a 8 Byte array into a 64-Bit value
+ *
+ * @param data Specifies the pointer to the 8 Byte array
+ *
+ * @return 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
+{
+ union {
+ uint64_t u64;
+ uint8_t u8[8];
+ } long_addr;
+
+ uint8_t index;
+
+ for (index = 0; index < 8; index++) {
+ long_addr.u8[index] = *data++;
+ }
+
+ return long_addr.u64;
+}
+
+/** @} */
+
+#endif /* UTILS_COMPILER_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/header_files/io.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,82 @@ +/** + * \file + * + * \brief Arch file for SAM0. + * + * This file defines common SAM0 series. + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _SAM_IO_ +#define _SAM_IO_ + +#include <stddef.h> +#include <stdint.h> +#include <stdbool.h> + + +/* SAM D20 family */ +#if (SAMD20) +# include "samd20.h" +#endif + +#if (SAMD21) +# include "samd21.h" +#endif + +#if (SAMR21) +# include "samr21.h" +#endif + +#if (SAMD10) +# include "samd10.h" +#endif + +#if (SAMD11) +# include "samd11.h" +#endif + +#if (SAML21) +# include "saml21.h" +#endif + +#endif /* _SAM_IO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrecursion.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,598 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor macro recursion utils.
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _MRECURSION_H_
+#define _MRECURSION_H_
+
+/**
+ * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+#define DEC_256 255
+#define DEC_255 254
+#define DEC_254 253
+#define DEC_253 252
+#define DEC_252 251
+#define DEC_251 250
+#define DEC_250 249
+#define DEC_249 248
+#define DEC_248 247
+#define DEC_247 246
+#define DEC_246 245
+#define DEC_245 244
+#define DEC_244 243
+#define DEC_243 242
+#define DEC_242 241
+#define DEC_241 240
+#define DEC_240 239
+#define DEC_239 238
+#define DEC_238 237
+#define DEC_237 236
+#define DEC_236 235
+#define DEC_235 234
+#define DEC_234 233
+#define DEC_233 232
+#define DEC_232 231
+#define DEC_231 230
+#define DEC_230 229
+#define DEC_229 228
+#define DEC_228 227
+#define DEC_227 226
+#define DEC_226 225
+#define DEC_225 224
+#define DEC_224 223
+#define DEC_223 222
+#define DEC_222 221
+#define DEC_221 220
+#define DEC_220 219
+#define DEC_219 218
+#define DEC_218 217
+#define DEC_217 216
+#define DEC_216 215
+#define DEC_215 214
+#define DEC_214 213
+#define DEC_213 212
+#define DEC_212 211
+#define DEC_211 210
+#define DEC_210 209
+#define DEC_209 208
+#define DEC_208 207
+#define DEC_207 206
+#define DEC_206 205
+#define DEC_205 204
+#define DEC_204 203
+#define DEC_203 202
+#define DEC_202 201
+#define DEC_201 200
+#define DEC_200 199
+#define DEC_199 198
+#define DEC_198 197
+#define DEC_197 196
+#define DEC_196 195
+#define DEC_195 194
+#define DEC_194 193
+#define DEC_193 192
+#define DEC_192 191
+#define DEC_191 190
+#define DEC_190 189
+#define DEC_189 188
+#define DEC_188 187
+#define DEC_187 186
+#define DEC_186 185
+#define DEC_185 184
+#define DEC_184 183
+#define DEC_183 182
+#define DEC_182 181
+#define DEC_181 180
+#define DEC_180 179
+#define DEC_179 178
+#define DEC_178 177
+#define DEC_177 176
+#define DEC_176 175
+#define DEC_175 174
+#define DEC_174 173
+#define DEC_173 172
+#define DEC_172 171
+#define DEC_171 170
+#define DEC_170 169
+#define DEC_169 168
+#define DEC_168 167
+#define DEC_167 166
+#define DEC_166 165
+#define DEC_165 164
+#define DEC_164 163
+#define DEC_163 162
+#define DEC_162 161
+#define DEC_161 160
+#define DEC_160 159
+#define DEC_159 158
+#define DEC_158 157
+#define DEC_157 156
+#define DEC_156 155
+#define DEC_155 154
+#define DEC_154 153
+#define DEC_153 152
+#define DEC_152 151
+#define DEC_151 150
+#define DEC_150 149
+#define DEC_149 148
+#define DEC_148 147
+#define DEC_147 146
+#define DEC_146 145
+#define DEC_145 144
+#define DEC_144 143
+#define DEC_143 142
+#define DEC_142 141
+#define DEC_141 140
+#define DEC_140 139
+#define DEC_139 138
+#define DEC_138 137
+#define DEC_137 136
+#define DEC_136 135
+#define DEC_135 134
+#define DEC_134 133
+#define DEC_133 132
+#define DEC_132 131
+#define DEC_131 130
+#define DEC_130 129
+#define DEC_129 128
+#define DEC_128 127
+#define DEC_127 126
+#define DEC_126 125
+#define DEC_125 124
+#define DEC_124 123
+#define DEC_123 122
+#define DEC_122 121
+#define DEC_121 120
+#define DEC_120 119
+#define DEC_119 118
+#define DEC_118 117
+#define DEC_117 116
+#define DEC_116 115
+#define DEC_115 114
+#define DEC_114 113
+#define DEC_113 112
+#define DEC_112 111
+#define DEC_111 110
+#define DEC_110 109
+#define DEC_109 108
+#define DEC_108 107
+#define DEC_107 106
+#define DEC_106 105
+#define DEC_105 104
+#define DEC_104 103
+#define DEC_103 102
+#define DEC_102 101
+#define DEC_101 100
+#define DEC_100 99
+#define DEC_99 98
+#define DEC_98 97
+#define DEC_97 96
+#define DEC_96 95
+#define DEC_95 94
+#define DEC_94 93
+#define DEC_93 92
+#define DEC_92 91
+#define DEC_91 90
+#define DEC_90 89
+#define DEC_89 88
+#define DEC_88 87
+#define DEC_87 86
+#define DEC_86 85
+#define DEC_85 84
+#define DEC_84 83
+#define DEC_83 82
+#define DEC_82 81
+#define DEC_81 80
+#define DEC_80 79
+#define DEC_79 78
+#define DEC_78 77
+#define DEC_77 76
+#define DEC_76 75
+#define DEC_75 74
+#define DEC_74 73
+#define DEC_73 72
+#define DEC_72 71
+#define DEC_71 70
+#define DEC_70 69
+#define DEC_69 68
+#define DEC_68 67
+#define DEC_67 66
+#define DEC_66 65
+#define DEC_65 64
+#define DEC_64 63
+#define DEC_63 62
+#define DEC_62 61
+#define DEC_61 60
+#define DEC_60 59
+#define DEC_59 58
+#define DEC_58 57
+#define DEC_57 56
+#define DEC_56 55
+#define DEC_55 54
+#define DEC_54 53
+#define DEC_53 52
+#define DEC_52 51
+#define DEC_51 50
+#define DEC_50 49
+#define DEC_49 48
+#define DEC_48 47
+#define DEC_47 46
+#define DEC_46 45
+#define DEC_45 44
+#define DEC_44 43
+#define DEC_43 42
+#define DEC_42 41
+#define DEC_41 40
+#define DEC_40 39
+#define DEC_39 38
+#define DEC_38 37
+#define DEC_37 36
+#define DEC_36 35
+#define DEC_35 34
+#define DEC_34 33
+#define DEC_33 32
+#define DEC_32 31
+#define DEC_31 30
+#define DEC_30 29
+#define DEC_29 28
+#define DEC_28 27
+#define DEC_27 26
+#define DEC_26 25
+#define DEC_25 24
+#define DEC_24 23
+#define DEC_23 22
+#define DEC_22 21
+#define DEC_21 20
+#define DEC_20 19
+#define DEC_19 18
+#define DEC_18 17
+#define DEC_17 16
+#define DEC_16 15
+#define DEC_15 14
+#define DEC_14 13
+#define DEC_13 12
+#define DEC_12 11
+#define DEC_11 10
+#define DEC_10 9
+#define DEC_9 8
+#define DEC_8 7
+#define DEC_7 6
+#define DEC_6 5
+#define DEC_5 4
+#define DEC_4 3
+#define DEC_3 2
+#define DEC_2 1
+#define DEC_1 0
+#define DEC_(n) DEC_##n
+
+
+/** Maximal number of repetitions supported by MRECURSION. */
+#define MRECURSION_LIMIT 256
+
+/** \brief Macro recursion.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count The number of repetitious calls to macro. Valid values
+ * range from 0 to MRECURSION_LIMIT.
+ * \param[in] macro A binary operation of the form macro(data, n). This macro
+ * is expanded by MRECURSION with the current repetition number
+ * and the auxiliary data argument.
+ * \param[in] data A recursive threshold, building on this to decline by times
+ * defined with param count.
+ *
+ * \return <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>
+ */
+#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data)
+
+#define MRECURSION0( macro, data)
+#define MRECURSION1( macro, data) MRECURSION0( macro, DEC_(data)) macro(data, 0)
+#define MRECURSION2( macro, data) MRECURSION1( macro, DEC_(data)) macro(data, 1)
+#define MRECURSION3( macro, data) MRECURSION2( macro, DEC_(data)) macro(data, 2)
+#define MRECURSION4( macro, data) MRECURSION3( macro, DEC_(data)) macro(data, 3)
+#define MRECURSION5( macro, data) MRECURSION4( macro, DEC_(data)) macro(data, 4)
+#define MRECURSION6( macro, data) MRECURSION5( macro, DEC_(data)) macro(data, 5)
+#define MRECURSION7( macro, data) MRECURSION6( macro, DEC_(data)) macro(data, 6)
+#define MRECURSION8( macro, data) MRECURSION7( macro, DEC_(data)) macro(data, 7)
+#define MRECURSION9( macro, data) MRECURSION8( macro, DEC_(data)) macro(data, 8)
+#define MRECURSION10( macro, data) MRECURSION9( macro, DEC_(data)) macro(data, 9)
+#define MRECURSION11( macro, data) MRECURSION10( macro, DEC_(data)) macro(data, 10)
+#define MRECURSION12( macro, data) MRECURSION11( macro, DEC_(data)) macro(data, 11)
+#define MRECURSION13( macro, data) MRECURSION12( macro, DEC_(data)) macro(data, 12)
+#define MRECURSION14( macro, data) MRECURSION13( macro, DEC_(data)) macro(data, 13)
+#define MRECURSION15( macro, data) MRECURSION14( macro, DEC_(data)) macro(data, 14)
+#define MRECURSION16( macro, data) MRECURSION15( macro, DEC_(data)) macro(data, 15)
+#define MRECURSION17( macro, data) MRECURSION16( macro, DEC_(data)) macro(data, 16)
+#define MRECURSION18( macro, data) MRECURSION17( macro, DEC_(data)) macro(data, 17)
+#define MRECURSION19( macro, data) MRECURSION18( macro, DEC_(data)) macro(data, 18)
+#define MRECURSION20( macro, data) MRECURSION19( macro, DEC_(data)) macro(data, 19)
+#define MRECURSION21( macro, data) MRECURSION20( macro, DEC_(data)) macro(data, 20)
+#define MRECURSION22( macro, data) MRECURSION21( macro, DEC_(data)) macro(data, 21)
+#define MRECURSION23( macro, data) MRECURSION22( macro, DEC_(data)) macro(data, 22)
+#define MRECURSION24( macro, data) MRECURSION23( macro, DEC_(data)) macro(data, 23)
+#define MRECURSION25( macro, data) MRECURSION24( macro, DEC_(data)) macro(data, 24)
+#define MRECURSION26( macro, data) MRECURSION25( macro, DEC_(data)) macro(data, 25)
+#define MRECURSION27( macro, data) MRECURSION26( macro, DEC_(data)) macro(data, 26)
+#define MRECURSION28( macro, data) MRECURSION27( macro, DEC_(data)) macro(data, 27)
+#define MRECURSION29( macro, data) MRECURSION28( macro, DEC_(data)) macro(data, 28)
+#define MRECURSION30( macro, data) MRECURSION29( macro, DEC_(data)) macro(data, 29)
+#define MRECURSION31( macro, data) MRECURSION30( macro, DEC_(data)) macro(data, 30)
+#define MRECURSION32( macro, data) MRECURSION31( macro, DEC_(data)) macro(data, 31)
+#define MRECURSION33( macro, data) MRECURSION32( macro, DEC_(data)) macro(data, 32)
+#define MRECURSION34( macro, data) MRECURSION33( macro, DEC_(data)) macro(data, 33)
+#define MRECURSION35( macro, data) MRECURSION34( macro, DEC_(data)) macro(data, 34)
+#define MRECURSION36( macro, data) MRECURSION35( macro, DEC_(data)) macro(data, 35)
+#define MRECURSION37( macro, data) MRECURSION36( macro, DEC_(data)) macro(data, 36)
+#define MRECURSION38( macro, data) MRECURSION37( macro, DEC_(data)) macro(data, 37)
+#define MRECURSION39( macro, data) MRECURSION38( macro, DEC_(data)) macro(data, 38)
+#define MRECURSION40( macro, data) MRECURSION39( macro, DEC_(data)) macro(data, 39)
+#define MRECURSION41( macro, data) MRECURSION40( macro, DEC_(data)) macro(data, 40)
+#define MRECURSION42( macro, data) MRECURSION41( macro, DEC_(data)) macro(data, 41)
+#define MRECURSION43( macro, data) MRECURSION42( macro, DEC_(data)) macro(data, 42)
+#define MRECURSION44( macro, data) MRECURSION43( macro, DEC_(data)) macro(data, 43)
+#define MRECURSION45( macro, data) MRECURSION44( macro, DEC_(data)) macro(data, 44)
+#define MRECURSION46( macro, data) MRECURSION45( macro, DEC_(data)) macro(data, 45)
+#define MRECURSION47( macro, data) MRECURSION46( macro, DEC_(data)) macro(data, 46)
+#define MRECURSION48( macro, data) MRECURSION47( macro, DEC_(data)) macro(data, 47)
+#define MRECURSION49( macro, data) MRECURSION48( macro, DEC_(data)) macro(data, 48)
+#define MRECURSION50( macro, data) MRECURSION49( macro, DEC_(data)) macro(data, 49)
+#define MRECURSION51( macro, data) MRECURSION50( macro, DEC_(data)) macro(data, 50)
+#define MRECURSION52( macro, data) MRECURSION51( macro, DEC_(data)) macro(data, 51)
+#define MRECURSION53( macro, data) MRECURSION52( macro, DEC_(data)) macro(data, 52)
+#define MRECURSION54( macro, data) MRECURSION53( macro, DEC_(data)) macro(data, 53)
+#define MRECURSION55( macro, data) MRECURSION54( macro, DEC_(data)) macro(data, 54)
+#define MRECURSION56( macro, data) MRECURSION55( macro, DEC_(data)) macro(data, 55)
+#define MRECURSION57( macro, data) MRECURSION56( macro, DEC_(data)) macro(data, 56)
+#define MRECURSION58( macro, data) MRECURSION57( macro, DEC_(data)) macro(data, 57)
+#define MRECURSION59( macro, data) MRECURSION58( macro, DEC_(data)) macro(data, 58)
+#define MRECURSION60( macro, data) MRECURSION59( macro, DEC_(data)) macro(data, 59)
+#define MRECURSION61( macro, data) MRECURSION60( macro, DEC_(data)) macro(data, 60)
+#define MRECURSION62( macro, data) MRECURSION61( macro, DEC_(data)) macro(data, 61)
+#define MRECURSION63( macro, data) MRECURSION62( macro, DEC_(data)) macro(data, 62)
+#define MRECURSION64( macro, data) MRECURSION63( macro, DEC_(data)) macro(data, 63)
+#define MRECURSION65( macro, data) MRECURSION64( macro, DEC_(data)) macro(data, 64)
+#define MRECURSION66( macro, data) MRECURSION65( macro, DEC_(data)) macro(data, 65)
+#define MRECURSION67( macro, data) MRECURSION66( macro, DEC_(data)) macro(data, 66)
+#define MRECURSION68( macro, data) MRECURSION67( macro, DEC_(data)) macro(data, 67)
+#define MRECURSION69( macro, data) MRECURSION68( macro, DEC_(data)) macro(data, 68)
+#define MRECURSION70( macro, data) MRECURSION69( macro, DEC_(data)) macro(data, 69)
+#define MRECURSION71( macro, data) MRECURSION70( macro, DEC_(data)) macro(data, 70)
+#define MRECURSION72( macro, data) MRECURSION71( macro, DEC_(data)) macro(data, 71)
+#define MRECURSION73( macro, data) MRECURSION72( macro, DEC_(data)) macro(data, 72)
+#define MRECURSION74( macro, data) MRECURSION73( macro, DEC_(data)) macro(data, 73)
+#define MRECURSION75( macro, data) MRECURSION74( macro, DEC_(data)) macro(data, 74)
+#define MRECURSION76( macro, data) MRECURSION75( macro, DEC_(data)) macro(data, 75)
+#define MRECURSION77( macro, data) MRECURSION76( macro, DEC_(data)) macro(data, 76)
+#define MRECURSION78( macro, data) MRECURSION77( macro, DEC_(data)) macro(data, 77)
+#define MRECURSION79( macro, data) MRECURSION78( macro, DEC_(data)) macro(data, 78)
+#define MRECURSION80( macro, data) MRECURSION79( macro, DEC_(data)) macro(data, 79)
+#define MRECURSION81( macro, data) MRECURSION80( macro, DEC_(data)) macro(data, 80)
+#define MRECURSION82( macro, data) MRECURSION81( macro, DEC_(data)) macro(data, 81)
+#define MRECURSION83( macro, data) MRECURSION82( macro, DEC_(data)) macro(data, 82)
+#define MRECURSION84( macro, data) MRECURSION83( macro, DEC_(data)) macro(data, 83)
+#define MRECURSION85( macro, data) MRECURSION84( macro, DEC_(data)) macro(data, 84)
+#define MRECURSION86( macro, data) MRECURSION85( macro, DEC_(data)) macro(data, 85)
+#define MRECURSION87( macro, data) MRECURSION86( macro, DEC_(data)) macro(data, 86)
+#define MRECURSION88( macro, data) MRECURSION87( macro, DEC_(data)) macro(data, 87)
+#define MRECURSION89( macro, data) MRECURSION88( macro, DEC_(data)) macro(data, 88)
+#define MRECURSION90( macro, data) MRECURSION89( macro, DEC_(data)) macro(data, 89)
+#define MRECURSION91( macro, data) MRECURSION90( macro, DEC_(data)) macro(data, 90)
+#define MRECURSION92( macro, data) MRECURSION91( macro, DEC_(data)) macro(data, 91)
+#define MRECURSION93( macro, data) MRECURSION92( macro, DEC_(data)) macro(data, 92)
+#define MRECURSION94( macro, data) MRECURSION93( macro, DEC_(data)) macro(data, 93)
+#define MRECURSION95( macro, data) MRECURSION94( macro, DEC_(data)) macro(data, 94)
+#define MRECURSION96( macro, data) MRECURSION95( macro, DEC_(data)) macro(data, 95)
+#define MRECURSION97( macro, data) MRECURSION96( macro, DEC_(data)) macro(data, 96)
+#define MRECURSION98( macro, data) MRECURSION97( macro, DEC_(data)) macro(data, 97)
+#define MRECURSION99( macro, data) MRECURSION98( macro, DEC_(data)) macro(data, 98)
+#define MRECURSION100(macro, data) MRECURSION99( macro, DEC_(data)) macro(data, 99)
+#define MRECURSION101(macro, data) MRECURSION100( macro, DEC_(data)) macro(data, 100)
+#define MRECURSION102(macro, data) MRECURSION101( macro, DEC_(data)) macro(data, 101)
+#define MRECURSION103(macro, data) MRECURSION102( macro, DEC_(data)) macro(data, 102)
+#define MRECURSION104(macro, data) MRECURSION103( macro, DEC_(data)) macro(data, 103)
+#define MRECURSION105(macro, data) MRECURSION104( macro, DEC_(data)) macro(data, 104)
+#define MRECURSION106(macro, data) MRECURSION105( macro, DEC_(data)) macro(data, 105)
+#define MRECURSION107(macro, data) MRECURSION106( macro, DEC_(data)) macro(data, 106)
+#define MRECURSION108(macro, data) MRECURSION107( macro, DEC_(data)) macro(data, 107)
+#define MRECURSION109(macro, data) MRECURSION108( macro, DEC_(data)) macro(data, 108)
+#define MRECURSION110(macro, data) MRECURSION109( macro, DEC_(data)) macro(data, 109)
+#define MRECURSION111(macro, data) MRECURSION110( macro, DEC_(data)) macro(data, 110)
+#define MRECURSION112(macro, data) MRECURSION111( macro, DEC_(data)) macro(data, 111)
+#define MRECURSION113(macro, data) MRECURSION112( macro, DEC_(data)) macro(data, 112)
+#define MRECURSION114(macro, data) MRECURSION113( macro, DEC_(data)) macro(data, 113)
+#define MRECURSION115(macro, data) MRECURSION114( macro, DEC_(data)) macro(data, 114)
+#define MRECURSION116(macro, data) MRECURSION115( macro, DEC_(data)) macro(data, 115)
+#define MRECURSION117(macro, data) MRECURSION116( macro, DEC_(data)) macro(data, 116)
+#define MRECURSION118(macro, data) MRECURSION117( macro, DEC_(data)) macro(data, 117)
+#define MRECURSION119(macro, data) MRECURSION118( macro, DEC_(data)) macro(data, 118)
+#define MRECURSION120(macro, data) MRECURSION119( macro, DEC_(data)) macro(data, 119)
+#define MRECURSION121(macro, data) MRECURSION120( macro, DEC_(data)) macro(data, 120)
+#define MRECURSION122(macro, data) MRECURSION121( macro, DEC_(data)) macro(data, 121)
+#define MRECURSION123(macro, data) MRECURSION122( macro, DEC_(data)) macro(data, 122)
+#define MRECURSION124(macro, data) MRECURSION123( macro, DEC_(data)) macro(data, 123)
+#define MRECURSION125(macro, data) MRECURSION124( macro, DEC_(data)) macro(data, 124)
+#define MRECURSION126(macro, data) MRECURSION125( macro, DEC_(data)) macro(data, 125)
+#define MRECURSION127(macro, data) MRECURSION126( macro, DEC_(data)) macro(data, 126)
+#define MRECURSION128(macro, data) MRECURSION127( macro, DEC_(data)) macro(data, 127)
+#define MRECURSION129(macro, data) MRECURSION128( macro, DEC_(data)) macro(data, 128)
+#define MRECURSION130(macro, data) MRECURSION129( macro, DEC_(data)) macro(data, 129)
+#define MRECURSION131(macro, data) MRECURSION130( macro, DEC_(data)) macro(data, 130)
+#define MRECURSION132(macro, data) MRECURSION131( macro, DEC_(data)) macro(data, 131)
+#define MRECURSION133(macro, data) MRECURSION132( macro, DEC_(data)) macro(data, 132)
+#define MRECURSION134(macro, data) MRECURSION133( macro, DEC_(data)) macro(data, 133)
+#define MRECURSION135(macro, data) MRECURSION134( macro, DEC_(data)) macro(data, 134)
+#define MRECURSION136(macro, data) MRECURSION135( macro, DEC_(data)) macro(data, 135)
+#define MRECURSION137(macro, data) MRECURSION136( macro, DEC_(data)) macro(data, 136)
+#define MRECURSION138(macro, data) MRECURSION137( macro, DEC_(data)) macro(data, 137)
+#define MRECURSION139(macro, data) MRECURSION138( macro, DEC_(data)) macro(data, 138)
+#define MRECURSION140(macro, data) MRECURSION139( macro, DEC_(data)) macro(data, 139)
+#define MRECURSION141(macro, data) MRECURSION140( macro, DEC_(data)) macro(data, 140)
+#define MRECURSION142(macro, data) MRECURSION141( macro, DEC_(data)) macro(data, 141)
+#define MRECURSION143(macro, data) MRECURSION142( macro, DEC_(data)) macro(data, 142)
+#define MRECURSION144(macro, data) MRECURSION143( macro, DEC_(data)) macro(data, 143)
+#define MRECURSION145(macro, data) MRECURSION144( macro, DEC_(data)) macro(data, 144)
+#define MRECURSION146(macro, data) MRECURSION145( macro, DEC_(data)) macro(data, 145)
+#define MRECURSION147(macro, data) MRECURSION146( macro, DEC_(data)) macro(data, 146)
+#define MRECURSION148(macro, data) MRECURSION147( macro, DEC_(data)) macro(data, 147)
+#define MRECURSION149(macro, data) MRECURSION148( macro, DEC_(data)) macro(data, 148)
+#define MRECURSION150(macro, data) MRECURSION149( macro, DEC_(data)) macro(data, 149)
+#define MRECURSION151(macro, data) MRECURSION150( macro, DEC_(data)) macro(data, 150)
+#define MRECURSION152(macro, data) MRECURSION151( macro, DEC_(data)) macro(data, 151)
+#define MRECURSION153(macro, data) MRECURSION152( macro, DEC_(data)) macro(data, 152)
+#define MRECURSION154(macro, data) MRECURSION153( macro, DEC_(data)) macro(data, 153)
+#define MRECURSION155(macro, data) MRECURSION154( macro, DEC_(data)) macro(data, 154)
+#define MRECURSION156(macro, data) MRECURSION155( macro, DEC_(data)) macro(data, 155)
+#define MRECURSION157(macro, data) MRECURSION156( macro, DEC_(data)) macro(data, 156)
+#define MRECURSION158(macro, data) MRECURSION157( macro, DEC_(data)) macro(data, 157)
+#define MRECURSION159(macro, data) MRECURSION158( macro, DEC_(data)) macro(data, 158)
+#define MRECURSION160(macro, data) MRECURSION159( macro, DEC_(data)) macro(data, 159)
+#define MRECURSION161(macro, data) MRECURSION160( macro, DEC_(data)) macro(data, 160)
+#define MRECURSION162(macro, data) MRECURSION161( macro, DEC_(data)) macro(data, 161)
+#define MRECURSION163(macro, data) MRECURSION162( macro, DEC_(data)) macro(data, 162)
+#define MRECURSION164(macro, data) MRECURSION163( macro, DEC_(data)) macro(data, 163)
+#define MRECURSION165(macro, data) MRECURSION164( macro, DEC_(data)) macro(data, 164)
+#define MRECURSION166(macro, data) MRECURSION165( macro, DEC_(data)) macro(data, 165)
+#define MRECURSION167(macro, data) MRECURSION166( macro, DEC_(data)) macro(data, 166)
+#define MRECURSION168(macro, data) MRECURSION167( macro, DEC_(data)) macro(data, 167)
+#define MRECURSION169(macro, data) MRECURSION168( macro, DEC_(data)) macro(data, 168)
+#define MRECURSION170(macro, data) MRECURSION169( macro, DEC_(data)) macro(data, 169)
+#define MRECURSION171(macro, data) MRECURSION170( macro, DEC_(data)) macro(data, 170)
+#define MRECURSION172(macro, data) MRECURSION171( macro, DEC_(data)) macro(data, 171)
+#define MRECURSION173(macro, data) MRECURSION172( macro, DEC_(data)) macro(data, 172)
+#define MRECURSION174(macro, data) MRECURSION173( macro, DEC_(data)) macro(data, 173)
+#define MRECURSION175(macro, data) MRECURSION174( macro, DEC_(data)) macro(data, 174)
+#define MRECURSION176(macro, data) MRECURSION175( macro, DEC_(data)) macro(data, 175)
+#define MRECURSION177(macro, data) MRECURSION176( macro, DEC_(data)) macro(data, 176)
+#define MRECURSION178(macro, data) MRECURSION177( macro, DEC_(data)) macro(data, 177)
+#define MRECURSION179(macro, data) MRECURSION178( macro, DEC_(data)) macro(data, 178)
+#define MRECURSION180(macro, data) MRECURSION179( macro, DEC_(data)) macro(data, 179)
+#define MRECURSION181(macro, data) MRECURSION180( macro, DEC_(data)) macro(data, 180)
+#define MRECURSION182(macro, data) MRECURSION181( macro, DEC_(data)) macro(data, 181)
+#define MRECURSION183(macro, data) MRECURSION182( macro, DEC_(data)) macro(data, 182)
+#define MRECURSION184(macro, data) MRECURSION183( macro, DEC_(data)) macro(data, 183)
+#define MRECURSION185(macro, data) MRECURSION184( macro, DEC_(data)) macro(data, 184)
+#define MRECURSION186(macro, data) MRECURSION185( macro, DEC_(data)) macro(data, 185)
+#define MRECURSION187(macro, data) MRECURSION186( macro, DEC_(data)) macro(data, 186)
+#define MRECURSION188(macro, data) MRECURSION187( macro, DEC_(data)) macro(data, 187)
+#define MRECURSION189(macro, data) MRECURSION188( macro, DEC_(data)) macro(data, 188)
+#define MRECURSION190(macro, data) MRECURSION189( macro, DEC_(data)) macro(data, 189)
+#define MRECURSION191(macro, data) MRECURSION190( macro, DEC_(data)) macro(data, 190)
+#define MRECURSION192(macro, data) MRECURSION191( macro, DEC_(data)) macro(data, 191)
+#define MRECURSION193(macro, data) MRECURSION192( macro, DEC_(data)) macro(data, 192)
+#define MRECURSION194(macro, data) MRECURSION193( macro, DEC_(data)) macro(data, 193)
+#define MRECURSION195(macro, data) MRECURSION194( macro, DEC_(data)) macro(data, 194)
+#define MRECURSION196(macro, data) MRECURSION195( macro, DEC_(data)) macro(data, 195)
+#define MRECURSION197(macro, data) MRECURSION196( macro, DEC_(data)) macro(data, 196)
+#define MRECURSION198(macro, data) MRECURSION197( macro, DEC_(data)) macro(data, 197)
+#define MRECURSION199(macro, data) MRECURSION198( macro, DEC_(data)) macro(data, 198)
+#define MRECURSION200(macro, data) MRECURSION199( macro, DEC_(data)) macro(data, 199)
+#define MRECURSION201(macro, data) MRECURSION200( macro, DEC_(data)) macro(data, 200)
+#define MRECURSION202(macro, data) MRECURSION201( macro, DEC_(data)) macro(data, 201)
+#define MRECURSION203(macro, data) MRECURSION202( macro, DEC_(data)) macro(data, 202)
+#define MRECURSION204(macro, data) MRECURSION203( macro, DEC_(data)) macro(data, 203)
+#define MRECURSION205(macro, data) MRECURSION204( macro, DEC_(data)) macro(data, 204)
+#define MRECURSION206(macro, data) MRECURSION205( macro, DEC_(data)) macro(data, 205)
+#define MRECURSION207(macro, data) MRECURSION206( macro, DEC_(data)) macro(data, 206)
+#define MRECURSION208(macro, data) MRECURSION207( macro, DEC_(data)) macro(data, 207)
+#define MRECURSION209(macro, data) MRECURSION208( macro, DEC_(data)) macro(data, 208)
+#define MRECURSION210(macro, data) MRECURSION209( macro, DEC_(data)) macro(data, 209)
+#define MRECURSION211(macro, data) MRECURSION210( macro, DEC_(data)) macro(data, 210)
+#define MRECURSION212(macro, data) MRECURSION211( macro, DEC_(data)) macro(data, 211)
+#define MRECURSION213(macro, data) MRECURSION212( macro, DEC_(data)) macro(data, 212)
+#define MRECURSION214(macro, data) MRECURSION213( macro, DEC_(data)) macro(data, 213)
+#define MRECURSION215(macro, data) MRECURSION214( macro, DEC_(data)) macro(data, 214)
+#define MRECURSION216(macro, data) MRECURSION215( macro, DEC_(data)) macro(data, 215)
+#define MRECURSION217(macro, data) MRECURSION216( macro, DEC_(data)) macro(data, 216)
+#define MRECURSION218(macro, data) MRECURSION217( macro, DEC_(data)) macro(data, 217)
+#define MRECURSION219(macro, data) MRECURSION218( macro, DEC_(data)) macro(data, 218)
+#define MRECURSION220(macro, data) MRECURSION219( macro, DEC_(data)) macro(data, 219)
+#define MRECURSION221(macro, data) MRECURSION220( macro, DEC_(data)) macro(data, 220)
+#define MRECURSION222(macro, data) MRECURSION221( macro, DEC_(data)) macro(data, 221)
+#define MRECURSION223(macro, data) MRECURSION222( macro, DEC_(data)) macro(data, 222)
+#define MRECURSION224(macro, data) MRECURSION223( macro, DEC_(data)) macro(data, 223)
+#define MRECURSION225(macro, data) MRECURSION224( macro, DEC_(data)) macro(data, 224)
+#define MRECURSION226(macro, data) MRECURSION225( macro, DEC_(data)) macro(data, 225)
+#define MRECURSION227(macro, data) MRECURSION226( macro, DEC_(data)) macro(data, 226)
+#define MRECURSION228(macro, data) MRECURSION227( macro, DEC_(data)) macro(data, 227)
+#define MRECURSION229(macro, data) MRECURSION228( macro, DEC_(data)) macro(data, 228)
+#define MRECURSION230(macro, data) MRECURSION229( macro, DEC_(data)) macro(data, 229)
+#define MRECURSION231(macro, data) MRECURSION230( macro, DEC_(data)) macro(data, 230)
+#define MRECURSION232(macro, data) MRECURSION231( macro, DEC_(data)) macro(data, 231)
+#define MRECURSION233(macro, data) MRECURSION232( macro, DEC_(data)) macro(data, 232)
+#define MRECURSION234(macro, data) MRECURSION233( macro, DEC_(data)) macro(data, 233)
+#define MRECURSION235(macro, data) MRECURSION234( macro, DEC_(data)) macro(data, 234)
+#define MRECURSION236(macro, data) MRECURSION235( macro, DEC_(data)) macro(data, 235)
+#define MRECURSION237(macro, data) MRECURSION236( macro, DEC_(data)) macro(data, 236)
+#define MRECURSION238(macro, data) MRECURSION237( macro, DEC_(data)) macro(data, 237)
+#define MRECURSION239(macro, data) MRECURSION238( macro, DEC_(data)) macro(data, 238)
+#define MRECURSION240(macro, data) MRECURSION239( macro, DEC_(data)) macro(data, 239)
+#define MRECURSION241(macro, data) MRECURSION240( macro, DEC_(data)) macro(data, 240)
+#define MRECURSION242(macro, data) MRECURSION241( macro, DEC_(data)) macro(data, 241)
+#define MRECURSION243(macro, data) MRECURSION242( macro, DEC_(data)) macro(data, 242)
+#define MRECURSION244(macro, data) MRECURSION243( macro, DEC_(data)) macro(data, 243)
+#define MRECURSION245(macro, data) MRECURSION244( macro, DEC_(data)) macro(data, 244)
+#define MRECURSION246(macro, data) MRECURSION245( macro, DEC_(data)) macro(data, 245)
+#define MRECURSION247(macro, data) MRECURSION246( macro, DEC_(data)) macro(data, 246)
+#define MRECURSION248(macro, data) MRECURSION247( macro, DEC_(data)) macro(data, 247)
+#define MRECURSION249(macro, data) MRECURSION248( macro, DEC_(data)) macro(data, 248)
+#define MRECURSION250(macro, data) MRECURSION249( macro, DEC_(data)) macro(data, 249)
+#define MRECURSION251(macro, data) MRECURSION250( macro, DEC_(data)) macro(data, 250)
+#define MRECURSION252(macro, data) MRECURSION251( macro, DEC_(data)) macro(data, 251)
+#define MRECURSION253(macro, data) MRECURSION252( macro, DEC_(data)) macro(data, 252)
+#define MRECURSION254(macro, data) MRECURSION253( macro, DEC_(data)) macro(data, 253)
+#define MRECURSION255(macro, data) MRECURSION254( macro, DEC_(data)) macro(data, 254)
+#define MRECURSION256(macro, data) MRECURSION255( macro, DEC_(data)) macro(data, 255)
+
+/** @} */
+
+#endif /* _MRECURSION_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrepeat.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,338 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor macro repeating utils.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+/**
+ * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+/** Maximal number of repetitions supported by MREPEAT. */
+#define MREPEAT_LIMIT 256
+
+/** \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count The number of repetitious calls to macro. Valid values
+ * range from 0 to MREPEAT_LIMIT.
+ * \param[in] macro A binary operation of the form macro(n, data). This macro
+ * is expanded by MREPEAT with the current repetition number
+ * and the auxiliary data argument.
+ * \param[in] data Auxiliary data passed to macro.
+ *
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
+ */
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data)
+
+#define MREPEAT0( macro, data)
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
+
+/** @} */
+
+#endif /* _MREPEAT_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/preprocessor.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Preprocessor utils. + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" +#include "mrecursion.h" + +#endif // _PREPROCESSOR_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/stringz.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,84 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor stringizing utils.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+/**
+ * \defgroup group_sam0_utils_stringz Preprocessor - Stringize
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * May be used only within macros with the token passed as an argument if the
+ * token is \#defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x) #x
+
+/** \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * No restriction of use if the token is \#defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x) STRINGZ(x)
+
+/** @} */
+
+#endif // _STRINGZ_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/tpaste.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor token pasting utils.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+/**
+ * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ *
+ * @{ */
+#define TPASTE2( a, b) a##b
+#define TPASTE3( a, b, c) a##b##c
+#define TPASTE4( a, b, c, d) a##b##c##d
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
+/** @} */
+
+/** \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ *
+ * @{ */
+#define ATPASTE2( a, b) TPASTE2( a, b)
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
+/** @} */
+
+/** @} */
+
+#endif // _TPASTE_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/status_codes.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,158 @@
+/**
+ * \file
+ *
+ * \brief Status code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef STATUS_CODES_H_INCLUDED
+#define STATUS_CODES_H_INCLUDED
+
+#include <stdint.h>
+
+/**
+ * \defgroup group_sam0_utils_status_codes Status Codes
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** Mask to retrieve the error category of a status code. */
+#define STATUS_CATEGORY_MASK 0xF0
+
+/** Mask to retrieve the error code within the category of a status code. */
+#define STATUS_ERROR_MASK 0x0F
+
+/** Status code error categories. */
+enum status_categories {
+ STATUS_CATEGORY_OK = 0x00,
+ STATUS_CATEGORY_COMMON = 0x10,
+ STATUS_CATEGORY_ANALOG = 0x30,
+ STATUS_CATEGORY_COM = 0x40,
+ STATUS_CATEGORY_IO = 0x50,
+};
+
+/**
+ * Status code that may be returned by shell commands and protocol
+ * implementations.
+ *
+ * \note Any change to these status codes and the corresponding
+ * message strings is strictly forbidden. New codes can be added,
+ * however, but make sure that any message string tables are updated
+ * at the same time.
+ */
+enum status_code {
+ STATUS_OK = STATUS_CATEGORY_OK | 0x00,
+ STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01,
+ STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02,
+ STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04,
+ STATUS_BUSY = STATUS_CATEGORY_OK | 0x05,
+ STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06,
+
+ STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00,
+ STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01,
+ STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02,
+ STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03,
+ STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04,
+ STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05,
+ STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06,
+ STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07,
+ STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08,
+ STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A,
+ STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B,
+ STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c,
+ STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d,
+ STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e,
+ STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f,
+
+ STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
+ STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
+
+ STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00,
+ STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01,
+ STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02,
+
+ STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00,
+};
+typedef enum status_code status_code_genare_t;
+
+/**
+ Status codes used by MAC stack.
+ */
+enum status_code_wireless {
+ //STATUS_OK = 0, //!< Success
+ ERR_IO_ERROR = -1, //!< I/O error
+ ERR_FLUSHED = -2, //!< Request flushed from queue
+ ERR_TIMEOUT = -3, //!< Operation timed out
+ ERR_BAD_DATA = -4, //!< Data integrity check failed
+ ERR_PROTOCOL = -5, //!< Protocol error
+ ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
+ ERR_NO_MEMORY = -7, //!< Insufficient memory
+ ERR_INVALID_ARG = -8, //!< Invalid argument
+ ERR_BAD_ADDRESS = -9, //!< Bad address
+ ERR_BUSY = -10, //!< Resource is busy
+ ERR_BAD_FORMAT = -11, //!< Data format not recognized
+ ERR_NO_TIMER = -12, //!< No timer available
+ ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
+ ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
+
+ /**
+ * \brief Operation in progress
+ *
+ * This status code is for driver-internal use when an operation
+ * is currently being performed.
+ *
+ * \note Drivers should never return this status code to any
+ * callers. It is strictly for internal use.
+ */
+ OPERATION_IN_PROGRESS = -128,
+};
+
+typedef enum status_code_wireless status_code_t;
+
+/** @} */
+
+#endif /* STATUS_CODES_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralNames.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include <compiler.h>
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _SERCOM_SPI_NAME(n, unused) \
+ SPI##n,
+
+#define _SERCOM_I2C_NAME(n, unused) \
+ I2C##n,
+
+
+
+typedef enum {
+ UART_0 = (int)0x42000800UL, // Base address of SERCOM0
+ UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
+ UART_2 = (int)0x42001000UL, // Base address of SERCOM2
+ UART_3 = (int)0x42001400UL, // Base address of SERCOM3
+ UART_4 = (int)0x42001800UL, // Base address of SERCOM4
+ UART_5 = (int)0x42001C00UL // Base address of SERCOM5
+} UARTName;
+/*
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;*/
+
+typedef enum {
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
+} SPIName;
+
+typedef enum {
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
+} I2CName;
+/*
+typedef enum {
+ PWM_1 = 1,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;*/
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+// Default peripherals
+#define MBED_SPI0 p5, p6, p7, p8
+#define MBED_SPI1 p11, p12, p13, p14
+
+#define MBED_UART0 p9, p10
+#define MBED_UART1 p13, p14
+#define MBED_UART2 p28, p27
+#define MBED_UARTUSB USBTX, USBRX
+
+#define MBED_I2C0 p28, p27
+#define MBED_I2C1 p9, p10
+
+#define MBED_CAN0 p30, p29
+
+#define MBED_ANALOGOUT0 p18
+
+#define MBED_ANALOGIN0 p15
+#define MBED_ANALOGIN1 p16
+#define MBED_ANALOGIN2 p17
+#define MBED_ANALOGIN3 p18
+#define MBED_ANALOGIN4 p19
+#define MBED_ANALOGIN5 p20
+
+#define MBED_PWMOUT0 p26
+#define MBED_PWMOUT1 p25
+#define MBED_PWMOUT2 p24
+#define MBED_PWMOUT3 p23
+#define MBED_PWMOUT4 p22
+#define MBED_PWMOUT5 p21
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralPins.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,53 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +void find_pin_settings (PinName output, PinName input, PinName clock, PinName chipsel, uint32_t* pad_pinmuxes); // clock also for RTS and chipsel for CTS +uint32_t find_mux_setting (PinName output, PinName input, PinName clock, PinName chipsel); +/************RTC***************/ +//extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +//extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +//extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +//extern const PinMap PinMap_I2C_SDA[]; +//extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +//extern const PinMap PinMap_SPI_SCLK[]; +//extern const PinMap PinMap_SPI_MOSI[]; +//extern const PinMap PinMap_SPI_MISO[]; +//extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +//extern const PinMap PinMap_PWM[]; + + + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/PinNames.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013 Nordic Semiconductor
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT,
+ PIN_INPUT_OUTPUT //pin state can be set and read back
+} PinDirection;
+
+typedef enum {
+ PA00 = 0,
+ PA01 = 1,
+ PA02 = 2,
+ PA03 = 3,
+ PA04 = 4,
+ PA05 = 5,
+ PA06 = 6,
+ PA07 = 7,
+ PA08 = 8,
+ PA09 = 9,
+ PA10 = 10,
+ PA11 = 11,
+ PA12 = 12,
+ PA13 = 13,
+ PA14 = 14,
+ PA15 = 15,
+ PA16 = 16,
+ PA17 = 17,
+ PA18 = 18,
+ PA19 = 19,
+ PA20 = 20,
+ PA21 = 21,
+ PA22 = 22,
+ PA23 = 23,
+ PA24 = 24,
+ PA25 = 25,
+ PA26 = 26,
+ PA27 = 27,
+ PA28 = 28,
+ PA29 = 29,
+ PA30 = 30,
+ PA31 = 31,
+
+ PB00 = 32,
+ PB01 = 33,
+ PB02 = 34,
+ PB03 = 35,
+ PB04 = 36,
+ PB05 = 37,
+ PB06 = 38,
+ PB07 = 39,
+ PB08 = 40,
+ PB09 = 41,
+ PB10 = 42,
+ PB11 = 43,
+ PB12 = 44,
+ PB13 = 45,
+ PB14 = 46,
+ PB15 = 47,
+ PB16 = 48,
+ PB17 = 49,
+ PB18 = 50,
+ PB19 = 51,
+ PB20 = 52,
+ PB21 = 53,
+ PB22 = 54,
+ PB23 = 55,
+ PB24 = 56,
+ PB25 = 57,
+ PB26 = 58,
+ PB27 = 59,
+ PB28 = 60,
+ PB29 = 61,
+ PB30 = 62,
+ PB31 = 63,
+
+ PC16 = 64,
+ PC18 = 65,
+ PC19 = 66,
+
+ USBTX = PA04,
+ USBRX = PA05,
+ LED1 = PA19,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/PortNames.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "compiler.h"
+
+//called before main - implement here if board needs it ortherwise, let
+// the application override this if necessary
+//TODO: To be implemented by adding system init and board init
+void mbed_sdk_init()
+{
+
+}
+/***************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,708 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board definition
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
+#define SAMD21_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samd21_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME "SAMD21_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ * @{ */
+#define BOARD_FREQ_SLCK_XTAL (32768U)
+#define BOARD_FREQ_SLCK_BYPASS (32768U)
+#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
+#define BOARD_MCK CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US 15625
+/** @} */
+
+/** \name LED0 definitions
+ * @{ */
+#define LED0_PIN PIN_PB30
+#define LED0_ACTIVE false
+#define LED0_INACTIVE !LED0_ACTIVE
+/** @} */
+
+/** \name SW0 definitions
+ * @{ */
+#define SW0_PIN PIN_PA15
+#define SW0_ACTIVE false
+#define SW0_INACTIVE !SW0_ACTIVE
+#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15
+#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_LINE 15
+/** @} */
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * @{ */
+#define LED_0_NAME "LED0 (yellow)"
+#define LED_0_PIN LED0_PIN
+#define LED_0_ACTIVE LED0_ACTIVE
+#define LED_0_INACTIVE LED0_INACTIVE
+#define LED0_GPIO LED0_PIN
+#define LED0 LED0_PIN
+
+#define LED_0_PWM4CTRL_MODULE TCC0
+#define LED_0_PWM4CTRL_CHANNEL 0
+#define LED_0_PWM4CTRL_OUTPUT 0
+#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT 1
+
+/**
+ * \name Serialflash definitions
+ *
+ * On board Serialflash definitions.
+ *
+ * @{ */
+#define SERIALFLASH_SPI_MODULE SERCOM5
+#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
+#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define SERIALFLASH_SPI_CS PIN_PA13
+/** @} */
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * @{ */
+#define BUTTON_0_NAME "SW0"
+#define BUTTON_0_PIN SW0_PIN
+#define BUTTON_0_ACTIVE SW0_ACTIVE
+#define BUTTON_0_INACTIVE SW0_INACTIVE
+#define BUTTON_0_EIC_PIN SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ * @{
+ */
+#define EXT1_PIN_3 PIN_PB00
+#define EXT1_PIN_4 PIN_PB01
+#define EXT1_PIN_5 PIN_PB06
+#define EXT1_PIN_6 PIN_PB07
+#define EXT1_PIN_7 PIN_PB02
+#define EXT1_PIN_8 PIN_PB03
+#define EXT1_PIN_9 PIN_PB04
+#define EXT1_PIN_10 PIN_PB05
+#define EXT1_PIN_11 PIN_PA08
+#define EXT1_PIN_12 PIN_PA09
+#define EXT1_PIN_13 PIN_PB09
+#define EXT1_PIN_14 PIN_PB08
+#define EXT1_PIN_15 PIN_PA05
+#define EXT1_PIN_16 PIN_PA06
+#define EXT1_PIN_17 PIN_PA04
+#define EXT1_PIN_18 PIN_PA07
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ * @{
+ */
+#define EXT1_PIN_ADC_0 EXT1_PIN_3
+#define EXT1_PIN_ADC_1 EXT1_PIN_4
+#define EXT1_PIN_GPIO_0 EXT1_PIN_5
+#define EXT1_PIN_GPIO_1 EXT1_PIN_6
+#define EXT1_PIN_PWM_0 EXT1_PIN_7
+#define EXT1_PIN_PWM_1 EXT1_PIN_8
+#define EXT1_PIN_IRQ EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL EXT1_PIN_12
+#define EXT1_PIN_UART_RX EXT1_PIN_13
+#define EXT1_PIN_UART_TX EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ * @{
+ */
+#define EXT1_ADC_MODULE ADC
+#define EXT1_ADC_0_CHANNEL 8
+#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8
+#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8
+#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
+#define EXT1_ADC_1_CHANNEL 9
+#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9
+#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9
+#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ * @{
+ */
+#define EXT1_PWM_MODULE TC6
+#define EXT1_PWM_0_CHANNEL 0
+#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0
+#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0
+#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0
+#define EXT1_PWM_1_CHANNEL 1
+#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1
+#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1
+#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT1_IRQ_MODULE EIC
+#define EXT1_IRQ_INPUT 4
+#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ * @{
+ */
+#define EXT1_I2C_MODULE SERCOM2
+#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ * @{
+ */
+#define EXT1_UART_MODULE SERCOM4
+#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
+#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ * @{
+ */
+#define EXT1_SPI_MODULE SERCOM0
+#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 pin definitions
+ * @{
+ */
+#define EXT2_PIN_3 PIN_PA10
+#define EXT2_PIN_4 PIN_PA11
+#define EXT2_PIN_5 PIN_PA20
+#define EXT2_PIN_6 PIN_PA21
+#define EXT2_PIN_7 PIN_PB12
+#define EXT2_PIN_8 PIN_PB13
+#define EXT2_PIN_9 PIN_PB14
+#define EXT2_PIN_10 PIN_PB15
+#define EXT2_PIN_11 PIN_PA08
+#define EXT2_PIN_12 PIN_PA09
+#define EXT2_PIN_13 PIN_PB11
+#define EXT2_PIN_14 PIN_PB10
+#define EXT2_PIN_15 PIN_PA17
+#define EXT2_PIN_16 PIN_PA18
+#define EXT2_PIN_17 PIN_PA16
+#define EXT2_PIN_18 PIN_PA19
+/** @} */
+
+/** \name Extension header #2 pin definitions by function
+ * @{
+ */
+#define EXT2_PIN_ADC_0 EXT2_PIN_3
+#define EXT2_PIN_ADC_1 EXT2_PIN_4
+#define EXT2_PIN_GPIO_0 EXT2_PIN_5
+#define EXT2_PIN_GPIO_1 EXT2_PIN_6
+#define EXT2_PIN_PWM_0 EXT2_PIN_7
+#define EXT2_PIN_PWM_1 EXT2_PIN_8
+#define EXT2_PIN_IRQ EXT2_PIN_9
+#define EXT2_PIN_I2C_SDA EXT2_PIN_11
+#define EXT2_PIN_I2C_SCL EXT2_PIN_12
+#define EXT2_PIN_UART_RX EXT2_PIN_13
+#define EXT2_PIN_UART_TX EXT2_PIN_14
+#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
+#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
+#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
+#define EXT2_PIN_SPI_MISO EXT2_PIN_17
+#define EXT2_PIN_SPI_SCK EXT2_PIN_18
+/** @} */
+
+/** \name Extension header #2 ADC definitions
+ * @{
+ */
+#define EXT2_ADC_MODULE ADC
+#define EXT2_ADC_0_CHANNEL 18
+#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
+#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
+#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
+#define EXT2_ADC_1_CHANNEL 19
+#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
+#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
+#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
+/** @} */
+
+/** \name Extension header #2 PWM definitions
+ * @{
+ */
+#define EXT2_PWM_MODULE TC4
+#define EXT2_PWM_0_CHANNEL 0
+#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0
+#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0
+#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0
+#define EXT2_PWM_1_CHANNEL 1
+#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1
+#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1
+#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1
+/** @} */
+
+/** \name Extension header #2 PWM for Control definitions
+ * @{
+ */
+#define EXT2_PWM4CTRL_MODULE TCC0
+#define EXT2_PWM4CTRL_0_CHANNEL 2
+#define EXT2_PWM4CTRL_0_OUTPUT 6
+#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_1_CHANNEL 3
+#define EXT2_PWM4CTRL_1_OUTPUT 7
+#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7
+/** @} */
+
+/** \name Extension header #2 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT2_IRQ_MODULE EIC
+#define EXT2_IRQ_INPUT 14
+#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
+/** @} */
+
+/** \name Extension header #2 I2C definitions
+* @{
+*/
+#define EXT2_I2C_MODULE SERCOM2
+#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 UART definitions
+ * @{
+ */
+#define EXT2_UART_MODULE SERCOM4
+#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0
+#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1
+#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
+#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 SPI definitions
+ * @{
+ */
+#define EXT2_SPI_MODULE SERCOM1
+#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
+#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
+#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
+#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
+#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
+#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ * @{
+ */
+#define EXT3_PIN_3 PIN_PA02
+#define EXT3_PIN_4 PIN_PA03
+#define EXT3_PIN_5 PIN_PB30
+#define EXT3_PIN_6 PIN_PA15
+#define EXT3_PIN_7 PIN_PA12
+#define EXT3_PIN_8 PIN_PA13
+#define EXT3_PIN_9 PIN_PA28
+#define EXT3_PIN_10 PIN_PA27
+#define EXT3_PIN_11 PIN_PA08
+#define EXT3_PIN_12 PIN_PA09
+#define EXT3_PIN_13 PIN_PB11
+#define EXT3_PIN_14 PIN_PB10
+#define EXT3_PIN_15 PIN_PB17
+#define EXT3_PIN_16 PIN_PB22
+#define EXT3_PIN_17 PIN_PB16
+#define EXT3_PIN_18 PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ * @{
+ */
+#define EXT3_PIN_ADC_0 EXT3_PIN_3
+#define EXT3_PIN_ADC_1 EXT3_PIN_4
+#define EXT3_PIN_GPIO_0 EXT3_PIN_5
+#define EXT3_PIN_GPIO_1 EXT3_PIN_6
+#define EXT3_PIN_PWM_0 EXT3_PIN_7
+#define EXT3_PIN_PWM_1 EXT3_PIN_8
+#define EXT3_PIN_IRQ EXT3_PIN_9
+#define EXT3_PIN_I2C_SDA EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL EXT3_PIN_12
+#define EXT3_PIN_UART_RX EXT3_PIN_13
+#define EXT3_PIN_UART_TX EXT3_PIN_14
+#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 ADC definitions
+ * @{
+ */
+#define EXT3_ADC_MODULE ADC
+#define EXT3_ADC_0_CHANNEL 0
+#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0
+#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0
+#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
+#define EXT3_ADC_1_CHANNEL 1
+#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1
+#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1
+#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
+/** @} */
+
+/** \name Extension header #3 PWM for Control definitions
+ * @{
+ */
+#define EXT3_PWM4CTRL_MODULE TCC2
+#define EXT3_PWM4CTRL_0_CHANNEL 0
+#define EXT3_PWM4CTRL_0_OUTPUT 0
+#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_1_CHANNEL 1
+#define EXT3_PWM4CTRL_1_OUTPUT 1
+#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1
+/** @} */
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT3_IRQ_MODULE EIC
+#define EXT3_IRQ_INPUT 8
+#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ * @{
+ */
+#define EXT3_I2C_MODULE SERCOM2
+#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ * @{
+ */
+#define EXT3_UART_MODULE SERCOM4
+#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
+#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
+#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
+#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
+#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ * @{
+ */
+#define EXT3_SPI_MODULE SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
+#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 Dataflash
+ * @{
+ */
+#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
+#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
+/** @} */
+
+/** \name USB definitions
+ * @{
+ */
+#define USB_ID
+#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
+#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
+#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
+#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
+#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
+#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
+#define USB_VBUS_PIN PIN_PA14
+#define USB_VBUS_EIC_LINE 14
+#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
+#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
+#define USB_ID_PIN PIN_PA03
+#define USB_ID_EIC_LINE 3
+#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3
+#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN PIN_PA27
+#define EDBG_GPIO1_PIN PIN_PA28
+#define EDBG_GPIO2_PIN PIN_PA20
+#define EDBG_GPIO3_PIN PIN_PA21
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE -1 /* Not available on this board */
+#define EDBG_UART_RX_PIN -1 /* Not available on this board */
+#define EDBG_UART_RX_MUX -1 /* Not available on this board */
+#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
+#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
+#define EDBG_UART_TX_PIN -1 /* Not available on this board */
+#define EDBG_UART_TX_MUX -1 /* Not available on this board */
+#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
+#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE SERCOM2
+#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_MODULE SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
+#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE SERCOM3
+#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
+#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
+#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
+#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
+/** @} */
+
+/** @} */
+
+/** \name 802.15.4 TRX Interface definitions
+ * @{
+ */
+
+#define AT86RFX_SPI EXT1_SPI_MODULE
+#define AT86RFX_RST_PIN EXT1_PIN_7
+#define AT86RFX_MISC_PIN EXT1_PIN_12
+#define AT86RFX_IRQ_PIN EXT1_PIN_9
+#define AT86RFX_SLP_PIN EXT1_PIN_10
+#define AT86RFX_SPI_CS EXT1_PIN_15
+#define AT86RFX_SPI_MOSI EXT1_PIN_16
+#define AT86RFX_SPI_MISO EXT1_PIN_17
+#define AT86RFX_SPI_SCK EXT1_PIN_18
+#define AT86RFX_CSD EXT1_PIN_5
+#define AT86RFX_CPS EXT1_PIN_8
+
+#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3
+
+#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
+#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX
+
+
+/** Enables the transceiver main interrupt. */
+#define ENABLE_TRX_IRQ() \
+ extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Disables the transceiver main interrupt. */
+#define DISABLE_TRX_IRQ() \
+ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Clears the transceiver main interrupt. */
+#define CLEAR_TRX_IRQ() \
+ extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+
+/*
+ * This macro saves the trx interrupt status and disables the trx interrupt.
+ */
+#define ENTER_TRX_REGION() \
+ { extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/*
+ * This macro restores the transceiver interrupt status
+ */
+#define LEAVE_TRX_REGION() \
+ extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+
+/** @} */
+
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/device.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 0 + +#define DEVICE_ANALOGIN 0 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 0 +#define DEVICE_SERIAL_FC 0 + +#define DEVICE_I2C 0 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 0 +#define DEVICE_SPISLAVE 0 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 0 +#define DEVICE_MAC_OFFSET 0 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/PeripheralPins.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,518 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+#define SERCOM_NULL 0xFF
+#define MUX_NULL 0xFF
+
+#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
+
+#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
+
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+};
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+ {PA04, UART_0, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA05, UART_0, 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+};
+
+/********SERCOM MAPPING*********/
+struct pin_sercom {
+ uint8_t pad_num; // a pin always mapped to a pad
+ uint8_t com_num[2]; // a pin always mapped to maximum of 2 sercoms
+// uint8_t pin_mux[2]; // Mux setting for the pin A,B...H ---> 0,1...7
+};
+struct pin_values {
+ uint8_t pin;
+ uint8_t pad;
+ uint8_t com;
+};
+
+struct pin_sercom SAM21[] = {{0, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA00
+ {1, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA01
+ {0, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA04
+ {1, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA05
+ {2, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA06
+ {3, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA07
+ {0, {0, 2}/*, {2, 3}*/}, // PA08
+ {1, {0, 2}/*, {2, 3}*/}, // PA09
+ {0, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA12
+ {1, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA13
+ {2, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA14
+ {3, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA15
+ {0, {1, 3}/*, {2, 3}*/}, // PA16
+ {1, {1, 3}/*, {2, 3}*/}, // PA17
+ {2, {1, 3}/*, {2, 3}*/}, // PA18
+ {3, {1, 3}/*, {2, 3}*/}, // PA19
+ {0, {3, 5}/*, {2, 3}*/}, // PA22
+ {1, {3, 5}/*, {2, 3}*/}, // PA23
+ {2, {3, 5}/*, {2, 3}*/}, // PA24
+ {3, {3, 5}/*, {2, 3}*/}, // PA25
+ {0, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA27
+ {1, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA28
+ {2, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA30
+ {3, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA31
+ {0, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB02
+ {1, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB03
+ {2, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB22
+ {3, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB23
+ {2, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB30
+ {1, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB31
+ {3, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PC18
+ {0, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/} // PC19
+};
+const PinMap PinMap_SERCOM_PINS[] = {
+ {PA00},
+ {PA01},
+ {PA04},
+ {PA05},
+ {PA06},
+ {PA07},
+ {PA08},
+ {PA09},
+ {PA12},
+ {PA13},
+ {PA14},
+ {PA15},
+ {PA16},
+ {PA17},
+ {PA18},
+ {PA19},
+ {PA22},
+ {PA23},
+ {PA24},
+ {PA25},
+ {PA27},
+ {PA28},
+ {PA30},
+ {PA31},
+
+ {PB02},
+ {PB03},
+ {PB22},
+ {PB23},
+ {PB30},
+ {PB31},
+
+ {PC18},
+ {PC19}
+
+};
+
+uint32_t pinmap_find_sercom_index (PinName pin, const PinMap* map)
+{
+ uint8_t count = 0;
+ while (map->pin != NC) {
+ if (map->pin == pin)
+ return count;
+ map++;
+ count++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_sercom_peripheral (PinName pin1, PinName pin2)
+{
+ uint8_t index1 = 0, index2 = 0;
+
+ if ((pin1 == (PinName)NC) || (pin2 == (PinName)NC)) {
+ return (uint32_t)NC;
+ }
+
+ index1 = pinmap_find_sercom_index(pin1, PinMap_SERCOM_PINS);
+ index2 = pinmap_find_sercom_index(pin2, PinMap_SERCOM_PINS);
+
+ if (SAM21[index1].com_num[1] == SERCOM_NULL) {
+ return SAM21[index1].com_num[0];
+ } else {
+ if ((SAM21[index1].com_num[0] == SAM21[index2].com_num[0]) || (SAM21[index1].com_num[0] == SAM21[index2].com_num[1])) {
+ return SAM21[index1].com_num[0];
+ } else {
+ return SAM21[index1].com_num[1];
+ }
+ }
+}
+
+uint32_t pinmap_sercom_pad (PinName pin)
+{
+ uint8_t index = 0;
+
+ if (pin == (PinName)NC)
+ return (uint32_t)NC;
+
+ index = pinmap_find_sercom_index(pin, PinMap_SERCOM_PINS);
+ return SAM21[index].pad_num;
+}
+
+uint32_t find_sercom_pinmux (struct pin_values* PinValues)
+{
+ switch (PinValues->com) {
+ case 0: // SERCOM0
+ switch (PinValues->pin) {
+ case PA04:
+ return PINMUX_PA04D_SERCOM0_PAD0;
+ break;
+ case PA08:
+ return PINMUX_PA08C_SERCOM0_PAD0;
+ break;
+ case PA05:
+ return PINMUX_PA05D_SERCOM0_PAD1;
+ break;
+ case PA09:
+ return PINMUX_PA09C_SERCOM0_PAD1;
+ break;
+ case PA06:
+ return PINMUX_PA06D_SERCOM0_PAD2;
+ break;
+ case PA10:
+ return PINMUX_PA10C_SERCOM0_PAD2;
+ break;
+ case PA07:
+ return PINMUX_PA07D_SERCOM0_PAD3;
+ break;
+ case PA11:
+ return PINMUX_PA11C_SERCOM0_PAD3;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1: // SERCOM1
+ switch (PinValues->pin) {
+ case PA16:
+ return PINMUX_PA16C_SERCOM1_PAD0;
+ break;
+ case PA00:
+ return PINMUX_PA00D_SERCOM1_PAD0;
+ break;
+ case PA17:
+ return PINMUX_PA17C_SERCOM1_PAD1;
+ break;
+ case PA01:
+ return PINMUX_PA01D_SERCOM1_PAD1;
+ break;
+ case PA30:
+ return PINMUX_PA30D_SERCOM1_PAD2;
+ break;
+ case PA18:
+ return PINMUX_PA18C_SERCOM1_PAD2;
+ break;
+ case PA31:
+ return PINMUX_PA31D_SERCOM1_PAD3;
+ break;
+ case PA19:
+ return PINMUX_PA19C_SERCOM1_PAD3;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2: // SERCOM2
+ switch (PinValues->pin) {
+ case PA08:
+ return PINMUX_PA08D_SERCOM2_PAD0;
+ break;
+ case PA12:
+ return PINMUX_PA12C_SERCOM2_PAD0;
+ break;
+ case PA09:
+ return PINMUX_PA09D_SERCOM2_PAD1;
+ break;
+ case PA13:
+ return PINMUX_PA13C_SERCOM2_PAD1;
+ break;
+ case PA10:
+ return PINMUX_PA10D_SERCOM2_PAD2;
+ break;
+ case PA14:
+ return PINMUX_PA14C_SERCOM2_PAD2;
+ break;
+ case PA11:
+ return PINMUX_PA11D_SERCOM2_PAD3;
+ break;
+ case PA15:
+ return PINMUX_PA15C_SERCOM2_PAD3;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3: // SERCOM3
+ switch (PinValues->pin) {
+ case PA16:
+ return PINMUX_PA16D_SERCOM3_PAD0;
+ break;
+ case PA22:
+ return PINMUX_PA22C_SERCOM3_PAD0;
+ break;
+ case PA27:
+ return PINMUX_PA27F_SERCOM3_PAD0;
+ break;
+ case PA17:
+ return PINMUX_PA17D_SERCOM3_PAD1;
+ break;
+ case PA23:
+ return PINMUX_PA23C_SERCOM3_PAD1;
+ break;
+ case PA28:
+ return PINMUX_PA28F_SERCOM3_PAD1;
+ break;
+ case PA18:
+ return PINMUX_PA18D_SERCOM3_PAD2;
+ break;
+ case PA20:
+ return PINMUX_PA20D_SERCOM3_PAD2;
+ break;
+ case PA24:
+ return PINMUX_PA24C_SERCOM3_PAD2;
+ break;
+ case PA19:
+ return PINMUX_PA19D_SERCOM3_PAD3;
+ break;
+ case PA25:
+ return PINMUX_PA25C_SERCOM3_PAD3;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 4: // SERCOM4
+ switch (PinValues->pin) {
+ case PA12:
+ return PINMUX_PA12D_SERCOM4_PAD0;
+ break;
+ case PB08:
+ return PINMUX_PB08D_SERCOM4_PAD0;
+ break;
+ case PC19:
+ return PINMUX_PC19F_SERCOM4_PAD0;
+ break;
+ case PA13:
+ return PINMUX_PA13D_SERCOM4_PAD1;
+ break;
+ case PB09:
+ return PINMUX_PB09D_SERCOM4_PAD1;
+ break;
+ case PB31:
+ return PINMUX_PB31F_SERCOM4_PAD1;
+ break;
+ case PA14:
+ return PINMUX_PA14D_SERCOM4_PAD2;
+ break;
+ case PB14:
+ return PINMUX_PB14C_SERCOM4_PAD2;
+ break;
+ case PB30:
+ return PINMUX_PB30F_SERCOM4_PAD2;
+ break;
+ case PA15:
+ return PINMUX_PA15D_SERCOM4_PAD3;
+ break;
+ case PB15:
+ return PINMUX_PB15C_SERCOM4_PAD3;
+ break;
+ case PC18:
+ return PINMUX_PC18F_SERCOM4_PAD3;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 5: // SERCOM5
+ switch (PinValues->pin) {
+ case PB16:
+ return PINMUX_PB16C_SERCOM5_PAD0;
+ break;
+ case PA22:
+ return PINMUX_PA22D_SERCOM5_PAD0;
+ break;
+ case PB02:
+ return PINMUX_PB02D_SERCOM5_PAD0;
+ break;
+ case PB30:
+ return PINMUX_PB30D_SERCOM5_PAD0;
+ break;
+ case PB17:
+ return PINMUX_PB17C_SERCOM5_PAD1;
+ break;
+ case PA23:
+ return PINMUX_PA23D_SERCOM5_PAD1;
+ break;
+ case PB03:
+ return PINMUX_PB03D_SERCOM5_PAD1;
+ break;
+ case PB31:
+ return PINMUX_PB31D_SERCOM5_PAD1;
+ break;
+ case PA24:
+ return PINMUX_PA24D_SERCOM5_PAD2;
+ break;
+ case PB00:
+ return PINMUX_PB00D_SERCOM5_PAD2;
+ break;
+ case PB22:
+ return PINMUX_PB22D_SERCOM5_PAD2;
+ break;
+ case PA20:
+ return PINMUX_PA20C_SERCOM5_PAD2;
+ break;
+ case PA25:
+ return PINMUX_PA25D_SERCOM5_PAD3;
+ break;
+ case PB23:
+ return PINMUX_PB23D_SERCOM5_PAD3;
+ break;
+ default:
+ break;
+ }
+ break;
+ }
+}
+uint32_t find_mux_setting (PinName output, PinName input, PinName clock, PinName chipsel)
+{
+ struct pin_values input_values, output_values, clock_values, chipsel_values;
+ uint32_t mux_setting = 0;
+
+ input_values.pin = input;
+ output_values.pin = output;
+ clock_values.pin = clock;
+ chipsel_values.pin = chipsel;
+
+ input_values.com = pinmap_sercom_peripheral(input, output);
+ output_values.com = input_values.com;
+ clock_values.com = input_values.com;
+ chipsel_values.com = input_values.com;
+
+ input_values.pad = pinmap_sercom_pad(input);
+ output_values.pad = pinmap_sercom_pad(output);
+ clock_values.pad = pinmap_sercom_pad(clock);
+ chipsel_values.pad = pinmap_sercom_pad(chipsel);
+
+ switch(input_values.pad) { //TODO: Condition for hardware flow control enabled is different.
+ case 0:
+ mux_setting |= SERCOM_USART_CTRLA_RXPO(0);
+ break;
+ case 1:
+ mux_setting |= SERCOM_USART_CTRLA_RXPO(1);
+ break;
+ case 2:
+ mux_setting |= SERCOM_USART_CTRLA_RXPO(2);
+ break;
+ case 3:
+ mux_setting |= SERCOM_USART_CTRLA_RXPO(3);
+ break;
+ }
+
+ if ((clock == NC) && (chipsel == NC)) { // condition for no hardware control and uart
+ if ((output_values.pad == 0)) { // condition for hardware enable and usart is different
+ mux_setting |= SERCOM_USART_CTRLA_TXPO(0);
+ } else if((output_values.pad == 2)) {
+ mux_setting |= SERCOM_USART_CTRLA_TXPO(1);
+ } else {
+ mux_setting = mux_setting; // dummy condition
+ }
+ } else { // for hardware flow control and uart // expecting the tx in pad 0, rts in pad2 and cts in pad 3
+ if((output_values.pad == 0) && (clock_values.pad/*rts pin*/ == 2) && (chipsel_values.pad/*cts pin*/ == 3)) {
+ mux_setting |= SERCOM_USART_CTRLA_TXPO(2);
+ }
+ }
+
+ return mux_setting;
+}
+
+void find_pin_settings (PinName output, PinName input, PinName clock, PinName chipsel, uint32_t* pad_pinmuxes)
+{
+ struct pin_values input_values, output_values, clock_values, chipsel_values;
+ uint8_t i = 0;
+
+ for (i = 0; i < 4 ; i++ ) { // load default values for the pins
+ pad_pinmuxes[i] = 0xFFFFFFFF; //PINMUX_UNUSED
+ }
+
+ input_values.pin = input;
+ output_values.pin = output;
+ clock_values.pin = clock;
+ chipsel_values.pin = chipsel;
+
+ input_values.com = pinmap_sercom_peripheral(input, output);
+ output_values.com = input_values.com;
+ clock_values.com = input_values.com;
+ chipsel_values.com = input_values.com;
+
+ input_values.pad = pinmap_sercom_pad(input);
+ output_values.pad = pinmap_sercom_pad(output);
+ clock_values.pad = pinmap_sercom_pad(clock);
+ chipsel_values.pad = pinmap_sercom_pad(chipsel);
+
+ if (input_values.pad < 0x04)
+ pad_pinmuxes[input_values.pad] = find_sercom_pinmux(&input_values);
+ if (output_values.pad < 0x04)
+ pad_pinmuxes[output_values.pad] = find_sercom_pinmux(&output_values);
+ if (clock_values.pad < 0x04)
+ pad_pinmuxes[clock_values.pad] = find_sercom_pinmux(&clock_values);
+ if (chipsel_values.pad < 0x04)
+ pad_pinmuxes[chipsel_values.pad] = find_sercom_pinmux(&chipsel_values);
+
+}
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "compiler.h"
+#include "system.h"
+
+uint8_t g_sys_init = 0;
+
+//called before main - implement here if board needs it ortherwise, let
+// the application override this if necessary
+//TODO: To be implemented by adding system init and board init
+void mbed_sdk_init()
+{
+ if(g_sys_init == 0) {
+ g_sys_init = 1;
+ system_init();
+ }
+}
+/***************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,521 @@
+/**
+ * \file
+ *
+ * \brief SAM R21 Xplained Pro board definition
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef SAMR21_XPLAINED_PRO_H_INCLUDED
+#define SAMR21_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samr21_xplained_pro_group SAM R21 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samr21_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME "SAMR21_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ * @{ */
+#define BOARD_FREQ_SLCK_XTAL (32768U)
+#define BOARD_FREQ_SLCK_BYPASS (32768U)
+#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
+#define BOARD_MCK CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US 15625
+/** @} */
+
+/** \name LED0 definitions
+ * @{ */
+#define LED0_PIN PIN_PA19
+#define LED0_ACTIVE false
+#define LED0_INACTIVE !LED0_ACTIVE
+#define LED0 LED0_PIN
+/** @} */
+
+/** \name SW0 definitions
+ * @{ */
+#define SW0_PIN PIN_PA28
+#define SW0_ACTIVE false
+#define SW0_INACTIVE !SW0_ACTIVE
+#define SW0_EIC_PIN PIN_PA28A_EIC_EXTINT8
+#define SW0_EIC_MUX MUX_PA28A_EIC_EXTINT8
+#define SW0_EIC_PINMUX PINMUX_PA28A_EIC_EXTINT8
+#define SW0_EIC_LINE 8
+/** @} */
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * @{ */
+#define LED_0_NAME "LED0 (yellow)"
+#define LED_0_PIN LED0_PIN
+#define LED_0_ACTIVE LED0_ACTIVE
+#define LED_0_INACTIVE LED0_INACTIVE
+#define LED0_GPIO LED0_PIN
+
+#define LED_0_PWM_MODULE TC3
+#define LED_0_PWM_CHANNEL 1
+#define LED_0_PWM_OUTPUT 1
+#define LED_0_PWM_PIN PIN_PA19E_TC3_WO1
+#define LED_0_PWM_MUX MUX_PA19E_TC3_WO1
+#define LED_0_PWM_PINMUX PINMUX_PA19E_TC3_WO1
+
+#define LED_0_PWM4CTRL_MODULE TCC0
+#define LED_0_PWM4CTRL_CHANNEL 3
+#define LED_0_PWM4CTRL_OUTPUT 3
+#define LED_0_PWM4CTRL_PIN PIN_PA19F_TCC0_WO3
+#define LED_0_PWM4CTRL_MUX MUX_PA19F_TCC0_WO3
+#define LED_0_PWM4CTRL_PINMUX PINMUX_PA19F_TCC0_WO3
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT 1
+
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * @{ */
+#define BUTTON_0_NAME "SW0"
+#define BUTTON_0_PIN SW0_PIN
+#define BUTTON_0_ACTIVE SW0_ACTIVE
+#define BUTTON_0_INACTIVE SW0_INACTIVE
+#define BUTTON_0_EIC_PIN SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ * @{
+ */
+#define EXT1_PIN_3 PIN_PA06
+#define EXT1_PIN_4 PIN_PA07
+#define EXT1_PIN_5 PIN_PA13
+#define EXT1_PIN_6 PIN_PA28
+#define EXT1_PIN_7 PIN_PA18
+#define EXT1_PIN_8 PIN_PA19
+#define EXT1_PIN_9 PIN_PA22
+#define EXT1_PIN_10 PIN_PA23
+#define EXT1_PIN_11 PIN_PA16
+#define EXT1_PIN_12 PIN_PA17
+#define EXT1_PIN_13 PIN_PA05
+#define EXT1_PIN_14 PIN_PA04
+#define EXT1_PIN_15 PIN_PB03
+#define EXT1_PIN_16 PIN_PB22
+#define EXT1_PIN_17 PIN_PB02
+#define EXT1_PIN_18 PIN_PB23
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ * @{
+ */
+#define EXT1_PIN_ADC_0 EXT1_PIN_3
+#define EXT1_PIN_ADC_1 EXT1_PIN_4
+#define EXT1_PIN_GPIO_0 EXT1_PIN_5
+#define EXT1_PIN_GPIO_1 EXT1_PIN_6
+#define EXT1_PIN_PWM_0 EXT1_PIN_7
+#define EXT1_PIN_PWM_1 EXT1_PIN_8
+#define EXT1_PIN_GPIO_3 EXT1_PIN_9
+#define EXT1_PIN_GPIO_4 EXT1_PIN_10
+#define EXT1_PIN_I2C_SDA EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL EXT1_PIN_12
+#define EXT1_PIN_UART_RX EXT1_PIN_13
+#define EXT1_PIN_UART_TX EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ * @{
+ */
+#define EXT1_ADC_MODULE ADC
+#define EXT1_ADC_0_CHANNEL 6
+#define EXT1_ADC_0_PIN PIN_PA06B_ADC_AIN6
+#define EXT1_ADC_0_MUX MUX_PA06B_ADC_AIN6
+#define EXT1_ADC_0_PINMUX PINMUX_PA06B_ADC_AIN6
+#define EXT1_ADC_1_CHANNEL 7
+#define EXT1_ADC_1_PIN PIN_PA07B_ADC_AIN7
+#define EXT1_ADC_1_MUX MUX_PA07B_ADC_AIN7
+#define EXT1_ADC_1_PINMUX PINMUX_PA07B_ADC_AIN7
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ * @{
+ */
+#define EXT1_PWM_MODULE TC3
+#define EXT1_PWM_0_CHANNEL 0
+#define EXT1_PWM_0_PIN PIN_PA18E_TC3_WO0
+#define EXT1_PWM_0_MUX MUX_PA18E_TC3_WO0
+#define EXT1_PWM_0_PINMUX PINMUX_PA18E_TC3_WO0
+#define EXT1_PWM_1_CHANNEL 1
+#define EXT1_PWM_1_PIN PIN_PA19E_TC3_WO1
+#define EXT1_PWM_1_MUX MUX_PA19E_TC3_WO1
+#define EXT1_PWM_1_PINMUX PINMUX_PA19E_TC3_WO1
+/** @} */
+
+/** \name Extension header #1 PWM for Control definitions
+ * @{
+ */
+#define EXT1_PWM4CTRL_MODULE TCC0
+#define EXT1_PWM4CTRL_0_CHANNEL 2
+#define EXT1_PWM4CTRL_0_OUTPUT 2
+#define EXT1_PWM4CTRL_0_PIN PIN_PA18F_TCC0_WO2
+#define EXT1_PWM4CTRL_0_MUX MUX_PA18F_TCC0_WO2
+#define EXT1_PWM4CTRL_0_PINMUX PINMUX_PA18F_TCC0_WO2
+#define EXT1_PWM4CTRL_1_CHANNEL 3
+#define EXT1_PWM4CTRL_1_OUTPUT 3
+#define EXT1_PWM4CTRL_1_PIN PIN_PA19F_TCC0_WO3
+#define EXT1_PWM4CTRL_1_MUX MUX_PA19F_TCC0_WO3
+#define EXT1_PWM4CTRL_1_PINMUX PINMUX_PA19F_TCC0_WO3
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT1_IRQ_MODULE EIC
+#define EXT1_IRQ_INPUT 6
+#define EXT1_IRQ_PIN PIN_PA22A_EIC_EXTINT6
+#define EXT1_IRQ_MUX MUX_PA22A_EIC_EXTINT6
+#define EXT1_IRQ_PINMUX PINMUX_PA22A_EIC_EXTINT6
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ * @{
+ */
+#define EXT1_I2C_MODULE SERCOM1
+#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
+#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
+#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ * @{
+ */
+#define EXT1_UART_MODULE SERCOM0
+#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
+#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ * @{
+ */
+#define EXT1_SPI_MODULE SERCOM5
+#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB03D_SERCOM5_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ * @{
+ */
+#define EXT3_PIN_5 PIN_PA15
+#define EXT3_PIN_10 PIN_PA08
+#define EXT3_PIN_11 PIN_PA16
+#define EXT3_PIN_12 PIN_PA17
+#define EXT3_PIN_15 PIN_PA14
+#define EXT3_PIN_16 PIN_PB22
+#define EXT3_PIN_17 PIN_PB02
+#define EXT3_PIN_18 PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ * @{
+ */
+#define EXT3_PIN_GPIO_0 EXT3_PIN_5
+#define EXT3_PIN_GPIO_1 EXT3_PIN_10
+#define EXT3_PIN_I2C_SDA EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL EXT3_PIN_12
+#define EXT3_PIN_GPIO_2 EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ * @{
+ */
+#define EXT3_SPI_SLAVE_SELECT_PIN PIN_PA14
+#define EXT3_SPI_MODULE SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
+#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 Dataflash
+ * @{
+ */
+#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
+#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
+/** @} */
+
+/** \name USB definitions
+ * @{
+ */
+#define USB_ID
+#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
+#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
+#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
+#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
+#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
+#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
+#define USB_VBUS_PIN PIN_PA07
+#define USB_VBUS_EIC_LINE 7
+#define USB_VBUS_EIC_MUX MUX_PA07A_EIC_EXTINT7
+#define USB_VBUS_EIC_PINMUX PINMUX_PA07A_EIC_EXTINT7
+/* USB ID pin is not connected */
+//#define USB_ID_PIN -1
+//#define USB_ID_EIC_LINE -1
+//#define USB_ID_EIC_MUX -1
+//#define USB_ID_EIC_PINMUX -1
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN PIN_PA08
+#define EDBG_GPIO1_PIN PIN_PA09
+#define EDBG_GPIO2_PIN PIN_PA12
+#define EDBG_GPIO3_PIN PIN_PA14
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE -1 /* Not available on this board */
+#define EDBG_UART_RX_PIN -1 /* Not available on this board */
+#define EDBG_UART_RX_MUX -1 /* Not available on this board */
+#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
+#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
+#define EDBG_UART_TX_PIN -1 /* Not available on this board */
+#define EDBG_UART_TX_MUX -1 /* Not available on this board */
+#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
+#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE SERCOM1
+#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
+#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
+#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_SLAVE_SELECT_PIN PIN_PA27
+#define EDBG_SPI_MODULE SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
+#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE SERCOM0
+#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
+#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
+#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
+#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
+/** @} */
+
+#define RF_SPI_MODULE SERCOM4
+#define RF_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define RF_SPI_SERCOM_PINMUX_PAD0 PINMUX_PC19F_SERCOM4_PAD0
+#define RF_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
+#define RF_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB30F_SERCOM4_PAD2
+#define RF_SPI_SERCOM_PINMUX_PAD3 PINMUX_PC18F_SERCOM4_PAD3
+
+
+#define RF_IRQ_MODULE EIC
+#define RF_IRQ_INPUT 0
+#define RF_IRQ_PIN PIN_PB00A_EIC_EXTINT0
+#define RF_IRQ_MUX MUX_PB00A_EIC_EXTINT0
+#define RF_IRQ_PINMUX PINMUX_PB00A_EIC_EXTINT0
+
+/** \name 802.15.4 TRX Interface definitions
+ * @{
+ */
+
+#define AT86RFX_SPI SERCOM4
+#define AT86RFX_RST_PIN PIN_PB15
+#define AT86RFX_IRQ_PIN PIN_PB00
+#define AT86RFX_SLP_PIN PIN_PA20
+#define AT86RFX_SPI_CS PIN_PB31
+#define AT86RFX_SPI_MOSI PIN_PB30
+#define AT86RFX_SPI_MISO PIN_PC19
+#define AT86RFX_SPI_SCK PIN_PC18
+#define PIN_RFCTRL1 PIN_PA09
+#define PIN_RFCTRL2 PIN_PA12
+#define RFCTRL_CFG_ANT_DIV 4
+
+
+#define AT86RFX_SPI_SERCOM_MUX_SETTING RF_SPI_SERCOM_MUX_SETTING
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 RF_SPI_SERCOM_PINMUX_PAD0
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 RF_SPI_SERCOM_PINMUX_PAD2
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 RF_SPI_SERCOM_PINMUX_PAD3
+
+#define AT86RFX_IRQ_CHAN RF_IRQ_INPUT
+#define AT86RFX_IRQ_PINMUX RF_IRQ_PINMUX
+
+
+/** Enables the transceiver main interrupt. */
+#define ENABLE_TRX_IRQ() \
+ extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Disables the transceiver main interrupt. */
+#define DISABLE_TRX_IRQ() \
+ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Clears the transceiver main interrupt. */
+#define CLEAR_TRX_IRQ() \
+ extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+
+/*
+ * This macro saves the trx interrupt status and disables the trx interrupt.
+ */
+#define ENTER_TRX_REGION() \
+ { extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/*
+ * This macro restores the transceiver interrupt status
+ */
+#define LEAVE_TRX_REGION() \
+ extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+
+/** @} */
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAMR21_XPLAINED_PRO_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/device.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,62 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 0 + +#define DEVICE_ANALOGIN 0 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 +#define DEVICE_SERIAL_ASYNCH 1 + +#define DEVICE_I2C 0 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 +#define DEVICE_SPI_ASYNCH 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 0 +#define DEVICE_MAC_OFFSET 0 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/dma_api.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,372 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "system.h"
+#include "dma_api.h"
+#include "dma_api_HAL.h"
+
+#include <math.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+/**
+ * \internal
+ * Structure redefinition, already defined in dma.c.
+ * Redefining as that definition is not available here
+ */
+struct _dma_module {
+ volatile bool _dma_init;
+ volatile uint32_t allocated_channels;
+ uint8_t free_channels;
+};
+
+extern struct _dma_module _dma_inst;
+extern uint8_t g_sys_init;
+
+static struct dma_instance_s dma_channels[CONF_MAX_USED_CHANNEL_NUM];
+
+/**
+ * \internal
+ * Get resource index from channel id
+ *
+ * @param[in] channelid Valid DMA channel id
+ * @return index to DMA instance
+ */
+static uint8_t get_index_from_id(int channelid)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
+
+ uint8_t i;
+
+ for (i=0; i<CONF_MAX_USED_CHANNEL_NUM; i++) {
+ if ((dma_channels[i].status & DMA_ALLOCATED)
+ && (dma_channels[i].resource.channel_id == channelid)) {
+ break;
+ }
+ }
+
+ return i;
+}
+
+/**
+ * \internal
+ * Handler function for DMA callback
+ *
+ * @param[in] resource pointer to the resource
+ * @return void
+ */
+static void dma_handler(const struct dma_resource* const resource)
+{
+ MBED_ASSERT(resource);
+ void (*callback_func)(void);
+
+ uint8_t channelid = resource->channel_id;
+ uint8_t channel_index;
+
+ channel_index = get_index_from_id(channelid);
+ if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
+ return;
+ }
+
+ callback_func = dma_channels[channel_index].handler;
+ if (callback_func) {
+ callback_func();
+ }
+}
+
+/**
+ * \internal
+ * Configure a DMA channel for specified resource
+ *
+ * @param[in] channel_index index to the resource
+ * @return void
+ */
+static void configure_dma_resource(uint8_t channel_index)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(channel_index < CONF_MAX_USED_CHANNEL_NUM);
+
+ enum status_code ret;
+ struct dma_resource_config config;
+
+ if (dma_channels[channel_index].status & DMA_ALLOCATED) {
+ return;
+ }
+
+ /* Get default configuration for DMA */
+ dma_get_config_defaults(&config);
+
+ /* Allocate a free channel */
+ ret = dma_allocate(&dma_channels[channel_index].resource, &config);
+
+ if (ret == STATUS_OK) {
+ dma_channels[channel_index].status = DMA_ALLOCATED;
+ }
+}
+
+/** Setup a DMA descriptor for specified resource
+ *
+ * @param[in] channel_index DMA channel id
+ * @param[in] src source address
+ * @param[in] src_inc_enable source address auto increment enable flag
+ * @param[in] desc destination address
+ * @param[in] desc_inc_enable destination address auto increment enable flag
+ * @param[in] length length of data to be transferred
+ * @param[in] beat_size beat size to be set
+ * @return void
+ */
+void dma_setup_transfer(uint8_t channelid, uint32_t src, bool src_inc_enable, uint32_t desc, bool desc_inc_enable, uint32_t length, uint8_t beat_size)
+{
+ enum status_code result;
+ uint8_t channel_index;
+ struct dma_descriptor_config descriptor_config;
+
+ /* Sanity check arguments */
+ MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
+ MBED_ASSERT(src);
+ MBED_ASSERT(desc);
+
+ channel_index = get_index_from_id(channelid);
+
+ dma_descriptor_get_config_defaults(&descriptor_config);
+
+ if (beat_size <= 8) {
+ descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE;
+ } else if ((beat_size > 8) && (beat_size <= 16)) {
+ descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD;
+ } else {
+ descriptor_config.beat_size = DMA_BEAT_SIZE_WORD;
+ }
+ descriptor_config.block_transfer_count = length;
+ descriptor_config.source_address = src;
+ descriptor_config.destination_address = desc;
+
+ /* Source address auto-increment is enabled by default */
+ if (!src_inc_enable) {
+ descriptor_config.src_increment_enable = false;
+ }
+
+ /* Destination address auto-increment is enabled by default */
+ if (!desc_inc_enable) {
+ descriptor_config.dst_increment_enable = false;
+ }
+
+ dma_descriptor_create(&dma_channels[channel_index].descriptor, &descriptor_config);
+
+ /* Add descriptor to resource */
+ if (dma_channels[channel_index].resource.descriptor == NULL) {
+ /* Multiple calls to this function without releasing already allocated channel is not handled now */
+ result = dma_add_descriptor(&dma_channels[channel_index].resource, &dma_channels[channel_index].descriptor);
+ if (result != STATUS_OK) {
+ dma_channels[channel_index].status |= DMA_ERROR;
+ }
+ }
+}
+
+
+/** Initialize the DMA
+ *
+ * Configures clock for DMAC
+ */
+void dma_init()
+{
+ int i;
+
+ if (g_sys_init == 0) {
+ system_init();
+ g_sys_init = 1;
+ }
+
+ if (!_dma_inst._dma_init) {
+ for (i=0; i<CONF_MAX_USED_CHANNEL_NUM; i++) {
+ dma_channels[i].status = DMA_NOT_USED;
+ }
+ }
+ /* Do nothing for now. ASF does the clock init when allocating channel */
+}
+
+/** Allocates channel for DMA
+ *
+ * Allocates channel for DMA with specified capability
+ * @param[in] capabilities Capability of DMA channel
+ */
+int dma_channel_allocate(uint32_t capabilities)
+{
+ uint8_t channel_index = 0;
+
+ for (channel_index=0; channel_index<CONF_MAX_USED_CHANNEL_NUM; channel_index++) {
+ if (dma_channels[channel_index].status == DMA_NOT_USED) {
+ break;
+ }
+ }
+
+ if (channel_index != CONF_MAX_USED_CHANNEL_NUM) {
+ configure_dma_resource(channel_index);
+ if (dma_channels[channel_index].status & DMA_ALLOCATED) {
+ return dma_channels[channel_index].resource.channel_id;
+ }
+ }
+
+ /* Couldn't find a channel. */
+ return DMA_ERROR_OUT_OF_CHANNELS;
+}
+
+/** Start DMA transfer
+ *
+ * Kick starts transfer in DMA channel with specified channel id
+ * @param[in] channelid Channel id of DMA channel
+ * @return zero if success otherwise non zero
+ */
+bool dma_start_transfer(int channelid)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
+
+ uint8_t channel_index;
+
+ channel_index = get_index_from_id(channelid);
+
+ if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
+ /* Return invalid value for now */
+ return false;
+ }
+
+ if (!(dma_channels[channel_index].status & DMA_ALLOCATED)) {
+ /* DMA not allocated, return invalid value for now */
+ return false;
+ }
+
+ /* Start DMA transfer */
+ if (STATUS_OK != dma_start_transfer_job(&dma_channels[channel_index].resource)) {
+ /* Error in starting DMA transfer */
+ return false;
+ }
+
+ return true;
+}
+
+/** DMA channel busy check
+ *
+ * To check whether DMA channel is busy with a job or not
+ * @param[in] channelid Channel id of DMA channel
+ * @return non zero if busy otherwise zero
+ */
+bool dma_busy(int channelid)
+{
+ int res = 0;
+ /* Sanity check arguments */
+ MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
+
+ uint8_t channel_index;
+
+ channel_index = get_index_from_id(channelid);
+
+ if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
+ /* This channel is not active! return zero for now */
+ res = 0;
+ }
+
+ return dma_is_busy(&dma_channels[channel_index].resource);
+}
+
+/** DMA channel transfer completion check
+ *
+ * To check whether DMA channel job is completed or not
+ * @param[in] channelid Channel id of DMA channel
+ * @return non zero if busy otherwise zero
+ */
+bool dma_is_transfer_complete(int channelid)
+{
+ int res = 0;
+ /* Sanity check arguments */
+ MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
+
+ uint8_t channel_index;
+
+ channel_index = get_index_from_id(channelid);
+
+ if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
+ /* This channel is not active! return zero for now */
+ res = 0;
+ }
+
+ return (STATUS_OK == dma_get_job_status(&dma_channels[channel_index].resource));
+}
+
+/** Registers callback function for DMA
+ *
+ * Registers callback function for DMA for specified events
+ * @param[in] channelid Channel id of DMA channel
+ * @param[in] handler Callback function pointer
+ * @param[in] event Events mask
+ * @return void
+ */
+void dma_set_handler(int channelid, uint32_t handler, uint32_t event)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
+
+ uint8_t channel_index;
+
+ channel_index = get_index_from_id(channelid);
+
+ if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
+ /* Return for now */
+ return;
+ }
+
+ dma_channels[channel_index].handler = handler;
+ if (event & DMA_TRANSFER_ERROR) {
+ dma_register_callback(&dma_channels[channel_index].resource, dma_handler, DMA_CALLBACK_TRANSFER_ERROR);
+ }
+ if (event & DMA_TRANSFER_COMPLETE) {
+ dma_register_callback(&dma_channels[channel_index].resource, dma_handler, DMA_CALLBACK_TRANSFER_DONE);
+ }
+
+ /* Set interrupt vector if someone have removed it */
+ NVIC_SetVector(DMAC_IRQn, (uint32_t)DMAC_Handler);
+ /* Enable interrupt */
+ NVIC_EnableIRQ(DMAC_IRQn);
+}
+
+/** Frees an allocated DMA channel
+ *
+ * Frees an already allocated DMA channel with specified channel id
+ * @param[in] channelid Channel id of DMA channel to be disabled
+ * @return zero if success
+ */
+int dma_channel_free(int channelid)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
+
+ uint8_t channel_index;
+
+ channel_index = get_index_from_id(channelid);
+
+ if (STATUS_OK == dma_free(&dma_channels[channel_index].resource)) {
+ dma_channels[channel_index].status = DMA_NOT_USED;
+ dma_channels[channel_index].resource.descriptor = NULL;
+ return 0;
+ } else {
+ /* Return invalid value for now */
+ return -1;
+ }
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/dma_api_HAL.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _DMA_API_HAL_H
+#define _DMA_API_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include "dma.h"
+
+enum dma_status_flags {
+ DMA_NOT_USED = (uint32_t)1,
+ DMA_ALLOCATED = (DMA_NOT_USED << 1),
+ DMA_TEMPORARY = (DMA_NOT_USED << 2),
+ DMA_ERROR = (DMA_NOT_USED << 3),
+};
+
+/* No other capabilities supported now */
+#define DMA_CAP_NONE 0
+
+#define DMA_ADDRESS_INC_DISABLE 0
+#define DMA_ADDRESS_INC_ENABLE 1
+
+#define DMA_TRANSFER_ERROR ((uint32_t)1 << 1)
+#define DMA_TRANSFER_COMPLETE ((uint32_t)1 << 2)
+
+#define DMA_EVENT_ALL (DMA_TRANSFER_ERROR | DMA_TRANSFER_COMPLETE)
+
+
+COMPILER_ALIGNED(16)
+struct dma_instance_s {
+ struct dma_resource resource;
+ DmacDescriptor descriptor;
+ uint8_t status;
+ uint32_t events;
+ uint32_t handler;
+};
+
+/** Setup a DMA descriptor for specified resource
+ *
+ * @param[in] channel_index DMA channel id
+ * @param[in] src source address
+ * @param[in] src_inc_enable source address auto increment enable flag
+ * @param[in] desc destination address
+ * @param[in] desc_inc_enable destination address auto increment enable flag
+ * @param[in] length length of data to be transferred
+ * @param[in] beat_size beat size to be set
+ * @return void
+ */
+void dma_setup_transfer(uint8_t channelid, uint32_t src, bool src_inc_enable, uint32_t desc, bool desc_inc_enable, uint32_t length, uint8_t beat_size);
+
+/** Start DMA transfer
+ *
+ * Kick starts transfer in DMA channel with specified channel id
+ * @param[in] channelid Channel id of DMA channel
+ * @return non zero if success otherwise zero
+ */
+bool dma_start_transfer(int channelid);
+
+/** DMA channel busy check
+ *
+ * To check whether DMA channel is busy with a job or not
+ * @param[in] channelid Channel id of DMA channel
+ * @return non zero if busy otherwise zero
+ */
+bool dma_busy(int channelid);
+
+/** DMA channel transfer completion check
+ *
+ * To check whether DMA channel job is completed or not
+ * @param[in] channelid Channel id of DMA channel
+ * @return non zero if busy otherwise zero
+ */
+bool dma_is_transfer_complete(int channelid);
+
+/** Registers callback function for DMA
+ *
+ * Registers callback function for DMA for specified events
+ * @param[in] channelid Channel id of DMA channel
+ * @param[in] handler Callback function pointer
+ * @param[in] event Events mask
+ * @return void
+ */
+void dma_set_handler(int channelid, uint32_t handler, uint32_t event);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DMA_API_HAL_H */
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1083 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef ADC_H_INCLUDED
+#define ADC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_adc_group SAM Analog to Digital Converter Driver (ADC)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the device's Analog to Digital Converter functionality, for
+ * the conversion of analog voltages into a corresponding digital form.
+ * The following driver API modes are covered by this manual:
+ * - Polled APIs
+ * \if ADC_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ * - ADC (Analog to Digital Converter)
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SUPPORT
+ * - Atmel | SMART SAM L21
+ * \else
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_adc_prerequisites
+ * - \ref asfdoc_sam0_adc_module_overview
+ * - \ref asfdoc_sam0_adc_special_considerations
+ * - \ref asfdoc_sam0_adc_extra_info
+ * - \ref asfdoc_sam0_adc_examples
+ * - \ref asfdoc_sam0_adc_api_overview
+ *
+ *
+ * \section asfdoc_sam0_adc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_adc_module_overview Module Overview
+ *
+ * This driver provides an interface for the Analog-to-Digital conversion
+ * functions on the device, to convert analog voltages to a corresponding
+ * digital value. The ADC has up to 12-bit resolution, and is capable of
+ * \if DEVICE_SAML21_SUPPORT
+ * converting up to 1,000,000 samples per second (1 Msps).
+ * \else
+ * converting up to 500K samples per second (Ksps).
+ * \endif
+ *
+ * The ADC has a compare function for accurate monitoring of user defined
+ * thresholds with minimum software intervention required.
+ * The ADC may be configured for 8-, 10-, or 12-bit result, reducing the
+ * conversion time. ADC conversion results are provided left or right adjusted
+ * which eases calculation when the result is represented as a signed integer.
+ *
+ * The input selection is flexible, and both single-ended and differential
+ * measurements can be made. For differential measurements, an optional gain
+ * stage is available to increase the dynamic range. In addition, several
+ * internal signal inputs are available. The ADC can provide both signed and
+ * unsigned results.
+ *
+ * The ADC measurements can either be started by application software or an
+ * incoming event from another peripheral in the device, and both internal and
+ * external reference voltages can be selected.
+ *
+ * \note Internal references will be enabled by the driver, but not disabled.
+ * Any reference not used by the application should be disabled by the application.
+ *
+ * A simplified block diagram of the ADC can be seen in
+ * \ref asfdoc_sam0_adc_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_adc_module_block_diagram
+ * \dot
+ * digraph overview {
+ * splines = false;
+ * rankdir=LR;
+ *
+ * mux1 [label="Positive input", shape=box];
+ * mux2 [label="Negative input", shape=box];
+ *
+ *
+ * mux3 [label="Reference", shape=box];
+ *
+ * adc [label="ADC", shape=polygon, sides=5, orientation=90, distortion=-0.6, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ * prescaler [label="PRESCALER", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * mux1 -> adc;
+ * mux2 -> adc;
+ * mux3 -> adc:sw;
+ * prescaler -> adc;
+ *
+ * postproc [label="Post processing", shape=box];
+ * result [label="RESULT", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * adc:e -> postproc:w;
+ * postproc:e -> result:w;
+ *
+ * {rank=same; mux1 mux2}
+ * {rank=same; prescaler adc}
+ *
+ * }
+ * \enddot
+ *
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_prescaler Sample Clock Prescaler
+ * The ADC features a prescaler, which enables conversion at lower clock rates
+ * than the input Generic Clock to the ADC module. This feature can be used to
+ * lower the synchronization time of the digital interface to the ADC module
+ * via a high speed Generic Clock frequency, while still allowing the ADC
+ * sampling rate to be reduced.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_resolution ADC Resolution
+ * The ADC supports full 8-bit, 10-bit, or 12-bit resolution. Hardware
+ * oversampling and decimation can be used to increase the
+ * effective resolution at the expense of throughput. Using oversampling and
+ * decimation mode the ADC resolution is increased from 12-bit to an effective
+ * 13-, 14-, 15-, or 16-bit. In these modes the conversion rate is reduced, as
+ * a greater number of samples is used to achieve the increased resolution. The
+ * available resolutions and effective conversion rate is listed in
+ * \ref asfdoc_sam0_adc_module_conversion_rate "the table below".
+ *
+ * \anchor asfdoc_sam0_adc_module_conversion_rate
+ * <table>
+ * <caption>Effective ADC Conversion Speed Using Oversampling</caption>
+ * <tr>
+ * <th>Resolution</th>
+ * <th>Effective conversion rate</th>
+ * </tr>
+ * <tr>
+ * <td>13-bit</td>
+ * <td>Conversion rate divided by 4</td>
+ * </tr>
+ * <tr>
+ * <td>14-bit</td>
+ * <td>Conversion rate divided by 16</td>
+ * </tr>
+ * <tr>
+ * <td>15-bit</td>
+ * <td>Conversion rate divided by 64</td>
+ * </tr>
+ * <tr>
+ * <td>16-bit</td>
+ * <td>Conversion rate divided by 256</td>
+ * </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_conversion Conversion Modes
+ * ADC conversions can be software triggered on demand by the user application,
+ * if continuous sampling is not required. It is also possible to configure the
+ * ADC in free-running mode, where new conversions are started as soon as the
+ * previous conversion is completed, or configure the ADC to scan across a
+ * number of input pins (see \ref asfdoc_sam0_adc_module_overview_pin_scan).
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_diff_mode Differential and Single-Ended Conversion
+ * The ADC has two conversion modes; differential and single-ended. When
+ * measuring signals where the positive input pin is always at a higher voltage
+ * than the negative input pin, the single-ended conversion mode should be used
+ * in order to achieve a full 12-bit output resolution.
+ *
+ * If however the positive input pin voltage may drop below the negative input
+ * pin the signed differential mode should be used.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_sample_time Sample Time
+ * The sample time for each ADC conversion is configurable as a number of half
+ * prescaled ADC clock cycles (depending on the prescaler value), allowing the
+ * user application to achieve faster or slower sampling depending on the
+ * source impedance of the ADC input channels. For applications with high
+ * impedance inputs the sample time can be increased to give the ADC an adequate
+ * time to sample and convert the input channel.
+ *
+ * The resulting sampling time is given by the following equation:
+ * \f[
+ * t_{SAMPLE} = (sample\_length+1) \times \frac{ADC_{CLK}} {2}
+ * \f]
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_averaging Averaging
+ * The ADC can be configured to trade conversion speed for accuracy by averaging
+ * multiple samples in hardware. This feature is suitable when operating in
+ * noisy conditions.
+ *
+ * You can specify any number of samples to accumulate (up to 1024) and the
+ * divide ratio to use (up to divide by 128). To modify these settings the
+ * ADC_RESOLUTION_CUSTOM needs to be set as the resolution. When this is set
+ * the number of samples to accumulate and the division ratio can be set by
+ * the configuration struct members \ref adc_config.accumulate_samples and
+ * \ref adc_config.divide_result. When using this mode the ADC result register
+ * will be set to be 16-bit wide to accommodate the larger result sizes
+ * produced by the accumulator.
+ *
+ * The effective ADC conversion rate will be reduced by a factor of the number
+ * of accumulated samples;
+ * however the effective resolution will be increased according to
+ * \ref asfdoc_sam0_adc_module_hw_av_resolution "the table below".
+ *
+ * \anchor asfdoc_sam0_adc_module_hw_av_resolution
+ * <table>
+ * <caption>Effective ADC Resolution From Various Hardware Averaging Modes</caption>
+ * <tr>
+ * <th>Number of samples</tr>
+ * <th>Final result</tr>
+ * </tr>
+ * <tr>
+ * <td>1</td>
+ * <td>12-bit</td>
+ * </tr>
+ * <tr>
+ * <td>2</td>
+ * <td>13-bit</td>
+ * </tr>
+ * <tr>
+ * <td>4</td>
+ * <td>14-bit</td>
+ * </tr>
+ * <tr>
+ * <td>8</td>
+ * <td>15-bit</td>
+ * </tr>
+ * <tr>
+ * <td>16</td>
+ * <td>16-bit</td>
+ * </tr>
+ * <tr>
+ * <td>32</td>
+ * <td>16-bit</td>
+ * </tr>
+ * <tr>
+ * <td>64</td>
+ * <td>16-bit</td>
+ * </tr>
+ * <tr>
+ * <td>128</td>
+ * <td>16-bit</td>
+ * </tr>
+ * <tr>
+ * <td>256</td>
+ * <td>16-bit</td>
+ * </tr>
+ * <tr>
+ * <td>512</td>
+ * <td>16-bit</td>
+ * </tr>
+ * <tr>
+ * <td>1024</td>
+ * <td>16-bit</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_offset_corr Offset and Gain Correction
+ * Inherent gain and offset errors affect the absolute accuracy of the ADC.
+ *
+ * The offset error is defined as the deviation of the ADC鈥檚 actual transfer
+ * function from ideal straight line at zero input voltage.
+ *
+ * The gain error is defined as the deviation of the last output step's
+ * midpoint from the ideal straight line, after compensating for offset error.
+ *
+ * The offset correction value is subtracted from the converted data before the
+ * result is ready. The gain correction value is multiplied with the offset
+ * corrected value.
+ *
+ * The equation for both offset and gain error compensation is shown below:
+ * \f[
+ * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET}) \times CORR_{GAIN}
+ * \f]
+ *
+ * When enabled, a given set of offset and gain correction values can be applied
+ * to the sampled data in hardware, giving a corrected stream of sample data to
+ * the user application at the cost of an increased sample latency.
+ *
+ * In single conversion, a latency of 13 ADC Generic Clock cycles is added for
+ * the final sample result availability. As the correction time is always less
+ * than the propagation delay, in free running mode this latency appears only
+ * during the first conversion. After the first conversion is complete future
+ * conversion results are available at the defined sampling rate.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_pin_scan Pin Scan
+ * In pin scan mode, the first ADC conversion will begin from the configured
+ * positive channel, plus the requested starting offset. When the first
+ * conversion is completed, the next conversion will start at the next positive
+ * input channel and so on, until all requested pins to scan have been sampled
+ * and converted.
+ * SAM L21 has automatic sequences feature instead of pin scan mode. In automatic
+ * sequence mode, all of 32 positives inputs can be included in a sequence. The
+ * sequence starts from the lowest input, and go to the next enabled input
+ * automatically.
+ *
+ * Pin scanning gives a simple mechanism to sample a large number of physical
+ * input channel samples, using a single physical ADC channel.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_window_monitor Window Monitor
+ * The ADC module window monitor function can be used to automatically compare
+ * the conversion result against a preconfigured pair of upper and lower
+ * threshold values.
+ *
+ * The threshold values are evaluated differently, depending on whether
+ * differential or single-ended mode is selected. In differential mode, the
+ * upper and lower thresholds are evaluated as signed values for the comparison,
+ * while in single-ended mode the comparisons are made as a set of unsigned
+ * values.
+ *
+ * The significant bits of the lower window monitor threshold and upper window
+ * monitor threshold values are user-configurable, and follow the overall ADC
+ * sampling bit precision set when the ADC is configured by the user application.
+ * For example, only the eight lower bits of the window threshold values will be
+ * compares to the sampled data whilst the ADC is configured in 8-bit mode.
+ * In addition, if using differential mode, the 8<SUP>th</SUP> bit will be considered as
+ * the sign bit even if bit 9 is zero.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_events Events
+ * Event generation and event actions are configurable in the ADC.
+ *
+ * The ADC has two actions that can be triggered upon event reception:
+ * \li Start conversion
+ * \li Flush pipeline and start conversion
+ *
+ * The ADC can generate two events:
+ * \li Window monitor
+ * \li Result ready
+ *
+ * If the event actions are enabled in the configuration, any incoming event
+ * will trigger the action.
+ *
+ * If the window monitor event is enabled, an event will be generated
+ * when the configured window condition is detected.
+ *
+ * If the result ready event is enabled, an event will be generated when a
+ * conversion is completed.
+ *
+ * \note The connection of events between modules requires the use of the
+ * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ * to route output event of one module to the the input event of another.
+ * For more information on event routing, refer to the event driver
+ * documentation.
+ *
+ *
+ * \section asfdoc_sam0_adc_special_considerations Special Considerations
+ *
+ * An integrated analog temperature sensor is available for use with the ADC.
+ * The bandgap voltage, as well as the scaled I/O and core voltages can also be
+ * measured by the ADC. For internal ADC inputs, the internal source(s) may need
+ * to be manually enabled by the user application before they can be measured.
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_adc_extra. This includes:
+ * - \ref asfdoc_sam0_adc_extra_acronyms
+ * - \ref asfdoc_sam0_adc_extra_dependencies
+ * - \ref asfdoc_sam0_adc_extra_errata
+ * - \ref asfdoc_sam0_adc_extra_history
+ *
+ *
+ * \section asfdoc_sam0_adc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_adc_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_adc_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system.h>
+#include <adc_feature.h>
+
+/**
+ * \name Module Status Flags
+ *
+ * ADC status flags, returned by \ref adc_get_status() and cleared by
+ * \ref adc_clear_status().
+ *
+ * @{
+ */
+
+/** ADC result ready. */
+#define ADC_STATUS_RESULT_READY (1UL << 0)
+/** Window monitor match. */
+#define ADC_STATUS_WINDOW (1UL << 1)
+/** ADC result overwritten before read. */
+#define ADC_STATUS_OVERRUN (1UL << 2)
+
+/** @} */
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+enum status_code adc_init(
+ struct adc_module *const module_inst,
+ Adc *hw,
+ struct adc_config *config);
+
+void adc_get_config_defaults(
+ struct adc_config *const config);
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ *
+ * \return Bitmask of \c ADC_STATUS_* flags.
+ *
+ * \retval ADC_STATUS_RESULT_READY ADC Result is ready to be read
+ * \retval ADC_STATUS_WINDOW ADC has detected a value inside the set
+ * window range
+ * \retval ADC_STATUS_OVERRUN ADC result has overrun
+ */
+static inline uint32_t adc_get_status(
+ struct adc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ uint32_t int_flags = adc_module->INTFLAG.reg;
+
+ uint32_t status_flags = 0;
+
+ /* Check for ADC Result Ready */
+ if (int_flags & ADC_INTFLAG_RESRDY) {
+ status_flags |= ADC_STATUS_RESULT_READY;
+ }
+
+ /* Check for ADC Window Match */
+ if (int_flags & ADC_INTFLAG_WINMON) {
+ status_flags |= ADC_STATUS_WINDOW;
+ }
+
+ /* Check for ADC Overrun */
+ if (int_flags & ADC_INTFLAG_OVERRUN) {
+ status_flags |= ADC_STATUS_OVERRUN;
+ }
+
+ return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] status_flags Bitmask of \c ADC_STATUS_* flags to clear
+ */
+static inline void adc_clear_status(
+ struct adc_module *const module_inst,
+ const uint32_t status_flags)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ uint32_t int_flags = 0;
+
+ /* Check for ADC Result Ready */
+ if (status_flags & ADC_STATUS_RESULT_READY) {
+ int_flags |= ADC_INTFLAG_RESRDY;
+ }
+
+ /* Check for ADC Window Match */
+ if (status_flags & ADC_STATUS_WINDOW) {
+ int_flags |= ADC_INTFLAG_WINMON;
+ }
+
+ /* Check for ADC Overrun */
+ if (status_flags & ADC_STATUS_OVERRUN) {
+ int_flags |= ADC_INTFLAG_OVERRUN;
+ }
+
+ /* Clear interrupt flag */
+ adc_module->INTFLAG.reg = int_flags;
+}
+/** @} */
+
+/**
+ * \name Enable, Disable and Reset ADC Module, Start Conversion and Read Result
+ * @{
+ */
+
+/**
+ * \brief Enables the ADC module.
+ *
+ * Enables an ADC module that has previously been configured. If any internal reference
+ * is selected it will be enabled.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_enable(
+ struct adc_module *const module_inst)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+#if ADC_CALLBACK_MODE == true
+ system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
+#endif
+
+ adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables the ADC module.
+ *
+ * Disables an ADC module that was previously enabled.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_disable(
+ struct adc_module *const module_inst)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+#if ADC_CALLBACK_MODE == true
+ system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
+#endif
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Resets the ADC module.
+ *
+ * Resets an ADC module, clearing all module state and registers to their
+ * default values.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_reset(
+ struct adc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ /* Disable to make sure the pipeline is flushed before reset */
+ adc_disable(module_inst);
+
+ /* Software reset the module */
+ adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+ return STATUS_OK;
+}
+
+
+/**
+ * \brief Enables an ADC event input or output.
+ *
+ * Enables one or more input or output events to or from the ADC module. See
+ * \ref adc_events "here" for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in] module_inst Software instance for the ADC peripheral
+ * \param[in] events Struct containing flags of events to enable
+ */
+static inline void adc_enable_events(
+ struct adc_module *const module_inst,
+ struct adc_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(events);
+
+ Adc *const adc_module = module_inst->hw;
+
+ uint32_t event_mask = 0;
+
+ /* Configure Window Monitor event */
+ if (events->generate_event_on_window_monitor) {
+ event_mask |= ADC_EVCTRL_WINMONEO;
+ }
+
+ /* Configure Result Ready event */
+ if (events->generate_event_on_conversion_done) {
+ event_mask |= ADC_EVCTRL_RESRDYEO;
+ }
+
+ adc_module->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an ADC event input or output.
+ *
+ * Disables one or more input or output events to or from the ADC module. See
+ * \ref adc_events "here" for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in] module_inst Software instance for the ADC peripheral
+ * \param[in] events Struct containing flags of events to disable
+ */
+static inline void adc_disable_events(
+ struct adc_module *const module_inst,
+ struct adc_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(events);
+
+ Adc *const adc_module = module_inst->hw;
+
+ uint32_t event_mask = 0;
+
+ /* Configure Window Monitor event */
+ if (events->generate_event_on_window_monitor) {
+ event_mask |= ADC_EVCTRL_WINMONEO;
+ }
+
+ /* Configure Result Ready event */
+ if (events->generate_event_on_conversion_done) {
+ event_mask |= ADC_EVCTRL_RESRDYEO;
+ }
+
+ adc_module->EVCTRL.reg &= ~event_mask;
+}
+
+/**
+ * \brief Starts an ADC conversion.
+ *
+ * Starts a new ADC conversion.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline void adc_start_conversion(
+ struct adc_module *const module_inst)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+}
+
+/**
+ * \brief Reads the ADC result.
+ *
+ * Reads the result from an ADC conversion that was previously started.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[out] result Pointer to store the result value in
+ *
+ * \return Status of the ADC read request.
+ * \retval STATUS_OK The result was retrieved successfully
+ * \retval STATUS_BUSY A conversion result was not ready
+ * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the
+ * ADC module before the result was read by the software
+ */
+static inline enum status_code adc_read(
+ struct adc_module *const module_inst,
+ uint16_t *result)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(result);
+
+ if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) {
+ /* Result not ready */
+ return STATUS_BUSY;
+ }
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Get ADC result */
+ *result = adc_module->RESULT.reg;
+
+ /* Reset ready flag */
+ adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
+
+ if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) {
+ adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
+ return STATUS_ERR_OVERFLOW;
+ }
+
+ return STATUS_OK;
+}
+
+/** @} */
+
+/**
+ * \name Runtime Changes of ADC Module
+ * @{
+ */
+
+/**
+ * \brief Flushes the ADC pipeline.
+ *
+ * Flushes the pipeline and restart the ADC clock on the next peripheral clock
+ * edge. All conversions in progress will be lost. When flush is complete, the
+ * module will resume where it left off.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline void adc_flush(
+ struct adc_module *const module_inst)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+}
+void adc_set_window_mode(
+ struct adc_module *const module_inst,
+ const enum adc_window_mode window_mode,
+ const int16_t window_lower_value,
+ const int16_t window_upper_value);
+
+/**
+ * \brief Sets positive ADC input pin.
+ *
+ * Sets the positive ADC input pin selection.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] positive_input Positive input pin
+ */
+static inline void adc_set_positive_input(
+ struct adc_module *const module_inst,
+ const enum adc_positive_input positive_input)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set positive input pin */
+ adc_module->INPUTCTRL.reg =
+ (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
+ (positive_input);
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+}
+
+
+/**
+ * \brief Sets negative ADC input pin for differential mode.
+ *
+ * Sets the negative ADC input pin, when the ADC is configured in differential
+ * mode.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] negative_input Negative input pin
+ */
+static inline void adc_set_negative_input(
+ struct adc_module *const module_inst,
+ const enum adc_negative_input negative_input)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set negative input pin */
+ adc_module->INPUTCTRL.reg =
+ (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
+ (negative_input);
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+}
+
+/** @} */
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * \name Enable and Disable Interrupts
+ * @{
+ */
+
+/**
+ * \brief Enable interrupt.
+ *
+ * Enable the given interrupt request from the ADC module.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] interrupt Interrupt to enable
+ */
+static inline void adc_enable_interrupt(struct adc_module *const module_inst,
+ enum adc_interrupt_flag interrupt)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+ /* Enable interrupt */
+ adc_module->INTENSET.reg = interrupt;
+}
+
+/**
+ * \brief Disable interrupt.
+ *
+ * Disable the given interrupt request from the ADC module.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] interrupt Interrupt to disable
+ */
+static inline void adc_disable_interrupt(struct adc_module *const module_inst,
+ enum adc_interrupt_flag interrupt)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+ /* Enable interrupt */
+ adc_module->INTENCLR.reg = interrupt;
+}
+
+/** @} */
+#endif /* ADC_CALLBACK_MODE == true */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_adc_extra Extra Information for ADC Driver
+ *
+ * \section asfdoc_sam0_adc_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>ADC</td>
+ * <td>Analog-to-Digital Converter</td>
+ * </tr>
+ * <tr>
+ * <td>DAC</td>
+ * <td>Digital-to-Analog Converter</td>
+ * </tr>
+ * <tr>
+ * <td>LSB</td>
+ * <td>Least Significant Bit</td>
+ * </tr>
+ * <tr>
+ * <td>MSB</td>
+ * <td>Most Significant Bit</td>
+ * </tr>
+ * <tr>
+ * <td>DMA</td>
+ * <td>Direct Memory Access</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * \if DEVICE_SAML21_SUPPORT
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * \else
+ * <tr>
+ * <td>Added support for SAMR21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21 and new DMA quick start guide</td>
+ * </tr>
+ * <tr>
+ * <td>Added ADC calibration constant loading from the device signature
+ * row when the module is initialized</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * \endif
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_adc_exqsg Examples for ADC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_adc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_adc_basic_use_case
+ * \if ADC_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_adc_basic_use_case_callback
+ * \endif
+ * - \subpage asfdoc_sam0_adc_dma_use_case
+ *
+ * \page asfdoc_sam0_adc_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * \if DEVICE_SAML21_SUPPORT
+ * <tr>
+ * <td>A</td>
+ * <td>11/2014</td>
+ * <td>Initial release.</td>
+ * </tr>
+ * \else
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Added additional documentation on the event system. Corrected
+ * documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * \endif
+ * </table>
+ */
+
+#endif /* ADC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "adc.h"
+
+#if SAMD20
+/* The Die revision D number */
+#define REVISON_D_NUM 3
+#endif
+
+/**
+ * \brief Initializes an ADC configuration structure to defaults
+ *
+ * Initializes a given ADC configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ * \li GCLK generator 0 (GCLK main) clock source
+ * \li 1V from internal bandgap reference
+ * \li Div 4 clock prescaler
+ * \li 12 bit resolution
+ * \li Window monitor disabled
+ * \li No gain
+ * \li Positive input on ADC PIN 0
+ * \li Negative input on ADC PIN 1
+ * \li Averaging disabled
+ * \li Oversampling disabled
+ * \li Right adjust data
+ * \li Single-ended mode
+ * \li Free running disabled
+ * \li All events (input and generation) disabled
+ * \li Sleep operation disabled
+ * \li No reference compensation
+ * \li No gain/offset correction
+ * \li No added sampling time
+ * \li Pin scan mode disabled
+ *
+ * \param[out] config Pointer to configuration struct to initialize to
+ * default values
+ */
+void adc_get_config_defaults(struct adc_config *const config)
+{
+ Assert(config);
+ config->clock_source = GCLK_GENERATOR_0;
+ config->reference = ADC_REFERENCE_INT1V;
+ config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4;
+ config->resolution = ADC_RESOLUTION_12BIT;
+ config->window.window_mode = ADC_WINDOW_MODE_DISABLE;
+ config->window.window_upper_value = 0;
+ config->window.window_lower_value = 0;
+ config->gain_factor = ADC_GAIN_FACTOR_1X;
+#if SAMR21
+ config->positive_input = ADC_POSITIVE_INPUT_PIN6 ;
+#else
+ config->positive_input = ADC_POSITIVE_INPUT_PIN0 ;
+#endif
+ config->negative_input = ADC_NEGATIVE_INPUT_GND ;
+ config->accumulate_samples = ADC_ACCUMULATE_DISABLE;
+ config->divide_result = ADC_DIVIDE_RESULT_DISABLE;
+ config->left_adjust = false;
+ config->differential_mode = false;
+ config->freerunning = false;
+ config->event_action = ADC_EVENT_ACTION_DISABLED;
+ config->run_in_standby = false;
+ config->reference_compensation_enable = false;
+ config->correction.correction_enable = false;
+ config->correction.gain_correction = ADC_GAINCORR_RESETVALUE;
+ config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE;
+ config->sample_length = 0;
+ config->pin_scan.offset_start_scan = 0;
+ config->pin_scan.inputs_to_scan = 0;
+}
+
+/**
+ * \brief Sets the ADC window mode
+ *
+ * Sets the ADC window mode to a given mode and value range.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] window_mode Window monitor mode to set
+ * \param[in] window_lower_value Lower window monitor threshold value
+ * \param[in] window_upper_value Upper window monitor threshold value
+ */
+void adc_set_window_mode(
+ struct adc_module *const module_inst,
+ const enum adc_window_mode window_mode,
+ const int16_t window_lower_value,
+ const int16_t window_upper_value)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set window mode */
+ adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set lower window monitor threshold value */
+ adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set upper window monitor threshold value */
+ adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
+}
+
+/**
+* \internal Configure MUX settings for the analog pins
+*
+* This function will set the given ADC input pins
+* to the analog function in the pinmux, giving
+* the ADC access to the analog signal
+*
+* \param [in] pin AINxx pin to configure
+*/
+static inline void _adc_configure_ain_pin(uint32_t pin)
+{
+#define PIN_INVALID_ADC_AIN 0xFFFFUL
+
+ /* Pinmapping table for AINxx -> GPIO pin number */
+ const uint32_t pinmapping[] = {
+#if (SAMD20E | SAMD21E)
+ PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
+ PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+ PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif (SAMD20G | SAMD21G)
+ PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
+ PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
+ PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
+ PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+ PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif (SAMD20J | SAMD21J)
+ PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
+ PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
+ PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
+ PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
+ PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
+ PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+ PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+ PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+ PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+ PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif SAMR21E
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif SAMR21G
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
+ PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD10C | SAMD11C)
+ PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
+ PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD10DS | SAMD11DS)
+ PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
+ PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
+ PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
+ PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD10DM | SAMD11DM)
+ PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
+ PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
+ PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
+ PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
+ PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+ PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#else
+# error ADC pin mappings are not defined for this device.
+#endif
+ };
+
+ uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
+
+ if (pin <= ADC_EXTCHANNEL_MSB) {
+ pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+
+ Assert(pin_map_result != PIN_INVALID_ADC_AIN);
+
+ struct system_pinmux_config config;
+ system_pinmux_get_config_defaults(&config);
+
+ /* Analog functions are all on MUX setting B */
+ config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+ config.mux_position = 1;
+
+ system_pinmux_pin_set_config(pin_map_result, &config);
+ }
+}
+
+/**
+ * \internal Writes an ADC configuration to the hardware module
+ *
+ * Writes out a given ADC module configuration to the hardware module.
+ *
+ * \param[out] module_inst Pointer to the ADC software instance struct
+ * \param[in] config Pointer to configuration struct
+ *
+ * \return Status of the configuration procedure
+ * \retval STATUS_OK The configuration was successful
+ * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
+ */
+static enum status_code _adc_set_config(
+ struct adc_module *const module_inst,
+ struct adc_config *const config)
+{
+ uint8_t adjres = 0;
+ uint32_t resolution = ADC_RESOLUTION_16BIT;
+ enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+#if SAMD20
+ uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos);
+#endif
+
+ /* Get the hardware module pointer */
+ Adc *const adc_module = module_inst->hw;
+
+ /* Configure GCLK channel and enable clock */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = config->clock_source;
+ system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
+ system_gclk_chan_enable(ADC_GCLK_ID);
+
+ /* Setup pinmuxing for analog inputs */
+ if (config->pin_scan.inputs_to_scan != 0) {
+ uint8_t offset = config->pin_scan.offset_start_scan;
+ uint8_t start_pin =
+ offset +(uint8_t)config->positive_input;
+ uint8_t end_pin =
+ start_pin + config->pin_scan.inputs_to_scan;
+
+ while (start_pin < end_pin) {
+ _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
+ start_pin++;
+ offset++;
+ }
+ _adc_configure_ain_pin(config->negative_input);
+ } else {
+ _adc_configure_ain_pin(config->positive_input);
+ _adc_configure_ain_pin(config->negative_input);
+ }
+
+ /* Configure run in standby */
+ adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
+
+ /* Configure reference */
+ adc_module->REFCTRL.reg =
+ (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
+ (config->reference);
+
+ /* Set adjusting result and number of samples */
+ switch (config->resolution) {
+
+ case ADC_RESOLUTION_CUSTOM:
+ adjres = config->divide_result;
+ accumulate = config->accumulate_samples;
+ /* 16-bit result register */
+ resolution = ADC_RESOLUTION_16BIT;
+ break;
+
+ case ADC_RESOLUTION_13BIT:
+ /* Increase resolution by 1 bit */
+ adjres = ADC_DIVIDE_RESULT_2;
+ accumulate = ADC_ACCUMULATE_SAMPLES_4;
+ /* 16-bit result register */
+ resolution = ADC_RESOLUTION_16BIT;
+ break;
+
+ case ADC_RESOLUTION_14BIT:
+ /* Increase resolution by 2 bit */
+ adjres = ADC_DIVIDE_RESULT_4;
+ accumulate = ADC_ACCUMULATE_SAMPLES_16;
+ /* 16-bit result register */
+ resolution = ADC_RESOLUTION_16BIT;
+ break;
+#if SAMD20
+ /* See $35.1.8 for ADC errata of SAM D20.
+ The revisions before D have this issue.*/
+ case ADC_RESOLUTION_15BIT:
+ /* Increase resolution by 3 bit */
+ if(revision_num < REVISON_D_NUM) {
+ adjres = ADC_DIVIDE_RESULT_8;
+ } else {
+ adjres = ADC_DIVIDE_RESULT_2;
+ }
+ accumulate = ADC_ACCUMULATE_SAMPLES_64;
+ /* 16-bit result register */
+ resolution = ADC_RESOLUTION_16BIT;
+ break;
+
+ case ADC_RESOLUTION_16BIT:
+ if(revision_num < REVISON_D_NUM) {
+ /* Increase resolution by 4 bit */
+ adjres = ADC_DIVIDE_RESULT_16;
+ } else {
+ adjres = ADC_DIVIDE_RESULT_DISABLE;
+ }
+ accumulate = ADC_ACCUMULATE_SAMPLES_256;
+ /* 16-bit result register */
+ resolution = ADC_RESOLUTION_16BIT;
+ break;
+#else
+ case ADC_RESOLUTION_15BIT:
+ /* Increase resolution by 3 bit */
+ adjres = ADC_DIVIDE_RESULT_2;
+ accumulate = ADC_ACCUMULATE_SAMPLES_64;
+ /* 16-bit result register */
+ resolution = ADC_RESOLUTION_16BIT;
+ break;
+
+ case ADC_RESOLUTION_16BIT:
+ /* Increase resolution by 4 bit */
+ adjres = ADC_DIVIDE_RESULT_DISABLE;
+ accumulate = ADC_ACCUMULATE_SAMPLES_256;
+ /* 16-bit result register */
+ resolution = ADC_RESOLUTION_16BIT;
+ break;
+#endif
+ case ADC_RESOLUTION_8BIT:
+ /* 8-bit result register */
+ resolution = ADC_RESOLUTION_8BIT;
+ break;
+ case ADC_RESOLUTION_10BIT:
+ /* 10-bit result register */
+ resolution = ADC_RESOLUTION_10BIT;
+ break;
+ case ADC_RESOLUTION_12BIT:
+ /* 12-bit result register */
+ resolution = ADC_RESOLUTION_12BIT;
+ break;
+
+ default:
+ /* Unknown. Abort. */
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+
+ /* Check validity of sample length value */
+ if (config->sample_length > 63) {
+ return STATUS_ERR_INVALID_ARG;
+ } else {
+ /* Configure sample length */
+ adc_module->SAMPCTRL.reg =
+ (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
+ }
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Configure CTRLB */
+ adc_module->CTRLB.reg =
+ config->clock_prescaler |
+ resolution |
+ (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
+ (config->freerunning << ADC_CTRLB_FREERUN_Pos) |
+ (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
+ (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
+
+ /* Check validity of window thresholds */
+ if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
+ switch (resolution) {
+ case ADC_RESOLUTION_8BIT:
+ if (config->differential_mode &&
+ (config->window.window_lower_value > 127 ||
+ config->window.window_lower_value < -128 ||
+ config->window.window_upper_value > 127 ||
+ config->window.window_upper_value < -128)) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ } else if (config->window.window_lower_value > 255 ||
+ config->window.window_upper_value > 255) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ }
+ break;
+ case ADC_RESOLUTION_10BIT:
+ if (config->differential_mode &&
+ (config->window.window_lower_value > 511 ||
+ config->window.window_lower_value < -512 ||
+ config->window.window_upper_value > 511 ||
+ config->window.window_upper_value > -512)) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ } else if (config->window.window_lower_value > 1023 ||
+ config->window.window_upper_value > 1023) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ }
+ break;
+ case ADC_RESOLUTION_12BIT:
+ if (config->differential_mode &&
+ (config->window.window_lower_value > 2047 ||
+ config->window.window_lower_value < -2048 ||
+ config->window.window_upper_value > 2047 ||
+ config->window.window_upper_value < -2048)) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ } else if (config->window.window_lower_value > 4095 ||
+ config->window.window_upper_value > 4095) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ }
+ break;
+ case ADC_RESOLUTION_16BIT:
+ if (config->differential_mode &&
+ (config->window.window_lower_value > 32767 ||
+ config->window.window_lower_value < -32768 ||
+ config->window.window_upper_value > 32767 ||
+ config->window.window_upper_value < -32768)) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ } else if (config->window.window_lower_value > 65535 ||
+ config->window.window_upper_value > 65535) {
+ /* Invalid value */
+ return STATUS_ERR_INVALID_ARG;
+ }
+ break;
+ }
+ }
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Configure window mode */
+ adc_module->WINCTRL.reg = config->window.window_mode;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Configure lower threshold */
+ adc_module->WINLT.reg =
+ config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Configure lower threshold */
+ adc_module->WINUT.reg = config->window.window_upper_value <<
+ ADC_WINUT_WINUT_Pos;
+
+ uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
+ if (inputs_to_scan > 0) {
+ /*
+ * Number of input sources included is the value written to INPUTSCAN
+ * plus 1.
+ */
+ inputs_to_scan--;
+ }
+
+ if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+ config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
+ /* Invalid number of input pins or input offset */
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Configure pin scan mode and positive and negative input pins */
+ adc_module->INPUTCTRL.reg =
+ config->gain_factor |
+ (config->pin_scan.offset_start_scan <<
+ ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+ (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
+ config->negative_input |
+ config->positive_input;
+
+ /* Configure events */
+ adc_module->EVCTRL.reg = config->event_action;
+
+ /* Disable all interrupts */
+ adc_module->INTENCLR.reg =
+ (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
+ (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
+
+ if (config->correction.correction_enable) {
+ /* Make sure gain_correction value is valid */
+ if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
+ return STATUS_ERR_INVALID_ARG;
+ } else {
+ /* Set gain correction value */
+ adc_module->GAINCORR.reg = config->correction.gain_correction <<
+ ADC_GAINCORR_GAINCORR_Pos;
+ }
+
+ /* Make sure offset correction value is valid */
+ if (config->correction.offset_correction > 2047 ||
+ config->correction.offset_correction < -2048) {
+ return STATUS_ERR_INVALID_ARG;
+ } else {
+ /* Set offset correction value */
+ adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+ ADC_OFFSETCORR_OFFSETCORR_Pos;
+ }
+ }
+
+ /* Load in the fixed device ADC calibration constants */
+ adc_module->CALIB.reg =
+ ADC_CALIB_BIAS_CAL(
+ (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
+ ) |
+ ADC_CALIB_LINEARITY_CAL(
+ (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
+ );
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the ADC
+ *
+ * Initializes the ADC device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[out] module_inst Pointer to the ADC software instance struct
+ * \param[in] hw Pointer to the ADC module instance
+ * \param[in] config Pointer to the configuration struct
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK The initialization was successful
+ * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
+ * \retval STATUS_BUSY The module is busy with a reset operation
+ * \retval STATUS_ERR_DENIED The module is enabled
+ */
+enum status_code adc_init(
+ struct adc_module *const module_inst,
+ Adc *hw,
+ struct adc_config *config)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(hw);
+ Assert(config);
+
+ /* Associate the software module instance with the hardware module */
+ module_inst->hw = hw;
+
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
+
+ if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
+ /* We are in the middle of a reset. Abort. */
+ return STATUS_BUSY;
+ }
+
+ if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
+ /* Module must be disabled before initialization. Abort. */
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Store the selected reference for later use */
+ module_inst->reference = config->reference;
+
+ /* Make sure bandgap is enabled if requested by the config */
+ if (module_inst->reference == ADC_REFERENCE_INT1V) {
+ system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
+ }
+
+#if ADC_CALLBACK_MODE == true
+ for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
+ module_inst->callback[i] = NULL;
+ };
+
+ module_inst->registered_callback_mask = 0;
+ module_inst->enabled_callback_mask = 0;
+ module_inst->remaining_conversions = 0;
+ module_inst->job_status = STATUS_OK;
+
+ _adc_instances[0] = module_inst;
+
+ if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
+ !config->freerunning) {
+ module_inst->software_trigger = true;
+ } else {
+ module_inst->software_trigger = false;
+ }
+#endif
+
+ /* Write configuration to module */
+ return _adc_set_config(module_inst, config);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc_feature.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,725 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC functionality
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef ADC_FEATURE_H_INCLUDED
+#define ADC_FEATURE_H_INCLUDED
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if ADC_CALLBACK_MODE == true
+# include <system_interrupt.h>
+
+#if !defined(__DOXYGEN__)
+extern struct adc_module *_adc_instances[ADC_INST_NUM];
+#endif
+
+/** Forward definition of the device instance. */
+struct adc_module;
+
+/** Type of the callback functions. */
+typedef void (*adc_callback_t)(const struct adc_module *const module);
+
+/**
+ * \brief ADC Callback enum
+ *
+ * Callback types for ADC callback driver.
+ *
+ */
+enum adc_callback {
+ /** Callback for buffer received. */
+ ADC_CALLBACK_READ_BUFFER,
+ /** Callback when window is hit. */
+ ADC_CALLBACK_WINDOW,
+ /** Callback for error. */
+ ADC_CALLBACK_ERROR,
+# if !defined(__DOXYGEN__)
+ /** Number of available callbacks. */
+ ADC_CALLBACK_N,
+# endif
+};
+
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_adc_group
+ * @{
+ */
+
+/**
+ * \brief ADC reference voltage enum
+ *
+ * Enum for the possible reference voltages for the ADC.
+ *
+ */
+enum adc_reference {
+ /** 1.0V voltage reference. */
+ ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V,
+ /** 1/1.48V<SUB>CC</SUB> reference. */
+ ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
+ /** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V). */
+ ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
+ /** External reference A. */
+ ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA,
+ /** External reference B. */
+ ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB,
+};
+
+/**
+ * \brief ADC clock prescaler enum
+ *
+ * Enum for the possible clock prescaler values for the ADC.
+ *
+ */
+enum adc_clock_prescaler {
+ /** ADC clock division factor 4. */
+ ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4,
+ /** ADC clock division factor 8. */
+ ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8,
+ /** ADC clock division factor 16. */
+ ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16,
+ /** ADC clock division factor 32. */
+ ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32,
+ /** ADC clock division factor 64. */
+ ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64,
+ /** ADC clock division factor 128. */
+ ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
+ /** ADC clock division factor 256. */
+ ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
+ /** ADC clock division factor 512. */
+ ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
+};
+
+/**
+ * \brief ADC resolution enum
+ *
+ * Enum for the possible resolution values for the ADC.
+ *
+ */
+enum adc_resolution {
+ /** ADC 12-bit resolution. */
+ ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
+ /** ADC 16-bit resolution using oversampling and decimation. */
+ ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
+ /** ADC 10-bit resolution. */
+ ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
+ /** ADC 8-bit resolution. */
+ ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT,
+ /** ADC 13-bit resolution using oversampling and decimation. */
+ ADC_RESOLUTION_13BIT,
+ /** ADC 14-bit resolution using oversampling and decimation. */
+ ADC_RESOLUTION_14BIT,
+ /** ADC 15-bit resolution using oversampling and decimation. */
+ ADC_RESOLUTION_15BIT,
+ /** ADC 16-bit result register for use with averaging. When using this mode
+ * the ADC result register will be set to 16-bit wide, and the number of
+ * samples to accumulate and the division factor is configured by the
+ * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
+ * members in the configuration struct.
+ */
+ ADC_RESOLUTION_CUSTOM,
+};
+
+/**
+ * \brief ADC window monitor mode enum
+ *
+ * Enum for the possible window monitor modes for the ADC.
+ *
+ */
+enum adc_window_mode {
+ /** No window mode. */
+ ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE,
+ /** RESULT > WINLT. */
+ ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1,
+ /** RESULT < WINUT. */
+ ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2,
+ /** WINLT < RESULT < WINUT. */
+ ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3,
+ /** !(WINLT < RESULT < WINUT). */
+ ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
+};
+
+/**
+ * \brief ADC gain factor selection enum
+ *
+ * Enum for the possible gain factor values for the ADC.
+ *
+ */
+enum adc_gain_factor {
+ /** 1x gain. */
+ ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X,
+ /** 2x gain. */
+ ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X,
+ /** 4x gain. */
+ ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X,
+ /** 8x gain. */
+ ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X,
+ /** 16x gain. */
+ ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X,
+ /** 1/2x gain. */
+ ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
+};
+
+/**
+ * \brief ADC event action enum
+ *
+ * Enum for the possible actions to take on an incoming event.
+ *
+ */
+enum adc_event_action {
+ /** Event action disabled. */
+ ADC_EVENT_ACTION_DISABLED = 0,
+ /** Flush ADC and start conversion. */
+ ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
+ /** Start conversion. */
+ ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI,
+};
+
+/**
+ * \brief ADC positive MUX input selection enum
+ *
+ * Enum for the possible positive MUX input selections for the ADC.
+ *
+ */
+enum adc_positive_input {
+ /** ADC0 pin. */
+ ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0,
+ /** ADC1 pin. */
+ ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1,
+ /** ADC2 pin. */
+ ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2,
+ /** ADC3 pin. */
+ ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3,
+ /** ADC4 pin. */
+ ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4,
+ /** ADC5 pin. */
+ ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5,
+ /** ADC6 pin. */
+ ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6,
+ /** ADC7 pin. */
+ ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7,
+ /** ADC8 pin. */
+ ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8,
+ /** ADC9 pin. */
+ ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9,
+ /** ADC10 pin. */
+ ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10,
+ /** ADC11 pin. */
+ ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11,
+ /** ADC12 pin. */
+ ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12,
+ /** ADC13 pin. */
+ ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13,
+ /** ADC14 pin. */
+ ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14,
+ /** ADC15 pin. */
+ ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15,
+ /** ADC16 pin. */
+ ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16,
+ /** ADC17 pin. */
+ ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17,
+ /** ADC18 pin. */
+ ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18,
+ /** ADC19 pin. */
+ ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19,
+ /** Temperature reference. */
+ ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP,
+ /** Bandgap voltage. */
+ ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP,
+ /** 1/4 scaled core supply. */
+ ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
+ /** 1/4 scaled I/O supply. */
+ ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
+ /** DAC input. */
+ ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC,
+};
+
+/**
+ * \brief ADC negative MUX input selection enum
+ *
+ * Enum for the possible negative MUX input selections for the ADC.
+ *
+ */
+enum adc_negative_input {
+ /** ADC0 pin. */
+ ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0,
+ /** ADC1 pin. */
+ ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1,
+ /** ADC2 pin. */
+ ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2,
+ /** ADC3 pin. */
+ ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3,
+ /** ADC4 pin. */
+ ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4,
+ /** ADC5 pin. */
+ ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5,
+ /** ADC6 pin. */
+ ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6,
+ /** ADC7 pin. */
+ ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7,
+ /** Internal ground. */
+ ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND,
+ /** I/O ground. */
+ ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND,
+};
+
+/**
+ * \brief ADC number of accumulated samples enum
+ *
+ * Enum for the possible numbers of ADC samples to accumulate.
+ * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
+ * resolution setting is used.
+ *
+ */
+enum adc_accumulate_samples {
+ /** No averaging. */
+ ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1,
+ /** Average 2 samples. */
+ ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2,
+ /** Average 4 samples. */
+ ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4,
+ /** Average 8 samples. */
+ ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8,
+ /** Average 16 samples. */
+ ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16,
+ /** Average 32 samples. */
+ ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32,
+ /** Average 64 samples. */
+ ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64,
+ /** Average 128 samples. */
+ ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128,
+ /** Average 265 samples. */
+ ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256,
+ /** Average 512 samples. */
+ ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512,
+ /** Average 1024 samples. */
+ ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
+};
+
+/**
+ * \brief ADC possible dividers for the result register
+ *
+ * Enum for the possible division factors to use when accumulating
+ * multiple samples. To keep the same resolution for the averaged
+ * result and the actual input value, the division factor must
+ * be equal to the number of samples accumulated. This setting is only
+ * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
+ */
+enum adc_divide_result {
+ /** Don't divide result register after accumulation. */
+ ADC_DIVIDE_RESULT_DISABLE = 0,
+ /** Divide result register by 2 after accumulation. */
+ ADC_DIVIDE_RESULT_2 = 1,
+ /** Divide result register by 4 after accumulation. */
+ ADC_DIVIDE_RESULT_4 = 2,
+ /** Divide result register by 8 after accumulation. */
+ ADC_DIVIDE_RESULT_8 = 3,
+ /** Divide result register by 16 after accumulation. */
+ ADC_DIVIDE_RESULT_16 = 4,
+ /** Divide result register by 32 after accumulation. */
+ ADC_DIVIDE_RESULT_32 = 5,
+ /** Divide result register by 64 after accumulation. */
+ ADC_DIVIDE_RESULT_64 = 6,
+ /** Divide result register by 128 after accumulation. */
+ ADC_DIVIDE_RESULT_128 = 7,
+};
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * Enum for the possible ADC interrupt flags.
+ */
+enum adc_interrupt_flag {
+ /** ADC result ready. */
+ ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
+ /** Window monitor match. */
+ ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON,
+ /** ADC result overwritten before read. */
+ ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN,
+};
+#endif
+
+/**
+ * \brief ADC oversampling and decimation enum
+ *
+ * Enum for the possible numbers of bits resolution can be increased by when
+ * using oversampling and decimation.
+ *
+ */
+enum adc_oversampling_and_decimation {
+ /** Don't use oversampling and decimation mode. */
+ ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
+ /** 1 bit resolution increase. */
+ ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
+ /** 2 bits resolution increase. */
+ ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
+ /** 3 bits resolution increase. */
+ ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
+ /** 4 bits resolution increase. */
+ ADC_OVERSAMPLING_AND_DECIMATION_4BIT
+};
+
+/**
+ * \brief Window monitor configuration structure
+ *
+ * Window monitor configuration structure.
+ */
+struct adc_window_config {
+ /** Selected window mode. */
+ enum adc_window_mode window_mode;
+ /** Lower window value. */
+ int32_t window_lower_value;
+ /** Upper window value. */
+ int32_t window_upper_value;
+};
+
+/**
+ * \brief ADC event enable/disable structure.
+ *
+ * Event flags for the ADC module. This is used to enable and
+ * disable events via \ref adc_enable_events() and \ref adc_disable_events().
+ */
+struct adc_events {
+ /** Enable event generation on conversion done. */
+ bool generate_event_on_conversion_done;
+ /** Enable event generation on window monitor. */
+ bool generate_event_on_window_monitor;
+};
+
+/**
+ * \brief Gain and offset correction configuration structure
+ *
+ * Gain and offset correction configuration structure.
+ * Part of the \ref adc_config struct and will be initialized by
+ * \ref adc_get_config_defaults.
+ */
+struct adc_correction_config {
+ /**
+ * Enables correction for gain and offset based on values of gain_correction and
+ * offset_correction if set to true.
+ */
+ bool correction_enable;
+ /**
+ * This value defines how the ADC conversion result is compensated for gain
+ * error before written to the result register. This is a fractional value,
+ * 1-bit integer plus an 11-bit fraction, therefore
+ * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
+ * \c 0b010000000000 to \c 0b111111111111.
+ */
+ uint16_t gain_correction;
+ /**
+ * This value defines how the ADC conversion result is compensated for
+ * offset error before written to the result register. This is a 12-bit
+ * value in two鈥檚 complement format.
+ */
+ int16_t offset_correction;
+};
+
+/**
+ * \brief Pin scan configuration structure
+ *
+ * Pin scan configuration structure. Part of the \ref adc_config struct and will
+ * be initialized by \ref adc_get_config_defaults.
+ */
+struct adc_pin_scan_config {
+ /**
+ * Offset (relative to selected positive input) of the first input pin to be
+ * used in pin scan mode.
+ */
+ uint8_t offset_start_scan;
+ /**
+ * Number of input pins to scan in pin scan mode. A value below two will
+ * disable pin scan mode.
+ */
+ uint8_t inputs_to_scan;
+};
+
+/**
+ * \brief ADC configuration structure
+ *
+ * Configuration structure for an ADC instance. This structure should be
+ * initialized by the \ref adc_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct adc_config {
+ /** GCLK generator used to clock the peripheral. */
+ enum gclk_generator clock_source;
+ /** Voltage reference. */
+ enum adc_reference reference;
+ /** Clock prescaler. */
+ enum adc_clock_prescaler clock_prescaler;
+ /** Result resolution. */
+ enum adc_resolution resolution;
+ /** Gain factor. */
+ enum adc_gain_factor gain_factor;
+ /** Positive MUX input. */
+ enum adc_positive_input positive_input;
+ /** Negative MUX input. */
+ enum adc_negative_input negative_input;
+ /** Number of ADC samples to accumulate when using the
+ * \c ADC_RESOLUTION_CUSTOM mode.
+ */
+ enum adc_accumulate_samples accumulate_samples;
+ /** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */
+ enum adc_divide_result divide_result;
+ /** Left adjusted result. */
+ bool left_adjust;
+ /** Enables differential mode if true. */
+ bool differential_mode;
+ /** Enables free running mode if true. */
+ bool freerunning;
+ /** Enables ADC in standby sleep mode if true. */
+ bool run_in_standby;
+ /**
+ * Enables reference buffer offset compensation if true.
+ * This will increase the accuracy of the gain stage, but decreases the input
+ * impedance; therefore the startup time of the reference must be increased.
+ */
+ bool reference_compensation_enable;
+ /**
+ * This value (0-63) control the ADC sampling time in number of half ADC
+ * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
+ * controlling the ADC input impedance. Sampling time is set according to
+ * the formula:
+ * Sample time = (sample_length+1) * (ADCclk / 2)
+ */
+ uint8_t sample_length;
+ /** Window monitor configuration structure. */
+ struct adc_window_config window;
+ /** Gain and offset correction configuration structure. */
+ struct adc_correction_config correction;
+ /** Event action to take on incoming event. */
+ enum adc_event_action event_action;
+ /** Pin scan configuration structure. */
+ struct adc_pin_scan_config pin_scan;
+};
+
+/**
+ * \brief ADC software device instance structure.
+ *
+ * ADC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ * application; they are reserved for module-internal use only.
+ */
+struct adc_module {
+#if !defined(__DOXYGEN__)
+ /** Pointer to ADC hardware module. */
+ Adc *hw;
+ /** Keep reference configuration so we know when enable is called. */
+ enum adc_reference reference;
+# if ADC_CALLBACK_MODE == true
+ /** Array to store callback functions. */
+ adc_callback_t callback[ADC_CALLBACK_N];
+ /** Pointer to buffer used for ADC results. */
+ volatile uint16_t *job_buffer;
+ /** Remaining number of conversions in current job. */
+ volatile uint16_t remaining_conversions;
+ /** Bit mask for callbacks registered. */
+ uint8_t registered_callback_mask;
+ /** Bit mask for callbacks enabled. */
+ uint8_t enabled_callback_mask;
+ /** Holds the status of the ongoing or last conversion job. */
+ volatile enum status_code job_status;
+ /** If software triggering is needed. */
+ bool software_trigger;
+# endif
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static inline bool adc_is_syncing(
+ struct adc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+
+ Adc *const adc_module = module_inst->hw;
+
+ if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+ return true;
+ }
+
+ return false;
+}
+#endif
+
+/**
+ * \name ADC Gain and Pin Scan Mode
+ * @{
+ */
+
+/**
+ * \brief Sets ADC gain factor
+ *
+ * Sets the ADC gain factor to a specified gain setting.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] gain_factor Gain factor value to set
+ */
+static inline void adc_set_gain(
+ struct adc_module *const module_inst,
+ const enum adc_gain_factor gain_factor)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set new gain factor */
+ adc_module->INPUTCTRL.reg =
+ (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
+ (gain_factor);
+}
+
+/**
+ * \brief Sets the ADC pin scan mode
+ *
+ * Configures the pin scan mode of the ADC module. In pin scan mode, the first
+ * conversion will start at the configured positive input + start_offset. When
+ * a conversion is done, a conversion will start on the next input, until
+ * \c inputs_to_scan number of conversions are made.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] inputs_to_scan Number of input pins to perform a conversion on
+ * (must be two or more)
+ * \param[in] start_offset Offset of first pin to scan (relative to
+ * configured positive input)
+ *
+ * \return Status of the pin scan configuration set request.
+ *
+ * \retval STATUS_OK Pin scan mode has been set successfully
+ * \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has
+ * an invalid value
+ */
+static inline enum status_code adc_set_pin_scan_mode(
+ struct adc_module *const module_inst,
+ uint8_t inputs_to_scan,
+ const uint8_t start_offset)
+
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ Adc *const adc_module = module_inst->hw;
+
+ if (inputs_to_scan > 0) {
+ /*
+ * Number of input sources included is the value written to INPUTSCAN
+ * plus 1.
+ */
+ inputs_to_scan--;
+ }
+
+ if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+ start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
+ /* Invalid number of input pins */
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ while (adc_is_syncing(module_inst)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set pin scan mode */
+ adc_module->INPUTCTRL.reg =
+ (adc_module->INPUTCTRL.reg &
+ ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
+ (start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+ (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables pin scan mode
+ *
+ * Disables pin scan mode. The next conversion will be made on only one pin
+ * (the configured positive input pin).
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline void adc_disable_pin_scan_mode(
+ struct adc_module *const module_inst)
+{
+ /* Disable pin scan mode */
+ adc_set_pin_scan_mode(module_inst, 0, 0);
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ADC_FEATURE_H_INCLUDED */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,653 @@
+/*
+ * \file
+ *
+ * \brief SAM Direct Memory Access Controller Driver
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include <string.h>
+#include "dma.h"
+#include "clock.h"
+#include "system_interrupt.h"
+
+struct _dma_module {
+ volatile bool _dma_init;
+ volatile uint32_t allocated_channels;
+ uint8_t free_channels;
+};
+
+struct _dma_module _dma_inst = {
+ ._dma_init = false,
+ .allocated_channels = 0,
+ .free_channels = CONF_MAX_USED_CHANNEL_NUM,
+};
+
+/** Maximum retry counter for resuming a job transfer. */
+#define MAX_JOB_RESUME_COUNT 10000
+
+/** DMA channel mask. */
+#define DMA_CHANNEL_MASK (0x1f)
+
+COMPILER_ALIGNED(16)
+DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/** Initial write back memory section. */
+COMPILER_ALIGNED(16)
+static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/** Internal DMA resource pool. */
+static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
+
+/**
+ * \brief Find a free channel for a DMA resource.
+ *
+ * Find a channel for the requested DMA resource.
+ *
+ * \return Status of channel allocation.
+ * \retval DMA_INVALID_CHANNEL No channel available
+ * \retval count Allocated channel for the DMA resource
+ */
+static uint8_t _dma_find_first_free_channel_and_allocate(void)
+{
+ uint8_t count;
+ uint32_t tmp;
+ bool allocated = false;
+
+ system_interrupt_enter_critical_section();
+
+ tmp = _dma_inst.allocated_channels;
+
+ for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
+ if (!(tmp & 0x00000001)) {
+ /* If free channel found, set as allocated and return
+ *number */
+
+ _dma_inst.allocated_channels |= 1 << count;
+ _dma_inst.free_channels--;
+ allocated = true;
+
+ break;
+ }
+
+ tmp = tmp >> 1;
+ }
+
+ system_interrupt_leave_critical_section();
+
+ if (!allocated) {
+ return DMA_INVALID_CHANNEL;
+ } else {
+ return count;
+ }
+}
+
+/**
+ * \brief Release an allocated DMA channel.
+ *
+ * \param[in] channel Channel id to be released
+ *
+ */
+static void _dma_release_channel(uint8_t channel)
+{
+ _dma_inst.allocated_channels &= ~(1 << channel);
+ _dma_inst.free_channels++;
+}
+
+/**
+ * \brief Configure the DMA resource.
+ *
+ * \param[in] dma_resource Pointer to a DMA resource instance
+ * \param[out] resource_config Configurations of the DMA resource
+ *
+ */
+static void _dma_set_config(struct dma_resource *resource,
+ struct dma_resource_config *resource_config)
+{
+ Assert(resource);
+ Assert(resource_config);
+ uint32_t temp_CHCTRLB_reg;
+ system_interrupt_enter_critical_section();
+
+ /** Select the DMA channel and clear software trigger */
+ DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+ DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
+
+ temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
+ DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
+ DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
+
+
+ if(resource_config->event_config.input_action) {
+ temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
+ resource_config->event_config.input_action);
+ }
+
+ /** Enable event output, the event output selection is configured in
+ * each transfer descriptor */
+ if (resource_config->event_config.event_output_enable) {
+ temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
+ }
+
+ /* Write config to CTRLB register */
+ DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
+
+
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief DMA interrupt service routine.
+ *
+ */
+void DMAC_Handler( void )
+{
+ uint8_t active_channel;
+ struct dma_resource *resource;
+ uint8_t isr;
+ uint32_t write_size;
+ uint32_t total_size;
+
+ system_interrupt_enter_critical_section();
+
+ /* Get Pending channel */
+ active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
+
+ Assert(_dma_active_resource[active_channel]);
+
+ /* Get active DMA resource based on channel */
+ resource = _dma_active_resource[active_channel];
+
+ /* Select the active channel */
+ DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+ isr = DMAC->CHINTFLAG.reg;
+
+ /* Calculate block transfer size of the DMA transfer */
+ total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+ write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+ resource->transfered_size = total_size - write_size;
+
+ /* DMA channel interrupt handler */
+ if (isr & DMAC_CHINTENCLR_TERR) {
+ /* Clear transfer error flag */
+ DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
+
+ /* Set I/O ERROR status */
+ resource->job_status = STATUS_ERR_IO;
+
+ /* Execute the callback function */
+ if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
+ (resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
+ resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
+ }
+ } else if (isr & DMAC_CHINTENCLR_TCMPL) {
+ /* Clear the transfer complete flag */
+ DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
+
+ /* Set job status */
+ resource->job_status = STATUS_OK;
+
+ /* Execute the callback function */
+ if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
+ (resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
+ resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
+ }
+ } else if (isr & DMAC_CHINTENCLR_SUSP) {
+ /* Clear channel suspend flag */
+ DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
+
+ /* Set job status */
+ resource->job_status = STATUS_SUSPEND;
+
+ /* Execute the callback function */
+ if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
+ (resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])) {
+ resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
+ }
+ }
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given DMA configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ * \li Software trigger is used as the transfer trigger
+ * \li Priority level 0
+ * \li Only software/event trigger
+ * \li Requires a trigger for each transaction
+ * \li No event input /output
+ * \li DMA channel is disabled during sleep mode (if has the feature)
+ * \param[out] config Pointer to the configuration
+ *
+ */
+void dma_get_config_defaults(struct dma_resource_config *config)
+{
+ Assert(config);
+ /* Set as priority 0 */
+ config->priority = DMA_PRIORITY_LEVEL_0;
+ /* Only software/event trigger */
+ config->peripheral_trigger = 0;
+ /* Transaction trigger */
+ config->trigger_action = DMA_TRIGGER_ACTON_TRANSACTION;
+
+ /* Event configurations, no event input/output */
+ config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
+ config->event_config.event_output_enable = false;
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+ config->run_in_standby = false;
+#endif
+}
+
+/**
+ * \brief Allocate a DMA with configurations.
+ *
+ * This function will allocate a proper channel for a DMA transfer request.
+ *
+ * \param[in,out] dma_resource Pointer to a DMA resource instance
+ * \param[in] transfer_config Configurations of the DMA transfer
+ *
+ * \return Status of the allocation procedure.
+ *
+ * \retval STATUS_OK The DMA resource was allocated successfully
+ * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
+ */
+enum status_code dma_allocate(struct dma_resource *resource,
+ struct dma_resource_config *config)
+{
+ uint8_t new_channel;
+
+ Assert(resource);
+
+ system_interrupt_enter_critical_section();
+
+ if (!_dma_inst._dma_init) {
+ /* Initialize clocks for DMA */
+#if (SAML21)
+ system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
+#else
+ system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
+ PM_APBBMASK_DMAC);
+#endif
+
+ /* Perform a software reset before enable DMA controller */
+ DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+ DMAC->CTRL.reg = DMAC_CTRL_SWRST;
+
+ /* Setup descriptor base address and write back section base
+ * address */
+ DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
+ DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
+
+ /* Enable all priority level at the same time */
+ DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
+
+ _dma_inst._dma_init = true;
+ }
+
+ /* Find the proper channel */
+ new_channel = _dma_find_first_free_channel_and_allocate();
+
+ /* If no channel available, return not found */
+ if (new_channel == DMA_INVALID_CHANNEL) {
+ system_interrupt_leave_critical_section();
+
+ return STATUS_ERR_NOT_FOUND;
+ }
+
+ /* Set the channel */
+ resource->channel_id = new_channel;
+
+ /** Perform a reset for the allocated channel */
+ DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+ DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+ DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+ if(config->run_in_standby) {
+ DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+ }
+#endif
+
+ /** Configure the DMA control,channel registers and descriptors here */
+ _dma_set_config(resource, config);
+
+ resource->descriptor = NULL;
+
+ /* Log the DMA resource into the internal DMA resource pool */
+ _dma_active_resource[resource->channel_id] = resource;
+
+ system_interrupt_leave_critical_section();
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Free an allocated DMA resource.
+ *
+ * This function will free an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the free procedure.
+ *
+ * \retval STATUS_OK The DMA resource was freed successfully
+ * \retval STATUS_BUSY The DMA resource was busy and can't be freed
+ * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized
+ */
+enum status_code dma_free(struct dma_resource *resource)
+{
+ Assert(resource);
+ Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+ system_interrupt_enter_critical_section();
+
+ /* Check if channel is busy */
+ if (dma_is_busy(resource)) {
+ system_interrupt_leave_critical_section();
+ return STATUS_BUSY;
+ }
+
+ /* Check if DMA resource was not allocated */
+ if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
+ system_interrupt_leave_critical_section();
+ return STATUS_ERR_NOT_INITIALIZED;
+ }
+
+ /* Release the DMA resource */
+ _dma_release_channel(resource->channel_id);
+
+ /* Reset the item in the DMA resource pool */
+ _dma_active_resource[resource->channel_id] = NULL;
+
+ system_interrupt_leave_critical_section();
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Start a DMA transfer.
+ *
+ * This function will start a DMA transfer through an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the transfer start procedure.
+ *
+ * \retval STATUS_OK The transfer was started successfully
+ * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
+ * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
+ */
+enum status_code dma_start_transfer_job(struct dma_resource *resource)
+{
+ Assert(resource);
+ Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+ system_interrupt_enter_critical_section();
+
+ /* Check if resource was busy */
+ if (resource->job_status == STATUS_BUSY) {
+ system_interrupt_leave_critical_section();
+ return STATUS_BUSY;
+ }
+
+ /* Check if transfer size is valid */
+ if (resource->descriptor->BTCNT.reg == 0) {
+ system_interrupt_leave_critical_section();
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Enable DMA interrupt */
+ system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
+
+ /* Set the interrupt flag */
+ DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+ DMAC->CHINTENSET.reg = DMAC_CHINTENSET_TERR |
+ DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_SUSP;
+
+ /* Set job status */
+ resource->job_status = STATUS_BUSY;
+
+ /* Set channel x descriptor 0 to the descriptor base address */
+ memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
+ sizeof(DmacDescriptor));
+
+ /* Enable the transfer channel */
+ DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+
+ system_interrupt_leave_critical_section();
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Abort a DMA transfer.
+ *
+ * This function will abort a DMA transfer. The DMA channel used for the DMA
+ * resource will be disabled.
+ * The block transfer count will be also calculated and written to the DMA
+ * resource structure.
+ *
+ * \note The DMA resource will not be freed after calling this function.
+ * The function \ref dma_free() can be used to free an allocated resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ */
+void dma_abort_job(struct dma_resource *resource)
+{
+ uint32_t write_size;
+ uint32_t total_size;
+
+ Assert(resource);
+ Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+ system_interrupt_enter_critical_section();
+
+ DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+ DMAC->CHCTRLA.reg = 0;
+
+ system_interrupt_leave_critical_section();
+
+ /* Get transferred size */
+ total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+ write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+ resource->transfered_size = total_size - write_size;
+
+ resource->job_status = STATUS_ABORTED;
+}
+
+/**
+ * \brief Suspend a DMA transfer.
+ *
+ * This function will request to suspend the transfer of the DMA resource.
+ * The channel is kept enabled, can receive transfer triggers (the transfer
+ * pending bit will be set), but will be removed from the arbitration scheme.
+ * The channel operation can be resumed by calling \ref dma_resume_job().
+ *
+ * \note This function sets the command to suspend the DMA channel
+ * associated with a DMA resource. The channel suspend interrupt flag
+ * indicates whether the transfer is truly suspended.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ */
+void dma_suspend_job(struct dma_resource *resource)
+{
+ Assert(resource);
+ Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the channel */
+ DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+
+ /* Send the suspend request */
+ DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Resume a suspended DMA transfer.
+ *
+ * This function try to resume a suspended transfer of a DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ */
+void dma_resume_job(struct dma_resource *resource)
+{
+ uint32_t bitmap_channel;
+ uint32_t count = 0;
+
+ Assert(resource);
+ Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+ /* Get bitmap of the allocated DMA channel */
+ bitmap_channel = (1 << resource->channel_id);
+
+ /* Check if channel was suspended */
+ if (resource->job_status != STATUS_SUSPEND) {
+ return;
+ }
+
+ system_interrupt_enter_critical_section();
+
+ /* Send resume request */
+ DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+ DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+
+ system_interrupt_leave_critical_section();
+
+ /* Check if transfer job resumed */
+ for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
+ if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
+ break;
+ }
+ }
+
+ if (count < MAX_JOB_RESUME_COUNT) {
+ /* Job resumed */
+ resource->job_status = STATUS_BUSY;
+ } else {
+ /* Job resume timeout */
+ resource->job_status = STATUS_ERR_TIMEOUT;
+ }
+}
+
+/**
+ * \brief Create a DMA transfer descriptor with configurations.
+ *
+ * This function will set the transfer configurations to the DMA transfer
+ * descriptor.
+ *
+ * \param[in] descriptor Pointer to the DMA transfer descriptor
+ * \param[in] config Pointer to the descriptor configuration structure
+ *
+ */
+void dma_descriptor_create(DmacDescriptor* descriptor,
+ struct dma_descriptor_config *config)
+{
+ /* Set block transfer control */
+ descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
+ descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
+ descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
+ descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
+ descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
+ descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
+ descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
+ descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
+
+ /* Set transfer size, source address and destination address */
+ descriptor->BTCNT.reg = config->block_transfer_count;
+ descriptor->SRCADDR.reg = config->source_address;
+ descriptor->DSTADDR.reg = config->destination_address;
+
+ /* Set next transfer descriptor address */
+ descriptor->DESCADDR.reg = config->next_descriptor_address;
+}
+
+/**
+ * \brief Add a DMA transfer descriptor to a DMA resource.
+ *
+ * This function will add a DMA transfer descriptor to a DMA resource.
+ * If there was a transfer descriptor already allocated to the DMA resource,
+ * the descriptor will be linked to the next descriptor address.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] descriptor Pointer to the transfer descriptor
+ *
+ * \retval STATUS_OK The descriptor is added to the DMA resource
+ * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
+ */
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+ DmacDescriptor* descriptor)
+{
+ DmacDescriptor* desc = resource->descriptor;
+
+ if (resource->job_status == STATUS_BUSY) {
+ return STATUS_BUSY;
+ }
+
+ /* Look up for an empty space for the descriptor */
+ if (desc == NULL) {
+ resource->descriptor = descriptor;
+ } else {
+ /* Looking for end of descriptor link */
+ while(desc->DESCADDR.reg != 0) {
+ desc = (DmacDescriptor*)(desc->DESCADDR.reg);
+ }
+
+ /* Set to the end of descriptor list */
+ desc->DESCADDR.reg = (uint32_t)descriptor;
+ }
+
+ return STATUS_OK;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,851 @@
+/**
+ * \file
+ *
+ * \brief SAM Direct Memory Access Controller Driver
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef DMA_H_INCLUDED
+#define DMA_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller Driver (DMAC)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the Direct Memory Access Controller(DMAC) module within
+ * the device. The DMAC can transfer data between memories and peripherals, and
+ * thus off-load these tasks from the CPU. The module supports peripheral to
+ * peripheral, peripheral to memory, memory to peripheral, and memory to memory
+ * transfers.
+ *
+ * The following peripherals are used by the DMAC Driver:
+ * - DMAC (Direct Memory Access Controller)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_dma_prerequisites
+ * - \ref asfdoc_sam0_dma_module_overview
+ * - \ref asfdoc_sam0_dma_special_considerations
+ * - \ref asfdoc_sam0_dma_extra_info
+ * - \ref asfdoc_sam0_dma_examples
+ * - \ref asfdoc_sam0_dma_api_overview
+ *
+ *
+ * \section asfdoc_sam0_dma_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_dma_module_overview Module Overview
+ *
+ * SAM devices with DMAC enables high data transfer rates with minimum
+ * CPU intervention and frees up CPU time. With access to all peripherals,
+ * the DMAC can handle automatic transfer of data to/from modules.
+ * It supports static and incremental addressing for both source and
+ * destination.
+ *
+ * The DMAC when used with Event System or peripheral triggers, provides a
+ * considerable advantage by reducing the power consumption and performing
+ * data transfer in the background.
+ * For example if the ADC is configured to generate an event, it can trigger
+ * the DMAC to transfer the data into another peripheral or into SRAM.
+ * The CPU can remain in sleep during this time to reduce power consumption.
+ *
+ * The DMAC module has 12 channels. The DMA channel
+ * operation can be suspended at any time by software, by events
+ * from event system, or after selectable descriptor execution. The operation
+ * can be resumed by software or by events from event system.
+ * The DMAC driver for SAM supports four types of transfers such as
+ * peripheral to peripheral, peripheral to memory, memory to peripheral, and
+ * memory to memory.
+ *
+ * The basic transfer unit is a beat which is defined as a single bus access.
+ * There can be multiple beats in a single block transfer and multiple block
+ * transfers in a DMA transaction.
+ * DMA transfer is based on descriptors, which holds transfer properties
+ * such as the source and destination addresses, transfer counter, and other
+ * additional transfer control information.
+ * The descriptors can be static or linked. When static, a single block transfer
+ * is performed. When linked, a number of transfer descriptors can be used to
+ * enable multiple block transfers within a single DMA transaction.
+ *
+ * The implementation of the DMA driver is based on the idea that DMA channel
+ * is a finite resource of entities with the same abilities. A DMA channel resource
+ * is able to move a defined set of data from a source address to destination
+ * address triggered by a transfer trigger. On the SAM devices there are 12
+ * DMA resources available for allocation. Each of these DMA resources can trigger
+ * interrupt callback routines and peripheral events.
+ * The other main features are
+ *
+ * - Selectable transfer trigger source
+ * - Software
+ * - Event System
+ * - Peripheral
+ * - Event input and output is supported for the four lower channels
+ * - Four level channel priority
+ * - Optional interrupt generation on transfer complete, channel error or channel suspend
+ * - Supports multi-buffer or circular buffer mode by linking multiple descriptors
+ * - Beat size configurable as 8-bit, 16-bit, or 32-bit
+ *
+ * A simplified block diagram of the DMA Resource can be seen in
+ * \ref asfdoc_sam0_dma_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_dma_module_block_diagram
+ * \dot
+ * digraph overview {
+ * splines = false;
+ * rankdir=LR;
+ *
+ * mux1 [label="Transfer Trigger", shape=box];
+ *
+ * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * mux1 -> dma;
+ * descriptor -> dma;
+ *
+ * interrupt [label="Interrupt", shape=box];
+ * events [label="Events", shape=box];
+ *
+ * dma:e -> interrupt:w;
+ * dma:e -> events:w;
+ *
+ * {rank=same; descriptor dma}
+ *
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_DMA_CHANNEL_STANDBY</td>
+ * <td>SAML21</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers
+ *
+ * <table border="0" cellborder="1" cellspacing="0" >
+ * <tr>
+ * <th> Name </th> <th> Description </th>
+ * </tr>
+ * <tr>
+ * <td > Beat </td>
+ * <td > It is a single bus access by the DMAC.
+ * Configurable as 8-bit, 16-bit, or 32-bit
+ * </td>
+ * </tr>
+ * <tr>
+ * <td > Burst </td>
+ * <td> It is a transfer of n-beats (n=1,4,8,16).
+ * For the DMAC module in SAM, the burst size is one beat.
+ * Arbitration takes place each time a burst transfer is completed
+ * </td>
+ * </tr>
+ * <tr>
+ * <td > Block transfer </td>
+ * <td> A single block transfer is a configurable number of (1 to 64k)
+ * beat transfers
+ * </td>
+ * </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels
+ * The DMAC in each device consists of several DMA channels, which
+ * along with the transfer descriptors defines the data transfer properties.
+ * - The transfer control descriptor defines the source and destination
+ * addresses, source and destination address increment settings, the
+ * block transfer count and event output condition selection
+ * - Dedicated channel registers control the peripheral trigger source,
+ * trigger mode settings, event input actions, and channel priority level
+ * settings
+ *
+ * With a successful DMA resource allocation, a dedicated
+ * DMA channel will be assigned. The channel will be occupied until the
+ * DMA resource is freed. A DMA resource handle is used to identify the specific
+ * DMA resource.
+ * When there are multiple channels with active requests, the arbiter prioritizes
+ * the channels requesting access to the bus.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers
+ * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A
+ * transfer request can be triggered from software, peripheral, or an event. There
+ * are dedicated source trigger selections for each DMA channel usage.
+
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor
+ * The transfer descriptor resides in the SRAM and
+ * defines these channel properties.
+ * <table border="0" cellborder="1" cellspacing="0" >
+ * <tr>
+ * <th> Field name </th> <th> Field width </th>
+ * </tr>
+ * <tr>
+ * <td > Descriptor Next Address </td> <td > 32 bits </td>
+ * </tr>
+ * <tr>
+ * <td > Destination Address </td> <td> 32 bits </td>
+ * </tr>
+ * <tr>
+ * <td > Source Address </td> <td> 32 bits </td>
+ * </tr>
+ * <tr>
+ * <td > Block Transfer Counter </td> <td> 16 bits </td>
+ * </tr>
+ * <tr>
+ * <td > Block Transfer Control </td> <td> 16 bits </td>
+ * </tr>
+ * </table>
+ *
+ * Before starting a transfer, at least one descriptor should be configured.
+ * After a successful allocation of a DMA channel, the transfer descriptor can
+ * be added with a call to \ref dma_add_descriptor(). If there is a transfer
+ * descriptor already allocated to the DMA resource, the descriptor will
+ * be linked to the next descriptor address.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events
+ * Both an interrupt callback and an peripheral event can be triggered by the
+ * DMA transfer. Three types of callbacks are supported by the DMA driver:
+ * transfer complete, channel suspend, and transfer error. Each of these callback
+ * types can be registered and enabled for each channel independently through
+ * the DMA driver API.
+ *
+ * The DMAC module can also generate events on transfer complete. Event
+ * generation is enabled through the DMA channel, event channel configuration,
+ * and event user multiplexing is done through the events driver.
+ *
+ * The DMAC can generate events in the below cases:
+ *
+ * - When a block transfer is complete
+ *
+ * - When each beat transfer within a block transfer is complete
+ *
+ * \section asfdoc_sam0_dma_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_dma_extra. This includes:
+ * - \ref asfdoc_sam0_dma_extra_acronyms
+ * - \ref asfdoc_sam0_dma_extra_dependencies
+ * - \ref asfdoc_sam0_dma_extra_errata
+ * - \ref asfdoc_sam0_dma_extra_history
+ *
+ *
+ * \section asfdoc_sam0_dma_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_dma_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_dma_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include "conf_dma.h"
+
+#if (SAML21)
+#define FEATURE_DMA_CHANNEL_STANDBY
+#endif
+
+/** DMA invalid channel number. */
+#define DMA_INVALID_CHANNEL 0xff
+
+/** ExInitial description section. */
+extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM];
+
+/** DMA priority level. */
+enum dma_priority_level {
+ /** Priority level 0. */
+ DMA_PRIORITY_LEVEL_0,
+ /** Priority level 1. */
+ DMA_PRIORITY_LEVEL_1,
+ /** Priority level 2. */
+ DMA_PRIORITY_LEVEL_2,
+ /** Priority level 3. */
+ DMA_PRIORITY_LEVEL_3,
+};
+
+/** DMA input actions. */
+enum dma_event_input_action {
+ /** No action. */
+ DMA_EVENT_INPUT_NOACT,
+ /** Normal transfer and periodic transfer trigger. */
+ DMA_EVENT_INPUT_TRIG,
+ /** Conditional transfer trigger. */
+ DMA_EVENT_INPUT_CTRIG,
+ /** Conditional block transfer. */
+ DMA_EVENT_INPUT_CBLOCK,
+ /** Channel suspend operation. */
+ DMA_EVENT_INPUT_SUSPEND,
+ /** Channel resume operation. */
+ DMA_EVENT_INPUT_RESUME,
+ /** Skip next block suspend action. */
+ DMA_EVENT_INPUT_SSKIP,
+};
+
+/**
+ * Address increment step size. These bits select the address increment step
+ * size. The setting apply to source or destination address, depending on
+ * STEPSEL setting.
+ */
+enum dma_address_increment_stepsize {
+ /** The address is incremented by (beat size * 1). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
+ /** The address is incremented by (beat size * 2). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
+ /** The address is incremented by (beat size * 4). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
+ /** The address is incremented by (beat size * 8). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
+ /** The address is incremented by (beat size * 16). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
+ /** The address is incremented by (beat size * 32). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
+ /** The address is incremented by (beat size * 64). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
+ /** The address is incremented by (beat size * 128). */
+ DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
+};
+
+/**
+ * DMA step selection. This bit determines whether the step size setting
+ * is applied to source or destination address.
+ */
+enum dma_step_selection {
+ /** Step size settings apply to the destination address. */
+ DMA_STEPSEL_DST = 0,
+ /** Step size settings apply to the source address. */
+ DMA_STEPSEL_SRC,
+};
+
+/** The basic transfer unit in DMAC is a beat, which is defined as a
+ * single bus access. Its size is configurable and applies to both read
+ * and write. */
+enum dma_beat_size {
+ /** 8-bit access. */
+ DMA_BEAT_SIZE_BYTE = 0,
+ /** 16-bit access. */
+ DMA_BEAT_SIZE_HWORD,
+ /** 32-bit access. */
+ DMA_BEAT_SIZE_WORD,
+};
+
+/**
+ * Block action definitions.
+ */
+enum dma_block_action {
+ /** No action. */
+ DMA_BLOCK_ACTION_NOACT = 0,
+ /** Channel in normal operation and sets transfer complete interrupt flag
+ * after block transfer. */
+ DMA_BLOCK_ACTION_INT,
+ /** Trigger channel suspend after block transfer and sets channel
+ * suspend interrupt flag once the channel is suspended. */
+ DMA_BLOCK_ACTION_SUSPEND,
+ /** Sets transfer complete interrupt flag after a block transfer and
+ * trigger channel suspend. The channel suspend interrupt flag will be set
+ * once the channel is suspended. */
+ DMA_BLOCK_ACTION_BOTH,
+};
+
+/** Event output selection. */
+enum dma_event_output_selection {
+ /** Event generation disable. */
+ DMA_EVENT_OUTPUT_DISABLE = 0,
+ /** Event strobe when block transfer complete. */
+ DMA_EVENT_OUTPUT_BLOCK,
+ /** Event output reserved. */
+ DMA_EVENT_OUTPUT_RESERVED,
+ /** Event strobe when beat transfer complete. */
+ DMA_EVENT_OUTPUT_BEAT,
+};
+
+/** DMA trigger action type. */
+enum dma_transfer_trigger_action {
+ /** Perform a block transfer when triggered. */
+ DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
+ /** Perform a beat transfer when triggered. */
+ DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
+ /** Perform a transaction when triggered. */
+ DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
+};
+
+/**
+ * Callback types for DMA callback driver.
+ */
+enum dma_callback_type {
+ /** Callback for transfer complete. */
+ DMA_CALLBACK_TRANSFER_DONE,
+ /** Callback for any of transfer errors. A transfer error is flagged
+ * if a bus error is detected during an AHB access or when the DMAC
+ * fetches an invalid descriptor. */
+ DMA_CALLBACK_TRANSFER_ERROR,
+ /** Callback for channel suspend. */
+ DMA_CALLBACK_CHANNEL_SUSPEND,
+ /** Number of available callbacks. */
+ DMA_CALLBACK_N,
+};
+
+/**
+ * DMA transfer descriptor configuration. When the source or destination address
+ * increment is enabled, the addresses stored into the configuration structure
+ * must correspond to the end of the transfer.
+ *
+ */
+struct dma_descriptor_config {
+ /** Descriptor valid flag used to identify whether a descriptor is
+ valid or not. */
+ bool descriptor_valid;
+ /** This is used to generate an event on specific transfer action in
+ a channel. Supported only in four lower channels. */
+ enum dma_event_output_selection event_output_selection;
+ /** Action taken when a block transfer is completed. */
+ enum dma_block_action block_action;
+ /** Beat size is configurable as 8-bit, 16-bit, or 32-bit. */
+ enum dma_beat_size beat_size;
+ /** Used for enabling the source address increment. */
+ bool src_increment_enable;
+ /** Used for enabling the destination address increment. */
+ bool dst_increment_enable;
+ /** This bit selects whether the source or destination address is
+ using the step size settings. */
+ enum dma_step_selection step_selection;
+ /** The step size for source/destination address increment.
+ The next address is calculated
+ as next_addr = addr + (2^step_size * beat size). */
+ enum dma_address_increment_stepsize step_size;
+ /** It is the number of beats in a block. This count value is
+ * decremented by one after each beat data transfer. */
+ uint16_t block_transfer_count;
+ /** Transfer source address. */
+ uint32_t source_address;
+ /** Transfer destination address. */
+ uint32_t destination_address;
+ /** Set to zero for static descriptors. This must have a valid memory
+ address for linked descriptors. */
+ uint32_t next_descriptor_address;
+};
+
+/** Configurations for DMA events. */
+struct dma_events_config {
+ /** Event input actions. */
+ enum dma_event_input_action input_action;
+ /** Enable DMA event output. */
+ bool event_output_enable;
+};
+
+/** DMA configurations for transfer. */
+struct dma_resource_config {
+ /** DMA transfer priority. */
+ enum dma_priority_level priority;
+ /**DMA peripheral trigger index. */
+ uint8_t peripheral_trigger;
+ /** DMA trigger action. */
+ enum dma_transfer_trigger_action trigger_action;
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+ /** Keep DMA channel enabled in standby sleep mode if true. */
+ bool run_in_standby;
+#endif
+ /** DMA events configurations. */
+ struct dma_events_config event_config;
+};
+
+/** Forward definition of the DMA resource. */
+struct dma_resource;
+/** Type definition for a DMA resource callback function. */
+typedef void (*dma_callback_t)(const struct dma_resource *const resource);
+
+/** Structure for DMA transfer resource. */
+struct dma_resource {
+ /** Allocated DMA channel ID. */
+ uint8_t channel_id;
+ /** Array of callback functions for DMA transfer job. */
+ dma_callback_t callback[DMA_CALLBACK_N];
+ /** Bit mask for enabled callbacks. */
+ uint8_t callback_enable;
+ /** Status of the last job. */
+ volatile enum status_code job_status;
+ /** Transferred data size. */
+ uint32_t transfered_size;
+ /** DMA transfer descriptor. */
+ DmacDescriptor* descriptor;
+};
+
+/**
+ * \brief Get DMA resource status.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ * \return Status of the DMA resource.
+ */
+static inline enum status_code dma_get_job_status(struct dma_resource *resource)
+{
+ Assert(resource);
+
+ return resource->job_status;
+}
+
+/**
+ * \brief Check if the given DMA resource is busy.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ * \return Status which indicates whether the DMA resource is busy.
+ *
+ * \retval true The DMA resource has an on-going transfer
+ * \retval false The DMA resource is not busy
+ */
+static inline bool dma_is_busy(struct dma_resource *resource)
+{
+ Assert(resource);
+
+ return (resource->job_status == STATUS_BUSY);
+}
+
+/**
+ * \brief Enable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_enable_callback(struct dma_resource *resource,
+ enum dma_callback_type type)
+{
+ Assert(resource);
+
+ resource->callback_enable |= 1 << type;
+}
+
+/**
+ * \brief Disable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_disable_callback(struct dma_resource *resource,
+ enum dma_callback_type type)
+{
+ Assert(resource);
+
+ resource->callback_enable &= ~(1 << type);
+}
+
+/**
+ * \brief Register a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions, which can be registered:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] callback Pointer to the callback function
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_register_callback(struct dma_resource *resource,
+ dma_callback_t callback, enum dma_callback_type type)
+{
+ Assert(resource);
+
+ resource->callback[type] = callback;
+}
+
+/**
+ * \brief Unregister a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * The application can unregister any of the callback functions which
+ * are already registered and are no longer needed.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_unregister_callback(struct dma_resource *resource,
+ enum dma_callback_type type)
+{
+ Assert(resource);
+
+ resource->callback[type] = NULL;
+}
+
+/**
+ * \brief Will set a software trigger for resource.
+ *
+ * This function is used to set a software trigger on the DMA channel
+ * associated with resource. If a trigger is already pending no new trigger
+ * will be generated for the channel.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ */
+static inline void dma_trigger_transfer(struct dma_resource *resource)
+{
+ Assert(resource);
+
+ DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
+}
+
+/**
+ * \brief Initializes DMA transfer configuration with predefined default values.
+ *
+ * This function will initialize a given DMA descriptor configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ * \li Set the descriptor as valid
+ * \li Disable event output
+ * \li No block action
+ * \li Set beat size as byte
+ * \li Enable source increment
+ * \li Enable destination increment
+ * \li Step size is applied to the destination address
+ * \li Address increment is beat size multiplied by 1
+ * \li Default transfer size is set to 0
+ * \li Default source address is set to NULL
+ * \li Default destination address is set to NULL
+ * \li Default next descriptor not available
+ * \param[out] config Pointer to the configuration
+ *
+ */
+static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
+{
+ Assert(config);
+
+ /* Set descriptor as valid */
+ config->descriptor_valid = true;
+ /* Disable event output */
+ config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
+ /* No block action */
+ config->block_action = DMA_BLOCK_ACTION_NOACT;
+ /* Set beat size to one byte */
+ config->beat_size = DMA_BEAT_SIZE_BYTE;
+ /* Enable source increment */
+ config->src_increment_enable = true;
+ /* Enable destination increment */
+ config->dst_increment_enable = true;
+ /* Step size is applied to the destination address */
+ config->step_selection = DMA_STEPSEL_DST;
+ /* Address increment is beat size multiplied by 1*/
+ config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
+ /* Default transfer size is set to 0 */
+ config->block_transfer_count = 0;
+ /* Default source address is set to NULL */
+ config->source_address = (uint32_t)NULL;
+ /* Default destination address is set to NULL */
+ config->destination_address = (uint32_t)NULL;
+ /** Next descriptor address set to 0 */
+ config->next_descriptor_address = 0;
+}
+
+/**
+ * \brief Update DMA descriptor.
+ *
+ * This function can update the descriptor of an allocated DMA resource.
+ *
+ */
+static inline void dma_update_descriptor(struct dma_resource *resource,
+ DmacDescriptor* descriptor)
+{
+ Assert(resource);
+
+ resource->descriptor = descriptor;
+}
+
+/**
+ * \brief Reset DMA descriptor.
+ *
+ * This function will clear the DESCADDR register of an allocated DMA resource.
+ *
+ */
+static inline void dma_reset_descriptor(struct dma_resource *resource)
+{
+ Assert(resource);
+
+ resource->descriptor = NULL;
+}
+
+void dma_get_config_defaults(struct dma_resource_config *config);
+enum status_code dma_allocate(struct dma_resource *resource,
+ struct dma_resource_config *config);
+enum status_code dma_free(struct dma_resource *resource);
+enum status_code dma_start_transfer_job(struct dma_resource *resource);
+void dma_abort_job(struct dma_resource *resource);
+void dma_suspend_job(struct dma_resource *resource);
+void dma_resume_job(struct dma_resource *resource);
+void dma_descriptor_create(DmacDescriptor* descriptor,
+ struct dma_descriptor_config *config);
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+ DmacDescriptor* descriptor);
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver
+ *
+ * \section asfdoc_sam0_dma_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>DMA</td>
+ * <td>Direct Memory Access</td>
+ * </tr>
+ * <tr>
+ * <td>DMAC</td>
+ * <td>Direct Memory Access Controller </td>
+ * </tr>
+ * <tr>
+ * <td>CPU</td>
+ * <td>Central Processing Unit</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Driver"
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Add SAM L21 support</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+* \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver
+*
+* This is a list of the available Quick Start Guides (QSGs) and example
+* applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with
+* step-by-step instructions to configure and use this driver in a selection of
+* use cases. Note that QSGs can be compiled as a standalone application or be
+* added to the user application.
+*
+* - \subpage asfdoc_sam0_dma_basic_use_case
+*
+* \note More DMA usage examples are available in peripheral QSGs.
+* A quick start guide for TC/TCC
+* shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for
+* DMA transfer from peripheral to memory or from memory to peripheral;
+* ADC/DAC shows peripheral to peripheral transfer.
+*
+* \page asfdoc_sam0_dma_document_revision_history Document Revision History
+*
+* <table>
+* <tr>
+* <th>Doc. Rev.</td>
+* <th>Date</td>
+* <th>Comments</td>
+* </tr>
+* <tr>
+* <td>C</td>
+* <td>11/2014</td>
+* <td>Added SAML21 support</td>
+* </tr>
+* <tr>
+* <td>B</td>
+* <td>12/2014</td>
+* <td>Added SAMR21 and SAMD10/D11 support</td>
+* </tr>
+* <tr>
+* <td>A</td>
+* <td>02/2014</td>
+* <td>Initial release</td>
+* </tr>
+* </table>
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma_crc.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,230 @@
+/**
+ * \file
+ *
+ * \brief SAM DMA cyclic redundancy check (CRC) Driver
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef DMA_CRC_H_INCLUDED
+#define DMA_CRC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMA channel n offset. */
+#define DMA_CRC_CHANNEL_N_OFFSET 0x20
+
+/** CRC Polynomial Type. */
+enum crc_polynomial_type {
+ /** CRC16 (CRC-CCITT). */
+ CRC_TYPE_16,
+ /** CRC32 (IEEE 802.3). */
+ CRC_TYPE_32,
+};
+
+/** CRC Beat Type. */
+enum crc_beat_size {
+ /** Byte bus access. */
+ CRC_BEAT_SIZE_BYTE,
+ /** Half-word bus access. */
+ CRC_BEAT_SIZE_HWORD,
+ /** Word bus access. */
+ CRC_BEAT_SIZE_WORD,
+};
+
+/** Configurations for CRC calculation. */
+struct dma_crc_config {
+ /** CRC polynomial type. */
+ enum crc_polynomial_type type;
+ /** CRC beat size. */
+ enum crc_beat_size size;
+};
+
+/**
+ * \brief Get DMA CRC default configurations.
+ *
+ * The default configuration is as follows:
+ * \li Polynomial type is set to CRC-16(CRC-CCITT)
+ * \li CRC Beat size: BYTE
+ *
+ * \param[in] config default configurations
+ */
+static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
+{
+ Assert(config);
+
+ config->type = CRC_TYPE_16;
+ config->size = CRC_BEAT_SIZE_BYTE;
+}
+
+/**
+ * \brief Enable DMA CRC module with an DMA channel.
+ *
+ * This function enables a CRC calculation with an allocated DMA channel. This channel ID
+ * can be gotten from a successful \ref dma_allocate.
+ *
+ * \param[in] channel_id DMA channel expected with CRC calculation
+ * \param[in] config CRC calculation configurations
+ *
+ * \return Status of the DMC CRC.
+ * \retval STATUS_OK Get the DMA CRC module
+ * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
+ */
+static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
+ struct dma_crc_config *config)
+{
+ if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
+ return STATUS_BUSY;
+ }
+
+ DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+ DMAC_CRCCTRL_CRCPOLY(config->type) |
+ DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
+
+ DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disable DMA CRC module.
+ *
+ */
+static inline void dma_crc_disable(void)
+{
+ DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
+ DMAC->CRCCTRL.reg = 0;
+}
+
+/**
+ * \brief Get DMA CRC checksum value.
+ *
+ * \return Calculated CRC checksum.
+ */
+static inline uint32_t dma_crc_get_checksum(void)
+{
+ if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
+ DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+ }
+
+ return DMAC->CRCCHKSUM.reg;
+}
+
+/**
+ * \brief Enable DMA CRC module with I/O.
+ *
+ * This function enables a CRC calculation with I/O mode.
+ *
+ * \param[in] config CRC calculation configurations.
+ *
+ * \return Status of the DMC CRC.
+ * \retval STATUS_OK Get the DMA CRC module
+ * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
+ */
+static inline enum status_code dma_crc_io_enable(
+ struct dma_crc_config *config)
+{
+ if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
+ return STATUS_BUSY;
+ }
+
+ if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
+ return STATUS_BUSY;
+ }
+
+ DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+ DMAC_CRCCTRL_CRCPOLY(config->type) |
+ DMAC_CRCCTRL_CRCSRC_IO;
+
+ if (config->type == CRC_TYPE_32) {
+ DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
+ }
+
+ DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Calculate CRC with I/O.
+ *
+ * This function calculate the CRC of the input data buffer.
+ *
+ * \param[in] buffer CRC Pointer to calculation buffer
+ * \param[in] total_beat_size Total beat size to be calculated
+ *
+ * \return Calculated CRC checksum value.
+ */
+static inline void dma_crc_io_calculation(void *buffer,
+ uint32_t total_beat_size)
+{
+ uint32_t counter = total_beat_size;
+ uint8_t *buffer_8;
+ uint16_t *buffer_16;
+ uint32_t *buffer_32;
+
+ for (counter=0; counter<total_beat_size; counter++) {
+ if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
+ buffer_8 = buffer;
+ DMAC->CRCDATAIN.reg = buffer_8[counter];
+ } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
+ buffer_16 = buffer;
+ DMAC->CRCDATAIN.reg = buffer_16[counter];
+ } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
+ buffer_32 = buffer;
+ DMAC->CRCDATAIN.reg = buffer_32[counter];
+ }
+ /* Wait several cycle to make sure CRC complete */
+ nop();
+ nop();
+ nop();
+ nop();
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_CRC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/quick_start/qs_dma_basic.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,155 @@ +/** + * \file + * + * \brief SAM Direct Memory Access Controller(DMAC) Driver Quick Start + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \page asfdoc_sam0_dma_basic_use_case Quick Start Guide for Memory to Memory Data Transfer Using DMAC + * + * The supported board list: + * - SAMD21 Xplained Pro + * - SAMR21 Xplained Pro + * - SAMD11 Xplained Pro + * - SAML21 Xplained Pro + * + * In this use case, the DMAC is configured for: + * \li Moving data from memory to memory + * \li Using software trigger + * \li Using DMA priority level 0 + * \li Transaction as DMA trigger action + * \li No action on input events + * \li Output event not enabled + * + * \section asfdoc_sam0_dma_basic_use_case_setup Setup + * + * \subsection asfdoc_sam0_dma_basic_use_casesetup_prereq Prerequisites + * There are no special setup requirements for this use-case. + * + * \subsection asfdoc_sam0_dma_basic_use_casesetup_code Code + * Copy-paste the following setup code to your user application: + * \snippet qs_dma_basic.c setup + * + * Add the below section to user application initialization (typically the + * start of \c main()): + * \snippet qs_dma_basic.c setup_init + * + * \subsection asfdoc_sam0_dma_basic_use_casesetup_flow Workflow + * -# Create a DMA resource configuration structure, which can be filled out to + * adjust the configuration of a single DMA transfer. + * \snippet qs_dma_basic.c setup_1 + * \br + * + * -# Initialize the DMA resource configuration struct with the module's + * default values. + * \snippet qs_dma_basic.c setup_2 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Allocate a DMA resource with the configurations. + * \snippet qs_dma_basic.c setup_3 + * \br + + * -# Declare a DMA transfer descriptor configuration structure, which can be + * filled out to adjust the configuration of a single DMA transfer. + * \snippet qs_dma_basic.c setup_4 + * \br + * + * -# Initialize the DMA transfer descriptor configuration struct with the + * module's default values. + * \snippet qs_dma_basic.c setup_5 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Set the specific parameters for a DMA transfer with transfer size, source + * address, and destination address. In this example, we have enabled the + * source and destination address increment. + * The source and destination addresses to be stored into descriptor_config + * must correspond to the end of the transfer. + * + * \snippet qs_dma_basic.c setup_6 + * \br + * + * -# Create the DMA transfer descriptor. + * \snippet qs_dma_basic.c setup_7 + * \br + * + * -# Add the DMA transfer descriptor to the allocated DMA resource. + * \snippet qs_dma_basic.c add_descriptor_to_dma_resource + * \br + * + * -# Register a callback to indicate transfer status. + * \snippet qs_dma_basic.c setup_callback_register + * \br + * + * -# Set the transfer done flag in the registered callback function. + * \snippet qs_dma_basic.c _transfer_done + * \br + * + * -# Enable the registered callbacks. + * \snippet qs_dma_basic.c setup_enable_callback + * \br + * + * \section asfdoc_sam0_dma_basic_use_case_main Use Case + * + * \subsection asfdoc_sam0_dma_basic_use_casecode_code Code + * Add the following code at the start of \c main(): + * \snippet qs_dma_basic.c sample_resource + * Copy the following code to your user application: + * \snippet qs_dma_basic.c main + * + * \subsection dma_basic_use_case_code_flow Workflow + * -# Start the DMA transfer job with the allocated DMA resource and + * transfer descriptor. + * \snippet qs_dma_basic.c main_1 + * + * -# Set the software trigger for the DMA channel. This can be done before + * or after the DMA job is started. Note that all transfers needs a trigger + * to start. + * \snippet qs_dma_basic.c main_1_1 + * + * -# Waiting for the setting of the transfer done flag. + * \snippet qs_dma_basic.c main_2 + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,710 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef EXTINT_H_INCLUDED
+#define EXTINT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_extint_group SAM External Interrupt Driver (EXTINT)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of external interrupts generated by the physical device pins,
+ * including edge detection. The following driver API modes are covered by this
+ * manual:
+ *
+ * - Polled APIs
+ * \if EXTINT_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ * - EIC (External Interrupt Controller)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_extint_prerequisites
+ * - \ref asfdoc_sam0_extint_module_overview
+ * - \ref asfdoc_sam0_extint_special_considerations
+ * - \ref asfdoc_sam0_extint_extra_info
+ * - \ref asfdoc_sam0_extint_examples
+ * - \ref asfdoc_sam0_extint_api_overview
+ *
+ *
+ * \section asfdoc_sam0_extint_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_extint_module_overview Module Overview
+ *
+ * The External Interrupt (EXTINT) module provides a method of asynchronously
+ * detecting rising edge, falling edge or specific level detection on individual
+ * I/O pins of a device. This detection can then be used to trigger a software
+ * interrupt or event, or polled for later use if required. External interrupts
+ * can also optionally be used to automatically wake up the device from sleep
+ * mode, allowing the device to conserve power while still being able to react
+ * to an external stimulus in a timely manner.
+ *
+ * \subsection asfdoc_sam0_extint_logical_channels Logical Channels
+ * The External Interrupt module contains a number of logical channels, each of
+ * which is capable of being individually configured for a given pin routing,
+ * detection mode, and filtering/wake up characteristics.
+ *
+ * Each individual logical external interrupt channel may be routed to a single
+ * physical device I/O pin in order to detect a particular edge or level of the
+ * incoming signal.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_nmi_chanel NMI Channels
+ *
+ * One or more Non Maskable Interrupt (NMI) channels are provided within each
+ * physical External Interrupt Controller module, allowing a single physical pin
+ * of the device to fire a single NMI interrupt in response to a particular
+ * edge or level stimulus. A NMI cannot, as the name suggests, be disabled in
+ * firmware and will take precedence over any in-progress interrupt sources.
+ *
+ * NMIs can be used to implement critical device features such as forced
+ * software reset or other functionality where the action should be executed in
+ * preference to all other running code with a minimum amount of latency.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_filtering Input Filtering and Detection
+ *
+ * To reduce the possibility of noise or other transient signals causing
+ * unwanted device wake-ups, interrupts and/or events via an external interrupt
+ * channel, a hardware signal filter can be enabled on individual channels. This
+ * filter provides a Majority-of-Three voter filter on the incoming signal, so
+ * that the input state is considered to be the majority vote of three
+ * subsequent samples of the pin input buffer. The possible sampled input and
+ * resulting filtered output when the filter is enabled is shown in
+ * \ref asfdoc_sam0_extint_filter_table "the table below".
+ *
+ * \anchor asfdoc_sam0_extint_filter_table
+ * <table>
+ * <caption>Sampled Input and Rresulting Filtered Output</caption>
+ * <tr>
+ * <th>Input Sample 1</th>
+ * <th>Input Sample 2</th>
+ * <th>Input Sample 3</th>
+ * <th>Filtered Output</th>
+ * </tr>
+ * <tr>
+ * <td>0</td> <td>0</td> <td>0</td> <td>0</td>
+ * </tr>
+ * <tr>
+ * <td>0</td> <td>0</td> <td>1</td> <td>0</td>
+ * </tr>
+ * <tr>
+ * <td>0</td> <td>1</td> <td>0</td> <td>0</td>
+ * </tr>
+ * <tr>
+ * <td>0</td> <td>1</td> <td>1</td> <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>1</td> <td>0</td> <td>0</td> <td>0</td>
+ * </tr>
+ * <tr>
+ * <td>1</td> <td>0</td> <td>1</td> <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>1</td> <td>1</td> <td>0</td> <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>1</td> <td>1</td> <td>1</td> <td>1</td>
+ * </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_events Events and Interrupts
+ *
+ * Channel detection states may be polled inside the application for synchronous
+ * detection, or events and interrupts may be used for asynchronous behavior.
+ * Each channel can be configured to give an asynchronous hardware event (which
+ * may in turn trigger actions in other hardware modules) or an asynchronous
+ * software interrupt.
+ *
+ * \note The connection of events between modules requires the use of the
+ * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ * to route output event of one module to the input event of another.
+ * For more information on event routing, refer to the event driver
+ * documentation.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_extint_int_connections "The diagram below" shows how this
+ * module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_extint_int_connections
+ * \dot
+ * digraph overview {
+ * node [label="Port Pad" shape=square] pad;
+ *
+ * subgraph driver {
+ * node [label="Peripheral MUX" shape=trapezium] pinmux;
+ * node [label="EIC Module" shape=ellipse] eic;
+ * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ * }
+ *
+ * pinmux -> eic;
+ * pad -> pinmux;
+ * pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_extint_special_considerations Special Considerations
+ *
+ * Not all devices support disabling of the NMI channel(s) detection mode - see
+ * your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_extint_extra. This includes:
+ * - \ref asfdoc_sam0_extint_extra_acronyms
+ * - \ref asfdoc_sam0_extint_extra_dependencies
+ * - \ref asfdoc_sam0_extint_extra_errata
+ * - \ref asfdoc_sam0_extint_extra_history
+ *
+ *
+ * \section asfdoc_sam0_extint_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_extint_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_extint_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief External interrupt edge detection configuration enum.
+ *
+ * Enum for the possible signal edge detection modes of the External
+ * Interrupt Controller module.
+ */
+enum extint_detect {
+ /** No edge detection. Not allowed as a NMI detection mode on some
+ * devices. */
+ EXTINT_DETECT_NONE = 0,
+ /** Detect rising signal edges. */
+ EXTINT_DETECT_RISING = 1,
+ /** Detect falling signal edges. */
+ EXTINT_DETECT_FALLING = 2,
+ /** Detect both signal edges. */
+ EXTINT_DETECT_BOTH = 3,
+ /** Detect high signal levels. */
+ EXTINT_DETECT_HIGH = 4,
+ /** Detect low signal levels. */
+ EXTINT_DETECT_LOW = 5,
+};
+
+/**
+ * \brief External interrupt internal pull configuration enum.
+ *
+ * Enum for the possible pin internal pull configurations.
+ *
+ * \note Disabling the internal pull resistor is not recommended if the driver
+ * is used in interrupt (callback) mode, due the possibility of floating
+ * inputs generating continuous interrupts.
+ */
+enum extint_pull {
+ /** Internal pull-up resistor is enabled on the pin. */
+ EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
+ /** Internal pull-down resistor is enabled on the pin. */
+ EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+ /** Internal pull resistor is disconnected from the pin. */
+ EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+};
+
+/** The EIC is clocked by GCLK_EIC. */
+#define EXTINT_CLK_GCLK 0
+/** The EIC is clocked by CLK_ULP32K. */
+#define EXTINT_CLK_ULP32K 1
+
+/**
+ * \brief External Interrupt Controller channel configuration structure.
+ *
+ * Configuration structure for the edge detection mode of an external
+ * interrupt channel.
+ */
+struct extint_chan_conf {
+ /** GPIO pin the NMI should be connected to. */
+ uint32_t gpio_pin;
+ /** MUX position the GPIO pin should be configured to. */
+ uint32_t gpio_pin_mux;
+ /** Internal pull to enable on the input pin. */
+ enum extint_pull gpio_pin_pull;
+#if (SAML21)
+ /** Enable asynchronous edge detection. */
+ bool enable_async_edge_detection;
+#else
+ /** Wake up the device if the channel interrupt fires during sleep mode. */
+ bool wake_if_sleeping;
+#endif
+ /** Filter the raw input signal to prevent noise from triggering an
+ * interrupt accidentally, using a 3 sample majority filter. */
+ bool filter_input_signal;
+ /** Edge detection mode to use. */
+ enum extint_detect detection_criteria;
+};
+
+/**
+ * \brief External Interrupt event enable/disable structure.
+ *
+ * Event flags for the \ref extint_enable_events() and
+ * \ref extint_disable_events().
+ */
+struct extint_events {
+ /** If \c true, an event will be generated when an external interrupt
+ * channel detection state changes. */
+ bool generate_event_on_detect[32 * EIC_INST_NUM];
+};
+
+/**
+ * \brief External Interrupt Controller NMI configuration structure.
+ *
+ * Configuration structure for the edge detection mode of an external
+ * interrupt NMI channel.
+ */
+struct extint_nmi_conf {
+ /** GPIO pin the NMI should be connected to. */
+ uint32_t gpio_pin;
+ /** MUX position the GPIO pin should be configured to. */
+ uint32_t gpio_pin_mux;
+ /** Internal pull to enable on the input pin. */
+ enum extint_pull gpio_pin_pull;
+ /** Filter the raw input signal to prevent noise from triggering an
+ * interrupt accidentally, using a 3 sample majority filter. */
+ bool filter_input_signal;
+ /** Edge detection mode to use. Not all devices support all possible
+ * detection modes for NMIs.
+ */
+ enum extint_detect detection_criteria;
+#if (SAML21)
+ /** Enable asynchronous edge detection. */
+ bool enable_async_edge_detection;
+#endif
+};
+// TEMP: Commented by V
+//#if EXTINT_CALLBACK_MODE == true
+/** Type definition for an EXTINT module callback function. */
+typedef void (*extint_callback_t)(void);
+
+#ifndef EIC_NUMBER_OF_INTERRUPTS
+# define EIC_NUMBER_OF_INTERRUPTS 16
+#endif
+//#endif
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ * Internal EXTINT module device instance structure definition.
+ */
+struct _extint_module {
+// TEMP: Commented by V
+//# if EXTINT_CALLBACK_MODE == true
+ /** Asynchronous channel callback table, for user-registered handlers. */
+ extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
+//# else
+ /** Dummy value to ensure the struct has at least one member */
+// uint8_t _dummy;
+//# endif
+};
+
+/**
+ * \brief Retrieves the base EIC module address from a given channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given external interrupt channel.
+ *
+ * \param[in] channel External interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_channel(
+ const uint8_t channel)
+{
+ uint8_t eic_index = (channel / 32);
+
+ if (eic_index < EIC_INST_NUM) {
+ /* Array of available EICs. */
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ return eics[eic_index];
+ } else {
+ Assert(false);
+ return NULL;
+ }
+}
+
+/**
+ * \brief Retrieves the base EIC module address from a given NMI channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given non-maskable external interrupt channel.
+ *
+ * \param[in] nmi_channel Non-Maskable interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_nmi(
+ const uint8_t nmi_channel)
+{
+ uint8_t eic_index = nmi_channel;
+
+ if (eic_index < EIC_INST_NUM) {
+ /* Array of available EICs. */
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ return eics[eic_index];
+ } else {
+ Assert(false);
+ return NULL;
+ }
+}
+#endif
+
+/** \name Event Management
+ * @{
+ */
+
+void extint_enable_events(
+ struct extint_events *const events);
+
+void extint_disable_events(
+ struct extint_events *const events);
+
+/** @} */
+
+/** \name Configuration and Initialization (Channel)
+ * @{
+ */
+
+void extint_chan_get_config_defaults(
+ struct extint_chan_conf *const config);
+
+void extint_chan_set_config(
+ const uint8_t channel,
+ const struct extint_chan_conf *const config);
+
+/** @} */
+
+/** \name Configuration and Initialization (NMI)
+ * @{
+ */
+
+/**
+ * \brief Initializes an External Interrupt NMI channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt NMI channel configuration structure
+ * to a set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input filtering disabled
+ * \li Detect falling edges of a signal
+ * \li Asynchronous edge detection is disabled
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void extint_nmi_get_config_defaults(
+ struct extint_nmi_conf *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->gpio_pin = 0;
+ config->gpio_pin_mux = 0;
+ config->gpio_pin_pull = EXTINT_PULL_UP;
+ config->filter_input_signal = false;
+ config->detection_criteria = EXTINT_DETECT_FALLING;
+#if (SAML21)
+ config->enable_async_edge_detection = false;
+#endif
+
+}
+
+enum status_code extint_nmi_set_config(
+ const uint8_t nmi_channel,
+ const struct extint_nmi_conf *const config);
+
+/** @} */
+
+/** \name Detection testing and clearing (channel)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured channel.
+ *
+ * Reads the current state of a configured channel, and determines
+ * if the detection criteria of the channel has been met.
+ *
+ * \param[in] channel External Interrupt channel index to check
+ *
+ * \return Status of the requested channel's edge detection state.
+ * \retval true If the channel's edge/level detection criteria was met
+ * \retval false If the channel has not detected its configured criteria
+ */
+static inline bool extint_chan_is_detected(
+ const uint8_t channel)
+{
+ Eic *const eic_module = _extint_get_eic_from_channel(channel);
+ uint32_t eic_mask = (1UL << (channel % 32));
+
+ return (eic_module->INTFLAG.reg & eic_mask);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured channel.
+ *
+ * Clears the current state of a configured channel, readying it for
+ * the next level or edge detection.
+ *
+ * \param[in] channel External Interrupt channel index to check
+ */
+static inline void extint_chan_clear_detected(
+ const uint8_t channel)
+{
+ Eic *const eic_module = _extint_get_eic_from_channel(channel);
+ uint32_t eic_mask = (1UL << (channel % 32));
+
+ eic_module->INTFLAG.reg = eic_mask;
+}
+
+/** @} */
+
+/** \name Detection Testing and Clearing (NMI)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured NMI channel.
+ *
+ * Reads the current state of a configured NMI channel, and determines
+ * if the detection criteria of the NMI channel has been met.
+ *
+ * \param[in] nmi_channel External Interrupt NMI channel index to check
+ *
+ * \return Status of the requested NMI channel's edge detection state.
+ * \retval true If the NMI channel's edge/level detection criteria was met
+ * \retval false If the NMI channel has not detected its configured criteria
+ */
+static inline bool extint_nmi_is_detected(
+ const uint8_t nmi_channel)
+{
+ Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+ return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured NMI channel.
+ *
+ * Clears the current state of a configured NMI channel, readying it for
+ * the next level or edge detection.
+ *
+ * \param[in] nmi_channel External Interrupt NMI channel index to check
+ */
+static inline void extint_nmi_clear_detected(
+ const uint8_t nmi_channel)
+{
+ Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+ eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+// TEMP: Commented by V
+//#if EXTINT_CALLBACK_MODE == true
+# include "extint_callback.h"
+//#endif
+
+/**
+ * \page asfdoc_sam0_extint_extra Extra Information for EXTINT Driver
+ *
+ * \section asfdoc_sam0_extint_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>EIC</td>
+ * <td>External Interrupt Controller</td>
+ * </tr>
+ * <tr>
+ * <td>MUX</td>
+ * <td>Multiplexer</td>
+ * </tr>
+ * <tr>
+ * <td>NMI</td>
+ * <td>Non-Maskable Interrupt</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Add SAML21 support</td>
+ * </tr>
+ * <tr>
+ * <td>Add SAMR21 support</td>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Driver updated to follow driver type convention.
+ * \li Removed \c %extint_reset(), \c %extint_disable() and
+ * \c extint_enable() functions. Added internal function
+ * \c %_system_extint_init().
+ * \li Added configuration EXTINT_CLOCK_SOURCE in conf_extint.h.
+ * \li Removed configuration EXTINT_CALLBACKS_MAX in conf_extint.h, and
+ * added channel parameter in the register functions
+ * \c %extint_register_callback() and \c %extint_unregister_callback().
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Updated interrupt handler to clear interrupt flag before calling
+ * callback function.</td>
+ * </tr>
+ * <tr>
+ * <td>Updated initialization function to also enable the digital interface
+ * clock to the module if it is disabled.</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_extint_exqsg Examples for EXTINT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_extint_group.
+ * QSGs are simple examples with step-by-step instructions to configure and
+ * use this driver in a selection of use cases. Note that QSGs can be compiled
+ * as a standalone application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_extint_basic_use_case
+ * \if EXTINT_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_extint_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_extint_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>12/2014</td>
+ * <td>Added support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Added additional documentation on the event system. Corrected
+ * documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,230 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include "extint.h"
+#include "extint_callback.h"
+
+/**
+ * \internal
+ * Internal driver device instance struct, declared in the main module driver.
+ */
+extern struct _extint_module _extint_dev;
+
+/**
+ * \internal
+ * This is the number of the channel whose callback is currently running
+ */
+uint8_t _current_channel;
+
+/**
+ * \brief Registers an asynchronous callback function with the driver.
+ *
+ * Registers an asynchronous callback with the EXTINT driver, fired when a
+ * channel detects the configured channel detection criteria
+ * (e.g. edge or level). Callbacks are fired once for each detected channel.
+ *
+ * \note NMI channel callbacks cannot be registered via this function; the
+ * device's NMI interrupt should be hooked directly in the user
+ * application and the NMI flags manually cleared via
+ * \ref extint_nmi_clear_detected().
+ *
+ * \param[in] callback Pointer to the callback function to register
+ * \param[in] channel Logical channel to register callback for
+ * \param[in] type Type of callback function to register
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK The callback was registered successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ * \retval STATUS_ERR_ALREADY_INITIALIZED Callback function has been
+ * registered, need unregister first
+ */
+enum status_code extint_register_callback(
+ const extint_callback_t callback,
+ const uint8_t channel,
+ const enum extint_callback_type type)
+{
+ /* Sanity check arguments */
+ Assert(callback);
+
+ if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ if (_extint_dev.callbacks[channel] == NULL) {
+ _extint_dev.callbacks[channel] = callback;
+ return STATUS_OK;
+ } else if (_extint_dev.callbacks[channel] == callback) {
+ return STATUS_OK;
+ }
+
+ return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/**
+ * \brief Unregisters an asynchronous callback function with the driver.
+ *
+ * Unregisters an asynchronous callback with the EXTINT driver, removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] callback Pointer to the callback function to unregister
+ * \param[in] channel Logical channel to unregister callback for
+ * \param[in] type Type of callback function to unregister
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK The callback was Unregistered successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ * \retval STATUS_ERR_BAD_ADDRESS No matching entry was found in the
+ * registration table
+ */
+enum status_code extint_unregister_callback(
+ const extint_callback_t callback,
+ const uint8_t channel,
+ const enum extint_callback_type type)
+{
+ /* Sanity check arguments */
+ Assert(callback);
+
+ if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ if (_extint_dev.callbacks[channel] == callback) {
+ _extint_dev.callbacks[channel] = NULL;
+ return STATUS_OK;
+ }
+
+ return STATUS_ERR_BAD_ADDRESS;
+}
+
+/**
+ * \brief Enables asynchronous callback generation for a given channel and type.
+ *
+ * Enables asynchronous callbacks for a given logical external interrupt channel
+ * and type. This must be called before an external interrupt channel will
+ * generate callback events.
+ *
+ * \param[in] channel Logical channel to enable callback generation for
+ * \param[in] type Type of callback function callbacks to enable
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ */
+enum status_code extint_chan_enable_callback(
+ const uint8_t channel,
+ const enum extint_callback_type type)
+{
+ if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+ Eic *const eic = _extint_get_eic_from_channel(channel);
+
+ eic->INTENSET.reg = (1UL << channel);
+ } else {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables asynchronous callback generation for a given channel and type.
+ *
+ * Disables asynchronous callbacks for a given logical external interrupt
+ * channel and type.
+ *
+ * \param[in] channel Logical channel to disable callback generation for
+ * \param[in] type Type of callback function callbacks to disable
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK The callback was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
+ */
+enum status_code extint_chan_disable_callback(
+ const uint8_t channel,
+ const enum extint_callback_type type)
+{
+ if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+ Eic *const eic = _extint_get_eic_from_channel(channel);
+
+ eic->INTENCLR.reg = (1UL << channel);
+ } else {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Find what channel caused the callback.
+ *
+ * Can be used in an EXTINT callback function to find what channel caused
+ * the callback in case same callback is used by multiple channels.
+ *
+ * \return Channel number.
+ */
+uint8_t extint_get_current_channel(void)
+{
+ return _current_channel;
+}
+
+/** Handler for the EXTINT hardware module interrupt. */
+void EIC_Handler(void)
+{
+ /* Find any triggered channels, run associated callback handlers */
+ for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
+ if (extint_chan_is_detected(_current_channel)) {
+ /* Clear flag */
+ extint_chan_clear_detected(_current_channel);
+ /* Find any associated callback entries in the callback table */
+ if (_extint_dev.callbacks[_current_channel] != NULL) {
+ /* Run the registered callback */
+ _extint_dev.callbacks[_current_channel]();
+ }
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,107 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef EXTINT_CALLBACK_H_INCLUDED
+#define EXTINT_CALLBACK_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_extint_group
+ *
+ * @{
+ */
+
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+
+/** Enum for the possible callback types for the EXTINT module. */
+enum extint_callback_type {
+ /** Callback type for when an external interrupt detects the configured
+ * channel criteria (i.e. edge or level detection)
+ */
+ EXTINT_CALLBACK_TYPE_DETECT,
+};
+
+enum status_code extint_register_callback(
+ const extint_callback_t callback,
+ const uint8_t channel,
+ const enum extint_callback_type type);
+
+enum status_code extint_unregister_callback(
+ const extint_callback_t callback,
+ const uint8_t channel,
+ const enum extint_callback_type type);
+
+uint8_t extint_get_current_channel(void);
+
+/** @} */
+
+/** \name Callback Enabling and Disabling (Channel)
+ * @{
+ */
+
+enum status_code extint_chan_enable_callback(
+ const uint8_t channel,
+ const enum extint_callback_type type);
+
+enum status_code extint_chan_disable_callback(
+ const uint8_t channel,
+ const enum extint_callback_type type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_sam_d_r/extint.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,426 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include <system.h>
+#include <system_interrupt.h>
+#include <extint.h>
+#include <conf_extint.h>
+
+#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__)
+# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0.
+
+/** Configuration option, setting the EIC clock source which can be used for
+ * EIC edge detection or filtering. This option may be overridden in the module
+ * configuration header file \c conf_extint.h.
+ */
+# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
+#endif
+
+/**
+ * \internal
+ * Internal driver device instance struct.
+ */
+struct _extint_module _extint_dev;
+
+/**
+ * \brief Determin if the general clock is required
+ *
+ * \param[in] filter_input_signal Filter the raw input signal to prevent noise
+ * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect)
+ */
+#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
+ ((filter_input_signal) ? true : (\
+ (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
+ (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
+ (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
+
+static void _extint_enable(void);
+static void _extint_disable(void);
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool extint_is_syncing(void)
+{
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+ if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) {
+ return true;
+ }
+ }
+ return false;
+}
+/**
+ * \internal
+ * \brief Initializes and enables the External Interrupt driver.
+ *
+ * Enable the clocks used by External Interrupt driver.
+ *
+ * Resets the External Interrupt driver, resetting all hardware
+ * module registers to their power-on defaults, then enable it for further use.
+ *
+ * Reset the callback list if callback mode is used.
+ *
+ * This function must be called before attempting to use any NMI or standard
+ * external interrupt channel functions.
+ *
+ * \note When SYSTEM module is used, this function will be invoked by
+ * \ref system_init() automatically if the module is included.
+ */
+void _system_extint_init(void);
+void _system_extint_init(void)
+{
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC);
+
+ /* Configure the generic clock for the module and enable it */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
+ system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
+
+ /* Enable the clock anyway, since when needed it will be requested
+ * by External Interrupt driver */
+ system_gclk_chan_enable(EIC_GCLK_ID);
+
+ /* Reset all EIC hardware modules. */
+ for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+ eics[i]->CTRL.reg |= EIC_CTRL_SWRST;
+ }
+
+ while (extint_is_syncing()) {
+ /* Wait for all hardware modules to complete synchronization */
+ }
+
+ /* Reset the software module */
+// TEMP: Commented by V
+//#if EXTINT_CALLBACK_MODE == true
+ /* Clear callback registration table */
+ for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
+ _extint_dev.callbacks[j] = NULL;
+ }
+ system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
+//#endif
+
+ /* Enables the driver for further use */
+ _extint_enable();
+}
+
+/**
+ * \internal
+ * \brief Enables the External Interrupt driver.
+ *
+ * Enables EIC modules.
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_enable(void)
+{
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ /* Enable all EIC hardware modules. */
+ for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+ eics[i]->CTRL.reg |= EIC_CTRL_ENABLE;
+ }
+
+ while (extint_is_syncing()) {
+ /* Wait for all hardware modules to complete synchronization */
+ }
+}
+
+/**
+ * \internal
+ * \brief Disables the External Interrupt driver.
+ *
+ * Disables EIC modules that were previously started via a call to
+ * \ref _extint_enable().
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_disable(void)
+{
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ /* Disable all EIC hardware modules. */
+ for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+ eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE;
+ }
+
+ while (extint_is_syncing()) {
+ /* Wait for all hardware modules to complete synchronization */
+ }
+}
+
+/**
+ * \brief Initializes an External Interrupt channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt channel configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Wake the device if an edge detection occurs whilst in sleep
+ * \li Input filtering disabled
+ * \li Internal pull-up enabled
+ * \li Detect falling edges of a signal
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+void extint_chan_get_config_defaults(
+ struct extint_chan_conf *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->gpio_pin = 0;
+ config->gpio_pin_mux = 0;
+ config->gpio_pin_pull = EXTINT_PULL_UP;
+ config->wake_if_sleeping = true;
+ config->filter_input_signal = false;
+ config->detection_criteria = EXTINT_DETECT_FALLING;
+}
+
+/**
+ * \brief Writes an External Interrupt channel configuration to the hardware module.
+ *
+ * Writes out a given configuration of an External Interrupt channel
+ * configuration to the hardware module. If the channel is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] channel External Interrupt channel to configure
+ * \param[in] config Configuration settings for the channel
+
+ */
+void extint_chan_set_config(
+ const uint8_t channel,
+ const struct extint_chan_conf *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+ /* Sanity check clock requirements */
+ Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+ _extint_is_gclk_required(config->filter_input_signal,
+ config->detection_criteria)));
+
+ struct system_pinmux_config pinmux_config;
+ system_pinmux_get_config_defaults(&pinmux_config);
+
+ pinmux_config.mux_position = config->gpio_pin_mux;
+ pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+ system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+ /* Get a pointer to the module hardware instance */
+ Eic *const EIC_module = _extint_get_eic_from_channel(channel);
+
+ uint32_t config_pos = (4 * (channel % 8));
+ uint32_t new_config;
+
+ /* Determine the channel's new edge detection configuration */
+ new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
+
+ /* Enable the hardware signal filter if requested in the config */
+ if (config->filter_input_signal) {
+ new_config |= EIC_CONFIG_FILTEN0;
+ }
+
+ /* Clear the existing and set the new channel configuration */
+ EIC_module->CONFIG[channel / 8].reg
+ = (EIC_module->CONFIG[channel / 8].reg &
+ ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
+ (new_config << config_pos);
+
+ /* Set the channel's new wake up mode setting */
+ if (config->wake_if_sleeping) {
+ EIC_module->WAKEUP.reg |= (1UL << channel);
+ } else {
+ EIC_module->WAKEUP.reg &= ~(1UL << channel);
+ }
+}
+
+/**
+ * \brief Writes an External Interrupt NMI channel configuration to the hardware module.
+ *
+ * Writes out a given configuration of an External Interrupt NMI channel
+ * configuration to the hardware module. If the channel is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] nmi_channel External Interrupt NMI channel to configure
+ * \param[in] config Configuration settings for the channel
+ *
+ * \returns Status code indicating the success or failure of the request.
+ * \retval STATUS_OK Configuration succeeded
+ * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pinmux value was supplied
+ * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested
+ */
+enum status_code extint_nmi_set_config(
+ const uint8_t nmi_channel,
+ const struct extint_nmi_conf *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+ /* Sanity check clock requirements */
+ Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+ _extint_is_gclk_required(config->filter_input_signal,
+ config->detection_criteria)));
+
+ struct system_pinmux_config pinmux_config;
+ system_pinmux_get_config_defaults(&pinmux_config);
+
+ pinmux_config.mux_position = config->gpio_pin_mux;
+ pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+ system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+ /* Get a pointer to the module hardware instance */
+ Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
+
+ uint32_t new_config;
+
+ /* Determine the NMI's new edge detection configuration */
+ new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
+
+ /* Enable the hardware signal filter if requested in the config */
+ if (config->filter_input_signal) {
+ new_config |= EIC_NMICTRL_NMIFILTEN;
+ }
+
+ /* Disable EIC and general clock to configure NMI */
+ _extint_disable();
+ system_gclk_chan_disable(EIC_GCLK_ID);
+
+ EIC_module->NMICTRL.reg = new_config;
+
+ /* Enable the general clock and EIC after configure NMI */
+ system_gclk_chan_enable(EIC_GCLK_ID);
+ _extint_enable();
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Enables an External Interrupt event output.
+ *
+ * Enables one or more output events from the External Interrupt module. See
+ * \ref extint_events "here" for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in] events Struct containing flags of events to enable
+ */
+void extint_enable_events(
+ struct extint_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(events);
+
+ /* Array of available EICs. */
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ /* Update the event control register for each physical EIC instance */
+ for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+ uint32_t event_mask = 0;
+
+ /* Create an enable mask for the current EIC module */
+ for (uint32_t j = 0; j < 32; j++) {
+ if (events->generate_event_on_detect[(32 * i) + j]) {
+ event_mask |= (1UL << j);
+ }
+ }
+
+ /* Enable the masked events */
+ eics[i]->EVCTRL.reg |= event_mask;
+ }
+}
+
+/**
+ * \brief Disables an External Interrupt event output.
+ *
+ * Disables one or more output events from the External Interrupt module. See
+ * \ref extint_events "here" for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in] events Struct containing flags of events to disable
+ */
+void extint_disable_events(
+ struct extint_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(events);
+
+ /* Array of available EICs. */
+ Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+ /* Update the event control register for each physical EIC instance */
+ for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+ uint32_t event_mask = 0;
+
+ /* Create a disable mask for the current EIC module */
+ for (uint32_t j = 0; j < 32; j++) {
+ if (events->generate_event_on_detect[(32 * i) + j]) {
+ event_mask |= (1UL << j);
+ }
+ }
+
+ /* Disable the masked events */
+ eics[i]->EVCTRL.reg &= ~event_mask;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include <port.h>
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] config Configuration settings for the pin
+ */
+void port_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct port_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ struct system_pinmux_config pinmux_config;
+ system_pinmux_get_config_defaults(&pinmux_config);
+
+ pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+ pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
+ pinmux_config.powersave = config->powersave;
+
+ system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+}
+
+/**
+ * \brief Writes a Port group configuration group to the hardware module.
+ *
+ * Writes out a given configuration of a Port group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[out] port Base of the PORT module to write to
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] config Configuration settings for the pin group
+ */
+void port_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct port_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(port);
+ Assert(config);
+
+ struct system_pinmux_config pinmux_config;
+ system_pinmux_get_config_defaults(&pinmux_config);
+
+ pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+ pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
+ pinmux_config.powersave = config->powersave;
+
+ system_pinmux_group_set_config(port, mask, &pinmux_config);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,790 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef PORT_H_INCLUDED
+#define PORT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_port_group SAM Port Driver (PORT)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the device's General Purpose Input/Output (GPIO) pin
+ * functionality, for manual pin state reading and writing.
+ *
+ * The following peripherals are used by this module:
+ * - PORT (GPIO Management)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_port_prerequisites
+ * - \ref asfdoc_sam0_port_module_overview
+ * - \ref asfdoc_sam0_port_special_considerations
+ * - \ref asfdoc_sam0_port_extra_info
+ * - \ref asfdoc_sam0_port_examples
+ * - \ref asfdoc_sam0_port_api_overview
+ *
+ *
+ * \section asfdoc_sam0_port_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_port_module_overview Module Overview
+ *
+ * The device GPIO (PORT) module provides an interface between the user
+ * application logic and external hardware peripherals, when general pin state
+ * manipulation is required. This driver provides an easy-to-use interface to
+ * the physical pin input samplers and output drivers, so that pins can be read
+ * from or written to for general purpose external hardware control.
+ *
+ * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_PORT_INPUT_EVENT</td>
+ * <td>SAML21</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
+ * this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_port_module_int_connections
+ * \dot
+ * digraph overview {
+ * node [label="Port Pad" shape=square] pad;
+ *
+ * subgraph driver {
+ * node [label="Peripheral MUX" shape=trapezium] pinmux;
+ * node [label="GPIO Module" shape=ellipse] gpio;
+ * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ * }
+ *
+ * pinmux -> gpio;
+ * pad -> pinmux;
+ * pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_port_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampler can be disabled when the pin is configured
+ * in pure output mode to save power; reading the pin state of a pin configured
+ * in output-only mode will read the logical output state that was last set.
+ *
+ * \section asfdoc_sam0_port_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_port_extra. This includes:
+ * - \ref asfdoc_sam0_port_extra_acronyms
+ * - \ref asfdoc_sam0_port_extra_dependencies
+ * - \ref asfdoc_sam0_port_extra_errata
+ * - \ref asfdoc_sam0_port_extra_history
+ *
+ *
+ * \section asfdoc_sam0_port_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_port_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_port_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define port features set according to different device family.
+ * @{
+*/
+#if (SAML21) || defined(__DOXYGEN__)
+/** Event input control feature support for PORT group. */
+# define FEATURE_PORT_INPUT_EVENT
+#endif
+/*@}*/
+
+/** \name PORT Alias Macros
+ * @{
+ */
+
+/** Convenience definition for GPIO module group A on the device (if
+ * available). */
+#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
+# define PORTA PORT->Group[0]
+#endif
+
+#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group B on the device (if
+ * available). */
+# define PORTB PORT->Group[1]
+#endif
+
+#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group C on the device (if
+ * available). */
+# define PORTC PORT->Group[2]
+#endif
+
+#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group D on the device (if
+ * available). */
+# define PORTD PORT->Group[3]
+#endif
+
+/** @} */
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum port_pin_dir {
+ /** The pin's input buffer should be enabled, so that the pin state can
+ * be read. */
+ PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT,
+ /** The pin's output buffer should be enabled, so that the pin state can
+ * be set. */
+ PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+ /** The pin's output and input buffers should be enabled, so that the pin
+ * state can be set and read back. */
+ PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum port_pin_pull {
+ /** No logical pull should be applied to the pin. */
+ PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+ /** Pin should be pulled up when idle. */
+ PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
+ /** Pin should be pulled down when idle. */
+ PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+/**
+ * \brief Port input event action.
+ *
+ * List of port input events action on pin.
+ */
+enum port_input_event_action {
+ /** Event out to pin. */
+ PORT_INPUT_EVENT_ACTION_OUT = 0,
+ /** Set output register of pin on event. */
+ PORT_INPUT_EVENT_ACTION_SET,
+ /** Clear output register pin on event. */
+ PORT_INPUT_EVENT_ACTION_CLR,
+ /** Toggle output register pin on event. */
+ PORT_INPUT_EVENT_ACTION_TGL,
+};
+
+/**
+ * \brief Port input event.
+ *
+ * List of port input events.
+ */
+enum port_input_event {
+ /** Port input event 0. */
+ PORT_INPUT_EVENT_0 = 0,
+ /** Port input event 1. */
+ PORT_INPUT_EVENT_1 = 1,
+ /** Port input event 2. */
+ PORT_INPUT_EVENT_2 = 2,
+ /** Port input event 3. */
+ PORT_INPUT_EVENT_3 = 3,
+};
+
+/**
+ * \brief Port input event configuration structure.
+ *
+ * Configuration structure for a port input event.
+ */
+struct port_input_event_config {
+ /** PPort input event action. */
+ enum port_input_event_action action;
+ /** GPIO pin. */
+ uint8_t gpio_pin;
+};
+#endif
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should be
+ * initialized by the \ref port_get_config_defaults() function before being
+ * modified by the user application.
+ */
+struct port_config {
+ /** Port buffer input/output direction. */
+ enum port_pin_dir direction;
+
+ /** Port pull-up/pull-down for input pins. */
+ enum port_pin_pull input_pull;
+
+ /** Enable lowest possible powerstate on the pin
+ *
+ * \note All other configurations will be ignored, the pin will be disabled.
+ */
+ bool powersave;
+};
+
+/** \name State Reading/Writing (Physical Group Orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to convert
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* port_get_group_from_gpio_pin(
+ const uint8_t gpio_pin)
+{
+ return system_pinmux_get_group_from_gpio_pin(gpio_pin);
+}
+
+/**
+ * \brief Retrieves the state of a group of port pins that are configured as inputs.
+ *
+ * Reads the current logic level of a port module's pins and returns the
+ * current levels as a bitmask.
+ *
+ * \param[in] port Base of the PORT module to read from
+ * \param[in] mask Mask of the port pin(s) to read
+ *
+ * \return Status of the port pin(s) input buffers.
+ */
+static inline uint32_t port_group_get_input_level(
+ const PortGroup *const port,
+ const uint32_t mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ return (port->IN.reg & mask);
+}
+
+/**
+ * \brief Retrieves the state of a group of port pins that are configured as outputs.
+ *
+ * Reads the current logical output level of a port module's pins and returns
+ * the current levels as a bitmask.
+ *
+ * \param[in] port Base of the PORT module to read from
+ * \param[in] mask Mask of the port pin(s) to read
+ *
+ * \return Status of the port pin(s) output buffers.
+ */
+static inline uint32_t port_group_get_output_level(
+ const PortGroup *const port,
+ const uint32_t mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ return (port->OUT.reg & mask);
+}
+
+/**
+ * \brief Sets the state of a group of port pins that are configured as outputs.
+ *
+ * Sets the current output level of a port module's pins to a given logic
+ * level.
+ *
+ * \param[out] port Base of the PORT module to write to
+ * \param[in] mask Mask of the port pin(s) to change
+ * \param[in] level_mask Mask of the port level(s) to set
+ */
+static inline void port_group_set_output_level(
+ PortGroup *const port,
+ const uint32_t mask,
+ const uint32_t level_mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ port->OUTSET.reg = (mask & level_mask);
+ port->OUTCLR.reg = (mask & ~level_mask);
+}
+
+/**
+ * \brief Toggles the state of a group of port pins that are configured as an outputs.
+ *
+ * Toggles the current output levels of a port module's pins.
+ *
+ * \param[out] port Base of the PORT module to write to
+ * \param[in] mask Mask of the port pin(s) to toggle
+ */
+static inline void port_group_toggle_output_level(
+ PortGroup *const port,
+ const uint32_t mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ port->OUTTGL.reg = mask;
+}
+
+/** @} */
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin/group configuration structure to defaults.
+ *
+ * Initializes a given Port pin/group configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input mode with internal pullup enabled
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void port_get_config_defaults(
+ struct port_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->direction = PORT_PIN_DIR_INPUT;
+ config->input_pull = PORT_PIN_PULL_UP;
+ config->powersave = false;
+}
+
+void port_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct port_config *const config);
+
+void port_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct port_config *const config);
+
+/** @} */
+
+/** \name State Reading/Writing (Logical Pin Orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the state of a port pin that is configured as an input.
+ *
+ * Reads the current logic level of a port pin and returns the current
+ * level as a Boolean value.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to read
+ *
+ * \return Status of the port pin's input buffer.
+ */
+static inline bool port_pin_get_input_level(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ return (port_base->IN.reg & pin_mask);
+}
+
+/**
+ * \brief Retrieves the state of a port pin that is configured as an output.
+ *
+ * Reads the current logical output level of a port pin and returns the current
+ * level as a Boolean value.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to read
+ *
+ * \return Status of the port pin's output buffer.
+ */
+static inline bool port_pin_get_output_level(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ return (port_base->OUT.reg & pin_mask);
+}
+
+/**
+ * \brief Sets the state of a port pin that is configured as an output.
+ *
+ * Sets the current output level of a port pin to a given logic level.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to write to
+ * \param[in] level Logical level to set the given pin to
+ */
+static inline void port_pin_set_output_level(
+ const uint8_t gpio_pin,
+ const bool level)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ /* Set the pin to high or low atomically based on the requested level */
+ if (level) {
+ port_base->OUTSET.reg = pin_mask;
+ } else {
+ port_base->OUTCLR.reg = pin_mask;
+ }
+}
+
+/**
+ * \brief Toggles the state of a port pin that is configured as an output.
+ *
+ * Toggles the current output level of a port pin.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to toggle
+ */
+static inline void port_pin_toggle_output_level(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ /* Toggle pin output level */
+ port_base->OUTTGL.reg = pin_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+
+/** \name Port Input Event
+ * @{
+ */
+
+/**
+ * \brief Enable the port event input.
+ *
+ * Enable the port event input with the given pin and event.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin
+ * \param[in] n Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid parameter
+ * \retval STATUS_OK Successfully
+ */
+static inline enum status_code port_enable_input_event(
+ const uint8_t gpio_pin,
+ const enum port_input_event n)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ switch (n) {
+ case PORT_INPUT_EVENT_0:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+ break;
+ case PORT_INPUT_EVENT_1:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+ break;
+ case PORT_INPUT_EVENT_2:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+ break;
+ case PORT_INPUT_EVENT_3:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+ break;
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disable the port event input.
+ *
+ * Disable the port event input with the given pin and event.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin
+ * \param[in] gpio_pin Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid parameter
+ * \retval STATUS_OK Successfully
+ */
+static inline enum status_code port_disable_input_event(
+ const uint8_t gpio_pin,
+ const enum port_input_event n)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ switch (n) {
+ case PORT_INPUT_EVENT_0:
+ port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+ break;
+ case PORT_INPUT_EVENT_1:
+ port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+ break;
+ case PORT_INPUT_EVENT_2:
+ port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+ break;
+ case PORT_INPUT_EVENT_3:
+ port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+ break;
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Retrieve the default configuration for port input event.
+ *
+ * Fills a configuration structure with the default configuration for port input event:
+ * - Event output to pin
+ * - Event action to be executed on PIN 0
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void port_input_event_get_config_defaults(
+ struct port_input_event_config *const config)
+{
+ Assert(config);
+ config->action = PORT_INPUT_EVENT_ACTION_OUT;
+ config->gpio_pin = 0;
+}
+
+/**
+ * \brief Configure port input event.
+ *
+ * Configures port input event with the given configuration settings.
+ *
+ * \param[in] config Port input even configuration structure containing the new config
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid parameter
+ * \retval STATUS_OK Successfully
+ */
+
+static inline enum status_code port_input_event_set_config(
+ const enum port_input_event n,
+ struct port_input_event_config *const config)
+{
+ Assert(config);
+ PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
+ uint8_t pin_index = config->gpio_pin % 32;
+ struct port_config pin_conf;
+
+ port_get_config_defaults(&pin_conf);
+ /* Configure the GPIO pin as outputs*/
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+ port_pin_set_config(config->gpio_pin, &pin_conf);
+
+ switch (n) {
+ case PORT_INPUT_EVENT_0:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+ | PORT_EVCTRL_PID0(pin_index);
+ break;
+ case PORT_INPUT_EVENT_1:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+ | PORT_EVCTRL_PID0(pin_index);
+ break;
+ case PORT_INPUT_EVENT_2:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+ | PORT_EVCTRL_PID0(pin_index);
+ break;
+ case PORT_INPUT_EVENT_3:
+ port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+ | PORT_EVCTRL_PID0(pin_index);
+ break;
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+ return STATUS_OK;
+}
+
+/** @} */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_port_extra Extra Information for PORT Driver
+ *
+ * \section asfdoc_sam0_port_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>GPIO</td>
+ * <td>General Purpose Input/Output</td>
+ * </tr>
+ * <tr>
+ * <td>MUX</td>
+ * <td>Multiplexer</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_port_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_port_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_port_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Added input event feature and support for SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_port_exqsg Examples for PORT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_port_basic_use_case
+ *
+ * \page asfdoc_sam0_port_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>11/2014</td>
+ * <td>Added input event feature and support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/quick_start/qs_port_basic.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,108 @@ +/** + * \file + * + * \brief SAM GPIO Port Driver Quick Start + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic + * + * In this use case, the PORT module is configured for: + * \li One pin in input mode, with pull-up enabled + * \li One pin in output mode + * + * This use case sets up the PORT to read the current state of a GPIO pin set as + * an input, and mirrors the opposite logical state on a pin configured as an + * output. + * + * \section asfdoc_sam0_port_basic_use_case_setup Setup + * + * \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites + * There are no special setup requirements for this use-case. + * + * \subsection asfdoc_sam0_port_basic_use_case_setup_code Code + * Copy-paste the following setup code to your user application: + * \snippet qs_port_basic.c setup + * + * Add to user application initialization (typically the start of \c main()): + * \snippet qs_port_basic.c setup_init + * + * \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow + * -# Create a PORT module pin configuration struct, which can be filled out to + * adjust the configuration of a single port pin. + * \snippet qs_port_basic.c setup_1 + * -# Initialize the pin configuration struct with the module's default values. + * \snippet qs_port_basic.c setup_2 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Adjust the configuration struct to request an input pin. + * \snippet qs_port_basic.c setup_3 + * -# Configure push button pin with the initialized pin configuration struct, to enable + * the input sampler on the pin. + * \snippet qs_port_basic.c setup_4 + * -# Adjust the configuration struct to request an output pin. + * \snippet qs_port_basic.c setup_5 + * \note The existing configuration struct may be re-used, as long as any + * values that have been altered from the default settings are taken + * into account by the user application. + * + * -# Configure LED pin with the initialized pin configuration struct, to enable + * the output driver on the pin. + * \snippet qs_port_basic.c setup_6 + * + * \section asfdoc_sam0_port_basic_use_case_use_main Use Case + * + * \subsection asfdoc_sam0_port_basic_use_case_code Code + * Copy-paste the following code to your user application: + * \snippet qs_port_basic.c main + * + * \subsection asfdoc_sam0_port_basic_use_case_flow Workflow + * -# Read in the current input sampler state of push button pin, which has been + * configured as an input in the use-case setup code. + * \snippet qs_port_basic.c main_1 + * -# Write the inverted pin level state to LED pin, which has been configured as + * an output in the use-case setup code. + * \snippet qs_port_basic.c main_2 + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_calendar.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1254 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Mode)
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef RTC_CALENDAR_H_INCLUDED
+#define RTC_CALENDAR_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_rtc_calendar_group SAM RTC Calendar Driver (RTC CAL)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the device's Real Time Clock functionality in Calendar
+ * operating mode, for the configuration and retrieval of the current time and
+ * date as maintained by the RTC module. The following driver API modes are
+ * covered by this manual:
+ *
+ * - Polled APIs
+ * \if RTC_CALENDAR_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ * - RTC (Real Time Clock)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_rtc_calendar_prerequisites
+ * - \ref asfdoc_sam0_rtc_calendar_module_overview
+ * - \ref asfdoc_sam0_rtc_calendar_special_considerations
+ * - \ref asfdoc_sam0_rtc_calendar_extra_info
+ * - \ref asfdoc_sam0_rtc_calendar_examples
+ * - \ref asfdoc_sam0_rtc_calendar_api_overview
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_module_overview Module Overview
+ *
+ * The RTC module in the SAM devices is a 32-bit counter, with a 10-bit
+ * programmable prescaler. Typically, the RTC clock is run continuously,
+ * including in the device's low-power sleep modes, to track the current time
+ * and date information. The RTC can be used as a source to wake up the system
+ * at a scheduled time or periodically using the alarm functions.
+ *
+ * In this driver, the RTC is operated in Calendar mode. This allows for an
+ * easy integration of a real time clock and calendar into a user application
+ * to track the passing of time and/or perform scheduled tasks.
+ *
+ * Whilst operating in Calendar mode, the RTC features:
+ * - Time tracking in seconds, minutes, and hours
+ * - 12 or 24 hour mode
+ * - Date tracking in day, month, and year
+ * - Automatic leap year correction
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_RTC_PERIODIC_INT</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_RTC_PRESCALER_OFF</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_RTC_CLOCK_SELECTION</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_RTC_GENERAL_PURPOSE_REG</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_RTC_CONTINUOUSLY_UPDATED</td>
+ * <td>SAMD20, SAMD21, SAMR21, SAMD10, SAMD11</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_module_overview_alarms Alarms and Overflow
+ * The RTC has four independent hardware alarms that can be configured by the user
+ * application. These alarms will be will triggered on match with the current
+ * clock value, and can be set up to trigger an interrupt, event, or both. The
+ * RTC can also be configured to clear the clock value on alarm match, resetting
+ * the clock to the original start time.
+ *
+ * If the RTC is operated in clock-only mode (i.e. with calendar disabled), the
+ * RTC counter value will instead be cleared on overflow once the maximum count
+ * value has been reached:
+ *
+ * \f[ COUNT_{MAX} = 2^{32}-1 \f]
+ *
+ * When the RTC is operated with the calendar enabled and run using a nominal
+ * 1Hz input clock frequency, a register overflow will occur after 64 years.
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_module_overview_periodic Periodic Events
+ * The RTC can generate events at periodic intervals, allowing for direct
+ * peripheral actions without CPU intervention. The periodic events can be
+ * generated on the upper eight bits of the RTC prescaler, and will be generated on
+ * the rising edge transition of the specified bit. The resulting periodic
+ * frequency can be calculated by the following formula:
+ *
+ * \f[ f_{PERIODIC}=\frac{f_{ASY}}{2^{n+3}} \f]
+ *
+ * Where \f$f_{ASY}\f$ refers to the \e asynchronous clock set up in the RTC
+ * module configuration. For the RTC to operate correctly in calendar mode, this
+ * frequency must be 1KHz, while the RTC's internal prescaler should be set to
+ * divide by 1024. The \b n parameter is the event source generator index of the
+ * RTC module. If the asynchronous clock is operated at the recommended 1KHz,
+ * the formula results in the values shown in
+ * \ref asfdoc_sam0_rtc_calendar_module_rtc_hz "the table below".
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_module_rtc_hz
+ * <table>
+ * <caption>RTC Event Frequencies for Each Prescaler Bit Using a 1KHz Clock</caption>
+ * <tr>
+ * <th>n</th> <th>Periodic event</th>
+ * </tr>
+ * <tr>
+ * <td>7</td> <td>1Hz</td>
+ * </tr>
+ * <tr>
+ * <td>6</td> <td>2Hz</td>
+ * </tr>
+ * <tr>
+ * <td>5</td> <td>4Hz</td>
+ * </tr>
+ * <tr>
+ * <td>4</td> <td>8Hz</td>
+ * </tr>
+ * <tr>
+ * <td>3</td> <td>16Hz</td>
+ * </tr>
+ * <tr>
+ * <td>2</td> <td>32Hz</td>
+ * </tr>
+ * <tr>
+ * <td>1</td> <td>64Hz</td>
+ * </tr>
+ * <tr>
+ * <td>0</td> <td>128Hz</td>
+ * </tr>
+ * </table>
+ *
+ * \note The connection of events between modules requires the use of the
+ * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ * to route output event of one module to the the input event of another.
+ * For more information on event routing, refer to the event driver
+ * documentation.
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_module_overview_correction Digital Frequency Correction
+ * The RTC module contains Digital Frequency Correction logic to compensate for
+ * inaccurate source clock frequencies which would otherwise result in skewed
+ * time measurements. The correction scheme requires that at least two bits
+ * in the RTC module prescaler are reserved by the correction logic. As a
+ * result of this implementation, frequency correction is only available when
+ * the RTC is running from a 1Hz reference clock.
+ *
+ * The correction procedure is implemented by subtracting or adding a single
+ * cycle from the RTC prescaler every 1024 RTC GCLK cycles. The adjustment is
+ * applied the specified number of time (maximum 127) over 976 of these periods. The
+ * corresponding correction in PPM will be given by:
+ *
+ * \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f]
+ *
+ * The RTC clock will tick faster if provided with a positive correction value,
+ * and slower when given a negative correction value.
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_special_considerations_year Year Limit
+ * The RTC module has a year range of 63 years from the starting year configured
+ * when the module is initialized. Dates outside the start to end year range
+ * described below will need software adjustment:
+ *
+ * \f[ [YEAR_{START}, YEAR_{START}+64) \f]
+ *
+ * \subsection asfdoc_sam0_rtc_calendar_special_considerations_clock Clock Setup
+ * \subsubsection asfdoc_sam0_rtc_calendar_clock_samd_r SAM D20/D21/R21/D10/D11 Clock Setup
+ * The RTC is typically clocked by a specialized GCLK generator that has a
+ * smaller prescaler than the others. By default the RTC clock is on, selected
+ * to use the internal 32KHz RC-oscillator with a prescaler of 32, giving a
+ * resulting clock frequency of 1024Hz to the RTC. When the internal RTC
+ * prescaler is set to 1024, this yields an end-frequency of 1Hz for correct
+ * time keeping operations.
+ *
+ * The implementer also has the option to set other end-frequencies.
+ * \ref asfdoc_sam0_rtc_calendar_rtc_out_freq "The table below" lists the
+ * available RTC frequencies for each possible GCLK and RTC input prescaler
+ * options.
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_rtc_out_freq
+ * <table>
+ * <caption>RTC Output Frequencies from Allowable Input Clocks</caption>
+ * <tr>
+ * <th>End-frequency</th>
+ * <th>GCLK prescaler</th>
+ * <th>RTC prescaler</th>
+ * </tr>
+ * <tr>
+ * <td>32KHz</td>
+ * <td>1</td>
+ * <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>1KHz</td>
+ * <td>32</td>
+ * <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>1Hz</td>
+ * <td>32</td>
+ * <td>1024</td>
+ * </tr>
+ * </table>
+ *
+ * The overall RTC module clocking scheme is shown in
+ * \ref asfdoc_sam0_rtc_calendar_rtc_clock_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_rtc_clock_fig
+ * \dot
+ * digraph clocking_scheme {
+ * rankdir=LR;
+ * GCLK [shape="record", label="<f0> GCLK | <f1> RTC_GCLK",
+ * bgcolor="lightgray", style="filled"];
+ * RTCPRE [shape="record" label="<f0> RTC | <f1> RTC PRESCALER"];
+ * RTC [shape="record", label="<f0> RTC | <f1> RTC CLOCK"];
+ *
+ * GCLK:f1 -> RTCPRE:f1;
+ * RTCPRE:f1 -> RTC:f1;
+ * }
+ * \enddot
+ *
+ * \note For the calendar to operate correctly, an asynchronous clock of 1Hz
+ * should be used.
+ *
+ * \subsubsection asfdoc_sam0_rtc_calendar_clock_saml SAM L21 Clock Setup
+ * The RTC clock can be selected from OSC32K,XOSC32K or OSCULP32K , and a 32KHz
+ * or 1KHz oscillator clock frequency is required. This clock must be
+ * configured and enabled in the 32KHz oscillator controller before using the RTC.
+ *
+ * The table below lists the available RTC clock \ref asfdoc_sam0_rtc_calendar_rtc_clk
+ *
+ * \anchor asfdoc_sam0_rtc_calendar_rtc_clk
+ * <table>
+ * <caption>RTC clocks source</caption>
+ * <tr>
+ * <th>RTC clock frequency</th>
+ * <th>Clock source</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>1.024KHz</td>
+ * <td>ULP1K</td>
+ * <td>1.024KHz from 32KHz internal ULP oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>32.768KHz</td>
+ * <td>ULP32K</td>
+ * <td>32.768KHz from 32KHz internal ULP oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>1.024KHz</td>
+ * <td>OSC1K</td>
+ * <td>1.024KHz from 32KHz internal oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>32.768KHz</td>
+ * <td>OSC32K</td>
+ * <td>32.768KHz from 32KHz internal oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>1.024KHz</td>
+ * <td>XOSC1K</td>
+ * <td>1.024KHz from 32KHz internal oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>32.768KHz</td>
+ * <td>XOSC32K</td>
+ * <td>32.768KHz from 32KHz external crystal oscillator</td>
+ * </tr>
+ * </table>
+ *
+ * \note For the calendar to operate correctly, an asynchronous clock of 1Hz
+ * should be used.
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_rtc_calendar_extra. This includes:
+ * - \ref asfdoc_sam0_rtc_calendar_extra_acronyms
+ * - \ref asfdoc_sam0_rtc_calendar_extra_dependencies
+ * - \ref asfdoc_sam0_rtc_calendar_extra_errata
+ * - \ref asfdoc_sam0_rtc_calendar_extra_history
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_rtc_calendar_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_api_overview API Overview
+ * @{
+ */
+
+#include <conf_clocks.h>
+
+#if RTC_CALENDAR_ASYNC == true
+# include <system_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Define port features set according to different device family
+ * @{
+*/
+#if (SAML21) || defined(__DOXYGEN__)
+/** RTC periodic interval interrupt. */
+# define FEATURE_RTC_PERIODIC_INT
+/** RTC prescaler is off. */
+# define FEATURE_RTC_PRESCALER_OFF
+/** RTC clock selection. */
+# define FEATURE_RTC_CLOCK_SELECTION
+/** General purpose registers. */
+# define FEATURE_RTC_GENERAL_PURPOSE_REG
+#else
+/** RTC continuously updated. */
+# define FEATURE_RTC_CONTINUOUSLY_UPDATED
+#endif
+/*@}*/
+
+#ifdef FEATURE_RTC_CLOCK_SELECTION
+/**
+ * \brief Available clock source for RTC.
+ * RTC clock source.
+ */
+enum rtc_clock_sel {
+ /** 1.024KHz from 32KHz internal ULP oscillator. */
+ RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val,
+ /** 32.768KHz from 32KHz internal ULP oscillator. */
+ RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val,
+ /** 1.024KHz from 32KHz internal oscillator. */
+ RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val,
+ /** 32.768KHz from 32KHz internal oscillator. */
+ RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val,
+ /** 1.024KHz from 32KHz internal oscillator. */
+ RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val,
+ /** 32.768KHz from 32.768KHz external crystal oscillator. */
+ RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val,
+};
+#endif
+
+#if !defined (RTC_NUM_OF_ALARMS) && defined(RTC_ALARM_NUM)
+#define RTC_NUM_OF_ALARMS RTC_ALARM_NUM
+#endif
+
+/**
+ * \brief Available alarm channels.
+ *
+ * Available alarm channels.
+ *
+ * \note Not all alarm channels are available on all devices.
+ */
+enum rtc_calendar_alarm {
+ /** Alarm channel 0. */
+ RTC_CALENDAR_ALARM_0 = 0,
+#if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+ /** Alarm channel 1. */
+ RTC_CALENDAR_ALARM_1 = 1,
+#endif
+#if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+ /** Alarm channel 2. */
+ RTC_CALENDAR_ALARM_2 = 2,
+#endif
+#if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+ /** Alarm channel 3. */
+ RTC_CALENDAR_ALARM_3 = 3,
+#endif
+};
+
+#if RTC_CALENDAR_ASYNC == true
+#ifdef FEATURE_RTC_PERIODIC_INT
+/**
+ * \brief Callback types.
+ *
+ * The available callback types for the RTC calendar module.
+ */
+enum rtc_calendar_callback {
+ /** Callback for Periodic Interval 0 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0 = 0,
+ /** Callback for Periodic Interval 1 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_1,
+ /** Callback for Periodic Interval 2 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_2,
+ /** Callback for Periodic Interval 3 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_3,
+ /** Callback for Periodic Interval 4 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_4,
+ /** Callback for Periodic Interval 5 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_5,
+ /** Callback for Periodic Interval 6 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_6,
+ /** Callback for Periodic Interval 7 Interrupt. */
+ RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7,
+ /** Callback for alarm 0. */
+ RTC_CALENDAR_CALLBACK_ALARM_0,
+# if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+ /** Callback for alarm 1. */
+ RTC_CALENDAR_CALLBACK_ALARM_1,
+# endif
+# if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+ /** Callback for alarm 2. */
+ RTC_CALENDAR_CALLBACK_ALARM_2,
+# endif
+# if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+ /** Callback for alarm 3. */
+ RTC_CALENDAR_CALLBACK_ALARM_3,
+# endif
+ /** Callback for overflow. */
+ RTC_CALENDAR_CALLBACK_OVERFLOW,
+# if !defined(__DOXYGEN__)
+ /** Total number of callbacks. */
+ _RTC_CALENDAR_CALLBACK_N
+# endif
+};
+#else
+/**
+ * \brief Callback types.
+ *
+ * The available callback types for the RTC calendar module.
+ */
+enum rtc_calendar_callback {
+ /** Callback for alarm 0. */
+ RTC_CALENDAR_CALLBACK_ALARM_0 = 0,
+# if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+ /** Callback for alarm 1. */
+ RTC_CALENDAR_CALLBACK_ALARM_1,
+# endif
+# if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+ /** Callback for alarm 2. */
+ RTC_CALENDAR_CALLBACK_ALARM_2,
+# endif
+# if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+ /** Callback for alarm 3. */
+ RTC_CALENDAR_CALLBACK_ALARM_3,
+# endif
+ /** Callback for overflow. */
+ RTC_CALENDAR_CALLBACK_OVERFLOW,
+# if !defined(__DOXYGEN__)
+ /** Total number of callbacks. */
+ _RTC_CALENDAR_CALLBACK_N
+# endif
+};
+#endif
+
+# if !defined(__DOXYGEN__)
+typedef void (*rtc_calendar_callback_t)(void);
+# endif
+#endif
+
+#ifdef FEATURE_RTC_PRESCALER_OFF
+/**
+ * \brief RTC input clock prescaler settings.
+ *
+ * The available input clock prescaler values for the RTC calendar module.
+ */
+enum rtc_calendar_prescaler {
+ /** RTC prescaler is off, and the input clock frequency is
+ prescaled by a factor of 1. */
+ RTC_CALENDAR_PRESCALER_OFF = RTC_MODE2_CTRLA_PRESCALER_OFF,
+ /** RTC input clock frequency is prescaled by a factor of 1. */
+ RTC_CALENDAR_PRESCALER_DIV_1 = RTC_MODE2_CTRLA_PRESCALER_DIV1,
+ /** RTC input clock frequency is prescaled by a factor of 2. */
+ RTC_CALENDAR_PRESCALER_DIV_2 = RTC_MODE2_CTRLA_PRESCALER_DIV2,
+ /** RTC input clock frequency is prescaled by a factor of 4. */
+ RTC_CALENDAR_PRESCALER_DIV_4 = RTC_MODE2_CTRLA_PRESCALER_DIV4,
+ /** RTC input clock frequency is prescaled by a factor of 8. */
+ RTC_CALENDAR_PRESCALER_DIV_8 = RTC_MODE2_CTRLA_PRESCALER_DIV8,
+ /** RTC input clock frequency is prescaled by a factor of 16. */
+ RTC_CALENDAR_PRESCALER_DIV_16 = RTC_MODE2_CTRLA_PRESCALER_DIV16,
+ /** RTC input clock frequency is prescaled by a factor of 32. */
+ RTC_CALENDAR_PRESCALER_DIV_32 = RTC_MODE2_CTRLA_PRESCALER_DIV32,
+ /** RTC input clock frequency is prescaled by a factor of 64. */
+ RTC_CALENDAR_PRESCALER_DIV_64 = RTC_MODE2_CTRLA_PRESCALER_DIV64,
+ /** RTC input clock frequency is prescaled by a factor of 128. */
+ RTC_CALENDAR_PRESCALER_DIV_128 = RTC_MODE2_CTRLA_PRESCALER_DIV128,
+ /** RTC input clock frequency is prescaled by a factor of 256. */
+ RTC_CALENDAR_PRESCALER_DIV_256 = RTC_MODE2_CTRLA_PRESCALER_DIV256,
+ /** RTC input clock frequency is prescaled by a factor of 512. */
+ RTC_CALENDAR_PRESCALER_DIV_512 = RTC_MODE2_CTRLA_PRESCALER_DIV512,
+ /** RTC input clock frequency is prescaled by a factor of 1024. */
+ RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRLA_PRESCALER_DIV1024,
+};
+
+#else
+/**
+ * \brief RTC input clock prescaler settings.
+ *
+ * The available input clock prescaler values for the RTC calendar module.
+ */
+enum rtc_calendar_prescaler {
+ /** RTC input clock frequency is prescaled by a factor of 1. */
+ RTC_CALENDAR_PRESCALER_DIV_1 = RTC_MODE2_CTRL_PRESCALER_DIV1,
+ /** RTC input clock frequency is prescaled by a factor of 2. */
+ RTC_CALENDAR_PRESCALER_DIV_2 = RTC_MODE2_CTRL_PRESCALER_DIV2,
+ /** RTC input clock frequency is prescaled by a factor of 4. */
+ RTC_CALENDAR_PRESCALER_DIV_4 = RTC_MODE2_CTRL_PRESCALER_DIV4,
+ /** RTC input clock frequency is prescaled by a factor of 8. */
+ RTC_CALENDAR_PRESCALER_DIV_8 = RTC_MODE2_CTRL_PRESCALER_DIV8,
+ /** RTC input clock frequency is prescaled by a factor of 16. */
+ RTC_CALENDAR_PRESCALER_DIV_16 = RTC_MODE2_CTRL_PRESCALER_DIV16,
+ /** RTC input clock frequency is prescaled by a factor of 32. */
+ RTC_CALENDAR_PRESCALER_DIV_32 = RTC_MODE2_CTRL_PRESCALER_DIV32,
+ /** RTC input clock frequency is prescaled by a factor of 64. */
+ RTC_CALENDAR_PRESCALER_DIV_64 = RTC_MODE2_CTRL_PRESCALER_DIV64,
+ /** RTC input clock frequency is prescaled by a factor of 128. */
+ RTC_CALENDAR_PRESCALER_DIV_128 = RTC_MODE2_CTRL_PRESCALER_DIV128,
+ /** RTC input clock frequency is prescaled by a factor of 256. */
+ RTC_CALENDAR_PRESCALER_DIV_256 = RTC_MODE2_CTRL_PRESCALER_DIV256,
+ /** RTC input clock frequency is prescaled by a factor of 512. */
+ RTC_CALENDAR_PRESCALER_DIV_512 = RTC_MODE2_CTRL_PRESCALER_DIV512,
+ /** RTC input clock frequency is prescaled by a factor of 1024. */
+ RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRL_PRESCALER_DIV1024,
+};
+#endif
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Device structure.
+ */
+struct rtc_module {
+ /** RTC hardware module. */
+ Rtc *hw;
+ /** If clock mode 24h. */
+ bool clock_24h;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+ /** If continuously update clock register. */
+ bool continuously_update;
+#endif
+ /** Initial year for counter value 0. */
+ uint16_t year_init_value;
+# if RTC_CALENDAR_ASYNC == true
+ /** Pointers to callback functions. */
+ volatile rtc_calendar_callback_t callbacks[_RTC_CALENDAR_CALLBACK_N];
+ /** Mask for registered callbacks. */
+ volatile uint16_t registered_callback;
+ /** Mask for enabled callbacks. */
+ volatile uint16_t enabled_callback;
+# endif
+};
+#endif
+
+/**
+ * \brief Available mask options for alarms.
+ *
+ * Available mask options for alarms.
+ */
+enum rtc_calendar_alarm_mask {
+ /** Alarm disabled. */
+ RTC_CALENDAR_ALARM_MASK_DISABLED = RTC_MODE2_MASK_SEL_OFF,
+ /** Alarm match on second. */
+ RTC_CALENDAR_ALARM_MASK_SEC = RTC_MODE2_MASK_SEL_SS,
+ /** Alarm match on second and minute. */
+ RTC_CALENDAR_ALARM_MASK_MIN = RTC_MODE2_MASK_SEL_MMSS,
+ /** Alarm match on second, minute, and hour. */
+ RTC_CALENDAR_ALARM_MASK_HOUR = RTC_MODE2_MASK_SEL_HHMMSS,
+ /** Alarm match on second, minute, hour, and day. */
+ RTC_CALENDAR_ALARM_MASK_DAY = RTC_MODE2_MASK_SEL_DDHHMMSS,
+ /** Alarm match on second, minute, hour, day, and month. */
+ RTC_CALENDAR_ALARM_MASK_MONTH = RTC_MODE2_MASK_SEL_MMDDHHMMSS,
+ /** Alarm match on second, minute, hour, day, month, and year. */
+ RTC_CALENDAR_ALARM_MASK_YEAR = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS,
+};
+
+/**
+ * \brief RTC Calendar event enable/disable structure.
+ *
+ * Event flags for the \ref rtc_calendar_enable_events() and
+ * \ref rtc_calendar_disable_events().
+ */
+struct rtc_calendar_events {
+ /** Generate an output event on each overflow of the RTC count. */
+ bool generate_event_on_overflow;
+ /** Generate an output event on a alarm channel match against the RTC
+ * count. */
+ bool generate_event_on_alarm[RTC_NUM_OF_ALARMS];
+ /** Generate an output event periodically at a binary division of the RTC
+ * counter frequency.
+ */
+ bool generate_event_on_periodic[8];
+};
+
+/**
+ * \brief Time structure.
+ *
+ * Time structure containing the time given by or set to the RTC calendar.
+ * The structure uses seven values to give second, minute, hour, PM/AM, day,
+ * month, and year. It should be initialized via the
+ * \ref rtc_calendar_get_time_defaults() function before use.
+ */
+struct rtc_calendar_time {
+ /** Second value. */
+ uint8_t second;
+ /** Minute value. */
+ uint8_t minute;
+ /** Hour value. */
+ uint8_t hour;
+ /** PM/AM value, \c true for PM, or \c false for AM. */
+ bool pm;
+ /** Day value, where day 1 is the first day of the month. */
+ uint8_t day;
+ /** Month value, where month 1 is January. */
+ uint8_t month;
+ /** Year value.*/
+ uint16_t year;
+};
+
+/**
+ * \brief Alarm structure.
+ *
+ * Alarm structure containing time of the alarm and a mask to determine when
+ * the alarm will trigger.
+ */
+struct rtc_calendar_alarm_time {
+ /** Alarm time. */
+ struct rtc_calendar_time time;
+ /** Alarm mask to determine on what precision the alarm will match. */
+ enum rtc_calendar_alarm_mask mask;
+};
+
+/**
+ * \brief RTC configuration structure.
+ *
+ * Configuration structure for the RTC instance. This structure should
+ * be initialized using the \ref rtc_calendar_get_config_defaults() before any
+ * user configurations are set.
+ */
+struct rtc_calendar_config {
+ /** Input clock prescaler for the RTC module. */
+ enum rtc_calendar_prescaler prescaler;
+ /** If \c true, clears the clock on alarm match. */
+ bool clear_on_match;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+ /** If \c true, the digital counter registers will be continuously updated
+ * so that internal synchronization is not needed when reading the current
+ * count. */
+ bool continuously_update;
+#endif
+ /** If \c true, time is represented in 24 hour mode. */
+ bool clock_24h;
+ /** Initial year for counter value 0. */
+ uint16_t year_init_value;
+ /** Alarm values. */
+ struct rtc_calendar_alarm_time alarm[RTC_NUM_OF_ALARMS];
+};
+
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initialize a \c time structure.
+ *
+ * This will initialize a given time structure to the time 00:00:00 (hh:mm:ss)
+ * and date 2000-01-01 (YYYY-MM-DD).
+ *
+ * \param[out] time Time structure to initialize
+ */
+static inline void rtc_calendar_get_time_defaults(
+ struct rtc_calendar_time *const time)
+{
+ time->second = 0;
+ time->minute = 0;
+ time->hour = 0;
+ time->pm = 0;
+ time->day = 1;
+ time->month = 1;
+ time->year = 2000;
+}
+
+/**
+ * \brief Gets the RTC default settings.
+ *
+ * Initializes the configuration structure to the known default values. This
+ * function should be called at the start of any RTC initiation.
+ *
+ * The default configuration is as follows:
+ * - Input clock divided by a factor of 1024
+ * - Clear on alarm match off
+ * - Continuously sync clock off
+ * - 12 hour calendar
+ * - Start year 2000 (Year 0 in the counter will be year 2000)
+ * - Events off
+ * - Alarms set to January 1. 2000, 00:00:00
+ * - Alarm will match on second, minute, hour, day, month, and year
+ *
+ * \param[out] config Configuration structure to be initialized to default
+ * values.
+ */
+static inline void rtc_calendar_get_config_defaults(
+ struct rtc_calendar_config *const config)
+{
+ /* Sanity check argument */
+ Assert(config);
+
+ /* Initialize and set time structure to default. */
+ struct rtc_calendar_time time;
+ rtc_calendar_get_time_defaults(&time);
+
+ /* Set defaults into configuration structure */
+ config->prescaler = RTC_CALENDAR_PRESCALER_DIV_1024;
+ config->clear_on_match = false;
+#ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
+ config->continuously_update = false;
+#endif
+ config->clock_24h = false;
+ config->year_init_value = 2000;
+ for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+ config->alarm[i].time = time;
+ config->alarm[i].mask = RTC_CALENDAR_ALARM_MASK_YEAR;
+ }
+}
+
+void rtc_calendar_reset(struct rtc_module *const module);
+void rtc_calendar_enable(struct rtc_module *const module);
+void rtc_calendar_disable(struct rtc_module *const module);
+
+#if (RTC_INST_NUM > 1) && !defined(__DOXYGEN__)
+/**
+ * \internal Find the index of given RTC module instance.
+ *
+ * \param[in] hw RTC module instance pointer
+ *
+ * \return Index of the given RTC module instance.
+ */
+uint8_t _rtc_get_inst_index(
+ Rtc *const hw)
+{
+ /* List of available RTC modules. */
+ static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
+
+ /* Find index for RTC instance. */
+ for (uint32_t i = 0; i < RTC_INST_NUM; i++) {
+ if (hw == rtc_modules[i]) {
+ return i;
+ }
+ }
+
+ /* Invalid data given. */
+ Assert(false);
+ return 0;
+}
+#endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */
+
+void rtc_calendar_init(
+ struct rtc_module *const module,
+ Rtc *const hw,
+ const struct rtc_calendar_config *const config);
+
+void rtc_calendar_swap_time_mode(struct rtc_module *const module);
+
+enum status_code rtc_calendar_frequency_correction(
+ struct rtc_module *const module,
+ const int8_t value);
+
+/** @} */
+
+
+/** \name Time and Alarm Management
+ * @{
+ */
+
+void rtc_calendar_set_time(
+ struct rtc_module *const module,
+ const struct rtc_calendar_time *const time);
+
+void rtc_calendar_get_time(
+ struct rtc_module *const module,
+ struct rtc_calendar_time *const time);
+
+enum status_code rtc_calendar_set_alarm(
+ struct rtc_module *const module,
+ const struct rtc_calendar_alarm_time *const alarm,
+ const enum rtc_calendar_alarm alarm_index);
+
+enum status_code rtc_calendar_get_alarm(
+ struct rtc_module *const module,
+ struct rtc_calendar_alarm_time *const alarm,
+ const enum rtc_calendar_alarm alarm_index);
+
+/** @} */
+
+
+/** \name Status Flag Management
+ * @{
+ */
+
+/**
+ * \brief Check if an RTC overflow has occurred.
+ *
+ * Checks the overflow flag in the RTC. The flag is set when there
+ * is an overflow in the clock.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ *
+ * \return Overflow state of the RTC module.
+ *
+ * \retval true If the RTC count value has overflowed
+ * \retval false If the RTC count value has not overflowed
+ */
+static inline bool rtc_calendar_is_overflow(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Return status of flag. */
+ return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF);
+}
+
+/**
+ * \brief Clears the RTC overflow flag.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ *
+ * Clears the RTC module counter overflow flag, so that new overflow conditions
+ * can be detected.
+ */
+static inline void rtc_calendar_clear_overflow(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Clear flag. */
+ rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+/**
+ * \brief Check the RTC alarm flag.
+ *
+ * Check if the specified alarm flag is set. The flag is set when there
+ * is an compare match between the alarm value and the clock.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] alarm_index Index of the alarm to check
+ *
+ * \returns Match status of the specified alarm.
+ *
+ * \retval true If the specified alarm has matched the current time
+ * \retval false If the specified alarm has not matched the current time
+ */
+static inline bool rtc_calendar_is_alarm_match(
+ struct rtc_module *const module,
+ const enum rtc_calendar_alarm alarm_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Sanity check. */
+ if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+ Assert(false);
+ return false;
+ }
+
+ /* Return int flag status. */
+ return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(1 << alarm_index));
+}
+
+/**
+ * \brief Clears the RTC alarm match flag.
+ *
+ * Clear the requested alarm match flag, so that future alarm matches can be
+ * determined.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] alarm_index The index of the alarm match to clear
+ *
+ * \return Status of the alarm match clear operation.
+ *
+ * \retval STATUS_OK If flag was cleared correctly
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided
+ */
+static inline enum status_code rtc_calendar_clear_alarm_match(
+ struct rtc_module *const module,
+ const enum rtc_calendar_alarm alarm_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Sanity check. */
+ if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Clear flag. */
+ rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << alarm_index);
+
+ return STATUS_OK;
+}
+
+/** @} */
+
+
+/**
+ * \name Event Management
+ * @{
+ */
+
+/**
+ * \brief Enables a RTC event output.
+ *
+ * Enables one or more output events from the RTC module. See
+ * \ref rtc_calendar_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] events Struct containing flags of events to enable
+ */
+static inline void rtc_calendar_enable_events(
+ struct rtc_module *const module,
+ struct rtc_calendar_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ uint32_t event_mask = 0;
+
+ /* Check if the user has requested an overflow event. */
+ if (events->generate_event_on_overflow) {
+ event_mask |= RTC_MODE2_EVCTRL_OVFEO;
+ }
+
+ /* Check if the user has requested any alarm events. */
+ for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+ if (events->generate_event_on_alarm[i]) {
+ event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
+ }
+ }
+
+ /* Check if the user has requested any periodic events. */
+ for (uint8_t i = 0; i < 8; i++) {
+ if (events->generate_event_on_periodic[i]) {
+ event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
+ }
+ }
+
+ /* Enable given event(s). */
+ rtc_module->MODE2.EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables a RTC event output.
+ *
+ * Disabled one or more output events from the RTC module. See
+ * \ref rtc_calendar_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] events Struct containing flags of events to disable
+ */
+static inline void rtc_calendar_disable_events(
+ struct rtc_module *const module,
+ struct rtc_calendar_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ uint32_t event_mask = 0;
+
+ /* Check if the user has requested an overflow event. */
+ if (events->generate_event_on_overflow) {
+ event_mask |= RTC_MODE2_EVCTRL_OVFEO;
+ }
+
+ /* Check if the user has requested any alarm events. */
+ for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+ if (events->generate_event_on_alarm[i]) {
+ event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
+ }
+ }
+
+ /* Check if the user has requested any periodic events. */
+ for (uint8_t i = 0; i < 8; i++) {
+ if (events->generate_event_on_periodic[i]) {
+ event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
+ }
+ }
+
+ /* Disable given event(s). */
+ rtc_module->MODE2.EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_RTC_GENERAL_PURPOSE_REG
+/**
+ * \name RTC General Purpose Registers
+ * @{
+ */
+
+/**
+ * \brief Write a value into general purpose register.
+ *
+ * \param[in] module Pointer to the software instance struct
+ * \param[in] n General purpose type
+ * \param[in] index General purpose register index (0..3)
+ *
+ */
+static inline void rtc_write_general_purpose_reg(
+ struct rtc_module *const module,
+ const uint8_t index,
+ uint32_t value)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+ Assert(index <= 3);
+
+ Rtc *const rtc_module = module->hw;
+
+ rtc_module->MODE0.GP[index].reg = value;
+}
+
+/**
+ * \brief Read the value from general purpose register.
+ *
+ * \param[in] module Pointer to the software instance struct
+ * \param[in] index General purpose register index (0..3)
+ *
+ * \retval Value of general purpose register
+ */
+static inline uint32_t rtc_read_general_purpose_reg(
+ struct rtc_module *const module,
+ const uint8_t index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+ Assert(index <= 3);
+
+ Rtc *const rtc_module = module->hw;
+
+ return rtc_module->MODE0.GP[index].reg;
+}
+
+/** @} */
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page asfdoc_sam0_rtc_calendar_extra Extra Information for RTC (CAL) Driver
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</td>
+ * <th>Description</td>
+ * </tr>
+ * <tr>
+ * <td>RTC</td>
+ * <td>Real Time Counter</td>
+ * </tr>
+ * <tr>
+ * <td>PPM</td>
+ * <td>Part Per Million</td>
+ * </tr>
+ * <tr>
+ * <td>RC</td>
+ * <td>Resistor/Capacitor</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_rtc_calendar_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>
+ * Added support for SAMD21 and added driver instance parameter to all
+ * API function calls, except get_config_defaults
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Updated initialization function to also enable the digital interface
+ * clock to the module if it is disabled</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_rtc_calendar_exqsg Examples for RTC CAL Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_rtc_calendar_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that QSGs can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_rtc_calendar_basic_use_case
+ * \if RTC_CALENDAR_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_rtc_calendar_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_rtc_calendar_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>11/2014</td>
+ * <td>Added support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Added additional documentation on the event system. Corrected
+ * documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif /* RTC_CALENDAR_H_INCLUDED */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_sam_d_r/rtc_calendar.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,653 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Calendar Mode)
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include "rtc_calendar.h"
+#include <gclk.h>
+
+#if !defined(__DOXYGEN__)
+struct rtc_module *_rtc_instance[RTC_INST_NUM];
+#endif
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module RTC hardware module
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module has completed synchronization
+ * \retval false if the module synchronization is ongoing
+ */
+static inline bool rtc_calendar_is_syncing(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ if (rtc_module->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) {
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * \brief Enables the RTC module.
+ *
+ * Enables the RTC module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ */
+void rtc_calendar_enable(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+#if RTC_CALENDAR_ASYNC == true
+ system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+ while (rtc_calendar_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Enable RTC module. */
+ rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE;
+}
+
+/**
+ * \brief Disables the RTC module.
+ *
+ * Disables the RTC module.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ */
+void rtc_calendar_disable(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+#if RTC_CALENDAR_ASYNC == true
+ system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+ while (rtc_calendar_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Disable RTC module. */
+ rtc_module->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE;
+}
+
+/**
+ * \brief Resets the RTC module
+ * Resets the RTC module to hardware defaults.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ */
+void rtc_calendar_reset(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Disable module before reset. */
+ rtc_calendar_disable(module);
+
+#if RTC_CALENDAR_ASYNC == true
+ module->registered_callback = 0;
+ module->enabled_callback = 0;
+#endif
+
+ while (rtc_calendar_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Initiate software reset. */
+ rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST;
+}
+
+/**
+ * \internal Convert time structure to register_value.
+ */
+static uint32_t _rtc_calendar_time_to_register_value(
+ struct rtc_module *const module,
+ const struct rtc_calendar_time *const time)
+{
+ /* Initialize return value. */
+ uint32_t register_value;
+
+ /* Set year value into register_value minus initial year. */
+ register_value = (time->year - module->year_init_value) <<
+ RTC_MODE2_CLOCK_YEAR_Pos;
+
+ /* Set month value into register_value. */
+ register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos);
+
+ /* Set day value into register_value. */
+ register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos);
+
+ /* Set 24 hour value into register_value. */
+ register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos);
+
+ /* Check if 24 h clock and set pm flag. */
+ if (!(module->clock_24h) && (time->pm)) {
+ /* Set pm flag. */
+ register_value |= RTC_MODE2_CLOCK_HOUR_PM;
+ }
+
+ /* Set minute value into register_value. */
+ register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos);
+
+ /* Set second value into register_value. */
+ register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos);
+
+ return register_value;
+}
+
+/**
+ * \internal Convert register_value to time structure.
+ */
+static void _rtc_calendar_register_value_to_time(
+ struct rtc_module *const module,
+ const uint32_t register_value,
+ struct rtc_calendar_time *const time)
+{
+ /* Set year plus value of initial year. */
+ time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >>
+ RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value;
+
+ /* Set month value into time struct. */
+ time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >>
+ RTC_MODE2_CLOCK_MONTH_Pos);
+
+ /* Set day value into time struct. */
+ time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >>
+ RTC_MODE2_CLOCK_DAY_Pos);
+
+ if (module->clock_24h) {
+ /* Set hour in 24h mode. */
+ time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >>
+ RTC_MODE2_CLOCK_HOUR_Pos);
+ } else {
+ /* Set hour in 12h mode. */
+ time->hour = ((register_value &
+ (RTC_MODE2_CLOCK_HOUR_Msk & ~RTC_MODE2_CLOCK_HOUR_PM)) >>
+ RTC_MODE2_CLOCK_HOUR_Pos);
+
+ /* Set pm flag */
+ time->pm = ((register_value & RTC_MODE2_CLOCK_HOUR_PM) != 0);
+ }
+
+ /* Set minute value into time struct. */
+ time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >>
+ RTC_MODE2_CLOCK_MINUTE_Pos);
+
+ /* Set second value into time struct. */
+ time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >>
+ RTC_MODE2_CLOCK_SECOND_Pos);
+}
+
+/**
+ * \internal Applies the given configuration.
+ *
+ * Set the configurations given from the configuration structure to the
+ * hardware module.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] config Pointer to the configuration structure.
+ */
+static void _rtc_calendar_set_config(
+ struct rtc_module *const module,
+ const struct rtc_calendar_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Set up temporary register value. */
+ uint16_t tmp_reg;
+
+ /* Set to calendar mode and set the prescaler. */
+ tmp_reg = RTC_MODE2_CTRL_MODE(2) | config->prescaler;
+
+ /* Check clock mode. */
+ if (!(config->clock_24h)) {
+ /* Set clock mode 12h. */
+ tmp_reg |= RTC_MODE2_CTRL_CLKREP;
+ }
+
+ /* Check for clear on compare match. */
+ if (config->clear_on_match) {
+ /* Set clear on compare match. */
+ tmp_reg |= RTC_MODE2_CTRL_MATCHCLR;
+ }
+
+ /* Set temporary value to register. */
+ rtc_module->MODE2.CTRL.reg = tmp_reg;
+
+ /* Check to set continuously clock read update mode. */
+ if (config->continuously_update) {
+ /* Set continuously mode. */
+ rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT;
+ }
+
+ /* Set alarm time registers. */
+ for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+ rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i);
+ }
+}
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ *
+ * Initializes the module, setting up all given configurations to provide
+ * the desired functionality of the RTC.
+ *
+ * \param[out] module Pointer to the software instance struct
+ * \param[in] hw Pointer to hardware instance
+ * \param[in] config Pointer to the configuration structure.
+ */
+void rtc_calendar_init(
+ struct rtc_module *const module,
+ Rtc *const hw,
+ const struct rtc_calendar_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(hw);
+ Assert(config);
+
+ /* Initialize device instance */
+ module->hw = hw;
+
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
+
+ /* Set up GCLK */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
+ system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
+ system_gclk_chan_enable(RTC_GCLK_ID);
+
+ /* Reset module to hardware defaults. */
+ rtc_calendar_reset(module);
+
+ /* Save conf_struct internally for continued use. */
+ module->clock_24h = config->clock_24h;
+ module->continuously_update = config->continuously_update;
+ module->year_init_value = config->year_init_value;
+
+#if (RTC_INST_NUM == 1)
+ _rtc_instance[0] = module;
+#else
+ /* Register this instance for callbacks*/
+ _rtc_instance[_rtc_get_inst_index(hw)] = module;
+#endif
+
+ /* Set config. */
+ _rtc_calendar_set_config(module, config);
+}
+
+/**
+ * \brief Swaps between 12h and 24h clock mode.
+ *
+ * Swaps the current RTC time mode:
+ * - If currently in 12h mode, it will swap to 24h
+ * - If currently in 24h mode, it will swap to 12h
+ *
+ * \note This will not change setting in user's configuration structure.
+ *
+ * \param[in, out] module Pointer to the software instance struct
+ */
+void rtc_calendar_swap_time_mode(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Initialize time structure. */
+ struct rtc_calendar_time time;
+ struct rtc_calendar_alarm_time alarm;
+
+ /* Get current time. */
+ rtc_calendar_get_time(module, &time);
+
+ /* Check current mode. */
+ if (module->clock_24h) {
+ /* Set pm flag. */
+ time.pm = (uint8_t)(time.hour / 12);
+
+ /* Set 12h clock hour value. */
+ time.hour = time.hour % 12;
+ if (time.hour == 0) {
+ time.hour = 12;
+ }
+
+ /* Update alarms */
+ for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+ rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+ alarm.time.pm = (uint8_t)(alarm.time.hour / 12);
+ alarm.time.hour = alarm.time.hour % 12;
+ if (alarm.time.hour == 0) {
+ alarm.time.hour = 12;
+ }
+ module->clock_24h = false;
+ rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+ module->clock_24h = true;
+ }
+
+ /* Change value in configuration structure. */
+ module->clock_24h = false;
+ } else {
+ /* Set hour value based on pm flag. */
+ if (time.pm == 1) {
+ time.hour = time.hour + 12;
+
+ time.pm = 0;
+ } else if (time.hour == 12) {
+ time.hour = 0;
+ }
+
+ /* Update alarms */
+ for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
+ rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+ if (alarm.time.pm == 1) {
+ alarm.time.hour = alarm.time.hour + 12;
+ alarm.time.pm = 0;
+ module->clock_24h = true;
+ rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+ module->clock_24h = false;
+ } else if (alarm.time.hour == 12) {
+ alarm.time.hour = 0;
+ }
+ }
+
+ /* Change value in configuration structure. */
+ module->clock_24h = true;
+ }
+
+ /* Disable RTC so new configuration can be set. */
+ rtc_calendar_disable(module);
+
+ /* Toggle mode. */
+ rtc_module->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP;
+
+ /* Enable RTC. */
+ rtc_calendar_enable(module);
+
+ /* Set new time format in CLOCK register. */
+ rtc_calendar_set_time(module, &time);
+}
+
+/**
+ * \brief Set the current calendar time to desired time.
+ *
+ * Sets the time provided to the calendar.
+ *
+ * \param[in, out] module Pointer to the software instance struct
+ * \param[in] time The time to set in the calendar.
+ */
+void rtc_calendar_set_time(
+ struct rtc_module *const module,
+ const struct rtc_calendar_time *const time)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ uint32_t register_value = _rtc_calendar_time_to_register_value(module, time);
+
+ while (rtc_calendar_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Write value to register. */
+ rtc_module->MODE2.CLOCK.reg = register_value;
+}
+
+/**
+ * \brief Get the current calendar value.
+ *
+ * Retrieves the current time of the calendar.
+ *
+ * \param[in, out] module Pointer to the software instance struct
+ * \param[out] time Pointer to value that will be filled with current time.
+ */
+void rtc_calendar_get_time(
+ struct rtc_module *const module,
+ struct rtc_calendar_time *const time)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Change of read method based on value of continuously_update value in
+ * the configuration structure. */
+ if (!(module->continuously_update)) {
+ /* Request read on CLOCK register. */
+ rtc_module->MODE2.READREQ.reg = RTC_READREQ_RREQ;
+
+ while (rtc_calendar_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+ }
+
+ /* Read value. */
+ uint32_t register_value = rtc_module->MODE2.CLOCK.reg;
+
+ /* Convert value to time structure. */
+ _rtc_calendar_register_value_to_time(module, register_value, time);
+}
+
+/**
+ * \brief Set the alarm time for the specified alarm.
+ *
+ * Sets the time and mask specified to the requested alarm.
+ *
+ * \param[in, out] module Pointer to the software instance struct
+ * \param[in] alarm The alarm struct to set the alarm with.
+ * \param[in] alarm_index The index of the alarm to set.
+ *
+ * \return Status of setting alarm.
+ * \retval STATUS_OK If alarm was set correctly.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ */
+enum status_code rtc_calendar_set_alarm(
+ struct rtc_module *const module,
+ const struct rtc_calendar_alarm_time *const alarm,
+ const enum rtc_calendar_alarm alarm_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Sanity check. */
+ if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Get register_value from time. */
+ uint32_t register_value = _rtc_calendar_time_to_register_value(module, &(alarm->time));
+
+ while (rtc_calendar_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set alarm value. */
+ rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value;
+
+ /* Set alarm mask */
+ rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Get the current alarm time of specified alarm.
+ *
+ * Retrieves the current alarm time for the alarm specified.
+ *
+ * \param[in, out] module Pointer to the software instance struct
+ * \param[out] alarm Pointer to the struct that will be filled with alarm
+ * time and mask of the specified alarm.
+ * \param[in] alarm_index Index of alarm to get alarm time from.
+ *
+ * \return Status of getting alarm.
+ * \retval STATUS_OK If alarm was read correctly.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ */
+enum status_code rtc_calendar_get_alarm(
+ struct rtc_module *const module,
+ struct rtc_calendar_alarm_time *const alarm,
+ const enum rtc_calendar_alarm alarm_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Sanity check. */
+ if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Read alarm value. */
+ uint32_t register_value =
+ rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg;
+
+ /* Convert to time structure. */
+ _rtc_calendar_register_value_to_time(module, register_value, &(alarm->time));
+
+ /* Read alarm mask */
+ alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Calibrate for too-slow or too-fast oscillator.
+ *
+ * When used, the RTC will compensate for an inaccurate oscillator. The
+ * RTC module will add or subtract cycles from the RTC prescaler to adjust the
+ * frequency in approximately 1 PPM steps. The provided correction value should
+ * be between -127 and 127, allowing for a maximum 127 PPM correction in either
+ * direction.
+ *
+ * If no correction is needed, set value to zero.
+ *
+ * \note Can only be used when the RTC is operated at 1Hz.
+ *
+ * \param[in, out] module Pointer to the software instance struct
+ * \param[in] value Between -127 and 127 used for the correction.
+ *
+ * \return Status of the calibration procedure.
+ * \retval STATUS_OK If calibration was done correctly.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ */
+enum status_code rtc_calendar_frequency_correction(
+ struct rtc_module *const module,
+ const int8_t value)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Check if valid argument. */
+ if (abs(value) > 0x7F) {
+ /* Value bigger than allowed, return invalid argument. */
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ uint32_t new_correction_value;
+
+ /* Load the new correction value as a positive value, sign added later */
+ new_correction_value = abs(value);
+
+ /* Convert to positive value and adjust register sign bit. */
+ if (value < 0) {
+ new_correction_value |= RTC_FREQCORR_SIGN;
+ }
+
+ while (rtc_calendar_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set value. */
+ rtc_module->MODE2.FREQCORR.reg = new_correction_value;
+
+ return STATUS_OK;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_common.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Common Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef I2C_COMMON_H_INCLUDED
+#define I2C_COMMON_H_INCLUDED
+
+#include <compiler.h>
+#include <sercom.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \if (I2C_MASTER_MODE && I2C_SLAVE_MODE)
+ * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Driver (SERCOM I2C)
+ * \elseif I2C_MASTER_MODE
+ * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Master Mode Driver (SERCOM I2C)
+ * \elseif I2C_SLAVE_MODE
+ * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Slave Mode Driver (SERCOM I2C)
+ * \endif
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the device's SERCOM I<SUP>2</SUP>C module, for the transfer
+ * of data via an I<SUP>2</SUP>C bus. The following driver API modes are covered
+ * by this manual:
+ *
+ * \if I2C_MASTER_MODE
+ * - Master Mode Polled APIs
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - Master Mode Callback APIs
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - Slave Mode Polled APIs
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - Slave Mode Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_i2c_prerequisites
+ * - \ref asfdoc_sam0_sercom_i2c_overview
+ * - \ref asfdoc_sam0_sercom_i2c_special_considerations
+ * - \ref asfdoc_sam0_sercom_i2c_extra
+ * - \ref asfdoc_sam0_sercom_i2c_examples
+ * - \ref asfdoc_sam0_sercom_i2c_api_overview
+ *
+ * \section asfdoc_sam0_sercom_i2c_prerequisites Prerequisites
+ * There are no prerequisites.
+ *
+ * \section asfdoc_sam0_sercom_i2c_overview Module Overview
+ * The outline of this section is as follows:
+ * - \ref asfdoc_sam0_sercom_i2c_module_features
+ * - \ref asfdoc_sam0_sercom_i2c_functional_desc
+ * - \ref asfdoc_sam0_sercom_i2c_bus_topology
+ * - \ref asfdoc_sam0_sercom_i2c_transactions
+ * - \ref asfdoc_sam0_sercom_i2c_multi_master
+ * - \ref asfdoc_sam0_sercom_i2c_bus_states
+ * - \ref asfdoc_sam0_sercom_i2c_timeout
+ * - \ref asfdoc_sam0_sercom_i2c_sleep_modes
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_I2C_10_BIT_ADDRESS</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_I2C_SCL_STRETCH_MODE</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_I2C_SCL_EXTEND_TIMEOUT</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_functional_desc Functional Description
+ * The I<SUP>2</SUP>C provides a simple two-wire bidirectional bus consisting of a
+ * wired-AND type serial clock line (SCL) and a wired-AND type serial data line
+ * (SDA).
+ *
+ * The I<SUP>2</SUP>C bus provides a simple, but efficient method of interconnecting
+ * multiple master and slave devices. An arbitration mechanism is provided for
+ * resolving bus ownership between masters, as only one master device may own
+ * the bus at any given time. The arbitration mechanism relies on the wired-AND
+ * connections to avoid bus drivers short-circuiting.
+ *
+ * A unique address is assigned to all slave devices connected to the bus. A
+ * device can contain both master and slave logic, and can emulate multiple
+ * slave devices by responding to more than one address.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_bus_topology Bus Topology
+ * The I<SUP>2</SUP>C bus topology is illustrated in
+ * \ref asfdoc_sam0_sercom_i2c_bus_topology_figure "the figure below". The pull-up
+ * resistors (Rs) will provide a high level on the bus lines when none of the
+ * I<SUP>2</SUP>C devices are driving the bus. These are optional, and can be
+ * replaced with a constant current source.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_bus_topology_figure
+ * \image html bus_topology.svg "I2C Bus Topology" Width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_transactions Transactions
+ * The I<SUP>2</SUP>C standard defines three fundamental transaction formats:
+ * - Master Write
+ * - The master transmits data packets to the slave after addressing it
+ * - Master Read
+ * - The slave transmits data packets to the master after being addressed
+ * - Combined Read/Write
+ * - A combined transaction consists of several write and read transactions
+ *
+ * A data transfer starts with the master issuing a \b Start condition on the
+ * bus, followed by the address of the slave together with a bit to indicate
+ * whether the master wants to read from or write to the slave.
+ * The addressed slave must respond to this by sending an \b ACK back to the
+ * master.
+ *
+ * After this, data packets are sent from the master or slave, according to the
+ * read/write bit. Each packet must be acknowledged (ACK) or not
+ * acknowledged (NACK) by the receiver.
+ *
+ * If a slave responds with a NACK, the master must assume that the slave
+ * cannot receive any more data and cancel the write operation.
+ *
+ * The master completes a transaction by issuing a \b Stop condition.
+ *
+ * A master can issue multiple \b Start conditions during a transaction; this
+ * is then called a \b Repeated \b Start condition.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_address_packets Address Packets
+ * The slave address consists of seven bits. The 8<SUP>th</SUP> bit in the transfer
+ * determines the data direction (read or write). An address packet always
+ * succeeds a \b Start or \b Repeated \b Start condition. The 8<SUP>th</SUP> bit is handled
+ * in the driver, and the user will only have to provide the 7-bit address.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_data_packets Data Packets
+ * Data packets are nine bits long, consisting of one 8-bit data byte, and an
+ * acknowledgement bit. Data packets follow either an address packet or another
+ * data packet on the bus.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_trans_examples Transaction Examples
+ * The gray bits in the following examples are sent from master to slave, and
+ * the white bits are sent from slave to master.
+ * Example of a read transaction is shown in
+ * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_read "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the direction flag set to read is then sent and
+ * acknowledged by the slave. Then the slave sends one data packet which is
+ * acknowledged by the master. The slave sends another packet, which is not
+ * acknowledged by the master and indicates that the master will terminate the
+ * transaction. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_read
+ * \image html i2c_read.svg "I2C Packet Read" Width=100%
+ *
+ * Example of a write transaction is shown in
+ * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_write "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the dir flag set to write is then sent and acknowledged
+ * by the slave. Then the master sends two data packets, each acknowledged by
+ * the slave. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_write
+ * \image html i2c_write.svg "I2C Packet Write" Width=100%
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_packet_timeout Packet Timeout
+ * When a master sends an I<SUP>2</SUP>C packet, there is no way of
+ * being sure that a slave will acknowledge the packet. To avoid stalling the
+ * device forever while waiting for an acknowledge, a user selectable timeout
+ * is provided in the \ref i2c_master_config struct which
+ * lets the driver exit a read or write operation after the specified time.
+ * The function will then return the STATUS_ERR_TIMEOUT flag.
+ *
+ * This is also the case for the slave when using the functions postfixed
+ * \c _wait.
+ *
+ * The time before the timeout occurs, will be the same as
+ * for \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "unknown bus state" timeout.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_repeated_start Repeated Start
+ * To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be
+ * used.
+ * These functions will not send a \b Stop condition when the transfer is done,
+ * thus the next transfer will start with a \b Repeated \b Start. To end the
+ * transaction, the functions without the \c _no_stop postfix must be used
+ * for the last read/write.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_multi_master Multi Master
+ * In a multi master environment, arbitration of the bus is important, as only
+ * one master can own the bus at any point.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_arbitration Arbitration
+ *
+ * \par Clock stretching
+ * The serial clock line is always driven by a master device. However, all
+ * devices connected to the bus are allowed stretch the low period of the clock
+ * to slow down the overall clock frequency or to insert wait states while
+ * processing data.
+ * Both master and slave can randomly stretch the clock, which will force the
+ * other device into a wait-state until the clock line goes high again.
+ *
+ * \par Arbitration on the data line
+ * If two masters start transmitting at the same time, they will both transmit
+ * until one master detects that the other master is pulling the data line low.
+ * When this is detected, the master not pulling the line low, will stop the
+ * transmission and wait until the bus is idle.
+ * As it is the master trying to contact the slave with the lowest address that
+ * will get the bus ownership, this will create an arbitration scheme always
+ * prioritizing the slaves with the lowest address in case of a bus collision.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_clock_sync Clock Synchronization
+ * In situations where more than one master is trying to control the bus clock
+ * line at the same time, a clock synchronization algorithm based on the same
+ * principles used for clock stretching is necessary.
+ *
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_bus_states Bus States
+ * As the I<SUP>2</SUP>C bus is limited to one transaction at the time,
+ * a master that wants to perform a bus transaction must wait until the bus is
+ * free.
+ * Because of this, it is necessary for all masters in a multi-master system to
+ * know the current status of the bus to be able to avoid conflicts and to
+ * ensure data integrity.
+ * \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start
+ * condition)
+ * \li \b OWNER If the master initiates a transaction successfully
+ * \li \b BUSY If another master is driving the bus
+ * \li \b UNKNOWN If the master has recently been enabled or connected to
+ * the bus. Is forced to \b IDLE after given
+ * \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" when
+ * the master module is enabled.
+ *
+ * The bus state diagram can be seen in
+ * \ref asfdoc_sam0_sercom_i2c_bus_states_figure "the figure below".
+ * \li S: Start condition
+ * \li P: Stop condition
+ * \li Sr: Repeated start condition
+ * \anchor asfdoc_sam0_sercom_i2c_bus_states_figure
+ * \image html bus_state_diagram.svg "I2C Bus State Diagram" Width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_timeout Bus Timing
+ * Inactive bus timeout for the master and SDA hold time is configurable in the
+ * drivers.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_unknown_bus_timeout Unknown Bus State Timeout
+ * When a master is enabled or connected to the bus, the bus state will be
+ * unknown until either a given timeout or a stop command has occurred. The
+ * timeout is configurable in the \ref i2c_master_config struct.
+ * The timeout time will depend on toolchain and optimization level used, as
+ * the timeout is a loop incrementing a value until it reaches the specified
+ * timeout value.
+ *
+ * \subsubsection sda_hold SDA Hold Timeout
+ * When using the I<SUP>2</SUP>C in slave mode, it will be important to
+ * set a SDA hold time which assures that the master will be able to pick up
+ * the bit sent from the slave. The SDA hold time makes sure that this is the
+ * case by holding the data line low for a given period after the negative edge
+ * on the clock.
+ *
+ * The SDA hold time is also available for the master driver, but is not a
+ * necessity.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_sleep_modes Operation in Sleep Modes
+ * The I<SUP>2</SUP>C module can operate in all sleep modes by setting
+ * the run_in_standby Boolean in the \ref i2c_master_config or
+ * \ref i2c_slave_config struct.
+ * The operation in slave and master mode is shown in
+ * \ref asfdoc_sam0_sercom_i2c_sleep_modes_table "the table below".
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_sleep_modes_table
+ * <table>
+ * <caption>I<SUP>2</SUP>C Standby Operations</caption>
+ * <tr>
+ * <th>Run in standby</th>
+ * <th>Slave</th>
+ * <th>Master</th>
+ * </tr>
+ * <tr>
+ * <td>false</td>
+ * <td>Disabled, all reception is dropped</td>
+ * <td>GCLK disabled when master is idle</td>
+ * </tr>
+ * <tr>
+ * <td>true</td>
+ * <td>Wake on address match when enabled</td>
+ * <td>GCLK enabled while in sleep modes</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_special_considerations Special Considerations
+ *
+ * \if (I2C_MASTER_CALLBACK_MODE || I2C_SLAVE_CALLBACK_MODE)
+ * \subsection asfdoc_sam0_sercom_i2c_common_interrupt Interrupt-driven Operation
+ * While an interrupt-driven operation is in progress, subsequent calls to a
+ * write or read operation will return the STATUS_BUSY flag, indicating that
+ * only one operation is allowed at any given time.
+ *
+ * To check if another transmission can be initiated, the user can either call
+ * another transfer operation, or use the
+ * \ref i2c_master_get_job_status/\ref i2c_slave_get_job_status functions
+ * depending on mode.
+ *
+ * If the user would like to get callback from operations while using the
+ * interrupt-driven driver, the callback must be registered and then enabled
+ * using the "register_callback" and "enable_callback" functions.
+ * \else
+ * There are no special considerations for this driver for the APIs listed in
+ * this document.
+ * \endif
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra Extra Information
+ * For extra information, see \ref asfdoc_sam0_sercom_i2c_extra_info_page.
+ * This includes:
+ * - \ref asfdoc_sam0_sercom_i2c_acronyms
+ * - \ref asfdoc_sam0_sercom_i2c_extra_dependencies
+ * - \ref asfdoc_sam0_sercom_i2c_extra_errata
+ * - \ref asfdoc_sam0_sercom_i2c_extra_history
+ *
+ * \section asfdoc_sam0_sercom_i2c_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_i2c_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_i2c_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name Driver Feature Definition
+ * Define SERCOM I<SUP>2</SUP>C driver features set according to different device family.
+ *
+ * \note The high speed mode and 10-bit address feature are not
+ * supported by the driver now.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) ||defined(__DOXYGEN__)
+/** Fast mode plus and high speed support. */
+# define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/** 10-bit address support. */
+# define FEATURE_I2C_10_BIT_ADDRESS
+/** SCL stretch mode support. */
+# define FEATURE_I2C_SCL_STRETCH_MODE
+/** SCL extend timeout support. */
+# define FEATURE_I2C_SCL_EXTEND_TIMEOUT
+# define FEATURE_I2C_DMA_SUPPORT
+#endif
+/*@}*/
+
+/** \brief Transfer direction
+ *
+ * For master: transfer direction or setting direction bit in address.
+ * For slave: direction of request from master.
+ */
+enum i2c_transfer_direction {
+ /** Master write operation is in progress. */
+ I2C_TRANSFER_WRITE = 0,
+ /** Master read operation is in progress. */
+ I2C_TRANSFER_READ = 1,
+};
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_extra_info_page Extra Information for SERCOM I2C Driver
+ *
+ * \section asfdoc_sam0_sercom_i2c_acronyms Acronyms
+ * \ref asfdoc_sam0_sercom_i2c_acronyms_table "Below" is a table listing the acronyms
+ * used in this module, along with their intended meanings.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_acronyms_table
+ * <table>
+ * <caption>Acronyms</caption>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>SDA</td>
+ * <td>Serial Data Line</td>
+ * </tr>
+ * <tr>
+ * <td>SCL</td>
+ * <td>Serial Clock Line</td>
+ * </tr>
+ * <tr>
+ * <td>SERCOM</td>
+ * <td>Serial Communication Interface</td>
+ * </tr>
+ * <tr>
+ * <td>DMA</td>
+ * <td>Direct Memory Access</td>
+ * </tr>
+ * </table>
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies
+ * The I<SUP>2</SUP>C driver has the following dependencies:
+ * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_history Module History
+ * \ref asfdoc_sam0_sercom_i2c_extra_history_table "Below" is an overview of the
+ * module history, detailing enhancements and fixes made to the module since
+ * its first release. The current version of this corresponds to the newest
+ * version listed in
+ * \ref asfdoc_sam0_sercom_i2c_extra_history_table "the table below".
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_extra_history_table
+ * <table>
+ * <caption>Module History</caption>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Added 10-bit addressing and high speed support in SAM D21
+ * \li Seperate structure i2c_packet into i2c_master_packet and i2c_slave packet
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Added support for SCL stretch and extended timeout hardware features in SAM D21
+ * \li Added fast mode plus support in SAM D21
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Fixed incorrect logical mask for determining if a bus error has
+ * occurred in I<SUP>2</SUP>C Slave mode
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_exqsg Examples for SERCOM I2C Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * \if I2C_MASTER_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case"
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case"
+ * - \subpage asfdoc_sam0_sercom_i2c_master_dma_use_case "Quick Start Guide for the I2C Master module - DMA Use Case"
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case"
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case"
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_dma_use_case "Quick Start Guide for the I2C Slave module - DMA Use Case"
+ * \endif
+ *
+ * \page asfdoc_sam0_sercom_i2c_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>11/2014</td>
+ * <td>Added SAM L21 support.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added 10-bit addressing and high speed support in SAM D21
+ * Added SAM R21/D10/D11 support.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added the SAM D21 to the application note.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release.</td>
+ * </tr>
+ * </table>
+ */
+
+#endif /* I2C_COMMON_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_master.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,603 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef I2C_MASTER_H_INCLUDED
+#define I2C_MASTER_H_INCLUDED
+
+#include "i2c_common.h"
+#include <sercom.h>
+#include <pinmux.h>
+
+#if I2C_MASTER_CALLBACK_MODE == true
+# include <sercom_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PINMUX_DEFAULT
+# define PINMUX_DEFAULT 0
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ *
+ * @{
+ */
+
+/**
+ * \brief I<SUP>2</SUP>C master packet for read/write
+ *
+ * Structure to be used when transferring I<SUP>2</SUP>C master packets.
+ */
+struct i2c_master_packet {
+ /** Address to slave device. */
+ uint16_t address;
+ /** Length of data array. */
+ uint16_t data_length;
+ /** Data array containing all data to be transferred. */
+ uint8_t *data;
+ /** Use 10-bit addressing. Set to false if the feature is not supported by the device. */
+ bool ten_bit_address;
+ /** Use high speed transfer. Set to false if the feature is not supported by the device. */
+ bool high_speed;
+ /** High speed mode master code (0000 1XXX), valid when high_speed is true. */
+ uint8_t hs_master_code;
+};
+
+/** \brief Interrupt flags
+ *
+ * Flags used when reading or setting interrupt flags.
+ */
+enum i2c_master_interrupt_flag {
+ /** Interrupt flag used for write. */
+ I2C_MASTER_INTERRUPT_WRITE = 0,
+ /** Interrupt flag used for read. */
+ I2C_MASTER_INTERRUPT_READ = 1,
+};
+
+/**
+ * \brief Values for hold time after start bit.
+ *
+ * Values for the possible I<SUP>2</SUP>C master mode SDA internal hold times after start
+ * bit has been sent.
+ */
+enum i2c_master_start_hold_time {
+ /** Internal SDA hold time disabled. */
+ I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0),
+ /** Internal SDA hold time 50ns - 100ns. */
+ I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1),
+ /** Internal SDA hold time 300ns - 600ns. */
+ I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2),
+ /** Internal SDA hold time 400ns - 800ns. */
+ I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3),
+};
+
+/**
+ * \ brief Values for inactive bus time-out.
+ *
+ * If the inactive bus time-out is enabled and the bus is inactive for
+ * longer than the time-out setting, the bus state logic will be set to idle.
+ */
+enum i2c_master_inactive_timeout {
+ /** Inactive bus time-out disabled. */
+ I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0),
+ /** Inactive bus time-out 5-6 SCL cycle time-out. */
+ I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1),
+ /** Inactive bus time-out 10-11 SCL cycle time-out. */
+ I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2),
+ /** Inactive bus time-out 20-21 SCL cycle time-out. */
+ I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3),
+};
+
+/**
+ * \brief I<SUP>2</SUP>C frequencies
+ *
+ * Values for I<SUP>2</SUP>C speeds supported by the module. The driver
+ * will also support setting any other value, in which case set
+ * the value in the \ref i2c_master_config at desired value divided by 1000.
+ *
+ * Example: If 10KHz operation is required, give baud_rate in the configuration
+ * structure the value 10.
+ */
+enum i2c_master_baud_rate {
+ /** Baud rate at 100KHz (Standard-mode). */
+ I2C_MASTER_BAUD_RATE_100KHZ = 100,
+ /** Baud rate at 400KHz (Fast-mode). */
+ I2C_MASTER_BAUD_RATE_400KHZ = 400,
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+ /** Baud rate at 1MHz (Fast-mode Plus). */
+ I2C_MASTER_BAUD_RATE_1000KHZ = 1000,
+ /** Baud rate at 3.4MHz (High-speed mode). */
+ I2C_MASTER_BAUD_RATE_3400KHZ = 3400,
+#endif
+};
+
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/**
+ * \brief Enum for the transfer speed
+ *
+ * Enum for the transfer speed.
+ */
+enum i2c_master_transfer_speed {
+ /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */
+ I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0),
+ /** Fast-mode Plus (Fm+) up to 1MHz. */
+ I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1),
+ /** High-speed mode (Hs-mode) up to 3.4MHz. */
+ I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2),
+};
+#endif
+
+#if I2C_MASTER_CALLBACK_MODE == true
+/**
+ * \brief Callback types
+ *
+ * The available callback types for the I<SUP>2</SUP>C master module.
+ */
+enum i2c_master_callback {
+ /** Callback for packet write complete. */
+ I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
+ /** Callback for packet read complete. */
+ I2C_MASTER_CALLBACK_READ_COMPLETE = 1,
+ /** Callback for error. */
+ I2C_MASTER_CALLBACK_ERROR = 2,
+# if !defined(__DOXYGEN__)
+ /** Total number of callbacks. */
+ _I2C_MASTER_CALLBACK_N = 3,
+# endif
+};
+
+# if !defined(__DOXYGEN__)
+/* Prototype for software module. */
+struct i2c_master_module;
+
+typedef void (*i2c_master_callback_t)(
+ struct i2c_master_module *const module);
+# endif
+#endif
+
+/**
+ * \brief SERCOM I<SUP>2</SUP>C Master driver software device instance structure.
+ *
+ * SERCOM I<SUP>2</SUP>C Master driver software instance structure, used to
+ * retain software state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ * application; they are reserved for module-internal use only.
+ */
+struct i2c_master_module {
+#if !defined(__DOXYGEN__)
+ /** Hardware instance initialized for the struct. */
+ Sercom *hw;
+ /** Module lock. */
+ volatile bool locked;
+ /** Unknown bus state timeout. */
+ uint16_t unknown_bus_state_timeout;
+ /** Buffer write timeout value. */
+ uint16_t buffer_timeout;
+ /** If true, stop condition will be sent after a read/write. */
+ bool send_stop;
+# if I2C_MASTER_CALLBACK_MODE == true
+ /** Pointers to callback functions. */
+ volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
+ /** Mask for registered callbacks. */
+ volatile uint8_t registered_callback;
+ /** Mask for enabled callbacks. */
+ volatile uint8_t enabled_callback;
+ /** The total number of bytes to transfer. */
+ volatile uint16_t buffer_length;
+ /**
+ * Counter used for bytes left to send in write and to count number of
+ * obtained bytes in read.
+ */
+ volatile uint16_t buffer_remaining;
+ /** Data buffer for packet write and read. */
+ volatile uint8_t *buffer;
+ /** Save direction of async request. 1 = read, 0 = write. */
+ volatile enum i2c_transfer_direction transfer_direction;
+ /** Status for status read back in error callback. */
+ volatile enum status_code status;
+# endif
+#endif
+};
+
+/**
+ * \brief Configuration structure for the I<SUP>2</SUP>C Master device
+ *
+ * This is the configuration structure for the I<SUP>2</SUP>C Master device. It
+ * is used as an argument for \ref i2c_master_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref i2c_master_get_config_defaults .
+ */
+struct i2c_master_config {
+ /** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+ * standard-mode, Fast-mode and Fast-mode Plus Transfers,
+ * \ref i2c_master_baud_rate. */
+ uint32_t baud_rate;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+ /** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+ * High-speed mode, \ref i2c_master_baud_rate. */
+ uint32_t baud_rate_high_speed;
+ /** Transfer speed mode. */
+ enum i2c_master_transfer_speed transfer_speed;
+#endif
+ /** GCLK generator to use as clock source. */
+ enum gclk_generator generator_source;
+ /** Bus hold time after start signal on data line. */
+ enum i2c_master_start_hold_time start_hold_time;
+ /** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout". */
+ uint16_t unknown_bus_state_timeout;
+ /** Timeout for packet write to wait for slave. */
+ uint16_t buffer_timeout;
+ /** Set to keep module active in sleep modes. */
+ bool run_in_standby;
+ /** PAD0 (SDA) pinmux. */
+ uint32_t pinmux_pad0;
+ /** PAD1 (SCL) pinmux. */
+ uint32_t pinmux_pad1;
+ /** Set to enable SCL low time-out. */
+ bool scl_low_timeout;
+ /** Inactive bus time out. */
+ enum i2c_master_inactive_timeout inactive_timeout;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+ /** Set to enable SCL stretch only after ACK bit (required for high speed). */
+ bool scl_stretch_only_after_ack_bit;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+ /** Set to enable slave SCL low extend time-out. */
+ bool slave_scl_low_extend_timeout;
+ /** Set to enable maser SCL low extend time-out. */
+ bool master_scl_low_extend_timeout;
+#endif
+};
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code i2c_master_lock(
+ struct i2c_master_module *const module)
+{
+ enum status_code status;
+
+ system_interrupt_enter_critical_section();
+
+ if (module->locked) {
+ status = STATUS_BUSY;
+ } else {
+ module->locked = true;
+ status = STATUS_OK;
+ }
+
+ system_interrupt_leave_critical_section();
+
+ return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline void i2c_master_unlock(struct i2c_master_module *const module)
+{
+ module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Returns the synchronization status of the module
+ *
+ * Returns the synchronization status of the module.
+ *
+ * \param[in] module Pointer to software module structure
+ *
+ * \return Status of the synchronization.
+ * \retval true Module is busy synchronizing
+ * \retval false Module is not synchronizing
+ */
+static inline bool i2c_master_is_syncing (
+ const struct i2c_master_module *const module)
+{
+ /* Sanity check. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_hw = &(module->hw->I2CM);
+
+#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
+ return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY);
+#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
+ return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
+#else
+# error Unknown SERCOM SYNCBUSY scheme!
+#endif
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal
+ * Wait for hardware module to sync
+ *
+ * \param[in] module Pointer to software module structure
+ */
+static void _i2c_master_wait_for_sync(
+ const struct i2c_master_module *const module)
+{
+ /* Sanity check. */
+ Assert(module);
+
+ while (i2c_master_is_syncing(module)) {
+ /* Wait for I2C module to sync. */
+ }
+}
+#endif
+
+/**
+ * \brief Gets the I<SUP>2</SUP>C master default configurations
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Baudrate 100KHz
+ * - GCLK generator 0
+ * - Do not run in standby
+ * - Start bit hold time 300ns - 600ns
+ * - Buffer timeout = 65535
+ * - Unknown bus status timeout = 65535
+ * - Do not run in standby
+ * - PINMUX_DEFAULT for SERCOM pads
+ *
+ * Those default configuration only availale if the device supports it:
+ * - High speed baudrate 3.4MHz
+ * - Standard-mode and Fast-mode transfer speed
+ * - SCL stretch disabled
+ * - slave SCL low extend time-out disabled
+ * - maser SCL low extend time-out disabled
+ *
+ * \param[out] config Pointer to configuration structure to be initiated
+ */
+static inline void i2c_master_get_config_defaults(
+ struct i2c_master_config *const config)
+{
+ /*Sanity check argument. */
+ Assert(config);
+ config->baud_rate = I2C_MASTER_BAUD_RATE_100KHZ;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+ config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
+ config->transfer_speed = I2C_MASTER_SPEED_STANDARD_AND_FAST;
+#endif
+ config->generator_source = GCLK_GENERATOR_0;
+ config->run_in_standby = false;
+ config->start_hold_time = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
+ config->buffer_timeout = 65535;
+ config->unknown_bus_state_timeout = 65535;
+ config->pinmux_pad0 = PINMUX_DEFAULT;
+ config->pinmux_pad1 = PINMUX_DEFAULT;
+ config->scl_low_timeout = false;
+ config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+ config->scl_stretch_only_after_ack_bit = false;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+ config->slave_scl_low_extend_timeout = false;
+ config->master_scl_low_extend_timeout = false;
+#endif
+}
+
+enum status_code i2c_master_init(
+ struct i2c_master_module *const module,
+ Sercom *const hw,
+ const struct i2c_master_config *const config);
+
+/**
+ * \brief Enables the I<SUP>2</SUP>C module
+ *
+ * Enables the requested I<SUP>2</SUP>C module and set the bus state to IDLE
+ * after the specified \ref asfdoc_sam0_sercom_i2c_timeout "timeout" period if no
+ * stop bit is detected.
+ *
+ * \param[in] module Pointer to the software module struct
+ */
+static inline void i2c_master_enable(
+ const struct i2c_master_module *const module)
+{
+ /* Sanity check of arguments. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Timeout counter used to force bus state. */
+ uint32_t timeout_counter = 0;
+
+ /* Wait for module to sync. */
+ _i2c_master_wait_for_sync(module);
+
+ /* Enable module. */
+ i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Enable module interrupts */
+ system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+ /* Start timeout if bus state is unknown. */
+ while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
+ timeout_counter++;
+ if(timeout_counter >= (module->unknown_bus_state_timeout)) {
+ /* Timeout, force bus state to idle. */
+ i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1);
+ /* Workaround #1 */
+ return;
+ }
+ }
+}
+
+/**
+ * \brief Disable the I<SUP>2</SUP>C module
+ *
+ * Disables the requested I<SUP>2</SUP>C module.
+ *
+ * \param[in] module Pointer to the software module struct
+ */
+static inline void i2c_master_disable(
+ const struct i2c_master_module *const module)
+{
+ /* Sanity check of arguments. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Wait for module to sync. */
+ _i2c_master_wait_for_sync(module);
+
+ /* Disable module. */
+ i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Disable module interrupts */
+ system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+}
+
+void i2c_master_reset(struct i2c_master_module *const module);
+
+/** @} */
+
+/**
+* \name Read and Write
+* @{
+*/
+
+enum status_code i2c_master_read_packet_wait(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_wait_no_stop(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait_no_stop(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet);
+
+void i2c_master_send_stop(struct i2c_master_module *const module);
+
+/** @} */
+
+#ifdef FEATURE_I2C_DMA_SUPPORT
+/**
+* \name SERCOM I2C Master with DMA Interfaces
+* @{
+*/
+
+/**
+ * \brief Set I<SUP>2</SUP>C for DMA transfer with slave address and transfer size.
+ *
+ * This function will set the slave address, transfer size and enable the auto transfer
+ * mode for DMA.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ * \param[in] addr I<SUP>2</SUP>C slave address
+ * \param[in] length I<SUP>2</SUP>C transfer length with DMA
+ * \param[in] direction I<SUP>2</SUP>C transfer direction
+ *
+ */
+static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module,
+ uint16_t addr, uint8_t length, enum i2c_transfer_direction direction)
+{
+ module->hw->I2CM.ADDR.reg =
+ SERCOM_I2CM_ADDR_ADDR(addr<<1) |
+ SERCOM_I2CM_ADDR_LENEN |
+ SERCOM_I2CM_ADDR_LEN(length) |
+ direction;
+}
+
+/** @} */
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_MASTER_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,877 @@
+/**
+ * \file
+ *
+ * \brief SAM I2C Master Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "i2c_master.h"
+
+#if I2C_MASTER_CALLBACK_MODE == true
+# include "i2c_master_interrupt.h"
+#endif
+
+/* Forward declaration */
+enum status_code _i2c_master_wait_for_bus(
+ struct i2c_master_module *const module);
+
+enum status_code _i2c_master_address_response(
+ struct i2c_master_module *const module);
+
+enum status_code _i2c_master_send_hs_master_code(
+ struct i2c_master_module *const module,
+ uint8_t hs_master_code);
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \internal Sets configurations to module
+ *
+ * \param[out] module Pointer to software module structure
+ * \param[in] config Configuration structure with configurations to set
+ *
+ * \return Status of setting configuration.
+ * \retval STATUS_OK If module was configured correctly
+ * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than
+ * previously set
+ * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible
+ * with set GCLK frequency
+ */
+static enum status_code _i2c_master_set_config(
+ struct i2c_master_module *const module,
+ const struct i2c_master_config *const config)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(module->hw);
+ Assert(config);
+
+ /* Temporary variables. */
+ uint32_t tmp_ctrla;
+ int32_t tmp_baud;
+ int32_t tmp_baud_hs;
+ enum status_code tmp_status_code = STATUS_OK;
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+ Sercom *const sercom_hw = module->hw;
+
+ uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
+
+ /* Pin configuration */
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+
+ uint32_t pad0 = config->pinmux_pad0;
+ uint32_t pad1 = config->pinmux_pad1;
+
+ /* SERCOM PAD0 - SDA */
+ if (pad0 == PINMUX_DEFAULT) {
+ pad0 = _sercom_get_default_pad(sercom_hw, 0);
+ }
+ pin_conf.mux_position = pad0 & 0xFFFF;
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+ system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+ /* SERCOM PAD1 - SCL */
+ if (pad1 == PINMUX_DEFAULT) {
+ pad1 = _sercom_get_default_pad(sercom_hw, 1);
+ }
+ pin_conf.mux_position = pad1 & 0xFFFF;
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+ system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+ /* Save timeout on unknown bus state in software module. */
+ module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
+
+ /* Save timeout on buffer write. */
+ module->buffer_timeout = config->buffer_timeout;
+
+ /* Set whether module should run in standby. */
+ if (config->run_in_standby || system_is_debugger_present()) {
+ tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
+ } else {
+ tmp_ctrla = 0;
+ }
+
+ /* Check and set start data hold timeout. */
+ if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
+ tmp_ctrla |= config->start_hold_time;
+ }
+
+ /* Check and set transfer speed */
+ tmp_ctrla |= config->transfer_speed;
+
+ /* Check and set SCL low timeout. */
+ if (config->scl_low_timeout) {
+ tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+ }
+
+ /* Check and set inactive bus timeout. */
+ if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
+ tmp_ctrla |= config->inactive_timeout;
+ }
+
+ /* Check and set SCL clock stretch mode. */
+ if (config->scl_stretch_only_after_ack_bit) {
+ tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
+ }
+
+ /* Check and set slave SCL low extend timeout. */
+ if (config->slave_scl_low_extend_timeout) {
+ tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+ }
+
+ /* Check and set master SCL low extend timeout. */
+ if (config->master_scl_low_extend_timeout) {
+ tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+ }
+
+ /* Write config to register CTRLA. */
+ i2c_module->CTRLA.reg |= tmp_ctrla;
+
+ /* Set configurations in CTRLB. */
+ i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
+
+ /* Find and set baudrate. */
+ tmp_baud = (int32_t)(div_ceil(
+ system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index),
+ (2000*(config->baud_rate))) - 5);
+
+ /* Check that baudrate is supported at current speed. */
+ if (tmp_baud > 255 || tmp_baud < 0) {
+ /* Baud rate not supported. */
+ tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ } else {
+ /* Find baudrate for high speed */
+ tmp_baud_hs = (int32_t)(div_ceil(
+ system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index),
+ (2000*(config->baud_rate_high_speed))) - 1);
+
+ /* Check that baudrate is supported at current speed. */
+ if (tmp_baud_hs > 255 || tmp_baud_hs < 0) {
+ /* Baud rate not supported. */
+ tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ }
+ }
+ if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) {
+ /* Baud rate acceptable. */
+ i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
+ SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs);
+ }
+
+ return tmp_status_code;
+}
+#endif /* __DOXYGEN__ */
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the SERCOM I<SUP>2</SUP>C master device requested and sets the provided
+ * software module struct. Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module Pointer to software module struct
+ * \param[in] hw Pointer to the hardware instance
+ * \param[in] config Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK Module initiated correctly
+ * \retval STATUS_ERR_DENIED If module is enabled
+ * \retval STATUS_BUSY If module is busy resetting
+ * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than
+ * previously set
+ * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible
+ * with set GCLK frequency
+ *
+ */
+enum status_code i2c_master_init(
+ struct i2c_master_module *const module,
+ Sercom *const hw,
+ const struct i2c_master_config *const config)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(hw);
+ Assert(config);
+
+ /* Initialize software module */
+ module->hw = hw;
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+#if (SAML21)
+ uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+#else
+ uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+#endif
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ /* Turn on module in PM */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+ /* Set up the GCLK for the module */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = config->generator_source;
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+ system_gclk_chan_enable(gclk_index);
+ sercom_set_gclk_generator(config->generator_source, false);
+
+ /* Check if module is enabled. */
+ if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Check if reset is in progress. */
+ if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
+ return STATUS_BUSY;
+ }
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Get sercom instance index and register callback. */
+ uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+ _sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
+ _sercom_instances[instance_index] = module;
+
+ /* Initialize values in module. */
+ module->registered_callback = 0;
+ module->enabled_callback = 0;
+ module->buffer_length = 0;
+ module->buffer_remaining = 0;
+
+ module->status = STATUS_OK;
+ module->buffer = NULL;
+#endif
+
+ /* Set sercom module to operate in I2C master mode. */
+ i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
+
+ /* Set config and return status. */
+ return _i2c_master_set_config(module, config);
+}
+
+/**
+ * \brief Resets the hardware module
+ *
+ * Reset the module to hardware defaults.
+ *
+ * \param[in,out] module Pointer to software module structure
+ */
+void i2c_master_reset(struct i2c_master_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Wait for sync */
+ _i2c_master_wait_for_sync(module);
+
+ /* Disable module */
+ i2c_master_disable(module);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Clear all pending interrupts */
+ system_interrupt_enter_critical_section();
+ system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+ system_interrupt_leave_critical_section();
+#endif
+
+ /* Wait for sync */
+ _i2c_master_wait_for_sync(module);
+
+ /* Reset module */
+ i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal
+ * Address response. Called when address is answered or timed out.
+ *
+ * \param[in,out] module Pointer to software module structure
+ *
+ * \return Status of address response.
+ * \retval STATUS_OK No error has occurred
+ * \retval STATUS_ERR_DENIED If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
+ * acknowledged the address
+ */
+enum status_code _i2c_master_address_response(
+ struct i2c_master_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
+ * BUSY */
+ if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
+
+ /* Clear write interrupt flag */
+ i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+
+ /* Check arbitration. */
+ if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
+ /* Return packet collision. */
+ return STATUS_ERR_PACKET_COLLISION;
+ }
+ /* Check that slave responded with ack. */
+ } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+ /* Slave busy. Issue ack and stop command. */
+ i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+
+ /* Return bad address value. */
+ return STATUS_ERR_BAD_ADDRESS;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Waits for answer on bus.
+ *
+ * \param[in,out] module Pointer to software module structure
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK If given response from slave device
+ * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout
+ * period
+ */
+enum status_code _i2c_master_wait_for_bus(
+ struct i2c_master_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Wait for reply. */
+ uint16_t timeout_counter = 0;
+ while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
+ !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) {
+
+ /* Check timeout condition. */
+ if (++timeout_counter >= module->buffer_timeout) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+ return STATUS_OK;
+}
+#endif /* __DOXYGEN__ */
+
+/**
+ * \internal
+ * Send master code for high speed transfer.
+ *
+ * \param[in,out] module Pointer to software module structure
+ * \param[in] hs_master_code 8-bit master code (0000 1XXX)
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK No error happen
+ */
+enum status_code _i2c_master_send_hs_master_code(
+ struct i2c_master_module *const module,
+ uint8_t hs_master_code)
+{
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+ /* Return value. */
+ enum status_code tmp_status;
+
+ /* Set NACK for high speed code */
+ i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+ /* Send high speed code */
+ i2c_module->ADDR.reg = hs_master_code;
+ /* Wait for response on bus. */
+ tmp_status = _i2c_master_wait_for_bus(module);
+ /* Clear write interrupt flag */
+ i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+ return tmp_status;
+}
+
+
+/**
+ * \internal
+ * Starts blocking read operation.
+ *
+ * \param[in,out] module Pointer to software module struct
+ * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT If no response was given within
+ * specified timeout period
+ * \retval STATUS_ERR_DENIED If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
+ * acknowledged the address
+ *
+ */
+static enum status_code _i2c_master_read_packet(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+ Assert(packet);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Return value. */
+ enum status_code tmp_status;
+ uint16_t tmp_data_length = packet->data_length;
+
+ /* Written buffer counter. */
+ uint16_t counter = 0;
+
+ bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+ /* Switch to high speed mode */
+ if (packet->high_speed) {
+ _i2c_master_send_hs_master_code(module, packet->hs_master_code);
+ }
+
+ /* Set action to ACK. */
+ i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+ /* Set address and direction bit. Will send start command on bus. */
+ if (packet->ten_bit_address) {
+ /*
+ * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
+ * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
+ */
+ i2c_module->ADDR.reg = (packet->address << 1) |
+ (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+ SERCOM_I2CM_ADDR_TENBITEN;
+
+ /* Wait for response on bus. */
+ tmp_status = _i2c_master_wait_for_bus(module);
+
+ /* Set action to ack. */
+ i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+ /* Check for address response error unless previous error is
+ * detected. */
+ if (tmp_status == STATUS_OK) {
+ tmp_status = _i2c_master_address_response(module);
+ }
+
+ if (tmp_status == STATUS_OK) {
+ /*
+ * Write ADDR[7:0] register to 鈥10 address[9:8] 1鈥
+ * ADDR.TENBITEN must be cleared
+ */
+ i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
+ (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+ I2C_TRANSFER_READ;
+ } else {
+ return tmp_status;
+ }
+ } else {
+ i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
+ (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+ }
+
+ /* Wait for response on bus. */
+ tmp_status = _i2c_master_wait_for_bus(module);
+
+ /* Set action to ack. */
+ i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+ /* Check for address response error unless previous error is
+ * detected. */
+ if (tmp_status == STATUS_OK) {
+ tmp_status = _i2c_master_address_response(module);
+ }
+
+ /* Check that no error has occurred. */
+ if (tmp_status == STATUS_OK) {
+ /* Read data buffer. */
+ while (tmp_data_length--) {
+ /* Check that bus ownership is not lost. */
+ if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
+ return STATUS_ERR_PACKET_COLLISION;
+ }
+
+ if (((!sclsm_flag) && (tmp_data_length == 0)) ||
+ ((sclsm_flag) && (tmp_data_length == 1))) {
+ /* Set action to NACK */
+ i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+ } else {
+ /* Save data to buffer. */
+ _i2c_master_wait_for_sync(module);
+ packet->data[counter++] = i2c_module->DATA.reg;
+ /* Wait for response. */
+ tmp_status = _i2c_master_wait_for_bus(module);
+ }
+
+ /* Check for error. */
+ if (tmp_status != STATUS_OK) {
+ break;
+ }
+ }
+
+ if (module->send_stop) {
+ /* Send stop command unless arbitration is lost. */
+ _i2c_master_wait_for_sync(module);
+ i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+ }
+
+ /* Save last data to buffer. */
+ _i2c_master_wait_for_sync(module);
+ packet->data[counter] = i2c_module->DATA.reg;
+ }
+
+ return tmp_status;
+}
+
+/**
+ * \brief Reads data packet from slave
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ * interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module Pointer to software module struct
+ * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT If no response was given within
+ * specified timeout period
+ * \retval STATUS_ERR_DENIED If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
+ * acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet)
+{
+ /* Sanity check */
+ Assert(module);
+ Assert(module->hw);
+ Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Check if the I2C module is busy with a job. */
+ if (module->buffer_remaining > 0) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ module->send_stop = true;
+
+ return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Reads data packet from slave without sending a stop condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus without sending a stop condition when done, thus retaining ownership of
+ * the bus when done. To end the transaction, a
+ * \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * \note This will stall the device from any other operation. For
+ * interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module Pointer to software module struct
+ * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT If no response was given within
+ * specified timeout period
+ * \retval STATUS_ERR_DENIED If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
+ * acknowledged the address
+ */
+enum status_code i2c_master_read_packet_wait_no_stop(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet)
+{
+ /* Sanity check */
+ Assert(module);
+ Assert(module->hw);
+ Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Check if the I2C module is busy with a job. */
+ if (module->buffer_remaining > 0) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ module->send_stop = false;
+
+ return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts blocking write operation.
+ *
+ * \param[in,out] module Pointer to software module struct
+ * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK The packet was read successfully
+ * \retval STATUS_ERR_TIMEOUT If no response was given within
+ * specified timeout period
+ * \retval STATUS_ERR_DENIED If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
+ * acknowledged the address
+ */
+static enum status_code _i2c_master_write_packet(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet)
+{
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Return value. */
+ enum status_code tmp_status;
+ uint16_t tmp_data_length = packet->data_length;
+
+ _i2c_master_wait_for_sync(module);
+
+ /* Switch to high speed mode */
+ if (packet->high_speed) {
+ _i2c_master_send_hs_master_code(module, packet->hs_master_code);
+ }
+
+ /* Set action to ACK. */
+ i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+ /* Set address and direction bit. Will send start command on bus. */
+ if (packet->ten_bit_address) {
+ i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+ (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+ SERCOM_I2CM_ADDR_TENBITEN;
+ } else {
+ i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+ (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+ }
+ /* Wait for response on bus. */
+ tmp_status = _i2c_master_wait_for_bus(module);
+
+ /* Check for address response error unless previous error is
+ * detected. */
+ if (tmp_status == STATUS_OK) {
+ tmp_status = _i2c_master_address_response(module);
+ }
+
+ /* Check that no error has occurred. */
+ if (tmp_status == STATUS_OK) {
+ /* Buffer counter. */
+ uint16_t buffer_counter = 0;
+
+ /* Write data buffer. */
+ while (tmp_data_length--) {
+ /* Check that bus ownership is not lost. */
+ if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
+ return STATUS_ERR_PACKET_COLLISION;
+ }
+
+ /* Write byte to slave. */
+ _i2c_master_wait_for_sync(module);
+ i2c_module->DATA.reg = packet->data[buffer_counter++];
+
+ /* Wait for response. */
+ tmp_status = _i2c_master_wait_for_bus(module);
+
+ /* Check for error. */
+ if (tmp_status != STATUS_OK) {
+ break;
+ }
+
+ /* Check for NACK from slave. */
+ if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+ /* Return bad data value. */
+ tmp_status = STATUS_ERR_OVERFLOW;
+ break;
+ }
+ }
+
+ if (module->send_stop) {
+ /* Stop command */
+ _i2c_master_wait_for_sync(module);
+ i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+ }
+ }
+
+ return tmp_status;
+}
+
+/**
+ * \brief Writes data packet to slave
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * and sends a stop condition when finished.
+ *
+ * \note This will stall the device from any other operation. For
+ * interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module Pointer to software module struct
+ * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK If packet was read
+ * \retval STATUS_BUSY If master module is busy with a job
+ * \retval STATUS_ERR_DENIED If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
+ * acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent
+ * data, indicating that slave does not
+ * want more data and was not able to read
+ * last data sent
+ */
+enum status_code i2c_master_write_packet_wait(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet)
+{
+ /* Sanity check */
+ Assert(module);
+ Assert(module->hw);
+ Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Check if the I2C module is busy with a job */
+ if (module->buffer_remaining > 0) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ module->send_stop = true;
+
+ return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Writes data packet to slave without sending a stop condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending a
+ * stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * \note This will stall the device from any other operation. For
+ * interrupt-driven operation, see \ref i2c_master_read_packet_job.
+ *
+ * \param[in,out] module Pointer to software module struct
+ * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of reading packet.
+ * \retval STATUS_OK If packet was read
+ * \retval STATUS_BUSY If master module is busy
+ * \retval STATUS_ERR_DENIED If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
+ * acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent
+ * data, indicating that slave do not want
+ * more data
+ */
+enum status_code i2c_master_write_packet_wait_no_stop(
+ struct i2c_master_module *const module,
+ struct i2c_master_packet *const packet)
+{
+ /* Sanity check */
+ Assert(module);
+ Assert(module->hw);
+ Assert(packet);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+ /* Check if the I2C module is busy with a job */
+ if (module->buffer_remaining > 0) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ module->send_stop = false;
+
+ return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Sends stop condition on bus
+ *
+ * Sends a stop condition on bus.
+ *
+ * \note This function can only be used after the
+ * \ref i2c_master_write_packet_wait_no_stop function. If a stop condition
+ * is to be sent after a read, the \ref i2c_master_read_packet_wait
+ * function must be used.
+ *
+ * \param[in] module Pointer to the software instance struct
+ */
+void i2c_master_send_stop(struct i2c_master_module *const module)
+{
+ /* Sanity check */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Send stop command */
+ _i2c_master_wait_for_sync(module);
+ i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,720 @@
+/**
+ * \file
+ *
+ * \brief SAM I<SUP>2</SUP>C Slave Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "i2c_slave.h"
+#if I2C_SLAVE_CALLBACK_MODE == true
+# include "i2c_slave_interrupt.h"
+#endif
+
+/**
+ * \internal Sets configuration to module
+ *
+ * \param[out] module Pointer to software module structure
+ * \param[in] config Configuration structure with configurations to set
+ *
+ * \return Status of setting configuration.
+ * \retval STATUS_OK Module was configured correctly
+ * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than
+ * previously set
+ */
+static enum status_code _i2c_slave_set_config(
+ struct i2c_slave_module *const module,
+ const struct i2c_slave_config *const config)
+{
+ uint32_t tmp_ctrla;
+
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(module->hw);
+ Assert(config);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+ Sercom *const sercom_hw = module->hw;
+
+ module->buffer_timeout = config->buffer_timeout;
+ module->ten_bit_address = config->ten_bit_address;
+
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+
+ uint32_t pad0 = config->pinmux_pad0;
+ uint32_t pad1 = config->pinmux_pad1;
+
+ /* SERCOM PAD0 - SDA */
+ if (pad0 == PINMUX_DEFAULT) {
+ pad0 = _sercom_get_default_pad(sercom_hw, 0);
+ }
+ pin_conf.mux_position = pad0 & 0xFFFF;
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+ system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+ /* SERCOM PAD1 - SCL */
+ if (pad1 == PINMUX_DEFAULT) {
+ pad1 = _sercom_get_default_pad(sercom_hw, 1);
+ }
+ pin_conf.mux_position = pad1 & 0xFFFF;
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+ system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+ /* Prepare config to write to register CTRLA */
+ if (config->run_in_standby || system_is_debugger_present()) {
+ tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY;
+ } else {
+ tmp_ctrla = 0;
+ }
+
+ tmp_ctrla |= ((uint32_t)config->sda_hold_time |
+ config->transfer_speed |
+ (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) |
+ (config->scl_stretch_only_after_ack_bit << SERCOM_I2CS_CTRLA_SCLSM_Pos) |
+ (config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos));
+
+ i2c_hw->CTRLA.reg |= tmp_ctrla;
+
+ /* Set CTRLB configuration */
+ i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode;
+
+ i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos |
+ config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos |
+ config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos |
+ config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the requested I<SUP>2</SUP>C hardware module
+ *
+ * Initializes the SERCOM I<SUP>2</SUP>C Slave device requested and sets the provided
+ * software module struct. Run this function before any further use of
+ * the driver.
+ *
+ * \param[out] module Pointer to software module struct
+ * \param[in] hw Pointer to the hardware instance
+ * \param[in] config Pointer to the configuration struct
+ *
+ * \return Status of initialization.
+ * \retval STATUS_OK Module initiated correctly
+ * \retval STATUS_ERR_DENIED If module is enabled
+ * \retval STATUS_BUSY If module is busy resetting
+ * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than
+ * previously set
+ */
+enum status_code i2c_slave_init(
+ struct i2c_slave_module *const module,
+ Sercom *const hw,
+ const struct i2c_slave_config *const config)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(hw);
+ Assert(config);
+
+ /* Initialize software module */
+ module->hw = hw;
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+ /* Check if module is enabled. */
+ if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Check if reset is in progress. */
+ if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) {
+ return STATUS_BUSY;
+ }
+
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+#if (SAML21)
+ uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+#else
+ uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+#endif
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ /* Turn on module in PM */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+ /* Set up the GCLK for the module */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = config->generator_source;
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+ system_gclk_chan_enable(gclk_index);
+ sercom_set_gclk_generator(config->generator_source, false);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /* Get sercom instance index. */
+ uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+
+ /* Save software module in interrupt handler. */
+ _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler);
+
+ /* Save software module. */
+ _sercom_instances[instance_index] = module;
+
+ /* Initialize values in module. */
+ module->registered_callback = 0;
+ module->enabled_callback = 0;
+ module->buffer_length = 0;
+ module->nack_on_address = config->enable_nack_on_address;
+#endif
+
+ /* Set SERCOM module to operate in I2C slave mode. */
+ i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4);
+
+ /* Set config and return status. */
+ return _i2c_slave_set_config(module, config);
+}
+
+/**
+ * \brief Resets the hardware module
+ *
+ * This will reset the module to hardware defaults.
+ *
+ * \param[in,out] module Pointer to software module structure
+ */
+void i2c_slave_reset(
+ struct i2c_slave_module *const module)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /* Reset module instance. */
+ module->registered_callback = 0;
+ module->enabled_callback = 0;
+ module->buffer_length = 0;
+ module->buffer_remaining = 0;
+ module->buffer = NULL;
+#endif
+
+ /* Disable module */
+ i2c_slave_disable(module);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /* Clear all pending interrupts. */
+ system_interrupt_enter_critical_section();
+ system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+ system_interrupt_leave_critical_section();
+#endif
+
+ /* Wait for sync. */
+ _i2c_slave_wait_for_sync(module);
+
+ /* Reset module. */
+ i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
+}
+
+/**
+ * \internal Waits for answer on bus
+ *
+ * \param[in] module Pointer to software module structure
+ *
+ * \return Status of bus.
+ * \retval STATUS_OK If given response from slave device
+ * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout
+ * period
+ */
+static enum status_code _i2c_slave_wait_for_bus(
+ struct i2c_slave_module *const module)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+ /* Wait for reply. */
+ uint16_t timeout_counter = 0;
+ while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) &&
+ (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) &&
+ (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) {
+
+ /* Check timeout condition. */
+ if (++timeout_counter >= module->buffer_timeout) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Writes a packet to the master
+ *
+ * Writes a packet to the master. This will wait for the master to issue
+ * a request.
+ *
+ * \param[in] module Pointer to software module structure
+ * \param[in] packet Packet to write to master
+ *
+ * \return Status of packet write.
+ * \retval STATUS_OK Packet was written successfully
+ * \retval STATUS_ERR_DENIED Start condition not received, another
+ * interrupt flag is set
+ * \retval STATUS_ERR_IO There was an error in the previous transfer
+ * \retval STATUS_ERR_BAD_FORMAT Master wants to write data
+ * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided
+ * \retval STATUS_ERR_BUSY The I<SUP>2</SUP>C module is busy with a job
+ * \retval STATUS_ERR_ERR_OVERFLOW Master NACKed before entire packet was
+ * transferred
+ * \retval STATUS_ERR_TIMEOUT No response was given within the timeout
+ * period
+ */
+enum status_code i2c_slave_write_packet_wait(
+ struct i2c_slave_module *const module,
+ struct i2c_slave_packet *const packet)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(module->hw);
+ Assert(packet);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+ uint16_t length = packet->data_length;
+
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /* Check if the module is busy with a job or AMATCH is enabled */
+ if (module->buffer_remaining > 0 ||
+ (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ enum status_code status;
+ /* Wait for master to send address packet */
+ status = _i2c_slave_wait_for_bus(module);
+
+ if (status != STATUS_OK) {
+ /* Timeout, return */
+ return status;
+ }
+ if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+ /* Not address interrupt, something is wrong */
+ return STATUS_ERR_DENIED;
+ }
+
+ if (module->ten_bit_address) {
+ /* ACK the first address */
+ i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+ /* Wait for address interrupt */
+ status = _i2c_slave_wait_for_bus(module);
+
+ if (status != STATUS_OK) {
+ /* Timeout, return */
+ return STATUS_ERR_TIMEOUT;
+ }
+
+ if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+ /* Not address interrupt, something is wrong */
+ return STATUS_ERR_DENIED;
+ }
+ }
+
+ /* Check if there was an error in last transfer */
+ if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+ SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+ return STATUS_ERR_IO;
+ }
+
+ /* Check direction */
+ if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+ /* Write request from master, send NACK and return */
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+ return STATUS_ERR_BAD_FORMAT;
+ }
+
+ /* Read request from master, ACK address */
+ i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+ uint16_t i = 0;
+
+ /* Wait for data interrupt */
+ status = _i2c_slave_wait_for_bus(module);
+ if (status != STATUS_OK) {
+ /* Timeout, return */
+ return status;
+ }
+
+ while (length--) {
+ /* Write data */
+ _i2c_slave_wait_for_sync(module);
+ i2c_hw->DATA.reg = packet->data[i++];
+
+ /* Wait for response from master */
+ status = _i2c_slave_wait_for_bus(module);
+
+ if (status != STATUS_OK) {
+ /* Timeout, return */
+ return status;
+ }
+
+ if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK &&
+ length !=0) {
+ /* NACK from master, abort */
+ /* Release line */
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+ return STATUS_ERR_OVERFLOW;
+ }
+ /* ACK from master, continue writing */
+ }
+
+ /* Release line */
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Reads a packet from the master
+ *
+ * Reads a packet from the master. This will wait for the master to issue a
+ * request.
+ *
+ * \param[in] module Pointer to software module structure
+ * \param[out] packet Packet to read from master
+ *
+ * \return Status of packet read.
+ * \retval STATUS_OK Packet was read successfully
+ * \retval STATUS_ABORTED Master sent stop condition or repeated
+ * start before specified length of bytes
+ * was received
+ * \retval STATUS_ERR_IO There was an error in the previous transfer
+ * \retval STATUS_ERR_DENIED Start condition not received, another
+ * interrupt flag is set
+ * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided
+ * \retval STATUS_ERR_BUSY The I<SUP>2</SUP>C module is busy with a job
+ * \retval STATUS_ERR_BAD_FORMAT Master wants to read data
+ * \retval STATUS_ERR_ERR_OVERFLOW Last byte received overflows buffer
+ */
+enum status_code i2c_slave_read_packet_wait(
+ struct i2c_slave_module *const module,
+ struct i2c_slave_packet *const packet)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(module->hw);
+ Assert(packet);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+ uint16_t length = packet->data_length;
+
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /* Check if the module is busy with a job or AMATCH is enabled */
+ if (module->buffer_remaining > 0 ||
+ (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ enum status_code status;
+
+ /* Wait for master to send address packet */
+ status = _i2c_slave_wait_for_bus(module);
+ if (status != STATUS_OK) {
+ /* Timeout, return */
+ return status;
+ }
+
+ if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+ /* Not address interrupt, something is wrong */
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Check if there was an error in the last transfer */
+ if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+ SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
+ return STATUS_ERR_IO;
+ }
+ /* Check direction */
+ if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+ /* Read request from master, send NACK and return */
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+ return STATUS_ERR_BAD_FORMAT;
+ }
+
+ /* Write request from master, ACK address */
+ i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+ uint16_t i = 0;
+ while (length--) {
+
+ /* Wait for next byte or stop condition */
+ status = _i2c_slave_wait_for_bus(module);
+ if (status != STATUS_OK) {
+ /* Timeout, return */
+ return status;
+ }
+
+ if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) ||
+ i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
+ /* Master sent stop condition, or repeated start, read done */
+ /* Clear stop flag */
+ i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+ return STATUS_ABORTED;
+ }
+
+ /* Read data */
+ _i2c_slave_wait_for_sync(module);
+ packet->data[i++] = i2c_hw->DATA.reg;
+
+ }
+
+ /* Packet read done, wait for packet to NACK, Stop or repeated start */
+ status = _i2c_slave_wait_for_bus(module);
+
+ if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
+ /* Buffer is full, send NACK */
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+ i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+ }
+ if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
+ /* Clear stop flag */
+ i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Waits for a start condition on the bus
+ *
+ * \note This function is only available for 7-bit slave addressing.
+ *
+ * Waits for the master to issue a start condition on the bus.
+ * Note that this function does not check for errors in the last transfer,
+ * this will be discovered when reading or writing.
+ *
+ * \param[in] module Pointer to software module structure
+ *
+ * \return Direction of the current transfer, when in slave mode.
+ * \retval I2C_SLAVE_DIRECTION_NONE No request from master within timeout
+ * period
+ * \retval I2C_SLAVE_DIRECTION_READ Write request from master
+ * \retval I2C_SLAVE_DIRECTION_WRITE Read request from master
+ */
+enum i2c_slave_direction i2c_slave_get_direction_wait(
+ struct i2c_slave_module *const module)
+{
+ /* Sanity check arguments. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+ enum status_code status;
+
+ /* Wait for address interrupt */
+ status = _i2c_slave_wait_for_bus(module);
+
+ if (status != STATUS_OK) {
+ /* Timeout, return */
+ return I2C_SLAVE_DIRECTION_NONE;
+ }
+
+ if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
+ /* Not address interrupt, something is wrong */
+ return I2C_SLAVE_DIRECTION_NONE;
+ }
+
+ /* Check direction */
+ if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
+ /* Read request from master */
+ return I2C_SLAVE_DIRECTION_WRITE;
+ } else {
+ /* Write request from master */
+ return I2C_SLAVE_DIRECTION_READ;
+ }
+}
+
+/**
+ * \brief Retrieves the current module status
+ *
+ * Checks the status of the module and returns it as a bitmask of status
+ * flags.
+ *
+ * \param[in] module Pointer to the I<SUP>2</SUP>C slave software device struct
+ *
+ * \return Bitmask of status flags.
+ *
+ * \retval I2C_SLAVE_STATUS_ADDRESS_MATCH A valid address has been received
+ * \retval I2C_SLAVE_STATUS_DATA_READY A I<SUP>2</SUP>C slave byte transmission is
+ * successfully completed
+ * \retval I2C_SLAVE_STATUS_STOP_RECEIVED A stop condition is detected for a
+ * transaction being processed
+ * \retval I2C_SLAVE_STATUS_CLOCK_HOLD The slave is holding the SCL line
+ * low
+ * \retval I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT An SCL low time-out has occurred
+ * \retval I2C_SLAVE_STATUS_REPEATED_START Indicates a repeated start, only
+ * valid if \ref
+ * I2C_SLAVE_STATUS_ADDRESS_MATCH is
+ * set
+ * \retval I2C_SLAVE_STATUS_RECEIVED_NACK The last data packet sent was not
+ * acknowledged
+ * \retval I2C_SLAVE_STATUS_COLLISION The I<SUP>2</SUP>C slave was not able to
+ * transmit a high data or NACK bit
+ * \retval I2C_SLAVE_STATUS_BUS_ERROR An illegal bus condition has
+ * occurred on the bus
+ */
+uint32_t i2c_slave_get_status(
+ struct i2c_slave_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+ uint8_t intflags = i2c_hw->INTFLAG.reg;
+ uint8_t status = i2c_hw->STATUS.reg;
+ uint32_t status_flags = 0;
+
+ /* Check Address Match flag */
+ if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) {
+ status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH;
+ }
+ /* Check Data Ready flag */
+ if (intflags & SERCOM_I2CS_INTFLAG_DRDY) {
+ status_flags |= I2C_SLAVE_STATUS_DATA_READY;
+ }
+ /* Check Stop flag */
+ if (intflags & SERCOM_I2CS_INTFLAG_PREC) {
+ status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED;
+ }
+ /* Check Clock Hold */
+ if (status & SERCOM_I2CS_STATUS_CLKHOLD) {
+ status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD;
+ }
+ /* Check SCL Low Timeout */
+ if (status & SERCOM_I2CS_STATUS_LOWTOUT) {
+ status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT;
+ }
+ /* Check Repeated Start */
+ if (status & SERCOM_I2CS_STATUS_SR) {
+ status_flags |= I2C_SLAVE_STATUS_REPEATED_START;
+ }
+ /* Check Received Not Acknowledge */
+ if (status & SERCOM_I2CS_STATUS_RXNACK) {
+ status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK;
+ }
+ /* Check Transmit Collision */
+ if (status & SERCOM_I2CS_STATUS_COLL) {
+ status_flags |= I2C_SLAVE_STATUS_COLLISION;
+ }
+ /* Check Bus Error */
+ if (status & SERCOM_I2CS_STATUS_BUSERR) {
+ status_flags |= I2C_SLAVE_STATUS_BUS_ERROR;
+ }
+
+ return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag
+ *
+ * Clears the given status flag of the module.
+ *
+ * \note Not all status flags can be cleared.
+ *
+ * \param[in] module Pointer to the I<SUP>2</SUP>C software device struct
+ * \param[in] status_flags Bit mask of status flags to clear
+ *
+ */
+void i2c_slave_clear_status(
+ struct i2c_slave_module *const module,
+ uint32_t status_flags)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+ /* Clear Address Match flag */
+ if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) {
+ i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+ }
+ /* Clear Data Ready flag */
+ if (status_flags & I2C_SLAVE_STATUS_DATA_READY) {
+ i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+ }
+ /* Clear Stop flag */
+ if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) {
+ i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+ }
+ /* Clear SCL Low Timeout */
+ if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) {
+ i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+ }
+ /* Clear Transmit Collision */
+ if (status_flags & I2C_SLAVE_STATUS_COLLISION) {
+ i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+ }
+ /* Clear Bus Error */
+ if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) {
+ i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_slave.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,663 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Slave Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef I2C_SLAVE_H_INCLUDED
+#define I2C_SLAVE_H_INCLUDED
+
+#include "i2c_common.h"
+#include <sercom.h>
+#include <pinmux.h>
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+# include <sercom_interrupt.h>
+#endif
+
+#ifndef PINMUX_DEFAULT
+# define PINMUX_DEFAULT 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ *
+ * @{
+ *
+ */
+
+/**
+ * \name I2C Slave Status Flags
+ *
+ * I<SUP>2</SUP>C slave status flags, returned by \ref i2c_slave_get_status() and cleared
+ * by \ref i2c_slave_clear_status().
+ * @{
+ */
+
+/** Address Match.
+ * \note Should only be cleared internally by driver.
+ */
+#define I2C_SLAVE_STATUS_ADDRESS_MATCH (1UL << 0)
+/** Data Ready. */
+#define I2C_SLAVE_STATUS_DATA_READY (1UL << 1)
+/** Stop Received. */
+#define I2C_SLAVE_STATUS_STOP_RECEIVED (1UL << 2)
+/** Clock Hold.
+ * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is
+ * set.
+ */
+#define I2C_SLAVE_STATUS_CLOCK_HOLD (1UL << 3)
+/** SCL Low Timeout. */
+#define I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT (1UL << 4)
+/** Repeated Start.
+ * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is
+ * set.
+ */
+#define I2C_SLAVE_STATUS_REPEATED_START (1UL << 5)
+/** Received not acknowledge.
+ * \note Cannot be cleared.
+ */
+#define I2C_SLAVE_STATUS_RECEIVED_NACK (1UL << 6)
+/** Transmit Collision. */
+#define I2C_SLAVE_STATUS_COLLISION (1UL << 7)
+/** Bus error. */
+#define I2C_SLAVE_STATUS_BUS_ERROR (1UL << 8)
+
+/** @} */
+
+/**
+ * \brief I<SUP>2</SUP>C slave packet for read/write
+ *
+ * Structure to be used when transferring I<SUP>2</SUP>C slave packets.
+ */
+struct i2c_slave_packet {
+ /** Length of data array. */
+ uint16_t data_length;
+ /** Data array containing all data to be transferred. */
+ uint8_t *data;
+};
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+/**
+* \brief Callback types
+*
+* The available callback types for the I<SUP>2</SUP>C slave.
+*/
+enum i2c_slave_callback {
+ /** Callback for packet write complete. */
+ I2C_SLAVE_CALLBACK_WRITE_COMPLETE,
+ /** Callback for packet read complete. */
+ I2C_SLAVE_CALLBACK_READ_COMPLETE,
+ /**
+ * Callback for read request from master - can be used to
+ * issue a write.
+ */
+ I2C_SLAVE_CALLBACK_READ_REQUEST,
+ /**
+ * Callback for write request from master - can be used to issue a read.
+ */
+ I2C_SLAVE_CALLBACK_WRITE_REQUEST,
+ /** Callback for error. */
+ I2C_SLAVE_CALLBACK_ERROR,
+ /**
+ * Callback for error in last transfer. Discovered on a new address
+ * interrupt.
+ */
+ I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER,
+# if !defined(__DOXYGEN__)
+ /** Total number of callbacks. */
+ _I2C_SLAVE_CALLBACK_N,
+# endif
+};
+
+# if !defined(__DOXYGEN__)
+/** Software module prototype. */
+struct i2c_slave_module;
+
+/** Callback type. */
+typedef void (*i2c_slave_callback_t)(
+ struct i2c_slave_module *const module);
+# endif
+#endif
+
+/**
+ * \brief Enum for the possible SDA hold times with respect to the negative
+ * edge of SCL
+ *
+ * Enum for the possible SDA hold times with respect to the negative edge
+ * of SCL.
+ */
+enum i2c_slave_sda_hold_time {
+ /** SDA hold time disabled. */
+ I2C_SLAVE_SDA_HOLD_TIME_DISABLED =
+ ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+ /** SDA hold time 50ns - 100ns. */
+ I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS =
+ ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+ /** SDA hold time 300ns - 600ns. */
+ I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS =
+ ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+ /** SDA hold time 400ns - 800ns. */
+ I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS =
+ ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+};
+
+/**
+ * \brief Enum for the possible address modes
+ *
+ * Enum for the possible address modes.
+ */
+enum i2c_slave_address_mode {
+ /** Address match on address_mask used as a mask to address. */
+ I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0),
+ /** Address math on both address and address_mask. */
+ I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1),
+ /**
+ * Address match on range of addresses between and including address and
+ * address_mask.
+ */
+ I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2),
+};
+
+/**
+ * \brief Enum for the direction of a request
+ *
+ * Enum for the direction of a request.
+ */
+enum i2c_slave_direction {
+ /** Read. */
+ I2C_SLAVE_DIRECTION_READ,
+ /** Write. */
+ I2C_SLAVE_DIRECTION_WRITE,
+ /** No direction. */
+ I2C_SLAVE_DIRECTION_NONE,
+};
+
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/**
+ * \brief Enum for the transfer speed
+ *
+ * Enum for the transfer speed.
+ */
+enum i2c_slave_transfer_speed {
+ /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */
+ I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0),
+ /** Fast-mode Plus (Fm+) up to 1MHz. */
+ I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1),
+ /** High-speed mode (Hs-mode) up to 3.4MHz. */
+ I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2),
+};
+#endif
+
+/**
+ * \brief SERCOM I<SUP>2</SUP>C Slave driver software device instance structure.
+ *
+ * SERCOM I<SUP>2</SUP>C Slave driver software instance structure, used to
+ * retain software state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ * application; they are reserved for module-internal use only.
+ */
+struct i2c_slave_module {
+#if !defined(__DOXYGEN__)
+ /** Hardware instance initialized for the struct. */
+ Sercom *hw;
+ /** Module lock. */
+ volatile bool locked;
+ /** Timeout value for polled functions. */
+ uint16_t buffer_timeout;
+# ifdef FEATURE_I2C_10_BIT_ADDRESS
+ /** Using 10-bit addressing for the slave. */
+ bool ten_bit_address;
+# endif
+# if I2C_SLAVE_CALLBACK_MODE == true
+ /** Nack on address match. */
+ bool nack_on_address;
+ /** Pointers to callback functions. */
+ volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N];
+ /** Mask for registered callbacks. */
+ volatile uint8_t registered_callback;
+ /** Mask for enabled callbacks. */
+ volatile uint8_t enabled_callback;
+ /** The total number of bytes to transfer. */
+ volatile uint16_t buffer_length;
+ /**
+ * Counter used for bytes left to send in write and to count number of
+ * obtained bytes in read.
+ */
+ uint16_t buffer_remaining;
+ /** Data buffer for packet write and read. */
+ volatile uint8_t *buffer;
+ /** Save direction of request from master. 1 = read, 0 = write. */
+ volatile enum i2c_transfer_direction transfer_direction;
+ /** Status for status read back in error callback. */
+ volatile enum status_code status;
+# endif
+#endif
+};
+
+/**
+ * \brief Configuration structure for the I<SUP>2</SUP>C Slave device
+ *
+ * This is the configuration structure for the I<SUP>2</SUP>C Slave device. It is used
+ * as an argument for \ref i2c_slave_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref i2c_slave_get_config_defaults.
+ */
+struct i2c_slave_config {
+ /** Set to enable the SCL low timeout. */
+ bool enable_scl_low_timeout;
+ /** SDA hold time with respect to the negative edge of SCL. */
+ enum i2c_slave_sda_hold_time sda_hold_time;
+ /** Timeout to wait for master in polled functions. */
+ uint16_t buffer_timeout;
+ /** Addressing mode. */
+ enum i2c_slave_address_mode address_mode;
+ /** Address or upper limit of address range. */
+ uint16_t address;
+ /** Address mask, second address or lower limit of address range. */
+ uint16_t address_mask;
+#ifdef FEATURE_I2C_10_BIT_ADDRESS
+ /** Enable 10-bit addressing. */
+ bool ten_bit_address;
+#endif
+ /**
+ * Enable general call address recognition (general call address
+ * is defined as 0000000 with direction bit 0).
+ */
+ bool enable_general_call_address;
+
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+ /** Transfer speed mode. */
+ enum i2c_slave_transfer_speed transfer_speed;
+#endif
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /**
+ * Enable NACK on address match (this can be changed after initialization
+ * via the \ref i2c_slave_enable_nack_on_address and
+ * \ref i2c_slave_disable_nack_on_address functions).
+ */
+ bool enable_nack_on_address;
+#endif
+ /** GCLK generator to use as clock source. */
+ enum gclk_generator generator_source;
+ /** Set to keep module active in sleep modes. */
+ bool run_in_standby;
+ /** PAD0 (SDA) pinmux. */
+ uint32_t pinmux_pad0;
+ /** PAD1 (SCL) pinmux. */
+ uint32_t pinmux_pad1;
+ /** Set to enable SCL low time-out. */
+ bool scl_low_timeout;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+ /** Set to enable SCL stretch only after ACK bit (required for high speed). */
+ bool scl_stretch_only_after_ack_bit;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+ /** Set to enable slave SCL low extend time-out. */
+ bool slave_scl_low_extend_timeout;
+#endif
+};
+
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code i2c_slave_lock(
+ struct i2c_slave_module *const module)
+{
+ enum status_code status;
+
+ system_interrupt_enter_critical_section();
+
+ if (module->locked) {
+ status = STATUS_BUSY;
+ } else {
+ module->locked = true;
+ status = STATUS_OK;
+ }
+
+ system_interrupt_leave_critical_section();
+
+ return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline void i2c_slave_unlock(struct i2c_slave_module *const module)
+{
+ module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Returns the synchronization status of the module
+ *
+ * Returns the synchronization status of the module.
+ *
+ * \param[out] module Pointer to software module structure
+ *
+ * \return Status of the synchronization.
+ * \retval true Module is busy synchronizing
+ * \retval false Module is not synchronizing
+ */
+static inline bool i2c_slave_is_syncing(
+ const struct i2c_slave_module *const module)
+{
+ /* Sanity check */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+ /* Return sync status */
+#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
+ return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY);
+#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
+ return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK);
+#else
+# error Unknown SERCOM SYNCBUSY scheme!
+#endif
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Wait for hardware module to sync
+ *
+ * \param[in] module Pointer to software module structure
+ */
+static void _i2c_slave_wait_for_sync(
+ const struct i2c_slave_module *const module)
+{
+ /* Sanity check. */
+ Assert(module);
+
+ while (i2c_slave_is_syncing(module)) {
+ /* Wait for I2C module to sync */
+ }
+}
+#endif
+
+/**
+ * \brief Gets the I<SUP>2</SUP>C slave default configurations
+ *
+ * This will initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Disable SCL low timeout
+ * - 300ns - 600ns SDA hold time
+ * - Buffer timeout = 65535
+ * - Address with mask
+ * - Address = 0
+ * - Address mask = 0 (one single address)
+ * - General call address disabled
+ * - Address nack disabled if the interrupt driver is used
+ * - GCLK generator 0
+ * - Do not run in standby
+ * - PINMUX_DEFAULT for SERCOM pads
+ *
+ * Those default configuration only availale if the device supports it:
+ * - Not using 10-bit addressing
+ * - Standard-mode and Fast-mode transfer speed
+ * - SCL stretch disabled
+ * - slave SCL low extend time-out disabled
+ *
+ * \param[out] config Pointer to configuration structure to be initialized
+ */
+static inline void i2c_slave_get_config_defaults(
+ struct i2c_slave_config *const config)
+{
+ /*Sanity check argument. */
+ Assert(config);
+ config->enable_scl_low_timeout = false;
+ config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS;
+ config->buffer_timeout = 65535;
+ config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK;
+ config->address = 0;
+ config->address_mask = 0;
+#ifdef FEATURE_I2C_10_BIT_ADDRESS
+ config->ten_bit_address = false;
+#endif
+ config->enable_general_call_address = false;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+ config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST;
+#endif
+#if I2C_SLAVE_CALLBACK_MODE == true
+ config->enable_nack_on_address = false;
+#endif
+ config->generator_source = GCLK_GENERATOR_0;
+ config->run_in_standby = false;
+ config->pinmux_pad0 = PINMUX_DEFAULT;
+ config->pinmux_pad1 = PINMUX_DEFAULT;
+ config->scl_low_timeout = false;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+ config->scl_stretch_only_after_ack_bit = false;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+ config->slave_scl_low_extend_timeout = false;
+#endif
+}
+
+enum status_code i2c_slave_init(struct i2c_slave_module *const module,
+ Sercom *const hw,
+ const struct i2c_slave_config *const config);
+
+/**
+ * \brief Enables the I<SUP>2</SUP>C module
+ *
+ * This will enable the requested I<SUP>2</SUP>C module.
+ *
+ * \param[in] module Pointer to the software module struct
+ */
+static inline void i2c_slave_enable(
+ const struct i2c_slave_module *const module)
+{
+ /* Sanity check of arguments. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /* Enable global interrupt for module */
+ system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+ /* Wait for module to sync */
+ _i2c_slave_wait_for_sync(module);
+
+ /* Enable module */
+ i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+}
+
+
+/**
+ * \brief Disables the I<SUP>2</SUP>C module
+ *
+ * This will disable the I<SUP>2</SUP>C module specified in the provided software module
+ * structure.
+ *
+ * \param[in] module Pointer to the software module struct
+ */
+static inline void i2c_slave_disable(
+ const struct i2c_slave_module *const module)
+{
+ /* Sanity check of arguments. */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+#if I2C_SLAVE_CALLBACK_MODE == true
+ /* Disable interrupts */
+ i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC |
+ SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY;
+
+ /* Clear interrupt flags */
+ i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH |
+ SERCOM_I2CS_INTFLAG_DRDY;
+
+ /* Disable global interrupt for module */
+ system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+ /* Wait for module to sync */
+ _i2c_slave_wait_for_sync(module);
+
+ /* Disable module */
+ i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+}
+
+void i2c_slave_reset(
+ struct i2c_slave_module *const module);
+
+/** @} */
+
+/**
+ * \name Read and Write
+ * @{
+ */
+
+enum status_code i2c_slave_write_packet_wait(
+ struct i2c_slave_module *const module,
+ struct i2c_slave_packet *const packet);
+enum status_code i2c_slave_read_packet_wait(
+ struct i2c_slave_module *const module,
+ struct i2c_slave_packet *const packet);
+enum i2c_slave_direction i2c_slave_get_direction_wait(
+ struct i2c_slave_module *const module);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+uint32_t i2c_slave_get_status(
+ struct i2c_slave_module *const module);
+void i2c_slave_clear_status(
+ struct i2c_slave_module *const module,
+ uint32_t status_flags);
+/** @} */
+
+#ifdef FEATURE_I2C_DMA_SUPPORT
+/**
+ * \name SERCOM I2C Slave with DMA Interfaces
+ * @{
+ */
+
+/**
+ * \brief Read SERCOM I<SUP>2</SUP>C interrupt status.
+ *
+ * Read I<SUP>2</SUP>C interrupt status for DMA transfer.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ */
+static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_module *const module)
+{
+ return (uint8_t)module->hw->I2CS.INTFLAG.reg;
+}
+
+/**
+ * \brief Write SERCOM I<SUP>2</SUP>C interrupt status.
+ *
+ * Write I<SUP>2</SUP>C interrupt status for DMA transfer.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ * \param[in] flag Interrupt flag status
+ *
+ */
+static inline void i2c_slave_dma_write_interrupt_status(struct i2c_slave_module *const module,
+ uint8_t flag)
+{
+ module->hw->I2CS.INTFLAG.reg = flag;
+}
+
+/** @} */
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_SLAVE_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master/qs_i2c_master_basic_use.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief SAM SERCOM I2C Master Quick Start Guide + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \page asfdoc_sam0_sercom_i2c_master_basic_use_case Quick Start Guide for SERCOM I2C Master - Basic + * + * In this use case, the I<SUP>2</SUP>C will used and set up as follows: + * - Master mode + * - 100KHz operation speed + * - Not operational in standby + * - 10000 packet timeout value + * - 65535 unknown bus state timeout value + * + * + * \section asfdoc_sam0_sercom_i2c_master_basic_use_case_prereq Prerequisites + * The device must be connected to an I<SUP>2</SUP>C slave. + * + * \section asfdoc_sam0_sercom_i2c_master_basic_use_setup Setup + * + * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_code Code + * The following must be added to the user application: + * + * - A sample buffer to send, a sample buffer to read: + * \snippet qs_i2c_master_basic_use.c packet_data + * + * - Slave address to access: + * \snippet qs_i2c_master_basic_use.c address + * + * - Number of times to try to send packet if it fails: + * \snippet qs_i2c_master_basic_use.c timeout + * + * - Globally accessible module structure: + * \snippet qs_i2c_master_basic_use.c dev_inst + * + * - Function for setting up the module: + * \snippet qs_i2c_master_basic_use.c initialize_i2c + * + * - Add to user application \c main(): + * \snippet qs_i2c_master_basic_use.c init + * + * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_workflow Workflow + * -# Configure and enable module. + * \snippet qs_i2c_master_basic_use.c initialize_i2c + * -# Create and initialize configuration structure. + * \snippet qs_i2c_master_basic_use.c init_conf + * -# Change settings in the configuration. + * \snippet qs_i2c_master_basic_use.c conf_change + * -# Initialize the module with the set configurations. + * \snippet qs_i2c_master_basic_use.c init_module + * -# Enable the module. + * \snippet qs_i2c_master_basic_use.c enable_module + * -# Create a variable to see when we should stop trying to send packet. + * \snippet qs_i2c_master_basic_use.c timeout_counter + * -# Create a packet to send. + * \snippet qs_i2c_master_basic_use.c packet + * + * \section asfdoc_sam0_sercom_i2c_master_basic_use_implemenation Implementation + * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_code Code + * Add to user application \c main(): + * \snippet qs_i2c_master_basic_use.c main + * + * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_workflow Workflow + * -# Write packet to slave. + * \snippet qs_i2c_master_basic_use.c write_packet + * The module will try to send the packet TIMEOUT number of times or until it is + * successfully sent. + * -# Read packet from slave. + * \snippet qs_i2c_master_basic_use.c read_packet + * The module will try to read the packet TIMEOUT number of times or until it is + * successfully read. + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#include <asf.h> +#include <conf_clocks.h> +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master_dma/qs_i2c_master_dma.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,170 @@ +/** + * \file + * + * \brief SAM SERCOM I2C Master Driver with DMA Quick Start Guide + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \page asfdoc_sam0_sercom_i2c_master_dma_use_case Quick Start Guide for Using DMA with SERCOM I2C Master + * + * The supported board list: + * - SAMD21 Xplained Pro + * - SAMR21 Xplained Pro + * - SAML21 Xplained Pro + * + * In this use case, the I<SUP>2</SUP>C will used and set up as follows: + * - Master mode + * - 100KHz operation speed + * - Not operational in standby + * - 10000 packet timeout value + * - 65535 unknown bus state timeout value + * + * + * \section asfdoc_sam0_sercom_i2c_master_dma_use_case_prereq Prerequisites + * The device must be connected to an I<SUP>2</SUP>C slave. + * + * \section asfdoc_sam0_sercom_i2c_master_dma_use_setup Setup + * + * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_code Code + * The following must be added to the user application: + * + * - A sample buffer to send, number of entries to send and address of slave: + * \snippet qs_i2c_master_dma.c packet_data + * + * Number of times to try to send packet if it fails: + * \snippet qs_i2c_master_dma.c timeout + * + * - Globally accessible module structure: + * \snippet qs_i2c_master_dma.c dev_i2c_inst + * + * - Function for setting up the module: + * \snippet qs_i2c_master_dma.c initialize_i2c + * + * - Globally accessible DMA module structure: + * \snippet qs_i2c_master_dma.c dma_resource + * + * - Globally transfer done flag: + * \snippet qs_i2c_master_dma.c transfer_done_flag + * + * - Globally accessible DMA transfer descriptor: + * \snippet qs_i2c_master_dma.c transfer_descriptor + * + * - Function for transfer done callback: + * \snippet qs_i2c_master_dma.c transfer_done + * + * - Function for setting up the DMA resource: + * \snippet qs_i2c_master_dma.c config_dma_resource + * + * - Function for setting up the DMA transfer descriptor: + * \snippet qs_i2c_master_dma.c setup_dma_transfer_descriptor + * - Add to user application \c main(): + * \snippet qs_i2c_master_dma.c init + * + * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow Workflow + * \subsubsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow_i2c Configure and enable SERCOM: + * \snippet qs_i2c_master_dma.c config_i2c + * -# Create and initialize configuration structure. + * \snippet qs_i2c_master_dma.c init_conf + * -# Change settings in the configuration. + * \snippet qs_i2c_master_dma.c conf_change + * -# Initialize the module with the set configurations. + * \snippet qs_i2c_master_dma.c init_module + * -# Enable the module. + * \snippet qs_i2c_master_dma.c enable_module + * + * \subsubsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow_dma Configure DMA + * -# Create a DMA resource configuration structure, which can be filled out to + * adjust the configuration of a single DMA transfer. + * \snippet qs_i2c_master_dma.c dma_setup_1 + * + * -# Initialize the DMA resource configuration struct with the module's + * default values. + * \snippet qs_i2c_master_dma.c dma_setup_2 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Set extra configurations for the DMA resource. It is using peripheral + * trigger. SERCOM TX trigger causes a transaction transfer in + * this example. + * \snippet qs_i2c_master_dma.c dma_setup_3 + * + * -# Allocate a DMA resource with the configurations. + * \snippet qs_i2c_master_dma.c dma_setup_4 + * + * -# Create a DMA transfer descriptor configuration structure, which can be + * filled out to adjust the configuration of a single DMA transfer. + * \snippet qs_i2c_master_dma.c dma_setup_5 + * + * -# Initialize the DMA transfer descriptor configuration struct with the module's + * default values. + * \snippet qs_i2c_master_dma.c dma_setup_6 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Set the specific parameters for a DMA transfer with transfer size, source + * address, and destination address. + * \snippet qs_i2c_master_dma.c dma_setup_7 + * + * -# Create the DMA transfer descriptor. + * \snippet qs_i2c_master_dma.c dma_setup_8 + * + * \section asfdoc_sam0_sercom_i2c_master_dma_use_implemenation Implementation + * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_code Code + * Add to user application \c main(): + * \snippet qs_i2c_master_dma.c main + * + * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_workflow Workflow + * -# Start the DMA transfer job. + * \snippet qs_i2c_master_dma.c start_transfer_job + * + * -# Set the auto address length and enable flag. + * \snippet qs_i2c_master_dma.c set_i2c_addr + * + * -# Waiting for transfer complete. + * \snippet qs_i2c_master_dma.c waiting_for_complete + * + * -# Enter an infinite loop once transfer complete. + * \snippet qs_i2c_master_dma.c inf_loop + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave/qs_i2c_slave_basic_use.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief SAM SERCOM I2C Slave Quick Start Guide with Callbacks + * + * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \page asfdoc_sam0_sercom_i2c_slave_basic_use_case Quick Start Guide for SERCOM I2C Slave - Basic + * + * In this use case, the I<SUP>2</SUP>C will used and set up as follows: + * - Slave mode + * - 100KHz operation speed + * - Not operational in standby + * - 10000 packet timeout value + * + * \section asfdoc_sam0_sercom_i2c_slave_basic_use_case_prereq Prerequisites + * The device must be connected to an I<SUP>2</SUP>C master. + * + * \section asfdoc_sam0_sercom_i2c_slave_basic_use_case_setup_code Setup + * + * \subsection asfdoc_sam0_sercom_i2c_slave_basic_use_setup_code Code + * The following must be added to the user application: + * + * A sample buffer to write from, a sample buffer to read to and length of buffers: + * \snippet qs_i2c_slave_basic_use.c packet_data + * + * Address to respond to: + * \snippet qs_i2c_slave_basic_use.c address + * + * Globally accessible module structure: + * \snippet qs_i2c_slave_basic_use.c module + * + * Function for setting up the module: + * \snippet qs_i2c_slave_basic_use.c initialize_i2c + * + * Add to user application \c main(): + * \snippet qs_i2c_slave_basic_use.c run_initialize_i2c + * + * \subsection asfdoc_sam0_sercom_i2c_slave_basic_use_setup_workflow Workflow + * -# Configure and enable module. + * \snippet qs_i2c_slave_basic_use.c config + * -# Create and initialize configuration structure. + * \snippet qs_i2c_slave_basic_use.c init_conf + * -# Change address and address mode settings in the configuration. + * \snippet qs_i2c_slave_basic_use.c conf_changes + * -# Initialize the module with the set configurations. + * \snippet qs_i2c_slave_basic_use.c init_module + * -# Enable the module. + * \snippet qs_i2c_slave_basic_use.c enable_module + * -# Create variable to hold transfer direction. + * \snippet qs_i2c_slave_basic_use.c dir + * -# Create packet variable to transfer. + * \snippet qs_i2c_slave_basic_use.c pack + * + * \section asfdoc_sam0_sercom_i2c_slave_basic_use_implementation Implementation + * \subsection asfdoc_sam0_sercom_i2c_slave_basic_use_implementation_code Code + * Add to user application \c main(): + * \snippet qs_i2c_slave_basic_use.c while + * \subsection i2c_slave_basic_use_implementation_workflow Workflow + * -# Wait for start condition from master and get transfer direction. + * \snippet qs_i2c_slave_basic_use.c get_dir + * -# Depending on transfer direction, set up buffer to read to or write from, + * and write or read from master. + * \snippet qs_i2c_slave_basic_use.c transfer + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#include <asf.h> +#include <conf_clocks.h> +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave_dma/qs_i2c_slave_dma.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,159 @@ +/** + * \file + * + * \brief SAM SERCOM I2C Slave with DMA Quick Start Guide + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \page asfdoc_sam0_sercom_i2c_slave_dma_use_case Quick Start Guide for Using DMA with SERCOM I2C Slave + * + * The supported board list: + * - SAMD21 Xplained Pro + * - SAMR21 Xplained Pro + * - SAML21 Xplained Pro + * + * In this use case, the I<SUP>2</SUP>C will used and set up as follows: + * - Slave mode + * - 100KHz operation speed + * - Not operational in standby + * - 65535 unknown bus state timeout value + * + * + * \section asfdoc_sam0_sercom_i2c_slave_dma_use_case_prereq Prerequisites + * The device must be connected to an I<SUP>2</SUP>C slave. + * + * \section asfdoc_sam0_sercom_i2c_slave_dma_use_setup Setup + * + * \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_code Code + * The following must be added to the user application: + * + * - Address to respond to: + * \snippet qs_i2c_slave_dma.c address + * + * - A sample buffer to send, number of entries to send and address of slave: + * \snippet qs_i2c_slave_dma.c packet_data + * + * - Globally accessible module structure: + * \snippet qs_i2c_slave_dma.c module + * + * - Function for setting up the module: + * \snippet qs_i2c_slave_dma.c initialize_i2c + * + * - Globally accessible DMA module structure: + * \snippet qs_i2c_slave_dma.c dma_resource + * + * - Globally accessible DMA transfer descriptor: + * \snippet qs_i2c_slave_dma.c transfer_descriptor + * + * - Function for setting up the DMA resource: + * \snippet qs_i2c_slave_dma.c config_dma_resource + * + * - Function for setting up the DMA transfer descriptor: + * \snippet qs_i2c_slave_dma.c setup_dma_transfer_descriptor + * + * - Add to user application \c main(): + * \snippet qs_i2c_slave_dma.c init + * + * \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_workflow Workflow + * \subsubsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_workflow_i2c Configure and enable SERCOM: + * \snippet qs_i2c_slave_dma.c initialize_i2c + * -# Create and initialize configuration structure. + * \snippet qs_i2c_slave_dma.c init_conf + * -# Change settings in the configuration. + * \snippet qs_i2c_slave_dma.c conf_changes + * -# Initialize the module with the set configurations. + * \snippet qs_i2c_slave_dma.c init_module + * -# Enable the module. + * \snippet qs_i2c_slave_dma.c enable_module + * + * \subsubsection asfdoc_sam0_sercom_i2c_slave_dma_use_setup_workflow_dma Configure DMA + * -# Create a DMA resource configuration structure, which can be filled out to + * adjust the configuration of a single DMA transfer. + * \snippet qs_i2c_slave_dma.c dma_setup_1 + * + * -# Initialize the DMA resource configuration struct with the module's + * default values. + * \snippet qs_i2c_slave_dma.c dma_setup_2 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Set extra configurations for the DMA resource. It is using peripheral + * trigger. SERCOM RX trigger causes a beat transfer in this + * example. + * \snippet qs_i2c_slave_dma.c dma_setup_3 + * + * -# Allocate a DMA resource with the configurations. + * \snippet qs_i2c_slave_dma.c dma_setup_4 + * + * -# Create a DMA transfer descriptor configuration structure, which can be + * filled out to adjust the configuration of a single DMA transfer. + * \snippet qs_i2c_slave_dma.c dma_setup_5 + * + * -# Initialize the DMA transfer descriptor configuration struct with the module's + * default values. + * \snippet qs_i2c_slave_dma.c dma_setup_6 + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Set the specific parameters for a DMA transfer with transfer size, source + * address, and destination address. + * \snippet qs_i2c_slave_dma.c dma_setup_7 + * + * -# Create the DMA transfer descriptor. + * \snippet qs_i2c_slave_dma.c dma_setup_8 + * + * \section asfdoc_sam0_sercom_i2c_slave_dma_use_implemenation Implementation + * \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_implemenation_code Code + * Add to user application \c main(): + * \snippet qs_i2c_slave_dma.c main + * + * \subsection asfdoc_sam0_sercom_i2c_slave_dma_use_implemenation_workflow Workflow + * -# Start to wait a packet from master. + * \snippet qs_i2c_slave_dma.c wait_packet + * + * -# Once data ready, clear the address match status. + * \snippet qs_i2c_slave_dma.c clear_status + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,296 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include "sercom.h"
+
+#define SHIFT 32
+#define BAUD_INT_MAX 8192
+#define BAUD_FP_MAX 8
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Configuration structure to save current gclk status.
+ */
+struct _sercom_conf {
+ /* Status of gclk generator initialization. */
+ bool generator_is_set;
+ /* Sercom gclk generator used. */
+ enum gclk_generator generator_source;
+};
+
+static struct _sercom_conf _sercom_config;
+
+
+/**
+ * \internal Calculate 64 bit division, ref can be found in
+ * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
+ */
+static uint64_t long_division(uint64_t n, uint64_t d)
+{
+ int32_t i;
+ uint64_t q = 0, r = 0, bit_shift;
+ for (i = 63; i >= 0; i--) {
+ bit_shift = (uint64_t)1 << i;
+
+ r = r << 1;
+
+ if (n & bit_shift) {
+ r |= 0x01;
+ }
+
+ if (r >= d) {
+ r = r - d;
+ q |= bit_shift;
+ }
+ }
+
+ return q;
+}
+
+/**
+ * \internal Calculate synchronous baudrate value (SPI/UART)
+ */
+enum status_code _sercom_get_sync_baud_val(
+ const uint32_t baudrate,
+ const uint32_t external_clock,
+ uint16_t *const baudvalue)
+{
+ /* Baud value variable */
+ uint16_t baud_calculated = 0;
+ uint32_t clock_value = external_clock;
+
+
+ /* Check if baudrate is outside of valid range. */
+ if (baudrate > (external_clock / 2)) {
+ /* Return with error code */
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ }
+
+ /* Calculate BAUD value from clock frequency and baudrate */
+ clock_value = external_clock / 2;
+ while (clock_value >= baudrate) {
+ clock_value = clock_value - baudrate;
+ baud_calculated++;
+ }
+ baud_calculated = baud_calculated - 1;
+
+ /* Check if BAUD value is more than 255, which is maximum
+ * for synchronous mode */
+ if (baud_calculated > 0xFF) {
+ /* Return with an error code */
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ } else {
+ *baudvalue = baud_calculated;
+ return STATUS_OK;
+ }
+}
+
+/**
+ * \internal Calculate asynchronous baudrate value (UART)
+*/
+enum status_code _sercom_get_async_baud_val(
+ const uint32_t baudrate,
+ const uint32_t peripheral_clock,
+ uint16_t *const baudval,
+ enum sercom_asynchronous_operation_mode mode,
+ enum sercom_asynchronous_sample_num sample_num)
+{
+ /* Temporary variables */
+ uint64_t ratio = 0;
+ uint64_t scale = 0;
+ uint64_t baud_calculated = 0;
+ uint8_t baud_fp;
+ uint32_t baud_int = 0;
+ uint64_t temp1, temp2;
+
+ /* Check if the baudrate is outside of valid range */
+ if ((baudrate * sample_num) > peripheral_clock) {
+ /* Return with error code */
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ }
+
+ if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
+ /* Calculate the BAUD value */
+ temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+ ratio = long_division(temp1, peripheral_clock);
+ scale = ((uint64_t)1 << SHIFT) - ratio;
+ baud_calculated = (65536 * scale) >> SHIFT;
+ } else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
+ for(baud_fp = 0; baud_fp < BAUD_FP_MAX; baud_fp++) {
+ temp1 = BAUD_FP_MAX * (uint64_t)peripheral_clock;
+ temp2 = ((uint64_t)baudrate * sample_num);
+ baud_int = long_division(temp1, temp2);
+ baud_int -= baud_fp;
+ baud_int = baud_int / BAUD_FP_MAX;
+ if(baud_int < BAUD_INT_MAX) {
+ break;
+ }
+ }
+ if(baud_fp == BAUD_FP_MAX) {
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ }
+ baud_calculated = baud_int | (baud_fp << 13);
+ }
+
+ *baudval = baud_calculated;
+ return STATUS_OK;
+}
+#endif
+
+/**
+ * \brief Set GCLK channel to generator.
+ *
+ * This will set the appropriate GCLK channel to the requested GCLK generator.
+ * This will set the generator for all SERCOM instances, and the user will thus
+ * only be able to set the same generator that has previously been set, if any.
+ *
+ * After the generator has been set the first time, the generator can be changed
+ * using the \c force_change flag.
+ *
+ * \param[in] generator_source The generator to use for SERCOM.
+ * \param[in] force_change Force change the generator.
+ *
+ * \return Status code indicating the GCLK generator change operation.
+ * \retval STATUS_OK If the generator update request was
+ * successful.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED If a generator was already configured
+ * and the new configuration was not
+ * forced.
+ */
+enum status_code sercom_set_gclk_generator(
+ const enum gclk_generator generator_source,
+ const bool force_change)
+{
+ /* Check if valid option. */
+ if (!_sercom_config.generator_is_set || force_change) {
+ /* Create and fill a GCLK configuration structure for the new config. */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = generator_source;
+ system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+ system_gclk_chan_enable(SERCOM_GCLK_ID);
+
+ /* Save config. */
+ _sercom_config.generator_source = generator_source;
+ _sercom_config.generator_is_set = true;
+
+ return STATUS_OK;
+ } else if (generator_source == _sercom_config.generator_source) {
+ /* Return status OK if same config. */
+ return STATUS_OK;
+ }
+
+ /* Return invalid config to already initialized GCLK. */
+ return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/** \internal
+ * Creates a switch statement case entry to convert a SERCOM instance and pad
+ * index to the default SERCOM pad MUX setting.
+ */
+#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
+ case (uintptr_t)SERCOM##n: \
+ switch (pad) { \
+ case 0: \
+ return SERCOM##n##_PAD0_DEFAULT; \
+ case 1: \
+ return SERCOM##n##_PAD1_DEFAULT; \
+ case 2: \
+ return SERCOM##n##_PAD2_DEFAULT; \
+ case 3: \
+ return SERCOM##n##_PAD3_DEFAULT; \
+ } \
+ break;
+
+/**
+ * \internal Gets the default PAD pinout for a given SERCOM.
+ *
+ * Returns the pinmux settings for the given SERCOM and pad. This is used
+ * for default configuration of pins.
+ *
+ * \param[in] sercom_module Pointer to the SERCOM module
+ * \param[in] pad PAD to get default pinout for
+ *
+ * \returns The default pinmux for the given SERCOM instance and PAD
+ *
+ */
+uint32_t _sercom_get_default_pad(
+ Sercom *const sercom_module,
+ const uint8_t pad)
+{
+ switch ((uintptr_t)sercom_module) {
+ /* Auto-generate a lookup table for the default SERCOM pad defaults */
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+ }
+
+ Assert(false);
+ return 0;
+}
+
+/**
+ * \internal
+ * Find index of given instance.
+ *
+ * \param[in] sercom_instance Instance pointer.
+ *
+ * \return Index of given instance.
+ */
+uint8_t _sercom_get_sercom_inst_index(
+ Sercom *const sercom_instance)
+{
+ /* Save all available SERCOM instances for compare. */
+ Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+ /* Find index for sercom instance. */
+ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+ if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+ return i;
+ }
+ }
+
+ /* Invalid data given. */
+ Assert(false);
+ return 0;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef SERCOM_H_INCLUDED
+#define SERCOM_H_INCLUDED
+
+#include <compiler.h>
+#include <system.h>
+#include <clock.h>
+#include <system_interrupt.h>
+#include "sercom_pinout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (SAMD10) || (SAMD11)
+
+#if (SERCOM0_GCLK_ID_SLOW == SERCOM1_GCLK_ID_SLOW && \
+ SERCOM0_GCLK_ID_SLOW == SERCOM2_GCLK_ID_SLOW)
+# define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+#else
+# error "SERCOM modules must share the same slow GCLK channel ID."
+#endif
+
+#else
+
+#if (SERCOM0_GCLK_ID_SLOW == SERCOM1_GCLK_ID_SLOW && \
+ SERCOM0_GCLK_ID_SLOW == SERCOM2_GCLK_ID_SLOW && \
+ SERCOM0_GCLK_ID_SLOW == SERCOM3_GCLK_ID_SLOW)
+# define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+#else
+# error "SERCOM modules must share the same slow GCLK channel ID."
+#endif
+
+#endif
+
+#if (0x1ff >= REV_SERCOM)
+# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
+#elif (0x2ff >= REV_SERCOM)
+# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
+#else
+# error "Unknown SYNCBUSY scheme for this SERCOM revision"
+#endif
+
+/**
+ * \brief sercom asynchronous operation mode
+ *
+ * Select sercom asynchronous operation mode
+ */
+enum sercom_asynchronous_operation_mode {
+ SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
+ SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
+};
+
+/**
+ * \brief sercom asynchronous samples per bit
+ *
+ * Select number of samples per bit
+ */
+enum sercom_asynchronous_sample_num {
+ SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
+ SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
+ SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
+};
+
+enum status_code sercom_set_gclk_generator(
+ const enum gclk_generator generator_source,
+ const bool force_change);
+
+enum status_code _sercom_get_sync_baud_val(
+ const uint32_t baudrate,
+ const uint32_t external_clock,
+ uint16_t *const baudval);
+
+enum status_code _sercom_get_async_baud_val(
+ const uint32_t baudrate,
+ const uint32_t peripheral_clock,
+ uint16_t *const baudval,
+ enum sercom_asynchronous_operation_mode mode,
+ enum sercom_asynchronous_sample_num sample_num);
+
+uint32_t _sercom_get_default_pad(
+ Sercom *const sercom_module,
+ const uint8_t pad);
+
+uint8_t _sercom_get_sercom_inst_index(
+ Sercom *const sercom_instance);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SERCOM_H_INCLUDED
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,140 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include "sercom_interrupt.h"
+
+void *_sercom_instances[SERCOM_INST_NUM];
+
+/** Save status of initialized handlers. */
+static bool _handler_table_initialized = false;
+
+/** Void pointers for saving device instance structures. */
+static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
+
+/**
+ * \internal
+ * Default interrupt handler.
+ *
+ * \param[in] instance SERCOM instance used.
+ */
+static void _sercom_default_handler(
+ const uint8_t instance)
+{
+ Assert(false);
+}
+
+/**
+ * \internal
+ * Saves the given callback handler.
+ *
+ * \param[in] instance Instance index.
+ * \param[in] interrupt_handler Pointer to instance callback handler.
+ */
+void _sercom_set_handler(
+ const uint8_t instance,
+ const sercom_handler_t interrupt_handler)
+{
+ /* Initialize handlers with default handler and device instances with 0. */
+ if (_handler_table_initialized == false) {
+ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+ _sercom_interrupt_handlers[i] = &_sercom_default_handler;
+ _sercom_instances[i] = NULL;
+ }
+
+ _handler_table_initialized = true;
+ }
+
+ /* Save interrupt handler. */
+ _sercom_interrupt_handlers[instance] = interrupt_handler;
+}
+
+
+/** \internal
+ * Converts a given SERCOM index to its interrupt vector index.
+ */
+#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
+ SYSTEM_INTERRUPT_MODULE_SERCOM##n,
+
+/** \internal
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.
+ */
+#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
+ void SERCOM##n##_Handler(void) \
+ { \
+ _sercom_interrupt_handlers[n](n); \
+ }
+
+/**
+ * \internal
+ * Returns the system interrupt vector.
+ *
+ * \param[in] sercom_instance Instance pointer
+ *
+ * \return Enum of system interrupt vector
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
+ */
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+ Sercom *const sercom_instance)
+{
+ const uint8_t sercom_int_vectors[SERCOM_INST_NUM] = {
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+ };
+
+ /* Retrieve the index of the SERCOM being requested */
+ uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+
+ /* Get the vector number from the lookup table for the requested SERCOM */
+ return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+}
+
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef SERCOM_INTERRUPT_H_INCLUDED
+#define SERCOM_INTERRUPT_H_INCLUDED
+
+#include "sercom.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Look-up table for device instances. */
+extern void *_sercom_instances[SERCOM_INST_NUM];
+
+typedef void (*sercom_handler_t)(uint8_t instance);
+
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+ Sercom *const sercom_instance);
+
+void _sercom_set_handler(
+ const uint8_t instance,
+ const sercom_handler_t interrupt_handler);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SERCOM_INTERRUPT_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_pinout.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SAM SERCOM Module Pinout Definitions + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ +#ifndef SERCOM_PINOUT_H_INCLUDED +#define SERCOM_PINOUT_H_INCLUDED + +#include <compiler.h> + +#if SAMR21E +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 + +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 + +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 + +/* SERCOM3 */ +#define SERCOM3_PAD0_DEFAULT PINMUX_PA27F_SERCOM3_PAD0 +#define SERCOM3_PAD1_DEFAULT PINMUX_PA28F_SERCOM3_PAD1 +#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 +#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 + +/* SERCOM4 */ +#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 +#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 +#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 +#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 + +/* SERCOM5 */ +#define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0 +#define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1 +#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 +#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 + +#elif SAMR21G +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 + +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 + +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 + +/* SERCOM3 */ +#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 +#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 +#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 +#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 + +/* SERCOM4 */ +#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 +#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 +#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 +#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 + +/* SERCOM5 */ +#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 +#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 +#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 +#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 + +#elif (SAMD10) || (SAMD11) +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 + +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 + +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3 + +#else +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 + +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 + +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 + +/* SERCOM3 */ +#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 +#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 +#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 +#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 + +/* SERCOM4 */ +#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0 +#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1 +#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 +#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 + +/* SERCOM5 */ +#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 +#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 +#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 +#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 +#endif + +#endif /* SERCOM_PINOUT_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,724 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include "usart.h"
+#include <pinmux.h>
+#if USART_CALLBACK_MODE == true
+# include "usart_interrupt.h"
+#endif
+
+/**
+ * \internal
+ * Set Configuration of the USART module
+ */
+static enum status_code _usart_set_config(
+ struct usart_module *const module,
+ const struct usart_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Index for generic clock */
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ /* Cache new register values to minimize the number of register writes */
+ uint32_t ctrla = 0;
+ uint32_t ctrlb = 0;
+ uint16_t baud = 0;
+
+ enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+ switch (config->sample_rate) {
+ case USART_SAMPLE_RATE_16X_ARITHMETIC:
+ mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+ break;
+ case USART_SAMPLE_RATE_8X_ARITHMETIC:
+ mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+ break;
+ case USART_SAMPLE_RATE_3X_ARITHMETIC:
+ mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+ break;
+ case USART_SAMPLE_RATE_16X_FRACTIONAL:
+ mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+ break;
+ case USART_SAMPLE_RATE_8X_FRACTIONAL:
+ mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+ break;
+ }
+#endif
+
+ /* Set data order, internal muxing, and clock polarity */
+ ctrla = (uint32_t)config->data_order |
+ (uint32_t)config->mux_setting |
+#ifdef FEATURE_USART_OVER_SAMPLE
+ config->sample_adjustment |
+ config->sample_rate |
+#endif
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+ (config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+#endif
+ (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+
+ enum status_code status_code = STATUS_OK;
+
+ /* Get baud value from mode and clock */
+ switch (config->transfer_mode) {
+ case USART_TRANSFER_SYNCHRONOUSLY:
+ if (!config->use_external_clock) {
+ status_code = _sercom_get_sync_baud_val(config->baudrate,
+ system_gclk_chan_get_hz(gclk_index), &baud);
+ }
+
+ break;
+
+ case USART_TRANSFER_ASYNCHRONOUSLY:
+ if (config->use_external_clock) {
+ status_code =
+ _sercom_get_async_baud_val(config->baudrate,
+ config->ext_clock_freq, &baud, mode, sample_num);
+ } else {
+ status_code =
+ _sercom_get_async_baud_val(config->baudrate,
+ system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+ }
+
+ break;
+ }
+
+ /* Check if calculating the baudrate failed */
+ if (status_code != STATUS_OK) {
+ /* Abort */
+ return status_code;
+ }
+
+#ifdef FEATURE_USART_IRDA
+ if(config->encoding_format_enable) {
+ usart_hw->RXPL.reg = config->receive_pulse_length;
+ }
+#endif
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /*Set baud val */
+ usart_hw->BAUD.reg = baud;
+
+ /* Set sample mode */
+ ctrla |= config->transfer_mode;
+
+ if (config->use_external_clock == false) {
+ ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+ } else {
+ ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
+ }
+
+ /* Set stopbits, character size and enable transceivers */
+ ctrlb = (uint32_t)config->stopbits | (uint32_t)config->character_size |
+#ifdef FEATURE_USART_IRDA
+ (config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ (config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ (config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+#endif
+ (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+ (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+
+ /* Check parity mode bits */
+ if (config->parity != USART_PARITY_NONE) {
+#ifdef FEATURE_USART_LIN_SLAVE
+ if(config->lin_slave_enable) {
+ ctrla |= SERCOM_USART_CTRLA_FORM(0x5);
+ } else {
+ ctrla |= SERCOM_USART_CTRLA_FORM(1);
+ }
+#else
+ ctrla |= SERCOM_USART_CTRLA_FORM(1);
+#endif
+ ctrlb |= config->parity;
+ } else {
+#ifdef FEATURE_USART_LIN_SLAVE
+ if(config->lin_slave_enable) {
+ ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+ } else {
+ ctrla |= SERCOM_USART_CTRLA_FORM(0);
+ }
+#else
+ ctrla |= SERCOM_USART_CTRLA_FORM(0);
+#endif
+ }
+
+ /* Set whether module should run in standby. */
+ if (config->run_in_standby || system_is_debugger_present()) {
+ ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+ }
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Write configuration to CTRLB */
+ usart_hw->CTRLB.reg = ctrlb;
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Write configuration to CTRLA */
+ usart_hw->CTRLA.reg = ctrla;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the device
+ *
+ * Initializes the USART device based on the setting specified in the
+ * configuration struct.
+ *
+ * \param[out] module Pointer to USART device
+ * \param[in] hw Pointer to USART hardware instance
+ * \param[in] config Pointer to configuration struct
+ *
+ * \return Status of the initialization.
+ *
+ * \retval STATUS_OK The initialization was successful
+ * \retval STATUS_BUSY The USART module is busy
+ * resetting
+ * \retval STATUS_ERR_DENIED The USART have not been disabled in
+ * advance of initialization
+ * \retval STATUS_ERR_INVALID_ARG The configuration struct contains
+ * invalid configuration
+ * \retval STATUS_ERR_ALREADY_INITIALIZED The SERCOM instance has already been
+ * initialized with different clock
+ * configuration
+ * \retval STATUS_ERR_BAUD_UNAVAILABLE The BAUD rate given by the
+ * configuration
+ * struct cannot be reached with
+ * the current clock configuration
+ */
+enum status_code usart_init(
+ struct usart_module *const module,
+ Sercom *const hw,
+ const struct usart_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(hw);
+ Assert(config);
+
+ enum status_code status_code = STATUS_OK;
+
+ /* Assign module pointer to software instance struct */
+ module->hw = hw;
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+#if (SAML21)
+ uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+#else
+ uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+#endif
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+ /* The module is busy resetting itself */
+ return STATUS_BUSY;
+ }
+
+ if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+ /* Check the module is enabled */
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Turn on module in PM */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+ /* Set up the GCLK for the module */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = config->generator_source;
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+ system_gclk_chan_enable(gclk_index);
+ sercom_set_gclk_generator(config->generator_source, false);
+
+ /* Set character size */
+ module->character_size = config->character_size;
+
+ /* Set transmitter and receiver status */
+ module->receiver_enabled = config->receiver_enable;
+ module->transmitter_enabled = config->transmitter_enable;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+ module->lin_slave_enabled = config->lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ module->start_frame_detection_enabled = config->start_frame_detection_enable;
+#endif
+ /* Set configuration according to the config struct */
+ status_code = _usart_set_config(module, config);
+ if(status_code != STATUS_OK) {
+ return status_code;
+ }
+
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+ uint32_t pad_pinmuxes[] = {
+ config->pinmux_pad0, config->pinmux_pad1,
+ config->pinmux_pad2, config->pinmux_pad3
+ };
+
+ /* Configure the SERCOM pins according to the user configuration */
+ for (uint8_t pad = 0; pad < 4; pad++) {
+ uint32_t current_pinmux = pad_pinmuxes[pad];
+
+ if (current_pinmux == PINMUX_DEFAULT) {
+ current_pinmux = _sercom_get_default_pad(hw, pad);
+ }
+
+ if (current_pinmux != PINMUX_UNUSED) {
+ pin_conf.mux_position = current_pinmux & 0xFFFF;
+ system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+ }
+ }
+
+#if USART_CALLBACK_MODE == true
+ /* Initialize parameters */
+ for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
+ module->callback[i] = NULL;
+ }
+
+ module->tx_buffer_ptr = NULL;
+ module->rx_buffer_ptr = NULL;
+ module->remaining_tx_buffer_length = 0x0000;
+ module->remaining_rx_buffer_length = 0x0000;
+ module->callback_reg_mask = 0x00;
+ module->callback_enable_mask = 0x00;
+ module->rx_status = STATUS_OK;
+ module->tx_status = STATUS_OK;
+
+ /* Set interrupt handler and register USART software module struct in
+ * look-up table */
+ uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+ _sercom_set_handler(instance_index, _usart_interrupt_handler);
+ _sercom_instances[instance_index] = module;
+#endif
+
+ return status_code;
+}
+
+/**
+ * \brief Transmit a character via the USART
+ *
+ * This blocking function will transmit a single character via the
+ * USART.
+ *
+ * \param[in] module Pointer to the software instance struct
+ * \param[in] tx_data Data to transfer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK If the operation was completed
+ * \retval STATUS_BUSY If the operation was not completed, due to the USART
+ * module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_wait(
+ struct usart_module *const module,
+ const uint16_t tx_data)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Check that the transmitter is enabled */
+ if (!(module->transmitter_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+#if USART_CALLBACK_MODE == true
+ /* Check if the USART is busy doing asynchronous operation. */
+ if (module->remaining_tx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+
+#else
+ /* Check if USART is ready for new data */
+ if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+ /* Return error code */
+ return STATUS_BUSY;
+ }
+#endif
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Write data to USART module */
+ usart_hw->DATA.reg = tx_data;
+
+ while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+ /* Wait until data is sent */
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Receive a character via the USART
+ *
+ * This blocking function will receive a character via the USART.
+ *
+ * \param[in] module Pointer to the software instance struct
+ * \param[out] rx_data Pointer to received data
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK If the operation was completed
+ * \retval STATUS_BUSY If the operation was not completed,
+ * due to the USART module being busy
+ * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
+ * due to configuration mismatch between USART
+ * and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
+ * due to the baudrate being too low or the
+ * system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due to
+ * data being corrupted
+ * \retval STATUS_ERR_DENIED If the receiver is not enabled
+ */
+enum status_code usart_read_wait(
+ struct usart_module *const module,
+ uint16_t *const rx_data)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Error variable */
+ uint8_t error_code;
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Check that the receiver is enabled */
+ if (!(module->receiver_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+#if USART_CALLBACK_MODE == true
+ /* Check if the USART is busy doing asynchronous operation. */
+ if (module->remaining_rx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ /* Check if USART has new data */
+ if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+ /* Return error code */
+ return STATUS_BUSY;
+ }
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Read out the status code and mask away all but the 3 LSBs*/
+ error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+ /* Check if an error has occurred during the receiving */
+ if (error_code) {
+ /* Check which error occurred */
+ if (error_code & SERCOM_USART_STATUS_FERR) {
+ /* Clear flag by writing a 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+
+ return STATUS_ERR_BAD_FORMAT;
+ } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+ /* Clear flag by writing a 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+
+ return STATUS_ERR_OVERFLOW;
+ } else if (error_code & SERCOM_USART_STATUS_PERR) {
+ /* Clear flag by writing a 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+
+ return STATUS_ERR_BAD_DATA;
+ }
+#ifdef FEATURE_USART_LIN_SLAVE
+ else if (error_code & SERCOM_USART_STATUS_ISF) {
+ /* Clear flag by writing 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF;
+
+ return STATUS_ERR_PROTOCOL;
+ }
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ else if (error_code & SERCOM_USART_STATUS_COLL) {
+ /* Clear flag by writing 1 to it
+ * return with an error code */
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL;
+
+ return STATUS_ERR_PACKET_COLLISION;
+ }
+#endif
+ }
+
+ /* Read data from USART module */
+ *rx_data = usart_hw->DATA.reg;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Transmit a buffer of characters via the USART
+ *
+ * This blocking function will transmit a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c _job) functions is
+ * not recommended as it has no functionality to check if there is an
+ * ongoing interrupt driven operation running or not.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] tx_data Pointer to data to transmit
+ * \param[in] length Number of characters to transmit
+ *
+ * \note if using 9-bit data, the array that *tx_data point to should be defined
+ * as uint16_t array and should be casted to uint8_t* pointer. Because it
+ * is an address pointer, the highest byte is not discarded. For example:
+ * \code
+ #define TX_LEN 3
+ uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+ usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
+ \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ * arguments
+ * \retval STATUS_ERR_TIMEOUT If operation was not completed, due to USART
+ * module timing out
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_wait(
+ struct usart_module *const module,
+ const uint8_t *tx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Check if the buffer length is valid */
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check that the transmitter is enabled */
+ if (!(module->transmitter_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ uint16_t tx_pos = 0;
+
+ /* Blocks while buffer is being transferred */
+ while (length--) {
+ /* Wait for the USART to be ready for new data and abort
+ * operation if it doesn't get ready within the timeout*/
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
+ break;
+ } else if (i == USART_TIMEOUT) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+
+ /* Data to send is at least 8 bits long */
+ uint16_t data_to_send = tx_data[tx_pos++];
+
+ /* Check if the character size exceeds 8 bit */
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+ data_to_send |= (tx_data[tx_pos++] << 8);
+ }
+
+ /* Send the data through the USART module */
+ usart_write_wait(module, data_to_send);
+ }
+
+ /* Wait until Transmit is complete or timeout */
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
+ break;
+ } else if (i == USART_TIMEOUT) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Receive a buffer of \c length characters via the USART
+ *
+ * This blocking function will receive a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c *_job)
+ * functions is not recommended as it has no functionality to check if
+ * there is an ongoing interrupt driven operation running or not.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[out] rx_data Pointer to receive buffer
+ * \param[in] length Number of characters to receive
+ *
+ * \note if using 9-bit data, the array that *rx_data point to should be defined
+ * as uint16_t array and should be casted to uint8_t* pointer. Because it
+ * is an address pointer, the highest byte is not discarded. For example:
+ * \code
+ #define RX_LEN 3
+ uint16_t rx_buf[RX_LEN] = {0x0,};
+ usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
+ \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to an
+ * invalid argument being supplied
+ * \retval STATUS_ERR_TIMEOUT If operation was not completed, due
+ * to USART module timing out
+ * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
+ * due to a configuration mismatch
+ * between USART and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
+ * due to the baudrate being too low or the
+ * system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due
+ * to data being corrupted
+ * \retval STATUS_ERR_DENIED If the receiver is not enabled
+ */
+enum status_code usart_read_buffer_wait(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Check if the buffer length is valid */
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check that the receiver is enabled */
+ if (!(module->receiver_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ uint16_t rx_pos = 0;
+
+ /* Blocks while buffer is being received */
+ while (length--) {
+ /* Wait for the USART to have new data and abort operation if it
+ * doesn't get ready within the timeout*/
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
+ break;
+ } else if (i == USART_TIMEOUT) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+
+ enum status_code retval;
+ uint16_t received_data = 0;
+
+ retval = usart_read_wait(module, &received_data);
+
+ if (retval != STATUS_OK) {
+ /* Overflow, abort */
+ return retval;
+ }
+
+ /* Read value will be at least 8-bits long */
+ rx_data[rx_pos++] = received_data;
+
+ /* If 9-bit data, write next received byte to the buffer */
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+ rx_data[rx_pos++] = (received_data >> 8);
+ }
+ }
+
+ return STATUS_OK;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1267 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef USART_H_INCLUDED
+#define USART_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_sercom_usart_group SAM Serial USART Driver (SERCOM USART)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the SERCOM module in its USART mode to transfer or receive
+ * USART data frames. The following driver API modes are covered by this
+ * manual:
+ *
+ * - Polled APIs
+ * \if USART_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_usart_prerequisites
+ * - \ref asfdoc_sam0_sercom_usart_overview
+ * - \ref asfdoc_sam0_sercom_usart_special_considerations
+ * - \ref asfdoc_sam0_sercom_usart_extra_info
+ * - \ref asfdoc_sam0_sercom_usart_examples
+ * - \ref asfdoc_sam0_sercom_usart_api_overview
+ *
+ * \section asfdoc_sam0_sercom_usart_prerequisites Prerequisites
+ *
+ * To use the USART you need to have a GCLK generator enabled and running
+ * that can be used as the SERCOM clock source. This can either be configured
+ * in conf_clocks.h or by using the system clock driver.
+ *
+ * \section asfdoc_sam0_sercom_usart_overview Module Overview
+ *
+ * This driver will use one (or more) SERCOM interfaces on the system
+ * and configure it to run as a USART interface in either synchronous
+ * or asynchronous mode.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_SYNC_SCHEME_V2</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_OVER_SAMPLE</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_HARDWARE_FLOW_CONTROL</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_IRDA</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_LIN_SLAVE</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_COLLISION_DECTION</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_START_FRAME_DECTION</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION</td>
+ * <td>SAM D21/R21/D10/D11/L21</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_frame_format Frame Format
+ *
+ * Communication is based on frames, where the frame format can be customized
+ * to accommodate a wide range of standards. A frame consists of a start bit,
+ * a number of data bits, an optional parity bit for error detection as well
+ * as a configurable length stop bit(s) - see
+ * \ref asfdoc_sam0_sercom_usart_frame_diagram "the figure below".
+ * \ref asfdoc_sam0_sercom_usart_frame_params "The table below" shows the
+ * available parameters you can change in a frame.
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_params
+ * <table>
+ * <caption>USART Frame Parameters</caption>
+ * <tr>
+ * <th>Parameter</th>
+ * <th>Options</th>
+ * </tr>
+ * <tr>
+ * <td>Start bit</td>
+ * <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>Data bits</td>
+ * <td>5, 6, 7, 8, 9</td>
+ * </tr>
+ * <tr>
+ * <td>Parity bit</td>
+ * <td>None, Even, Odd</td>
+ * </tr>
+ * <tr>
+ * <td>Stop bits</td>
+ * <td>1, 2</td>
+ * </tr>
+ * </table>
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_diagram
+ * \image html usart_frame.svg "USART Frame Overview" width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_sync Synchronous Mode
+ *
+ * In synchronous mode a dedicated clock line is provided; either by the USART
+ * itself if in master mode, or by an external master if in slave mode.
+ * Maximum transmission speed is the same as the GCLK clocking the USART
+ * peripheral when in slave mode, and the GCLK divided by two if in
+ * master mode. In synchronous mode the interface needs three lines to
+ * communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ * - XCK (Clock pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_sync_sampling Data Sampling
+ * In synchronous mode the data is sampled on either the rising or falling edge
+ * of the clock signal. This is configured by setting the clock polarity in the
+ * configuration struct.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_async Asynchronous Mode
+ *
+ * In asynchronous mode no dedicated clock line is used, and the communication
+ * is based on matching the clock speed on the transmitter and receiver. The
+ * clock is generated from the internal SERCOM baudrate generator, and the
+ * frames are synchronized by using the frame start bits. Maximum transmission
+ * speed is limited to the SERCOM GCLK divided by 16.
+ * In asynchronous mode the interface only needs two lines to communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_async_clock_matching Transmitter/receiver Clock Matching
+ *
+ * For successful transmit and receive using the asynchronous mode the receiver
+ * and transmitter clocks needs to be closely matched. When receiving a frame
+ * that does not match the selected baudrate closely enough the receiver will
+ * be unable to synchronize the frame(s), and garbage transmissions will
+ * result.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_parity Parity
+ * Parity can be enabled to detect if a transmission was in error. This is done
+ * by counting the number of "1" bits in the frame. When using Even parity the
+ * parity bit will be set if the total number of "1"s in the frame are an even
+ * number. If using Odd parity the parity bit will be set if the total number
+ * of "1"s are Odd.
+ *
+ * When receiving a character the receiver will count the number of "1"s in the
+ * frame and give an error if the received frame and parity bit disagree.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_pin_configuration GPIO Configuration
+ *
+ * The SERCOM module has four internal pads; the RX pin can be placed freely on
+ * any one of the four pads, and the TX and XCK pins have two predefined
+ * positions that can be selected as a pair. The pads can then be routed to an
+ * external GPIO pin using the normal pin multiplexing scheme on the SAM.
+ *
+ * \section asfdoc_sam0_sercom_usart_special_considerations Special Considerations
+ *
+ * \if USART_CALLBACK_MODE
+ * Never execute large portions of code in the callbacks. These
+ * are run from the interrupt routine, and thus having long callbacks will
+ * keep the processor in the interrupt handler for an equally long time.
+ * A common way to handle this is to use global flags signaling the
+ * main application that an interrupt event has happened, and only do the
+ * minimal needed processing in the callback.
+ * \else
+ * No special considerations.
+ * \endif
+ *
+ * \section asfdoc_sam0_sercom_usart_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_sercom_usart_extra. This includes:
+ * - \ref asfdoc_sam0_sercom_usart_extra_acronyms
+ * - \ref asfdoc_sam0_sercom_usart_extra_dependencies
+ * - \ref asfdoc_sam0_sercom_usart_extra_errata
+ * - \ref asfdoc_sam0_sercom_usart_extra_history
+ *
+ * \section asfdoc_sam0_sercom_usart_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_usart_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_usart_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <sercom.h>
+#include <pinmux.h>
+
+#define USART_CALLBACK_MODE true
+
+#if USART_CALLBACK_MODE == true
+# include <sercom_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define SERCOM USART features set according to different device family.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || defined(__DOXYGEN__)
+/** Usart sync scheme version 2. */
+# define FEATURE_USART_SYNC_SCHEME_V2
+/** Usart over sampling. */
+# define FEATURE_USART_OVER_SAMPLE
+/** Usart hardware control flow. */
+# define FEATURE_USART_HARDWARE_FLOW_CONTROL
+/** IrDA mode. */
+# define FEATURE_USART_IRDA
+/** LIN slave mode. */
+# define FEATURE_USART_LIN_SLAVE
+/** Usart collision detection. */
+# define FEATURE_USART_COLLISION_DECTION
+/** Usart start frame detection. */
+# define FEATURE_USART_START_FRAME_DECTION
+/** Usart start buffer overflow notification. */
+# define FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+#endif
+/*@}*/
+
+#ifndef PINMUX_DEFAULT
+/** Default pinmux. */
+# define PINMUX_DEFAULT 0
+#endif
+
+#ifndef PINMUX_UNUSED
+/** Unused pinmux. */
+# define PINMUX_UNUSED 0xFFFFFFFF
+#endif
+
+#ifndef USART_TIMEOUT
+/** USART timeout value. */
+# define USART_TIMEOUT 0xFFFF
+#endif
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART Callback enum
+ *
+ * Callbacks for the Asynchronous USART driver.
+ */
+enum usart_callback {
+ /** Callback for buffer transmitted. */
+ USART_CALLBACK_BUFFER_TRANSMITTED,
+ /** Callback for buffer received. */
+ USART_CALLBACK_BUFFER_RECEIVED,
+ /** Callback for error. */
+ USART_CALLBACK_ERROR,
+#ifdef FEATURE_USART_LIN_SLAVE
+ /** Callback for break character is received. */
+ USART_CALLBACK_BREAK_RECEIVED,
+#endif
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+ /** Callback for a change is detected on the CTS pin. */
+ USART_CALLBACK_CTS_INPUT_CHANGE,
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ /** Callback for a start condition is detected on the RxD line. */
+ USART_CALLBACK_START_RECEIVED,
+#endif
+# if !defined(__DOXYGEN__)
+ /** Number of available callbacks. */
+ USART_CALLBACK_N,
+# endif
+};
+#endif
+
+/**
+ * \brief USART Data Order enum
+ *
+ * The data order decides which of MSB or LSB is shifted out first when data is
+ * transferred.
+ */
+enum usart_dataorder {
+ /** The MSB will be shifted out first during transmission,
+ * and shifted in first during reception. */
+ USART_DATAORDER_MSB = 0,
+ /** The LSB will be shifted out first during transmission,
+ * and shifted in first during reception. */
+ USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,
+};
+
+/**
+ * \brief USART Transfer mode enum
+ *
+ * Select USART transfer mode.
+ */
+enum usart_transfer_mode {
+ /** Transfer of data is done synchronously. */
+ USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),
+ /** Transfer of data is done asynchronously. */
+ USART_TRANSFER_ASYNCHRONOUSLY = 0
+};
+
+/**
+ * \brief USART Parity enum
+ *
+ * Select parity USART parity mode.
+ */
+enum usart_parity {
+ /** For odd parity checking, the parity bit will be set if number of
+ * ones being transferred is even. */
+ USART_PARITY_ODD = SERCOM_USART_CTRLB_PMODE,
+
+ /** For even parity checking, the parity bit will be set if number of
+ * ones being received is odd. */
+ USART_PARITY_EVEN = 0,
+
+ /** No parity checking will be executed, and there will be no parity bit
+ * in the received frame. */
+ USART_PARITY_NONE = 0xFF,
+};
+
+/**
+ * \brief USART signal MUX settings
+ *
+ * Set the functionality of the SERCOM pins.
+ *
+ * See \ref asfdoc_sam0_sercom_usart_mux_settings for a description of the
+ * various MUX setting options.
+ */
+enum usart_signal_mux_settings {
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+ /** MUX setting RX_0_TX_0_XCK_1. */
+ USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_0_TX_2_XCK_3. */
+ USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3. */
+ USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)),
+ /** MUX setting RX_1_TX_0_XCK_1. */
+ USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_1_TX_2_XCK_3. */
+ USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3. */
+ USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)),
+ /** MUX setting RX_2_TX_0_XCK_1. */
+ USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_2_TX_2_XCK_3. */
+ USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3. */
+ USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)),
+ /** MUX setting RX_3_TX_0_XCK_1. */
+ USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_3_TX_2_XCK_3. */
+ USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3. */
+ USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)),
+#else
+ /** MUX setting RX_0_TX_0_XCK_1. */
+ USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),
+ /** MUX setting RX_0_TX_2_XCK_3. */
+ USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),
+ /** MUX setting RX_1_TX_0_XCK_1. */
+ USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),
+ /** MUX setting RX_1_TX_2_XCK_3. */
+ USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),
+ /** MUX setting RX_2_TX_0_XCK_1. */
+ USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),
+ /** MUX setting RX_2_TX_2_XCK_3. */
+ USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),
+ /** MUX setting RX_3_TX_0_XCK_1. */
+ USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),
+ /** MUX setting RX_3_TX_2_XCK_3. */
+ USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),
+#endif
+};
+
+/**
+ * \brief USART Stop Bits enum
+ *
+ * Number of stop bits for a frame.
+ */
+enum usart_stopbits {
+ /** Each transferred frame contains one stop bit. */
+ USART_STOPBITS_1 = 0,
+ /** Each transferred frame contains two stop bits. */
+ USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,
+};
+
+/**
+ * \brief USART Character Size
+ *
+ * Number of bits for the character sent in a frame.
+ */
+enum usart_character_size {
+ /** The char being sent in a frame is five bits long. */
+ USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),
+ /** The char being sent in a frame is six bits long. */
+ USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),
+ /** The char being sent in a frame is seven bits long. */
+ USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),
+ /** The char being sent in a frame is eight bits long. */
+ USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),
+ /** The char being sent in a frame is nine bits long. */
+ USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),
+};
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+/**
+ * \brief USART Sample Rate
+ *
+ * The value of sample rate and baudrate generation mode.
+ */
+enum usart_sample_rate {
+ /** 16x over-sampling using arithmetic baudrate generation. */
+ USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0),
+ /** 16x over-sampling using fractional baudrate generation. */
+ USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1),
+ /** 8x over-sampling using arithmetic baudrate generation. */
+ USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2),
+ /** 8x over-sampling using fractional baudrate generation. */
+ USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3),
+ /** 3x over-sampling using arithmetic baudrate generation. */
+ USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4),
+};
+
+/**
+ * \brief USART Sample Adjustment
+ *
+ * The value of sample number used for majority voting.
+ */
+enum usart_sample_adjustment {
+ /** The first, middle and last sample number used for majority voting is 7-8-9. */
+ USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0),
+ /** The first, middle and last sample number used for majority voting is 9-10-11. */
+ USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1),
+ /** The first, middle and last sample number used for majority voting is 11-12-13. */
+ USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2),
+ /** The first, middle and last sample number used for majority voting is 13-14-15. */
+ USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3),
+};
+#endif
+
+/**
+ * \brief USART Transceiver
+ *
+ * Select Receiver or Transmitter.
+ */
+enum usart_transceiver_type {
+ /** The parameter is for the Receiver. */
+ USART_TRANSCEIVER_RX,
+ /** The parameter is for the Transmitter. */
+ USART_TRANSCEIVER_TX,
+};
+
+/**
+ * \brief USART configuration struct
+ *
+ * Configuration options for USART.
+ */
+struct usart_config {
+ /** USART bit order (MSB or LSB first). */
+ enum usart_dataorder data_order;
+ /** USART in asynchronous or synchronous mode. */
+ enum usart_transfer_mode transfer_mode;
+ /** USART parity. */
+ enum usart_parity parity;
+ /** Number of stop bits. */
+ enum usart_stopbits stopbits;
+ /** USART character size. */
+ enum usart_character_size character_size;
+ /** USART pin out. */
+ enum usart_signal_mux_settings mux_setting;
+#ifdef FEATURE_USART_OVER_SAMPLE
+ /** USART sample rate. */
+ enum usart_sample_rate sample_rate;
+ /** USART sample adjustment. */
+ enum usart_sample_adjustment sample_adjustment;
+#endif
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+ /** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs.*/
+ bool immediate_buffer_overflow_notification;
+#endif
+#ifdef FEATURE_USART_IRDA
+ /** Enable IrDA encoding format. */
+ bool encoding_format_enable;
+ /** The minimum pulse length that is required for a pulse to be accepted by the IrDA receiver. */
+ uint8_t receive_pulse_length;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+ /** Enable LIN Slave Support. */
+ bool lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ /** Enable start of frame dection. */
+ bool start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ /** Enable collision dection. */
+ bool collision_detection_enable;
+#endif
+ /** USART baudrate. */
+ uint32_t baudrate;
+ /** Enable receiver. */
+ bool receiver_enable;
+ /** Enable transmitter. */
+ bool transmitter_enable;
+
+ /** USART Clock Polarity.
+ * If true, data changes on falling XCK edge and
+ * is sampled at rising edge.
+ * If false, data changes on rising XCK edge and
+ * is sampled at falling edge.
+ * */
+ bool clock_polarity_inverted;
+
+ /** States whether to use the external clock applied to the XCK pin.
+ * In synchronous mode the shift register will act directly on the XCK clock.
+ * In asynchronous mode the XCK will be the input to the USART hardware module.
+ */
+ bool use_external_clock;
+ /** External clock frequency in synchronous mode.
+ * This must be set if \c use_external_clock is true. */
+ uint32_t ext_clock_freq;
+ /** If true the USART will be kept running in Standby sleep mode. */
+ bool run_in_standby;
+ /** GCLK generator source. */
+ enum gclk_generator generator_source;
+ /** PAD0 pinmux. */
+ uint32_t pinmux_pad0;
+ /** PAD1 pinmux. */
+ uint32_t pinmux_pad1;
+ /** PAD2 pinmux. */
+ uint32_t pinmux_pad2;
+ /** PAD3 pinmux. */
+ uint32_t pinmux_pad3;
+};
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART module instance
+ *
+ * Forward Declaration for the device instance.
+ */
+struct usart_module;
+
+/**
+ * \brief USART callback type
+ *
+ * Type of the callback functions.
+ */
+typedef void (*usart_callback_t)(const struct usart_module *const module);
+#endif
+
+/**
+ * \brief SERCOM USART driver software device instance structure.
+ *
+ * SERCOM USART driver software instance structure, used to retain software
+ * state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ * application; they are reserved for module-internal use only.
+ */
+struct usart_module {
+#if !defined(__DOXYGEN__)
+ /** Pointer to the hardware instance. */
+ Sercom *hw;
+ /** Module lock. */
+ volatile bool locked;
+ /** Character size of the data being transferred. */
+ enum usart_character_size character_size;
+ /** Receiver enabled. */
+ bool receiver_enabled;
+ /** Transmitter enabled. */
+ bool transmitter_enabled;
+#ifdef FEATURE_USART_LIN_SLAVE
+ /** LIN Slave Support enabled. */
+ bool lin_slave_enabled;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ /** Start of frame dection enabled. */
+ bool start_frame_detection_enabled;
+#endif
+# if USART_CALLBACK_MODE == true
+ /** Array to store callback function pointers in. */
+ usart_callback_t callback[USART_CALLBACK_N];
+ /** Buffer pointer to where the next received character will be put. */
+ volatile uint8_t *rx_buffer_ptr;
+
+ /** Buffer pointer to where the next character will be transmitted from.
+ **/
+ volatile uint8_t *tx_buffer_ptr;
+ /** Remaining characters to receive. */
+ volatile uint16_t remaining_rx_buffer_length;
+ /** Remaining characters to transmit. */
+ volatile uint16_t remaining_tx_buffer_length;
+ /** Bit mask for callbacks registered. */
+ uint8_t callback_reg_mask;
+ /** Bit mask for callbacks enabled. */
+ uint8_t callback_enable_mask;
+ /** Holds the status of the ongoing or last read operation. */
+ volatile enum status_code rx_status;
+ /** Holds the status of the ongoing or last write operation. */
+ volatile enum status_code tx_status;
+# endif
+#endif
+};
+
+/**
+* \name Lock/Unlock
+* @{
+*/
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code usart_lock(
+ struct usart_module *const module)
+{
+ enum status_code status;
+
+ system_interrupt_enter_critical_section();
+
+ if (module->locked) {
+ status = STATUS_BUSY;
+ } else {
+ module->locked = true;
+ status = STATUS_OK;
+ }
+
+ system_interrupt_leave_critical_section();
+
+ return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ */
+static inline void usart_unlock(struct usart_module *const module)
+{
+ module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \brief Check if peripheral is busy syncing registers across clock domains
+ *
+ * Return peripheral synchronization status. If doing a non-blocking
+ * implementation this function can be used to check the sync state and hold of
+ * any new actions until sync is complete. If this functions is not run; the
+ * functions will block until the sync has completed.
+ *
+ * \param[in] module Pointer to peripheral module
+ *
+ * \return Peripheral sync status.
+ *
+ * \retval true Peripheral is busy syncing
+ * \retval false Peripheral is not busy syncing and can be read/written without
+ * stalling the bus.
+ */
+static inline bool usart_is_syncing(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+#ifdef FEATURE_USART_SYNC_SCHEME_V2
+ return (usart_hw->SYNCBUSY.reg);
+#else
+ return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY);
+#endif
+}
+
+#if !defined (__DOXYGEN__)
+/**
+ * \internal
+ * Waits until synchronization is complete
+ */
+static inline void _usart_wait_for_sync(
+ const struct usart_module *const module)
+{
+ /* Sanity check. */
+ Assert(module);
+
+ while (usart_is_syncing(module)) {
+ /* Wait until the synchronization is complete */
+ }
+}
+#endif
+
+/**
+ * \brief Initializes the device to predefined defaults
+ *
+ * Initialize the USART device to predefined defaults:
+ * - 8-bit asynchronous USART
+ * - No parity
+ * - One stop bit
+ * - 9600 baud
+ * - Transmitter enabled
+ * - Receiver enabled
+ * - GCLK generator 0 as clock source
+ * - Default pin configuration
+ *
+ * The configuration struct will be updated with the default
+ * configuration.
+ *
+ * \param[in,out] config Pointer to configuration struct
+ */
+static inline void usart_get_config_defaults(
+ struct usart_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Set default config in the config struct */
+ config->data_order = USART_DATAORDER_LSB;
+ config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY;
+ config->parity = USART_PARITY_NONE;
+ config->stopbits = USART_STOPBITS_1;
+ config->character_size = USART_CHARACTER_SIZE_8BIT;
+ config->baudrate = 9600;
+ config->receiver_enable = true;
+ config->transmitter_enable = true;
+ config->clock_polarity_inverted = false;
+ config->use_external_clock = false;
+ config->ext_clock_freq = 0;
+ config->mux_setting = USART_RX_1_TX_2_XCK_3;
+ config->run_in_standby = false;
+ config->generator_source = GCLK_GENERATOR_0;
+ config->pinmux_pad0 = PINMUX_DEFAULT;
+ config->pinmux_pad1 = PINMUX_DEFAULT;
+ config->pinmux_pad2 = PINMUX_DEFAULT;
+ config->pinmux_pad3 = PINMUX_DEFAULT;
+#ifdef FEATURE_USART_OVER_SAMPLE
+ config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9;
+ config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+ config->lin_slave_enable = false;
+#endif
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+ config->immediate_buffer_overflow_notification = false;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ config->start_frame_detection_enable = false;
+#endif
+#ifdef FEATURE_USART_IRDA
+ config->encoding_format_enable = false;
+ config->receive_pulse_length = 19;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ config->collision_detection_enable = false;
+#endif
+}
+
+enum status_code usart_init(
+ struct usart_module *const module,
+ Sercom *const hw,
+ const struct usart_config *const config);
+
+/**
+ * \brief Enable the module
+ *
+ * Enables the USART module.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ */
+static inline void usart_enable(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+#if USART_CALLBACK_MODE == true
+ /* Enable Global interrupt for module */
+ system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Enable USART module */
+ usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disable module
+ *
+ * Disables the USART module.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ */
+static inline void usart_disable(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+#if USART_CALLBACK_MODE == true
+ /* Disable Global interrupt for module */
+ system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Disable USART module */
+ usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Resets the USART module
+ *
+ * Disables and resets the USART module.
+ *
+ * \param[in] module Pointer to the USART software instance struct
+ */
+static inline void usart_reset(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ usart_disable(module);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Reset module */
+ usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
+}
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_wait(
+ struct usart_module *const module,
+ const uint16_t tx_data);
+
+enum status_code usart_read_wait(
+ struct usart_module *const module,
+ uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_wait(
+ struct usart_module *const module,
+ const uint8_t *tx_data,
+ uint16_t length);
+
+enum status_code usart_read_buffer_wait(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length);
+/** @} */
+
+/**
+ * \name Enabling/Disabling Receiver and Transmitter
+ * @{
+ */
+
+/**
+ * \brief Enable Transceiver
+ *
+ * Enable the given transceiver. Either RX or TX.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] transceiver_type Transceiver type
+ */
+static inline void usart_enable_transceiver(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ switch (transceiver_type) {
+ case USART_TRANSCEIVER_RX:
+ /* Enable RX */
+ usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+ module->receiver_enabled = true;
+ break;
+
+ case USART_TRANSCEIVER_TX:
+ /* Enable TX */
+ usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+ module->transmitter_enabled = true;
+ break;
+ }
+}
+
+/**
+ * \brief Disable Transceiver
+ *
+ * Disable the given transceiver (RX or TX).
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] transceiver_type Transceiver type
+ */
+static inline void usart_disable_transceiver(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ switch (transceiver_type) {
+ case USART_TRANSCEIVER_RX:
+ /* Disable RX */
+ usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+ module->receiver_enabled = false;
+ break;
+
+ case USART_TRANSCEIVER_TX:
+ /* Disable TX */
+ usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+ module->transmitter_enabled = false;
+ break;
+ }
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+* \page asfdoc_sam0_sercom_usart_extra Extra Information for SERCOM USART Driver
+*
+* \section asfdoc_sam0_sercom_usart_extra_acronyms Acronyms
+*
+* Below is a table listing the acronyms used in this module, along with their
+* intended meanings.
+*
+* <table>
+* <tr>
+* <th>Acronym</th>
+* <th>Description</th>
+* </tr>
+* <tr>
+* <td>SERCOM</td>
+* <td>Serial Communication Interface</td>
+* </tr>
+* <tr>
+* <td>USART</td>
+* <td>Universal Synchronous and Asynchronous Serial Receiver and Transmitter</td>
+* </tr>
+* <tr>
+* <td>LSB</td>
+* <td>Least Significant Bit</td>
+* </tr>
+* <tr>
+* <td>MSB</td>
+* <td>Most Significant Bit</td>
+* </tr>
+* <tr>
+* <td>DMA</td>
+* <td>Direct Memory Access</td>
+* </tr>
+* </table>
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_dependencies Dependencies
+* This driver has the following dependencies:
+*
+* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+* - \ref asfdoc_sam0_system_clock_group "System clock configuration"
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_errata Errata
+* There are no errata related to this driver.
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_history Module History
+* An overview of the module history is presented in the table below, with
+* details on the enhancements and fixes made to the module since its first
+* release. The current version of this corresponds to the newest version in
+* the table.
+*
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Add support for SAML21 (same features as SAMD21)</td>
+ * </tr>
+ * <tr>
+ * <td>Add support for SAMD10/D11 (same features as SAMD21)</td>
+ * </tr>
+ * <tr>
+ * <td>Add support for SAMR21 (same features as SAMD21)</td>
+ * </tr>
+ * <tr>
+ * <td>Add support for SAMD21 and added new feature as below:
+ \li Oversample
+ \li Buffer overflow notification
+ \li Irda
+ \li Lin slave
+ \li Start frame detection
+ \li Hardware flow control
+ \li Collision detection
+ \li DMA support </td>
+ * </tr>
+ * <tr>
+ * <td>\li Added new \c transmitter_enable and \c receiver_enable Boolean
+ * values to \c struct usart_config
+ * \li Altered \c usart_write_* and usart_read_* functions to abort with
+ * an error code if the relevant transceiver is not enabled
+ * \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait()
+ * not aborting correctly when a timeout condition occurs</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+*/
+
+/**
+ * \page asfdoc_sam0_sercom_usart_exqsg Examples for SERCOM USART Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_usart_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_sercom_usart_basic_use_case
+ * \if USART_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_usart_callback_use_case
+ * \endif
+ * - \subpage asfdoc_sam0_sercom_usart_dma_use_case
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_mux_settings SERCOM USART MUX Settings
+ *
+ * The following lists the possible internal SERCOM module pad function
+ * assignments, for the four SERCOM pads when in USART mode. Note that this is
+ * in addition to the physical GPIO pin MUX of the device, and can be used in
+ * conjunction to optimize the serial data pin-out.
+ *
+ * When TX and RX are connected to the same pin, the USART will operate in
+ * half-duplex mode if both the transmitter and receivers are enabled.
+ *
+ * \note When RX and XCK are connected to the same pin, the receiver must not
+ * be enabled if the USART is configured to use an external clock.
+ *
+ *
+ * <table>
+ * <tr>
+ * <th>MUX/Pad</th>
+ * <th>PAD 0</th>
+ * <th>PAD 1</th>
+ * <th>PAD 2</th>
+ * <th>PAD 3</th>
+ * </tr>
+ * <tr>
+ * <td>RX_0_TX_0_XCK_1</td>
+ * <td>TX / RX</td>
+ * <td>XCK</td>
+ * <td>-</td>
+ * <td>-</td>
+ * </tr>
+ * <tr>
+ * <td>RX_0_TX_2_XCK_3</td>
+ * <td>RX</td>
+ * <td>-</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * </tr>
+ * <tr>
+ * <td>RX_1_TX_0_XCK_1</td>
+ * <td>TX</td>
+ * <td>RX / XCK</td>
+ * <td>-</td>
+ * <td>-</td>
+ * </tr>
+ * <tr>
+ * <td>RX_1_TX_2_XCK_3</td>
+ * <td>-</td>
+ * <td>RX</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * </tr>
+ * <tr>
+ * <td>RX_2_TX_0_XCK_1</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * <td>RX</td>
+ * <td>-</td>
+ * </tr>
+ * <tr>
+ * <td>RX_2_TX_2_XCK_3</td>
+ * <td>-</td>
+ * <td>-</td>
+ * <td>TX / RX</td>
+ * <td>XCK</td>
+ * </tr>
+ * <tr>
+ * <td>RX_3_TX_0_XCK_1</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * <td>-</td>
+ * <td>RX</td>
+ * </tr>
+ * <tr>
+ * <td>RX_3_TX_2_XCK_3</td>
+ * <td>-</td>
+ * <td>-</td>
+ * <td>TX</td>
+ * <td>RX / XCK</td>
+ * </tr>
+ * </table>
+ *
+ * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>F</td>
+ * <td>11/2014</td>
+ * <td>Add support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>12/2014</td>
+ * <td>Add support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>01/2014</td>
+ * <td>Add support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>10/2013</td>
+ * <td>Replaced the pad multiplexing documentation with a condensed table.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+#endif /* USART_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,660 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "usart_interrupt.h"
+
+/**
+ * \internal
+ * Asynchronous write of a buffer with a given length
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] tx_data Pointer to data to be transmitted
+ * \param[in] length Length of data buffer
+ *
+ */
+void _usart_write_buffer(
+ struct usart_module *const module,
+ uint8_t *tx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Write parameters to the device instance */
+ module->remaining_tx_buffer_length = length;
+ module->tx_buffer_ptr = tx_data;
+ module->tx_status = STATUS_BUSY;
+
+ /* Enable the Data Register Empty Interrupt */
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+/**
+ * \internal
+ * Asynchronous read of a buffer with a given length
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] rx_data Pointer to data to be received
+ * \param[in] length Length of data buffer
+ *
+ */
+void _usart_read_buffer(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Set length for the buffer and the pointer, and let
+ * the interrupt handler do the rest */
+ module->remaining_rx_buffer_length = length;
+ module->rx_buffer_ptr = rx_data;
+ module->rx_status = STATUS_BUSY;
+
+ /* Enable the RX Complete Interrupt */
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+ /* Enable the break character is received Interrupt */
+ if(module->lin_slave_enabled) {
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
+ }
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ /* Enable a start condition is detected Interrupt */
+ if(module->start_frame_detection_enabled) {
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
+ }
+#endif
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usart_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for
+ * the callback type are met.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] callback_func Pointer to callback function
+ * \param[in] callback_type Callback type given by an enum
+ *
+ */
+void usart_register_callback(
+ struct usart_module *const module,
+ usart_callback_t callback_func,
+ enum usart_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(callback_func);
+
+ /* Register callback function */
+ module->callback[callback_type] = callback_func;
+
+ /* Set the bit corresponding to the callback_type */
+ module->callback_reg_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in,out] module Pointer to USART software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ *
+ */
+void usart_unregister_callback(
+ struct usart_module *const module,
+ enum usart_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+
+ /* Unregister callback function */
+ module->callback[callback_type] = NULL;
+
+ /* Clear the bit corresponding to the callback_type */
+ module->callback_reg_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Asynchronous write a single char
+ *
+ * Sets up the driver to write the data given. If registered and enabled,
+ * a callback function will be called when the transmit is completed.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] tx_data Data to transfer
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK If operation was completed
+ * \retval STATUS_BUSY If operation was not completed, due to the
+ * USART module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_job(
+ struct usart_module *const module,
+ const uint16_t *tx_data)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(tx_data);
+
+ /* Check if the USART transmitter is busy */
+ if (module->remaining_tx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+
+ /* Check that the transmitter is enabled */
+ if (!(module->transmitter_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Call internal write buffer function with length 1 */
+ _usart_write_buffer(module, (uint8_t *)tx_data, 1);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous read a single char
+ *
+ * Sets up the driver to read data from the USART module to the data
+ * pointer given. If registered and enabled, a callback will be called
+ * when the receiving is completed.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[out] rx_data Pointer to where received data should be put
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK If operation was completed
+ * \retval STATUS_BUSY If operation was not completed
+ */
+enum status_code usart_read_job(
+ struct usart_module *const module,
+ uint16_t *const rx_data)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(rx_data);
+
+ /* Check if the USART receiver is busy */
+ if (module->remaining_rx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+
+ /* Call internal read buffer function with length 1 */
+ _usart_read_buffer(module, (uint8_t *)rx_data, 1);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write a given buffer over the USART. If registered and
+ * enabled, a callback function will be called.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] tx_data Pointer do data buffer to transmit
+ * \param[in] length Length of the data to transmit
+ *
+ * \note if using 9-bit data, the array that *tx_data point to should be defined
+ * as uint16_t array and should be casted to uint8_t* pointer. Because it
+ * is an address pointer, the highest byte is not discarded. For example:
+ * \code
+ #define TX_LEN 3
+ uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+ usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN);
+ \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK If operation was completed successfully.
+ * \retval STATUS_BUSY If operation was not completed, due to the
+ * USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ * arguments
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_job(
+ struct usart_module *const module,
+ uint8_t *tx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(tx_data);
+
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check if the USART transmitter is busy */
+ if (module->remaining_tx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+
+ /* Check that the receiver is enabled */
+ if (!(module->transmitter_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Issue internal asynchronous write */
+ _usart_write_buffer(module, tx_data, length);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the USART to a given buffer. If registered
+ * and enabled, a callback function will be called.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[out] rx_data Pointer to data buffer to receive
+ * \param[in] length Data buffer length
+ *
+ * \note if using 9-bit data, the array that *rx_data point to should be defined
+ * as uint16_t array and should be casted to uint8_t* pointer. Because it
+ * is an address pointer, the highest byte is not discarded. For example:
+ * \code
+ #define RX_LEN 3
+ uint16_t rx_buf[RX_LEN] = {0x0,};
+ usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN);
+ \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK If operation was completed
+ * \retval STATUS_BUSY If operation was not completed, due to the
+ * USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ * arguments
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_read_buffer_job(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(rx_data);
+
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check that the receiver is enabled */
+ if (!(module->receiver_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Check if the USART receiver is busy */
+ if (module->remaining_rx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+
+ /* Issue internal asynchronous read */
+ _usart_read_buffer(module, rx_data, length);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Cancels ongoing read/write operation
+ *
+ * Cancels the ongoing read/write operation modifying parameters in the
+ * USART software struct.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] transceiver_type Transfer type to cancel
+ */
+void usart_abort_job(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ switch(transceiver_type) {
+ case USART_TRANSCEIVER_RX:
+ /* Clear the interrupt flag in order to prevent the receive
+ * complete callback to fire */
+ usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+
+ /* Clear the software reception buffer */
+ module->remaining_rx_buffer_length = 0;
+
+ break;
+
+ case USART_TRANSCEIVER_TX:
+ /* Clear the interrupt flag in order to prevent the receive
+ * complete callback to fire */
+ usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+
+ /* Clear the software reception buffer */
+ module->remaining_tx_buffer_length = 0;
+
+ break;
+ }
+}
+
+/**
+ * \brief Get status from the ongoing or last asynchronous transfer operation
+ *
+ * Returns the error from a given ongoing or last asynchronous transfer operation.
+ * Either from a read or write transfer.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] transceiver_type Transfer type to check
+ *
+ * \return Status of the given job.
+ * \retval STATUS_OK No error occurred during the last transfer
+ * \retval STATUS_BUSY A transfer is ongoing
+ * \retval STATUS_ERR_BAD_DATA The last operation was aborted due to a
+ * parity error. The transfer could be affected
+ * by external noise
+ * \retval STATUS_ERR_BAD_FORMAT The last operation was aborted due to a
+ * frame error
+ * \retval STATUS_ERR_OVERFLOW The last operation was aborted due to a
+ * buffer overflow
+ * \retval STATUS_ERR_INVALID_ARG An invalid transceiver enum given
+ */
+enum status_code usart_get_job_status(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+
+ /* Variable for status code */
+ enum status_code status_code;
+
+ switch(transceiver_type) {
+ case USART_TRANSCEIVER_RX:
+ status_code = module->rx_status;
+ break;
+
+ case USART_TRANSCEIVER_TX:
+ status_code = module->tx_status;
+ break;
+
+ default:
+ status_code = STATUS_ERR_INVALID_ARG;
+ break;
+ }
+
+ return status_code;
+}
+
+/**
+ * \internal
+ * Handles interrupts as they occur, and it will run callback functions
+ * which are registered and enabled.
+ *
+ * \param[in] instance ID of the SERCOM instance calling the interrupt
+ * handler.
+ */
+void _usart_interrupt_handler(
+ uint8_t instance)
+{
+ /* Temporary variables */
+ uint16_t interrupt_status;
+ uint16_t callback_status;
+ uint8_t error_code;
+
+
+ /* Get device instance from the look-up table */
+ struct usart_module *module
+ = (struct usart_module *)_sercom_instances[instance];
+
+ /* Pointer to the hardware module instance */
+ SercomUsart *const usart_hw
+ = &(module->hw->USART);
+
+ /* Wait for the synchronization to complete */
+ _usart_wait_for_sync(module);
+
+ /* Read and mask interrupt flag register */
+ interrupt_status = usart_hw->INTFLAG.reg;
+ interrupt_status &= usart_hw->INTENSET.reg;
+ callback_status = module->callback_reg_mask &
+ module->callback_enable_mask;
+
+ /* Check if a DATA READY interrupt has occurred,
+ * and if there is more to transfer */
+ if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
+ if (module->remaining_tx_buffer_length) {
+ /* Write value will be at least 8-bits long */
+ uint16_t data_to_send = *(module->tx_buffer_ptr);
+ /* Increment 8-bit pointer */
+ (module->tx_buffer_ptr)++;
+
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+ data_to_send |= (*(module->tx_buffer_ptr) << 8);
+ /* Increment 8-bit pointer */
+ (module->tx_buffer_ptr)++;
+ }
+ /* Write the data to send */
+ usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
+
+ if (--(module->remaining_tx_buffer_length) == 0) {
+ /* Disable the Data Register Empty Interrupt */
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+ /* Enable Transmission Complete interrupt */
+ usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+
+ }
+ } else {
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+ }
+
+ /* Check if the Transmission Complete interrupt has occurred and
+ * that the transmit buffer is empty */
+ }
+
+ if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
+
+ /* Disable TX Complete Interrupt, and set STATUS_OK */
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+ module->tx_status = STATUS_OK;
+
+ /* Run callback if registered and enabled */
+ if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
+ (*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
+ }
+
+ /* Check if the Receive Complete interrupt has occurred, and that
+ * there's more data to receive */
+ }
+
+ if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+
+ if (module->remaining_rx_buffer_length) {
+ /* Read out the status code and mask away all but the 4 LSBs*/
+ error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+#if !SAMD20
+ /* CTS status should not be considered as an error */
+ if(error_code & SERCOM_USART_STATUS_CTS) {
+ error_code &= ~SERCOM_USART_STATUS_CTS;
+ }
+#endif
+ /* Check if an error has occurred during the receiving */
+ if (error_code) {
+ /* Check which error occurred */
+ if (error_code & SERCOM_USART_STATUS_FERR) {
+ /* Store the error code and clear flag by writing 1 to it */
+ module->rx_status = STATUS_ERR_BAD_FORMAT;
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_FERR;
+ } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+ /* Store the error code and clear flag by writing 1 to it */
+ module->rx_status = STATUS_ERR_OVERFLOW;
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF;
+ } else if (error_code & SERCOM_USART_STATUS_PERR) {
+ /* Store the error code and clear flag by writing 1 to it */
+ module->rx_status = STATUS_ERR_BAD_DATA;
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_PERR;
+ }
+#ifdef FEATURE_USART_LIN_SLAVE
+ else if (error_code & SERCOM_USART_STATUS_ISF) {
+ /* Store the error code and clear flag by writing 1 to it */
+ module->rx_status = STATUS_ERR_PROTOCOL;
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF;
+ }
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ else if (error_code & SERCOM_USART_STATUS_COLL) {
+ /* Store the error code and clear flag by writing 1 to it */
+ module->rx_status = STATUS_ERR_PACKET_COLLISION;
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL;
+ }
+#endif
+
+ /* Run callback if registered and enabled */
+ if (callback_status
+ & (1 << USART_CALLBACK_ERROR)) {
+ (*(module->callback[USART_CALLBACK_ERROR]))(module);
+ }
+
+ } else {
+
+ /* Read current packet from DATA register,
+ * increment buffer pointer and decrement buffer length */
+ uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
+
+ /* Read value will be at least 8-bits long */
+ *(module->rx_buffer_ptr) = received_data;
+ /* Increment 8-bit pointer */
+ module->rx_buffer_ptr += 1;
+
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+ /* 9-bit data, write next received byte to the buffer */
+ *(module->rx_buffer_ptr) = (received_data >> 8);
+ /* Increment 8-bit pointer */
+ module->rx_buffer_ptr += 1;
+ }
+
+ /* Check if the last character have been received */
+ if(--(module->remaining_rx_buffer_length) == 0) {
+ /* Disable RX Complete Interrupt,
+ * and set STATUS_OK */
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+ module->rx_status = STATUS_OK;
+
+ /* Run callback if registered and enabled */
+ if (callback_status
+ & (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
+ (*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
+ }
+ }
+ }
+ } else {
+ /* This should not happen. Disable Receive Complete interrupt. */
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+ }
+ }
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+ if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+ /* Disable interrupts */
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+ /* Clear interrupt flag */
+ usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+
+ /* Run callback if registered and enabled */
+ if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
+ (*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
+ }
+ }
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+ if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+ /* Disable interrupts */
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+ /* Clear interrupt flag */
+ usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+
+ /* Run callback if registered and enabled */
+ if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
+ (*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
+ }
+ }
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+ /* Disable interrupts */
+ usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+ /* Clear interrupt flag */
+ usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+
+ /* Run callback if registered and enabled */
+ if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
+ (*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+ }
+ }
+#endif
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,176 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef USART_INTERRUPT_H_INCLUDED
+#define USART_INTERRUPT_H_INCLUDED
+
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+void _usart_write_buffer(
+ struct usart_module *const module,
+ uint8_t *tx_data,
+ uint16_t length);
+
+void _usart_read_buffer(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length);
+
+void _usart_interrupt_handler(
+ uint8_t instance);
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_usart_group
+ *
+ * @{
+ */
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void usart_register_callback(
+ struct usart_module *const module,
+ usart_callback_t callback_func,
+ enum usart_callback callback_type);
+
+void usart_unregister_callback(
+ struct usart_module *module,
+ enum usart_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref usart_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ */
+static inline void usart_enable_callback(
+ struct usart_module *const module,
+ enum usart_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+
+ /* Enable callback */
+ module->callback_enable_mask |= (1 << callback_type);
+
+}
+
+/**
+ * \brief Disable callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ */
+static inline void usart_disable_callback(
+ struct usart_module *const module,
+ enum usart_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+
+ /* Disable callback */
+ module->callback_enable_mask &= ~(1 << callback_type);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_job(
+ struct usart_module *const module,
+ const uint16_t *tx_data);
+
+enum status_code usart_read_job(
+ struct usart_module *const module,
+ uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_job(
+ struct usart_module *const module,
+ uint8_t *tx_data,
+ uint16_t length);
+
+enum status_code usart_read_buffer_job(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length);
+
+void usart_abort_job(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type);
+
+enum status_code usart_get_job_status(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USART_INTERRUPT_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief SAM Clock Driver + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ +#ifndef SYSTEM_CLOCK_H_INCLUDED +#define SYSTEM_CLOCK_H_INCLUDED + +#include <compiler.h> +#include <gclk.h> +#include <clock_feature.h> + +#endif /* SYSTEM_CLOCK_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1003 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21 Clock Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include <compiler.h>
+#include <clock.h>
+#include <conf_clocks.h>
+#include <system.h>
+
+#ifndef SYSCTRL_FUSES_OSC32K_ADDR
+# define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR
+# define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos
+#endif
+
+/**
+ * \internal
+ * \brief DFLL-specific data container.
+ */
+struct _system_clock_dfll_config {
+ uint32_t control;
+ uint32_t val;
+ uint32_t mul;
+};
+
+/**
+ * \internal
+ * \brief DPLL-specific data container.
+ */
+struct _system_clock_dpll_config {
+ uint32_t frequency;
+};
+
+
+/**
+ * \internal
+ * \brief XOSC-specific data container.
+ */
+struct _system_clock_xosc_config {
+ uint32_t frequency;
+};
+
+/**
+ * \internal
+ * \brief System clock module data container.
+ */
+struct _system_clock_module {
+ volatile struct _system_clock_dfll_config dfll;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ volatile struct _system_clock_dpll_config dpll;
+#endif
+
+ volatile struct _system_clock_xosc_config xosc;
+ volatile struct _system_clock_xosc_config xosc32k;
+};
+
+/**
+ * \internal
+ * \brief Internal module instance to cache configuration values.
+ */
+static struct _system_clock_module _system_clock_inst = {
+ .dfll = {
+ .control = 0,
+ .val = 0,
+ .mul = 0,
+ },
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ .dpll = {
+ .frequency = 0,
+ },
+#endif
+ .xosc = {
+ .frequency = 0,
+ },
+ .xosc32k = {
+ .frequency = 0,
+ },
+};
+
+/**
+ * \internal
+ * \brief Wait for sync to the DFLL control registers.
+ */
+static inline void _system_dfll_wait_for_sync(void)
+{
+ while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+ /* Wait for DFLL sync */
+ }
+}
+
+/**
+ * \internal
+ * \brief Wait for sync to the OSC32K control registers.
+ */
+static inline void _system_osc32k_wait_for_sync(void)
+{
+ while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
+ /* Wait for OSC32K sync */
+ }
+}
+
+static inline void _system_clock_source_dfll_set_config_errata_9905(void)
+{
+
+ /* Disable ONDEMAND mode while writing configurations */
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND;
+ _system_dfll_wait_for_sync();
+
+ SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+ SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+
+ /* Write full configuration to DFLL control register */
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+}
+
+/**
+ * \brief Retrieve the frequency of a clock source.
+ *
+ * Determines the current operating frequency of a given clock source.
+ *
+ * \param[in] clock_source Clock source to get the frequency
+ *
+ * \returns Frequency of the given clock source, in Hz.
+ */
+uint32_t system_clock_source_get_hz(
+ const enum system_clock_source clock_source)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ return _system_clock_inst.xosc.frequency;
+
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ return 32768UL;
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ return 32768UL;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ return _system_clock_inst.xosc32k.frequency;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+
+ /* Check if the DFLL has been configured */
+ if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+ return 0;
+
+ /* Make sure that the DFLL module is ready */
+ _system_dfll_wait_for_sync();
+
+ /* Check if operating in closed loop mode */
+ if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {
+ return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+ (_system_clock_inst.dfll.mul & 0xffff);
+ }
+
+ return 48000000UL;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
+ return 0;
+ }
+
+ return _system_clock_inst.dpll.frequency;
+#endif
+
+ default:
+ return 0;
+ }
+}
+
+/**
+ * \brief Configure the internal OSC8M oscillator clock source.
+ *
+ * Configures the 8MHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config OSC8M configuration structure containing the new config
+ */
+void system_clock_source_osc8m_set_config(
+ struct system_clock_source_osc8m_config *const config)
+{
+ SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+
+ /* Use temporary struct to reduce register access */
+ temp.bit.PRESC = config->prescaler;
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+
+ SYSCTRL->OSC8M = temp;
+}
+
+/**
+ * \brief Configure the internal OSC32K oscillator clock source.
+ *
+ * Configures the 32KHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config OSC32K configuration structure containing the new config
+ */
+void system_clock_source_osc32k_set_config(
+ struct system_clock_source_osc32k_config *const config)
+{
+ SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
+
+ /* Update settings via a temporary struct to reduce register access */
+ temp.bit.EN1K = config->enable_1khz_output;
+ temp.bit.EN32K = config->enable_32khz_output;
+ temp.bit.STARTUP = config->startup_time;
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+ temp.bit.WRTLOCK = config->write_once;
+
+ SYSCTRL->OSC32K = temp;
+}
+
+/**
+ * \brief Configure the external oscillator clock source.
+ *
+ * Configures the external oscillator clock source with the given configuration
+ * settings.
+ *
+ * \param[in] config External oscillator configuration structure containing
+ * the new config
+ */
+void system_clock_source_xosc_set_config(
+ struct system_clock_source_xosc_config *const config)
+{
+ SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
+
+ temp.bit.STARTUP = config->startup_time;
+
+ if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+ temp.bit.XTALEN = 1;
+ } else {
+ temp.bit.XTALEN = 0;
+ }
+
+ temp.bit.AMPGC = config->auto_gain_control;
+
+ /* Set gain if automatic gain control is not selected */
+ if (!config->auto_gain_control) {
+ if (config->frequency <= 2000000) {
+ temp.bit.GAIN = 0;
+ } else if (config->frequency <= 4000000) {
+ temp.bit.GAIN = 1;
+ } else if (config->frequency <= 8000000) {
+ temp.bit.GAIN = 2;
+ } else if (config->frequency <= 16000000) {
+ temp.bit.GAIN = 3;
+ } else if (config->frequency <= 30000000) {
+ temp.bit.GAIN = 4;
+ }
+
+ }
+
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+
+ /* Store XOSC frequency for internal use */
+ _system_clock_inst.xosc.frequency = config->frequency;
+
+ SYSCTRL->XOSC = temp;
+}
+
+/**
+ * \brief Configure the XOSC32K external 32KHz oscillator clock source.
+ *
+ * Configures the external 32KHz oscillator clock source with the given
+ * configuration settings.
+ *
+ * \param[in] config XOSC32K configuration structure containing the new config
+ */
+void system_clock_source_xosc32k_set_config(
+ struct system_clock_source_xosc32k_config *const config)
+{
+ SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
+
+ temp.bit.STARTUP = config->startup_time;
+
+ if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+ temp.bit.XTALEN = 1;
+ } else {
+ temp.bit.XTALEN = 0;
+ }
+
+ temp.bit.AAMPEN = config->auto_gain_control;
+ temp.bit.EN1K = config->enable_1khz_output;
+ temp.bit.EN32K = config->enable_32khz_output;
+
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+ temp.bit.WRTLOCK = config->write_once;
+
+ /* Cache the new frequency in case the user needs to check the current
+ * operating frequency later */
+ _system_clock_inst.xosc32k.frequency = config->frequency;
+
+ SYSCTRL->XOSC32K = temp;
+}
+
+/**
+ * \brief Configure the DFLL clock source.
+ *
+ * Configures the Digital Frequency Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DFLL will be running when this function returns, as the DFLL module
+ * needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config DFLL configuration structure containing the new config
+ */
+void system_clock_source_dfll_set_config(
+ struct system_clock_source_dfll_config *const config)
+{
+ _system_clock_inst.dfll.val =
+ SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
+ SYSCTRL_DFLLVAL_FINE(config->fine_value);
+
+ _system_clock_inst.dfll.control =
+ (uint32_t)config->wakeup_lock |
+ (uint32_t)config->stable_tracking |
+ (uint32_t)config->quick_lock |
+ (uint32_t)config->chill_cycle |
+ ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
+
+ if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+
+ _system_clock_inst.dfll.mul =
+ SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+ SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) |
+ SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+ /* Enable the closed loop mode */
+ _system_clock_inst.dfll.control |= config->loop_mode;
+ }
+ if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+
+ _system_clock_inst.dfll.mul =
+ SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+ /* Enable the USB recovery mode */
+ _system_clock_inst.dfll.control |= config->loop_mode |
+ SYSCTRL_DFLLCTRL_BPLCKC;
+ }
+}
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Configure the DPLL clock source.
+ *
+ * Configures the Digital Phase-Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DPLL will be running when this function returns, as the DPLL module
+ * needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config DPLL configuration structure containing the new config
+ */
+void system_clock_source_dpll_set_config(
+ struct system_clock_source_dpll_config *const config)
+{
+
+ uint32_t tmpldr;
+ uint8_t tmpldrfrac;
+ uint32_t refclk;
+
+ refclk = config->reference_frequency;
+
+ /* Only reference clock REF1 can be divided */
+ if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1) {
+ refclk = refclk / config->reference_divider;
+ }
+
+ /* Calculate LDRFRAC and LDR */
+ tmpldr = (config->output_frequency << 4) / refclk;
+ tmpldrfrac = tmpldr & 0x0f;
+ tmpldr = (tmpldr >> 4) - 1;
+
+ SYSCTRL->DPLLCTRLA.reg =
+ ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
+ ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
+
+ SYSCTRL->DPLLRATIO.reg =
+ SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
+ SYSCTRL_DPLLRATIO_LDR(tmpldr);
+
+ SYSCTRL->DPLLCTRLB.reg =
+ SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
+ ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
+ SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
+ SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
+ ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
+ ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
+ SYSCTRL_DPLLCTRLB_FILTER(config->filter);
+
+ /*
+ * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
+ */
+ _system_clock_inst.dpll.frequency =
+ (config->reference_frequency *
+ (((tmpldr + 1) << 4) + tmpldrfrac)
+ ) >> 4;
+}
+#endif
+
+/**
+ * \brief Writes the calibration values for a given oscillator clock source.
+ *
+ * Writes an oscillator calibration value to the given oscillator control
+ * registers. The acceptable ranges are:
+ *
+ * For OSC32K:
+ * - 7 bits (max value 128)
+ * For OSC8MHZ:
+ * - 8 bits (Max value 255)
+ * For OSCULP:
+ * - 5 bits (Max value 32)
+ *
+ * \note The frequency range parameter applies only when configuring the 8MHz
+ * oscillator and will be ignored for the other oscillators.
+ *
+ * \param[in] clock_source Clock source to calibrate
+ * \param[in] calibration_value Calibration value to write
+ * \param[in] freq_range Frequency range (8MHz oscillator only)
+ *
+ * \retval STATUS_OK The calibration value was written
+ * successfully.
+ * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock
+ * source.
+ */
+enum status_code system_clock_source_write_calibration(
+ const enum system_clock_source clock_source,
+ const uint16_t calibration_value,
+ const uint8_t freq_range)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+
+ if (calibration_value > 0xfff || freq_range > 4) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ SYSCTRL->OSC8M.bit.CALIB = calibration_value;
+ SYSCTRL->OSC8M.bit.FRANGE = freq_range;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+
+ if (calibration_value > 128) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ _system_osc32k_wait_for_sync();
+ SYSCTRL->OSC32K.bit.CALIB = calibration_value;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+
+ if (calibration_value > 32) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ break;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Enables a clock source.
+ *
+ * Enables a clock source which has been previously configured.
+ *
+ * \param[in] clock_source Clock source to enable
+ *
+ * \retval STATUS_OK Clock source was enabled successfully and
+ * is ready
+ * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this
+ * device
+ */
+enum status_code system_clock_source_enable(
+ const enum system_clock_source clock_source)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+ return STATUS_OK;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+ _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+ _system_clock_source_dfll_set_config_errata_9905();
+ break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
+ break;
+#endif
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ /* Always enabled */
+ return STATUS_OK;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+ }
+
+ /**
+ * \brief Disables a clock source.
+ *
+ * Disables a clock source that was previously enabled.
+ *
+ * \param[in] clock_source Clock source to disable
+ *
+ * \retval STATUS_OK Clock source was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was
+ * given
+ */
+ enum status_code system_clock_source_disable(
+ const enum system_clock_source clock_source)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+ _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+ break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
+ break;
+#endif
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ /* Not possible to disable */
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+
+ }
+
+ return STATUS_OK;
+ }
+
+ /**
+ * \brief Checks if a clock source is ready.
+ *
+ * Checks if a given clock source is ready to be used.
+ *
+ * \param[in] clock_source Clock source to check if ready
+ *
+ * \returns Ready state of the given clock source.
+ *
+ * \retval true Clock source is enabled and ready
+ * \retval false Clock source is disabled or not yet ready
+ */
+ bool system_clock_source_is_ready(
+ const enum system_clock_source clock_source)
+{
+ uint32_t mask = 0;
+
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ mask = SYSCTRL_PCLKSR_OSC8MRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ mask = SYSCTRL_PCLKSR_OSC32KRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ mask = SYSCTRL_PCLKSR_XOSCRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ mask = SYSCTRL_PCLKSR_XOSC32KRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+ mask = (SYSCTRL_PCLKSR_DFLLRDY |
+ SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
+ } else {
+ mask = SYSCTRL_PCLKSR_DFLLRDY;
+ }
+ break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ return ((SYSCTRL->DPLLSTATUS.reg &
+ (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
+ (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
+#endif
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ /* Not possible to disable */
+ return true;
+
+ default:
+ return false;
+ }
+
+ return ((SYSCTRL->PCLKSR.reg & mask) == mask);
+}
+
+/* Include some checks for conf_clocks.h validation */
+#include "clock_config_check.h"
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
+ */
+# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
+ if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
+ struct system_gclk_gen_config gclk_conf; \
+ system_gclk_gen_get_config_defaults(&gclk_conf); \
+ gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \
+ gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \
+ gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
+ gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \
+ system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \
+ system_gclk_gen_enable(GCLK_GENERATOR_##n); \
+ }
+
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,
+ * provided that it is not the main Generic Clock Generator channel.
+ */
+# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
+ if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
+#endif
+
+/** \internal
+ *
+ * Switch all peripheral clock to a not enabled general clock
+ * to save power.
+ */
+static void _switch_peripheral_gclk(void)
+{
+ uint32_t gclk_id;
+ struct system_gclk_chan_config gclk_conf;
+
+#if CONF_CLOCK_GCLK_1_ENABLE == false
+ gclk_conf.source_generator = GCLK_GENERATOR_1;
+#elif CONF_CLOCK_GCLK_2_ENABLE == false
+ gclk_conf.source_generator = GCLK_GENERATOR_2;
+#elif CONF_CLOCK_GCLK_3_ENABLE == false
+ gclk_conf.source_generator = GCLK_GENERATOR_3;
+#elif CONF_CLOCK_GCLK_4_ENABLE == false
+ gclk_conf.source_generator = GCLK_GENERATOR_4;
+#elif CONF_CLOCK_GCLK_5_ENABLE == false
+ gclk_conf.source_generator = GCLK_GENERATOR_5;
+#elif CONF_CLOCK_GCLK_6_ENABLE == false
+ gclk_conf.source_generator = GCLK_GENERATOR_6;
+#elif CONF_CLOCK_GCLK_7_ENABLE == false
+ gclk_conf.source_generator = GCLK_GENERATOR_7;
+#else
+ gclk_conf.source_generator = GCLK_GENERATOR_7;
+#endif
+
+ for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
+ system_gclk_chan_set_config(gclk_id, &gclk_conf);
+ }
+}
+
+/**
+ * \brief Initialize clock system based on the configuration in conf_clocks.h.
+ *
+ * This function will apply the settings in conf_clocks.h when run from the user
+ * application. All clock sources and GCLK generators are running when this function
+ * returns.
+ *
+ * \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
+ * the OSC8M default enable can be disabled after system_clock_init. Make sure the
+ * clock switch successfully before disabling OSC8M.
+ */
+void system_clock_init(void)
+{
+ /* Various bits in the INTFLAG register can be set to one at startup.
+ This will ensure that these bits are cleared */
+ SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+ SYSCTRL_INTFLAG_DFLLRDY;
+
+ system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
+
+ /* Switch all peripheral clock to a not enabled general clock to save power. */
+ _switch_peripheral_gclk();
+
+ /* XOSC */
+#if CONF_CLOCK_XOSC_ENABLE == true
+ struct system_clock_source_xosc_config xosc_conf;
+ system_clock_source_xosc_get_config_defaults(&xosc_conf);
+
+ xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
+ xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME;
+ xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
+ xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
+ xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND;
+ xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
+
+ system_clock_source_xosc_set_config(&xosc_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
+#endif
+
+
+ /* XOSC32K */
+#if CONF_CLOCK_XOSC32K_ENABLE == true
+ struct system_clock_source_xosc32k_config xosc32k_conf;
+ system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
+
+ xosc32k_conf.frequency = 32768UL;
+ xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
+ xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME;
+ xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
+ xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
+ xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
+ xosc32k_conf.on_demand = false;
+ xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
+
+ system_clock_source_xosc32k_set_config(&xosc32k_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+ while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+ if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
+ SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
+ }
+#endif
+
+
+ /* OSCK32K */
+#if CONF_CLOCK_OSC32K_ENABLE == true
+ SYSCTRL->OSC32K.bit.CALIB =
+ (*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> SYSCTRL_FUSES_OSC32K_Pos);
+
+ struct system_clock_source_osc32k_config osc32k_conf;
+ system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
+
+ osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME;
+ osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
+ osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
+ osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND;
+ osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
+
+ system_clock_source_osc32k_set_config(&osc32k_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
+#endif
+
+
+ /* DFLL Config (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+ struct system_clock_source_dfll_config dfll_conf;
+ system_clock_source_dfll_get_config_defaults(&dfll_conf);
+
+ dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE;
+ dfll_conf.on_demand = false;
+
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
+ dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE;
+ dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE;
+ }
+
+# if CONF_CLOCK_DFLL_QUICK_LOCK == true
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+# else
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
+# endif
+
+# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+# else
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+# endif
+
+# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+# else
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
+# endif
+
+# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+# else
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+# endif
+
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+ dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
+ }
+
+ dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
+ dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
+
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+#define NVM_DFLL_COARSE_POS 58
+#define NVM_DFLL_COARSE_SIZE 6
+#define NVM_DFLL_FINE_POS 64
+#define NVM_DFLL_FINE_SIZE 10
+ uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_DFLL_COARSE_POS / 32))
+ >> (NVM_DFLL_COARSE_POS % 32))
+ & ((1 << NVM_DFLL_COARSE_SIZE) - 1);
+ if (coarse == 0x3f) {
+ coarse = 0x1f;
+ }
+ uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_DFLL_FINE_POS / 32))
+ >> (NVM_DFLL_FINE_POS % 32))
+ & ((1 << NVM_DFLL_FINE_SIZE) - 1);
+ if (fine == 0x3ff) {
+ fine = 0x1ff;
+ }
+ dfll_conf.coarse_value = coarse;
+ dfll_conf.fine_value = fine;
+
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+
+ dfll_conf.multiply_factor = 48000;
+ }
+
+ system_clock_source_dfll_set_config(&dfll_conf);
+#endif
+
+
+ /* OSC8M */
+ struct system_clock_source_osc8m_config osc8m_conf;
+ system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+
+ osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER;
+ osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND;
+ osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+
+ system_clock_source_osc8m_set_config(&osc8m_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+
+
+ /* GCLK */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+ system_gclk_init();
+
+ /* Configure all GCLK generators except for the main generator, which
+ * is configured later after all other clock systems are set up */
+ MREPEAT(8, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
+
+# if CONF_CLOCK_DFLL_ENABLE == true
+ /* Enable DFLL reference clock if in closed loop mode */
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+ struct system_gclk_chan_config dfll_gclk_chan_conf;
+
+ system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
+ dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
+ system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
+ system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
+ }
+# endif
+#endif
+
+
+ /* DFLL Enable (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+ while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+ if (CONF_CLOCK_DFLL_ON_DEMAND) {
+ SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+ }
+#endif
+
+ /* DPLL */
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+# if (CONF_CLOCK_DPLL_ENABLE == true)
+
+ /* Enable DPLL reference clock */
+ if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0) {
+ /* XOSC32K should have been enabled for DPLL_REF0 */
+ Assert(CONF_CLOCK_XOSC32K_ENABLE);
+ }
+
+ struct system_clock_source_dpll_config dpll_config;
+ system_clock_source_dpll_get_config_defaults(&dpll_config);
+
+ dpll_config.on_demand = false;
+ dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
+ dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS;
+ dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST;
+ dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
+
+ dpll_config.filter = CONF_CLOCK_DPLL_FILTER;
+
+ dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
+ dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
+ dpll_config.reference_divider = CONF_CLOCK_DPLL_REFEREMCE_DIVIDER;
+ dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
+
+ system_clock_source_dpll_set_config(&dpll_config);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
+ while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
+ if (CONF_CLOCK_DPLL_ON_DEMAND) {
+ SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
+ }
+
+# endif
+#endif
+
+ /* CPU and BUS clocks */
+ system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
+
+ system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
+ system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
+
+ /* GCLK 0 */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+ /* Configure the main GCLK last as it might depend on other generators */
+ _CONF_CLOCK_GCLK_CONFIG(0, ~);
+#endif
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_config_check.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,426 @@ +/** + * \file + * + * \brief SAM D21/R21 Clock Driver + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef CLOCK_CONFIG_CHECK_H +# define CLOCK_CONFIG_CHECK_H + +#if !defined(CONF_CLOCK_FLASH_WAIT_STATES) +# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_CPU_DIVIDER) +# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_APBA_DIVIDER) +# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_APBB_DIVIDER) +# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC8M_PRESCALER) +# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND) +# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY) +# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC_ENABLE) +# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL) +# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY) +# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME) +# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) +# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC_ON_DEMAND) +# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY) +# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE) +# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL) +# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME) +# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL) +# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT) +# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT) +# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND) +# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY) +# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE) +# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME) +# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT) +# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT) +# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND) +# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY) +# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ENABLE) +# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_LOOP_MODE) +# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ON_DEMAND) +# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_COARSE_VALUE) +# error CONF_CLOCK_DFLL_COARSE_VALUE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_FINE_VALUE) +# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR) +# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR) +# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK) +# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK) +# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP) +# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE) +# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE) +# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE) +# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_ENABLE) +# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_ON_DEMAND) +# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY) +# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS) +# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST) +# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE) +# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_TIME) +# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK) +# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_FILTER) +# error CONF_CLOCK_DPLL_FILTER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY) +# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFEREMCE_DIVIDER) +# error CONF_CLOCK_DPLL_REFEREMCE_DIVIDER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY) +# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_CONFIGURE_GCLK) +# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_ENABLE) +# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_PRESCALER) +# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_ENABLE) +# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_PRESCALER) +# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_ENABLE) +# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_PRESCALER) +# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_ENABLE) +# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_PRESCALER) +# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_ENABLE) +# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_PRESCALER) +# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_ENABLE) +# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_PRESCALER) +# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_ENABLE) +# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_PRESCALER) +# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_ENABLE) +# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_PRESCALER) +# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clock.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clock.h +#endif + +#endif /* CLOCK_CONFIG_CHECK_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1491 @@
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
+#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the device's clocking related functions. This includes
+ * the various clock sources, bus clocks, and generic clocks within the device,
+ * with functions to manage the enabling, disabling, source selection, and
+ * prescaling of clocks to various internal peripherals.
+ *
+ * The following peripherals are used by this module:
+ *
+ * - GCLK (Generic Clock Management)
+ * - PM (Power Management)
+ * - SYSCTRL (Clock Source Control)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_clock_prerequisites
+ * - \ref asfdoc_sam0_system_clock_module_overview
+ * - \ref asfdoc_sam0_system_clock_special_considerations
+ * - \ref asfdoc_sam0_system_clock_extra_info
+ * - \ref asfdoc_sam0_system_clock_examples
+ * - \ref asfdoc_sam0_system_clock_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_clock_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_module_overview Module Overview
+ * The SAM devices contain a sophisticated clocking system, which is designed
+ * to give the maximum flexibility to the user application. This system allows
+ * a system designer to tune the performance and power consumption of the device
+ * in a dynamic manner, to achieve the best trade-off between the two for a
+ * particular application.
+ *
+ * This driver provides a set of functions for the configuration and management
+ * of the various clock related functionality within the device.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_SYSTEM_CLOCK_DPLL</td>
+ * <td>SAMD21, SAMR21, SAMD10, SAMD11</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
+ * The SAM devices have a number of master clock source modules, each of
+ * which being capable of producing a stabilized output frequency, which can then
+ * be fed into the various peripherals and modules within the device.
+ *
+ * Possible clock source modules include internal R/C oscillators, internal
+ * DFLL modules, as well as external crystal oscillators and/or clock inputs.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
+ * The CPU and AHB/APBx buses are clocked by the same physical clock source
+ * (referred in this module as the Main Clock), however the APBx buses may
+ * have additional prescaler division ratios set to give each peripheral bus a
+ * different clock speed.
+ *
+ * The general main clock tree for the CPU and associated buses is shown in
+ * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_clock_tree
+ * \dot
+ * digraph overview {
+ * rankdir=LR;
+ * clk_src [label="Clock Sources", shape=none, height=0];
+ * node [label="CPU Bus" shape=ellipse] cpu_bus;
+ * node [label="AHB Bus" shape=ellipse] ahb_bus;
+ * node [label="APBA Bus" shape=ellipse] apb_a_bus;
+ * node [label="APBB Bus" shape=ellipse] apb_b_bus;
+ * node [label="APBC Bus" shape=ellipse] apb_c_bus;
+ * node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
+ * node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
+ * node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
+ * node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
+ * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
+ *
+ * clk_src -> main_clock_mux;
+ * main_clock_mux -> main_prescaler;
+ * main_prescaler -> cpu_bus;
+ * main_prescaler -> ahb_bus;
+ * main_prescaler -> apb_a_prescaler;
+ * main_prescaler -> apb_b_prescaler;
+ * main_prescaler -> apb_c_prescaler;
+ * apb_a_prescaler -> apb_a_bus;
+ * apb_b_prescaler -> apb_b_bus;
+ * apb_c_prescaler -> apb_c_bus;
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
+ * To save power, the input clock to one or more peripherals on the AHB and APBx
+ * buses can be masked away - when masked, no clock is passed into the module.
+ * Disabling of clocks of unused modules will prevent all access to the masked
+ * module, but will reduce the overall device power consumption.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
+ * Within the SAM devices there are a number of Generic Clocks; these are used to
+ * provide clocks to the various peripheral clock domains in the device in a
+ * standardized manner. One or more master source clocks can be selected as the
+ * input clock to a Generic Clock Generator, which can prescale down the input
+ * frequency to a slower rate for use in a peripheral.
+ *
+ * Additionally, a number of individually selectable Generic Clock Channels are
+ * provided, which multiplex and gate the various generator outputs for one or
+ * more peripherals within the device. This setup allows for a single common
+ * generator to feed one or more channels, which can then be enabled or disabled
+ * individually as required.
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_overview
+ * \dot
+ * digraph overview {
+ * rankdir=LR;
+ * node [label="Clock\nSource a" shape=square] system_clock_source;
+ * node [label="Generator 1" shape=square] clock_gen;
+ * node [label="Channel x" shape=square] clock_chan0;
+ * node [label="Channel y" shape=square] clock_chan1;
+ * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
+ * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
+ *
+ * system_clock_source -> clock_gen;
+ * clock_gen -> clock_chan0;
+ * clock_chan0 -> peripheral0;
+ * clock_gen -> clock_chan1;
+ * clock_chan1 -> peripheral1;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
+ * An example setup of a complete clock chain within the device is shown in
+ * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_example_fig
+ * \dot
+ * digraph overview {
+ * rankdir=LR;
+ * node [label="External\nOscillator" shape=square] system_clock_source0;
+ * node [label="Generator 0" shape=square] clock_gen0;
+ * node [label="Channel x" shape=square] clock_chan0;
+ * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
+ *
+ * system_clock_source0 -> clock_gen0;
+ * clock_gen0 -> clock_chan0;
+ * clock_chan0 -> peripheral0;
+ * node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
+ * node [label="Generator 1" shape=square] clock_gen1;
+ * node [label="Channel y" shape=square] clock_chan1;
+ * node [label="Channel z" shape=square] clock_chan2;
+ * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
+ * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2;
+ *
+ * system_clock_source1 -> clock_gen1;
+ * clock_gen1 -> clock_chan1;
+ * clock_gen1 -> clock_chan2;
+ * clock_chan1 -> peripheral1;
+ * clock_chan2 -> peripheral2;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
+ * Each Generic Clock generator within the device can source its input clock
+ * from one of the provided Source Clocks, and prescale the output for one or
+ * more Generic Clock Channels in a one-to-many relationship. The generators
+ * thus allow for several clocks to be generated of different frequencies,
+ * power usages, and accuracies, which can be turned on and off individually to
+ * disable the clocks to multiple peripherals as a group.
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
+ * To connect a Generic Clock Generator to a peripheral within the
+ * device, a Generic Clock Channel is used. Each peripheral or
+ * peripheral group has an associated Generic Clock Channel, which serves as the
+ * clock input for the peripheral(s). To supply a clock to the peripheral
+ * module(s), the associated channel must be connected to a running Generic
+ * Clock Generator and the channel enabled.
+ *
+ * \section asfdoc_sam0_system_clock_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
+ * - \ref asfdoc_sam0_system_clock_extra_acronyms
+ * - \ref asfdoc_sam0_system_clock_extra_dependencies
+ * - \ref asfdoc_sam0_system_clock_extra_errata
+ * - \ref asfdoc_sam0_system_clock_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_clock_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_clock_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#include <status_codes.h>
+/**
+ * \name Driver Feature Definition
+ * Define system clock features set according to different device family.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || defined(__DOXYGEN__)
+/** Digital Phase Locked Loop (DPLL) feature support. */
+# define FEATURE_SYSTEM_CLOCK_DPLL
+#endif
+/*@}*/
+
+/**
+ * \brief Available start-up times for the XOSC32K.
+ *
+ * Available external 32KHz oscillator start-up times, as a number of external
+ * clock cycles.
+ */
+enum system_xosc32k_startup {
+ /** Wait zero clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_0,
+ /** Wait 32 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_32,
+ /** Wait 2048 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_2048,
+ /** Wait 4096 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_4096,
+ /** Wait 16384 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_16384,
+ /** Wait 32768 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_32768,
+ /** Wait 65536 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_65536,
+ /** Wait 131072 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC32K_STARTUP_131072,
+};
+
+/**
+ * \brief Available start-up times for the XOSC.
+ *
+ * Available external oscillator start-up times, as a number of external clock
+ * cycles.
+ */
+enum system_xosc_startup {
+ /** Wait one clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_1,
+ /** Wait two clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_2,
+ /** Wait four clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_4,
+ /** Wait eight clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_8,
+ /** Wait 16 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_16,
+ /** Wait 32 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_32,
+ /** Wait 64 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_64,
+ /** Wait 128 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_128,
+ /** Wait 256 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_256,
+ /** Wait 512 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_512,
+ /** Wait 1024 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_1024,
+ /** Wait 2048 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_2048,
+ /** Wait 4096 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_4096,
+ /** Wait 8192 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_8192,
+ /** Wait 16384 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_16384,
+ /** Wait 32768 clock cycles until the clock source is considered stable. */
+ SYSTEM_XOSC_STARTUP_32768,
+};
+
+/**
+ * \brief Available start-up times for the OSC32K.
+ *
+ * Available internal 32KHz oscillator start-up times, as a number of internal
+ * OSC32K clock cycles.
+ */
+enum system_osc32k_startup {
+ /** Wait three clock cycles until the clock source is considered stable. */
+ SYSTEM_OSC32K_STARTUP_3,
+ /** Wait four clock cycles until the clock source is considered stable. */
+ SYSTEM_OSC32K_STARTUP_4,
+ /** Wait six clock cycles until the clock source is considered stable. */
+ SYSTEM_OSC32K_STARTUP_6,
+ /** Wait ten clock cycles until the clock source is considered stable. */
+ SYSTEM_OSC32K_STARTUP_10,
+ /** Wait 18 clock cycles until the clock source is considered stable. */
+ SYSTEM_OSC32K_STARTUP_18,
+ /** Wait 34 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_34,
+ /** Wait 66 clock cycles until the clock source is considered stable. */
+ SYSTEM_OSC32K_STARTUP_66,
+ /** Wait 130 clock cycles until the clock source is considered stable. */
+ SYSTEM_OSC32K_STARTUP_130,
+};
+
+/**
+ * \brief Division prescalers for the internal 8MHz system clock.
+ *
+ * Available prescalers for the internal 8MHz (nominal) system clock.
+ */
+enum system_osc8m_div {
+ /** Do not divide the 8MHz RC oscillator output. */
+ SYSTEM_OSC8M_DIV_1,
+ /** Divide the 8MHz RC oscillator output by two. */
+ SYSTEM_OSC8M_DIV_2,
+ /** Divide the 8MHz RC oscillator output by four. */
+ SYSTEM_OSC8M_DIV_4,
+ /** Divide the 8MHz RC oscillator output by eight. */
+ SYSTEM_OSC8M_DIV_8,
+};
+
+/**
+ * \brief Frequency range for the internal 8MHz RC oscillator.
+ *
+ * Internal 8MHz RC oscillator frequency range setting
+ */
+enum system_osc8m_frequency_range {
+ /** Frequency range 4MHz to 6MHz. */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
+ /** Frequency range 6MHz to 8MHz. */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
+ /** Frequency range 8MHz to 11MHz. */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
+ /** Frequency range 11MHz to 15MHz. */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
+};
+
+/**
+ * \brief Main CPU and APB/AHB bus clock source prescaler values.
+ *
+ * Available division ratios for the CPU and APB/AHB bus clocks.
+ */
+enum system_main_clock_div {
+ /** Divide Main clock by one. */
+ SYSTEM_MAIN_CLOCK_DIV_1,
+ /** Divide Main clock by two. */
+ SYSTEM_MAIN_CLOCK_DIV_2,
+ /** Divide Main clock by four. */
+ SYSTEM_MAIN_CLOCK_DIV_4,
+ /** Divide Main clock by eight. */
+ SYSTEM_MAIN_CLOCK_DIV_8,
+ /** Divide Main clock by 16. */
+ SYSTEM_MAIN_CLOCK_DIV_16,
+ /** Divide Main clock by 32. */
+ SYSTEM_MAIN_CLOCK_DIV_32,
+ /** Divide Main clock by 64. */
+ SYSTEM_MAIN_CLOCK_DIV_64,
+ /** Divide Main clock by 128. */
+ SYSTEM_MAIN_CLOCK_DIV_128,
+};
+
+/**
+ * \brief External clock source types.
+ *
+ * Available external clock source types.
+ */
+enum system_clock_external {
+ /** The external clock source is a crystal oscillator. */
+ SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
+ /** The connected clock source is an external logic level clock signal. */
+ SYSTEM_CLOCK_EXTERNAL_CLOCK,
+};
+
+/**
+ * \brief Operating modes of the DFLL clock source.
+ *
+ * Available operating modes of the DFLL clock source module.
+ */
+enum system_clock_dfll_loop_mode {
+ /** The DFLL is operating in open loop mode with no feedback. */
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
+ /** The DFLL is operating in closed loop mode with frequency feedback from
+ * a low frequency reference clock.
+ */
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
+
+#ifdef SYSCTRL_DFLLCTRL_USBCRM
+ /** The DFLL is operating in USB recovery mode with frequency feedback
+ * from USB SOF.
+ */
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
+#endif
+};
+
+/**
+ * \brief Locking behavior for the DFLL during device wake-up.
+ *
+ * DFLL lock behavior modes on device wake-up from sleep.
+ */
+enum system_clock_dfll_wakeup_lock {
+ /** Keep DFLL lock when the device wakes from sleep. */
+ SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
+ /** Lose DFLL lock when the devices wakes from sleep. */
+ SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
+};
+
+/**
+ * \brief Fine tracking behavior for the DFLL once a lock has been acquired.
+ *
+ * DFLL fine tracking behavior modes after a lock has been acquired.
+ */
+enum system_clock_dfll_stable_tracking {
+ /** Keep tracking after the DFLL has gotten a fine lock. */
+ SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
+ /** Stop tracking after the DFLL has gotten a fine lock. */
+ SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
+};
+
+/**
+ * \brief Chill-cycle behavior of the DFLL module.
+ *
+ * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
+ * of time when the DFLL output frequency is not measured by the unit, to allow
+ * the output to stabilize after a change in the input clock source.
+ */
+enum system_clock_dfll_chill_cycle {
+ /** Enable a chill cycle, where the DFLL output frequency is not measured. */
+ SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
+ /** Disable a chill cycle, where the DFLL output frequency is not measured. */
+ SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
+};
+
+/**
+ * \brief QuickLock settings for the DFLL module.
+ *
+ * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
+ * the DFLL output frequency at the expense of accuracy.
+ */
+enum system_clock_dfll_quick_lock {
+ /** Enable the QuickLock feature for looser lock requirements on the DFLL. */
+ SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
+ /** Disable the QuickLock feature for strict lock requirements on the DFLL. */
+ SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
+};
+
+/**
+ * \brief Available clock sources in the system.
+ *
+ * Clock sources available to the GCLK generators.
+ */
+enum system_clock_source {
+ /** Internal 8MHz RC oscillator. */
+ SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M,
+ /** Internal 32KHz RC oscillator. */
+ SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
+ /** External oscillator. */
+ SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,
+ /** External 32KHz oscillator. */
+ SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
+ /** Digital Frequency Locked Loop (DFLL). */
+ SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
+ /** Internal Ultra Low Power 32KHz oscillator. */
+ SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
+ /** Generator input pad */
+ SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
+ /** Generic clock generator one output */
+ SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ /** Digital Phase Locked Loop (DPLL).
+ * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
+ */
+ SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
+#endif
+};
+
+/**
+ * \brief List of APB peripheral buses.
+ *
+ * Available bus clock domains on the APB bus.
+ */
+enum system_clock_apb_bus {
+ /** Peripheral bus A on the APB bus. */
+ SYSTEM_CLOCK_APB_APBA,
+ /** Peripheral bus B on the APB bus. */
+ SYSTEM_CLOCK_APB_APBB,
+ /** Peripheral bus C on the APB bus. */
+ SYSTEM_CLOCK_APB_APBC,
+};
+
+/**
+ * \brief Configuration structure for XOSC.
+ *
+ * External oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc_config {
+ /** External clock type. */
+ enum system_clock_external external_clock;
+ /** Crystal oscillator start-up time. */
+ enum system_xosc_startup startup_time;
+ /** Enable automatic amplitude gain control. */
+ bool auto_gain_control;
+ /** External clock/crystal frequency. */
+ uint32_t frequency;
+ /** Keep the XOSC enabled in standby sleep mode. */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the XOSC won't run
+ * until requested by a peripheral. */
+ bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for XOSC32K.
+ *
+ * External 32KHz oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc32k_config {
+ /** External clock type. */
+ enum system_clock_external external_clock;
+ /** Crystal oscillator start-up time. */
+ enum system_xosc32k_startup startup_time;
+ /** Enable automatic amplitude control. */
+ bool auto_gain_control;
+ /** Enable 1KHz output. */
+ bool enable_1khz_output;
+ /** Enable 32KHz output. */
+ bool enable_32khz_output;
+ /** External clock/crystal frequency. */
+ uint32_t frequency;
+ /** Keep the XOSC32K enabled in standby sleep mode. */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the XOSC32K won't run
+ * until requested by a peripheral. */
+ bool on_demand;
+ /** Lock configuration after it has been written,
+ * a device reset will release the lock. */
+ bool write_once;
+};
+
+/**
+ * \brief Configuration structure for OSC8M.
+ *
+ * Internal 8MHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc8m_config {
+ /* Internal 8MHz RC oscillator prescaler. */
+ enum system_osc8m_div prescaler;
+ /** Keep the OSC8M enabled in standby sleep mode. */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the OSC8M won't run
+ * until requested by a peripheral. */
+ bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for OSC32K.
+ *
+ * Internal 32KHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc32k_config {
+ /** Startup time. */
+ enum system_osc32k_startup startup_time;
+ /** Enable 1KHz output. */
+ bool enable_1khz_output;
+ /** Enable 32KHz output. */
+ bool enable_32khz_output;
+ /** Keep the OSC32K enabled in standby sleep mode. */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the OSC32K won't run
+ * until requested by a peripheral. */
+ bool on_demand;
+ /** Lock configuration after it has been written,
+ * a device reset will release the lock. */
+ bool write_once;
+};
+
+/**
+ * \brief Configuration structure for DFLL.
+ *
+ * DFLL oscillator configuration structure.
+ */
+struct system_clock_source_dfll_config {
+ /** Loop mode. */
+ enum system_clock_dfll_loop_mode loop_mode;
+ /** Run On Demand. If this is set the DFLL won't run
+ * until requested by a peripheral. */
+ bool on_demand;
+ /** Enable Quick Lock. */
+ enum system_clock_dfll_quick_lock quick_lock;
+ /** Enable Chill Cycle. */
+ enum system_clock_dfll_chill_cycle chill_cycle;
+ /** DFLL lock state on wakeup. */
+ enum system_clock_dfll_wakeup_lock wakeup_lock;
+ /** DFLL tracking after fine lock. */
+ enum system_clock_dfll_stable_tracking stable_tracking;
+ /** Coarse calibration value (Open loop mode). */
+ uint8_t coarse_value;
+ /** Fine calibration value (Open loop mode). */
+ uint16_t fine_value;
+ /** Coarse adjustment maximum step size (Closed loop mode). */
+ uint8_t coarse_max_step;
+ /** Fine adjustment maximum step size (Closed loop mode). */
+ uint16_t fine_max_step;
+ /** DFLL multiply factor (Closed loop mode. */
+ uint16_t multiply_factor;
+};
+
+/**
+ * \name External Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external oscillator module:
+ * - External Crystal
+ * - Start-up time of 16384 external clock cycles
+ * - Automatic crystal gain control mode enabled
+ * - Frequency of 12MHz
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc_get_config_defaults(
+ struct system_clock_source_xosc_config *const config)
+{
+ Assert(config);
+
+ config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+ config->startup_time = SYSTEM_XOSC_STARTUP_16384;
+ config->auto_gain_control = true;
+ config->frequency = 12000000UL;
+ config->run_in_standby = false;
+ config->on_demand = true;
+}
+
+void system_clock_source_xosc_set_config(
+ struct system_clock_source_xosc_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name External 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external 32KHz oscillator module:
+ * - External Crystal
+ * - Start-up time of 16384 external clock cycles
+ * - Automatic crystal gain control mode disabled
+ * - Frequency of 32.768KHz
+ * - 1KHz clock output disabled
+ * - 32KHz clock output enabled
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ * - Don't lock registers after configuration has been written
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc32k_get_config_defaults(
+ struct system_clock_source_xosc32k_config *const config)
+{
+ Assert(config);
+
+ config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+ config->startup_time = SYSTEM_XOSC32K_STARTUP_16384;
+ config->auto_gain_control = false;
+ config->frequency = 32768UL;
+ config->enable_1khz_output = false;
+ config->enable_32khz_output = true;
+ config->run_in_standby = false;
+ config->on_demand = true;
+ config->write_once = false;
+}
+
+void system_clock_source_xosc32k_set_config(
+ struct system_clock_source_xosc32k_config *const config);
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 32KHz oscillator module:
+ * - 1KHz clock output enabled
+ * - 32KHz clock output enabled
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ * - Set startup time to 130 cycles
+ * - Don't lock registers after configuration has been written
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc32k_get_config_defaults(
+ struct system_clock_source_osc32k_config *const config)
+{
+ Assert(config);
+
+ config->enable_1khz_output = true;
+ config->enable_32khz_output = true;
+ config->run_in_standby = false;
+ config->on_demand = true;
+ config->startup_time = SYSTEM_OSC32K_STARTUP_130;
+ config->write_once = false;
+}
+
+void system_clock_source_osc32k_set_config(
+ struct system_clock_source_osc32k_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 8MHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC8M.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 8MHz (nominal) oscillator module:
+ * - Clock output frequency divided by a factor of eight
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc8m_get_config_defaults(
+ struct system_clock_source_osc8m_config *const config)
+{
+ Assert(config);
+
+ config->prescaler = SYSTEM_OSC8M_DIV_8;
+ config->run_in_standby = false;
+ config->on_demand = true;
+}
+
+void system_clock_source_osc8m_set_config(
+ struct system_clock_source_osc8m_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal DFLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DFLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DFLL oscillator module:
+ * - Open loop mode
+ * - QuickLock mode enabled
+ * - Chill cycle enabled
+ * - Output frequency lock maintained during device wake-up
+ * - Continuous tracking of the output frequency
+ * - Default tracking values at the mid-points for both coarse and fine
+ * tracking parameters
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dfll_get_config_defaults(
+ struct system_clock_source_dfll_config *const config)
+{
+ Assert(config);
+
+ config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
+ config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+ config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+ config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+ config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+ config->on_demand = true;
+
+ /* Open loop mode calibration value */
+ config->coarse_value = 0x1f / 4; /* Midpoint */
+ config->fine_value = 0xff / 4; /* Midpoint */
+
+ /* Closed loop mode */
+ config->coarse_max_step = 1;
+ config->fine_max_step = 1;
+ config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
+}
+
+void system_clock_source_dfll_set_config(
+ struct system_clock_source_dfll_config *const config);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Clock Source Management
+ * @{
+ */
+enum status_code system_clock_source_write_calibration(
+ const enum system_clock_source system_clock_source,
+ const uint16_t calibration_value,
+ const uint8_t freq_range);
+
+enum status_code system_clock_source_enable(
+ const enum system_clock_source system_clock_source);
+
+enum status_code system_clock_source_disable(
+ const enum system_clock_source clk_source);
+
+bool system_clock_source_is_ready(
+ const enum system_clock_source clk_source);
+
+uint32_t system_clock_source_get_hz(
+ const enum system_clock_source clk_source);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Main Clock Management
+ * @{
+ */
+
+/**
+ * \brief Set main CPU clock divider.
+ *
+ * Sets the clock divider used on the main clock to provide the CPU clock.
+ *
+ * \param[in] divider CPU clock divider to set
+ */
+static inline void system_cpu_clock_set_divider(
+ const enum system_main_clock_div divider)
+{
+ Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
+ PM->CPUSEL.reg = (uint32_t)divider;
+}
+
+/**
+ * \brief Retrieves the current frequency of the CPU core.
+ *
+ * Retrieves the operating frequency of the CPU core, obtained from the main
+ * generic clock and the set CPU bus divider.
+ *
+ * \return Current CPU frequency in Hz.
+ */
+static inline uint32_t system_cpu_clock_get_hz(void)
+{
+ return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
+}
+
+/**
+ * \brief Set APBx clock divider.
+ *
+ * Set the clock divider used on the main clock to provide the clock for the
+ * given APBx bus.
+ *
+ * \param[in] divider APBx bus divider to set
+ * \param[in] bus APBx bus to set divider
+ *
+ * \returns Status of the clock division change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
+ * \retval STATUS_OK The APBx clock was set successfully
+ */
+static inline enum status_code system_apb_clock_set_divider(
+ const enum system_clock_apb_bus bus,
+ const enum system_main_clock_div divider)
+{
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ PM->APBASEL.reg = (uint32_t)divider;
+ break;
+ case SYSTEM_CLOCK_APB_APBB:
+ PM->APBBSEL.reg = (uint32_t)divider;
+ break;
+ case SYSTEM_CLOCK_APB_APBC:
+ PM->APBCSEL.reg = (uint32_t)divider;
+ break;
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+ }
+
+ /**
+ * \brief Retrieves the current frequency of a ABPx.
+ *
+ * Retrieves the operating frequency of an APBx bus, obtained from the main
+ * generic clock and the set APBx bus divider.
+ *
+ * \return Current APBx bus frequency in Hz.
+ */
+ static inline uint32_t system_apb_clock_get_hz(
+ const enum system_clock_apb_bus bus)
+{
+ uint16_t bus_divider = 0;
+
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ bus_divider = PM->APBASEL.reg;
+ break;
+ case SYSTEM_CLOCK_APB_APBB:
+ bus_divider = PM->APBBSEL.reg;
+ break;
+ case SYSTEM_CLOCK_APB_APBC:
+ bus_divider = PM->APBCSEL.reg;
+ break;
+ default:
+ Assert(false);
+ return 0;
+ }
+
+ return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * \name Bus Clock Masking
+ * @{
+ */
+
+/**
+ * \brief Set bits in the clock mask for the AHB bus.
+ *
+ * This function will set bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will enable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask AHB clock mask to enable
+ */
+static inline void system_ahb_clock_set_mask(
+ const uint32_t ahb_mask)
+{
+ PM->AHBMASK.reg |= ahb_mask;
+}
+
+/**
+ * \brief Clear bits in the clock mask for the AHB bus.
+ *
+ * This function will clear bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will disable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask AHB clock mask to disable
+ */
+static inline void system_ahb_clock_clear_mask(
+ const uint32_t ahb_mask)
+{
+ PM->AHBMASK.reg &= ~ahb_mask;
+}
+
+/**
+ * \brief Set bits in the clock mask for an APBx bus.
+ *
+ * This function will set bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will enable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ * the device header files
+ * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
+ * constants from the device header files
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus given
+ * \retval STATUS_OK The clock mask was set successfully
+ */
+static inline enum status_code system_apb_clock_set_mask(
+ const enum system_clock_apb_bus bus,
+ const uint32_t mask)
+{
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ PM->APBAMASK.reg |= mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBB:
+ PM->APBBMASK.reg |= mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBC:
+ PM->APBCMASK.reg |= mask;
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+
+ }
+
+ return STATUS_OK;
+ }
+
+ /**
+ * \brief Clear bits in the clock mask for an APBx bus.
+ *
+ * This function will clear bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will disable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ * the device header files
+ * \param[in] bus Bus to clear clock mask bits
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
+ * \retval STATUS_OK The clock mask was changed successfully
+ */
+ static inline enum status_code system_apb_clock_clear_mask(
+ const enum system_clock_apb_bus bus,
+ const uint32_t mask)
+{
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ PM->APBAMASK.reg &= ~mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBB:
+ PM->APBBMASK.reg &= ~mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBC:
+ PM->APBCMASK.reg &= ~mask;
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+ }
+
+ /**
+ * @}
+ */
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ /**
+ * \brief Reference clock source of the DPLL module.
+ */
+ enum system_clock_source_dpll_reference_clock {
+ /** Select CLK_DPLL_REF0 as clock reference. */
+ SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0,
+ /** Select CLK_DPLL_REF1 as clock reference. */
+ SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1,
+ /** Select GCLK_DPLL as clock reference. */
+ SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
+};
+
+/**
+ * \brief Lock time-out value of the DPLL module.
+ */
+enum system_clock_source_dpll_lock_time {
+ /** Set no time-out as default. */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
+ /** Set time-out if no lock within 8ms. */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
+ /** Set time-out if no lock within 9ms. */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
+ /** Set time-out if no lock within 10ms. */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
+ /** Set time-out if no lock within 11ms. */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
+};
+
+/**
+ * \brief Filter type of the DPLL module.
+ */
+enum system_clock_source_dpll_filter {
+ /** Default filter mode. */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
+ /** Low bandwidth filter. */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
+ /** High bandwidth filter. */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
+ /** High damping filter. */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
+};
+
+/**
+ * \brief Configuration structure for DPLL.
+ *
+ * DPLL oscillator configuration structure.
+ */
+struct system_clock_source_dpll_config {
+ /** Run On Demand. If this is set the DPLL won't run
+ * until requested by a peripheral. */
+ bool on_demand;
+ /** Keep the DPLL enabled in standby sleep mode. */
+ bool run_in_standby;
+ /** Bypass lock signal. */
+ bool lock_bypass;
+ /** Wake up fast. If this is set DPLL output clock is enabled after
+ * the startup time. */
+ bool wake_up_fast;
+ /** Enable low power mode. */
+ bool low_power_enable;
+
+ /** Output frequency of the clock. */
+ uint32_t output_frequency;
+ /** Reference frequency of the clock. */
+ uint32_t reference_frequency;
+ /** Devider of reference clock. */
+ uint16_t reference_divider;
+
+ /** Filter type of the DPLL module. */
+ enum system_clock_source_dpll_filter filter;
+ /** Lock time-out value of the DPLL module. */
+ enum system_clock_source_dpll_lock_time lock_time;
+ /** Reference clock source of the DPLL module. */
+ enum system_clock_source_dpll_reference_clock reference_clock;
+};
+
+/**
+ * \name Internal DPLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DPLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DPLL oscillator module:
+ * - Run only when requested by peripheral (on demand)
+ * - Don't run in STANDBY sleep mode
+ * - Lock bypass disabled
+ * - Fast wake up disabled
+ * - Low power mode disabled
+ * - Output frequency is 48MHz
+ * - Reference clock frequency is 32768Hz
+ * - Not divide reference clock
+ * - Select REF0 as reference clock
+ * - Set lock time to default mode
+ * - Use default filter
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dpll_get_config_defaults(
+ struct system_clock_source_dpll_config *const config)
+{
+ config->on_demand = true;
+ config->run_in_standby = false;
+ config->lock_bypass = false;
+ config->wake_up_fast = false;
+ config->low_power_enable = false;
+
+ config->output_frequency = 48000000;
+ config->reference_frequency = 32768;
+ config->reference_divider = 1;
+ config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0;
+
+ config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
+ config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
+};
+
+void system_clock_source_dpll_set_config(
+ struct system_clock_source_dpll_config *const config);
+
+/* @} */
+#endif
+
+/**
+ * \name System Clock Initialization
+ * @{
+ */
+
+void system_clock_init(void);
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Flash Wait States
+ * @{
+ */
+
+/**
+ * \brief Set flash controller wait states.
+ *
+ * Will set the number of wait states that are used by the onboard
+ * flash memory. The number of wait states depend on both device
+ * supply voltage and CPU speed. The required number of wait states
+ * can be found in the electrical characteristics of the device.
+ *
+ * \param[in] wait_states Number of wait states to use for internal flash
+ */
+static inline void system_flash_set_waitstates(uint8_t wait_states)
+{
+ Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+ ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+
+ NVMCTRL->CTRLB.bit.RWS = wait_states;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
+ *
+ * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>DFLL</td>
+ * <td>Digital Frequency Locked Loop</td>
+ * </tr>
+ * <tr>
+ * <td>MUX</td>
+ * <td>Multiplexer</td>
+ * </tr>
+ * <tr>
+ * <td>OSC32K</td>
+ * <td>Internal 32KHz Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>OSC8M</td>
+ * <td>Internal 8MHz Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>PLL</td>
+ * <td>Phase Locked Loop</td>
+ * </tr>
+ * <tr>
+ * <td>OSC</td>
+ * <td>Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>XOSC</td>
+ * <td>External Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>XOSC32K</td>
+ * <td>External 32KHz Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>AHB</td>
+ * <td>Advanced High-performance Bus</td>
+ * </tr>
+ * <tr>
+ * <td>APB</td>
+ * <td>Advanced Peripheral Bus</td>
+ * </tr>
+ * <tr>
+ * <td>DPLL</td>
+ * <td>Digital Phase Locked Loop</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_errata Errata
+ *
+ * - This driver implements workaround for errata 10558
+ *
+ * "Several reset values of SYSCTRL.INTFLAG are wrong (BOD and DFLL)"
+ * When system_init is called it will reset these interrupts flags before they are used.
+
+ * - This driver implements experimental workaround for errata 9905
+ *
+ * "The DFLL clock must be requested before being configured otherwise a
+ * write access to a DFLL register can freeze the device."
+ * This driver will enable and configure the DFLL before the ONDEMAND bit is set.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Corrected OSC32K startup time definitions
+ * \li Support locking of OSC32K and XOSC32K config register (default: false)
+ * \li Added DPLL support, functions added:
+ * \c system_clock_source_dpll_get_config_defaults() and
+ * \c system_clock_source_dpll_set_config()
+ * \li Moved gclk channel locking feature out of the config struct
+ * functions added:
+ * \c system_gclk_chan_lock(),
+ * \c system_gclk_chan_is_locked()
+ * \c system_gclk_chan_is_enabled() and
+ * \c system_gclk_gen_is_enabled()
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
+ * and configured to a failed/not running clock generator</td>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
+ * \li Fixed system_flash_set_waitstates() failing with an assertion
+ * if an odd number of wait states provided
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Updated dfll configuration function to implement workaround for
+ * errata 9905 in the DFLL module
+ * \li Updated \c system_clock_init() to reset interrupt flags before
+ * they are used, errata 10558
+ * \li Fixed \c system_clock_source_get_hz() to return correcy DFLL
+ * frequency number
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>\li Fixed \c system_clock_source_is_ready not returning the correct
+ * state for \c SYSTEM_CLOCK_SOURCE_OSC8M
+ * \li Renamed the various \c system_clock_source_*_get_default_config()
+ * functions to \c system_clock_source_*_get_config_defaults() to
+ * match the remainder of ASF
+ * \li Added OSC8M calibration constant loading from the device signature
+ * row when the oscillator is initialized
+ * \li Updated default configuration of the XOSC32 to disable Automatic
+ * Gain Control due to silicon errata
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in
+ * a selection of use cases. Note that QSGs can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_system_clock_basic_use_case
+ * - \subpage asfdoc_sam0_system_gclk_basic_use_case
+ *
+ * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos. Fixed missing steps in the Basic
+ * Use Case Quick Start Guide.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/gclk.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,522 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21 Generic Clock Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include <gclk.h>
+#include <clock.h>
+#include <system_interrupt.h>
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false if the module has completed synchronization
+ * \retval true if the module synchronization is ongoing
+ */
+static inline bool system_gclk_is_syncing(void)
+{
+ if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * \brief Initializes the GCLK driver.
+ *
+ * Initializes the Generic Clock module, disabling and resetting all active
+ * Generic Clock Generators and Channels to their power-on default values.
+ */
+void system_gclk_init(void)
+{
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+ /* Software reset the module to ensure it is re-initialized correctly */
+ GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+ while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
+ /* Wait for reset to complete */
+ }
+}
+
+/**
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock Generator configuration
+ * to the hardware module.
+ *
+ * \note Changing the clock source on the fly (on a running
+ * generator) can take additional time if the clock source is configured
+ * to only run on-demand (ONDEMAND bit is set) and it is not currently
+ * running (no peripheral is requesting the clock source). In this case
+ * the GCLK will request the new clock while still keeping a request to
+ * the old clock source until the new clock source is ready.
+ *
+ * \note This function will not start a generator that is not already running;
+ * to start the generator, call \ref system_gclk_gen_enable()
+ * after configuring a generator.
+ *
+ * \param[in] generator Generic Clock Generator index to configure
+ * \param[in] config Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+ const uint8_t generator,
+ struct system_gclk_gen_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Cache new register configurations to minimize sync requirements. */
+ uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+ uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos);
+
+ /* Select the requested source clock for the generator */
+ new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+ /* Configure the clock to be either high or low when disabled */
+ if (config->high_when_disabled) {
+ new_genctrl_config |= GCLK_GENCTRL_OOV;
+ }
+
+ /* Configure if the clock output to I/O pin should be enabled. */
+ if (config->output_enable) {
+ new_genctrl_config |= GCLK_GENCTRL_OE;
+ }
+
+ /* Set division factor */
+ if (config->division_factor > 1) {
+ /* Check if division is a power of two */
+ if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+ /* Determine the index of the highest bit set to get the
+ * division factor that must be loaded into the division
+ * register */
+
+ uint32_t div2_count = 0;
+
+ uint32_t mask;
+ for (mask = (1UL << 1); mask < config->division_factor;
+ mask <<= 1) {
+ div2_count++;
+ }
+
+ /* Set binary divider power of 2 division factor */
+ new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos;
+ new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+ } else {
+ /* Set integer division factor */
+
+ new_gendiv_config |=
+ (config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+ /* Enable non-binary division with increased duty cycle accuracy */
+ new_genctrl_config |= GCLK_GENCTRL_IDC;
+ }
+
+ }
+
+ /* Enable or disable the clock in standby mode */
+ if (config->run_in_standby) {
+ new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+ }
+
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the correct generator */
+ *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+ /* Write the new generator configuration */
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+ GCLK->GENDIV.reg = new_gendiv_config;
+
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+ GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Enables a Generic Clock Generator that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock Generator that was previously
+ * configured via a call to \ref system_gclk_gen_set_config().
+ *
+ * \param[in] generator Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+ const uint8_t generator)
+{
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ /* Enable generator */
+ GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock Generator that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock Generator that was previously
+ * started via a call to \ref system_gclk_gen_enable().
+ *
+ * \param[in] generator Generic Clock Generator index to disable
+ */
+void system_gclk_gen_disable(
+ const uint8_t generator)
+{
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ /* Disable generator */
+ GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+ while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
+ /* Wait for clock to become disabled */
+ }
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock Generator is enabled.
+ *
+ * \param[in] generator Generic Clock Generator index to check
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock Generator is enabled
+ * \retval false The Generic Clock Generator is disabled
+ */
+bool system_gclk_gen_is_enabled(
+ const uint8_t generator)
+{
+ bool enabled;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ /* Obtain the enabled status */
+ enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+ system_interrupt_leave_critical_section();
+
+ return enabled;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock generator.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * generator, used as a source to a Generic Clock Channel module.
+ *
+ * \param[in] generator Generic Clock Generator index
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+ const uint8_t generator)
+{
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the appropriate generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ /* Get the frequency of the source connected to the GCLK generator */
+ uint32_t gen_input_hz = system_clock_source_get_hz(
+ (enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+
+ uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+
+ /* Select the appropriate generator division register */
+ *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ uint32_t divider = GCLK->GENDIV.bit.DIV;
+
+ system_interrupt_leave_critical_section();
+
+ /* Check if the generator is using fractional or binary division */
+ if (!divsel && divider > 1) {
+ gen_input_hz /= divider;
+ } else if (divsel) {
+ gen_input_hz >>= (divider+1);
+ }
+
+ return gen_input_hz;
+}
+
+/**
+ * \brief Writes a Generic Clock configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock configuration to the
+ * hardware module. If the clock is currently running, it will be stopped.
+ *
+ * \note Once called the clock will not be running; to start the clock,
+ * call \ref system_gclk_chan_enable() after configuring a clock channel.
+ *
+ * \param[in] channel Generic Clock channel to configure
+ * \param[in] config Configuration settings for the clock
+ *
+ */
+void system_gclk_chan_set_config(
+ const uint8_t channel,
+ struct system_gclk_chan_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Cache the new config to reduce sync requirements */
+ uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+
+ /* Select the desired generic clock generator */
+ new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+
+ /* Disable generic clock channel */
+ system_gclk_chan_disable(channel);
+
+ /* Write the new configuration */
+ GCLK->CLKCTRL.reg = new_clkctrl_config;
+}
+
+/**
+ * \brief Enables a Generic Clock that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock that was previously
+ * configured via a call to \ref system_gclk_chan_set_config().
+ *
+ * \param[in] channel Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+ const uint8_t channel)
+{
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+ /* Enable the generic clock */
+ GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock that was previously started
+ * via a call to \ref system_gclk_chan_enable().
+ *
+ * \param[in] channel Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+ const uint8_t channel)
+{
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+ /* Sanity check WRTLOCK */
+ Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+
+ /* Switch to known-working source so that the channel can be disabled */
+ uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+ GCLK->CLKCTRL.bit.GEN = 0;
+
+ /* Disable the generic clock */
+ GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+ while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+ /* Wait for clock to become disabled */
+ }
+
+ /* Restore previous configured clock generator */
+ GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is enabled.
+ *
+ * \param[in] channel Generic Clock Channel index
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock channel is enabled
+ * \retval false The Generic Clock channel is disabled
+ */
+bool system_gclk_chan_is_enabled(
+ const uint8_t channel)
+{
+ bool enabled;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generic clock channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+ enabled = GCLK->CLKCTRL.bit.CLKEN;
+
+ system_interrupt_leave_critical_section();
+
+ return enabled;
+}
+
+/**
+ * \brief Locks a Generic Clock channel from further configuration writes.
+ *
+ * Locks a generic clock channel from further configuration writes. It is only
+ * possible to unlock the channel configuration through a power on reset.
+ *
+ * \param[in] channel Generic Clock channel to enable
+ */
+void system_gclk_chan_lock(
+ const uint8_t channel)
+{
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+ /* Lock the generic clock */
+ GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is locked.
+ *
+ * \param[in] channel Generic Clock Channel index
+ *
+ * \return The lock status.
+ * \retval true The Generic Clock channel is locked
+ * \retval false The Generic Clock channel is not locked
+ */
+bool system_gclk_chan_is_locked(
+ const uint8_t channel)
+{
+ bool locked;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generic clock channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+ locked = GCLK->CLKCTRL.bit.WRTLOCK;
+
+ system_interrupt_leave_critical_section();
+
+ return locked;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock channel.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * channel, used as a source to a device peripheral module.
+ *
+ * \param[in] channel Generic Clock Channel index
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+ const uint8_t channel)
+{
+ uint8_t gen_id;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generic clock channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+ gen_id = GCLK->CLKCTRL.bit.GEN;
+
+ system_interrupt_leave_critical_section();
+
+ /* Return the clock speed of the associated GCLK generator */
+ return system_gclk_gen_get_hz(gen_id);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/gclk.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,305 @@
+/**
+ * \file
+ *
+ * \brief SAM Generic Clock Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
+#define SYSTEM_CLOCK_GCLK_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_system_clock_group
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief List of available GCLK generators.
+ *
+ * List of Available GCLK generators. This enum is used in the peripheral
+ * device drivers to select the GCLK generator to be used for its operation.
+ *
+ * The number of GCLK generators available is device dependent.
+ */
+enum gclk_generator {
+ /** GCLK generator channel 0. */
+ GCLK_GENERATOR_0,
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
+ /** GCLK generator channel 1. */
+ GCLK_GENERATOR_1,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
+ /** GCLK generator channel 2. */
+ GCLK_GENERATOR_2,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
+ /** GCLK generator channel 3. */
+ GCLK_GENERATOR_3,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
+ /** GCLK generator channel 4. */
+ GCLK_GENERATOR_4,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
+ /** GCLK generator channel 5. */
+ GCLK_GENERATOR_5,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
+ /** GCLK generator channel 6. */
+ GCLK_GENERATOR_6,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
+ /** GCLK generator channel 7. */
+ GCLK_GENERATOR_7,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
+ /** GCLK generator channel 8. */
+ GCLK_GENERATOR_8,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
+ /** GCLK generator channel 9. */
+ GCLK_GENERATOR_9,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
+ /** GCLK generator channel 10. */
+ GCLK_GENERATOR_10,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
+ /** GCLK generator channel 11. */
+ GCLK_GENERATOR_11,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
+ /** GCLK generator channel 12. */
+ GCLK_GENERATOR_12,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
+ /** GCLK generator channel 13. */
+ GCLK_GENERATOR_13,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
+ /** GCLK generator channel 14. */
+ GCLK_GENERATOR_14,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
+ /** GCLK generator channel 15. */
+ GCLK_GENERATOR_15,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
+ /** GCLK generator channel 16. */
+ GCLK_GENERATOR_16,
+#endif
+};
+
+/**
+ * \brief Generic Clock Generator configuration structure.
+ *
+ * Configuration structure for a Generic Clock Generator channel. This
+ * structure should be initialized by the
+ * \ref system_gclk_gen_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_gclk_gen_config {
+ /** Source clock input channel index, see the \ref system_clock_source. */
+ uint8_t source_clock;
+ /** If \c true, the generator output level is high when disabled. */
+ bool high_when_disabled;
+ /** Integer division factor of the clock output compared to the input. */
+ uint32_t division_factor;
+ /** If \c true, the clock is kept enabled during device standby mode. */
+ bool run_in_standby;
+ /** If \c true, enables GCLK generator clock output to a GPIO pin. */
+ bool output_enable;
+};
+
+/**
+ * \brief Generic Clock configuration structure.
+ *
+ * Configuration structure for a Generic Clock channel. This structure
+ * should be initialized by the \ref system_gclk_chan_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct system_gclk_chan_config {
+ /** Generic Clock Generator source channel. */
+ enum gclk_generator source_generator;
+};
+
+/** \name Generic Clock Management
+ * @{
+ */
+void system_gclk_init(void);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Generators)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock Generator configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock Generator configuration structure to
+ * a set of known default values. This function should be called on all
+ * new instances of these configuration structures before being modified
+ * by the user application.
+ *
+ * The default configuration is as follows:
+ * \li Clock is generated undivided from the source frequency
+ * \li Clock generator output is low when the generator is disabled
+ * \li The input clock is sourced from input clock channel 0
+ * \li Clock will be disabled during sleep
+ * \li The clock output will not be routed to a physical GPIO pin
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void system_gclk_gen_get_config_defaults(
+ struct system_gclk_gen_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->division_factor = 1;
+ config->high_when_disabled = false;
+#if SAML21
+ config->source_clock = GCLK_SOURCE_OSC16M;
+#else
+ config->source_clock = GCLK_SOURCE_OSC8M;
+#endif
+ config->run_in_standby = false;
+ config->output_enable = false;
+}
+
+void system_gclk_gen_set_config(
+ const uint8_t generator,
+ struct system_gclk_gen_config *const config);
+
+void system_gclk_gen_enable(
+ const uint8_t generator);
+
+void system_gclk_gen_disable(
+ const uint8_t generator);
+
+bool system_gclk_gen_is_enabled(
+ const uint8_t generator);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Channels)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Clock is sourced from the Generic Clock Generator channel 0
+ * \li Clock configuration will not be write-locked when set
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void system_gclk_chan_get_config_defaults(
+ struct system_gclk_chan_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->source_generator = GCLK_GENERATOR_0;
+}
+
+void system_gclk_chan_set_config(
+ const uint8_t channel,
+ struct system_gclk_chan_config *const config);
+
+void system_gclk_chan_enable(
+ const uint8_t channel);
+
+void system_gclk_chan_disable(
+ const uint8_t channel);
+
+bool system_gclk_chan_is_enabled(
+ const uint8_t channel);
+
+void system_gclk_chan_lock(
+ const uint8_t channel);
+
+bool system_gclk_chan_is_locked(
+ const uint8_t channel);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Frequency Retrieval
+ * @{
+ */
+
+uint32_t system_gclk_gen_get_hz(
+ const uint8_t generator);
+
+uint32_t system_gclk_chan_get_hz(
+ const uint8_t channel);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,217 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include "system_interrupt.h"
+
+/**
+ * \brief Check if a interrupt line is pending.
+ *
+ * Checks if the requested interrupt vector is pending.
+ *
+ * \param[in] vector Interrupt vector number to check
+ *
+ * \returns A boolean identifying if the requested interrupt vector is pending.
+ *
+ * \retval true Specified interrupt vector is pending
+ * \retval false Specified interrupt vector is not pending
+ *
+ */
+bool system_interrupt_is_pending(
+ const enum system_interrupt_vector vector)
+{
+ bool result;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
+ } else {
+ Assert(false);
+ result = false;
+ }
+
+ return result;
+}
+
+/**
+ * \brief Set a interrupt vector as pending.
+ *
+ * Set the requested interrupt vector as pending (i.e issues a software
+ * interrupt request for the specified vector). The software handler will be
+ * handled (if enabled) in a priority order based on vector number and
+ * configured priority settings.
+ *
+ * \param[in] vector Interrupt vector number which is set as pending
+ *
+ * \returns Status code identifying if the vector was successfully set as
+ * pending.
+ *
+ * \retval STATUS_OK If no error was detected
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_pending(
+ const enum system_interrupt_vector vector)
+{
+ enum status_code status = STATUS_OK;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ NVIC->ISPR[0] = (1 << vector);
+ } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+ /* Note: Because NMI has highest priority it will be executed
+ * immediately after it has been set pending */
+ SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+ } else {
+ /* The user want to set something unsupported as pending */
+ Assert(false);
+ status = STATUS_ERR_INVALID_ARG;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Clear pending interrupt vector.
+ *
+ * Clear a pending interrupt vector, so the software handler is not executed.
+ *
+ * \param[in] vector Interrupt vector number to clear
+ *
+ * \returns A status code identifying if the interrupt pending state was
+ * successfully cleared.
+ *
+ * \retval STATUS_OK If no error was detected
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_clear_pending(
+ const enum system_interrupt_vector vector)
+{
+ enum status_code status = STATUS_OK;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ NVIC->ICPR[0] = (1 << vector);
+ } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+ /* Note: Clearing of NMI pending interrupts does not make sense and is
+ * not supported by the device, as it has the highest priority and will
+ * always be executed at the moment it is set */
+ return STATUS_ERR_INVALID_ARG;
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+ } else {
+ Assert(false);
+ status = STATUS_ERR_INVALID_ARG;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Set interrupt vector priority level.
+ *
+ * Set the priority level of an external interrupt or exception.
+ *
+ * \param[in] vector Interrupt vector to change
+ * \param[in] priority_level New vector priority level to set
+ *
+ * \returns Status code indicating if the priority level of the interrupt was
+ * successfully set.
+ *
+ * \retval STATUS_OK If no error was detected
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_priority(
+ const enum system_interrupt_vector vector,
+ const enum system_interrupt_priority_level priority_level)
+{
+ enum status_code status = STATUS_OK;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ uint8_t register_num = vector / 4;
+ uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+ NVIC->IP[register_num] =
+ (NVIC->IP[register_num] & ~(0x3 << priority_pos)) |
+ (priority_level << priority_pos);
+
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
+ } else {
+ Assert(false);
+ status = STATUS_ERR_INVALID_ARG;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Get interrupt vector priority level.
+ *
+ * Retrieves the priority level of the requested external interrupt or exception.
+ *
+ * \param[in] vector Interrupt vector of which the priority level will be read
+ *
+ * \return Currently configured interrupt priority level of the given interrupt
+ * vector.
+ */
+enum system_interrupt_priority_level system_interrupt_get_priority(
+ const enum system_interrupt_vector vector)
+{
+ uint8_t register_num = vector / 4;
+ uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+ enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
+
+ if (vector >= 0) {
+ priority = (enum system_interrupt_priority_level)
+ ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ priority = (enum system_interrupt_priority_level)
+ ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+ }
+
+ return priority;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,440 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef SYSTEM_INTERRUPT_H_INCLUDED
+#define SYSTEM_INTERRUPT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt Driver (SYSTEM INTERRUPT)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of internal software and hardware interrupts/exceptions.
+ *
+ * The following peripherals are used by this module:
+ * - NVIC (Nested Vector Interrupt Controller)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_interrupt_prerequisites
+ * - \ref asfdoc_sam0_system_interrupt_module_overview
+ * - \ref asfdoc_sam0_system_interrupt_special_considerations
+ * - \ref asfdoc_sam0_system_interrupt_extra_info
+ * - \ref asfdoc_sam0_system_interrupt_examples
+ * - \ref asfdoc_sam0_system_interrupt_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_module_overview Module Overview
+ *
+ * The ARM® Cortex® M0+ core contains an interrupt and exception vector table, which
+ * can be used to configure the device's interrupt handlers; individual
+ * interrupts and exceptions can be enabled and disabled, as well as configured
+ * with a variable priority.
+ *
+ * This driver provides a set of wrappers around the core interrupt functions,
+ * to expose a simple API for the management of global and individual interrupts
+ * within the device.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
+ * In some applications it is important to ensure that no interrupts may be
+ * executed by the system whilst a critical portion of code is being run; for
+ * example, a buffer may be copied from one context to another - during which
+ * interrupts must be disabled to avoid corruption of the source buffer contents
+ * until the copy has completed. This driver provides a basic API to enter and
+ * exit nested critical sections, so that global interrupts can be kept disabled
+ * for as long as necessary to complete a critical application code section.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
+ * For some applications, it may be desirable to raise a module or core
+ * interrupt via software. For this reason, a set of APIs to set an interrupt or
+ * exception as pending are provided to the user application.
+ *
+ * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
+ *
+ * Interrupts from peripherals in the SAM devices are on a per-module basis;
+ * an interrupt raised from any source within a module will cause a single,
+ * module-common handler to execute. It is the user application or driver's
+ * responsibility to de-multiplex the module-common interrupt to determine the
+ * exact interrupt cause.
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes:
+ * - \ref asfdoc_sam0_system_interrupt_extra_acronyms
+ * - \ref asfdoc_sam0_system_interrupt_extra_dependencies
+ * - \ref asfdoc_sam0_system_interrupt_extra_errata
+ * - \ref asfdoc_sam0_system_interrupt_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_interrupt_exqsg.
+ *
+ * \section asfdoc_sam0_system_interrupt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+//#include <core_cm0plus.h>
+#include "system_interrupt_features.h"
+
+#include <interrupt_sam_nvic.h>
+#include "status_codes.h"
+/**
+ * \brief Table of possible system interrupt/exception vector priorities.
+ *
+ * Table of all possible interrupt and exception vector priorities within the
+ * device.
+ */
+enum system_interrupt_priority_level {
+ /** Priority level 0, the highest possible interrupt priority. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0,
+ /** Priority level 1. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1,
+ /** Priority level 2. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2,
+ /** Priority level 3, the lowest possible interrupt priority. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3,
+};
+
+/**
+ * \name Critical Section Management
+ * @{
+ */
+
+/**
+ * \brief Enters a critical section.
+ *
+ * Disables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_enter_critical_section(void)
+{
+ cpu_irq_enter_critical();
+}
+
+/**
+ * \brief Leaves a critical section.
+ *
+ * Enables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_leave_critical_section(void)
+{
+ cpu_irq_leave_critical();
+}
+
+/** @} */
+
+/**
+ * \name Interrupt Enabling/Disabling
+ * @{
+ */
+
+/**
+ * \brief Check if global interrupts are enabled.
+ *
+ * Checks if global interrupts are currently enabled.
+ *
+ * \returns A boolean that identifies if the global interrupts are enabled or not.
+ *
+ * \retval true Global interrupts are currently enabled
+ * \retval false Global interrupts are currently disabled
+ *
+ */
+static inline bool system_interrupt_is_global_enabled(void)
+{
+ return cpu_irq_is_enabled();
+}
+
+/**
+ * \brief Enables global interrupts.
+ *
+ * Enables global interrupts in the device to fire any enabled interrupt handlers.
+ */
+static inline void system_interrupt_enable_global(void)
+{
+ cpu_irq_enable();
+}
+
+/**
+ * \brief Disables global interrupts.
+ *
+ * Disabled global interrupts in the device, preventing any enabled interrupt
+ * handlers from executing.
+ */
+static inline void system_interrupt_disable_global(void)
+{
+ cpu_irq_disable();
+}
+
+/**
+ * \brief Checks if an interrupt vector is enabled or not.
+ *
+ * Checks if a specific interrupt vector is currently enabled.
+ *
+ * \param[in] vector Interrupt vector number to check
+ *
+ * \returns A variable identifying if the requested interrupt vector is enabled.
+ *
+ * \retval true Specified interrupt vector is currently enabled
+ * \retval false Specified interrupt vector is currently disabled
+ *
+ */
+static inline bool system_interrupt_is_enabled(
+ const enum system_interrupt_vector vector)
+{
+ return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
+}
+
+/**
+ * \brief Enable interrupt vector.
+ *
+ * Enables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to enable
+ */
+static inline void system_interrupt_enable(
+ const enum system_interrupt_vector vector)
+{
+ NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/**
+ * \brief Disable interrupt vector.
+ *
+ * Disables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to disable
+ */
+static inline void system_interrupt_disable(
+ const enum system_interrupt_vector vector)
+{
+ NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/** @} */
+
+/**
+ * \name Interrupt State Management
+ * @{
+ */
+
+/**
+ * \brief Get active interrupt (if any).
+ *
+ * Return the vector number for the current executing software handler, if any.
+ *
+ * \return Interrupt number that is currently executing.
+ */
+static inline enum system_interrupt_vector system_interrupt_get_active(void)
+{
+ uint32_t IPSR = __get_IPSR();
+
+ return (enum system_interrupt_vector)(IPSR & _SYSTEM_INTERRUPT_IPSR_MASK);
+}
+
+bool system_interrupt_is_pending(
+ const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_set_pending(
+ const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_clear_pending(
+ const enum system_interrupt_vector vector);
+
+/** @} */
+
+/**
+ * \name Interrupt Priority Management
+ * @{
+ */
+
+enum status_code system_interrupt_set_priority(
+ const enum system_interrupt_vector vector,
+ const enum system_interrupt_priority_level priority_level);
+
+enum system_interrupt_priority_level system_interrupt_get_priority(
+ const enum system_interrupt_vector vector);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>ISR</td>
+ * <td>Interrupt Service Routine</td>
+ * </tr>
+ * <tr>
+ * <td>NMI</td>
+ * <td>Non-maskable Interrupt</td>
+ * </tr>
+ * <tr>
+ * <td>SERCOM</td>
+ * <td>Serial Communication Interface</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMR21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
+ * - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
+ *
+ * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>11/2014</td>
+ * <td>Add support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Add support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Add support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,182 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 System Interrupt Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+
+#if !defined(__DOXYGEN__)
+
+/* Generates a interrupt vector table enum list entry for a given module type
+ and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
+# define _MODULE_IRQn(n, module) \
+ SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+
+/* Generates interrupt vector table enum list entries for all instances of a
+ given module type on the selected device. */
+# define _SYSTEM_INTERRUPT_MODULES(name) \
+ MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+
+# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f
+# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000007
+
+# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0
+
+# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 29
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_interrupt_group
+ * @{
+ */
+
+/**
+ * \brief Table of possible system interrupt/exception vector numbers.
+ *
+ * Table of all possible interrupt and exception vector indexes within the
+ * SAMD21 device.
+ */
+#if defined(__DOXYGEN__)
+/** \note The actual enumeration name is "system_interrupt_vector". */
+enum system_interrupt_vector_samd21 {
+#else
+enum system_interrupt_vector {
+#endif
+ /** Interrupt vector index for a NMI interrupt. */
+ SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn,
+ /** Interrupt vector index for a Hard Fault memory access exception. */
+ SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn,
+ /** Interrupt vector index for a Supervisor Call exception. */
+ SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn,
+ /** Interrupt vector index for a Pending Supervisor interrupt. */
+ SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn,
+ /** Interrupt vector index for a System Tick interrupt. */
+ SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn,
+
+ /** Interrupt vector index for a Power Manager peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn,
+ /** Interrupt vector index for a System Control peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn,
+ /** Interrupt vector index for a Watch Dog peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn,
+ /** Interrupt vector index for a Real Time Clock peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn,
+ /** Interrupt vector index for an External Interrupt peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn,
+ /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */
+ SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn,
+ /** Interrupt vector index for a Direct Memory Access interrupt. */
+ SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn,
+ /** Interrupt vector index for a Universal Serial Bus interrupt. */
+ SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn,
+ /** Interrupt vector index for an Event System interrupt. */
+ SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn,
+#if defined(__DOXYGEN__)
+ /** Interrupt vector index for a SERCOM peripheral interrupt.
+ *
+ * Each specific device may contain several SERCOM peripherals; each module
+ * instance will have its own entry in the table, with the instance number
+ * substituted for "n" in the entry name (e.g.
+ * \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+ */
+ SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn,
+
+ /** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
+ *
+ * Each specific device may contain several TCC peripherals; each module
+ * instance will have its own entry in the table, with the instance number
+ * substituted for "n" in the entry name (e.g.
+ * \c SYSTEM_INTERRUPT_MODULE_TCC0).
+ */
+ SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn,
+
+ /** Interrupt vector index for a Timer/Counter peripheral interrupt.
+ *
+ * Each specific device may contain several TC peripherals; each module
+ * instance will have its own entry in the table, with the instance number
+ * substituted for "n" in the entry name (e.g.
+ * \c SYSTEM_INTERRUPT_MODULE_TC3).
+ */
+ SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn,
+#else
+ //_SYSTEM_INTERRUPT_MODULES(SERCOM)
+ SYSTEM_INTERRUPT_MODULE_SERCOM0 = SERCOM0_IRQn,
+ SYSTEM_INTERRUPT_MODULE_SERCOM1 = SERCOM1_IRQn,
+ SYSTEM_INTERRUPT_MODULE_SERCOM2 = SERCOM2_IRQn,
+ SYSTEM_INTERRUPT_MODULE_SERCOM3 = SERCOM3_IRQn,
+ SYSTEM_INTERRUPT_MODULE_SERCOM4 = SERCOM4_IRQn,
+ SYSTEM_INTERRUPT_MODULE_SERCOM5 = SERCOM5_IRQn,
+
+ //_SYSTEM_INTERRUPT_MODULES(TCC)
+ SYSTEM_INTERRUPT_MODULE_TCC0 = TCC0_IRQn,
+ SYSTEM_INTERRUPT_MODULE_TCC1 = TCC1_IRQn,
+ SYSTEM_INTERRUPT_MODULE_TCC2 = TCC2_IRQn,
+
+ SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn,
+ SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn,
+ SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn,
+# if (SAMD21J)
+ SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn,
+ SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn,
+# endif
+#endif
+
+ /** Interrupt vector index for an Analog Comparator peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn,
+ /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn,
+ /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn,
+ /** Interrupt vector index for a Peripheral Touch Controller peripheral
+ * interrupt. */
+ SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn,
+ /** Interrupt vector index for a Inter-IC Sound Interface peripheral
+ * interrupt. */
+ SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn,
+};
+
+/** @} */
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,311 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#include <pinmux.h>
+
+/**
+ * \internal
+ * Writes out a given configuration of a Port pin configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] pin_mask Mask of the port pin to configure
+ * \param[in] config Configuration settings for the pin
+ */
+static void _system_pinmux_config(
+ PortGroup *const port,
+ const uint32_t pin_mask,
+ const struct system_pinmux_config *const config)
+{
+ Assert(port);
+ Assert(config);
+
+ /* Track the configuration bits into a temporary variable before writing */
+ uint32_t pin_cfg = 0;
+
+ /* Enabled powersave mode, don't create configuration */
+ if (!config->powersave) {
+ /* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
+ * be written later) and store the new MUX mask */
+ if (config->mux_position != SYSTEM_PINMUX_GPIO) {
+ pin_cfg |= PORT_WRCONFIG_PMUXEN;
+ pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+ }
+
+ /* Check if the user has requested that the input buffer be enabled */
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+ /* Enable input buffer flag */
+ pin_cfg |= PORT_WRCONFIG_INEN;
+
+ /* Enable pull-up/pull-down control flag if requested */
+ if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
+ pin_cfg |= PORT_WRCONFIG_PULLEN;
+ }
+
+ /* Clear the port DIR bits to disable the output buffer */
+ port->DIRCLR.reg = pin_mask;
+ }
+
+ /* Check if the user has requested that the output buffer be enabled */
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+ /* Cannot use a pullup if the output driver is enabled,
+ * if requested the input buffer can only sample the current
+ * output state */
+ pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+ }
+ } else {
+ port->DIRCLR.reg = pin_mask;
+ }
+
+ /* The Write Configuration register (WRCONFIG) requires the
+ * pins to to grouped into two 16-bit half-words - split them out here */
+ uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+ uint32_t upper_pin_mask = (pin_mask >> 16);
+
+ /* Configure the lower 16-bits of the port to the desired configuration,
+ * including the pin peripheral multiplexer just in case it is enabled */
+ port->WRCONFIG.reg
+ = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+ pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+ /* Configure the upper 16-bits of the port to the desired configuration,
+ * including the pin peripheral multiplexer just in case it is enabled */
+ port->WRCONFIG.reg
+ = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+ pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+ PORT_WRCONFIG_HWSEL;
+
+ if(!config->powersave) {
+ /* Set the pull-up state once the port pins are configured if one was
+ * requested and it does not violate the valid set of port
+ * configurations */
+ if (pin_cfg & PORT_WRCONFIG_PULLEN) {
+ /* Set the OUT register bits to enable the pullup if requested,
+ * clear to enable pull-down */
+ if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
+ port->OUTSET.reg = pin_mask;
+ } else {
+ port->OUTCLR.reg = pin_mask;
+ }
+ }
+
+ /* Check if the user has requested that the output buffer be enabled */
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+ /* Set the port DIR bits to enable the output buffer */
+ port->DIRSET.reg = pin_mask;
+ }
+ }
+}
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] config Configuration settings for the pin
+ */
+void system_pinmux_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct system_pinmux_config *const config)
+{
+ PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ _system_pinmux_config(port, pin_mask, config);
+}
+
+/**
+ * \brief Writes a Port pin group configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] config Configuration settings for the pin
+ */
+void system_pinmux_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct system_pinmux_config *const config)
+{
+ Assert(port);
+
+ for (int i = 0; i < 32; i++) {
+ if (mask & (1UL << i)) {
+ _system_pinmux_config(port, (1UL << i), config);
+ }
+ }
+}
+
+/**
+ * \brief Configures the input sampling mode for a group of pins.
+ *
+ * Configures the input sampling mode for a group of pins, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New pin sampling mode to configure
+ */
+void system_pinmux_group_set_input_sample_mode(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_sample mode)
+{
+ Assert(port);
+
+ if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+ port->CTRL.reg |= mask;
+ } else {
+ port->CTRL.reg &= ~mask;
+ }
+}
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Configures the output slew rate mode for a group of pins.
+ *
+ * Configures the output slew rate mode for a group of pins, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New pin slew rate mode to configure
+ */
+void system_pinmux_group_set_output_slew_rate(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_slew_rate mode)
+{
+ Assert(port);
+
+ for (int i = 0; i < 32; i++) {
+ if (mask & (1UL << i)) {
+ if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+ port->PINCFG[i].reg |= PORT_PINCFG_SLEWLIM;
+ } else {
+ port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
+ }
+ }
+ }
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Configures the output driver strength mode for a group of pins.
+ *
+ * Configures the output drive strength for a group of pins, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New output driver strength mode to configure
+ */
+void system_pinmux_group_set_output_strength(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_strength mode)
+{
+ Assert(port);
+
+ for (int i = 0; i < 32; i++) {
+ if (mask & (1UL << i)) {
+ if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+ port->PINCFG[i].reg |= PORT_PINCFG_DRVSTR;
+ } else {
+ port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
+ }
+ }
+ }
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Configures the output driver mode for a group of pins.
+ *
+ * Configures the output driver mode for a group of pins, to
+ * control the pad behavior.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New pad output driver mode to configure
+ */
+void system_pinmux_group_set_output_drive(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_drive mode)
+{
+ Assert(port);
+
+ for (int i = 0; i < 32; i++) {
+ if (mask & (1UL << i)) {
+ if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+ port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
+ } else {
+ port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
+ }
+ }
+ }
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,676 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef PINMUX_H_INCLUDED
+#define PINMUX_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer Driver (SYSTEM PINMUX)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the device's physical I/O Pins, to alter the direction and
+ * input/drive characteristics as well as to configure the pin peripheral
+ * multiplexer selection.
+ *
+ * The following peripherals are used by this module:
+ * - PORT (Port I/O Management)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * Physically, the modules are interconnected within the device as shown in the
+ * following diagram:
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_pinmux_prerequisites
+ * - \ref asfdoc_sam0_system_pinmux_module_overview
+ * - \ref asfdoc_sam0_system_pinmux_special_considerations
+ * - \ref asfdoc_sam0_system_pinmux_extra_info
+ * - \ref asfdoc_sam0_system_pinmux_examples
+ * - \ref asfdoc_sam0_system_pinmux_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_module_overview Module Overview
+ *
+ * The SAM devices contain a number of General Purpose I/O pins, used to
+ * interface the user application logic and internal hardware peripherals to
+ * an external system. The Pin Multiplexer (PINMUX) driver provides a method
+ * of configuring the individual pin peripheral multiplexers to select
+ * alternate pin functions.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH</td>
+ * <td>SAML21</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
+ * SAM devices contain a peripheral MUX, which is individually controllable
+ * for each I/O pin of the device. The peripheral MUX allows you to select the
+ * function of a physical package pin - whether it will be controlled as a user
+ * controllable GPIO pin, or whether it will be connected internally to one of
+ * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
+ * configured in GPIO mode, other peripherals connected to the same pin will be
+ * disabled.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
+ * There are several special modes that can be selected on one or more I/O pins
+ * of the device, which alter the input and output characteristics of the pad.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
+ * The Drive Strength configures the strength of the output driver on the
+ * pad. Normally, there is a fixed current limit that each I/O pin can safely
+ * drive, however some I/O pads offer a higher drive mode which increases this
+ * limit for that I/O pin at the expense of an increased power consumption.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
+ * The Slew Rate configures the slew rate of the output driver, limiting the
+ * rate at which the pad output voltage can change with time.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
+ * The Input Sample Mode configures the input sampler buffer of the pad. By
+ * default, the input buffer is only sampled "on-demand", i.e. when the user
+ * application attempts to read from the input buffer. This mode is the most
+ * power efficient, but increases the latency of the input sample by two clock
+ * cycles of the port clock. To reduce latency, the input sampler can instead
+ * be configured to always sample the input buffer on each port clock cycle, at
+ * the expense of an increased power consumption.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
+ * how this module is interconnected within the device:
+ *
+ * \anchor asfdoc_sam0_system_pinmux_intconnections
+ * \dot
+ * digraph overview {
+ * node [label="Port Pad" shape=square] pad;
+ *
+ * subgraph driver {
+ * node [label="Peripheral MUX" shape=trapezium] pinmux;
+ * node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
+ * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ * }
+ *
+ * pinmux -> gpio;
+ * pad -> pinmux;
+ * pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampling mode is set in groups of four physical
+ * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
+ * will configure the sampling mode of the entire sub-group.
+ *
+ * High Drive Strength output driver mode is not available on all device pins -
+ * refer to your device specific datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes:
+ * - \ref asfdoc_sam0_system_pinmux_extra_acronyms
+ * - \ref asfdoc_sam0_system_pinmux_extra_dependencies
+ * - \ref asfdoc_sam0_system_pinmux_extra_errata
+ * - \ref asfdoc_sam0_system_pinmux_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_pinmux_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*@{*/
+#if (SAML21) || defined(__DOXYGEN__)
+/** Output Driver Strength Selection feature support. */
+# define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+#endif
+/*@}*/
+
+/** Peripheral multiplexer index to select GPIO mode for a pin. */
+#define SYSTEM_PINMUX_GPIO (1 << 7)
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum system_pinmux_pin_dir {
+ /** The pin's input buffer should be enabled, so that the pin state can
+ * be read. */
+ SYSTEM_PINMUX_PIN_DIR_INPUT,
+ /** The pin's output buffer should be enabled, so that the pin state can
+ * be set (but not read back). */
+ SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+ /** The pin's output and input buffers should both be enabled, so that the
+ * pin state can be set and read back. */
+ SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum system_pinmux_pin_pull {
+ /** No logical pull should be applied to the pin. */
+ SYSTEM_PINMUX_PIN_PULL_NONE,
+ /** Pin should be pulled up when idle. */
+ SYSTEM_PINMUX_PIN_PULL_UP,
+ /** Pin should be pulled down when idle. */
+ SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+/**
+ * \brief Port pin digital input sampling mode enum.
+ *
+ * Enum for the possible input sampling modes for the port pin configuration
+ * structure, to indicate the type of sampling a port pin should use.
+ */
+enum system_pinmux_pin_sample {
+ /** Pin input buffer should continuously sample the pin state. */
+ SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
+ /** Pin input buffer should be enabled when the IN register is read. */
+ SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
+};
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should be
+ * structure should be initialized by the
+ * \ref system_pinmux_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_pinmux_config {
+ /** MUX index of the peripheral that should control the pin, if peripheral
+ * control is desired. For GPIO use, this should be set to
+ * \ref SYSTEM_PINMUX_GPIO. */
+ uint8_t mux_position;
+
+ /** Port buffer input/output direction. */
+ enum system_pinmux_pin_dir direction;
+
+ /** Logic level pull of the input buffer. */
+ enum system_pinmux_pin_pull input_pull;
+
+ /** Enable lowest possible powerstate on the pin.
+ *
+ * \note All other configurations will be ignored, the pin will be disabled.
+ */
+ bool powersave;
+};
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin configuration structure to defaults.
+ *
+ * Initializes a given Port pin configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Non peripheral (i.e. GPIO) controlled
+ * \li Input mode with internal pull-up enabled
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void system_pinmux_get_config_defaults(
+ struct system_pinmux_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->mux_position = SYSTEM_PINMUX_GPIO;
+ config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
+ config->powersave = false;
+}
+
+void system_pinmux_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct system_pinmux_config *const config);
+
+void system_pinmux_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct system_pinmux_config *const config);
+
+/** @} */
+
+/** \name Special Mode Configuration (Physical Group Orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to convert
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
+ const uint8_t gpio_pin)
+{
+ uint8_t port_index = (gpio_pin / 128);
+ uint8_t group_index = (gpio_pin / 32);
+
+ /* Array of available ports. */
+ Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+ if (port_index < PORT_INST_NUM) {
+ return &(ports[port_index]->Group[group_index]);
+ } else {
+ Assert(false);
+ return NULL;
+ }
+}
+
+void system_pinmux_group_set_input_sample_mode(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_sample mode);
+
+/** @} */
+
+/** \name Special Mode Configuration (Logical Pin Orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the currently selected MUX position of a logical pin.
+ *
+ * Retrieves the selected MUX peripheral on a given logical GPIO pin.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ *
+ * \return Currently selected peripheral index on the specified pin.
+ */
+static inline uint8_t system_pinmux_pin_get_mux_position(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_index = (gpio_pin % 32);
+
+ if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
+ return SYSTEM_PINMUX_GPIO;
+ }
+
+ uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
+
+ if (pin_index & 1) {
+ return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+ } else {
+ return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+ }
+}
+
+/**
+ * \brief Configures the input sampling mode for a GPIO pin.
+ *
+ * Configures the input sampling mode for a GPIO input, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode New pin sampling mode to configure
+ */
+static inline void system_pinmux_pin_set_input_sample_mode(
+ const uint8_t gpio_pin,
+ const enum system_pinmux_pin_sample mode)
+{
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_index = (gpio_pin % 32);
+
+ if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+ port->CTRL.reg |= (1 << pin_index);
+ } else {
+ port->CTRL.reg &= ~(1 << pin_index);
+ }
+}
+
+/** @} */
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Port pin drive output strength enum.
+ *
+ * Enum for the possible output drive strengths for the port pin
+ * configuration structure, to indicate the driver strength the pin should
+ * use.
+ */
+enum system_pinmux_pin_strength {
+ /** Normal output driver strength. */
+ SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,
+ /** High current output driver strength. */
+ SYSTEM_PINMUX_PIN_STRENGTH_HIGH,
+};
+
+/**
+ * \brief Configures the output driver strength mode for a GPIO pin.
+ *
+ * Configures the output drive strength for a GPIO output, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode New output driver strength mode to configure
+ */
+static inline void system_pinmux_pin_set_output_strength(
+ const uint8_t gpio_pin,
+ const enum system_pinmux_pin_strength mode)
+{
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_index = (gpio_pin % 32);
+
+ if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+ port->PINCFG[pin_index].reg |= PORT_PINCFG_DRVSTR;
+ } else {
+ port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;
+ }
+}
+
+void system_pinmux_group_set_output_strength(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_strength mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Port pin output slew rate enum.
+ *
+ * Enum for the possible output drive slew rates for the port pin
+ * configuration structure, to indicate the driver slew rate the pin should
+ * use.
+ */
+enum system_pinmux_pin_slew_rate {
+ /** Normal pin output slew rate. */
+ SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,
+ /** Enable slew rate limiter on the pin. */
+ SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,
+};
+
+/**
+ * \brief Configures the output slew rate mode for a GPIO pin.
+ *
+ * Configures the output slew rate mode for a GPIO output, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode New pin slew rate mode to configure
+ */
+static inline void system_pinmux_pin_set_output_slew_rate(
+ const uint8_t gpio_pin,
+ const enum system_pinmux_pin_slew_rate mode)
+{
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_index = (gpio_pin % 32);
+
+ if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+ port->PINCFG[pin_index].reg |= PORT_PINCFG_SLEWLIM;
+ } else {
+ port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;
+ }
+}
+
+void system_pinmux_group_set_output_slew_rate(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_slew_rate mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Port pin output drive mode enum.
+ *
+ * Enum for the possible output drive modes for the port pin configuration
+ * structure, to indicate the output mode the pin should use.
+ */
+enum system_pinmux_pin_drive {
+ /** Use totem pole output drive mode. */
+ SYSTEM_PINMUX_PIN_DRIVE_TOTEM,
+ /** Use open drain output drive mode. */
+ SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,
+};
+
+/**
+ * \brief Configures the output driver mode for a GPIO pin.
+ *
+ * Configures the output driver mode for a GPIO output, to
+ * control the pad behavior.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode New pad output driver mode to configure
+ */
+static inline void system_pinmux_pin_set_output_drive(
+ const uint8_t gpio_pin,
+ const enum system_pinmux_pin_drive mode)
+{
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_index = (gpio_pin % 32);
+
+ if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+ port->PINCFG[pin_index].reg |= PORT_PINCFG_ODRAIN;
+ } else {
+ port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;
+ }
+}
+
+void system_pinmux_group_set_output_drive(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_drive mode);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>GPIO</td>
+ * <td>General Purpose Input/Output</td>
+ * </tr>
+ * <tr>
+ * <td>MUX</td>
+ * <td>Multiplexer</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Add SAML21 support.</td>
+ * </tr>
+ * <tr>
+ * <td>Removed code of open drain, slew limit and drive strength
+ * features</td>
+ * </tr>
+ * <tr>
+ * <td>Fixed broken sampling mode function implementations, which wrote
+ * corrupt configuration values to the device registers</td>
+ * </tr>
+ * <tr>
+ * <td>Added missing NULL pointer asserts to the PORT driver functions</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that QSGs can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_system_pinmux_basic_use_case
+ *
+ * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>F</td>
+ * <td>11/2014</td>
+ * <td>Add support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>12/2014</td>
+ * <td>Add support for SAMR21 and SAMD10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>01/2014</td>
+ * <td>Add support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>09/2013</td>
+ * <td>Fixed incorrect documentation for the device pin sampling mode.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/quick_start/qs_pinmux_basic.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief SAM PINMUX Driver Quick Start + * + * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic + * + * In this use case, the PINMUX module is configured for: + * \li One pin in input mode, with pull-up enabled, connected to the GPIO + * module + * \li Sampling mode of the pin changed to sample on demand + * + * This use case sets up the PINMUX to configure a physical I/O pin set as + * an input with pull-up and changes the sampling mode of the pin to reduce + * power by only sampling the physical pin state when the user application + * attempts to read it. + * + * \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup + * + * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites + * There are no special setup requirements for this use-case. + * + * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code + * Copy-paste the following setup code to your application: + * \snippet qs_pinmux_basic.c setup + * + * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow + * -# Create a PINMUX module pin configuration struct, which can be filled out + * to adjust the configuration of a single port pin. + * \snippet qs_pinmux_basic.c pinmux_config + * -# Initialize the pin configuration struct with the module's default values. + * \snippet qs_pinmux_basic.c pinmux_config_defaults + * \note This should always be performed before using the configuration + * struct to ensure that all values are initialized to known default + * settings. + * + * -# Adjust the configuration struct to request an input pin with pullup + * connected to the GPIO peripheral. + * \snippet qs_pinmux_basic.c pinmux_update_config_values + * -# Configure GPIO10 with the initialized pin configuration struct, to enable + * the input sampler on the pin. + * \snippet qs_pinmux_basic.c pinmux_set_config + * + * \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case + * + * \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code + * Copy-paste the following code to your user application: + * \snippet qs_pinmux_basic.c main + * + * \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow + + * -# Adjust the configuration of the pin to enable on-demand sampling mode. + * \snippet qs_pinmux_basic.c pinmux_change_input_sampling + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/power/power_sam_d_r/power.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,224 @@
+/**
+ * \file
+ *
+ * \brief SAM Power related functionality
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef POWER_H_INCLUDED
+#define POWER_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Voltage references within the device.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+ /** Temperature sensor voltage reference. */
+ SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+ /** Bandgap voltage reference. */
+ SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
+};
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+ /** IDLE 0 sleep mode. */
+ SYSTEM_SLEEPMODE_IDLE_0,
+ /** IDLE 1 sleep mode. */
+ SYSTEM_SLEEPMODE_IDLE_1,
+ /** IDLE 2 sleep mode. */
+ SYSTEM_SLEEPMODE_IDLE_2,
+ /** Standby sleep mode. */
+ SYSTEM_SLEEPMODE_STANDBY,
+};
+
+
+
+/**
+ * \name Voltage References
+ * @{
+ */
+
+/**
+ * \brief Enable the selected voltage reference
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+ const enum system_voltage_reference vref)
+{
+ switch (vref) {
+ case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+ SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
+ break;
+
+ case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+ SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+ break;
+
+ default:
+ Assert(false);
+ return;
+ }
+}
+
+/**
+ * \brief Disable the selected voltage reference
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+ const enum system_voltage_reference vref)
+{
+ switch (vref) {
+ case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+ SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
+ break;
+
+ case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+ SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
+ break;
+
+ default:
+ Assert(false);
+ return;
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Device Sleep Control
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode Sleep mode to configure for the next sleep operation
+ *
+ * \retval STATUS_OK Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not
+ * available
+ */
+static inline enum status_code system_set_sleepmode(
+ const enum system_sleepmode sleep_mode)
+{
+#if (SAMD20 || SAMD21)
+ /* Errata: Make sure that the Flash does not power all the way down
+ * when in sleep mode. */
+ NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+#endif
+
+ switch (sleep_mode) {
+ case SYSTEM_SLEEPMODE_IDLE_0:
+ case SYSTEM_SLEEPMODE_IDLE_1:
+ case SYSTEM_SLEEPMODE_IDLE_2:
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ PM->SLEEP.reg = sleep_mode;
+ break;
+
+ case SYSTEM_SLEEPMODE_STANDBY:
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ break;
+
+ default:
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Put the system to sleep waiting for interrupt
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
+ * instruction to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode until woken by an interrupt.
+ */
+static inline void system_sleep(void)
+{
+ __DSB();
+ __WFI();
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* POWER_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/reset/reset_sam_d_r/reset.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,119 @@
+/**
+ * \file
+ *
+ * \brief SAM Reset related functionality
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef RESET_H_INCLUDED
+#define RESET_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+ /** The system was last reset by a software reset. */
+ SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST,
+ /** The system was last reset by the watchdog timer. */
+ SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT,
+ /** The system was last reset because the external reset line was pulled low. */
+ SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
+ /** The system was last reset by the BOD33. */
+ SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33,
+ /** The system was last reset by the BOD12. */
+ SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12,
+ /** The system was last reset by the POR (Power on reset). */
+ SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR,
+};
+
+
+/**
+ * \name Reset Control
+ * @{
+ */
+
+/**
+ * \brief Reset the MCU.
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC, all 32kHz sources,
+ * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
+ *
+ */
+static inline void system_reset(void)
+{
+ NVIC_SystemReset();
+}
+
+/**
+ * \brief Return the reset cause.
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+ return (enum system_reset_cause)PM->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RESET_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include <system.h>
+
+/**
+ * \internal
+ * Dummy initialization function, used as a weak alias target for the various
+ * init functions called by \ref system_init().
+ */
+void _system_dummy_init(void);
+void _system_dummy_init(void)
+{
+ return;
+}
+
+#if !defined(__DOXYGEN__)
+# if defined(__GNUC__)
+void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+# elif defined(__ICCARM__)
+void system_clock_init(void);
+void system_board_init(void);
+void _system_events_init(void);
+void _system_extint_init(void);
+# pragma weak system_clock_init=_system_dummy_init
+# pragma weak system_board_init=_system_dummy_init
+# pragma weak _system_events_init=_system_dummy_init
+# pragma weak _system_extint_init=_system_dummy_init
+# endif
+#endif
+
+/**
+ * \brief Initialize system.
+ *
+ * This function will call the various initialization functions within the
+ * system namespace. If a given optional system module is not available, the
+ * associated call will effectively be a NOP (No Operation).
+ *
+ * Currently the following initialization functions are supported:
+ * - System clock initialization (via the SYSTEM CLOCK sub-module)
+ * - Board hardware initialization (via the Board module)
+ * - Event system driver initialization (via the EVSYS module)
+ * - External Interrupt driver initialization (via the EXTINT module)
+ */
+void system_init(void)
+{
+ /* Configure GCLK and clock sources according to conf_clocks.h */
+ system_clock_init();
+
+ /* Initialize board hardware */
+ system_board_init();
+
+ /* Initialize EVSYS hardware */
+ _system_events_init();
+
+ /* Initialize External hardware */
+ _system_extint_init();
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,688 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef SYSTEM_H_INCLUDED
+#define SYSTEM_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <power.h>
+#include <reset.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_group SAM System Driver (SYSTEM)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the device's system relation functionality, necessary for
+ * the basic device operation. This is not limited to a single peripheral, but
+ * extends across multiple hardware peripherals.
+ *
+ * The following peripherals are used by this module:
+ * \if DEVICE_SAML21_SUPPORT
+ * - PM (Power Manager)
+ * - RSTC(Reset Controller)
+ * - SUPC(Supply Controller)
+ * \else
+ * - SYSCTRL (System Control)
+ * - PM (Power Manager)
+ * \endif
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SUPPORT
+ * - Atmel | SMART SAM L21
+ * \else
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_prerequisites
+ * - \ref asfdoc_sam0_system_module_overview
+ * - \ref asfdoc_sam0_system_special_considerations
+ * - \ref asfdoc_sam0_system_extra_info
+ * - \ref asfdoc_sam0_system_examples
+ * - \ref asfdoc_sam0_system_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_module_overview Module Overview
+ *
+ * The System driver provides a collection of interfaces between the user
+ * application logic, and the core device functionality (such as clocks, reset
+ * cause determination, etc.) that is required for all applications. It contains
+ * a number of sub-modules that control one specific aspect of the device:
+ *
+ * - System Core (this module)
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
+ * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
+ *
+ *
+ * \if DEVICE_SAML21_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE) and
+ * backup (VDDBU) domains. It sets the voltage regulators according to the sleep
+ * modes, the performance level, or the user configuration.
+ *
+ * In active mode, the voltage regulator can be chosen on the fly between a LDO
+ * or a Buck converter.In standby mode, the low power voltage regulator is used
+ * to supply VDDCORE.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch
+ * The SAM device supports connection of a battery backup to the VBAT power pin.
+ * It includes functionality that enables automatic power switching between main
+ * power and battery backup power. This will ensure power to the backup domain,
+ * when the main battery or power source is unavailable.
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_vref Voltage References
+ * The various analog modules within the SAM devices (such as AC, ADC, and
+ * DAC) require a voltage reference to be configured to act as a reference point
+ * for comparisons and conversions.
+ *
+ * The SAM devices contain multiple references, including an internal
+ * temperature sensor, and a fixed band-gap voltage source. When enabled, the
+ * associated voltage reference can be selected within the desired peripheral
+ * where applicable.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
+ * In some applications there may be a need to execute a different program
+ * flow based on how the device was reset. For example, if the cause of reset
+ * was the Watchdog timer (WDT), this might indicate an error in the application
+ * and a form of error handling or error logging might be needed.
+ *
+ * For this reason, an API is provided to retrieve the cause of the last system
+ * reset, so that appropriate action can be taken.
+ *
+ * \if DEVICE_SAML21_SUPPORT
+ * There are three groups of reset sources:
+ * - Power supply reset: Resets caused by an electrical issue. It covers POR and BODs reset.
+ * - User reset: Resets caused by the application. It covers external reset,
+ * system resetrequest and watchdog reset.
+ * - Backup reset: Resets caused by a backup mode exit condition.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level
+ * Performance level allows use to adjust the regulator output voltage to reduce
+ * power consumption. The user can select on the fly the performance level
+ * configuration which best suits its application.
+ *
+ * The SAM device embeds up to three performance level (PL0, PL1 and PL2).
+ * Each performance level defines a maximum frequency and a corresponding
+ * consumption in 渭A/MHz,when the application selects a new performance level,
+ * the voltage applied on the full logic area moves from a value to another,
+ * it can reduce the active consumption while decreasing the maximum frequency
+ * of the device.
+ *
+ * Performance level transition is possible only when the device is in active
+ * mode, after a reset, the device starts in the lowest performance level
+ * (lowest power consumption and lowest max. frequency). The application can then
+ * switch to another performance level at anytime without any stop in the code
+ * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure.
+ *
+ * \note When scaling down the performance level,the bus frequency should be first
+ * scaled down in order to not exceed the maximum frequency allowed for the
+ * low performance level.
+ * When scaling up the performance level (for example from PL0 to PL2), the bus
+ * frequency can be increased only once the performance level transition is
+ * completed,check the performance level status.
+ *
+ * \anchor asfdoc_sam0_system_performance_level_transition_figure
+ * \image html performance_level_transition.gif "The performance level transition"
+ *
+ * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating
+ * Power domain gating can turn on or off power domain voltage to save power
+ * while keeping other domain powered up. It can be used in standby sleep mode,
+ * in standby mode, when power-gated, the internal state of the logic can be
+ * retained allowing the application context to be kept.
+ *
+ * Power domain can be in three states:
+ * - Active state: the power domain is powered on.
+ * - Retention state: the main voltage supply for the power domain is switched off,
+ * while maintaining a secondary low-power supply for the sequential cells. The
+ * logic context is restored when waking up.
+ * - Off state: the power domain is entirely powered off. The logic context is lost.
+ *
+ * The SAM L21 device has three power domains: PD0, PD1 and PD2.
+ * - By default, a power domain is set automatically to retention state in standby
+ * sleep mode if no activity is required in it, the application can force all power
+ * domains to remain in active state during standby sleep mode in order to accelerate
+ * wakeup time.
+ * - Static Power_SleepWalking: When entering standby mode, if a peripheral needs to
+ * remain in run mode to perform sleepwalking task, its power domain (PDn) remains in
+ * active state as well as the inferior power domains (<PDn).
+ * - Dynamic Power_SleepWalking: During standby mode, a power domain (PDn) in active
+ * state (using the static Power_SleepWalking principle), can wakeup a superior power
+ * domain (>PDn) in order to perform a sleepwalking task. The superior power domain is
+ * then automatically set to active state. At the end of the sleepwalking task, either
+ * the device can be waken-up or the superior power domain can be set again to retention
+ * state.
+ *
+ * Power domains can be linked each other,it allows a power domain (PDn) to be kept
+ * in active state if the inferior power domain (PDn-1) is in active state too.
+ *
+ * The table \ref asfdoc_sam0_system_power_domain_overview_table illustrates the
+ * four cases to consider in standby mode
+ *
+ * \anchor asfdoc_sam0_system_power_domain_overview_table
+ * <table>
+ * <caption>Sleep Mode versus Power Domain State Overview</caption>
+ * <tr>
+ * <th>Sleep mode</th>
+ * <th></th>
+ * <th>PD0</th>
+ * <th>PD1</th>
+ * <th>PD2</th>
+ * <th>PDTOP</th>
+ * <th>PDBACKUP</th>
+ * </tr>
+ * <tr>
+ * <td>IDLE</td>
+ * <td></td>
+ * <td>active</td>
+ * <td>active</td>
+ * <td>active</td>
+ * <td>active</td>
+ * <td>active</td>
+ * </tr>
+ * <tr>
+ * <td>Standby</td>
+ * <td>Case 1</td>
+ * <td>active</td>
+ * <td>active</td>
+ * <td>active</td>
+ * <td>active</td>
+ * <td>active</td>
+ * </tr>
+ * <tr>
+ * <td>Standby</td>
+ * <td>Case 2</td>
+ * <td>active</td>
+ * <td>active</td>
+ * <td>retention</td>
+ * <td>active</td>
+ * <td>active</td>
+ * </tr>
+ * <tr>
+ * <td>Standby</td>
+ * <td>Case 3</td>
+ * <td>active</td>
+ * <td>retention</td>
+ * <td>retention</td>
+ * <td>active</td>
+ * <td>active</td>
+ * </tr>
+ * <tr>
+ * <td>Standby</td>
+ * <td>Case 4</td>
+ * <td>retention</td>
+ * <td>retention</td>
+ * <td>retention</td>
+ * <td>active</td>
+ * <td>active</td>
+ * </tr>
+ * <tr>
+ * <td>Backup</td>
+ * <td></td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>active</td>
+ * </tr>
+ * <tr>
+ * <td>Off</td>
+ * <td></td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode
+ * By default, in standby sleep mode, RAM is in low power mode (back biased)
+ * if its power domain is in retention state.
+ * The table \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode.
+ *
+ * \anchor asfdoc_sam0_system_power_ram_state_table
+ * <table>
+ * <caption>RAM Back-biasing mode</caption>
+ * <tr>
+ * <th>RAM mode</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>Retention Back-biasing mode</td>
+ * <td>RAM is back-biased if its power domain is in retention mode</td>
+ * </tr>
+ * <tr>
+ * <td>Standby Back-biasing mode</td>
+ * <td>RAM is back-biased if the device is in standby mode</td>
+ * </tr>
+ * <tr>
+ * <td>Standby OFF mode</td>
+ * <td>RAM is OFF if the device is in standby mode</td>
+ * </tr>
+ * <tr>
+ * <td>Always OFF mode</td>
+ * <td>RAM is OFF if the device is in RET mode</td>
+ * </tr>
+ * </table>
+ *
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
+ * The SAM devices have several sleep modes, where the sleep mode controls
+ * which clock systems on the device will remain enabled or disabled when the
+ * device enters a low power sleep mode.
+ * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
+ * clock settings of the different sleep modes.
+ *
+ * \anchor asfdoc_sam0_system_module_sleep_mode_table
+ * <table>
+ * <caption>SAM Device Sleep Modes</caption>
+ * \if DEVICE_SAML21_SUPPORT
+ * <tr>
+ * <th>Sleep mode</th>
+ * <th>System clock</th>
+ * <th>CPU clock</th>
+ * <th>AHB/AHB clock</th>
+ * <th>GCLK clocks</th>
+ * <th>Oscillators (ONDEMAND = 0)</th>
+ * <th>Oscillators (ONDEMAND = 1)</th>
+ * <th>Regulator mode</th>
+ * <th>RAM mode</th>
+ * </tr>
+ * <tr>
+ * <td>IDLE</td>
+ * <td>Run</td>
+ * <td>Stop</td>
+ * <td>Run if requested</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run if requested</td>
+ * <td>Normal</td>
+ * <td>Normal</td>
+ * </tr>
+ * <tr>
+ * <td>Standby</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Run if requested</td>
+ * <td>Run if requested</td>
+ * <td>Run if requested or RUNSTDBY = 1</td>
+ * <td>Run if requested</td>
+ * <td>Low pwer</td>
+ * <td>Low pwer</td>
+ * </tr>
+ * <tr>
+ * <td>Backup</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Backup</td>
+ * <td>OFF</td>
+ * </tr>
+ * <tr>
+ * <td>Off</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * <td>OFF</td>
+ * </tr>
+ * \else
+ * <tr>
+ * <th>Sleep mode</th>
+ * <th>CPU clock</th>
+ * <th>AHB clock</th>
+ * <th>APB clocks</th>
+ * <th>Clock sources</th>
+ * <th>System clock</th>
+ * <th>32KHz</th>
+ * <th>Reg mode</th>
+ * <th>RAM mode</th>
+ * </tr>
+ * <tr>
+ * <td>IDLE 0</td>
+ * <td>Stop</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Normal</td>
+ * <td>Normal</td>
+ * </tr>
+ * <tr>
+ * <td>IDLE 1</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Normal</td>
+ * <td>Normal</td>
+ * </tr>
+ * <tr>
+ * <td>IDLE 2</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Normal</td>
+ * <td>Normal</td>
+ * </tr>
+ * <tr>
+ * <td>STANDBY</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Low Power</td>
+ * <td>Source/Drain biasing</td>
+ * </tr>
+ * \endif
+ * </table>
+ *
+ * To enter device sleep, one of the available sleep modes must be set, and the
+ * function to enter sleep called. The device will automatically wake up in
+ * response to an interrupt being generated or other device event.
+ *
+ * Some peripheral clocks will remain enabled during sleep, depending on their
+ * configuration; if desired, modules can remain clocked during sleep to allow
+ * them to continue to operate while other parts of the system are powered down
+ * to save power.
+ *
+ *
+ * \section asfdoc_sam0_system_special_considerations Special Considerations
+ *
+ * Most of the functions in this driver have device specific restrictions and
+ * caveats; refer to your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_extra. This includes:
+ * - \ref asfdoc_sam0_system_extra_acronyms
+ * - \ref asfdoc_sam0_system_extra_dependencies
+ * - \ref asfdoc_sam0_system_extra_errata
+ * - \ref asfdoc_sam0_system_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_examples Examples
+ *
+ * For SYSTEM module related examples, refer to the sub-modules listed in
+ * the \ref asfdoc_sam0_system_module_overview "system module overview".
+ *
+ * \if DEVICE_SAML21_SUPPORT
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_power_exqsg.
+ * \endif
+ *
+ *
+ * \section asfdoc_sam0_system_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name System Debugger
+ * @{
+ */
+
+/**
+ * \brief Check if debugger is present.
+ *
+ * Check if debugger is connected to the onboard debug system (DAP).
+ *
+ * \return A bool identifying if a debugger is present.
+ *
+ * \retval true Debugger is connected to the system
+ * \retval false Debugger is not connected to the system
+ *
+ */
+static inline bool system_is_debugger_present(void)
+{
+ return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Identification
+ * @{
+ */
+
+/**
+ * \brief Retrieve the device identification signature.
+ *
+ * Retrieves the signature of the current device.
+ *
+ * \return Device ID signature as a 32-bit integer.
+ */
+static inline uint32_t system_get_device_id(void)
+{
+ return DSU->DID.reg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Initialization
+ * @{
+ */
+
+void system_init(void);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+
+* \page asfdoc_sam0_drivers_power_exqsg Examples for Power Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications. QSGs are simple examples with step-by-step instructions to
+ * configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_power_basic_use_case
+ *
+ * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
+ *
+ * \section asfdoc_sam0_system_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Definition</th>
+ * </tr>
+ * <tr>
+ * <td>PM</td>
+ * <td>Power Manager</td>
+ * </tr>
+ * \if DEVICE_SAML21_SUPPORT
+ * <tr>
+ * <td>SUPC</td>
+ * <td>Supply Controller</td>
+ * </tr>
+ * <tr>
+ * <td>RSTC</td>
+ * <td>Reset Controller</td>
+ * </tr>
+ * \else
+ * <tr>
+ * <td>SYSCTRL</td>
+ * <td>System control interface</td>
+ * </tr>
+ * \endif
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * \if DEVICE_SAML21_SUPPORT
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * \else
+ * <tr>
+ * <td>Added low power features and support for SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
+ * </tr>
+ * <tr>
+ * <td>Added new \c system_get_device_id() function to retrieved the device
+ * ID.</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * \endif
+ * </table>
+ *
+ * \page asfdoc_sam0_system_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * \if DEVICE_SAML21_SUPPORT
+ * <tr>
+ * <td>A</td>
+ * <td>12/2014</td>
+ * <td>Initial release.</td>
+ * </tr>
+ * \else
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * \endif
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_H_INCLUDED */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1715 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef TC_H_INCLUDED
+#define TC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_tc_group SAM Timer/Counter Driver (TC)
+ *
+ * This driver for Atmel庐 | SMART SAM devices provides an interface for the configuration
+ * and management of the timer modules within the device, for waveform
+ * generation and timing operations. The following driver API modes are covered
+ * by this manual:
+ *
+ * - Polled APIs
+ * \if TC_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ *
+ * The following peripherals are used by this module:
+ * - TC (Timer/Counter)
+ *
+ * The following devices can use this module:
+ * - Atmel | SMART SAM D20/D21
+ * - Atmel | SMART SAM R21
+ * - Atmel | SMART SAM D10/D11
+ * - Atmel | SMART SAM L21
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_tc_prerequisites
+ * - \ref asfdoc_sam0_tc_module_overview
+ * - \ref asfdoc_sam0_tc_special_considerations
+ * - \ref asfdoc_sam0_tc_extra_info
+ * - \ref asfdoc_sam0_tc_examples
+ * - \ref asfdoc_sam0_tc_api_overview
+ *
+ *
+ * \section asfdoc_sam0_tc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_tc_module_overview Module Overview
+ *
+ * The Timer/Counter (TC) module provides a set of timing and counting related
+ * functionality, such as the generation of periodic waveforms, the capturing
+ * of a periodic waveform's frequency/duty cycle, and software timekeeping for
+ * periodic operations. TC modules can be configured to use an 8-, 16-, or
+ * 32-bit counter size.
+ *
+ * This TC module for the SAM is capable of the following functions:
+ *
+ * - Generation of PWM signals
+ * - Generation of timestamps for events
+ * - General time counting
+ * - Waveform period capture
+ * - Waveform frequency capture
+ *
+ * \ref asfdoc_sam0_tc_block_diagram "The diagram below" shows the overview
+ * of the TC module design.
+ *
+ * \anchor asfdoc_sam0_tc_block_diagram
+ * \image html overview.svg "Basic Overview of the TC Module"
+ *
+ *
+ * \subsection asfdoc_sam0_tc_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_TC_DOUBLE_BUFFERED</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_TC_STAMP_PW_CAPTURE</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_TC_READ_SYNC</td>
+ * <td>SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_TC_IO_CAPTURE</td>
+ * <td>SAML21</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_func_desc Functional Description
+ * Independent of the configured counter size, each TC module can be set up
+ * in one of two different modes; capture and compare.
+ *
+ * In capture mode, the counter value is stored when a configurable event
+ * occurs. This mode can be used to generate timestamps used in event capture,
+ * or it can be used for the measurement of a periodic input signal's
+ * frequency/duty cycle.
+ *
+ * In compare mode, the counter value is compared against one or more of the
+ * configured channel compare values. When the counter value coincides with a
+ * compare value an action can be taken automatically by the module, such as
+ * generating an output event or toggling a pin when used for frequency or PWM
+ * signal generation.
+ *
+ * \note The connection of events between modules requires the use of the
+ * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ * to route output event of one module to the the input event of another.
+ * For more information on event routing, refer to the event driver
+ * documentation.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_tc_size Timer/Counter Size
+ * Each timer module can be configured in one of three different counter
+ * sizes; 8-, 16-, and 32-bit. The size of the counter determines the maximum
+ * value it can count to before an overflow occurs and the count is reset back
+ * to zero. \ref asfdoc_sam0_tc_count_size_vs_top "The table below" shows the
+ * maximum values for each of the possible counter sizes.
+ *
+ * \anchor asfdoc_sam0_tc_count_size_vs_top
+ * <table>
+ * <caption>Timer Counter Sizes and Their Maximum Count Values</caption>
+ * <tr>
+ * <th>Counter size</th>
+ * <th>Max. (hexadecimal)</th>
+ * <th>Max. (decimal)</th>
+ * </tr>
+ * <tr>
+ * <td>8-bit</td>
+ * <td>0xFF</td>
+ * <td>255</td>
+ * </tr>
+ * <tr>
+ * <td>16-bit</td>
+ * <td>0xFFFF</td>
+ * <td>65,535</td>
+ * </tr>
+ * <tr>
+ * <td>32-bit</td>
+ * <td>0xFFFFFFFF</td>
+ * <td>4,294,967,295</td>
+ * </tr>
+ * </table>
+ *
+ * When using the counter in 16- or 32-bit count mode, Compare Capture
+ * register 0 (CC0) is used to store the period value when running in PWM
+ * generation match mode.
+ *
+ * When using 32-bit counter size, two 16-bit counters are chained together
+ * in a cascade formation. Except in SAM D10/D11, Even numbered TC modules
+ * (e.g. TC0, TC2) can be configured as 32-bit counters. The odd numbered
+ * counters will act as slaves to the even numbered masters, and will not
+ * be reconfigurable until the master timer is disabled. The pairing of timer
+ * modules for 32-bit mode is shown in \ref asfdoc_sam0_tc_module_ms_pairs
+ * "the table below".
+ *
+ * \anchor asfdoc_sam0_tc_module_ms_pairs
+ * <table>
+ * <caption>TC Master and Slave Module Pairings</caption>
+ * <tr>
+ * <th>Master TC Module</th>
+ * <th>Slave TC Module</th>
+ * </tr>
+ * <tr>
+ * <td>TC0</td>
+ * <td>TC1</td>
+ * </tr>
+ * <tr>
+ * <td>TC2</td>
+ * <td>TC3</td>
+ * </tr>
+ * <tr>
+ * <td>...</td>
+ * <td>...</td>
+ * </tr>
+ * <tr>
+ * <td>TCn-1</td>
+ * <td>TCn</td>
+ * </tr>
+ * </table>
+ *
+ * In SAMD10/D11, odd numbered TC modules (e.g. TC1) can be configured as 32-bit
+ * counters. The even numbered(e.g. TC2) counters will act as slaves to the odd
+ * numbered masters.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_clock Clock Settings
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_clock_selection Clock Selection
+ * Each TC peripheral is clocked asynchronously to the system clock by a GCLK
+ * (Generic Clock) channel. The GCLK channel connects to any of the GCLK
+ * generators. The GCLK generators are configured to use one of the available
+ * clock sources on the system such as internal oscillator, external crystals,
+ * etc. see the \ref asfdoc_sam0_system_clock_group "Generic Clock driver"
+ *for
+ * more information.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_clock_prescaler Prescaler
+ * Each TC module in the SAM has its own individual clock prescaler, which
+ * can be used to divide the input clock frequency used in the counter. This
+ * prescaler only scales the clock used to provide clock pulses for the counter
+ * to count, and does not affect the digital register interface portion of
+ * the module, thus the timer registers will synchronize to the raw GCLK
+ * frequency input to the module.
+ *
+ * As a result of this, when selecting a GCLK frequency and timer prescaler
+ * value the user application should consider both the timer resolution
+ * required and the synchronization frequency, to avoid lengthy
+ * synchronization times of the module if a very slow GCLK frequency is fed
+ * into the TC module. It is preferable to use a higher module GCLK frequency
+ * as the input to the timer, and prescale this down as much as possible to
+ * obtain a suitable counter frequency in latency-sensitive applications.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_clock_reloading Reloading
+ * Timer modules also contain a configurable reload action, used when a
+ * re-trigger event occurs. Examples of a re-trigger event are the counter
+ * reaching the maximum value when counting up, or when an event from the event
+ * system tells the counter to re-trigger. The reload action determines if the
+ * prescaler should be reset, and when this should happen. The counter will
+ * always be reloaded with the value it is set to start counting from. The user
+ * can choose between three different reload actions, described in
+ * \ref asfdoc_sam0_tc_module_reload_act "the table below".
+ *
+ * \anchor asfdoc_sam0_tc_module_reload_act
+ * <table>
+ * <caption>TC Module Reload Actions</caption>
+ * <tr>
+ * <th>Reload action</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>\ref TC_RELOAD_ACTION_GCLK </td>
+ * <td>Reload TC counter value on next GCLK cycle. Leave prescaler
+ * as-is.</td>
+ * </tr>
+ * <tr>
+ * <td>\ref TC_RELOAD_ACTION_PRESC </td>
+ * <td>Reloads TC counter value on next prescaler clock. Leave prescaler
+ * as-is.</td>
+ * </tr>
+ * <tr>
+ * <td> \ref TC_RELOAD_ACTION_RESYNC </td>
+ * <td>Reload TC counter value on next GCLK cycle. Clear prescaler to
+ * zero.</td>
+ * </tr>
+ * </table>
+ *
+ * The reload action to use will depend on the specific application being
+ * implemented. One example is when an external trigger for a reload occurs; if
+ * the TC uses the prescaler, the counter in the prescaler should not have a
+ * value between zero and the division factor. The TC counter and the counter
+ * in the prescaler should both start at zero. When the counter is set to
+ * re-trigger when it reaches the maximum value on the other hand, this is not the
+ * right option to use. In such a case it would be better if the prescaler is
+ * left unaltered when the re-trigger happens, letting the counter reset on the
+ * next GCLK cycle.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_compare_match Compare Match Operations
+ * In compare match operation, Compare/Capture registers are used in comparison
+ * with the counter value. When the timer's count value matches the value of a
+ * compare channel, a user defined action can be taken.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_timer Basic Timer
+ *
+ * A Basic Timer is a simple application where compare match operations is used
+ * to determine when a specific period has elapsed. In Basic Timer operations,
+ * one or more values in the module's Compare/Capture registers are used to
+ * specify the time (as a number of prescaled GCLK cycles) when an action should
+ * be taken by the microcontroller. This can be an Interrupt Service Routine
+ * (ISR), event generator via the event system, or a software flag that is
+ * polled via the user application.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg Waveform Generation
+ *
+ * Waveform generation enables the TC module to generate square waves, or if
+ * combined with an external passive low-pass filter; analog waveforms.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_pwm Waveform Generation - PWM
+ *
+ * Pulse width modulation is a form of waveform generation and a signalling
+ * technique that can be useful in many situations. When PWM mode is used,
+ * a digital pulse train with a configurable frequency and duty cycle can be
+ * generated by the TC module and output to a GPIO pin of the device.
+ *
+ * Often PWM is used to communicate a control or information parameter to an
+ * external circuit or component. Differing impedances of the source generator
+ * and sink receiver circuits is less of an issue when using PWM compared to
+ * using an analog voltage value, as noise will not generally affect the
+ * signal's integrity to a meaningful extent.
+ *
+ * \ref asfdoc_sam0_tc_module_pwm_normal_diag "The figure below" illustrates
+ * operations and different states of the counter and its output when running
+ * the counter in PWM normal mode. As can be seen, the TOP value is unchanged
+ * and is set to MAX. The compare match value is changed at several points to
+ * illustrate the resulting waveform output changes. The PWM output is set to
+ * normal (i.e. non-inverted) output mode.
+ *
+ * \anchor asfdoc_sam0_tc_module_pwm_normal_diag
+ * \image html pwm_normal_ex.svg "Example of PWM in Normal Mode, and Different Counter Operations"
+ *
+ *
+ * In \ref asfdoc_sam0_tc_module_pwm_match_diag "the figure below", the
+ * counter is set to generate PWM in Match mode. The PWM output is inverted via
+ * the appropriate configuration option in the TC driver configuration
+ * structure. In this example, the counter value is changed once, but the
+ * compare match value is kept unchanged. As can be seen, it is possible to
+ * change the TOP value when running in PWM match mode.
+ *
+ * \anchor asfdoc_sam0_tc_module_pwm_match_diag
+ * \image html pwm_match_ex.svg "Example of PWM in Match Mode, and Different Counter Operations"
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_freq Waveform Generation - Frequency
+ *
+ * Frequency Generation mode is in many ways identical to PWM
+ * generation. However, in Frequency Generation a toggle only occurs
+ * on the output when a match on a capture channels occurs. When the
+ * match is made, the timer value is reset, resulting in a variable
+ * frequency square wave with a fixed 50% duty cycle.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt Capture Operations
+ *
+ * In capture operations, any event from the event system or a pin change can
+ * trigger a capture of the counter value. This captured counter value can be
+ * used as a timestamp for the event, or it can be used in frequency and pulse
+ * width capture.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_event_capture Capture Operations - Event
+ *
+ * Event capture is a simple use of the capture functionality,
+ * designed to create timestamps for specific events. When the TC
+ * module's input capture pin is externally toggled, the current timer
+ * count value is copied into a buffered register which can then be
+ * read out by the user application.
+ *
+ * Note that when performing any capture operation, there is a risk that the
+ * counter reaches its top value (MAX) when counting up, or the bottom value
+ * (zero) when counting down, before the capture event occurs. This can distort
+ * the result, making event timestamps to appear shorter than reality; the
+ * user application should check for timer overflow when reading a capture
+ * result in order to detect this situation and perform an appropriate
+ * adjustment.
+ *
+ * Before checking for a new capture, \ref TC_STATUS_COUNT_OVERFLOW
+ * should be checked. The response to an overflow error is left to the user
+ * application, however it may be necessary to clear both the capture overflow
+ * flag and the capture flag upon each capture reading.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_pwc Capture Operations - Pulse Width
+ *
+ * Pulse Width Capture mode makes it possible to measure the pulse width and
+ * period of PWM signals. This mode uses two capture channels of the counter.
+ * This means that the counter module used for Pulse Width Capture can not be
+ * used for any other purpose. There are two modes for pulse width capture;
+ * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture
+ * channel 0 is used for storing the pulse width and capture channel 1 stores
+ * the observed period. While in PPW mode, the roles of the two capture channels
+ * is reversed.
+ *
+ * As in the above example it is necessary to poll on interrupt flags to see
+ * if a new capture has happened and check that a capture overflow error has
+ * not occurred.
+ *
+ * \subsection asfdoc_sam0_tc_module_overview_oneshot One-shot Mode
+ *
+ * TC modules can be configured into a one-shot mode. When configured in this
+ * manner, starting the timer will cause it to count until the next overflow
+ * or underflow condition before automatically halting, waiting to be manually
+ * triggered by the user application software or an event signal from the event
+ * system.
+ *
+ * \subsubsection asfdoc_sam0_tc_module_overview_inversion Wave Generation Output Inversion
+ *
+ * The output of the wave generation can be inverted by hardware if desired,
+ * resulting in the logically inverted value being output to the configured
+ * device GPIO pin.
+ *
+ *
+ * \section asfdoc_sam0_tc_special_considerations Special Considerations
+ *
+ * The number of capture compare registers in each TC module is dependent on
+ * the specific SAM device being used, and in some cases the counter size.
+ *
+ * The maximum amount of capture compare registers available in any SAM
+ * device is two when running in 32-bit mode and four in 8- and 16-bit modes.
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_tc_extra. This includes:
+ * - \ref asfdoc_sam0_tc_extra_acronyms
+ * - \ref asfdoc_sam0_tc_extra_dependencies
+ * - \ref asfdoc_sam0_tc_extra_errata
+ * - \ref asfdoc_sam0_tc_extra_history
+ *
+ *
+ * \section asfdoc_sam0_tc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_tc_exqsg.
+ *
+ * \section asfdoc_sam0_tc_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+
+/**
+ * Define port features set according to different device family
+ * @{
+*/
+#if (SAML21) || defined(__DOXYGEN__)
+/** TC double buffered */
+# define FEATURE_TC_DOUBLE_BUFFERED
+/** SYNCBUSY scheme version 2 */
+# define FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2
+/** TC time stamp capture and pulse width capture */
+# define FEATURE_TC_STAMP_PW_CAPTURE
+/** Read synchronization of COUNT*/
+# define FEATURE_TC_READ_SYNC
+/** IO pin edge capture*/
+# define FEATURE_TC_IO_CAPTURE
+#endif
+/*@}*/
+
+#if !defined(__DOXYGEN__)
+#if SAMD20 || SAML21
+# define TC_INSTANCE_OFFSET 0
+#endif
+#if defined(SAMD21) || defined(SAMR21)
+//#if SAMD21 || SAMR21
+# define TC_INSTANCE_OFFSET 3
+#endif
+#if SAMD10 || SAMD11
+# define TC_INSTANCE_OFFSET 1
+#endif
+
+#if SAMD20
+# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC8_NUM
+#elif SAML21
+# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC_NUM
+#elif SAMD10 || SAMD11
+# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC1_CC8_NUM
+#else
+# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC3_CC8_NUM
+/* Same number for 8-, 16- and 32-bit TC and all TC instances */
+#endif
+
+/** TC Instance MAX ID Number. */
+#if SAMD20E || SAMD21G || SAMD21E || SAMR21
+#define TC_INST_MAX_ID 5
+#elif SAML21
+#define TC_INST_MAX_ID 4
+#elif SAMD10 || SAMD11
+#define TC_INST_MAX_ID 2
+#else
+#define TC_INST_MAX_ID 7
+#endif
+
+#endif
+
+//#if TC_ASYNC == true // TEMP: Commented by V
+# include <system_interrupt.h>
+//#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//#if TC_ASYNC == true // TEMP: Commented by V
+/** Enum for the possible callback types for the TC module. */
+enum tc_callback {
+ /** Callback for TC overflow. */
+ TC_CALLBACK_OVERFLOW,
+ /** Callback for capture overflow error. */
+ TC_CALLBACK_ERROR,
+ /** Callback for capture compare channel 0. */
+ TC_CALLBACK_CC_CHANNEL0,
+ /** Callback for capture compare channel 1. */
+ TC_CALLBACK_CC_CHANNEL1,
+# if !defined(__DOXYGEN__)
+ /** Number of available callbacks. */
+ TC_CALLBACK_N,
+# endif
+};
+//#endif
+
+/**
+ * \name Module Status Flags
+ *
+ * TC status flags, returned by \ref tc_get_status() and cleared by
+ * \ref tc_clear_status().
+ *
+ * @{
+ */
+
+/** Timer channel 0 has matched against its compare value, or has captured a
+ * new value.
+ */
+#define TC_STATUS_CHANNEL_0_MATCH (1UL << 0)
+
+/** Timer channel 1 has matched against its compare value, or has captured a
+ * new value.
+ */
+#define TC_STATUS_CHANNEL_1_MATCH (1UL << 1)
+
+/** Timer register synchronization has completed, and the synchronized count
+ * value may be read.
+ */
+#define TC_STATUS_SYNC_READY (1UL << 2)
+
+/** A new value was captured before the previous value was read, resulting in
+ * lost data.
+ */
+#define TC_STATUS_CAPTURE_OVERFLOW (1UL << 3)
+
+/** The timer count value has overflowed from its maximum value to its minimum
+ * when counting upward, or from its minimum value to its maximum when
+ * counting downward.
+ */
+#define TC_STATUS_COUNT_OVERFLOW (1UL << 4)
+
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+/** Channel 0 compare or capture buffer valid. */
+#define TC_STATUS_CHN0_BUFFER_VALID (1UL << 5)
+/** Channel 1 compare or capture buffer valid. */
+#define TC_STATUS_CHN1_BUFFER_VALID (1UL << 6)
+/** Period buffer valid. */
+#define TC_STATUS_PERIOD_BUFFER_VALID (1UL << 7)
+#endif
+/** @} */
+
+/**
+ * \brief Index of the compare capture channels.
+ *
+ * This enum is used to specify which capture/compare channel to do
+ * operations on.
+ */
+enum tc_compare_capture_channel {
+ /** Index of compare capture channel 0. */
+ TC_COMPARE_CAPTURE_CHANNEL_0,
+ /** Index of compare capture channel 1. */
+ TC_COMPARE_CAPTURE_CHANNEL_1,
+};
+
+/** TC wave generation mode. */
+#if SAML21
+#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_WAVE_WAVEGEN_NFRQ
+#define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_WAVE_WAVEGEN_MFRQ
+#define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_WAVE_WAVEGEN_NPWM
+#define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_WAVE_WAVEGEN_MPWM
+#else
+#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_CTRLA_WAVEGEN_NFRQ
+#define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_CTRLA_WAVEGEN_MFRQ
+#define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_CTRLA_WAVEGEN_NPWM
+#define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_CTRLA_WAVEGEN_MPWM
+#endif
+
+/**
+ * \brief TC wave generation mode enum.
+ *
+ * This enum is used to select which mode to run the wave
+ * generation in.
+ *
+ */
+enum tc_wave_generation {
+ /** Top is maximum, except in 8-bit counter size where it is the PER
+ * register.
+ */
+ TC_WAVE_GENERATION_NORMAL_FREQ = TC_WAVE_GENERATION_NORMAL_FREQ_MODE,
+
+ /** Top is CC0, except in 8-bit counter size where it is the PER
+ * register.
+ */
+ TC_WAVE_GENERATION_MATCH_FREQ = TC_WAVE_GENERATION_MATCH_FREQ_MODE,
+
+ /** Top is maximum, except in 8-bit counter size where it is the PER
+ * register.
+ */
+ TC_WAVE_GENERATION_NORMAL_PWM = TC_WAVE_GENERATION_NORMAL_PWM_MODE,
+
+ /** Top is CC0, except in 8-bit counter size where it is the PER
+ * register.
+ */
+ TC_WAVE_GENERATION_MATCH_PWM = TC_WAVE_GENERATION_MATCH_PWM_MODE,
+};
+
+/**
+ * \brief Specifies if the counter is 8-, 16-, or 32-bit.
+ *
+ * This enum specifies the maximum value it is possible to count to.
+ */
+enum tc_counter_size {
+ /** The counter's maximum value is 0xFF, the period register is
+ * available to be used as top value.
+ */
+ TC_COUNTER_SIZE_8BIT = TC_CTRLA_MODE_COUNT8,
+
+ /** The counter's maximum value is 0xFFFF. There is no separate
+ * period register, to modify top one of the capture compare
+ * registers has to be used. This limits the amount of
+ * available channels.
+ */
+ TC_COUNTER_SIZE_16BIT = TC_CTRLA_MODE_COUNT16,
+
+ /** The counter's maximum value is 0xFFFFFFFF. There is no separate
+ * period register, to modify top one of the capture compare
+ * registers has to be used. This limits the amount of
+ * available channels.
+ */
+ TC_COUNTER_SIZE_32BIT = TC_CTRLA_MODE_COUNT32,
+};
+
+/**
+ * \brief TC Counter reload action enum.
+ *
+ * This enum specify how the counter and prescaler should reload.
+ */
+enum tc_reload_action {
+ /** The counter is reloaded/reset on the next GCLK and starts
+ * counting on the prescaler clock.
+ */
+ TC_RELOAD_ACTION_GCLK = TC_CTRLA_PRESCSYNC_GCLK,
+
+ /** The counter is reloaded/reset on the next prescaler clock.
+ */
+ TC_RELOAD_ACTION_PRESC = TC_CTRLA_PRESCSYNC_PRESC,
+
+ /** The counter is reloaded/reset on the next GCLK, and the
+ * prescaler is restarted as well.
+ */
+ TC_RELOAD_ACTION_RESYNC = TC_CTRLA_PRESCSYNC_RESYNC,
+};
+
+/**
+ * \brief TC clock prescaler values.
+ *
+ * This enum is used to choose the clock prescaler
+ * configuration. The prescaler divides the clock frequency of the TC
+ * module to make the counter count slower.
+ */
+enum tc_clock_prescaler {
+ /** Divide clock by 1. */
+ TC_CLOCK_PRESCALER_DIV1 = TC_CTRLA_PRESCALER(0),
+ /** Divide clock by 2. */
+ TC_CLOCK_PRESCALER_DIV2 = TC_CTRLA_PRESCALER(1),
+ /** Divide clock by 4. */
+ TC_CLOCK_PRESCALER_DIV4 = TC_CTRLA_PRESCALER(2),
+ /** Divide clock by 8. */
+ TC_CLOCK_PRESCALER_DIV8 = TC_CTRLA_PRESCALER(3),
+ /** Divide clock by 16. */
+ TC_CLOCK_PRESCALER_DIV16 = TC_CTRLA_PRESCALER(4),
+ /** Divide clock by 64. */
+ TC_CLOCK_PRESCALER_DIV64 = TC_CTRLA_PRESCALER(5),
+ /** Divide clock by 256. */
+ TC_CLOCK_PRESCALER_DIV256 = TC_CTRLA_PRESCALER(6),
+ /** Divide clock by 1024. */
+ TC_CLOCK_PRESCALER_DIV1024 = TC_CTRLA_PRESCALER(7),
+};
+
+/**
+ * \brief TC module count direction.
+ *
+ * Timer/Counter count direction.
+ */
+enum tc_count_direction {
+ /** Timer should count upward from zero to MAX. */
+ TC_COUNT_DIRECTION_UP,
+
+ /** Timer should count downward to zero from MAX. */
+ TC_COUNT_DIRECTION_DOWN,
+};
+
+/** Waveform inversion mode. */
+#if SAML21
+#define TC_WAVEFORM_INVERT_CC0_MODE TC_DRVCTRL_INVEN(1)
+#define TC_WAVEFORM_INVERT_CC1_MODE TC_DRVCTRL_INVEN(2)
+#else
+#define TC_WAVEFORM_INVERT_CC0_MODE TC_CTRLC_INVEN(1)
+#define TC_WAVEFORM_INVERT_CC1_MODE TC_CTRLC_INVEN(2)
+#endif
+
+/**
+ * \brief Waveform inversion mode.
+ *
+ * Output waveform inversion mode.
+ */
+enum tc_waveform_invert_output {
+ /** No inversion of the waveform output. */
+ TC_WAVEFORM_INVERT_OUTPUT_NONE = 0,
+ /** Invert output from compare channel 0. */
+ TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE,
+ /** Invert output from compare channel 1. */
+ TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE,
+};
+
+/**
+ * \brief Action to perform when the TC module is triggered by an event.
+ *
+ * Event action to perform when the module is triggered by an event.
+ */
+enum tc_event_action {
+ /** No event action. */
+ TC_EVENT_ACTION_OFF = TC_EVCTRL_EVACT_OFF,
+ /** Re-trigger on event. */
+ TC_EVENT_ACTION_RETRIGGER = TC_EVCTRL_EVACT_RETRIGGER,
+ /** Increment counter on event. */
+ TC_EVENT_ACTION_INCREMENT_COUNTER = TC_EVCTRL_EVACT_COUNT,
+ /** Start counter on event. */
+ TC_EVENT_ACTION_START = TC_EVCTRL_EVACT_START,
+
+ /** Store period in capture register 0, pulse width in capture
+ * register 1.
+ */
+ TC_EVENT_ACTION_PPW = TC_EVCTRL_EVACT_PPW,
+
+ /** Store pulse width in capture register 0, period in capture
+ * register 1.
+ */
+ TC_EVENT_ACTION_PWP = TC_EVCTRL_EVACT_PWP,
+#ifdef FEATURE_TC_STAMP_PW_CAPTURE
+ /** Time stamp capture. */
+ TC_EVENT_ACTION_STAMP = TC_EVCTRL_EVACT_STAMP,
+ /** Pulse width capture. */
+ TC_EVENT_ACTION_PW = TC_EVCTRL_EVACT_PW,
+#endif
+};
+
+/**
+ * \brief TC event enable/disable structure.
+ *
+ * Event flags for the \ref tc_enable_events() and \ref tc_disable_events().
+ */
+struct tc_events {
+ /** Generate an output event on a compare channel match. */
+ bool generate_event_on_compare_channel
+ [NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+ /** Generate an output event on counter overflow. */
+ bool generate_event_on_overflow;
+ /** Perform the configured event action when an incoming event is signalled. */
+ bool on_event_perform_action;
+ /** Specifies if the input event source is inverted, when used in PWP or
+ * PPW event action modes.
+ */
+ bool invert_event_input;
+ /** Specifies which event to trigger if an event is triggered. */
+ enum tc_event_action event_action;
+};
+
+/**
+ * \brief Configuration struct for TC module in 8-bit size counter mode.
+ */
+struct tc_8bit_config {
+ /** Initial timer count value. */
+ uint8_t value;
+ /** Where to count to or from depending on the direction on the counter. */
+ uint8_t period;
+ /** Value to be used for compare match on each channel. */
+ uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for TC module in 16-bit size counter mode.
+ */
+struct tc_16bit_config {
+ /** Initial timer count value. */
+ uint16_t value;
+ /** Value to be used for compare match on each channel. */
+ uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for TC module in 32-bit size counter mode.
+ */
+struct tc_32bit_config {
+ /** Initial timer count value. */
+ uint32_t value;
+ /** Value to be used for compare match on each channel. */
+ uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+};
+
+/**
+ * \brief Configuration struct for TC module in 32-bit size counter mode.
+ */
+struct tc_pwm_channel {
+ /** When \c true, PWM output for the given channel is enabled. */
+ bool enabled;
+ /** Specifies pin output for each channel. */
+ uint32_t pin_out;
+ /** Specifies MUX setting for each output channel pin. */
+ uint32_t pin_mux;
+};
+
+/**
+ * \brief TC configuration structure.
+ *
+ * Configuration struct for a TC instance. This structure should be
+ * initialized by the \ref tc_get_config_defaults function before being
+ * modified by the user application.
+ */
+struct tc_config {
+ /** GCLK generator used to clock the peripheral. */
+ enum gclk_generator clock_source;
+
+ /** When \c true the module is enabled during standby. */
+ bool run_in_standby;
+#if (SAML21)
+ /** Run on demand. */
+ bool on_demand;
+#endif
+ /** Specifies either 8-, 16-, or 32-bit counter size. */
+ enum tc_counter_size counter_size;
+ /** Specifies the prescaler value for GCLK_TC. */
+ enum tc_clock_prescaler clock_prescaler;
+ /** Specifies which waveform generation mode to use. */
+ enum tc_wave_generation wave_generation;
+
+ /** Specifies the reload or reset time of the counter and prescaler
+ * resynchronization on a re-trigger event for the TC.
+ */
+ enum tc_reload_action reload_action;
+
+ /** Specifies which channel(s) to invert the waveform on.
+ For SAML21, it's also used to invert IO input pin. */
+ uint8_t waveform_invert_output;
+
+ /** Specifies which channel(s) to enable channel capture
+ * operation on.
+ */
+ bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+#ifdef FEATURE_TC_IO_CAPTURE
+ /** Specifies which channel(s) to enable I/O capture
+ * operation on.
+ */
+ bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+#endif
+
+ /** When \c true, one-shot will stop the TC on next hardware or software
+ * re-trigger event or overflow/underflow.
+ */
+ bool oneshot;
+
+ /** Specifies the direction for the TC to count. */
+ enum tc_count_direction count_direction;
+
+ /** Specifies the PWM channel for TC. */
+ struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+
+ /** Access the different counter size settings though this configuration member. */
+ union {
+ /** Struct for 8-bit specific timer configuration. */
+ struct tc_8bit_config counter_8_bit;
+ /** Struct for 16-bit specific timer configuration. */
+ struct tc_16bit_config counter_16_bit;
+ /** Struct for 32-bit specific timer configuration. */
+ struct tc_32bit_config counter_32_bit;
+ };
+
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+ /** Set to \c true to enable double buffering write. When enabled any write
+ * through \ref tc_set_top_value(), \ref tc_set_compare_value() and
+ * will direct to the buffer register as buffered
+ * value, and the buffered value will be committed to effective register
+ * on UPDATE condition, if update is not locked.
+ */
+ bool double_buffering_enabled;
+#endif
+};
+
+
+//#if TC_ASYNC == true // TEMP: Commented by V
+/* Forward Declaration for the device instance. */
+struct tc_module;
+
+/* Type of the callback functions. */
+typedef void (*tc_callback_t)(struct tc_module *const module);
+//#endif
+
+/**
+ * \brief TC software device instance structure.
+ *
+ * TC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ * application; they are reserved for module-internal use only.
+ */
+struct tc_module {
+#if !defined(__DOXYGEN__)
+ /** Hardware module pointer of the associated Timer/Counter peripheral. */
+ Tc *hw;
+
+ /** Size of the initialized Timer/Counter module configuration. */
+ enum tc_counter_size counter_size;
+//# if TC_ASYNC == true // TEMP: Commented by V
+ /** Array of callbacks. */
+ tc_callback_t callback[TC_CALLBACK_N];
+ /** Bit mask for callbacks registered. */
+ uint8_t register_callback_mask;
+ /** Bit mask for callbacks enabled. */
+ uint8_t enable_callback_mask;
+//# endif
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+ /** Set to \c true to enable double buffering write. */
+ bool double_buffering_enabled;
+#endif
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+uint8_t _tc_get_inst_index(
+ Tc *const hw);
+#endif
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to
+ *the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false If the module has completed synchronization
+ * \retval true If the module synchronization is ongoing
+ */
+static inline bool tc_is_syncing(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+#if (SAML21)
+ return (tc_module->SYNCBUSY.reg);
+#else
+ return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY);
+#endif
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given TC configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structures before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ * \li GCLK generator 0 (GCLK main) clock source
+ * \li 16-bit counter size on the counter
+ * \li No prescaler
+ * \li Normal frequency wave generation
+ * \li GCLK reload action
+ * \li Don't run in standby
+ * \li Don't run on demand for SAML21
+ * \li No inversion of waveform output
+ * \li No capture enabled
+ * \li No I/O capture enabled for SAML21
+ * \li No event input enabled
+ * \li Count upward
+ * \li Don't perform one-shot operations
+ * \li No event action
+ * \li No channel 0 PWM output
+ * \li No channel 1 PWM output
+ * \li Counter starts on 0
+ * \li Capture compare channel 0 set to 0
+ * \li Capture compare channel 1 set to 0
+ * \li No PWM pin output enabled
+ * \li Pin and MUX configuration not set
+ * \li Double buffer disabled (if have this feature)
+ *
+ * \param[out] config Pointer to a TC module configuration structure to set
+ */
+static inline void tc_get_config_defaults(
+ struct tc_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Write default config to config struct */
+ config->clock_source = GCLK_GENERATOR_0;
+ config->counter_size = TC_COUNTER_SIZE_16BIT;
+ config->clock_prescaler = TC_CLOCK_PRESCALER_DIV1;
+ config->wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ;
+ config->reload_action = TC_RELOAD_ACTION_GCLK;
+ config->run_in_standby = false;
+#if (SAML21)
+ config->on_demand = false;
+#endif
+ config->waveform_invert_output = TC_WAVEFORM_INVERT_OUTPUT_NONE;
+ config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
+ config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
+#ifdef FEATURE_TC_IO_CAPTURE
+ config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
+ config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
+#endif
+
+ config->count_direction = TC_COUNT_DIRECTION_UP;
+ config->oneshot = false;
+
+ config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false;
+ config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0;
+ config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0;
+
+ config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false;
+ config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0;
+ config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0;
+
+ config->counter_16_bit.value = 0x0000;
+ config->counter_16_bit.compare_capture_channel\
+ [TC_COMPARE_CAPTURE_CHANNEL_0] = 0x0000;
+ config->counter_16_bit.compare_capture_channel\
+ [TC_COMPARE_CAPTURE_CHANNEL_1] = 0x0000;
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+ config->double_buffering_enabled = false;
+#endif
+
+}
+
+enum status_code tc_init(
+ struct tc_module *const module_inst,
+ Tc *const hw,
+ const struct tc_config *const config);
+
+/** @} */
+
+/**
+ * \name Event Management
+ * @{
+ */
+
+/**
+ * \brief Enables a TC module event input or output.
+ *
+ * Enables one or more input or output events to or from the TC module.
+ * See \ref tc_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ * \param[in] events Struct containing flags of events to enable
+ */
+static inline void tc_enable_events(
+ struct tc_module *const module_inst,
+ struct tc_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(events);
+
+ Tc *const tc_module = module_inst->hw;
+
+ uint32_t event_mask = 0;
+
+ if (events->invert_event_input == true) {
+ event_mask |= TC_EVCTRL_TCINV;
+ }
+
+ if (events->on_event_perform_action == true) {
+ event_mask |= TC_EVCTRL_TCEI;
+ }
+
+ if (events->generate_event_on_overflow == true) {
+ event_mask |= TC_EVCTRL_OVFEO;
+ }
+
+ for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+ if (events->generate_event_on_compare_channel[i] == true) {
+ event_mask |= (TC_EVCTRL_MCEO(1) << i);
+ }
+ }
+
+ tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action;
+}
+
+/**
+ * \brief Disables a TC module event input or output.
+ *
+ * Disables one or more input or output events to or from the TC module.
+ * See \ref tc_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ * \param[in] events Struct containing flags of events to disable
+ */
+static inline void tc_disable_events(
+ struct tc_module *const module_inst,
+ struct tc_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(events);
+
+ Tc *const tc_module = module_inst->hw;
+
+ uint32_t event_mask = 0;
+
+ if (events->invert_event_input == true) {
+ event_mask |= TC_EVCTRL_TCINV;
+ }
+
+ if (events->on_event_perform_action == true) {
+ event_mask |= TC_EVCTRL_TCEI;
+ }
+
+ if (events->generate_event_on_overflow == true) {
+ event_mask |= TC_EVCTRL_OVFEO;
+ }
+
+ for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+ if (events->generate_event_on_compare_channel[i] == true) {
+ event_mask |= (TC_EVCTRL_MCEO(1) << i);
+ }
+ }
+
+ tc_module->COUNT8.EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+/**
+ * \name Enable/Disable/Reset
+ * @{
+ */
+
+enum status_code tc_reset(
+ const struct tc_module *const module_inst);
+
+/**
+ * \brief Enable the TC module.
+ *
+ * Enables a TC module that has been previously initialized. The counter will
+ * start when the counter is enabled.
+ *
+ * \note When the counter is configured to re-trigger on an event, the counter
+ * will not start until the start function is used.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ */
+static inline void tc_enable(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Enable TC module */
+ tc_module->CTRLA.reg |= TC_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disables the TC module.
+ *
+ * Disables a TC module and stops the counter.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ */
+static inline void tc_disable(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Disable TC module */
+ tc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE;
+}
+
+/** @} */
+
+/**
+ * \name Get/Set Count Value
+ * @{
+ */
+
+uint32_t tc_get_count_value(
+ const struct tc_module *const module_inst);
+
+enum status_code tc_set_count_value(
+ const struct tc_module *const module_inst,
+ const uint32_t count);
+
+/** @} */
+
+/**
+ * \name Start/Stop Counter
+ * @{
+ */
+
+/**
+ * \brief Stops the counter.
+ *
+ * This function will stop the counter. When the counter is stopped
+ * the value in the count value is set to 0 if the counter was
+ * counting up, or maximum if the counter was counting
+ * down when stopped.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ */
+static inline void tc_stop_counter(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Write command to execute */
+ tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(2);
+}
+
+/**
+ * \brief Starts the counter.
+ *
+ * Starts or restarts an initialized TC module's counter.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ */
+static inline void tc_start_counter(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Make certain that there are no conflicting commands in the register */
+ tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Write command to execute */
+ tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(1);
+}
+
+/** @} */
+
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+/**
+ * \name Double Buffering
+ * @{
+ */
+
+/**
+ * \brief Update double buffer.
+ *
+ * Update double buffer.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ */
+static inline void tc_update_double_buffer(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Make certain that there are no conflicting commands in the register */
+ tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Write command to execute */
+ tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(3);
+}
+/** @} */
+#endif
+
+#ifdef FEATURE_TC_READ_SYNC
+/**
+ * \name Count Read Synchronization
+ * @{
+ */
+
+/**
+ * \brief Read synchronization of COUNT.
+ *
+ * Read synchronization of COUNT.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ */
+static inline void tc_sync_read_count(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Make certain that there are no conflicting commands in the register */
+ tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Write command to execute */
+ tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(4);
+}
+/** @} */
+#endif
+
+/**
+ * \name Get Capture Set Compare
+ * @{
+ */
+
+uint32_t tc_get_capture_value(
+ const struct tc_module *const module_inst,
+ const enum tc_compare_capture_channel channel_index);
+
+enum status_code tc_set_compare_value(
+ const struct tc_module *const module_inst,
+ const enum tc_compare_capture_channel channel_index,
+ const uint32_t compare_value);
+
+/** @} */
+
+/**
+ * \name Set Top Value
+ * @{
+ */
+
+enum status_code tc_set_top_value(
+ const struct tc_module *const module_inst,
+ const uint32_t top_value);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst Pointer to the TC software instance struct
+ *
+ * \return Bitmask of \c TC_STATUS_* flags.
+ *
+ * \retval TC_STATUS_CHANNEL_0_MATCH Timer channel 0 compare/capture match
+ * \retval TC_STATUS_CHANNEL_1_MATCH Timer channel 1 compare/capture match
+ * \retval TC_STATUS_SYNC_READY Timer read synchronization has completed
+ * \retval TC_STATUS_CAPTURE_OVERFLOW Timer capture data has overflowed
+ * \retval TC_STATUS_COUNT_OVERFLOW Timer count value has overflowed
+ * \retval TC_STATUS_CHN0_BUFFER_VALID Timer count channel 0 compare/capture buffer valid
+ * \retval TC_STATUS_CHN1_BUFFER_VALID Timer count channel 1 compare/capture buffer valid
+ * \retval TC_STATUS_PERIOD_BUFFER_VALID Timer count period buffer valid
+ */
+static inline uint32_t tc_get_status(
+ struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ uint32_t int_flags = tc_module->INTFLAG.reg;
+
+ uint32_t status_flags = 0;
+
+ /* Check for TC channel 0 match */
+ if (int_flags & TC_INTFLAG_MC(1)) {
+ status_flags |= TC_STATUS_CHANNEL_0_MATCH;
+ }
+
+ /* Check for TC channel 1 match */
+ if (int_flags & TC_INTFLAG_MC(2)) {
+ status_flags |= TC_STATUS_CHANNEL_1_MATCH;
+ }
+
+#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2)
+ /* Check for TC read synchronization ready */
+ if (int_flags & TC_INTFLAG_SYNCRDY) {
+ status_flags |= TC_STATUS_SYNC_READY;
+ }
+#endif
+
+ /* Check for TC capture overflow */
+ if (int_flags & TC_INTFLAG_ERR) {
+ status_flags |= TC_STATUS_CAPTURE_OVERFLOW;
+ }
+
+ /* Check for TC count overflow */
+ if (int_flags & TC_INTFLAG_OVF) {
+ status_flags |= TC_STATUS_COUNT_OVERFLOW;
+ }
+#ifdef FEATURE_TC_DOUBLE_BUFFERED
+ uint8_t double_buffer_valid_status = tc_module->STATUS.reg;
+
+ /* Check channel 0 compare or capture buffer valid */
+ if (double_buffer_valid_status & TC_STATUS_CCBUFV0) {
+ status_flags |= TC_STATUS_CHN0_BUFFER_VALID;
+ }
+ /* Check channel 0 compare or capture buffer valid */
+ if (double_buffer_valid_status & TC_STATUS_CCBUFV1) {
+ status_flags |= TC_STATUS_CHN1_BUFFER_VALID;
+ }
+ /* Check period buffer valid */
+ if (double_buffer_valid_status & TC_STATUS_PERBUFV) {
+ status_flags |= TC_STATUS_PERIOD_BUFFER_VALID;
+ }
+#endif
+
+ return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst Pointer to the TC software instance struct
+ * \param[in] status_flags Bitmask of \c TC_STATUS_* flags to clear
+ */
+static inline void tc_clear_status(
+ struct tc_module *const module_inst,
+ const uint32_t status_flags)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ uint32_t int_flags = 0;
+
+ /* Check for TC channel 0 match */
+ if (status_flags & TC_STATUS_CHANNEL_0_MATCH) {
+ int_flags |= TC_INTFLAG_MC(1);
+ }
+
+ /* Check for TC channel 1 match */
+ if (status_flags & TC_STATUS_CHANNEL_1_MATCH) {
+ int_flags |= TC_INTFLAG_MC(2);
+ }
+
+#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2)
+ /* Check for TC read synchronization ready */
+ if (status_flags & TC_STATUS_SYNC_READY) {
+ int_flags |= TC_INTFLAG_SYNCRDY;
+ }
+#endif
+
+ /* Check for TC capture overflow */
+ if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) {
+ int_flags |= TC_INTFLAG_ERR;
+ }
+
+ /* Check for TC count overflow */
+ if (status_flags & TC_STATUS_COUNT_OVERFLOW) {
+ int_flags |= TC_INTFLAG_OVF;
+ }
+
+ /* Clear interrupt flag */
+ tc_module->INTFLAG.reg = int_flags;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_tc_extra Extra Information for TC Driver
+ *
+ * \section asfdoc_sam0_tc_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>DMA</td>
+ * <td>Direct Memory Access</td>
+ * </tr>
+ * <tr>
+ * <td>TC</td>
+ * <td>Timer Counter</td>
+ * </tr>
+ * <tr>
+ * <td>PWM</td>
+ * <td>Pulse Width Modulation</td>
+ * </tr>
+ * <tr>
+ * <td>PWP</td>
+ * <td>Pulse Width Period</td>
+ * </tr>
+ * <tr>
+ * <td>PPW</td>
+ * <td>Period Pulse Width</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_tc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAML21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMR21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21 and do some modifications as below:
+ * \li Clean up in the configuration structure, the counter size
+ * setting specific registers is accessed through the counter_8_bit,
+ * counter_16_bit and counter_32_bit structures
+ * \li All event related settings moved into the tc_event structure </td>
+ * </tr>
+ * <tr>
+ * <td>Added automatic digital clock interface enable for the slave TC
+ * module when a timer is initialized in 32-bit mode</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_tc_exqsg Examples for TC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_tc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_tc_basic_use_case
+ * \if TC_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_tc_timer_use_case
+ * - \subpage asfdoc_sam0_tc_callback_use_case
+ * \endif
+ * - \subpage asfdoc_sam0_tc_dma_use_case
+ *
+ * \page asfdoc_sam0_tc_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>11/2014</td>
+ * <td>Added support for SAML21.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>12/2014</td>
+ * <td>Added timer use case.
+ * Added support for SAMR21 and SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif /* TC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,194 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Callback Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "tc_interrupt.h"
+
+void *_tc_instances[TC_INST_NUM];
+
+void _tc_interrupt_handler(uint8_t instance);
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref tc_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in] module Pointer to TC software instance struct
+ * \param[in] callback_func Pointer to callback function
+ * \param[in] callback_type Callback type given by an enum
+ */
+enum status_code tc_register_callback(
+ struct tc_module *const module,
+ tc_callback_t callback_func,
+ const enum tc_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(callback_func);
+
+ /* Register callback function */
+ module->callback[callback_type] = callback_func;
+
+ /* Set the bit corresponding to the callback_type */
+ if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+ module->register_callback_mask |= TC_INTFLAG_MC(1);
+ } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+ module->register_callback_mask |= TC_INTFLAG_MC(2);
+ } else {
+ module->register_callback_mask |= (1 << callback_type);
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function implemented by the user. The callback should be
+ * disabled before it is unregistered.
+ *
+ * \param[in] module Pointer to TC software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ */
+enum status_code tc_unregister_callback(
+ struct tc_module *const module,
+ const enum tc_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+
+ /* Unregister callback function */
+ module->callback[callback_type] = NULL;
+
+ /* Clear the bit corresponding to the callback_type */
+ if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+ module->register_callback_mask &= ~TC_INTFLAG_MC(1);
+ } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+ module->register_callback_mask &= ~TC_INTFLAG_MC(2);
+ } else {
+ module->register_callback_mask &= ~(1 << callback_type);
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \internal ISR handler for TC
+ *
+ * Auto-generate a set of interrupt handlers for each TC in the device.
+ */
+#define _TC_INTERRUPT_HANDLER(n, m) \
+ void TC##n##_Handler(void) \
+ { \
+ _tc_interrupt_handler(m); \
+ }
+
+#if (SAML21E) || (SAML21G)
+_TC_INTERRUPT_HANDLER(0,0)
+_TC_INTERRUPT_HANDLER(1,1)
+_TC_INTERRUPT_HANDLER(4,2)
+#else
+MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID)
+#endif
+
+
+/**
+ * \internal Interrupt Handler for TC module
+ *
+ * Handles interrupts as they occur, it will run the callback functions
+ * that are registered and enabled.
+ *
+ * \param[in] instance ID of the TC instance calling the interrupt
+ * handler.
+ */
+void _tc_interrupt_handler(
+ uint8_t instance)
+{
+ /* Temporary variable */
+ uint8_t interrupt_and_callback_status_mask;
+
+ /* Get device instance from the look-up table */
+ struct tc_module *module
+ = (struct tc_module *)_tc_instances[instance];
+
+ /* Read and mask interrupt flag register */
+ interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg &
+ module->register_callback_mask &
+ module->enable_callback_mask;
+
+ /* Check if an Overflow interrupt has occurred */
+ if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) {
+ /* Invoke registered and enabled callback function */
+ (module->callback[TC_CALLBACK_OVERFLOW])(module);
+ /* Clear interrupt flag */
+ module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
+ }
+
+ /* Check if an Error interrupt has occurred */
+ if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) {
+ /* Invoke registered and enabled callback function */
+ (module->callback[TC_CALLBACK_ERROR])(module);
+ /* Clear interrupt flag */
+ module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
+ }
+
+ /* Check if an Match/Capture Channel 0 interrupt has occurred */
+ if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) {
+ /* Invoke registered and enabled callback function */
+ (module->callback[TC_CALLBACK_CC_CHANNEL0])(module);
+ /* Clear interrupt flag */
+ module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1);
+ }
+
+ /* Check if an Match/Capture Channel 1 interrupt has occurred */
+ if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) {
+ /* Invoke registered and enabled callback function */
+ (module->callback[TC_CALLBACK_CC_CHANNEL1])(module);
+ /* Clear interrupt flag */
+ module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2);
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,174 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Callback Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef TC_INTERRUPT_H_INCLUDED
+#define TC_INTERRUPT_H_INCLUDED
+
+#include "tc.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+extern void *_tc_instances[TC_INST_NUM];
+
+# define _TC_INTERRUPT_VECT_NUM(n, unused) \
+ SYSTEM_INTERRUPT_MODULE_TC##n,
+/**
+ * \internal Get the interrupt vector for the given device instance
+ *
+ * \param[in] TC module instance number.
+ *
+ * \return Interrupt vector for of the given TC module instance.
+ */
+static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector(
+ uint32_t inst_num)
+{
+ static uint8_t tc_interrupt_vectors[TC_INST_NUM] = {
+#if (SAML21E) || (SAML21G)
+ SYSTEM_INTERRUPT_MODULE_TC0,
+ SYSTEM_INTERRUPT_MODULE_TC1,
+ SYSTEM_INTERRUPT_MODULE_TC4
+#else
+ MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID)
+#endif
+ };
+
+ return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num];
+}
+#endif /* !defined(__DOXYGEN__) */
+
+/**
+ * \name Callback Management
+ * {@
+ */
+
+enum status_code tc_register_callback(
+ struct tc_module *const module,
+ tc_callback_t callback_func,
+ const enum tc_callback callback_type);
+
+enum status_code tc_unregister_callback(
+ struct tc_module *const module,
+ const enum tc_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by the \ref
+ * tc_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are
+ * met. This function will also enable the appropriate interrupts.
+ *
+ * \param[in] module Pointer to TC software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ */
+static inline void tc_enable_callback(
+ struct tc_module *const module,
+ const enum tc_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+
+
+ /* Enable interrupts for this TC module */
+ system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw)));
+
+ /* Enable callback */
+ if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+ module->enable_callback_mask |= TC_INTFLAG_MC(1);
+ module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1);
+ } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+ module->enable_callback_mask |= TC_INTFLAG_MC(2);
+ module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2);
+ } else {
+ module->enable_callback_mask |= (1 << callback_type);
+ module->hw->COUNT8.INTENSET.reg = (1 << callback_type);
+ }
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * tc_register_callback, and the callback will not be called from the
+ * interrupt routine. The function will also disable the appropriate
+ * interrupts.
+ *
+ * \param[in] module Pointer to TC software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ */
+static inline void tc_disable_callback(
+ struct tc_module *const module,
+ const enum tc_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+
+ /* Disable callback */
+ if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+ module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1);
+ module->enable_callback_mask &= ~TC_INTFLAG_MC(1);
+ } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+ module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2);
+ module->enable_callback_mask &= ~TC_INTFLAG_MC(2);
+ } else {
+ module->hw->COUNT8.INTENCLR.reg = (1 << callback_type);
+ module->enable_callback_mask &= ~(1 << callback_type);
+ }
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TC_INTERRUPT_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_sam_d_r/tc.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "tc.h"
+
+//#if TC_ASYNC == true // TEMP: Commented by V
+# include "tc_interrupt.h"
+# include <system_interrupt.h>
+
+/** \internal
+ * Converts a given TC index to its interrupt vector index.
+ */
+# define _TC_INTERRUPT_VECT_NUM(n, unused) \
+ SYSTEM_INTERRUPT_MODULE_TC##n,
+//#endif
+
+#if !defined(__DOXYGEN__)
+# define _TC_GCLK_ID(n,unused) TPASTE3(TC,n,_GCLK_ID) ,
+# define _TC_PM_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TC,n) ,
+
+# define TC_INST_GCLK_ID { MRECURSION(TC_INST_NUM, _TC_GCLK_ID, TC_INST_MAX_ID) }
+# define TC_INST_PM_APBCMASK { MRECURSION(TC_INST_NUM, _TC_PM_APBCMASK, TC_INST_MAX_ID) }
+
+#endif
+
+/**
+ * \internal Find the index of given TC module instance.
+ *
+ * \param[in] TC module instance pointer.
+ *
+ * \return Index of the given TC module instance.
+ */
+uint8_t _tc_get_inst_index(
+ Tc *const hw)
+{
+ /* List of available TC modules. */
+ Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+
+ /* Find index for TC instance. */
+ for (uint32_t i = 0; i < TC_INST_NUM; i++) {
+ if (hw == tc_modules[i]) {
+ return i;
+ }
+ }
+
+ /* Invalid data given. */
+ Assert(false);
+ return 0;
+}
+
+
+/**
+ * \brief Initializes a hardware TC module instance.
+ *
+ * Enables the clock and initializes the TC module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst Pointer to the software module instance struct
+ * \param[in] hw Pointer to the TC hardware module
+ * \param[in] config Pointer to the TC configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK The module was initialized successfully
+ * \retval STATUS_BUSY Hardware module was busy when the
+ * initialization procedure was attempted
+ * \retval STATUS_INVALID_ARG An invalid configuration option or argument
+ * was supplied
+ * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the
+ * hardware module is configured in 32-bit
+ * slave mode
+ */
+enum status_code tc_init(
+ struct tc_module *const module_inst,
+ Tc *const hw,
+ const struct tc_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(hw);
+ Assert(module_inst);
+ Assert(config);
+
+ /* Temporary variable to hold all updates to the CTRLA
+ * register before they are written to it */
+ uint16_t ctrla_tmp = 0;
+ /* Temporary variable to hold all updates to the CTRLBSET
+ * register before they are written to it */
+ uint8_t ctrlbset_tmp = 0;
+ /* Temporary variable to hold all updates to the CTRLC
+ * register before they are written to it */
+ uint8_t ctrlc_tmp = 0;
+ /* Temporary variable to hold TC instance number */
+ uint8_t instance = _tc_get_inst_index(hw);
+
+ /* Array of GLCK ID for different TC instances */
+ uint8_t inst_gclk_id[] = TC_INST_GCLK_ID;
+ /* Array of PM APBC mask bit position for different TC instances */
+ uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK;
+
+ struct system_pinmux_config pin_config;
+ struct system_gclk_chan_config gclk_chan_config;
+
+//#if TC_ASYNC == true // TEMP: Commented by V
+ /* Initialize parameters */
+ for (uint8_t i = 0; i < TC_CALLBACK_N; i++) {
+ module_inst->callback[i] = NULL;
+ }
+ module_inst->register_callback_mask = 0x00;
+ module_inst->enable_callback_mask = 0x00;
+
+ /* Register this instance for callbacks*/
+ _tc_instances[instance] = module_inst;
+//#endif
+
+ /* Associate the given device instance with the hardware module */
+ module_inst->hw = hw;
+
+#if SAMD10 || SAMD11
+ /* Check if even numbered TC modules are being configured in 32-bit
+ * counter size. Only odd numbered counters are allowed to be
+ * configured in 32-bit counter size.
+ */
+ if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+ !((instance + TC_INSTANCE_OFFSET) & 0x01)) {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+#else
+ /* Check if odd numbered TC modules are being configured in 32-bit
+ * counter size. Only even numbered counters are allowed to be
+ * configured in 32-bit counter size.
+ */
+ if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+ ((instance + TC_INSTANCE_OFFSET) & 0x01)) {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+#endif
+
+ /* Make the counter size variable in the module_inst struct reflect
+ * the counter size in the module
+ */
+ module_inst->counter_size = config->counter_size;
+
+ if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {
+ /* We are in the middle of a reset. Abort. */
+ return STATUS_BUSY;
+ }
+
+ if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
+ /* Module is used as a slave */
+ return STATUS_ERR_DENIED;
+ }
+
+ if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) {
+ /* Module must be disabled before initialization. Abort. */
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Set up the TC PWM out pin for channel 0 */
+ if (config->pwm_channel[0].enabled) {
+ system_pinmux_get_config_defaults(&pin_config);
+ pin_config.mux_position = config->pwm_channel[0].pin_mux;
+ pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+ system_pinmux_pin_set_config(
+ config->pwm_channel[0].pin_out, &pin_config);
+ }
+
+ /* Set up the TC PWM out pin for channel 1 */
+ if (config->pwm_channel[1].enabled) {
+ system_pinmux_get_config_defaults(&pin_config);
+ pin_config.mux_position = config->pwm_channel[1].pin_mux;
+ pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+ system_pinmux_pin_set_config(
+ config->pwm_channel[1].pin_out, &pin_config);
+ }
+
+ /* Enable the user interface clock in the PM */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+ inst_pm_apbmask[instance]);
+
+ /* Enable the slave counter if counter_size is 32-bit */
+ if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) {
+ /* Enable the user interface clock in the PM */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+ inst_pm_apbmask[instance + 1]);
+ }
+
+ /* Setup clock for module */
+ system_gclk_chan_get_config_defaults(&gclk_chan_config);
+ gclk_chan_config.source_generator = config->clock_source;
+ system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
+ system_gclk_chan_enable(inst_gclk_id[instance]);
+
+ /* Set ctrla register */
+ ctrla_tmp =
+ (uint32_t)config->counter_size |
+ (uint32_t)config->wave_generation |
+ (uint32_t)config->reload_action |
+ (uint32_t)config->clock_prescaler;
+
+ if (config->run_in_standby) {
+ ctrla_tmp |= TC_CTRLA_RUNSTDBY;
+ }
+
+ /* Write configuration to register */
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+ hw->COUNT8.CTRLA.reg = ctrla_tmp;
+
+ /* Set ctrlb register */
+ if (config->oneshot) {
+ ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
+ }
+
+ if (config->count_direction) {
+ ctrlbset_tmp |= TC_CTRLBSET_DIR;
+ }
+
+ /* Clear old ctrlb configuration */
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+ hw->COUNT8.CTRLBCLR.reg = 0xFF;
+
+ /* Check if we actually need to go into a wait state. */
+ if (ctrlbset_tmp) {
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+ /* Write configuration to register */
+ hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
+ }
+
+ /* Set ctrlc register*/
+ ctrlc_tmp = config->waveform_invert_output;
+ for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+ if (config->enable_capture_on_channel[i] == true) {
+ ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i);
+ }
+ }
+
+ /* Write configuration to register */
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+ hw->COUNT8.CTRLC.reg = ctrlc_tmp;
+
+ /* Write configuration to register */
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Switch for TC counter size */
+ switch (module_inst->counter_size) {
+ case TC_COUNTER_SIZE_8BIT:
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT8.COUNT.reg =
+ config->counter_8_bit.value;
+
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT8.PER.reg =
+ config->counter_8_bit.period;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT8.CC[0].reg =
+ config->counter_8_bit.compare_capture_channel[0];
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT8.CC[1].reg =
+ config->counter_8_bit.compare_capture_channel[1];
+
+ return STATUS_OK;
+
+ case TC_COUNTER_SIZE_16BIT:
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT16.COUNT.reg
+ = config->counter_16_bit.value;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT16.CC[0].reg =
+ config->counter_16_bit.compare_capture_channel[0];
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT16.CC[1].reg =
+ config->counter_16_bit.compare_capture_channel[1];
+
+ return STATUS_OK;
+
+ case TC_COUNTER_SIZE_32BIT:
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT32.COUNT.reg
+ = config->counter_32_bit.value;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT32.CC[0].reg =
+ config->counter_32_bit.compare_capture_channel[0];
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ hw->COUNT32.CC[1].reg =
+ config->counter_32_bit.compare_capture_channel[1];
+
+ return STATUS_OK;
+ }
+
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Sets TC module count value.
+ *
+ * Sets the current timer count value of a initialized TC module. The
+ * specified TC module may be started or stopped.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ * \param[in] count New timer count value to set
+ *
+ * \return Status of the count update procedure.
+ *
+ * \retval STATUS_OK The timer count was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified
+ */
+enum status_code tc_set_count_value(
+ const struct tc_module *const module_inst,
+ const uint32_t count)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance*/
+ Tc *const tc_module = module_inst->hw;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Write to based on the TC counter_size */
+ switch (module_inst->counter_size) {
+ case TC_COUNTER_SIZE_8BIT:
+ tc_module->COUNT8.COUNT.reg = (uint8_t)count;
+ return STATUS_OK;
+
+ case TC_COUNTER_SIZE_16BIT:
+ tc_module->COUNT16.COUNT.reg = (uint16_t)count;
+ return STATUS_OK;
+
+ case TC_COUNTER_SIZE_32BIT:
+ tc_module->COUNT32.COUNT.reg = (uint32_t)count;
+ return STATUS_OK;
+
+ default:
+ return STATUS_ERR_INVALID_ARG;
+ }
+}
+
+/**
+ * \brief Get TC module count value.
+ *
+ * Retrieves the current count value of a TC module. The specified TC module
+ * may be started or stopped.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ *
+ * \return Count value of the specified TC module.
+ */
+uint32_t tc_get_count_value(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ Tc *const tc_module = module_inst->hw;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Read from based on the TC counter size */
+ switch (module_inst->counter_size) {
+ case TC_COUNTER_SIZE_8BIT:
+ return (uint32_t)tc_module->COUNT8.COUNT.reg;
+
+ case TC_COUNTER_SIZE_16BIT:
+ return (uint32_t)tc_module->COUNT16.COUNT.reg;
+
+ case TC_COUNTER_SIZE_32BIT:
+ return tc_module->COUNT32.COUNT.reg;
+ }
+
+ Assert(false);
+ return 0;
+}
+
+/**
+ * \brief Gets the TC module capture value.
+ *
+ * Retrieves the capture value in the indicated TC module capture channel.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ * \param[in] channel_index Index of the Compare Capture channel to read
+ *
+ * \return Capture value stored in the specified timer channel.
+ */
+uint32_t tc_get_capture_value(
+ const struct tc_module *const module_inst,
+ const enum tc_compare_capture_channel channel_index)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ Tc *const tc_module = module_inst->hw;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Read out based on the TC counter size */
+ switch (module_inst->counter_size) {
+ case TC_COUNTER_SIZE_8BIT:
+ if (channel_index <
+ NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+ return tc_module->COUNT8.CC[channel_index].reg;
+ }
+
+ case TC_COUNTER_SIZE_16BIT:
+ if (channel_index <
+ NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+ return tc_module->COUNT16.CC[channel_index].reg;
+ }
+
+ case TC_COUNTER_SIZE_32BIT:
+ if (channel_index <
+ NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+ return tc_module->COUNT32.CC[channel_index].reg;
+ }
+ }
+
+ Assert(false);
+ return 0;
+}
+
+/**
+ * \brief Sets a TC module compare value.
+ *
+ * Writes a compare value to the given TC module compare/capture channel.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ * \param[in] channel_index Index of the compare channel to write to
+ * \param[in] compare New compare value to set
+ *
+ * \return Status of the compare update procedure.
+ *
+ * \retval STATUS_OK The compare value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied
+ */
+enum status_code tc_set_compare_value(
+ const struct tc_module *const module_inst,
+ const enum tc_compare_capture_channel channel_index,
+ const uint32_t compare)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module's hardware instance */
+ Tc *const tc_module = module_inst->hw;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ /* Read out based on the TC counter size */
+ switch (module_inst->counter_size) {
+ case TC_COUNTER_SIZE_8BIT:
+ if (channel_index <
+ NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+ tc_module->COUNT8.CC[channel_index].reg =
+ (uint8_t)compare;
+ return STATUS_OK;
+ }
+
+ case TC_COUNTER_SIZE_16BIT:
+ if (channel_index <
+ NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+ tc_module->COUNT16.CC[channel_index].reg =
+ (uint16_t)compare;
+ return STATUS_OK;
+ }
+
+ case TC_COUNTER_SIZE_32BIT:
+ if (channel_index <
+ NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+ tc_module->COUNT32.CC[channel_index].reg =
+ (uint32_t)compare;
+ return STATUS_OK;
+ }
+ }
+
+ return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Resets the TC module.
+ *
+ * Resets the TC module, restoring all hardware module registers to their
+ * default values and disabling the module. The TC module will not be
+ * accessible while the reset is being performed.
+ *
+ * \note When resetting a 32-bit counter only the master TC module's instance
+ * structure should be passed to the function.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ *
+ * \return Status of the procedure.
+ * \retval STATUS_OK The module was reset successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to
+ * the function. Only use reset on master
+ * TC.
+ */
+enum status_code tc_reset(
+ const struct tc_module *const module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Get a pointer to the module hardware instance */
+ TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+ if (tc_module->STATUS.reg & TC_STATUS_SLAVE) {
+ return STATUS_ERR_UNSUPPORTED_DEV;
+ }
+
+ /* Disable this module if it is running */
+ if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) {
+ tc_disable(module_inst);
+ while (tc_is_syncing(module_inst)) {
+ /* wait while module is disabling */
+ }
+ }
+
+ /* Reset this TC module */
+ tc_module->CTRLA.reg |= TC_CTRLA_SWRST;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Set the timer TOP/period value.
+ *
+ * For 8-bit counter size this function writes the top value to the period
+ * register.
+ *
+ * For 16- and 32-bit counter size this function writes the top value to
+ * Capture Compare register 0. The value in this register can not be used for
+ * any other purpose.
+ *
+ * \note This function is designed to be used in PWM or frequency
+ * match modes only. When the counter is set to 16- or 32-bit counter
+ * size. In 8-bit counter size it will always be possible to change the
+ * top value even in normal mode.
+ *
+ * \param[in] module_inst Pointer to the software module instance struct
+ * \param[in] top_value New timer TOP value to set
+ *
+ * \return Status of the TOP set procedure.
+ *
+ * \retval STATUS_OK The timer TOP value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the
+ * module instance is invalid.
+ */
+enum status_code tc_set_top_value (
+ const struct tc_module *const module_inst,
+ const uint32_t top_value)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(top_value);
+
+ Tc *const tc_module = module_inst->hw;
+
+ while (tc_is_syncing(module_inst)) {
+ /* Wait for sync */
+ }
+
+ switch (module_inst->counter_size) {
+ case TC_COUNTER_SIZE_8BIT:
+ tc_module->COUNT8.PER.reg = (uint8_t)top_value;
+ return STATUS_OK;
+
+ case TC_COUNTER_SIZE_16BIT:
+ tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
+ return STATUS_OK;
+
+ case TC_COUNTER_SIZE_32BIT:
+ tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
+ return STATUS_OK;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_api.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "gpio_api.h"
+#include "compiler.h"
+#include "port.h"
+
+uint32_t gpio_set(PinName pin)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ return (1UL << (pin % 32));
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ struct port_config pin_conf;
+ PortGroup *const port_base = (PortGroup*)port_get_group_from_gpio_pin(pin);
+
+ obj->pin = pin;
+ if (pin == (PinName)NC)
+ return;
+
+ obj->mask = gpio_set(pin);
+ port_get_config_defaults(&pin_conf);
+ obj->powersave = pin_conf.powersave;
+ obj->direction = PORT_PIN_DIR_INPUT;
+ obj->mode = PORT_PIN_PULL_UP;
+ port_pin_set_config(pin, &pin_conf);
+
+ obj->OUTCLR = &port_base->OUTCLR.reg;
+ obj->OUTSET = &port_base->OUTSET.reg;
+ obj->IN = &port_base->IN.reg;
+ obj->OUT = &port_base->OUT.reg;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ struct port_config pin_conf;
+
+ obj->mode = mode;
+ pin_conf.direction = obj->direction;
+ pin_conf.powersave = obj->powersave;
+ switch (mode) {
+ case PullNone :
+ pin_conf.input_pull = PORT_PIN_PULL_NONE;
+ break;
+ case PullUp:
+ pin_conf.input_pull = PORT_PIN_PULL_UP;
+ break;
+ case PullDown:
+ pin_conf.input_pull = PORT_PIN_PULL_DOWN;
+ break;
+ }
+ port_pin_set_config(obj->pin, &pin_conf);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ struct port_config pin_conf;
+
+ obj->direction = direction;
+ pin_conf.input_pull = obj->mode;
+ pin_conf.powersave = obj->powersave;
+ switch (direction) {
+ case PIN_INPUT :
+ pin_conf.direction = PORT_PIN_DIR_INPUT;
+ break;
+ case PIN_OUTPUT:
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+ break;
+ case PIN_INPUT_OUTPUT:
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT_WTH_READBACK;
+ break;
+ }
+ port_pin_set_config(obj->pin, &pin_conf);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_object.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ uint8_t powersave;
+ uint8_t mode;
+ uint8_t direction;
+
+ __IO uint32_t *OUTCLR;
+ __IO uint32_t *OUTSET;
+ __I uint32_t *IN;
+ __I uint32_t *OUT;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value)
+ *obj->OUTSET = obj->mask;
+ else
+ *obj->OUTCLR = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (obj->direction == PIN_INPUT)
+ return ((*obj->IN & obj->mask) ? 1 : 0);
+ else
+ return ((*obj->OUT & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+ return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/objects.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *OUTCLR;
+ __IO uint32_t *OUTSET;
+ __I uint32_t *IN;
+
+ PortName port;
+ uint32_t mask;
+};
+
+struct serial_s {
+ Sercom *usart;
+ uint32_t index;
+ uint32_t parity;
+ uint32_t stopbits;
+ uint32_t character_size;
+ uint32_t mux_setting;
+ uint32_t baudrate;
+ uint32_t pinmux_pad0;
+ uint32_t pinmux_pad1;
+ uint32_t pinmux_pad2;
+ uint32_t pinmux_pad3;
+ PinName rxpin;
+ PinName txpin;
+#if DEVICE_SERIAL_ASYNCH
+ uint32_t events;
+#endif
+};
+/*
+struct pwmout_s {
+ __IO uint32_t *MR;
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_UART_TypeDef *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct can_s {
+ LPC_CAN_TypeDef *dev;
+ int index;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+*/
+
+struct spi_s {
+ Sercom *spi;
+ uint8_t mode;
+#if DEVICE_SPI_ASYNCH
+ uint8_t status;
+ uint32_t mask;
+ uint32_t event;
+ void *tx_buffer;
+ void *rx_buffer;
+ uint8_t dma_usage;
+#endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/sercom_dma.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,95 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "system.h"
+
+#include <math.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "sercom.h"
+#include "dma_api.h"
+#include "dma_api_HAL.h"
+#include "sercom_dma.h"
+
+static struct sercom_dma sercom_channels[SERCOM_INST_NUM] = {{0}};
+
+/** Allocate a channel for TX
+ *
+ * @param[in] sercom_index index of sercom instance
+ * @param[out] tx_id pointer to channel id
+ * @return allocated channel id
+ */
+uint8_t sercom_setup_tx_channel(uint8_t sercom_index, uint8_t *tx_id)
+{
+ if (sercom_channels[sercom_index].tx_status & DMA_ALLOCATED) {
+ *tx_id = sercom_channels[sercom_index].tx_channel_id;
+ } else {
+ /* Try to allocate a channel */
+ sercom_channels[sercom_index].tx_channel_id = dma_channel_allocate(DMA_CAP_NONE);
+ if (sercom_channels[sercom_index].tx_channel_id != (uint8_t)DMA_ERROR_OUT_OF_CHANNELS) {
+ *tx_id = sercom_channels[sercom_index].tx_channel_id;
+ sercom_channels[sercom_index].tx_status = DMA_ALLOCATED;
+ } else {
+ /* Couldn't find a channel */
+ return DMA_ERROR_OUT_OF_CHANNELS;
+ }
+ }
+ return *tx_id;
+}
+
+/** Allocate a channel for RX
+ *
+ * @param[in] sercom_index index of sercom instance
+ * @param[out] rx_id pointer to channel id
+ * @return allocated channel id
+ */
+uint8_t sercom_setup_rx_channel(uint8_t sercom_index, uint8_t *rx_id)
+{
+ if (sercom_channels[sercom_index].rx_status & DMA_ALLOCATED) {
+ *rx_id = sercom_channels[sercom_index].rx_channel_id;
+ } else {
+ /* Try to allocate a channel */
+ sercom_channels[sercom_index].rx_channel_id = dma_channel_allocate(DMA_CAP_NONE);
+ if (sercom_channels[sercom_index].rx_channel_id != (uint8_t)DMA_ERROR_OUT_OF_CHANNELS) {
+ *rx_id = sercom_channels[sercom_index].rx_channel_id;
+ sercom_channels[sercom_index].rx_status = DMA_ALLOCATED;
+ } else {
+ /* Couldn't find a channel */
+ return DMA_ERROR_OUT_OF_CHANNELS;
+ }
+ }
+ return *rx_id;
+}
+
+/** Release DMA channels if allocated
+ *
+ * @param[in] sercom_index index of sercom instance
+ * @return void
+ */
+void sercom_release_channel(uint8_t sercom_index)
+{
+ if (sercom_channels[sercom_index].rx_status & DMA_ALLOCATED) {
+ if (0 == dma_channel_free(sercom_channels[sercom_index].rx_channel_id)) {
+ sercom_channels[sercom_index].rx_status = DMA_NOT_USED;
+ }
+ }
+ if (sercom_channels[sercom_index].tx_status & DMA_ALLOCATED) {
+ if (0 == dma_channel_free(sercom_channels[sercom_index].tx_channel_id)) {
+ sercom_channels[sercom_index].tx_status = DMA_NOT_USED;
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/sercom_dma.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _SERCOM_DMA_H
+#define _SERCOM_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include "dma.h"
+
+
+struct sercom_dma {
+ uint8_t tx_channel_id;
+ uint8_t rx_channel_id;
+ enum dma_status_flags tx_status;
+ enum dma_status_flags rx_status;
+};
+
+/** Allocate a channel for TX
+ *
+ * @param[in] sercom_index index of sercom instance
+ * @param[out] tx_id pointer to channel id
+ * @return allocated channel id
+ */
+uint8_t sercom_setup_tx_channel(uint8_t sercom_index, uint8_t *tx_id);
+
+/** Allocate a channel for RX
+ *
+ * @param[in] sercom_index index of sercom instance
+ * @param[out] rx_id pointer to channel id
+ * @return allocated channel id
+ */
+uint8_t sercom_setup_rx_channel(uint8_t sercom_index, uint8_t *rx_id);
+
+/** Release DMA channels if allocated
+ *
+ * @param[in] sercom_index index of sercom instance
+ * @return void
+ */
+void sercom_release_channel(uint8_t sercom_index);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SERCOM_DMA_H */
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/serial_api.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,957 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "serial_api.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "usart.h"
+#include "samr21_xplained_pro.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#define pUSART_S(obj) obj->serial.usart
+#define pSERIAL_S(obj) ((struct serial_s*)&(obj->serial))
+#else
+#define pUSART_S(obj) obj->serial
+#define pSERIAL_S(obj) ((struct serial_s*)obj)
+#endif
+#define _USART(obj) pUSART_S(obj)->USART
+#define USART_NUM 6
+
+
+uint8_t serial_get_index(serial_t *obj);
+IRQn_Type get_serial_irq_num (serial_t *obj);
+
+static uint32_t serial_irq_ids[USART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+extern uint8_t g_sys_init;
+
+static inline bool usart_syncing(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ return (_USART(obj).SYNCBUSY.reg);
+}
+
+static inline void enable_usart(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /* Enable USART module */
+ _USART(obj).CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+}
+
+static inline void disable_usart(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /* Disable USART module */
+ _USART(obj).CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+}
+
+static inline void reset_usart(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ disable_usart(obj);
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /* Reset module */
+ _USART(obj).CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
+}
+
+static enum status_code usart_set_config_default( serial_t *obj)
+{
+
+ /* Index for generic clock */
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj));
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ /* Cache new register values to minimize the number of register writes */
+ uint32_t ctrla = 0;
+ uint32_t ctrlb = 0;
+ uint16_t baud = 0;
+
+ enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+ /* Set data order, internal muxing, and clock polarity */
+ ctrla = (uint32_t)USART_DATAORDER_LSB | // data order
+ (uint32_t)pSERIAL_S(obj)->mux_setting; // mux setting // clock polarity is not used
+
+
+ /* Get baud value from mode and clock */
+ _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate,system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); // for asynchronous transfer mode
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /*Set baud val */
+ _USART(obj).BAUD.reg = baud;
+
+ /* Set sample mode */
+ ctrla |= USART_TRANSFER_ASYNCHRONOUSLY;
+
+ /* for disabled external clock source */
+ ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+
+ /* Set stopbits, character size and enable transceivers */
+ ctrlb = (uint32_t)pSERIAL_S(obj)->stopbits | (uint32_t)pSERIAL_S(obj)->character_size |
+ (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) | // receiver enable
+ (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos); // transmitter enable
+
+ /* Check parity mode bits */
+ if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) {
+ ctrla |= SERCOM_USART_CTRLA_FORM(1);
+ ctrlb |= pSERIAL_S(obj)->parity;
+ } else {
+ ctrla |= SERCOM_USART_CTRLA_FORM(0);
+ }
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /* Write configuration to CTRLB */
+ _USART(obj).CTRLB.reg = ctrlb;
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /* Write configuration to CTRLA */
+ _USART(obj).CTRLA.reg = ctrla;
+
+ return STATUS_OK;
+}
+
+void get_default_serial_values(serial_t *obj)
+{
+ /* Set default config to object */
+ pSERIAL_S(obj)->parity = USART_PARITY_NONE;
+ pSERIAL_S(obj)->stopbits = USART_STOPBITS_1;
+ pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT;
+ pSERIAL_S(obj)->baudrate = 9600;
+ pSERIAL_S(obj)->mux_setting = USART_RX_1_TX_2_XCK_3;
+ pSERIAL_S(obj)->pinmux_pad0 = PINMUX_DEFAULT;
+ pSERIAL_S(obj)->pinmux_pad1 = PINMUX_DEFAULT;
+ pSERIAL_S(obj)->pinmux_pad2 = PINMUX_DEFAULT;
+ pSERIAL_S(obj)->pinmux_pad3 = PINMUX_DEFAULT;
+};
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ if (g_sys_init == 0) {
+ system_init();
+ g_sys_init = 1;
+ }
+
+ struct system_gclk_chan_config gclk_chan_conf;
+ UARTName uart;
+ uint32_t gclk_index;
+ uint32_t pm_index;
+ uint32_t sercom_index = 0;
+ uint32_t muxsetting = 0;
+ uint32_t padsetting[4] = {0};
+
+ /* Disable USART module */
+ disable_usart(obj);
+
+ get_default_serial_values(obj);
+
+ find_pin_settings(tx, rx, NC, NC, &padsetting[0]); // tx, rx, clk(rts), chipsel(cts) pad array // getting pads from pins
+ muxsetting = find_mux_setting(tx, rx, NC, NC); // getting mux setting from pins
+ sercom_index = pinmap_sercom_peripheral(tx, rx); // same variable sercom_index reused for optimization
+ switch (sercom_index) {
+ case 0:
+ uart = UART_0;
+ pUSART_S(obj) = SERCOM0;
+ break;
+ case 1:
+ uart = UART_1;
+ pUSART_S(obj) = SERCOM1;
+ break;
+ case 2:
+ uart = UART_2;
+ pUSART_S(obj) = SERCOM2;
+ break;
+ case 3:
+ uart = UART_3;
+ pUSART_S(obj) = SERCOM3;
+ break;
+ case 4:
+ uart = UART_4;
+ pUSART_S(obj) = SERCOM4;
+ break;
+ case 5:
+ uart = UART_5;
+ pUSART_S(obj) = SERCOM5;
+ break;
+ }
+
+ pSERIAL_S(obj)->txpin = tx;
+ pSERIAL_S(obj)->rxpin = rx;
+ pSERIAL_S(obj)->mux_setting = muxsetting;//EDBG_CDC_SERCOM_MUX_SETTING;
+ pSERIAL_S(obj)->pinmux_pad0 = padsetting[0];//EDBG_CDC_SERCOM_PINMUX_PAD0;
+ pSERIAL_S(obj)->pinmux_pad1 = padsetting[1];//EDBG_CDC_SERCOM_PINMUX_PAD1;
+ pSERIAL_S(obj)->pinmux_pad2 = padsetting[2];//EDBG_CDC_SERCOM_PINMUX_PAD2;
+ pSERIAL_S(obj)->pinmux_pad3 = padsetting[3];//EDBG_CDC_SERCOM_PINMUX_PAD3;
+
+ pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+ gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+ /* The module is busy resetting itself */
+ }
+
+ if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+ /* Check the module is enabled */
+ }
+
+ /* Turn on module in PM */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+ /* Set up the GCLK for the module */
+ gclk_chan_conf.source_generator = GCLK_GENERATOR_0;
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+ system_gclk_chan_enable(gclk_index);
+ sercom_set_gclk_generator(GCLK_GENERATOR_0, false);
+
+ /* Set configuration according to the config struct */
+ usart_set_config_default(obj);
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+ uint32_t pad_pinmuxes[] = {
+ pSERIAL_S(obj)->pinmux_pad0, pSERIAL_S(obj)->pinmux_pad1,
+ pSERIAL_S(obj)->pinmux_pad2, pSERIAL_S(obj)->pinmux_pad3
+ };
+
+ /* Configure the SERCOM pins according to the user configuration */
+ for (uint8_t pad = 0; pad < 4; pad++) {
+ uint32_t current_pinmux = pad_pinmuxes[pad];
+
+ if (current_pinmux == PINMUX_DEFAULT) {
+ current_pinmux = _sercom_get_default_pad(pUSART_S(obj), pad);
+ }
+
+ if (current_pinmux != PINMUX_UNUSED) {
+ pin_conf.mux_position = current_pinmux & 0xFFFF;
+ system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+ }
+ }
+
+ if (uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /* Enable USART module */
+ enable_usart(obj);
+
+}
+
+void serial_free(serial_t *obj)
+{
+ serial_irq_ids[serial_get_index(obj)] = 0;
+ disable_usart(obj);
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+ MBED_ASSERT((baudrate == 110) || (baudrate == 150) || (baudrate == 300) || (baudrate == 1200) ||
+ (baudrate == 2400) || (baudrate == 4800) || (baudrate == 9600) || (baudrate == 19200) || (baudrate == 38400) ||
+ (baudrate == 57600) || (baudrate == 115200) || (baudrate == 230400) || (baudrate == 460800) || (baudrate == 921600) );
+
+ struct system_gclk_chan_config gclk_chan_conf;
+ uint32_t gclk_index;
+ uint16_t baud = 0;
+ uint32_t sercom_index = 0;
+ enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+ pSERIAL_S(obj)->baudrate = baudrate;
+ disable_usart(obj);
+
+ sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj));
+ gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ gclk_chan_conf.source_generator = GCLK_GENERATOR_0;
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+ system_gclk_chan_enable(gclk_index);
+ sercom_set_gclk_generator(GCLK_GENERATOR_0, false);
+
+ /* Get baud value from mode and clock */
+ _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /*Set baud val */
+ _USART(obj).BAUD.reg = baud;
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ enable_usart(obj);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+ MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
+ MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8) /*|| (data_bits == 9)*/);
+
+ /* Cache new register values to minimize the number of register writes */
+ uint32_t ctrla = 0;
+ uint32_t ctrlb = 0;
+
+ disable_usart(obj);
+
+ ctrla = _USART(obj).CTRLA.reg;
+ ctrlb = _USART(obj).CTRLB.reg;
+
+ ctrla &= ~(SERCOM_USART_CTRLA_FORM_Msk);
+ ctrlb &= ~(SERCOM_USART_CTRLB_CHSIZE_Msk);
+ ctrlb &= ~(SERCOM_USART_CTRLB_SBMODE);
+ ctrlb &= ~(SERCOM_USART_CTRLB_PMODE);
+
+ switch (stop_bits) {
+ case 1:
+ pSERIAL_S(obj)->stopbits = USART_STOPBITS_1;
+ break;
+ case 2:
+ pSERIAL_S(obj)->stopbits = USART_STOPBITS_2;
+ break;
+ default:
+ pSERIAL_S(obj)->stopbits = USART_STOPBITS_1;
+ }
+
+ switch (parity) {
+ case ParityNone:
+ pSERIAL_S(obj)->parity = USART_PARITY_NONE;
+ break;
+ case ParityOdd:
+ pSERIAL_S(obj)->parity = USART_PARITY_ODD;
+ break;
+ case ParityEven:
+ pSERIAL_S(obj)->parity = USART_PARITY_EVEN;
+ break;
+ default:
+ pSERIAL_S(obj)->parity = USART_PARITY_NONE;
+ }
+
+ switch (data_bits) {
+ case 5:
+ pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_5BIT;
+ break;
+ case 6:
+ pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_6BIT;
+ break;
+ case 7:
+ pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_7BIT;
+ break;
+ case 8:
+ pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT;
+ break; // 9 bit transfer not required in mbed
+ default:
+ pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT;
+ }
+
+
+ /* Set stopbits, character size and enable transceivers */
+ ctrlb = (uint32_t)pSERIAL_S(obj)->stopbits | (uint32_t)pSERIAL_S(obj)->character_size;
+
+ /* Check parity mode bits */
+ if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) {
+ ctrla |= SERCOM_USART_CTRLA_FORM(1);
+ ctrlb |= pSERIAL_S(obj)->parity;
+ } else {
+ ctrla |= SERCOM_USART_CTRLA_FORM(0);
+ }
+
+ /* Write configuration to CTRLB */
+ _USART(obj).CTRLB.reg = ctrlb;
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ /* Write configuration to CTRLA */
+ _USART(obj).CTRLA.reg = ctrla;
+
+ /* Wait until synchronization is complete */
+ usart_syncing(obj);
+
+ enable_usart(obj);
+}
+
+#ifdef DEVICE_SERIAL_FC
+void uart0_irq();
+void uart1_irq();
+void uart2_irq();
+void uart3_irq();
+void uart4_irq();
+void uart5_irq();
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+ uint32_t muxsetting = 0;
+ uint32_t sercom_index = 0;
+ uint32_t padsetting[4] = {0};
+
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+
+ switch ((int)pUSART_S(obj)) {
+ case UART_0:
+ vector = (uint32_t)uart0_irq;
+ break;
+ case UART_1:
+ vector = (uint32_t)uart1_irq;
+ break;
+ case UART_2:
+ vector = (uint32_t)uart2_irq;
+ break;
+ case UART_3:
+ vector = (uint32_t)uart3_irq;
+ break;
+ case UART_4:
+ vector = (uint32_t)uart4_irq;
+ break;
+ case UART_5:
+ vector = (uint32_t)uart5_irq;
+ break;
+ }
+ irq_n = get_serial_irq_num(obj);
+
+ disable_usart(obj);
+ //TODO : assert for rxflow and txflow pis to be added
+ find_pin_settings(pSERIAL_S(obj)->txpin, pSERIAL_S(obj)->rxpin, rxflow, txflow, &padsetting[0]); // tx, rx, clk(rts), chipsel(cts) pad array // getting pads from pins
+ muxsetting = find_mux_setting(pSERIAL_S(obj)->txpin, pSERIAL_S(obj)->rxpin, rxflow, txflow); // getting mux setting from pins
+
+ pSERIAL_S(obj)->mux_setting = muxsetting;//EDBG_CDC_SERCOM_MUX_SETTING;
+ pSERIAL_S(obj)->pinmux_pad0 = padsetting[0];//EDBG_CDC_SERCOM_PINMUX_PAD0;
+ pSERIAL_S(obj)->pinmux_pad1 = padsetting[1];//EDBG_CDC_SERCOM_PINMUX_PAD1;
+ pSERIAL_S(obj)->pinmux_pad2 = padsetting[2];//EDBG_CDC_SERCOM_PINMUX_PAD2;
+ pSERIAL_S(obj)->pinmux_pad3 = padsetting[3];//EDBG_CDC_SERCOM_PINMUX_PAD3;
+
+ /* Set configuration according to the config struct */
+ usart_set_config_default(obj);
+
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+ uint32_t pad_pinmuxes[] = {
+ pSERIAL_S(obj)->pinmux_pad0, pSERIAL_S(obj)->pinmux_pad1,
+ pSERIAL_S(obj)->pinmux_pad2, pSERIAL_S(obj)->pinmux_pad3
+ };
+
+ /* Configure the SERCOM pins according to the user configuration */
+ for (uint8_t pad = 0; pad < 3; pad++) {
+ uint32_t current_pinmux = pad_pinmuxes[pad];
+
+ if (current_pinmux == PINMUX_DEFAULT) {
+ current_pinmux = _sercom_get_default_pad(pUSART_S(obj), pad);
+ }
+
+ if (current_pinmux != PINMUX_UNUSED) {
+ pin_conf.mux_position = current_pinmux & 0xFFFF;
+ system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+ }
+ }
+ if (pSERIAL_S(obj)->pinmux_pad3 != PINMUX_UNUSED) {
+ pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
+ pin_conf.mux_position = pSERIAL_S(obj)->pinmux_pad3 & 0xFFFF;
+ system_pinmux_pin_set_config(pSERIAL_S(obj)->pinmux_pad3 >> 16, &pin_conf);
+ }
+
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ enable_usart(obj);
+ _USART(obj).INTENSET.reg = SERCOM_USART_INTENCLR_CTSIC;
+}
+
+void serial_break_set(serial_t *obj)
+{
+ disable_usart(obj);
+ _USART(obj).CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
+ usart_syncing(obj);
+ enable_usart(obj);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+ disable_usart(obj);
+ _USART(obj).CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
+ usart_syncing(obj);
+ enable_usart(obj);
+}
+
+#endif //DEVICE_SERIAL_FC
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+inline uint8_t serial_get_index(serial_t *obj)
+{
+ switch ((int)pUSART_S(obj)) {
+ case UART_0:
+ return 0;
+ case UART_1:
+ return 1;
+ case UART_2:
+ return 2;
+ case UART_3:
+ return 3;
+ case UART_4:
+ return 4;
+ case UART_5:
+ return 5;
+ }
+ return 0;
+}
+static inline void uart_irq(SercomUsart *const usart, uint32_t index)
+{
+ uint16_t interrupt_status;
+ interrupt_status = usart->INTFLAG.reg;
+ interrupt_status &= usart->INTENSET.reg;
+
+ if (serial_irq_ids[index] != 0) {
+ if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { // for transmit complete
+ usart->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+ irq_handler(serial_irq_ids[index], TxIrq);
+ }
+ if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { // for receive complete
+ usart->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+ irq_handler(serial_irq_ids[index], RxIrq);
+ }
+ if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) { // hardware flow control
+ usart->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+ usart->INTFLAG.reg = SERCOM_USART_INTENCLR_CTSIC;
+ }
+ }
+}
+
+void uart0_irq()
+{
+ uart_irq((SercomUsart *)UART_0, 0);
+}
+
+void uart1_irq()
+{
+ uart_irq((SercomUsart *)UART_1, 1);
+}
+
+void uart2_irq()
+{
+ uart_irq((SercomUsart *)UART_2, 2);
+}
+
+void uart3_irq()
+{
+ uart_irq((SercomUsart *)UART_3, 3);
+}
+
+void uart4_irq()
+{
+ uart_irq((SercomUsart *)UART_4, 4);
+}
+
+void uart5_irq()
+{
+ uart_irq((SercomUsart *)UART_5, 5);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ irq_handler = handler;
+ serial_irq_ids[serial_get_index(obj)] = id;
+}
+
+IRQn_Type get_serial_irq_num (serial_t *obj)
+{
+ switch ((int)pUSART_S(obj)) {
+ case UART_0:
+ return SERCOM0_IRQn;
+ case UART_1:
+ return SERCOM1_IRQn;
+ case UART_2:
+ return SERCOM2_IRQn;
+ case UART_3:
+ return SERCOM3_IRQn;
+ case UART_4:
+ return SERCOM4_IRQn;
+ case UART_5:
+ return SERCOM5_IRQn;
+ default:
+ MBED_ASSERT(0);
+ }
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+
+ switch ((int)pUSART_S(obj)) {
+ case UART_0:
+ vector = (uint32_t)uart0_irq;
+ break;
+ case UART_1:
+ vector = (uint32_t)uart1_irq;
+ break;
+ case UART_2:
+ vector = (uint32_t)uart2_irq;
+ break;
+ case UART_3:
+ vector = (uint32_t)uart3_irq;
+ break;
+ case UART_4:
+ vector = (uint32_t)uart4_irq;
+ break;
+ case UART_5:
+ vector = (uint32_t)uart5_irq;
+ break;
+ }
+ irq_n = get_serial_irq_num(obj);
+
+ if (enable) {
+ switch (irq) {
+ case RxIrq:
+ _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+ break;
+ case TxIrq:
+ _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+ break;
+ }
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ } else {
+ switch (irq) {
+ case RxIrq:
+ _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+ break;
+ case TxIrq:
+ _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+ break;
+ }
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj)
+{
+ while (!serial_readable(obj));
+ return _USART(obj).DATA.reg ;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ uint16_t q = (c & SERCOM_USART_DATA_MASK);
+ while (!serial_writable(obj));
+ _USART(obj).DATA.reg = q;
+ while (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)); // wait till data is sent
+}
+
+int serial_readable(serial_t *obj)
+{
+ uint32_t status = 1;
+ if (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+ status = 0;
+ } else {
+ status = 1;
+ }
+ return status;
+}
+
+int serial_writable(serial_t *obj)
+{
+ uint32_t status = 1;
+ if (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+ status = 0;
+ } else {
+ status = 1;
+ }
+ return status;
+}
+
+/************************************************************************************
+ * ASYNCHRONOUS HAL *
+ ************************************************************************************/
+
+#if DEVICE_SERIAL_ASYNCH
+
+/************************************
+ * HELPER FUNCTIONS *
+ ***********************************/
+void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+ if(enable) {
+ pSERIAL_S(obj)->events |= event;
+ } else {
+ pSERIAL_S(obj)->events &= ~ event;
+ }
+}
+
+void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+ if(enable) {
+ pSERIAL_S(obj)->events |= event;
+ } else {
+ pSERIAL_S(obj)->events &= ~ event;
+ }
+}
+
+void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
+{
+ // We only support byte buffers for now
+ MBED_ASSERT(width == 8);
+
+ if(serial_tx_active(obj)) return;
+
+ obj->tx_buff.buffer = tx;
+ obj->tx_buff.length = tx_length;
+ obj->tx_buff.pos = 0;
+
+ return;
+}
+
+void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
+{
+ // We only support byte buffers for now
+ MBED_ASSERT(width == 8);
+
+ if(serial_rx_active(obj)) return;
+
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.length = rx_length;
+ obj->rx_buff.pos = 0;
+
+ return;
+}
+
+void serial_set_char_match(serial_t *obj, uint8_t char_match)
+{
+ if (char_match != SERIAL_RESERVED_CHAR_MATCH) {
+ obj->char_match = char_match;
+ }
+}
+
+/************************************
+ * TRANSFER FUNCTIONS *
+ ***********************************/
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ MBED_ASSERT(tx != (void*)0);
+ if(tx_length == 0) return 0;
+
+ serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
+ serial_tx_enable_event(obj, event, true);
+
+// if( hint == DMA_USAGE_NEVER) { //TODO: DMA to be implemented later
+ NVIC_ClearPendingIRQ(get_serial_irq_num(obj));
+ NVIC_DisableIRQ(get_serial_irq_num(obj));
+ NVIC_SetPriority(get_serial_irq_num(obj), 1);
+ NVIC_SetVector(get_serial_irq_num(obj), (uint32_t)handler);
+ NVIC_EnableIRQ(get_serial_irq_num(obj));
+
+ if (pUSART_S(obj)) {
+ _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+ _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
+ }
+// }
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+ MBED_ASSERT(rx != (void*)0);
+
+ serial_rx_enable_event(obj, SERIAL_EVENT_RX_ALL, false);
+ serial_rx_enable_event(obj, event, true);
+ serial_set_char_match(obj, char_match);
+
+ serial_rx_buffer_set(obj, rx, rx_length, rx_width);
+
+// if( hint == DMA_USAGE_NEVER) { //TODO: DMA to be implemented later
+ NVIC_ClearPendingIRQ(get_serial_irq_num(obj));
+ NVIC_SetVector(get_serial_irq_num(obj), (uint32_t)handler);
+ NVIC_EnableIRQ(get_serial_irq_num(obj));
+
+ if (pUSART_S(obj)) {
+ _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+ }
+// }
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+ return ((_USART(obj).INTENSET.reg & SERCOM_USART_INTFLAG_DRE) ? true : false);
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+ return ((_USART(obj).INTENSET.reg & SERCOM_USART_INTFLAG_RXC) ? true : false);
+}
+
+int serial_tx_irq_handler_asynch(serial_t *obj)
+{
+ _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+ return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
+}
+
+int serial_rx_irq_handler_asynch(serial_t *obj)
+{
+ int event = 0;
+ /* This interrupt handler is called from USART irq */
+ uint8_t *buf = (uint8_t*)obj->rx_buff.buffer;
+ uint8_t error_code = 0;
+ uint16_t received_data = 0;
+
+
+ error_code = (uint8_t)(_USART(obj).STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+ /* Check if an error has occurred during the receiving */
+ if (error_code) {
+ /* Check which error occurred */
+ if (error_code & SERCOM_USART_STATUS_FERR) {
+ /* Store the error code and clear flag by writing 1 to it */
+ _USART(obj).STATUS.reg |= SERCOM_USART_STATUS_FERR;
+ return SERIAL_EVENT_RX_FRAMING_ERROR;
+ } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+ /* Store the error code and clear flag by writing 1 to it */
+ _USART(obj).STATUS.reg |= SERCOM_USART_STATUS_BUFOVF;
+ return SERIAL_EVENT_RX_OVERFLOW;
+ } else if (error_code & SERCOM_USART_STATUS_PERR) {
+ /* Store the error code and clear flag by writing 1 to it */
+ _USART(obj).STATUS.reg |= SERCOM_USART_STATUS_PERR;
+ return SERIAL_EVENT_RX_PARITY_ERROR;
+ }
+ }
+
+ /* Read current packet from DATA register,
+ * increment buffer pointer and decrement buffer length */
+ received_data = (_USART(obj).DATA.reg & SERCOM_USART_DATA_MASK);
+
+ /* Read value will be at least 8-bits long */
+ buf[obj->rx_buff.pos] = received_data;
+ /* Increment 8-bit pointer */
+ obj->rx_buff.pos++;
+
+ /* Check if the last character have been received */
+ if(--(obj->rx_buff.length) == 0) {
+ event |= SERIAL_EVENT_RX_COMPLETE;
+ if((buf[obj->rx_buff.pos - 1] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) {
+ event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+ }
+ serial_rx_abort_asynch(obj);
+ return event & obj->serial.events;
+ }
+
+ /* Check for character match event */
+ if((buf[obj->rx_buff.pos - 1] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) {
+ event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+ }
+
+ /* check for final char event */
+ if((obj->rx_buff.length) == 0) {
+ event |= SERIAL_EVENT_RX_COMPLETE & obj->serial.events;
+ }
+
+ if(event != 0) {
+ serial_rx_abort_asynch(obj);
+ return event & obj->serial.events;
+ }
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+//TODO: DMA to be implemented
+ uint16_t interrupt_status;
+ uint8_t *buf = obj->tx_buff.buffer;
+
+ interrupt_status = _USART(obj).INTFLAG.reg;
+ interrupt_status &= _USART(obj).INTENSET.reg;
+
+ if (pUSART_S(obj)) {
+ if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
+ /* Interrupt has another TX source */
+ if(obj->tx_buff.pos >= obj->tx_buff.length) {
+
+ /* Transfer complete. Switch off interrupt and return event. */
+ _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+ serial_tx_abort_asynch(obj);
+
+ return SERIAL_EVENT_TX_COMPLETE & obj->serial.events;
+ } else {
+ while((serial_writable(obj)) && (obj->tx_buff.pos <= (obj->tx_buff.length - 1))) {
+ _USART(obj).DATA.reg = buf[obj->tx_buff.pos];
+ obj->tx_buff.pos++;
+ }
+ }
+ }
+ if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
+ serial_tx_irq_handler_asynch(obj);
+ }
+ if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+ serial_rx_irq_handler_asynch(obj);
+ }
+ }
+
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+//TODO: DMA to be implemented
+ _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+ obj->tx_buff.pos = 0;
+ obj->tx_buff.length = 0;
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+//TODO: DMA to be implemented
+ _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+ obj->rx_buff.pos = 0;
+ obj->rx_buff.length = 0;
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/spi_api.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,984 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "spi_api.h"
+
+#include <math.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "sercom.h"
+
+/** Temporary definitions START
+ * Need to implement Pinmux APIs. For now, have hard coded to external SPIs available in SAM21 */
+#ifdef SAMR21
+#define EXT1_SPI_MODULE SERCOM5
+#define EXT1_SPI_SERCOM_MUX_SETTING ((0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) | (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB03D_SERCOM5_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+#elif SAMD21
+#define EXT1_SPI_MODULE SERCOM0
+#define EXT1_SPI_SERCOM_MUX_SETTING ((0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) | (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
+#endif
+
+/** Default pinmux. */
+# define PINMUX_DEFAULT 0
+
+/** Unused pinmux. */
+# define PINMUX_UNUSED 0xFFFFFFFF
+/** Temporary definitions END */
+
+/**
+ * \brief SPI modes enum
+ *
+ * SPI mode selection.
+ */
+enum spi_mode {
+ /** Master mode. */
+ SPI_MODE_MASTER = 1,
+ /** Slave mode. */
+ SPI_MODE_SLAVE = 0,
+};
+
+#if DEVICE_SPI_ASYNCH
+#define pSPI_S(obj) (&obj->spi)
+#define pSPI_SERCOM(obj) obj->spi.spi
+#else
+#define pSPI_S(obj) (obj)
+#define pSPI_SERCOM(obj) (obj->spi)
+#endif
+#define _SPI(obj) pSPI_SERCOM(obj)->SPI
+
+/** SPI default baud rate. */
+#define SPI_DEFAULT_BAUD 50000//100000
+
+
+/** SPI timeout value. */
+# define SPI_TIMEOUT 10000
+
+extern uint8_t g_sys_init;
+uint16_t dummy_fill_word = 0xFFFF;
+
+#if DEVICE_SPI_ASYNCH
+/* Global variables */
+extern void *_sercom_instances[SERCOM_INST_NUM];
+
+static void _spi_transceive_buffer(spi_t *obj);
+
+/** \internal
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.
+ */
+#define _SERCOM_SPI_INTERRUPT_HANDLER(n, unused) \
+void SERCOM##n##_SPIHandler(void) \
+{ \
+ _spi_transceive_buffer((spi_t *)_sercom_instances[n]); \
+}
+#define _SERCOM_SPI_INTERRUPT_HANDLER_DECLR(n, unused) \
+ (uint32_t)SERCOM##n##_SPIHandler,
+
+/** Auto-generate a set of interrupt handlers for each SERCOM SPI in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_INTERRUPT_HANDLER, ~)
+
+const uint32_t _sercom_handlers[SERCOM_INST_NUM] = {
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_INTERRUPT_HANDLER_DECLR, ~)
+};
+uint32_t _sercom_callbacks[SERCOM_INST_NUM] = {0};
+#endif /* DEVICE_SPI_ASYNCH */
+
+static inline bool spi_is_syncing(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Return synchronization status */
+ return (_SPI(obj).SYNCBUSY.reg);
+}
+
+static inline void spi_enable(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+#if DEVICE_SPI_ASYNCH
+ /* Enable interrupt */
+ NVIC_EnableIRQ(SERCOM0_IRQn + _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)));
+#endif
+
+ /* Wait until the synchronization is complete */
+ while (spi_is_syncing(obj));
+
+ /* Enable SPI */
+ _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+}
+
+static inline void spi_disable(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+#if DEVICE_SPI_ASYNCH
+ /* Disable interrupt */
+ NVIC_DisableIRQ(SERCOM0_IRQn + _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)));
+#endif
+ /* Wait until the synchronization is complete */
+ while (spi_is_syncing(obj));
+
+ /* Disable SPI */
+ _SPI(obj).CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+}
+
+static inline bool spi_is_write_complete(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Check interrupt flag */
+ return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC);
+}
+
+static inline bool spi_is_ready_to_write(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Check interrupt flag */
+ return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE);
+}
+
+static inline bool spi_is_ready_to_read(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Check interrupt flag */
+ return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC);
+}
+
+static inline bool spi_write(spi_t *obj, uint16_t tx_data)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Check if the data register has been copied to the shift register */
+ if (!spi_is_ready_to_write(obj)) {
+ /* Data register has not been copied to the shift register, return */
+ return false;
+ }
+
+ /* Write the character to the DATA register */
+ _SPI(obj).DATA.reg = tx_data & SERCOM_SPI_DATA_MASK;
+
+ return true;
+}
+
+static inline bool spi_read(spi_t *obj, uint16_t *rx_data)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Check if data is ready to be read */
+ if (!spi_is_ready_to_read(obj)) {
+ /* No data has been received, return */
+ return false;
+ }
+
+ /* Check if data is overflown */
+ if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) {
+ /* Clear overflow flag */
+ _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF;
+ }
+
+ /* Read the character from the DATA register */
+ if (_SPI(obj).CTRLB.bit.CHSIZE == 1) {
+ *rx_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK);
+ } else {
+ *rx_data = (uint8_t)_SPI(obj).DATA.reg;
+ }
+
+ return true;
+}
+
+/**
+ * \defgroup GeneralSPI SPI Configuration Functions
+ * @{
+ */
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj The SPI object to initialize
+ * @param[in] mosi The pin to use for MOSI
+ * @param[in] miso The pin to use for MISO
+ * @param[in] sclk The pin to use for SCLK
+ * @param[in] ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ uint16_t baud = 0;
+ uint32_t ctrla = 0;
+ uint32_t ctrlb = 0;
+ enum status_code error_code;
+
+ if (g_sys_init == 0) {
+ system_init();
+ g_sys_init = 1;
+ }
+
+ /* TODO: Calculate SERCOM instance from pins */
+ /* TEMP: Giving external SPI module value of SAMR21 for now */
+ pSPI_SERCOM(obj) = EXT1_SPI_MODULE;
+
+ /* Disable SPI */
+ spi_disable(obj);
+
+ /* Check if reset is in progress. */
+ if (_SPI(obj).CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) {
+ return;
+ }
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj));
+ uint32_t pm_index, gclk_index;
+#if (SAML21)
+ if (sercom_index == 5) {
+ pm_index = MCLK_APBDMASK_SERCOM5_Pos;
+ gclk_index = SERCOM5_GCLK_ID_CORE;
+ } else {
+ pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+ gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+ }
+#else
+ pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+ gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+ /* Turn on module in PM */
+#if (SAML21)
+ if (sercom_index == 5) {
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+ } else {
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+ }
+#else
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+ /* Set up the GCLK for the module */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = GCLK_GENERATOR_0;
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+ system_gclk_chan_enable(gclk_index);
+ sercom_set_gclk_generator(GCLK_GENERATOR_0, false);
+
+#if DEVICE_SPI_ASYNCH
+ /* Save the object */
+ _sercom_instances[sercom_index] = obj;
+
+ /* Configure interrupt handler */
+ NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)_sercom_handlers[sercom_index]);
+#endif
+
+ /* Set the SERCOM in SPI master mode */
+ _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3);
+ pSPI_S(obj)->mode = SPI_MODE_MASTER;
+
+ /* TODO: Do pin muxing here */
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+
+ uint32_t pad_pinmuxes[] = {
+ EXT1_SPI_SERCOM_PINMUX_PAD0, EXT1_SPI_SERCOM_PINMUX_PAD1,
+ EXT1_SPI_SERCOM_PINMUX_PAD2, EXT1_SPI_SERCOM_PINMUX_PAD3
+ };
+
+ /* Configure the SERCOM pins according to the user configuration */
+ for (uint8_t pad = 0; pad < 4; pad++) {
+ uint32_t current_pinmux = pad_pinmuxes[pad];
+ if (current_pinmux != PINMUX_UNUSED) {
+ pin_conf.mux_position = current_pinmux & 0xFFFF;
+ system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+ }
+ }
+
+ /* Get baud value, based on baudrate and the internal clock frequency */
+ uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
+ //internal_clock = 8000000;
+ error_code = _sercom_get_sync_baud_val(SPI_DEFAULT_BAUD, internal_clock, &baud);
+ if (error_code != STATUS_OK) {
+ /* Baud rate calculation error */
+ return;
+ }
+ _SPI(obj).BAUD.reg = (uint8_t)baud;
+
+ /* Set MUX setting */
+ ctrla |= EXT1_SPI_SERCOM_MUX_SETTING; /* TODO: Change this to appropriate Settings */
+
+ /* Set SPI character size */
+ ctrlb |= SERCOM_SPI_CTRLB_CHSIZE(0);
+
+ /* Enable receiver */
+ ctrlb |= SERCOM_SPI_CTRLB_RXEN;
+
+ /* Write CTRLA register */
+ _SPI(obj).CTRLA.reg |= ctrla;
+
+ /* Write CTRLB register */
+ _SPI(obj).CTRLB.reg |= ctrlb;
+
+ /* Enable SPI */
+ spi_enable(obj);
+}
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj)
+{
+ // [TODO]
+}
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] bits The number of bits per frame
+ * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in] slave Zero for master mode or non-zero for slave mode
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ /* Disable SPI */
+ spi_disable(obj);
+
+ if (slave) {
+ /* Set the SERCOM in SPI mode */
+ _SPI(obj).CTRLA.bit.MODE = 0x2;
+ pSPI_S(obj)->mode = SPI_MODE_SLAVE;
+
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+ uint32_t pad_pinmuxes[] = {
+ EXT1_SPI_SERCOM_PINMUX_PAD0, EXT1_SPI_SERCOM_PINMUX_PAD1,
+ EXT1_SPI_SERCOM_PINMUX_PAD2, EXT1_SPI_SERCOM_PINMUX_PAD3
+ };
+
+ /* Configure the SERCOM pins according to the user configuration */
+ for (uint8_t pad = 0; pad < 4; pad++) {
+ uint32_t current_pinmux = pad_pinmuxes[pad];
+ if (current_pinmux != PINMUX_UNUSED) {
+ pin_conf.mux_position = current_pinmux & 0xFFFF;
+ system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+ }
+ }
+ } else {
+ /* Already in SPI master mode */
+ }
+
+ /* TODO: Change MUX settings to appropriate value */
+
+ /* Set SPI Frame size - only 8-bit and 9-bit supported now */
+ _SPI(obj).CTRLB.bit.CHSIZE = (bits > 8)? 1 : 0;
+
+ /* Set SPI Clock Phase */
+ _SPI(obj).CTRLA.bit.CPHA = (mode & 0x01)? 1 : 0;
+
+ /* Set SPI Clock Polarity */
+ _SPI(obj).CTRLA.bit.CPOL = (mode & 0x02)? 1 : 0;
+
+ /* Enable SPI */
+ spi_enable(obj);
+}
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] hz The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz)
+{
+ uint16_t baud = 0;
+
+ /* Disable SPI */
+ spi_disable(obj);
+
+ /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj));
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+ uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
+
+ /* Get baud value, based on baudrate and the internal clock frequency */
+ enum status_code error_code = _sercom_get_sync_baud_val(hz, internal_clock, &baud);
+
+ if (error_code != STATUS_OK) {
+ /* Baud rate calculation error, return status code */
+ /* Enable SPI */
+ spi_enable(obj);
+ return;
+ }
+
+ _SPI(obj).BAUD.reg = (uint8_t)baud;
+
+ /* Enable SPI */
+ spi_enable(obj);
+}
+
+/**@}*/
+/**
+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int spi_master_write(spi_t *obj, int value)
+{
+ uint16_t rx_data = 0;
+
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+#if DEVICE_SPI_ASYNCH
+ if (obj->spi.status == STATUS_BUSY) {
+ /* Check if the SPI module is busy with a job */
+ return 0;
+ }
+#endif
+
+ /* Wait until the module is ready to write the character */
+ while (!spi_is_ready_to_write(obj));
+
+ /* Write data */
+ spi_write(obj, value);
+
+ if (!(_SPI(obj).CTRLB.bit.RXEN)) {
+ return 0;
+ }
+
+ /* Wait until the module is ready to read the character */
+ while (!spi_is_ready_to_read(obj));
+
+ /* Read data */
+ spi_read(obj, &rx_data);
+
+ return rx_data;
+}
+
+/** Check if a value is available to read
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if a value is available
+ */
+int spi_slave_receive(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ return spi_is_ready_to_read(obj);
+}
+
+/** Get a received value out of the SPI receive buffer in slave mode
+ *
+ * Blocks until a value is available
+ * @param[in] obj The SPI peripheral to read
+ * @return The value received
+ */
+int spi_slave_read(spi_t *obj)
+{
+ int i;
+ uint16_t rx_data = 0;
+
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Check for timeout period */
+ for (i = 0; i < SPI_TIMEOUT; i++) {
+ if (spi_is_ready_to_read(obj)) {
+ break;
+ }
+ }
+ if (i == SPI_TIMEOUT) {
+ /* Not ready to read data within timeout period */
+ return 0;
+ }
+
+ /* Read data */
+ spi_read(obj, &rx_data);
+
+ return rx_data;
+}
+
+/** Write a value to the SPI peripheral in slave mode
+ *
+ * Blocks until the SPI peripheral can be written to
+ * @param[in] obj The SPI peripheral to write
+ * @param[in] value The value to write
+ */
+void spi_slave_write(spi_t *obj, int value)
+{
+ int i;
+
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Check for timeout period */
+ for (i = 0; i < SPI_TIMEOUT; i++) {
+ if (spi_is_ready_to_write(obj)) {
+ break;
+ }
+ }
+ if (i == SPI_TIMEOUT) {
+ /* Not ready to write data within timeout period */
+ return;
+ }
+
+ /* Write data */
+ spi_write(obj, value);
+}
+
+/** Checks if the specified SPI peripheral is in use
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if the peripheral is currently transmitting
+ */
+int spi_busy(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ return spi_is_write_complete(obj);
+}
+
+/** Get the module number
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return The module number
+ */
+uint8_t spi_get_module(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ return _sercom_get_sercom_inst_index(pSPI_SERCOM(obj));
+}
+
+
+#if DEVICE_SPI_ASYNCH
+/**
+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+
+/**
+ * \internal
+ * Writes a character from the TX buffer to the Data register.
+ *
+ * \param[in,out] module Pointer to SPI software instance struct
+ */
+static void _spi_write_async(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ uint16_t data_to_send;
+ uint8_t *tx_buffer = obj->tx_buff.buffer;
+
+ /* Do nothing if we are at the end of buffer */
+ if (obj->tx_buff.pos < obj->tx_buff.length) {
+ /* Write value will be at least 8-bits long */
+ if (tx_buffer) {
+ data_to_send = tx_buffer[obj->tx_buff.pos];
+ } else {
+ data_to_send = dummy_fill_word;
+ }
+ /* Increment 8-bit index */
+ obj->tx_buff.pos++;
+
+ if (_SPI(obj).CTRLB.bit.CHSIZE == 1) {
+ if (tx_buffer)
+ data_to_send |= (tx_buffer[obj->tx_buff.pos] << 8);
+ /* Increment 8-bit index */
+ obj->tx_buff.pos++;
+ }
+ } else {
+ /* Write a dummy packet */
+ /* TODO: Current implementation do not enter this condition, remove if not needed */
+ data_to_send = dummy_fill_word;
+ }
+
+ /* Write the data to send*/
+ _SPI(obj).DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK;
+
+ /* Check for error */
+ if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) {
+ obj->spi.event |= SPI_EVENT_ERROR;
+ }
+}
+
+/**
+ * \internal
+ * Reads a character from the Data register to the RX buffer.
+ *
+ * \param[in,out] module Pointer to SPI software instance struct
+ */
+static void _spi_read_async(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ uint8_t *rx_buffer = obj->rx_buff.buffer;
+
+ /* Check if data is overflown */
+ if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) {
+ /* Clear overflow flag */
+ _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF;
+ if (obj->spi.mask & SPI_EVENT_RX_OVERFLOW) {
+ /* Set overflow error */
+ obj->spi.event |= SPI_EVENT_RX_OVERFLOW;
+ return;
+ }
+ }
+
+ /* Read data, either valid, or dummy */
+ uint16_t received_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK);
+
+ /* Do nothing if we are at the end of buffer */
+ if ((obj->rx_buff.pos >= obj->rx_buff.length) && rx_buffer) {
+ return;
+ }
+
+ /* Read value will be at least 8-bits long */
+ rx_buffer[obj->rx_buff.pos] = received_data;
+ /* Increment 8-bit index */
+ obj->rx_buff.pos++;
+
+ if (_SPI(obj).CTRLB.bit.CHSIZE == 1) {
+ /* 9-bit data, write next received byte to the buffer */
+ rx_buffer[obj->rx_buff.pos] = (received_data >> 8);
+ /* Increment 8-bit index */
+ obj->rx_buff.pos++;
+ }
+
+ /* Check for error */
+ if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) {
+ obj->spi.event |= SPI_EVENT_ERROR;
+ }
+}
+
+/**
+ * \internal
+ * Clears all interrupt flags of SPI
+ *
+ * \param[in,out] module Pointer to SPI software instance struct
+ */
+static void _spi_clear_interrupts(spi_t *obj)
+{
+ uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi);
+
+ /* Clear all interrupts */
+ _SPI(obj).INTENCLR.reg =
+ SERCOM_SPI_INTFLAG_DRE |
+ SERCOM_SPI_INTFLAG_TXC |
+ SERCOM_SPI_INTFLAG_RXC |
+ SERCOM_SPI_INTFLAG_ERROR;
+ NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index);
+ NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)NULL);
+}
+
+/**
+ * \internal
+ * Starts transceive of buffers with a given length
+ *
+ * \param[in,out] obj Pointer to SPI software instance struct
+ *
+ */
+static void _spi_transceive_buffer(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ void (*callback_func)(void);
+
+ uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi);
+
+ uint16_t interrupt_status = _SPI(obj).INTFLAG.reg;
+ interrupt_status &= _SPI(obj).INTENSET.reg;
+
+ if (interrupt_status & SERCOM_SPI_INTFLAG_DRE) {
+ /* Clear DRE interrupt */
+ _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE;
+ /* Write data */
+ _spi_write_async(obj);
+ /* Set TXC interrupt */
+ _SPI(obj).INTENSET.reg |= SERCOM_SPI_INTFLAG_TXC;
+ }
+ if (interrupt_status & SERCOM_SPI_INTFLAG_TXC) {
+ /* Clear TXC interrupt */
+ _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC;
+ if ((obj->rx_buff.buffer) && (obj->rx_buff.pos < obj->rx_buff.length)) {
+ while (!spi_is_ready_to_read(obj));
+ _spi_read_async(obj);
+ if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->tx_buff.length < obj->rx_buff.length)) {
+ obj->tx_buff.length = obj->rx_buff.length;
+ obj->tx_buff.buffer = 0;
+ }
+ }
+ if (obj->tx_buff.pos < obj->tx_buff.length) {
+ /* Set DRE interrupt */
+ _SPI(obj).INTENSET.reg |= SERCOM_SPI_INTFLAG_DRE;
+ }
+ }
+
+ if (obj->spi.event & (SPI_EVENT_ERROR | SPI_EVENT_RX_OVERFLOW) || (interrupt_status & SERCOM_SPI_INTFLAG_ERROR)) {
+ /* Clear all interrupts */
+ _spi_clear_interrupts(obj);
+
+ if (interrupt_status & SERCOM_SPI_INTFLAG_ERROR) {
+ obj->spi.event = STATUS_ERR_BAD_DATA;
+ }
+
+ /* Transfer interrupted, invoke the callback function */
+ if (obj->spi.event & SPI_EVENT_RX_OVERFLOW) {
+ obj->spi.status = STATUS_ERR_OVERFLOW;
+ } else {
+ obj->spi.status = STATUS_ERR_BAD_DATA;
+ }
+ callback_func = _sercom_callbacks[sercom_index];
+ if (callback_func && (obj->spi.mask & (SPI_EVENT_ERROR | SPI_EVENT_RX_OVERFLOW))) {
+ callback_func();
+ }
+ return;
+ }
+
+ if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->rx_buff.pos >= obj->rx_buff.length) && (interrupt_status & SERCOM_SPI_INTFLAG_TXC)) {
+ /* Clear all interrupts */
+ _spi_clear_interrupts(obj);
+
+ /* Transfer complete, invoke the callback function */
+ obj->spi.event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+ obj->spi.status = STATUS_OK;
+ callback_func = _sercom_callbacks[sercom_index];
+ if (callback_func && (obj->spi.mask & SPI_EVENT_COMPLETE)) {
+ callback_func();
+ }
+ return;
+ }
+}
+
+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
+ *
+ * @param[in] obj The SPI object which holds the transfer information
+ * @param[in] tx The buffer to send
+ * @param[in] tx_length The number of words to transmit
+ * @param[out]rx The buffer to receive
+ * @param[in] rx_length The number of words to receive
+ * @param[in] bit_width The bit width of buffer words
+ * @param[in] event The logical OR of events to be registered
+ * @param[in] handler SPI interrupt handler
+ * @param[in] hint A suggestion for how to use DMA with this transfer **< DMA currently not implemented >**
+ */
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ uint16_t dummy_read;
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi);
+
+ obj->spi.tx_buffer = tx;
+ obj->tx_buff.buffer = tx;
+ obj->tx_buff.pos = 0;
+ if (tx) {
+ /* Only two bit rates supported now */
+ obj->tx_buff.length = tx_length * ((bit_width > 8)? 2 : 1);
+ } else {
+ if (rx) {
+ obj->tx_buff.length = rx_length * ((bit_width > 8)? 2 : 1);
+ } else {
+ /* Nothing to transfer */
+ return;
+ }
+ }
+
+ obj->spi.rx_buffer = rx;
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.pos = 0;
+ if (rx) {
+ /* Only two bit rates supported now */
+ obj->rx_buff.length = rx_length * ((bit_width > 8)? 2 : 1);
+ } else {
+ /* Disable RXEN */
+ spi_disable(obj);
+ _SPI(obj).CTRLB.bit.RXEN = 0;
+ spi_enable(obj);
+ obj->rx_buff.length = 0;
+ }
+
+ /* Clear data buffer if there is anything pending to read */
+ while (spi_is_ready_to_read(obj)) {
+ dummy_read = _SPI(obj).DATA.reg;
+ }
+
+ _sercom_callbacks[sercom_index] = handler;
+ obj->spi.mask = event;
+
+ obj->spi.dma_usage = hint;
+
+ /*if (hint == DMA_USAGE_NEVER) {** TEMP: Commented as DMA is not implemented now */
+ /* Use irq method */
+ uint16_t irq_mask = 0;
+ obj->spi.status = STATUS_BUSY;
+
+ /* Enable interrupt */
+ NVIC_SetVector((SERCOM0_IRQn + sercom_index), _sercom_handlers[sercom_index]);
+ NVIC_EnableIRQ(SERCOM0_IRQn + sercom_index);
+
+ /* Clear all interrupts */
+ _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_ERROR;
+ _SPI(obj).INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_ERROR;
+ _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF;
+
+ /* Set SPI interrupts */
+ if (tx) {
+ irq_mask |= SERCOM_SPI_INTFLAG_DRE;
+ }
+ if (event & SPI_EVENT_ERROR) {
+ irq_mask |= SERCOM_SPI_INTFLAG_ERROR;
+ }
+ _SPI(obj).INTENSET.reg = irq_mask;
+ /*} ** TEMP: Commented as DMA is not implemented now */
+}
+
+/** The asynchronous IRQ handler
+ *
+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
+ * conditions, such as buffer overflows or transfer complete.
+ * @param[in] obj The SPI object which holds the transfer information
+ * @return event flags if a transfer termination condition was met or 0 otherwise.
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+ uint32_t transfer_event = 0;
+ uint32_t bytes_to_transfer = 0;
+
+ uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi);
+
+ /*if (obj->spi.dma_usage == DMA_USAGE_NEVER) {** TEMP: Commented as DMA is not implemented now */
+ /* IRQ method */
+ if (obj->spi.event & SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) {
+ obj->spi.event |= SPI_EVENT_COMPLETE;
+ transfer_event = obj->spi.event;
+ } else {
+ /* Data is still remaining to be transferred! */
+ obj->spi.status = STATUS_BUSY;
+
+ /* Read any pending data in RX buffer */
+ while (spi_is_ready_to_read(obj)) {
+ _spi_read_async(obj);
+ }
+
+ while (obj->tx_buff.pos < obj->tx_buff.length) {
+ /* Write data */
+ _spi_write_async(obj);
+ /* Read if any */
+ if ((obj->rx_buff.buffer) && (obj->rx_buff.pos < obj->rx_buff.length)) {
+ if (spi_is_ready_to_read(obj)) {
+ _spi_read_async(obj);
+ }
+ /* Extend TX buffer (with dummy) if there is more to receive */
+ if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->tx_buff.length < obj->rx_buff.length)) {
+ obj->tx_buff.length = obj->rx_buff.length;
+ obj->tx_buff.buffer = 0;
+ }
+ }
+ if (obj->spi.event & SPI_EVENT_ERROR) {
+ transfer_event = obj->spi.event;
+ obj->spi.status = STATUS_ERR_BAD_DATA;
+ break;
+ }
+ }
+ if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->rx_buff.pos >= obj->rx_buff.length)) {
+ transfer_event = (SPI_EVENT_INTERNAL_TRANSFER_COMPLETE | SPI_EVENT_COMPLETE);
+ obj->spi.status = STATUS_OK;
+ }
+ }
+ transfer_event &= (obj->spi.mask | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE);
+ /* Clear all interrupts */
+ _spi_clear_interrupts(obj);
+ /*}** TEMP: Commented as DMA is not implemented now */
+ return transfer_event;
+}
+
+/** Attempts to determine if the SPI peripheral is already in use.
+ * @param[in] obj The SPI object to check for activity
+ * @return non-zero if the SPI port is active or zero if it is not.
+ */
+uint8_t spi_active(spi_t *obj)
+{
+ /* Check if the SPI module is busy with a job */
+ return (obj->spi.status == STATUS_BUSY);
+}
+
+/** Abort an SPI transfer
+ *
+ * @param obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi);
+
+ /* Clear all interrupts */
+ _SPI(obj).INTENCLR.reg =
+ SERCOM_SPI_INTFLAG_DRE |
+ SERCOM_SPI_INTFLAG_TXC |
+ SERCOM_SPI_INTFLAG_RXC |
+ SERCOM_SPI_INTFLAG_ERROR;
+
+ // TODO: Disable and remove irq handler
+ NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index);
+ NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)NULL);
+
+ obj->spi.status = STATUS_ABORTED;
+}
+
+#endif /* DEVICE_SPI_ASYNCH */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM21/us_ticker.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,165 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "ins_gclk.h"
+#include "compiler.h"
+#include "system.h"
+#include "tc.h"
+#include "tc_interrupt.h"
+
+#define TICKER_COUNTER_uS TC4
+#define TICKER_COUNTER_IRQn TC4_IRQn
+#define TICKER_COUNTER_Handlr TC4_Handler
+
+static int us_ticker_inited = 0;
+extern uint8_t g_sys_init;
+
+struct tc_module us_ticker_module;
+
+
+static inline void tc_clear_interrupt(
+ struct tc_module *const module,
+ const enum tc_callback callback_type)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(module);
+
+ /* Clear interrupt flags */
+ if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+ module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1);
+ } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+ module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2);
+ } else {
+ module->hw->COUNT8.INTENCLR.reg = (1 << callback_type);
+ }
+}
+
+void us_ticker_irq_handler_internal(struct tc_module* us_tc_module)
+{
+ uint32_t status_flags;
+
+ /* Clear TC capture overflow and TC count overflow */
+ status_flags = TC_STATUS_CAPTURE_OVERFLOW | TC_STATUS_COUNT_OVERFLOW;
+ tc_clear_status(&us_ticker_module, status_flags);
+
+ us_ticker_irq_handler();
+}
+
+void us_ticker_init(void)
+{
+ uint32_t cycles_per_us;
+ uint32_t prescaler = 0;
+ struct tc_config config_tc;
+ enum status_code ret_status;
+
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ if (g_sys_init == 0) {
+ system_init();
+ g_sys_init = 1;
+ }
+
+ tc_get_config_defaults(&config_tc);
+
+ cycles_per_us = system_gclk_gen_get_hz(config_tc.clock_source) / 1000000;
+ MBED_ASSERT(cycles_per_us > 0);
+ /*while((cycles_per_us & 1) == 0 && prescaler <= 10) {
+ cycles_per_us = cycles_per_us >> 1;
+ prescaler++;
+ }*/
+ while((cycles_per_us > 1) && (prescaler <= 10)) {
+ cycles_per_us = cycles_per_us >> 1;
+ prescaler++;
+ }
+ if (prescaler >= 9) {
+ prescaler = 7;
+ } else if (prescaler >= 7) {
+ prescaler = 6;
+ } else if (prescaler >= 5) {
+ prescaler = 5;
+ }
+
+ config_tc.clock_prescaler = TC_CTRLA_PRESCALER(prescaler);
+ config_tc.counter_size = TC_COUNTER_SIZE_32BIT;
+ config_tc.run_in_standby = true;
+ config_tc.counter_32_bit.value = 0;
+ config_tc.counter_32_bit.compare_capture_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = 0xFFFFFFFF;
+
+ /* Initialize the timer */
+ ret_status = tc_init(&us_ticker_module, TICKER_COUNTER_uS, &config_tc);
+ MBED_ASSERT(ret_status == STATUS_OK);
+
+ /* Register callback function */
+ tc_register_callback(&us_ticker_module, (tc_callback_t)us_ticker_irq_handler_internal, TC_CALLBACK_CC_CHANNEL0);
+
+ /* Enable the timer module */
+ tc_enable(&us_ticker_module);
+}
+
+uint32_t us_ticker_read()
+{
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ return tc_get_count_value(&us_ticker_module);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ uint32_t cur_time;
+ int32_t delta;
+
+ cur_time = us_ticker_read();
+ delta = (int32_t)((uint32_t)timestamp - cur_time);
+ if (delta < 0) {
+ /* Event already occurred in past */
+ us_ticker_irq_handler();
+ return;
+ }
+
+ NVIC_DisableIRQ(TICKER_COUNTER_IRQn);
+ NVIC_SetVector(TICKER_COUNTER_IRQn, (uint32_t)TICKER_COUNTER_Handlr);
+
+ /* Enable the callback */
+ tc_enable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0);
+ tc_set_compare_value(&us_ticker_module, TC_COMPARE_CAPTURE_CHANNEL_0, (uint32_t)timestamp);
+
+ NVIC_EnableIRQ(TICKER_COUNTER_IRQn);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ /* Disable the callback */
+ tc_disable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0);
+ NVIC_DisableIRQ(TICKER_COUNTER_IRQn);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ uint32_t status_flags;
+
+ /* Clear TC channel 0 match */
+ status_flags = TC_STATUS_CHANNEL_0_MATCH;
+ tc_clear_status(&us_ticker_module, status_flags);
+
+ /* Clear the interrupt */
+ tc_clear_interrupt(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0);
+ NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn);
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common/boards/board.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,392 @@
+/**
+ * \file
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board (parameter BOARD).
+ *
+ * Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * \defgroup group_common_boards Generic board support
+ *
+ * The generic board support module includes board-specific definitions
+ * and function prototypes, such as the board initialization function.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.
+#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
+#define UC3L_EK 7 //!< AT32UC3L-EK board.
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
+#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
+#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board
+#define SAM3S_EK 32 //!< SAM3S-EK board.
+#define SAM3U_EK 33 //!< SAM3U-EK board.
+#define SAM3X_EK 34 //!< SAM3X-EK board.
+#define SAM3N_EK 35 //!< SAM3N-EK board.
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
+#define SAM4S_EK 37 //!< SAM4S-EK board.
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
+#define STK600_MEGA 39 //!< STK600 MEGA board.
+#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
+#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
+#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
+#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
+#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board
+#define SAM4L_EK 45 //!< SAM4L-EK board.
+#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
+#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
+#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
+#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
+#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
+#define SAM4E_EK 51 //!< SAM4E-EK board.
+#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
+#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
+#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
+#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit
+#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit
+#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit
+#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
+#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board
+#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
+#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
+#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
+#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB
+#define SAM4C_EK 64 //!< SAM4C-EK board.
+#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
+#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
+#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
+#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
+#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
+#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
+#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
+#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
+#define ATPL230AMB 73 //!< ATPL230AMB board.
+#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
+#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board.
+#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board.
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices
+#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
+#define USER_BOARD 99 //!< User-reserved board (if any).
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102 1 //!< AT32UC3B EXT1102 board
+#define MC300 2 //!< AT32UC3 MC300 board
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
+#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
+#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
+#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+# include "evk1100/evk1100.h"
+#elif BOARD == EVK1101
+# include "evk1101/evk1101.h"
+#elif BOARD == UC3C_EK
+# include "uc3c_ek/uc3c_ek.h"
+#elif BOARD == EVK1104
+# include "evk1104/evk1104.h"
+#elif BOARD == EVK1105
+# include "evk1105/evk1105.h"
+#elif BOARD == STK600_RCUC3L0
+# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+# include "uc3l_ek/uc3l_ek.h"
+#elif BOARD == STK600_RCUC3L4
+# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
+#elif BOARD == XPLAIN
+# include "xplain/xplain.h"
+#elif BOARD == STK600_MEGA
+/*No header-file to include*/
+#elif BOARD == STK600_MEGA_RF
+# include "stk600.h"
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
+# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
+#elif BOARD == ATMEGA256RFR2_ZIGBIT
+# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
+#elif BOARD == STK600_RC032X
+# include "stk600/rc032x/stk600_rc032x.h"
+#elif BOARD == STK600_RC044X
+# include "stk600/rc044x/stk600_rc044x.h"
+#elif BOARD == STK600_RC064X
+# include "stk600/rc064x/stk600_rc064x.h"
+#elif BOARD == STK600_RC100X
+# include "stk600/rc100x/stk600_rc100x.h"
+#elif BOARD == UC3_A3_XPLAINED
+# include "uc3_a3_xplained/uc3_a3_xplained.h"
+#elif BOARD == UC3_L0_XPLAINED
+# include "uc3_l0_xplained/uc3_l0_xplained.h"
+#elif BOARD == STK600_RCUC3B0
+# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
+#elif BOARD == STK600_RCUC3D
+# include "stk600/rcuc3d/stk600_rcuc3d.h"
+#elif BOARD == STK600_RCUC3C0
+# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
+#elif BOARD == SAMG53_XPLAINED_PRO
+# include "samg53_xplained_pro/samg53_xplained_pro.h"
+#elif BOARD == SAMG55_XPLAINED_PRO
+# include "samg55_xplained_pro/samg55_xplained_pro.h"
+#elif BOARD == XMEGA_B1_XPLAINED
+# include "xmega_b1_xplained/xmega_b1_xplained.h"
+#elif BOARD == STK600_RC064X_LCDX
+# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
+#elif BOARD == STK600_RC100X_LCDX
+# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
+#elif BOARD == XMEGA_A1_XPLAINED
+# include "xmega_a1_xplained/xmega_a1_xplained.h"
+#elif BOARD == XMEGA_A1U_XPLAINED_PRO
+# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
+#elif BOARD == UC3_L0_XPLAINED_BC
+# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
+#elif BOARD == SAM3S_EK
+# include "sam3s_ek/sam3s_ek.h"
+# include "system_sam3s.h"
+#elif BOARD == SAM3S_EK2
+# include "sam3s_ek2/sam3s_ek2.h"
+# include "system_sam3sd8.h"
+#elif BOARD == SAM3U_EK
+# include "sam3u_ek/sam3u_ek.h"
+# include "system_sam3u.h"
+#elif BOARD == SAM3X_EK
+# include "sam3x_ek/sam3x_ek.h"
+# include "system_sam3x.h"
+#elif BOARD == SAM3N_EK
+# include "sam3n_ek/sam3n_ek.h"
+# include "system_sam3n.h"
+#elif BOARD == SAM4S_EK
+# include "sam4s_ek/sam4s_ek.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_WPIR_RD
+# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_XPLAINED
+# include "sam4s_xplained/sam4s_xplained.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_EK2
+# include "sam4s_ek2/sam4s_ek2.h"
+# include "system_sam4s.h"
+#elif BOARD == MEGA_1284P_XPLAINED
+/*No header-file to include*/
+#elif BOARD == ARDUINO_DUE_X
+# include "arduino_due_x/arduino_due_x.h"
+# include "system_sam3x.h"
+#elif BOARD == SAM4L_EK
+# include "sam4l_ek/sam4l_ek.h"
+#elif BOARD == SAM4E_EK
+# include "sam4e_ek/sam4e_ek.h"
+#elif BOARD == SAMD20_XPLAINED_PRO
+# include "samd20_xplained_pro/samd20_xplained_pro.h"
+#elif BOARD == SAMD21_XPLAINED_PRO
+# include "samd21_xplained_pro/samd21_xplained_pro.h"
+#elif BOARD == SAMR21_XPLAINED_PRO
+# include "samr21_xplained_pro/samr21_xplained_pro.h"
+#elif BOARD == SAMD11_XPLAINED_PRO
+# include "samd11_xplained_pro/samd11_xplained_pro.h"
+#elif BOARD == SAML21_XPLAINED_PRO
+# include "saml21_xplained_pro/saml21_xplained_pro.h"
+#elif BOARD == SAM4N_XPLAINED_PRO
+# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
+#elif BOARD == MEGA1284P_XPLAINED_BC
+# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
+#elif BOARD == UC3_L0_QT600
+# include "uc3_l0_qt600/uc3_l0_qt600.h"
+#elif BOARD == XMEGA_A3BU_XPLAINED
+# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
+#elif BOARD == XMEGA_E5_XPLAINED
+# include "xmega_e5_xplained/xmega_e5_xplained.h"
+#elif BOARD == UC3B_BOARD_CONTROLLER
+# include "uc3b_board_controller/uc3b_board_controller.h"
+#elif BOARD == RZ600
+# include "rz600/rz600.h"
+#elif BOARD == STK600_RCUC3A0
+# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
+#elif BOARD == ATXMEGA128A1_QT600
+# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
+#elif BOARD == STK600_RCUC3L3
+# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
+#elif BOARD == SAM4S_XPLAINED_PRO
+# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
+#elif BOARD == SAM4L_XPLAINED_PRO
+# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
+#elif BOARD == SAM4L8_XPLAINED_PRO
+# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
+#elif BOARD == SAM4C_EK
+# include "sam4c_ek/sam4c_ek.h"
+#elif BOARD == SAM4CMP_DB
+# include "sam4cmp_db/sam4cmp_db.h"
+#elif BOARD == SAM4CMS_DB
+# include "sam4cms_db/sam4cms_db.h"
+#elif BOARD == SAM4CP16BMB
+# include "sam4cp16bmb/sam4cp16bmb.h"
+#elif BOARD == ATPL230AMB
+# include "atpl230amb/atpl230amb.h"
+#elif BOARD == SIMULATOR_XMEGA_A1
+# include "simulator/xmega_a1/simulator_xmega_a1.h"
+#elif BOARD == XMEGA_C3_XPLAINED
+# include "xmega_c3_xplained/xmega_c3_xplained.h"
+#elif BOARD == XMEGA_RF233_ZIGBIT
+# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
+#elif BOARD == XMEGA_A3_REB_CBB
+# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
+#elif BOARD == ATMEGARFX_RCB
+# include "atmegarfx_rcb/atmegarfx_rcb.h"
+#elif BOARD == RCB256RFR2_XPRO
+# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
+#elif BOARD == XMEGA_RF212B_ZIGBIT
+# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
+#elif BOARD == SAM4E_XPLAINED_PRO
+# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
+#elif BOARD == AVR_SIMULATOR_UC3
+# include "avr_simulator_uc3/avr_simulator_uc3.h"
+#elif BOARD == USER_BOARD
+// User-reserved area: #include the header file of your board here (if any).
+# include "user_board.h"
+#elif BOARD == DUMMY_BOARD
+# include "dummy/dummy_board.h"
+#else
+# error No known Atmel board defined
+#endif
+
+#if (defined EXT_BOARD)
+# if EXT_BOARD == MC300
+# include "mc300/mc300.h"
+# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+# include "sensors_xplained/sensors_xplained.h"
+# elif EXT_BOARD == RZ600_AT86RF231
+# include "at86rf231/at86rf231.h"
+# elif EXT_BOARD == RZ600_AT86RF230B
+# include "at86rf230b/at86rf230b.h"
+# elif EXT_BOARD == RZ600_AT86RF212
+# include "at86rf212/at86rf212.h"
+# elif EXT_BOARD == SECURITY_XPLAINED
+# include "security_xplained.h"
+# elif EXT_BOARD == USER_EXT_BOARD
+// User-reserved area: #include the header file of your extension board here
+// (if any).
+# endif
+#endif
+
+
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+
+#endif // #ifdef __AVR32_ABI_COMPILER__
+#else
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif // _BOARD_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common/utils/interrupt.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,142 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8- and 32-bit AVR
+ *
+ * Copyright (c) 2010-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef UTILS_INTERRUPT_H
+#define UTILS_INTERRUPT_H
+
+#include <parts.h>
+
+#if XMEGA || MEGA || TINY
+# include "interrupt/interrupt_avr8.h"
+#elif UC3
+# include "interrupt/interrupt_avr32.h"
+#elif SAM
+# include "interrupt/interrupt_sam_nvic.h"
+#else
+# error Unsupported device.
+#endif
+
+/**
+ * \defgroup interrupt_group Global interrupt management
+ *
+ * This is a driver for global enabling and disabling of interrupts.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \def CONFIG_INTERRUPT_FORCE_INTC
+ * \brief Force usage of the ASF INTC driver
+ *
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
+ * This is useful to ensure compatibility across compilers and shall be used only when required
+ * by the application needs.
+ */
+# define CONFIG_INTERRUPT_FORCE_INTC
+#endif
+
+//! \name Global interrupt flags
+//@{
+/**
+ * \typedef irqflags_t
+ * \brief Type used for holding state of interrupt flag
+ */
+
+/**
+ * \def cpu_irq_enable
+ * \brief Enable interrupts globally
+ */
+
+/**
+ * \def cpu_irq_disable
+ * \brief Disable interrupts globally
+ */
+
+/**
+ * \fn irqflags_t cpu_irq_save(void)
+ * \brief Get and clear the global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_restore.
+ *
+ * \return Current state of interrupt flags.
+ *
+ * \note This function leaves interrupts disabled.
+ */
+
+/**
+ * \fn void cpu_irq_restore(irqflags_t flags)
+ * \brief Restore global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_save.
+ *
+ * \param flags State to set interrupt flag to.
+ */
+
+/**
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
+ * \brief Check if interrupts are globally enabled in supplied flags
+ *
+ * \param flags Currents state of interrupt flags.
+ *
+ * \return True if interrupts are enabled.
+ */
+
+/**
+ * \def cpu_irq_is_enabled
+ * \brief Check if interrupts are globally enabled
+ *
+ * \return True if interrupts are enabled.
+ */
+//@}
+
+//! @}
+
+/**
+ * \ingroup interrupt_group
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
+ */
+
+#endif /* UTILS_INTERRUPT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,86 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "interrupt_sam_nvic.h"
+
+#if !defined(__DOXYGEN__)
+/* Deprecated - global flag to determine the global interrupt state. Required by
+ * QTouch library, however new applications should use cpu_irq_is_enabled()
+ * which probes the true global interrupt state from the CPU special registers.
+ */
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+ if (cpu_irq_critical_section_counter == 0) {
+ if (cpu_irq_is_enabled()) {
+ cpu_irq_disable();
+ cpu_irq_prev_interrupt_state = true;
+ } else {
+ /* Make sure the to save the prev state as false */
+ cpu_irq_prev_interrupt_state = false;
+ }
+
+ }
+
+ cpu_irq_critical_section_counter++;
+}
+
+void cpu_irq_leave_critical(void)
+{
+ /* Check if the user is trying to leave a critical section when not in a critical section */
+ Assert(cpu_irq_critical_section_counter > 0);
+
+ cpu_irq_critical_section_counter--;
+
+ /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+ was enabled when entering critical state */
+ if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+ cpu_irq_enable();
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,189 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ * add to vector table in binary generation, so there is no service
+ * register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+ ISR(foo_irq_handler)
+ {
+ // Function definition
+ ...
+ }
+\endcode
+ *
+ * \param func Name for the function.
+ */
+# define ISR(func) \
+ void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+# define irq_initialize_vectors() \
+ do { \
+ } while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+ irq_initialize_vectors();
+ irq_register_handler(foo_irq_handler);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ * files (exceptions.h).
+ */
+# define irq_register_handler(int_num, int_prio) \
+ NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
+ NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
+ NVIC_EnableIRQ( (IRQn_Type)int_num); \
+
+//@}
+
+# define cpu_irq_enable() \
+ do { \
+ g_interrupt_enabled = true; \
+ __DMB(); \
+ __enable_irq(); \
+ } while (0)
+# define cpu_irq_disable() \
+ do { \
+ __disable_irq(); \
+ __DMB(); \
+ g_interrupt_enabled = false; \
+ } while (0)
+
+typedef uint32_t irqflags_t;
+
+#if !defined(__DOXYGEN__)
+extern volatile bool g_interrupt_enabled;
+#endif
+
+#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
+
+static volatile uint32_t cpu_irq_critical_section_counter;
+static volatile bool cpu_irq_prev_interrupt_state;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+ irqflags_t flags = cpu_irq_is_enabled();
+ cpu_irq_disable();
+ return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+ return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+ if (cpu_irq_is_enabled_flags(flags))
+ cpu_irq_enable();
+}
+
+void cpu_irq_enter_critical(void);
+void cpu_irq_leave_critical(void);
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt() cpu_irq_enable()
+#define Disable_global_interrupt() cpu_irq_disable()
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common/utils/parts.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,1280 @@
+/**
+ * \file
+ *
+ * \brief Atmel part identification macros
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#ifndef ATMEL_PARTS_H
+#define ATMEL_PARTS_H
+
+/**
+ * \defgroup part_macros_group Atmel part identification macros
+ *
+ * This collection of macros identify which series and families that the various
+ * Atmel parts belong to. These can be used to select part-dependent sections of
+ * code at compile time.
+ *
+ * @{
+ */
+
+/**
+ * \name Convenience macros for part checking
+ * @{
+ */
+/* ! Check GCC and IAR part definition for 8-bit AVR */
+#define AVR8_PART_IS_DEFINED(part) \
+ (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for 32-bit AVR */
+#define AVR32_PART_IS_DEFINED(part) \
+ (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for SAM */
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
+/** @} */
+
+/**
+ * \defgroup uc3_part_macros_group AVR UC3 parts
+ * @{
+ */
+
+/**
+ * \name AVR UC3 A series
+ * @{
+ */
+#define UC3A0 ( \
+ AVR32_PART_IS_DEFINED(UC3A0128) || \
+ AVR32_PART_IS_DEFINED(UC3A0256) || \
+ AVR32_PART_IS_DEFINED(UC3A0512) \
+ )
+
+#define UC3A1 ( \
+ AVR32_PART_IS_DEFINED(UC3A1128) || \
+ AVR32_PART_IS_DEFINED(UC3A1256) || \
+ AVR32_PART_IS_DEFINED(UC3A1512) \
+ )
+
+#define UC3A3 ( \
+ AVR32_PART_IS_DEFINED(UC3A364) || \
+ AVR32_PART_IS_DEFINED(UC3A364S) || \
+ AVR32_PART_IS_DEFINED(UC3A3128) || \
+ AVR32_PART_IS_DEFINED(UC3A3128S) || \
+ AVR32_PART_IS_DEFINED(UC3A3256) || \
+ AVR32_PART_IS_DEFINED(UC3A3256S) \
+ )
+
+#define UC3A4 ( \
+ AVR32_PART_IS_DEFINED(UC3A464) || \
+ AVR32_PART_IS_DEFINED(UC3A464S) || \
+ AVR32_PART_IS_DEFINED(UC3A4128) || \
+ AVR32_PART_IS_DEFINED(UC3A4128S) || \
+ AVR32_PART_IS_DEFINED(UC3A4256) || \
+ AVR32_PART_IS_DEFINED(UC3A4256S) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 B series
+ * @{
+ */
+#define UC3B0 ( \
+ AVR32_PART_IS_DEFINED(UC3B064) || \
+ AVR32_PART_IS_DEFINED(UC3B0128) || \
+ AVR32_PART_IS_DEFINED(UC3B0256) || \
+ AVR32_PART_IS_DEFINED(UC3B0512) \
+ )
+
+#define UC3B1 ( \
+ AVR32_PART_IS_DEFINED(UC3B164) || \
+ AVR32_PART_IS_DEFINED(UC3B1128) || \
+ AVR32_PART_IS_DEFINED(UC3B1256) || \
+ AVR32_PART_IS_DEFINED(UC3B1512) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 C series
+ * @{
+ */
+#define UC3C0 ( \
+ AVR32_PART_IS_DEFINED(UC3C064C) || \
+ AVR32_PART_IS_DEFINED(UC3C0128C) || \
+ AVR32_PART_IS_DEFINED(UC3C0256C) || \
+ AVR32_PART_IS_DEFINED(UC3C0512C) \
+ )
+
+#define UC3C1 ( \
+ AVR32_PART_IS_DEFINED(UC3C164C) || \
+ AVR32_PART_IS_DEFINED(UC3C1128C) || \
+ AVR32_PART_IS_DEFINED(UC3C1256C) || \
+ AVR32_PART_IS_DEFINED(UC3C1512C) \
+ )
+
+#define UC3C2 ( \
+ AVR32_PART_IS_DEFINED(UC3C264C) || \
+ AVR32_PART_IS_DEFINED(UC3C2128C) || \
+ AVR32_PART_IS_DEFINED(UC3C2256C) || \
+ AVR32_PART_IS_DEFINED(UC3C2512C) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 D series
+ * @{
+ */
+#define UC3D3 ( \
+ AVR32_PART_IS_DEFINED(UC64D3) || \
+ AVR32_PART_IS_DEFINED(UC128D3) \
+ )
+
+#define UC3D4 ( \
+ AVR32_PART_IS_DEFINED(UC64D4) || \
+ AVR32_PART_IS_DEFINED(UC128D4) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 L series
+ * @{
+ */
+#define UC3L0 ( \
+ AVR32_PART_IS_DEFINED(UC3L016) || \
+ AVR32_PART_IS_DEFINED(UC3L032) || \
+ AVR32_PART_IS_DEFINED(UC3L064) \
+ )
+
+#define UC3L0128 ( \
+ AVR32_PART_IS_DEFINED(UC3L0128) \
+ )
+
+#define UC3L0256 ( \
+ AVR32_PART_IS_DEFINED(UC3L0256) \
+ )
+
+#define UC3L3 ( \
+ AVR32_PART_IS_DEFINED(UC64L3U) || \
+ AVR32_PART_IS_DEFINED(UC128L3U) || \
+ AVR32_PART_IS_DEFINED(UC256L3U) \
+ )
+
+#define UC3L4 ( \
+ AVR32_PART_IS_DEFINED(UC64L4U) || \
+ AVR32_PART_IS_DEFINED(UC128L4U) || \
+ AVR32_PART_IS_DEFINED(UC256L4U) \
+ )
+
+#define UC3L3_L4 (UC3L3 || UC3L4)
+/** @} */
+
+/**
+ * \name AVR UC3 families
+ * @{
+ */
+/** AVR UC3 A family */
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)
+
+/** AVR UC3 B family */
+#define UC3B (UC3B0 || UC3B1)
+
+/** AVR UC3 C family */
+#define UC3C (UC3C0 || UC3C1 || UC3C2)
+
+/** AVR UC3 D family */
+#define UC3D (UC3D3 || UC3D4)
+
+/** AVR UC3 L family */
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)
+/** @} */
+
+/** AVR UC3 product line */
+#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)
+
+/** @} */
+
+/**
+ * \defgroup xmega_part_macros_group AVR XMEGA parts
+ * @{
+ */
+
+/**
+ * \name AVR XMEGA A series
+ * @{
+ */
+#define XMEGA_A1 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A1) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A1) \
+ )
+
+#define XMEGA_A3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A3) || \
+ AVR8_PART_IS_DEFINED(ATxmega192A3) || \
+ AVR8_PART_IS_DEFINED(ATxmega256A3) \
+ )
+
+#define XMEGA_A3B ( \
+ AVR8_PART_IS_DEFINED(ATxmega256A3B) \
+ )
+
+#define XMEGA_A4 ( \
+ AVR8_PART_IS_DEFINED(ATxmega16A4) || \
+ AVR8_PART_IS_DEFINED(ATxmega32A4) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA AU series
+ * @{
+ */
+#define XMEGA_A1U ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A1U) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A1U) \
+ )
+
+#define XMEGA_A3U ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A3U) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
+ AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
+ AVR8_PART_IS_DEFINED(ATxmega256A3U) \
+ )
+
+#define XMEGA_A3BU ( \
+ AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
+ )
+
+#define XMEGA_A4U ( \
+ AVR8_PART_IS_DEFINED(ATxmega16A4U) || \
+ AVR8_PART_IS_DEFINED(ATxmega32A4U) || \
+ AVR8_PART_IS_DEFINED(ATxmega64A4U) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A4U) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA B series
+ * @{
+ */
+#define XMEGA_B1 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64B1) || \
+ AVR8_PART_IS_DEFINED(ATxmega128B1) \
+ )
+
+#define XMEGA_B3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64B3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128B3) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA C series
+ * @{
+ */
+#define XMEGA_C3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega384C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega256C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega192C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega64C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega32C3) \
+ )
+
+#define XMEGA_C4 ( \
+ AVR8_PART_IS_DEFINED(ATxmega32C4) || \
+ AVR8_PART_IS_DEFINED(ATxmega16C4) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA D series
+ * @{
+ */
+#define XMEGA_D3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega32D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega64D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega192D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega256D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega384D3) \
+ )
+
+#define XMEGA_D4 ( \
+ AVR8_PART_IS_DEFINED(ATxmega16D4) || \
+ AVR8_PART_IS_DEFINED(ATxmega32D4) || \
+ AVR8_PART_IS_DEFINED(ATxmega64D4) || \
+ AVR8_PART_IS_DEFINED(ATxmega128D4) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA E series
+ * @{
+ */
+#define XMEGA_E5 ( \
+ AVR8_PART_IS_DEFINED(ATxmega8E5) || \
+ AVR8_PART_IS_DEFINED(ATxmega16E5) || \
+ AVR8_PART_IS_DEFINED(ATxmega32E5) \
+ )
+/** @} */
+
+
+/**
+ * \name AVR XMEGA families
+ * @{
+ */
+/** AVR XMEGA A family */
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)
+
+/** AVR XMEGA AU family */
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)
+
+/** AVR XMEGA B family */
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)
+
+/** AVR XMEGA C family */
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)
+
+/** AVR XMEGA D family */
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)
+
+/** AVR XMEGA E family */
+#define XMEGA_E (XMEGA_E5)
+/** @} */
+
+
+/** AVR XMEGA product line */
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)
+
+/** @} */
+
+/**
+ * \defgroup mega_part_macros_group megaAVR parts
+ *
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the
+ * part header files. They are not names of official megaAVR device series or
+ * families.
+ *
+ * @{
+ */
+
+/**
+ * \name ATmegaxx0/xx1 subgroups
+ * @{
+ */
+#define MEGA_XX0 ( \
+ AVR8_PART_IS_DEFINED(ATmega640) || \
+ AVR8_PART_IS_DEFINED(ATmega1280) || \
+ AVR8_PART_IS_DEFINED(ATmega2560) \
+ )
+
+#define MEGA_XX1 ( \
+ AVR8_PART_IS_DEFINED(ATmega1281) || \
+ AVR8_PART_IS_DEFINED(ATmega2561) \
+ )
+/** @} */
+
+/**
+ * \name megaAVR groups
+ * @{
+ */
+/** ATmegaxx0/xx1 group */
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)
+
+/** ATmegaxx4 group */
+#define MEGA_XX4 ( \
+ AVR8_PART_IS_DEFINED(ATmega164A) || \
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \
+ AVR8_PART_IS_DEFINED(ATmega324A) || \
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \
+ AVR8_PART_IS_DEFINED(ATmega644) || \
+ AVR8_PART_IS_DEFINED(ATmega644A) || \
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \
+ AVR8_PART_IS_DEFINED(ATmega1284P) || \
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+ )
+
+/** ATmegaxx4 group */
+#define MEGA_XX4_A ( \
+ AVR8_PART_IS_DEFINED(ATmega164A) || \
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \
+ AVR8_PART_IS_DEFINED(ATmega324A) || \
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \
+ AVR8_PART_IS_DEFINED(ATmega644A) || \
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \
+ AVR8_PART_IS_DEFINED(ATmega1284P) \
+ )
+
+/** ATmegaxx8 group */
+#define MEGA_XX8 ( \
+ AVR8_PART_IS_DEFINED(ATmega48) || \
+ AVR8_PART_IS_DEFINED(ATmega48A) || \
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \
+ AVR8_PART_IS_DEFINED(ATmega88) || \
+ AVR8_PART_IS_DEFINED(ATmega88A) || \
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \
+ AVR8_PART_IS_DEFINED(ATmega168) || \
+ AVR8_PART_IS_DEFINED(ATmega168A) || \
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \
+ AVR8_PART_IS_DEFINED(ATmega328) || \
+ AVR8_PART_IS_DEFINED(ATmega328P) \
+ )
+
+/** ATmegaxx8A/P/PA group */
+#define MEGA_XX8_A ( \
+ AVR8_PART_IS_DEFINED(ATmega48A) || \
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \
+ AVR8_PART_IS_DEFINED(ATmega88A) || \
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \
+ AVR8_PART_IS_DEFINED(ATmega168A) || \
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \
+ AVR8_PART_IS_DEFINED(ATmega328P) \
+ )
+
+/** ATmegaxx group */
+#define MEGA_XX ( \
+ AVR8_PART_IS_DEFINED(ATmega16) || \
+ AVR8_PART_IS_DEFINED(ATmega16A) || \
+ AVR8_PART_IS_DEFINED(ATmega32) || \
+ AVR8_PART_IS_DEFINED(ATmega32A) || \
+ AVR8_PART_IS_DEFINED(ATmega64) || \
+ AVR8_PART_IS_DEFINED(ATmega64A) || \
+ AVR8_PART_IS_DEFINED(ATmega128) || \
+ AVR8_PART_IS_DEFINED(ATmega128A) \
+ )
+
+/** ATmegaxxA/P/PA group */
+#define MEGA_XX_A ( \
+ AVR8_PART_IS_DEFINED(ATmega16A) || \
+ AVR8_PART_IS_DEFINED(ATmega32A) || \
+ AVR8_PART_IS_DEFINED(ATmega64A) || \
+ AVR8_PART_IS_DEFINED(ATmega128A) \
+ )
+/** ATmegaxxRFA1 group */
+#define MEGA_RFA1 ( \
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+ )
+
+/** ATmegaxxRFR2 group */
+#define MEGA_RFR2 ( \
+ AVR8_PART_IS_DEFINED(ATmega64RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega128RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega256RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega644RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
+ )
+
+
+/** ATmegaxxRFxx group */
+#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)
+
+/**
+ * \name ATmegaxx_un0/un1/un2 subgroups
+ * @{
+ */
+#define MEGA_XX_UN0 ( \
+ AVR8_PART_IS_DEFINED(ATmega16) || \
+ AVR8_PART_IS_DEFINED(ATmega16A) || \
+ AVR8_PART_IS_DEFINED(ATmega32) || \
+ AVR8_PART_IS_DEFINED(ATmega32A) \
+ )
+
+/** ATmegaxx group without power reduction and
+ * And interrupt sense register.
+ */
+#define MEGA_XX_UN1 ( \
+ AVR8_PART_IS_DEFINED(ATmega64) || \
+ AVR8_PART_IS_DEFINED(ATmega64A) || \
+ AVR8_PART_IS_DEFINED(ATmega128) || \
+ AVR8_PART_IS_DEFINED(ATmega128A) \
+ )
+
+/** ATmegaxx group without power reduction and
+ * And interrupt sense register.
+ */
+#define MEGA_XX_UN2 ( \
+ AVR8_PART_IS_DEFINED(ATmega169P) || \
+ AVR8_PART_IS_DEFINED(ATmega169PA) || \
+ AVR8_PART_IS_DEFINED(ATmega329P) || \
+ AVR8_PART_IS_DEFINED(ATmega329PA) \
+ )
+
+/** Devices added to complete megaAVR offering.
+ * Please do not use this group symbol as it is not intended
+ * to be permanent: the devices should be regrouped.
+ */
+#define MEGA_UNCATEGORIZED ( \
+ AVR8_PART_IS_DEFINED(AT90CAN128) || \
+ AVR8_PART_IS_DEFINED(AT90CAN32) || \
+ AVR8_PART_IS_DEFINED(AT90CAN64) || \
+ AVR8_PART_IS_DEFINED(AT90PWM1) || \
+ AVR8_PART_IS_DEFINED(AT90PWM216) || \
+ AVR8_PART_IS_DEFINED(AT90PWM2B) || \
+ AVR8_PART_IS_DEFINED(AT90PWM316) || \
+ AVR8_PART_IS_DEFINED(AT90PWM3B) || \
+ AVR8_PART_IS_DEFINED(AT90PWM81) || \
+ AVR8_PART_IS_DEFINED(AT90USB1286) || \
+ AVR8_PART_IS_DEFINED(AT90USB1287) || \
+ AVR8_PART_IS_DEFINED(AT90USB162) || \
+ AVR8_PART_IS_DEFINED(AT90USB646) || \
+ AVR8_PART_IS_DEFINED(AT90USB647) || \
+ AVR8_PART_IS_DEFINED(AT90USB82) || \
+ AVR8_PART_IS_DEFINED(ATmega1284) || \
+ AVR8_PART_IS_DEFINED(ATmega162) || \
+ AVR8_PART_IS_DEFINED(ATmega164P) || \
+ AVR8_PART_IS_DEFINED(ATmega165A) || \
+ AVR8_PART_IS_DEFINED(ATmega165P) || \
+ AVR8_PART_IS_DEFINED(ATmega165PA) || \
+ AVR8_PART_IS_DEFINED(ATmega168P) || \
+ AVR8_PART_IS_DEFINED(ATmega169A) || \
+ AVR8_PART_IS_DEFINED(ATmega16M1) || \
+ AVR8_PART_IS_DEFINED(ATmega16U2) || \
+ AVR8_PART_IS_DEFINED(ATmega16U4) || \
+ AVR8_PART_IS_DEFINED(ATmega256RFA2) || \
+ AVR8_PART_IS_DEFINED(ATmega324P) || \
+ AVR8_PART_IS_DEFINED(ATmega325) || \
+ AVR8_PART_IS_DEFINED(ATmega3250) || \
+ AVR8_PART_IS_DEFINED(ATmega3250A) || \
+ AVR8_PART_IS_DEFINED(ATmega3250P) || \
+ AVR8_PART_IS_DEFINED(ATmega3250PA) || \
+ AVR8_PART_IS_DEFINED(ATmega325A) || \
+ AVR8_PART_IS_DEFINED(ATmega325P) || \
+ AVR8_PART_IS_DEFINED(ATmega325PA) || \
+ AVR8_PART_IS_DEFINED(ATmega329) || \
+ AVR8_PART_IS_DEFINED(ATmega3290) || \
+ AVR8_PART_IS_DEFINED(ATmega3290A) || \
+ AVR8_PART_IS_DEFINED(ATmega3290P) || \
+ AVR8_PART_IS_DEFINED(ATmega3290PA) || \
+ AVR8_PART_IS_DEFINED(ATmega329A) || \
+ AVR8_PART_IS_DEFINED(ATmega32M1) || \
+ AVR8_PART_IS_DEFINED(ATmega32U2) || \
+ AVR8_PART_IS_DEFINED(ATmega32U4) || \
+ AVR8_PART_IS_DEFINED(ATmega48P) || \
+ AVR8_PART_IS_DEFINED(ATmega644P) || \
+ AVR8_PART_IS_DEFINED(ATmega645) || \
+ AVR8_PART_IS_DEFINED(ATmega6450) || \
+ AVR8_PART_IS_DEFINED(ATmega6450A) || \
+ AVR8_PART_IS_DEFINED(ATmega6450P) || \
+ AVR8_PART_IS_DEFINED(ATmega645A) || \
+ AVR8_PART_IS_DEFINED(ATmega645P) || \
+ AVR8_PART_IS_DEFINED(ATmega649) || \
+ AVR8_PART_IS_DEFINED(ATmega6490) || \
+ AVR8_PART_IS_DEFINED(ATmega6490A) || \
+ AVR8_PART_IS_DEFINED(ATmega6490P) || \
+ AVR8_PART_IS_DEFINED(ATmega649A) || \
+ AVR8_PART_IS_DEFINED(ATmega649P) || \
+ AVR8_PART_IS_DEFINED(ATmega64M1) || \
+ AVR8_PART_IS_DEFINED(ATmega64RFA2) || \
+ AVR8_PART_IS_DEFINED(ATmega8) || \
+ AVR8_PART_IS_DEFINED(ATmega8515) || \
+ AVR8_PART_IS_DEFINED(ATmega8535) || \
+ AVR8_PART_IS_DEFINED(ATmega88P) || \
+ AVR8_PART_IS_DEFINED(ATmega8A) || \
+ AVR8_PART_IS_DEFINED(ATmega8U2) \
+ )
+
+/** Unspecified group */
+#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
+ MEGA_UNCATEGORIZED)
+
+/** @} */
+
+/** megaAVR product line */
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
+ MEGA_UNSPECIFIED)
+
+/** @} */
+
+/**
+ * \defgroup tiny_part_macros_group tinyAVR parts
+ *
+ * @{
+ */
+
+/**
+ * \name tinyAVR groups
+ * @{
+ */
+
+/** Devices added to complete tinyAVR offering.
+ * Please do not use this group symbol as it is not intended
+ * to be permanent: the devices should be regrouped.
+ */
+#define TINY_UNCATEGORIZED ( \
+ AVR8_PART_IS_DEFINED(ATtiny10) || \
+ AVR8_PART_IS_DEFINED(ATtiny13) || \
+ AVR8_PART_IS_DEFINED(ATtiny13A) || \
+ AVR8_PART_IS_DEFINED(ATtiny1634) || \
+ AVR8_PART_IS_DEFINED(ATtiny167) || \
+ AVR8_PART_IS_DEFINED(ATtiny20) || \
+ AVR8_PART_IS_DEFINED(ATtiny2313) || \
+ AVR8_PART_IS_DEFINED(ATtiny2313A) || \
+ AVR8_PART_IS_DEFINED(ATtiny24) || \
+ AVR8_PART_IS_DEFINED(ATtiny24A) || \
+ AVR8_PART_IS_DEFINED(ATtiny25) || \
+ AVR8_PART_IS_DEFINED(ATtiny26) || \
+ AVR8_PART_IS_DEFINED(ATtiny261) || \
+ AVR8_PART_IS_DEFINED(ATtiny261A) || \
+ AVR8_PART_IS_DEFINED(ATtiny4) || \
+ AVR8_PART_IS_DEFINED(ATtiny40) || \
+ AVR8_PART_IS_DEFINED(ATtiny4313) || \
+ AVR8_PART_IS_DEFINED(ATtiny43U) || \
+ AVR8_PART_IS_DEFINED(ATtiny44) || \
+ AVR8_PART_IS_DEFINED(ATtiny44A) || \
+ AVR8_PART_IS_DEFINED(ATtiny45) || \
+ AVR8_PART_IS_DEFINED(ATtiny461) || \
+ AVR8_PART_IS_DEFINED(ATtiny461A) || \
+ AVR8_PART_IS_DEFINED(ATtiny48) || \
+ AVR8_PART_IS_DEFINED(ATtiny5) || \
+ AVR8_PART_IS_DEFINED(ATtiny828) || \
+ AVR8_PART_IS_DEFINED(ATtiny84) || \
+ AVR8_PART_IS_DEFINED(ATtiny84A) || \
+ AVR8_PART_IS_DEFINED(ATtiny85) || \
+ AVR8_PART_IS_DEFINED(ATtiny861) || \
+ AVR8_PART_IS_DEFINED(ATtiny861A) || \
+ AVR8_PART_IS_DEFINED(ATtiny87) || \
+ AVR8_PART_IS_DEFINED(ATtiny88) || \
+ AVR8_PART_IS_DEFINED(ATtiny9) \
+ )
+
+/** @} */
+
+/** tinyAVR product line */
+#define TINY (TINY_UNCATEGORIZED)
+
+/** @} */
+
+/**
+ * \defgroup sam_part_macros_group SAM parts
+ * @{
+ */
+
+/**
+ * \name SAM3S series
+ * @{
+ */
+#define SAM3S1 ( \
+ SAM_PART_IS_DEFINED(SAM3S1A) || \
+ SAM_PART_IS_DEFINED(SAM3S1B) || \
+ SAM_PART_IS_DEFINED(SAM3S1C) \
+ )
+
+#define SAM3S2 ( \
+ SAM_PART_IS_DEFINED(SAM3S2A) || \
+ SAM_PART_IS_DEFINED(SAM3S2B) || \
+ SAM_PART_IS_DEFINED(SAM3S2C) \
+ )
+
+#define SAM3S4 ( \
+ SAM_PART_IS_DEFINED(SAM3S4A) || \
+ SAM_PART_IS_DEFINED(SAM3S4B) || \
+ SAM_PART_IS_DEFINED(SAM3S4C) \
+ )
+
+#define SAM3S8 ( \
+ SAM_PART_IS_DEFINED(SAM3S8B) || \
+ SAM_PART_IS_DEFINED(SAM3S8C) \
+ )
+
+#define SAM3SD8 ( \
+ SAM_PART_IS_DEFINED(SAM3SD8B) || \
+ SAM_PART_IS_DEFINED(SAM3SD8C) \
+ )
+/** @} */
+
+/**
+ * \name SAM3U series
+ * @{
+ */
+#define SAM3U1 ( \
+ SAM_PART_IS_DEFINED(SAM3U1C) || \
+ SAM_PART_IS_DEFINED(SAM3U1E) \
+ )
+
+#define SAM3U2 ( \
+ SAM_PART_IS_DEFINED(SAM3U2C) || \
+ SAM_PART_IS_DEFINED(SAM3U2E) \
+ )
+
+#define SAM3U4 ( \
+ SAM_PART_IS_DEFINED(SAM3U4C) || \
+ SAM_PART_IS_DEFINED(SAM3U4E) \
+ )
+/** @} */
+
+/**
+ * \name SAM3N series
+ * @{
+ */
+#define SAM3N00 ( \
+ SAM_PART_IS_DEFINED(SAM3N00A) || \
+ SAM_PART_IS_DEFINED(SAM3N00B) \
+ )
+
+#define SAM3N0 ( \
+ SAM_PART_IS_DEFINED(SAM3N0A) || \
+ SAM_PART_IS_DEFINED(SAM3N0B) || \
+ SAM_PART_IS_DEFINED(SAM3N0C) \
+ )
+
+#define SAM3N1 ( \
+ SAM_PART_IS_DEFINED(SAM3N1A) || \
+ SAM_PART_IS_DEFINED(SAM3N1B) || \
+ SAM_PART_IS_DEFINED(SAM3N1C) \
+ )
+
+#define SAM3N2 ( \
+ SAM_PART_IS_DEFINED(SAM3N2A) || \
+ SAM_PART_IS_DEFINED(SAM3N2B) || \
+ SAM_PART_IS_DEFINED(SAM3N2C) \
+ )
+
+#define SAM3N4 ( \
+ SAM_PART_IS_DEFINED(SAM3N4A) || \
+ SAM_PART_IS_DEFINED(SAM3N4B) || \
+ SAM_PART_IS_DEFINED(SAM3N4C) \
+ )
+/** @} */
+
+/**
+ * \name SAM3X series
+ * @{
+ */
+#define SAM3X4 ( \
+ SAM_PART_IS_DEFINED(SAM3X4C) || \
+ SAM_PART_IS_DEFINED(SAM3X4E) \
+ )
+
+#define SAM3X8 ( \
+ SAM_PART_IS_DEFINED(SAM3X8C) || \
+ SAM_PART_IS_DEFINED(SAM3X8E) || \
+ SAM_PART_IS_DEFINED(SAM3X8H) \
+ )
+/** @} */
+
+/**
+ * \name SAM3A series
+ * @{
+ */
+#define SAM3A4 ( \
+ SAM_PART_IS_DEFINED(SAM3A4C) \
+ )
+
+#define SAM3A8 ( \
+ SAM_PART_IS_DEFINED(SAM3A8C) \
+ )
+/** @} */
+
+/**
+ * \name SAM4S series
+ * @{
+ */
+#define SAM4S2 ( \
+ SAM_PART_IS_DEFINED(SAM4S2A) || \
+ SAM_PART_IS_DEFINED(SAM4S2B) || \
+ SAM_PART_IS_DEFINED(SAM4S2C) \
+ )
+
+#define SAM4S4 ( \
+ SAM_PART_IS_DEFINED(SAM4S4A) || \
+ SAM_PART_IS_DEFINED(SAM4S4B) || \
+ SAM_PART_IS_DEFINED(SAM4S4C) \
+ )
+
+#define SAM4S8 ( \
+ SAM_PART_IS_DEFINED(SAM4S8B) || \
+ SAM_PART_IS_DEFINED(SAM4S8C) \
+ )
+
+#define SAM4S16 ( \
+ SAM_PART_IS_DEFINED(SAM4S16B) || \
+ SAM_PART_IS_DEFINED(SAM4S16C) \
+ )
+
+#define SAM4SA16 ( \
+ SAM_PART_IS_DEFINED(SAM4SA16B) || \
+ SAM_PART_IS_DEFINED(SAM4SA16C) \
+ )
+
+#define SAM4SD16 ( \
+ SAM_PART_IS_DEFINED(SAM4SD16B) || \
+ SAM_PART_IS_DEFINED(SAM4SD16C) \
+ )
+
+#define SAM4SD32 ( \
+ SAM_PART_IS_DEFINED(SAM4SD32B) || \
+ SAM_PART_IS_DEFINED(SAM4SD32C) \
+ )
+/** @} */
+
+/**
+ * \name SAM4L series
+ * @{
+ */
+#define SAM4LS ( \
+ SAM_PART_IS_DEFINED(SAM4LS2A) || \
+ SAM_PART_IS_DEFINED(SAM4LS2B) || \
+ SAM_PART_IS_DEFINED(SAM4LS2C) || \
+ SAM_PART_IS_DEFINED(SAM4LS4A) || \
+ SAM_PART_IS_DEFINED(SAM4LS4B) || \
+ SAM_PART_IS_DEFINED(SAM4LS4C) || \
+ SAM_PART_IS_DEFINED(SAM4LS8A) || \
+ SAM_PART_IS_DEFINED(SAM4LS8B) || \
+ SAM_PART_IS_DEFINED(SAM4LS8C) \
+ )
+
+#define SAM4LC ( \
+ SAM_PART_IS_DEFINED(SAM4LC2A) || \
+ SAM_PART_IS_DEFINED(SAM4LC2B) || \
+ SAM_PART_IS_DEFINED(SAM4LC2C) || \
+ SAM_PART_IS_DEFINED(SAM4LC4A) || \
+ SAM_PART_IS_DEFINED(SAM4LC4B) || \
+ SAM_PART_IS_DEFINED(SAM4LC4C) || \
+ SAM_PART_IS_DEFINED(SAM4LC8A) || \
+ SAM_PART_IS_DEFINED(SAM4LC8B) || \
+ SAM_PART_IS_DEFINED(SAM4LC8C) \
+ )
+/** @} */
+
+/**
+ * \name SAMD20 series
+ * @{
+ */
+#define SAMD20J ( \
+ SAM_PART_IS_DEFINED(SAMD20J14) || \
+ SAM_PART_IS_DEFINED(SAMD20J15) || \
+ SAM_PART_IS_DEFINED(SAMD20J16) || \
+ SAM_PART_IS_DEFINED(SAMD20J17) || \
+ SAM_PART_IS_DEFINED(SAMD20J18) \
+ )
+
+#define SAMD20G ( \
+ SAM_PART_IS_DEFINED(SAMD20G14) || \
+ SAM_PART_IS_DEFINED(SAMD20G15) || \
+ SAM_PART_IS_DEFINED(SAMD20G16) || \
+ SAM_PART_IS_DEFINED(SAMD20G17) || \
+ SAM_PART_IS_DEFINED(SAMD20G17U) || \
+ SAM_PART_IS_DEFINED(SAMD20G18) || \
+ SAM_PART_IS_DEFINED(SAMD20G18U) \
+ )
+
+#define SAMD20E ( \
+ SAM_PART_IS_DEFINED(SAMD20E14) || \
+ SAM_PART_IS_DEFINED(SAMD20E15) || \
+ SAM_PART_IS_DEFINED(SAMD20E16) || \
+ SAM_PART_IS_DEFINED(SAMD20E17) || \
+ SAM_PART_IS_DEFINED(SAMD20E18) || \
+ SAM_PART_IS_DEFINED(SAMD20E1F) \
+ )
+/** @} */
+
+/**
+ * \name SAMD21 series
+ * @{
+ */
+#define SAMD21J ( \
+ SAM_PART_IS_DEFINED(SAMD21J15A) || \
+ SAM_PART_IS_DEFINED(SAMD21J16A) || \
+ SAM_PART_IS_DEFINED(SAMD21J17A) || \
+ SAM_PART_IS_DEFINED(SAMD21J18A) \
+ )
+
+#define SAMD21G ( \
+ SAM_PART_IS_DEFINED(SAMD21G15A) || \
+ SAM_PART_IS_DEFINED(SAMD21G16A) || \
+ SAM_PART_IS_DEFINED(SAMD21G17A) || \
+ SAM_PART_IS_DEFINED(SAMD21G18A) \
+ )
+
+#define SAMD21E ( \
+ SAM_PART_IS_DEFINED(SAMD21E15A) || \
+ SAM_PART_IS_DEFINED(SAMD21E16A) || \
+ SAM_PART_IS_DEFINED(SAMD21E17A) || \
+ SAM_PART_IS_DEFINED(SAMD21E18A) \
+ )
+/** @} */
+
+/**
+ * \name SAMR21 series
+ * @{
+ */
+#define SAMR21G ( \
+ SAM_PART_IS_DEFINED(SAMR21G16A) || \
+ SAM_PART_IS_DEFINED(SAMR21G17A) || \
+ SAM_PART_IS_DEFINED(SAMR21G18A) \
+ )
+
+#define SAMR21E ( \
+ SAM_PART_IS_DEFINED(SAMR21E16A) || \
+ SAM_PART_IS_DEFINED(SAMR21E17A) || \
+ SAM_PART_IS_DEFINED(SAMR21E18A) \
+ )
+/** @} */
+
+/**
+ * \name SAMD10 series
+ * @{
+ */
+#define SAMD10C ( \
+ SAM_PART_IS_DEFINED(SAMD10C12A) || \
+ SAM_PART_IS_DEFINED(SAMD10C13A) || \
+ SAM_PART_IS_DEFINED(SAMD10C14A) \
+ )
+
+#define SAMD10DS ( \
+ SAM_PART_IS_DEFINED(SAMD10D12AS) || \
+ SAM_PART_IS_DEFINED(SAMD10D13AS) || \
+ SAM_PART_IS_DEFINED(SAMD10D14AS) \
+ )
+
+#define SAMD10DM ( \
+ SAM_PART_IS_DEFINED(SAMD10D12AM) || \
+ SAM_PART_IS_DEFINED(SAMD10D13AM) || \
+ SAM_PART_IS_DEFINED(SAMD10D14AM) \
+ )
+/** @} */
+
+/**
+ * \name SAMD11 series
+ * @{
+ */
+#define SAMD11C ( \
+ SAM_PART_IS_DEFINED(SAMD11C14A) \
+ )
+
+#define SAMD11DS ( \
+ SAM_PART_IS_DEFINED(SAMD11D14AS) \
+ )
+
+#define SAMD11DM ( \
+ SAM_PART_IS_DEFINED(SAMD11D14AM) \
+ )
+/** @} */
+
+/**
+ * \name SAML21 series
+ * @{
+ */
+#define SAML21E ( \
+ SAM_PART_IS_DEFINED(SAML21E15A) || \
+ SAM_PART_IS_DEFINED(SAML21E16A) || \
+ SAM_PART_IS_DEFINED(SAML21E17A) || \
+ SAM_PART_IS_DEFINED(SAML21E18A) \
+ )
+
+#define SAML21G ( \
+ SAM_PART_IS_DEFINED(SAML21G16A) || \
+ SAM_PART_IS_DEFINED(SAML21G17A) || \
+ SAM_PART_IS_DEFINED(SAML21G18A) \
+ )
+
+#define SAML21J ( \
+ SAM_PART_IS_DEFINED(SAML21J16A) || \
+ SAM_PART_IS_DEFINED(SAML21J17A) || \
+ SAM_PART_IS_DEFINED(SAML21J18A) \
+ )
+/** @} */
+
+/**
+ * \name SAM4E series
+ * @{
+ */
+#define SAM4E8 ( \
+ SAM_PART_IS_DEFINED(SAM4E8C) || \
+ SAM_PART_IS_DEFINED(SAM4E8E) \
+ )
+
+#define SAM4E16 ( \
+ SAM_PART_IS_DEFINED(SAM4E16C) || \
+ SAM_PART_IS_DEFINED(SAM4E16E) \
+ )
+/** @} */
+
+/**
+ * \name SAM4N series
+ * @{
+ */
+#define SAM4N8 ( \
+ SAM_PART_IS_DEFINED(SAM4N8A) || \
+ SAM_PART_IS_DEFINED(SAM4N8B) || \
+ SAM_PART_IS_DEFINED(SAM4N8C) \
+ )
+
+#define SAM4N16 ( \
+ SAM_PART_IS_DEFINED(SAM4N16B) || \
+ SAM_PART_IS_DEFINED(SAM4N16C) \
+ )
+/** @} */
+
+/**
+ * \name SAM4C series
+ * @{
+ */
+#define SAM4C8_0 ( \
+ SAM_PART_IS_DEFINED(SAM4C8C_0) \
+ )
+
+#define SAM4C8_1 ( \
+ SAM_PART_IS_DEFINED(SAM4C8C_1) \
+ )
+
+#define SAM4C8 (SAM4C8_0 || SAM4C8_1)
+
+#define SAM4C16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4C16C_0) \
+ )
+
+#define SAM4C16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4C16C_1) \
+ )
+
+#define SAM4C16 (SAM4C16_0 || SAM4C16_1)
+
+#define SAM4C32_0 ( \
+ SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
+ SAM_PART_IS_DEFINED(SAM4C32E_0) \
+ )
+
+#define SAM4C32_1 ( \
+ SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
+ SAM_PART_IS_DEFINED(SAM4C32E_1) \
+ )
+
+
+#define SAM4C32 (SAM4C32_0 || SAM4C32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CM series
+ * @{
+ */
+#define SAM4CMP8_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
+ )
+
+#define SAM4CMP8_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
+ )
+
+#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
+
+#define SAM4CMP16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
+ )
+
+#define SAM4CMP16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
+ )
+
+#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
+
+#define SAM4CMP32_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
+ )
+
+#define SAM4CMP32_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
+ )
+
+#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
+
+#define SAM4CMS8_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
+ )
+
+#define SAM4CMS8_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
+ )
+
+#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
+
+#define SAM4CMS16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
+ )
+
+#define SAM4CMS16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
+ )
+
+#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
+
+#define SAM4CMS32_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
+ )
+
+#define SAM4CMS32_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
+ )
+
+#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CP series
+ * @{
+ */
+#define SAM4CP16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CP16B_0) \
+ )
+
+#define SAM4CP16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CP16B_1) \
+ )
+
+#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
+/** @} */
+
+/**
+ * \name SAMG series
+ * @{
+ */
+#define SAMG51 ( \
+ SAM_PART_IS_DEFINED(SAMG51G18) \
+ )
+
+#define SAMG53 ( \
+ SAM_PART_IS_DEFINED(SAMG53G19) ||\
+ SAM_PART_IS_DEFINED(SAMG53N19) \
+ )
+
+#define SAMG54 ( \
+ SAM_PART_IS_DEFINED(SAMG54G19) ||\
+ SAM_PART_IS_DEFINED(SAMG54J19) ||\
+ SAM_PART_IS_DEFINED(SAMG54N19) \
+ )
+
+#define SAMG55 ( \
+ SAM_PART_IS_DEFINED(SAMG55G18) ||\
+ SAM_PART_IS_DEFINED(SAMG55G19) ||\
+ SAM_PART_IS_DEFINED(SAMG55J18) ||\
+ SAM_PART_IS_DEFINED(SAMG55J19) ||\
+ SAM_PART_IS_DEFINED(SAMG55N19) \
+ )
+/** @} */
+/**
+ * \name SAM families
+ * @{
+ */
+/** SAM3S Family */
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
+
+/** SAM3U Family */
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
+
+/** SAM3N Family */
+#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
+
+/** SAM3XA Family */
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
+
+/** SAM4S Family */
+#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)
+
+/** SAM4L Family */
+#define SAM4L (SAM4LS || SAM4LC)
+
+/** SAMD20 Family */
+#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)
+
+/** SAMD21 Family */
+#define SAMD21 (SAMD21J || SAMD21G || SAMD21E)
+
+/** SAMD10 Family */
+#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM)
+
+/** SAMD11 Family */
+#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM)
+
+/** SAMD Family */
+#define SAMD (SAMD20 || SAMD21 || SAMD10 || SAMD11)
+
+/** SAMR21 Family */
+#define SAMR21 (SAMR21G || SAMR21E)
+
+/** SAML21 Family */
+#define SAML21 (SAML21J || SAML21G || SAML21E)
+
+/** SAM4E Family */
+#define SAM4E (SAM4E8 || SAM4E16)
+
+/** SAM4N Family */
+#define SAM4N (SAM4N8 || SAM4N16)
+
+/** SAM4C Family */
+#define SAM4C_0 (SAM4C8_0 || SAM4C16_0 || SAM4C32_0)
+#define SAM4C_1 (SAM4C8_1 || SAM4C16_1 || SAM4C32_1)
+#define SAM4C (SAM4C8 || SAM4C16 || SAM4C32)
+
+/** SAM4CM Family */
+#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || SAM4CMS8_0 || \
+ SAM4CMS16_0 || SAM4CMS32_0)
+#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || SAM4CMS8_1 || \
+ SAM4CMS16_1 || SAM4CMS32_1)
+#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || SAM4CMS8 || \
+ SAM4CMS16 || SAM4CMS32)
+
+/** SAM4CP Family */
+#define SAM4CP_0 (SAM4CP16_0)
+#define SAM4CP_1 (SAM4CP16_1)
+#define SAM4CP (SAM4CP16)
+
+/** SAMG Family */
+#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55)
+
+/** SAM0 product line (cortex-m0+) */
+#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21)
+
+/** @} */
+
+/** SAM product line */
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
+ SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG)
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* ATMEL_PARTS_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common2/services/delay/delay.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief Common Delay Service
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef DELAY_H_INCLUDED
+#define DELAY_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup group_common_services_delay Busy-Wait Delay Routines
+ *
+ * This module provides simple loop-based delay routines for those
+ * applications requiring a brief wait during execution. Common for
+ * API ver. 2.
+ *
+ * @{
+ */
+#include <compiler.h>
+#include <gclk.h>
+
+// TEMP: Added by V
+#include "sam0/systick_counter.h"
+#ifdef SYSTICK_MODE
+#include "sam0/systick_counter.h"
+#endif
+#ifdef CYCLE_MODE
+#include "sam0/cycle_counter.h"
+#endif
+
+void delay_init(void);
+
+/**
+ * \def delay_s
+ * \brief Delay in at least specified number of seconds.
+ * \param delay Delay in seconds
+ */
+#define delay_s(delay) cpu_delay_s(delay)
+
+/**
+ * \def delay_ms
+ * \brief Delay in at least specified number of milliseconds.
+ * \param delay Delay in milliseconds
+ */
+#define delay_ms(delay) cpu_delay_ms(delay)
+
+/**
+ * \def delay_us
+ * \brief Delay in at least specified number of microseconds.
+ * \param delay Delay in microseconds
+ */
+#define delay_us(delay) cpu_delay_us(delay)
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* DELAY_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.c Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+
+#include "delay.h"
+
+/**
+ * Value used to calculate ms delay. Default to be used with a 8MHz clock;
+ */
+static uint32_t cycles_per_ms = 8000000UL / 1000;
+static uint32_t cycles_per_us = 8000000UL / 1000000;
+
+/**
+ * \brief Initialize the delay driver.
+ *
+ * This must be called during start up to initialize the delay routine with
+ * the current used main clock. It must run any time the main CPU clock is changed.
+ */
+void delay_init(void)
+{
+ cycles_per_ms = system_gclk_gen_get_hz(0);
+ cycles_per_ms /= 1000;
+ cycles_per_us = cycles_per_ms / 1000;
+
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * \brief Delay loop to delay at least n number of microseconds
+ *
+ * \param n Number of microseconds to wait
+ */
+void delay_cycles_us(
+ uint32_t n)
+{
+ while (n--) {
+ /* Devide up to blocks of 10u */
+ delay_cycles(cycles_per_us);
+ }
+}
+
+/**
+ * \brief Delay loop to delay at least n number of milliseconds
+ *
+ * \param n Number of milliseconds to wait
+ */
+void delay_cycles_ms(
+ uint32_t n)
+{
+ while (n--) {
+ /* Devide up to blocks of 1ms */
+ delay_cycles(cycles_per_ms);
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.h Wed Jul 01 09:45:11 2015 +0100
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/**
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
+#ifndef CYCLE_COUNTER_H_INCLUDED
+#define CYCLE_COUNTER_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Convenience functions for busy-wait delay loops
+ *
+ * @{
+ */
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ * Delay program execution for at least the specified number of CPU cycles.
+ *
+ * \param n Number of cycles to delay
+ */
+static inline void delay_cycles(
+ const uint32_t n)
+{
+ if (n > 0) {
+ SysTick->LOAD = n;
+ SysTick->VAL = 0;
+
+ while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
+ };
+ }
+}
+
+void delay_cycles_us(uint32_t n);
+
+void delay_cycles_ms(uint32_t n);
+
+/**
+ * \brief Delay program execution for at least the specified number of microseconds.
+ *
+ * \param delay number of microseconds to wait
+ */
+#define cpu_delay_us(delay) delay_cycles_us(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of milliseconds.
+ *
+ * \param delay number of milliseconds to wait
+ */
+#define cpu_delay_ms(delay) delay_cycles_ms(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of seconds.
+ *
+ * \param delay number of seconds to wait
+ */
+#define cpu_delay_s(delay) delay_cycles_ms(1000 * delay)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CYCLE_COUNTER_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/config/conf_board.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,50 @@ +/** + * \file + * + * \brief SAM R21 Xplained Pro board configuration. + * + * Copyright (c) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + +#ifndef CONF_BOARD_H_INCLUDED +#define CONF_BOARD_H_INCLUDED + +#endif /* CONF_BOARD_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/config/conf_clocks.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,186 @@ +/** + * \file + * + * \brief SAM R21 Clock configuration + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ +#include <clock.h> + +#ifndef CONF_CLOCKS_H_INCLUDED +# define CONF_CLOCKS_H_INCLUDED + +/* System clock bus configuration */ +# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false +# define CONF_CLOCK_FLASH_WAIT_STATES 0 +# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 +# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 +# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 + +/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */ +# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1 +# define CONF_CLOCK_OSC8M_ON_DEMAND true +# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ +# define CONF_CLOCK_XOSC_ENABLE false +# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL +# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL +# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 +# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true +# define CONF_CLOCK_XOSC_ON_DEMAND true +# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ +# define CONF_CLOCK_XOSC32K_ENABLE false +# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL +# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 +# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false +# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false +# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true +# define CONF_CLOCK_XOSC32K_ON_DEMAND true +# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ +# define CONF_CLOCK_OSC32K_ENABLE false +# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 +# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true +# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true +# define CONF_CLOCK_OSC32K_ON_DEMAND true +# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ +# define CONF_CLOCK_DFLL_ENABLE false +# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN +# define CONF_CLOCK_DFLL_ON_DEMAND false + +/* DFLL open loop mode configuration */ +# define CONF_CLOCK_DFLL_COARSE_VALUE (0x1f / 4) +# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4) + +/* DFLL closed loop mode configuration */ +# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 +# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR 6 +# define CONF_CLOCK_DFLL_QUICK_LOCK true +# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true +# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true +# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true +# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4) +# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4) + +/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ +# define CONF_CLOCK_DPLL_ENABLE false +# define CONF_CLOCK_DPLL_ON_DEMAND true +# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false +# define CONF_CLOCK_DPLL_LOCK_BYPASS false +# define CONF_CLOCK_DPLL_WAKE_UP_FAST false +# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false + +# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_NO_TIMEOUT +# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0 +# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT + +# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 +# define CONF_CLOCK_DPLL_REFEREMCE_DIVIDER 1 +# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 + +/* Set this to true to configure the GCLK when running clocks_init. If set to + * false, none of the GCLK generators will be configured in clocks_init(). */ +# define CONF_CLOCK_CONFIGURE_GCLK true + +/* Configure GCLK generator 0 (Main Clock) */ +# define CONF_CLOCK_GCLK_0_ENABLE true +# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_0_PRESCALER 1 +# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false + +/* Configure GCLK generator 1 */ +# define CONF_CLOCK_GCLK_1_ENABLE false +# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_1_PRESCALER 1 +# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false + +/* Configure GCLK generator 2 (RTC) */ +# define CONF_CLOCK_GCLK_2_ENABLE false +# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K +# define CONF_CLOCK_GCLK_2_PRESCALER 32 +# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false + +/* Configure GCLK generator 3 */ +# define CONF_CLOCK_GCLK_3_ENABLE false +# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_3_PRESCALER 1 +# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false + +/* Configure GCLK generator 4 */ +# define CONF_CLOCK_GCLK_4_ENABLE false +# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_4_PRESCALER 1 +# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false + +/* Configure GCLK generator 5 */ +# define CONF_CLOCK_GCLK_5_ENABLE false +# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_5_PRESCALER 1 +# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false + +/* Configure GCLK generator 6 */ +# define CONF_CLOCK_GCLK_6_ENABLE false +# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_6_PRESCALER 1 +# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false + +/* Configure GCLK generator 7 */ +# define CONF_CLOCK_GCLK_7_ENABLE false +# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_7_PRESCALER 1 +# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false + +#endif /* CONF_CLOCKS_H_INCLUDED */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/config/conf_dma.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief SAM R21 Direct Memory Access Driver Configuration Header + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ +#ifndef CONF_DMA_H_INCLUDED +#define CONF_DMA_H_INCLUDED + +# define CONF_MAX_USED_CHANNEL_NUM 1 + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/config/conf_extint.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief SAM R21 External Interrupt Driver Configuration Header + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ +#ifndef CONF_EXTINT_H_INCLUDED +#define CONF_EXTINT_H_INCLUDED + +# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/config/conf_spi.h Wed Jul 01 09:45:11 2015 +0100 @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief SAM R21 SPI configuration + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/** +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ + + +#ifndef CONF_SPI_H_INCLUDED +# define CONF_SPI_H_INCLUDED + +# define CONF_SPI_MASTER_ENABLE true +# define CONF_SPI_SLAVE_ENABLE false +# define CONF_SPI_TIMEOUT 10000 + +#endif /* CONF_SPI_H_INCLUDED */ +
