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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Child:
592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 /**
mbed_official 579:53297373a894 2 * \file
mbed_official 579:53297373a894 3 *
mbed_official 579:53297373a894 4 * \brief Component description for DSU
mbed_official 579:53297373a894 5 *
mbed_official 579:53297373a894 6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
mbed_official 579:53297373a894 7 *
mbed_official 579:53297373a894 8 * \asf_license_start
mbed_official 579:53297373a894 9 *
mbed_official 579:53297373a894 10 * \page License
mbed_official 579:53297373a894 11 *
mbed_official 579:53297373a894 12 * Redistribution and use in source and binary forms, with or without
mbed_official 579:53297373a894 13 * modification, are permitted provided that the following conditions are met:
mbed_official 579:53297373a894 14 *
mbed_official 579:53297373a894 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 579:53297373a894 16 * this list of conditions and the following disclaimer.
mbed_official 579:53297373a894 17 *
mbed_official 579:53297373a894 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 579:53297373a894 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 579:53297373a894 20 * and/or other materials provided with the distribution.
mbed_official 579:53297373a894 21 *
mbed_official 579:53297373a894 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 579:53297373a894 23 * from this software without specific prior written permission.
mbed_official 579:53297373a894 24 *
mbed_official 579:53297373a894 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 579:53297373a894 26 * Atmel microcontroller product.
mbed_official 579:53297373a894 27 *
mbed_official 579:53297373a894 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 579:53297373a894 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 579:53297373a894 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 579:53297373a894 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 579:53297373a894 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 579:53297373a894 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 579:53297373a894 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 579:53297373a894 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 579:53297373a894 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 579:53297373a894 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 579:53297373a894 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 579:53297373a894 39 *
mbed_official 579:53297373a894 40 * \asf_license_stop
mbed_official 579:53297373a894 41 *
mbed_official 579:53297373a894 42 */
mbed_official 579:53297373a894 43 /**
mbed_official 579:53297373a894 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 579:53297373a894 45 */
mbed_official 579:53297373a894 46
mbed_official 579:53297373a894 47 #ifndef _SAMD21_DSU_COMPONENT_
mbed_official 579:53297373a894 48 #define _SAMD21_DSU_COMPONENT_
mbed_official 579:53297373a894 49
mbed_official 579:53297373a894 50 /* ========================================================================== */
mbed_official 579:53297373a894 51 /** SOFTWARE API DEFINITION FOR DSU */
mbed_official 579:53297373a894 52 /* ========================================================================== */
mbed_official 579:53297373a894 53 /** \addtogroup SAMD21_DSU Device Service Unit */
mbed_official 579:53297373a894 54 /*@{*/
mbed_official 579:53297373a894 55
mbed_official 579:53297373a894 56 #define DSU_U2209
mbed_official 579:53297373a894 57 #define REV_DSU 0x200
mbed_official 579:53297373a894 58
mbed_official 579:53297373a894 59 /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
mbed_official 579:53297373a894 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 61 typedef union {
mbed_official 579:53297373a894 62 struct {
mbed_official 579:53297373a894 63 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 579:53297373a894 64 uint8_t :1; /*!< bit: 1 Reserved */
mbed_official 579:53297373a894 65 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
mbed_official 579:53297373a894 66 uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
mbed_official 579:53297373a894 67 uint8_t CE:1; /*!< bit: 4 Chip Erase */
mbed_official 579:53297373a894 68 uint8_t :3; /*!< bit: 5.. 7 Reserved */
mbed_official 579:53297373a894 69 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 70 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 71 } DSU_CTRL_Type;
mbed_official 579:53297373a894 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 73
mbed_official 579:53297373a894 74 #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
mbed_official 579:53297373a894 75 #define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */
mbed_official 579:53297373a894 76
mbed_official 579:53297373a894 77 #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
mbed_official 579:53297373a894 78 #define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos)
mbed_official 579:53297373a894 79 #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
mbed_official 579:53297373a894 80 #define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos)
mbed_official 579:53297373a894 81 #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
mbed_official 579:53297373a894 82 #define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos)
mbed_official 579:53297373a894 83 #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
mbed_official 579:53297373a894 84 #define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos)
mbed_official 579:53297373a894 85 #define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */
mbed_official 579:53297373a894 86
mbed_official 579:53297373a894 87 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
mbed_official 579:53297373a894 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 89 typedef union {
mbed_official 579:53297373a894 90 struct {
mbed_official 579:53297373a894 91 uint8_t DONE:1; /*!< bit: 0 Done */
mbed_official 579:53297373a894 92 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
mbed_official 579:53297373a894 93 uint8_t BERR:1; /*!< bit: 2 Bus Error */
mbed_official 579:53297373a894 94 uint8_t FAILURE:1; /*!< bit: 3 Failure */
mbed_official 579:53297373a894 95 uint8_t PERR:1; /*!< bit: 4 Protection Error */
mbed_official 579:53297373a894 96 uint8_t :3; /*!< bit: 5.. 7 Reserved */
mbed_official 579:53297373a894 97 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 98 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 99 } DSU_STATUSA_Type;
mbed_official 579:53297373a894 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 101
mbed_official 579:53297373a894 102 #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
mbed_official 579:53297373a894 103 #define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */
mbed_official 579:53297373a894 104
mbed_official 579:53297373a894 105 #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
mbed_official 579:53297373a894 106 #define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos)
mbed_official 579:53297373a894 107 #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
mbed_official 579:53297373a894 108 #define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
mbed_official 579:53297373a894 109 #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
mbed_official 579:53297373a894 110 #define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos)
mbed_official 579:53297373a894 111 #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
mbed_official 579:53297373a894 112 #define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos)
mbed_official 579:53297373a894 113 #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
mbed_official 579:53297373a894 114 #define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos)
mbed_official 579:53297373a894 115 #define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */
mbed_official 579:53297373a894 116
mbed_official 579:53297373a894 117 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
mbed_official 579:53297373a894 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 119 typedef union {
mbed_official 579:53297373a894 120 struct {
mbed_official 579:53297373a894 121 uint8_t PROT:1; /*!< bit: 0 Protected */
mbed_official 579:53297373a894 122 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
mbed_official 579:53297373a894 123 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
mbed_official 579:53297373a894 124 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
mbed_official 579:53297373a894 125 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
mbed_official 579:53297373a894 126 uint8_t :3; /*!< bit: 5.. 7 Reserved */
mbed_official 579:53297373a894 127 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 128 struct {
mbed_official 579:53297373a894 129 uint8_t :2; /*!< bit: 0.. 1 Reserved */
mbed_official 579:53297373a894 130 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
mbed_official 579:53297373a894 131 uint8_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 579:53297373a894 132 } vec; /*!< Structure used for vec access */
mbed_official 579:53297373a894 133 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 134 } DSU_STATUSB_Type;
mbed_official 579:53297373a894 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 136
mbed_official 579:53297373a894 137 #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
mbed_official 579:53297373a894 138 #define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */
mbed_official 579:53297373a894 139
mbed_official 579:53297373a894 140 #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
mbed_official 579:53297373a894 141 #define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos)
mbed_official 579:53297373a894 142 #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
mbed_official 579:53297373a894 143 #define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos)
mbed_official 579:53297373a894 144 #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
mbed_official 579:53297373a894 145 #define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
mbed_official 579:53297373a894 146 #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
mbed_official 579:53297373a894 147 #define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
mbed_official 579:53297373a894 148 #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
mbed_official 579:53297373a894 149 #define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
mbed_official 579:53297373a894 150 #define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
mbed_official 579:53297373a894 151 #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
mbed_official 579:53297373a894 152 #define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
mbed_official 579:53297373a894 153 #define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
mbed_official 579:53297373a894 154
mbed_official 579:53297373a894 155 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
mbed_official 579:53297373a894 156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 157 typedef union {
mbed_official 579:53297373a894 158 struct {
mbed_official 579:53297373a894 159 uint32_t :2; /*!< bit: 0.. 1 Reserved */
mbed_official 579:53297373a894 160 uint32_t ADDR:30; /*!< bit: 2..31 Address */
mbed_official 579:53297373a894 161 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 162 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 163 } DSU_ADDR_Type;
mbed_official 579:53297373a894 164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 165
mbed_official 579:53297373a894 166 #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
mbed_official 579:53297373a894 167 #define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
mbed_official 579:53297373a894 168
mbed_official 579:53297373a894 169 #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
mbed_official 579:53297373a894 170 #define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
mbed_official 579:53297373a894 171 #define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
mbed_official 579:53297373a894 172 #define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
mbed_official 579:53297373a894 173
mbed_official 579:53297373a894 174 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
mbed_official 579:53297373a894 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 176 typedef union {
mbed_official 579:53297373a894 177 struct {
mbed_official 579:53297373a894 178 uint32_t :2; /*!< bit: 0.. 1 Reserved */
mbed_official 579:53297373a894 179 uint32_t LENGTH:30; /*!< bit: 2..31 Length */
mbed_official 579:53297373a894 180 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 181 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 182 } DSU_LENGTH_Type;
mbed_official 579:53297373a894 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 184
mbed_official 579:53297373a894 185 #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
mbed_official 579:53297373a894 186 #define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
mbed_official 579:53297373a894 187
mbed_official 579:53297373a894 188 #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
mbed_official 579:53297373a894 189 #define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
mbed_official 579:53297373a894 190 #define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
mbed_official 579:53297373a894 191 #define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
mbed_official 579:53297373a894 192
mbed_official 579:53297373a894 193 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
mbed_official 579:53297373a894 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 195 typedef union {
mbed_official 579:53297373a894 196 struct {
mbed_official 579:53297373a894 197 uint32_t DATA:32; /*!< bit: 0..31 Data */
mbed_official 579:53297373a894 198 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 199 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 200 } DSU_DATA_Type;
mbed_official 579:53297373a894 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 202
mbed_official 579:53297373a894 203 #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
mbed_official 579:53297373a894 204 #define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
mbed_official 579:53297373a894 205
mbed_official 579:53297373a894 206 #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
mbed_official 579:53297373a894 207 #define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
mbed_official 579:53297373a894 208 #define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
mbed_official 579:53297373a894 209 #define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
mbed_official 579:53297373a894 210
mbed_official 579:53297373a894 211 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
mbed_official 579:53297373a894 212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 213 typedef union {
mbed_official 579:53297373a894 214 struct {
mbed_official 579:53297373a894 215 uint32_t DATA:32; /*!< bit: 0..31 Data */
mbed_official 579:53297373a894 216 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 217 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 218 } DSU_DCC_Type;
mbed_official 579:53297373a894 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 220
mbed_official 579:53297373a894 221 #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
mbed_official 579:53297373a894 222 #define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
mbed_official 579:53297373a894 223
mbed_official 579:53297373a894 224 #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
mbed_official 579:53297373a894 225 #define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
mbed_official 579:53297373a894 226 #define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
mbed_official 579:53297373a894 227 #define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
mbed_official 579:53297373a894 228
mbed_official 579:53297373a894 229 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
mbed_official 579:53297373a894 230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 231 typedef union {
mbed_official 579:53297373a894 232 struct {
mbed_official 579:53297373a894 233 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
mbed_official 579:53297373a894 234 uint32_t REVISION:4; /*!< bit: 8..11 Revision */
mbed_official 579:53297373a894 235 uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
mbed_official 579:53297373a894 236 uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
mbed_official 579:53297373a894 237 uint32_t :1; /*!< bit: 22 Reserved */
mbed_official 579:53297373a894 238 uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
mbed_official 579:53297373a894 239 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
mbed_official 579:53297373a894 240 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 241 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 242 } DSU_DID_Type;
mbed_official 579:53297373a894 243 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 244
mbed_official 579:53297373a894 245 #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
mbed_official 579:53297373a894 246
mbed_official 579:53297373a894 247 #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
mbed_official 579:53297373a894 248 #define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
mbed_official 579:53297373a894 249 #define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
mbed_official 579:53297373a894 250 #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
mbed_official 579:53297373a894 251 #define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
mbed_official 579:53297373a894 252 #define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
mbed_official 579:53297373a894 253 #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
mbed_official 579:53297373a894 254 #define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
mbed_official 579:53297373a894 255 #define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
mbed_official 579:53297373a894 256 #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
mbed_official 579:53297373a894 257 #define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
mbed_official 579:53297373a894 258 #define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
mbed_official 579:53297373a894 259 #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
mbed_official 579:53297373a894 260 #define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
mbed_official 579:53297373a894 261 #define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
mbed_official 579:53297373a894 262 #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
mbed_official 579:53297373a894 263 #define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
mbed_official 579:53297373a894 264 #define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
mbed_official 579:53297373a894 265 #define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
mbed_official 579:53297373a894 266
mbed_official 579:53297373a894 267 /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
mbed_official 579:53297373a894 268 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 269 typedef union {
mbed_official 579:53297373a894 270 struct {
mbed_official 579:53297373a894 271 uint32_t EPRES:1; /*!< bit: 0 Entry Present */
mbed_official 579:53297373a894 272 uint32_t FMT:1; /*!< bit: 1 Format */
mbed_official 579:53297373a894 273 uint32_t :10; /*!< bit: 2..11 Reserved */
mbed_official 579:53297373a894 274 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
mbed_official 579:53297373a894 275 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 276 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 277 } DSU_ENTRY_Type;
mbed_official 579:53297373a894 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 279
mbed_official 579:53297373a894 280 #define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
mbed_official 579:53297373a894 281 #define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
mbed_official 579:53297373a894 282
mbed_official 579:53297373a894 283 #define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
mbed_official 579:53297373a894 284 #define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos)
mbed_official 579:53297373a894 285 #define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
mbed_official 579:53297373a894 286 #define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
mbed_official 579:53297373a894 287 #define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
mbed_official 579:53297373a894 288 #define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
mbed_official 579:53297373a894 289 #define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
mbed_official 579:53297373a894 290 #define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
mbed_official 579:53297373a894 291
mbed_official 579:53297373a894 292 /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
mbed_official 579:53297373a894 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 294 typedef union {
mbed_official 579:53297373a894 295 struct {
mbed_official 579:53297373a894 296 uint32_t END:32; /*!< bit: 0..31 End Marker */
mbed_official 579:53297373a894 297 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 298 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 299 } DSU_END_Type;
mbed_official 579:53297373a894 300 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 301
mbed_official 579:53297373a894 302 #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
mbed_official 579:53297373a894 303 #define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
mbed_official 579:53297373a894 304
mbed_official 579:53297373a894 305 #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
mbed_official 579:53297373a894 306 #define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
mbed_official 579:53297373a894 307 #define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
mbed_official 579:53297373a894 308 #define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
mbed_official 579:53297373a894 309
mbed_official 579:53297373a894 310 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
mbed_official 579:53297373a894 311 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 312 typedef union {
mbed_official 579:53297373a894 313 struct {
mbed_official 579:53297373a894 314 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
mbed_official 579:53297373a894 315 uint32_t :31; /*!< bit: 1..31 Reserved */
mbed_official 579:53297373a894 316 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 317 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 318 } DSU_MEMTYPE_Type;
mbed_official 579:53297373a894 319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 320
mbed_official 579:53297373a894 321 #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
mbed_official 579:53297373a894 322 #define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
mbed_official 579:53297373a894 323
mbed_official 579:53297373a894 324 #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
mbed_official 579:53297373a894 325 #define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
mbed_official 579:53297373a894 326 #define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
mbed_official 579:53297373a894 327
mbed_official 579:53297373a894 328 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
mbed_official 579:53297373a894 329 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 330 typedef union {
mbed_official 579:53297373a894 331 struct {
mbed_official 579:53297373a894 332 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
mbed_official 579:53297373a894 333 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
mbed_official 579:53297373a894 334 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 335 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 336 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 337 } DSU_PID4_Type;
mbed_official 579:53297373a894 338 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 339
mbed_official 579:53297373a894 340 #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
mbed_official 579:53297373a894 341 #define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
mbed_official 579:53297373a894 342
mbed_official 579:53297373a894 343 #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
mbed_official 579:53297373a894 344 #define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
mbed_official 579:53297373a894 345 #define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
mbed_official 579:53297373a894 346 #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
mbed_official 579:53297373a894 347 #define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
mbed_official 579:53297373a894 348 #define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
mbed_official 579:53297373a894 349 #define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
mbed_official 579:53297373a894 350
mbed_official 579:53297373a894 351 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
mbed_official 579:53297373a894 352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 353 typedef union {
mbed_official 579:53297373a894 354 struct {
mbed_official 579:53297373a894 355 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
mbed_official 579:53297373a894 356 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 357 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 358 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 359 } DSU_PID0_Type;
mbed_official 579:53297373a894 360 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 361
mbed_official 579:53297373a894 362 #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
mbed_official 579:53297373a894 363 #define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
mbed_official 579:53297373a894 364
mbed_official 579:53297373a894 365 #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
mbed_official 579:53297373a894 366 #define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
mbed_official 579:53297373a894 367 #define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
mbed_official 579:53297373a894 368 #define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
mbed_official 579:53297373a894 369
mbed_official 579:53297373a894 370 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
mbed_official 579:53297373a894 371 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 372 typedef union {
mbed_official 579:53297373a894 373 struct {
mbed_official 579:53297373a894 374 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
mbed_official 579:53297373a894 375 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
mbed_official 579:53297373a894 376 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 377 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 378 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 379 } DSU_PID1_Type;
mbed_official 579:53297373a894 380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 381
mbed_official 579:53297373a894 382 #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
mbed_official 579:53297373a894 383 #define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
mbed_official 579:53297373a894 384
mbed_official 579:53297373a894 385 #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
mbed_official 579:53297373a894 386 #define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
mbed_official 579:53297373a894 387 #define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
mbed_official 579:53297373a894 388 #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
mbed_official 579:53297373a894 389 #define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
mbed_official 579:53297373a894 390 #define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
mbed_official 579:53297373a894 391 #define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
mbed_official 579:53297373a894 392
mbed_official 579:53297373a894 393 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
mbed_official 579:53297373a894 394 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 395 typedef union {
mbed_official 579:53297373a894 396 struct {
mbed_official 579:53297373a894 397 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
mbed_official 579:53297373a894 398 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
mbed_official 579:53297373a894 399 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
mbed_official 579:53297373a894 400 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 401 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 402 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 403 } DSU_PID2_Type;
mbed_official 579:53297373a894 404 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 405
mbed_official 579:53297373a894 406 #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
mbed_official 579:53297373a894 407 #define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
mbed_official 579:53297373a894 408
mbed_official 579:53297373a894 409 #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
mbed_official 579:53297373a894 410 #define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
mbed_official 579:53297373a894 411 #define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
mbed_official 579:53297373a894 412 #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
mbed_official 579:53297373a894 413 #define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
mbed_official 579:53297373a894 414 #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
mbed_official 579:53297373a894 415 #define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
mbed_official 579:53297373a894 416 #define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
mbed_official 579:53297373a894 417 #define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
mbed_official 579:53297373a894 418
mbed_official 579:53297373a894 419 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
mbed_official 579:53297373a894 420 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 421 typedef union {
mbed_official 579:53297373a894 422 struct {
mbed_official 579:53297373a894 423 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
mbed_official 579:53297373a894 424 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
mbed_official 579:53297373a894 425 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 426 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 427 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 428 } DSU_PID3_Type;
mbed_official 579:53297373a894 429 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 430
mbed_official 579:53297373a894 431 #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
mbed_official 579:53297373a894 432 #define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
mbed_official 579:53297373a894 433
mbed_official 579:53297373a894 434 #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
mbed_official 579:53297373a894 435 #define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
mbed_official 579:53297373a894 436 #define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
mbed_official 579:53297373a894 437 #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
mbed_official 579:53297373a894 438 #define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
mbed_official 579:53297373a894 439 #define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
mbed_official 579:53297373a894 440 #define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
mbed_official 579:53297373a894 441
mbed_official 579:53297373a894 442 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
mbed_official 579:53297373a894 443 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 444 typedef union {
mbed_official 579:53297373a894 445 struct {
mbed_official 579:53297373a894 446 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
mbed_official 579:53297373a894 447 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 448 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 449 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 450 } DSU_CID0_Type;
mbed_official 579:53297373a894 451 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 452
mbed_official 579:53297373a894 453 #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
mbed_official 579:53297373a894 454 #define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
mbed_official 579:53297373a894 455
mbed_official 579:53297373a894 456 #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
mbed_official 579:53297373a894 457 #define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
mbed_official 579:53297373a894 458 #define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
mbed_official 579:53297373a894 459 #define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
mbed_official 579:53297373a894 460
mbed_official 579:53297373a894 461 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
mbed_official 579:53297373a894 462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 463 typedef union {
mbed_official 579:53297373a894 464 struct {
mbed_official 579:53297373a894 465 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
mbed_official 579:53297373a894 466 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
mbed_official 579:53297373a894 467 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 468 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 469 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 470 } DSU_CID1_Type;
mbed_official 579:53297373a894 471 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 472
mbed_official 579:53297373a894 473 #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
mbed_official 579:53297373a894 474 #define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
mbed_official 579:53297373a894 475
mbed_official 579:53297373a894 476 #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
mbed_official 579:53297373a894 477 #define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
mbed_official 579:53297373a894 478 #define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
mbed_official 579:53297373a894 479 #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
mbed_official 579:53297373a894 480 #define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
mbed_official 579:53297373a894 481 #define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
mbed_official 579:53297373a894 482 #define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
mbed_official 579:53297373a894 483
mbed_official 579:53297373a894 484 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
mbed_official 579:53297373a894 485 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 486 typedef union {
mbed_official 579:53297373a894 487 struct {
mbed_official 579:53297373a894 488 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
mbed_official 579:53297373a894 489 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 490 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 491 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 492 } DSU_CID2_Type;
mbed_official 579:53297373a894 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 494
mbed_official 579:53297373a894 495 #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
mbed_official 579:53297373a894 496 #define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
mbed_official 579:53297373a894 497
mbed_official 579:53297373a894 498 #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
mbed_official 579:53297373a894 499 #define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
mbed_official 579:53297373a894 500 #define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
mbed_official 579:53297373a894 501 #define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
mbed_official 579:53297373a894 502
mbed_official 579:53297373a894 503 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
mbed_official 579:53297373a894 504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 505 typedef union {
mbed_official 579:53297373a894 506 struct {
mbed_official 579:53297373a894 507 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
mbed_official 579:53297373a894 508 uint32_t :24; /*!< bit: 8..31 Reserved */
mbed_official 579:53297373a894 509 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 510 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 511 } DSU_CID3_Type;
mbed_official 579:53297373a894 512 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 513
mbed_official 579:53297373a894 514 #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
mbed_official 579:53297373a894 515 #define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
mbed_official 579:53297373a894 516
mbed_official 579:53297373a894 517 #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
mbed_official 579:53297373a894 518 #define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
mbed_official 579:53297373a894 519 #define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
mbed_official 579:53297373a894 520 #define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
mbed_official 579:53297373a894 521
mbed_official 579:53297373a894 522 /** \brief DSU hardware registers */
mbed_official 579:53297373a894 523 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 524 typedef struct {
mbed_official 579:53297373a894 525 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
mbed_official 579:53297373a894 526 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
mbed_official 579:53297373a894 527 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
mbed_official 579:53297373a894 528 RoReg8 Reserved1[0x1];
mbed_official 579:53297373a894 529 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
mbed_official 579:53297373a894 530 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
mbed_official 579:53297373a894 531 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
mbed_official 579:53297373a894 532 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
mbed_official 579:53297373a894 533 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
mbed_official 579:53297373a894 534 RoReg8 Reserved2[0xFE4];
mbed_official 579:53297373a894 535 __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
mbed_official 579:53297373a894 536 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
mbed_official 579:53297373a894 537 RoReg8 Reserved3[0xFC0];
mbed_official 579:53297373a894 538 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
mbed_official 579:53297373a894 539 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
mbed_official 579:53297373a894 540 RoReg8 Reserved4[0xC];
mbed_official 579:53297373a894 541 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
mbed_official 579:53297373a894 542 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
mbed_official 579:53297373a894 543 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
mbed_official 579:53297373a894 544 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
mbed_official 579:53297373a894 545 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
mbed_official 579:53297373a894 546 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
mbed_official 579:53297373a894 547 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
mbed_official 579:53297373a894 548 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
mbed_official 579:53297373a894 549 } Dsu;
mbed_official 579:53297373a894 550 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 551
mbed_official 579:53297373a894 552 /*@}*/
mbed_official 579:53297373a894 553
mbed_official 579:53297373a894 554 #endif /* _SAMD21_DSU_COMPONENT_ */