mbed official
mbed library sources
Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more
Superseded
This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.
Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.
If you are looking for a stable and tested release, please import one of the official mbed library releases:
Import librarymbed
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h@579:53297373a894, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Revision:
- 579:53297373a894
- Child:
- 592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | /** |
| mbed_official | 579:53297373a894 | 2 | * \file |
| mbed_official | 579:53297373a894 | 3 | * |
| mbed_official | 579:53297373a894 | 4 | * \brief Instance description for SYSCTRL |
| mbed_official | 579:53297373a894 | 5 | * |
| mbed_official | 579:53297373a894 | 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved. |
| mbed_official | 579:53297373a894 | 7 | * |
| mbed_official | 579:53297373a894 | 8 | * \asf_license_start |
| mbed_official | 579:53297373a894 | 9 | * |
| mbed_official | 579:53297373a894 | 10 | * \page License |
| mbed_official | 579:53297373a894 | 11 | * |
| mbed_official | 579:53297373a894 | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 579:53297373a894 | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 579:53297373a894 | 14 | * |
| mbed_official | 579:53297373a894 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 579:53297373a894 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 579:53297373a894 | 17 | * |
| mbed_official | 579:53297373a894 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 579:53297373a894 | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 579:53297373a894 | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 579:53297373a894 | 21 | * |
| mbed_official | 579:53297373a894 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| mbed_official | 579:53297373a894 | 23 | * from this software without specific prior written permission. |
| mbed_official | 579:53297373a894 | 24 | * |
| mbed_official | 579:53297373a894 | 25 | * 4. This software may only be redistributed and used in connection with an |
| mbed_official | 579:53297373a894 | 26 | * Atmel microcontroller product. |
| mbed_official | 579:53297373a894 | 27 | * |
| mbed_official | 579:53297373a894 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| mbed_official | 579:53297373a894 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| mbed_official | 579:53297373a894 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| mbed_official | 579:53297373a894 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| mbed_official | 579:53297373a894 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 579:53297373a894 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| mbed_official | 579:53297373a894 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| mbed_official | 579:53297373a894 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| mbed_official | 579:53297373a894 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| mbed_official | 579:53297373a894 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| mbed_official | 579:53297373a894 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 579:53297373a894 | 39 | * |
| mbed_official | 579:53297373a894 | 40 | * \asf_license_stop |
| mbed_official | 579:53297373a894 | 41 | * |
| mbed_official | 579:53297373a894 | 42 | */ |
| mbed_official | 579:53297373a894 | 43 | /** |
| mbed_official | 579:53297373a894 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
| mbed_official | 579:53297373a894 | 45 | */ |
| mbed_official | 579:53297373a894 | 46 | |
| mbed_official | 579:53297373a894 | 47 | #ifndef _SAMD21_SYSCTRL_INSTANCE_ |
| mbed_official | 579:53297373a894 | 48 | #define _SAMD21_SYSCTRL_INSTANCE_ |
| mbed_official | 579:53297373a894 | 49 | |
| mbed_official | 579:53297373a894 | 50 | /* ========== Register definition for SYSCTRL peripheral ========== */ |
| mbed_official | 579:53297373a894 | 51 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 52 | #define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 53 | #define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 54 | #define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 55 | #define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ |
| mbed_official | 579:53297373a894 | 56 | #define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ |
| mbed_official | 579:53297373a894 | 57 | #define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| mbed_official | 579:53297373a894 | 58 | #define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ |
| mbed_official | 579:53297373a894 | 59 | #define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| mbed_official | 579:53297373a894 | 60 | #define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ |
| mbed_official | 579:53297373a894 | 61 | #define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ |
| mbed_official | 579:53297373a894 | 62 | #define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ |
| mbed_official | 579:53297373a894 | 63 | #define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ |
| mbed_official | 579:53297373a894 | 64 | #define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ |
| mbed_official | 579:53297373a894 | 65 | #define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ |
| mbed_official | 579:53297373a894 | 66 | #define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ |
| mbed_official | 579:53297373a894 | 67 | #define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ |
| mbed_official | 579:53297373a894 | 68 | #define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ |
| mbed_official | 579:53297373a894 | 69 | #define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ |
| mbed_official | 579:53297373a894 | 70 | #define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ |
| mbed_official | 579:53297373a894 | 71 | #define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ |
| mbed_official | 579:53297373a894 | 72 | #else |
| mbed_official | 579:53297373a894 | 73 | #define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 74 | #define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 75 | #define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 76 | #define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ |
| mbed_official | 579:53297373a894 | 77 | #define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ |
| mbed_official | 579:53297373a894 | 78 | #define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| mbed_official | 579:53297373a894 | 79 | #define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ |
| mbed_official | 579:53297373a894 | 80 | #define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| mbed_official | 579:53297373a894 | 81 | #define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ |
| mbed_official | 579:53297373a894 | 82 | #define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ |
| mbed_official | 579:53297373a894 | 83 | #define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ |
| mbed_official | 579:53297373a894 | 84 | #define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ |
| mbed_official | 579:53297373a894 | 85 | #define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ |
| mbed_official | 579:53297373a894 | 86 | #define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ |
| mbed_official | 579:53297373a894 | 87 | #define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ |
| mbed_official | 579:53297373a894 | 88 | #define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ |
| mbed_official | 579:53297373a894 | 89 | #define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ |
| mbed_official | 579:53297373a894 | 90 | #define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ |
| mbed_official | 579:53297373a894 | 91 | #define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ |
| mbed_official | 579:53297373a894 | 92 | #define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ |
| mbed_official | 579:53297373a894 | 93 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 94 | |
| mbed_official | 579:53297373a894 | 95 | /* ========== Instance parameters for SYSCTRL peripheral ========== */ |
| mbed_official | 579:53297373a894 | 96 | #define SYSCTRL_BGAP_CALIB_MSB 11 |
| mbed_official | 579:53297373a894 | 97 | #define SYSCTRL_BOD33_CALIB_MSB 5 |
| mbed_official | 579:53297373a894 | 98 | #define SYSCTRL_DFLL48M_COARSE_MSB 5 |
| mbed_official | 579:53297373a894 | 99 | #define SYSCTRL_DFLL48M_FINE_MSB 9 |
| mbed_official | 579:53297373a894 | 100 | #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 |
| mbed_official | 579:53297373a894 | 101 | #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL |
| mbed_official | 579:53297373a894 | 102 | #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K |
| mbed_official | 579:53297373a894 | 103 | #define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 |
| mbed_official | 579:53297373a894 | 104 | #define SYSCTRL_POR33_ENTEST_MSB 1 |
| mbed_official | 579:53297373a894 | 105 | #define SYSCTRL_ULPVREF_DIVLEV_MSB 3 |
| mbed_official | 579:53297373a894 | 106 | #define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 |
| mbed_official | 579:53297373a894 | 107 | #define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 |
| mbed_official | 579:53297373a894 | 108 | #define SYSCTRL_VREF_CONTROL_MSB 48 |
| mbed_official | 579:53297373a894 | 109 | #define SYSCTRL_VREF_STATUS_MSB 7 |
| mbed_official | 579:53297373a894 | 110 | #define SYSCTRL_VREG_LEVEL_MSB 2 |
| mbed_official | 579:53297373a894 | 111 | #define SYSCTRL_BOD12_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 112 | #define SYSCTRL_BOD33_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 113 | #define SYSCTRL_DFLL48M_VERSION 0x301 |
| mbed_official | 579:53297373a894 | 114 | #define SYSCTRL_FDPLL_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 115 | #define SYSCTRL_OSCULP32K_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 116 | #define SYSCTRL_OSC8M_VERSION 0x120 |
| mbed_official | 579:53297373a894 | 117 | #define SYSCTRL_OSC32K_VERSION 0x1101 |
| mbed_official | 579:53297373a894 | 118 | #define SYSCTRL_VREF_VERSION 0x200 |
| mbed_official | 579:53297373a894 | 119 | #define SYSCTRL_VREG_VERSION 0x201 |
| mbed_official | 579:53297373a894 | 120 | #define SYSCTRL_XOSC_VERSION 0x1111 |
| mbed_official | 579:53297373a894 | 121 | #define SYSCTRL_XOSC32K_VERSION 0x1111 |
| mbed_official | 579:53297373a894 | 122 | |
| mbed_official | 579:53297373a894 | 123 | #endif /* _SAMD21_SYSCTRL_INSTANCE_ */ |