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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_SYSCTRL_INSTANCE_ |
| mbed_official | 579:53297373a894 | 2 | #define _SAMD21_SYSCTRL_INSTANCE_ |
| mbed_official | 579:53297373a894 | 3 | |
| mbed_official | 579:53297373a894 | 4 | /* ========== Register definition for SYSCTRL peripheral ========== */ |
| mbed_official | 579:53297373a894 | 5 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 6 | #define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 7 | #define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 8 | #define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 9 | #define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ |
| mbed_official | 579:53297373a894 | 10 | #define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ |
| mbed_official | 579:53297373a894 | 11 | #define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| mbed_official | 579:53297373a894 | 12 | #define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ |
| mbed_official | 579:53297373a894 | 13 | #define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| mbed_official | 579:53297373a894 | 14 | #define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ |
| mbed_official | 579:53297373a894 | 15 | #define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ |
| mbed_official | 579:53297373a894 | 16 | #define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ |
| mbed_official | 579:53297373a894 | 17 | #define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ |
| mbed_official | 579:53297373a894 | 18 | #define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ |
| mbed_official | 579:53297373a894 | 19 | #define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ |
| mbed_official | 579:53297373a894 | 20 | #define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ |
| mbed_official | 579:53297373a894 | 21 | #define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ |
| mbed_official | 579:53297373a894 | 22 | #define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ |
| mbed_official | 579:53297373a894 | 23 | #define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ |
| mbed_official | 579:53297373a894 | 24 | #define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ |
| mbed_official | 579:53297373a894 | 25 | #define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ |
| mbed_official | 579:53297373a894 | 26 | #else |
| mbed_official | 579:53297373a894 | 27 | #define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 28 | #define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 29 | #define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 30 | #define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ |
| mbed_official | 579:53297373a894 | 31 | #define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ |
| mbed_official | 579:53297373a894 | 32 | #define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| mbed_official | 579:53297373a894 | 33 | #define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ |
| mbed_official | 579:53297373a894 | 34 | #define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| mbed_official | 579:53297373a894 | 35 | #define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ |
| mbed_official | 579:53297373a894 | 36 | #define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ |
| mbed_official | 579:53297373a894 | 37 | #define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ |
| mbed_official | 579:53297373a894 | 38 | #define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ |
| mbed_official | 579:53297373a894 | 39 | #define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ |
| mbed_official | 579:53297373a894 | 40 | #define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ |
| mbed_official | 579:53297373a894 | 41 | #define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ |
| mbed_official | 579:53297373a894 | 42 | #define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ |
| mbed_official | 579:53297373a894 | 43 | #define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ |
| mbed_official | 579:53297373a894 | 44 | #define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ |
| mbed_official | 579:53297373a894 | 45 | #define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ |
| mbed_official | 579:53297373a894 | 46 | #define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ |
| mbed_official | 579:53297373a894 | 47 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 48 | |
| mbed_official | 579:53297373a894 | 49 | /* ========== Instance parameters for SYSCTRL peripheral ========== */ |
| mbed_official | 579:53297373a894 | 50 | #define SYSCTRL_BGAP_CALIB_MSB 11 |
| mbed_official | 579:53297373a894 | 51 | #define SYSCTRL_BOD33_CALIB_MSB 5 |
| mbed_official | 579:53297373a894 | 52 | #define SYSCTRL_DFLL48M_COARSE_MSB 5 |
| mbed_official | 579:53297373a894 | 53 | #define SYSCTRL_DFLL48M_FINE_MSB 9 |
| mbed_official | 579:53297373a894 | 54 | #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 |
| mbed_official | 579:53297373a894 | 55 | #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL |
| mbed_official | 579:53297373a894 | 56 | #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K |
| mbed_official | 579:53297373a894 | 57 | #define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 |
| mbed_official | 579:53297373a894 | 58 | #define SYSCTRL_POR33_ENTEST_MSB 1 |
| mbed_official | 579:53297373a894 | 59 | #define SYSCTRL_ULPVREF_DIVLEV_MSB 3 |
| mbed_official | 579:53297373a894 | 60 | #define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 |
| mbed_official | 579:53297373a894 | 61 | #define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 |
| mbed_official | 579:53297373a894 | 62 | #define SYSCTRL_VREF_CONTROL_MSB 48 |
| mbed_official | 579:53297373a894 | 63 | #define SYSCTRL_VREF_STATUS_MSB 7 |
| mbed_official | 579:53297373a894 | 64 | #define SYSCTRL_VREG_LEVEL_MSB 2 |
| mbed_official | 579:53297373a894 | 65 | #define SYSCTRL_BOD12_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 66 | #define SYSCTRL_BOD33_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 67 | #define SYSCTRL_DFLL48M_VERSION 0x301 |
| mbed_official | 579:53297373a894 | 68 | #define SYSCTRL_FDPLL_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 69 | #define SYSCTRL_OSCULP32K_VERSION 0x111 |
| mbed_official | 579:53297373a894 | 70 | #define SYSCTRL_OSC8M_VERSION 0x120 |
| mbed_official | 579:53297373a894 | 71 | #define SYSCTRL_OSC32K_VERSION 0x1101 |
| mbed_official | 579:53297373a894 | 72 | #define SYSCTRL_VREF_VERSION 0x200 |
| mbed_official | 579:53297373a894 | 73 | #define SYSCTRL_VREG_VERSION 0x201 |
| mbed_official | 579:53297373a894 | 74 | #define SYSCTRL_XOSC_VERSION 0x1111 |
| mbed_official | 579:53297373a894 | 75 | #define SYSCTRL_XOSC32K_VERSION 0x1111 |
| mbed_official | 579:53297373a894 | 76 | |
| mbed_official | 579:53297373a894 | 77 | #endif /* _SAMD21_SYSCTRL_INSTANCE_ */ |
