Test application for getting the Nucleo F0 30 board to work with Evan's prototype LED board.
Dependencies: mbed
main.cpp@5:9a662dec2ddb, 2014-08-05 (annotated)
- Committer:
- bgrissom
- Date:
- Tue Aug 05 23:53:59 2014 +0000
- Revision:
- 5:9a662dec2ddb
- Parent:
- 4:4eeacb39a417
- Child:
- 6:e4da8955cf65
With Red, Blue, and Green LEDs working on the 18 X 18 (20x20 pixel pitch) board.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bgrissom | 1:256d7a2f8391 | 1 | #include "mbed.h" |
bgrissom | 2:a57a5501152c | 2 | |
bgrissom | 2:a57a5501152c | 3 | #define OK (0) |
bgrissom | 2:a57a5501152c | 4 | #define ERROR (-1) |
bgrissom | 2:a57a5501152c | 5 | |
bgrissom | 5:9a662dec2ddb | 6 | #define PIN_41 PB_5 |
bgrissom | 5:9a662dec2ddb | 7 | #define PIN_46 PB_9 |
bgrissom | 5:9a662dec2ddb | 8 | #define PIN_32 PA_11 |
bgrissom | 5:9a662dec2ddb | 9 | #define PIN_20 PB_2 |
bgrissom | 5:9a662dec2ddb | 10 | #define HEX_ONE_THOUSAND (0x03E8) |
bgrissom | 5:9a662dec2ddb | 11 | |
bgrissom | 5:9a662dec2ddb | 12 | DigitalOut ENA(PIN_41); |
bgrissom | 5:9a662dec2ddb | 13 | DigitalOut ENB(PIN_46); |
bgrissom | 5:9a662dec2ddb | 14 | DigitalOut ENC(PIN_32); |
bgrissom | 5:9a662dec2ddb | 15 | DigitalOut EnSclk(PIN_20); |
bgrissom | 5:9a662dec2ddb | 16 | |
bgrissom | 5:9a662dec2ddb | 17 | |
bgrissom | 2:a57a5501152c | 18 | // Forward Declarations |
bgrissom | 2:a57a5501152c | 19 | void pwmout_period_ns(pwmout_t* obj, int us); |
bgrissom | 2:a57a5501152c | 20 | int cmd_S0(uint16_t value); |
bgrissom | 2:a57a5501152c | 21 | void cmd_S1(void); |
bgrissom | 2:a57a5501152c | 22 | |
bgrissom | 3:6f12c437ab88 | 23 | // Globals |
bgrissom | 2:a57a5501152c | 24 | bool gSpiMode = false; |
bgrissom | 2:a57a5501152c | 25 | SPI* gSpiPtr = NULL; |
bgrissom | 5:9a662dec2ddb | 26 | DigitalOut gbbTRANS(PA_4); // Global bit bang TRANS (data) line |
bgrissom | 5:9a662dec2ddb | 27 | const int SCLK_ENABLED = 0; |
bgrissom | 3:6f12c437ab88 | 28 | |
bgrissom | 2:a57a5501152c | 29 | |
bgrissom | 1:256d7a2f8391 | 30 | int main() { |
bgrissom | 5:9a662dec2ddb | 31 | ENA = 1; |
bgrissom | 5:9a662dec2ddb | 32 | ENB = 1; |
bgrissom | 5:9a662dec2ddb | 33 | ENC = 1; |
bgrissom | 5:9a662dec2ddb | 34 | EnSclk = SCLK_ENABLED; |
bgrissom | 5:9a662dec2ddb | 35 | |
bgrissom | 5:9a662dec2ddb | 36 | |
bgrissom | 1:256d7a2f8391 | 37 | // NOTE: 24MHz is half the 48MHz clock rate. The PWM registers |
bgrissom | 1:256d7a2f8391 | 38 | // seem to only allow 24MHz at this point, so I'm matching |
bgrissom | 1:256d7a2f8391 | 39 | // the SPI bus speed to be the same. |
bgrissom | 1:256d7a2f8391 | 40 | // |
bgrissom | 1:256d7a2f8391 | 41 | // 1/24MHz => 1/(24*10^6) => 41.6*10^-9 second period, |
bgrissom | 1:256d7a2f8391 | 42 | // which means 41.6ns period and 20.8ns pulse width at |
bgrissom | 1:256d7a2f8391 | 43 | // 50% duty cycle (which seems to be right for the SPI clock |
bgrissom | 1:256d7a2f8391 | 44 | // line as well as a reasonable choice for the PWM line). |
bgrissom | 0:b0f98b83cb07 | 45 | |
bgrissom | 3:6f12c437ab88 | 46 | // BAG ORIG: gbbTRANS = 1; // Start with TRANS high. It acts like a SPI slave select |
bgrissom | 3:6f12c437ab88 | 47 | // that is active-low. |
bgrissom | 3:6f12c437ab88 | 48 | gbbTRANS = 0; |
bgrissom | 0:b0f98b83cb07 | 49 | |
bgrissom | 3:6f12c437ab88 | 50 | // PWMCLK |
bgrissom | 2:a57a5501152c | 51 | pwmout_t outs; |
bgrissom | 5:9a662dec2ddb | 52 | pwmout_init(&outs, PB_4); |
bgrissom | 5:9a662dec2ddb | 53 | //pwmout_period_ns(&outs, 2); // 24 MHz (not very clean on the scope) |
bgrissom | 4:4eeacb39a417 | 54 | // pwmout_period_ns(&outs, 40); // 1.2 MHz on the scope |
bgrissom | 5:9a662dec2ddb | 55 | pwmout_period_us(&outs, 2); // 1.2 MHz on the scope |
bgrissom | 2:a57a5501152c | 56 | pwmout_write(&outs, 0.5f); |
bgrissom | 2:a57a5501152c | 57 | |
bgrissom | 2:a57a5501152c | 58 | int ret = OK; // Return value |
bgrissom | 2:a57a5501152c | 59 | int i = 0; |
bgrissom | 2:a57a5501152c | 60 | |
bgrissom | 4:4eeacb39a417 | 61 | printf("17:10\n"); |
bgrissom | 2:a57a5501152c | 62 | |
bgrissom | 5:9a662dec2ddb | 63 | //while (1) { |
bgrissom | 5:9a662dec2ddb | 64 | for (i=0; i<400; i++) { |
bgrissom | 5:9a662dec2ddb | 65 | ret = cmd_S0(0x0900); |
bgrissom | 3:6f12c437ab88 | 66 | // ORIG: ret = cmd_S0(0xFFFF); |
bgrissom | 2:a57a5501152c | 67 | if (ret != OK) { |
bgrissom | 2:a57a5501152c | 68 | printf("ERROR cmd_S0()\n"); |
bgrissom | 2:a57a5501152c | 69 | return ERROR; |
bgrissom | 2:a57a5501152c | 70 | } |
bgrissom | 2:a57a5501152c | 71 | } |
bgrissom | 2:a57a5501152c | 72 | cmd_S1(); |
bgrissom | 5:9a662dec2ddb | 73 | //} |
bgrissom | 2:a57a5501152c | 74 | } |
bgrissom | 0:b0f98b83cb07 | 75 | |
bgrissom | 2:a57a5501152c | 76 | |
bgrissom | 0:b0f98b83cb07 | 77 | |
bgrissom | 2:a57a5501152c | 78 | // S0 Command: |
bgrissom | 2:a57a5501152c | 79 | // Needs only SCK and SIN (which are SPI_SCK and SPI_MOSI respectively). |
bgrissom | 2:a57a5501152c | 80 | // This is because TRANS can be 0 for this command according to the datasheet. |
bgrissom | 2:a57a5501152c | 81 | int cmd_S0(uint16_t value) { |
bgrissom | 2:a57a5501152c | 82 | // Command S0 and S1 share the same clock line, so we need to be |
bgrissom | 2:a57a5501152c | 83 | // careful which mode we are in. This avoids re-initializing these |
bgrissom | 2:a57a5501152c | 84 | // pins if we are already in SPI mode. |
bgrissom | 2:a57a5501152c | 85 | // WARNING: Re-initializing every time makes the MOSI line dirty and |
bgrissom | 2:a57a5501152c | 86 | // is wasteful for the CPU. |
bgrissom | 2:a57a5501152c | 87 | if ( gSpiMode == false && |
bgrissom | 2:a57a5501152c | 88 | gSpiPtr == NULL) |
bgrissom | 2:a57a5501152c | 89 | { |
bgrissom | 2:a57a5501152c | 90 | // We are not using MISO, this is a one-way bus |
bgrissom | 2:a57a5501152c | 91 | gSpiPtr = new SPI(SPI_MOSI, NC, SPI_SCK); |
bgrissom | 1:256d7a2f8391 | 92 | |
bgrissom | 2:a57a5501152c | 93 | if (gSpiPtr == NULL) { |
bgrissom | 2:a57a5501152c | 94 | printf("ERROR: Could not allocate SPI\n"); |
bgrissom | 2:a57a5501152c | 95 | return ERROR; |
bgrissom | 2:a57a5501152c | 96 | } |
bgrissom | 1:256d7a2f8391 | 97 | |
bgrissom | 2:a57a5501152c | 98 | // Note: Polarity and phase are both 0 for the TC62D723FNG |
bgrissom | 2:a57a5501152c | 99 | // For a graphical reminder on polarity and phase, visit: |
bgrissom | 2:a57a5501152c | 100 | // http://www.eetimes.com/document.asp?doc_id=1272534 |
bgrissom | 2:a57a5501152c | 101 | gSpiPtr->format(16, 0); |
bgrissom | 4:4eeacb39a417 | 102 | // gSpiPtr->frequency(1000000); // 1.5 MHz on the scope |
bgrissom | 3:6f12c437ab88 | 103 | gSpiPtr->frequency(24000000); // 24 MHz |
bgrissom | 2:a57a5501152c | 104 | gSpiMode = true; |
bgrissom | 2:a57a5501152c | 105 | } |
bgrissom | 3:6f12c437ab88 | 106 | gbbTRANS = 0; // Like an SPI slave select |
bgrissom | 2:a57a5501152c | 107 | gSpiPtr->write(value); |
bgrissom | 3:6f12c437ab88 | 108 | gbbTRANS = 1; // Like an SPI slave select |
bgrissom | 4:4eeacb39a417 | 109 | // LONGTERM OPTIMIZATION: Evan suggests setting it |
bgrissom | 4:4eeacb39a417 | 110 | // wait_us(1); |
bgrissom | 4:4eeacb39a417 | 111 | // gbbTRANS = 0; // Set back low |
bgrissom | 2:a57a5501152c | 112 | return OK; |
bgrissom | 2:a57a5501152c | 113 | } |
bgrissom | 1:256d7a2f8391 | 114 | |
bgrissom | 0:b0f98b83cb07 | 115 | |
bgrissom | 0:b0f98b83cb07 | 116 | |
bgrissom | 2:a57a5501152c | 117 | void cmd_S1(void) { |
bgrissom | 2:a57a5501152c | 118 | int i = 0; |
bgrissom | 2:a57a5501152c | 119 | int j = 0; |
bgrissom | 2:a57a5501152c | 120 | |
bgrissom | 3:6f12c437ab88 | 121 | gbbTRANS = 0; // FIXME |
bgrissom | 3:6f12c437ab88 | 122 | |
bgrissom | 2:a57a5501152c | 123 | if ( gSpiMode == true && |
bgrissom | 2:a57a5501152c | 124 | gSpiPtr != NULL) |
bgrissom | 2:a57a5501152c | 125 | { |
bgrissom | 2:a57a5501152c | 126 | delete gSpiPtr; |
bgrissom | 2:a57a5501152c | 127 | gSpiPtr = NULL; |
bgrissom | 2:a57a5501152c | 128 | gSpiMode = false; |
bgrissom | 2:a57a5501152c | 129 | } |
bgrissom | 1:256d7a2f8391 | 130 | |
bgrissom | 2:a57a5501152c | 131 | DigitalOut bbSCK (D13); // bit bang clock |
bgrissom | 2:a57a5501152c | 132 | |
bgrissom | 3:6f12c437ab88 | 133 | bbSCK = 0; // Start off/low |
bgrissom | 3:6f12c437ab88 | 134 | gbbTRANS = 1; // Set high |
bgrissom | 2:a57a5501152c | 135 | |
bgrissom | 2:a57a5501152c | 136 | // Loop 6 times = 3 clock cycles |
bgrissom | 2:a57a5501152c | 137 | for (j=0; j<6; j++) { // Always use an even number here! |
bgrissom | 2:a57a5501152c | 138 | // The order of these two lines matter! |
bgrissom | 2:a57a5501152c | 139 | i == 0 ? i = 1 : i = 0; // Toggle i |
bgrissom | 2:a57a5501152c | 140 | i == 0 ? bbSCK = 0 : bbSCK = 1; // Set SCK to the same value as i |
bgrissom | 0:b0f98b83cb07 | 141 | } |
bgrissom | 3:6f12c437ab88 | 142 | gbbTRANS = 0; // Set low |
bgrissom | 2:a57a5501152c | 143 | } |
bgrissom | 2:a57a5501152c | 144 | |
bgrissom | 2:a57a5501152c | 145 | |
bgrissom | 5:9a662dec2ddb | 146 | /* USED FOR THE F030 BOARD |
bgrissom | 3:6f12c437ab88 | 147 | // This code is based off: |
bgrissom | 3:6f12c437ab88 | 148 | // mbed/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pwmout_api.c pwmout_period_us() |
bgrissom | 5:9a662dec2ddb | 149 | void pwmout_period_ns_NOT_USED(pwmout_t* obj, int us) { |
bgrissom | 3:6f12c437ab88 | 150 | TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); |
bgrissom | 3:6f12c437ab88 | 151 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; |
bgrissom | 3:6f12c437ab88 | 152 | float dc = pwmout_read(obj); |
bgrissom | 3:6f12c437ab88 | 153 | |
bgrissom | 3:6f12c437ab88 | 154 | TIM_Cmd(tim, DISABLE); |
bgrissom | 3:6f12c437ab88 | 155 | |
bgrissom | 3:6f12c437ab88 | 156 | obj->period = us; |
bgrissom | 3:6f12c437ab88 | 157 | |
bgrissom | 3:6f12c437ab88 | 158 | TIM_TimeBaseStructure.TIM_Period = obj->period - 1; |
bgrissom | 3:6f12c437ab88 | 159 | // Orig code: TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick |
bgrissom | 3:6f12c437ab88 | 160 | TIM_TimeBaseStructure.TIM_Prescaler = 0; // BAG 1 ns tick (?) |
bgrissom | 3:6f12c437ab88 | 161 | TIM_TimeBaseStructure.TIM_ClockDivision = 0; |
bgrissom | 3:6f12c437ab88 | 162 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; |
bgrissom | 3:6f12c437ab88 | 163 | TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure); |
bgrissom | 3:6f12c437ab88 | 164 | |
bgrissom | 3:6f12c437ab88 | 165 | // Set duty cycle again |
bgrissom | 3:6f12c437ab88 | 166 | pwmout_write(obj, dc); |
bgrissom | 3:6f12c437ab88 | 167 | |
bgrissom | 3:6f12c437ab88 | 168 | TIM_ARRPreloadConfig(tim, ENABLE); |
bgrissom | 3:6f12c437ab88 | 169 | |
bgrissom | 3:6f12c437ab88 | 170 | TIM_Cmd(tim, ENABLE); |
bgrissom | 3:6f12c437ab88 | 171 | } |
bgrissom | 5:9a662dec2ddb | 172 | */ |
bgrissom | 5:9a662dec2ddb | 173 | |
bgrissom | 5:9a662dec2ddb | 174 | |
bgrissom | 5:9a662dec2ddb | 175 | |
bgrissom | 5:9a662dec2ddb | 176 | /* HAVE NOT GOTTEN THIS WORKNIG FOR THE F072 |
bgrissom | 5:9a662dec2ddb | 177 | // This code is based off: |
bgrissom | 5:9a662dec2ddb | 178 | // mbed/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072* /pwmout_api.c pwmout_period_us() |
bgrissom | 5:9a662dec2ddb | 179 | void pwmout_period_ns(pwmout_t* obj, int us) { |
bgrissom | 5:9a662dec2ddb | 180 | TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); |
bgrissom | 5:9a662dec2ddb | 181 | |
bgrissom | 5:9a662dec2ddb | 182 | float dc = pwmout_read(obj); |
bgrissom | 5:9a662dec2ddb | 183 | |
bgrissom | 5:9a662dec2ddb | 184 | __HAL_TIM_DISABLE(&TimHandle); |
bgrissom | 5:9a662dec2ddb | 185 | |
bgrissom | 5:9a662dec2ddb | 186 | // Update the SystemCoreClock variable |
bgrissom | 5:9a662dec2ddb | 187 | SystemCoreClockUpdate(); |
bgrissom | 5:9a662dec2ddb | 188 | |
bgrissom | 5:9a662dec2ddb | 189 | TimHandle.Init.Period = us - 1; |
bgrissom | 5:9a662dec2ddb | 190 | // TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick |
bgrissom | 5:9a662dec2ddb | 191 | TimHandle.Init.Prescaler = 0; // BAG 1 ns tick (?) |
bgrissom | 5:9a662dec2ddb | 192 | TimHandle.Init.ClockDivision = 0; |
bgrissom | 5:9a662dec2ddb | 193 | TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; |
bgrissom | 5:9a662dec2ddb | 194 | HAL_TIM_PWM_Init(&TimHandle); |
bgrissom | 5:9a662dec2ddb | 195 | |
bgrissom | 5:9a662dec2ddb | 196 | // Set duty cycle again |
bgrissom | 5:9a662dec2ddb | 197 | pwmout_write(obj, dc); |
bgrissom | 5:9a662dec2ddb | 198 | |
bgrissom | 5:9a662dec2ddb | 199 | // Save for future use |
bgrissom | 5:9a662dec2ddb | 200 | obj->period = us; |
bgrissom | 5:9a662dec2ddb | 201 | |
bgrissom | 5:9a662dec2ddb | 202 | __HAL_TIM_ENABLE(&TimHandle); |
bgrissom | 5:9a662dec2ddb | 203 | } |
bgrissom | 5:9a662dec2ddb | 204 | */ |