Anthem / Mbed 2 deprecated brad_Nucleo_spi_master

Test application for getting the Nucleo F0 30 board to work with Evan's prototype LED board.

Dependencies:   mbed

main.cpp@2:a57a5501152c, 2014-07-11 (annotated)

Committer:
bgrissom
Date:
Fri Jul 11 15:37:30 2014 +0000
Revision:
2:a57a5501152c
Parent:
1:256d7a2f8391
Child:
3:6f12c437ab88
Full basic test suite with PWM line and SPI and S1/TRANS switching.  --Brad.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bgrissom 1:256d7a2f8391 1 #include "mbed.h"
bgrissom 2:a57a5501152c 2
bgrissom 2:a57a5501152c 3 #define OK (0)
bgrissom 2:a57a5501152c 4 #define ERROR (-1)
bgrissom 2:a57a5501152c 5
bgrissom 2:a57a5501152c 6 // Forward Declarations
bgrissom 2:a57a5501152c 7 void pwmout_period_ns(pwmout_t* obj, int us);
bgrissom 2:a57a5501152c 8 int cmd_S0(uint16_t value);
bgrissom 2:a57a5501152c 9 void cmd_S1(void);
bgrissom 2:a57a5501152c 10
bgrissom 2:a57a5501152c 11 bool gSpiMode = false;
bgrissom 2:a57a5501152c 12 SPI* gSpiPtr = NULL;
bgrissom 2:a57a5501152c 13
bgrissom 1:256d7a2f8391 14 int main() {
bgrissom 1:256d7a2f8391 15 // NOTE: 24MHz is half the 48MHz clock rate. The PWM registers
bgrissom 1:256d7a2f8391 16 // seem to only allow 24MHz at this point, so I'm matching
bgrissom 1:256d7a2f8391 17 // the SPI bus speed to be the same.
bgrissom 1:256d7a2f8391 18 //
bgrissom 1:256d7a2f8391 19 // 1/24MHz => 1/(24*10^6) => 41.6*10^-9 second period,
bgrissom 1:256d7a2f8391 20 // which means 41.6ns period and 20.8ns pulse width at
bgrissom 1:256d7a2f8391 21 // 50% duty cycle (which seems to be right for the SPI clock
bgrissom 1:256d7a2f8391 22 // line as well as a reasonable choice for the PWM line).
bgrissom 0:b0f98b83cb07 23
bgrissom 0:b0f98b83cb07 24
bgrissom 1:256d7a2f8391 25 /////////////////////////////////////////////////
bgrissom 2:a57a5501152c 26 // PWMCLK
bgrissom 1:256d7a2f8391 27 /////////////////////////////////////////////////
bgrissom 2:a57a5501152c 28 pwmout_t outs;
bgrissom 2:a57a5501152c 29 pwmout_init(&outs, D9);
bgrissom 2:a57a5501152c 30 //pwmout_period_ns(&outs, 2); // 24 MHz (not very clean on the scope)
bgrissom 2:a57a5501152c 31 pwmout_period_ns(&outs, 40); //
bgrissom 2:a57a5501152c 32 pwmout_write(&outs, 0.5f);
bgrissom 2:a57a5501152c 33
bgrissom 2:a57a5501152c 34
bgrissom 2:a57a5501152c 35 int ret = OK; // Return value
bgrissom 2:a57a5501152c 36 int i = 0;
bgrissom 2:a57a5501152c 37
bgrissom 2:a57a5501152c 38 printf("17:32\n");
bgrissom 2:a57a5501152c 39
bgrissom 2:a57a5501152c 40 while (1) {
bgrissom 2:a57a5501152c 41 //wait_ms(50);
bgrissom 2:a57a5501152c 42 for (i=0; i<16; i++) {
bgrissom 2:a57a5501152c 43 ret = cmd_S0(0x0003);
bgrissom 2:a57a5501152c 44 if (ret != OK) {
bgrissom 2:a57a5501152c 45 printf("ERROR cmd_S0()\n");
bgrissom 2:a57a5501152c 46 return ERROR;
bgrissom 2:a57a5501152c 47 }
bgrissom 2:a57a5501152c 48 }
bgrissom 2:a57a5501152c 49 cmd_S1();
bgrissom 2:a57a5501152c 50 }
bgrissom 2:a57a5501152c 51 }
bgrissom 0:b0f98b83cb07 52
bgrissom 2:a57a5501152c 53
bgrissom 2:a57a5501152c 54 // This code is based off:
bgrissom 2:a57a5501152c 55 // mbed/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pwmout_api.c pwmout_period_us()
bgrissom 2:a57a5501152c 56 void pwmout_period_ns(pwmout_t* obj, int us) {
bgrissom 2:a57a5501152c 57 TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm);
bgrissom 2:a57a5501152c 58 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
bgrissom 2:a57a5501152c 59 float dc = pwmout_read(obj);
bgrissom 2:a57a5501152c 60
bgrissom 2:a57a5501152c 61 TIM_Cmd(tim, DISABLE);
bgrissom 2:a57a5501152c 62
bgrissom 2:a57a5501152c 63 obj->period = us;
bgrissom 2:a57a5501152c 64
bgrissom 2:a57a5501152c 65 TIM_TimeBaseStructure.TIM_Period = obj->period - 1;
bgrissom 2:a57a5501152c 66 // Orig code: TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
bgrissom 2:a57a5501152c 67 TIM_TimeBaseStructure.TIM_Prescaler = 0; // BAG 1 ns tick (?)
bgrissom 2:a57a5501152c 68 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
bgrissom 2:a57a5501152c 69 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
bgrissom 2:a57a5501152c 70 TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure);
bgrissom 2:a57a5501152c 71
bgrissom 2:a57a5501152c 72 // Set duty cycle again
bgrissom 2:a57a5501152c 73 pwmout_write(obj, dc);
bgrissom 2:a57a5501152c 74
bgrissom 2:a57a5501152c 75 TIM_ARRPreloadConfig(tim, ENABLE);
bgrissom 2:a57a5501152c 76
bgrissom 2:a57a5501152c 77 TIM_Cmd(tim, ENABLE);
bgrissom 2:a57a5501152c 78 }
bgrissom 0:b0f98b83cb07 79
bgrissom 0:b0f98b83cb07 80
bgrissom 0:b0f98b83cb07 81
bgrissom 2:a57a5501152c 82 // S0 Command:
bgrissom 2:a57a5501152c 83 // Needs only SCK and SIN (which are SPI_SCK and SPI_MOSI respectively).
bgrissom 2:a57a5501152c 84 // This is because TRANS can be 0 for this command according to the datasheet.
bgrissom 2:a57a5501152c 85 int cmd_S0(uint16_t value) {
bgrissom 2:a57a5501152c 86 // Command S0 and S1 share the same clock line, so we need to be
bgrissom 2:a57a5501152c 87 // careful which mode we are in. This avoids re-initializing these
bgrissom 2:a57a5501152c 88 // pins if we are already in SPI mode.
bgrissom 2:a57a5501152c 89 // WARNING: Re-initializing every time makes the MOSI line dirty and
bgrissom 2:a57a5501152c 90 // is wasteful for the CPU.
bgrissom 2:a57a5501152c 91 if ( gSpiMode == false &&
bgrissom 2:a57a5501152c 92 gSpiPtr == NULL)
bgrissom 2:a57a5501152c 93 {
bgrissom 2:a57a5501152c 94 // We are not using MISO, this is a one-way bus
bgrissom 2:a57a5501152c 95 gSpiPtr = new SPI(SPI_MOSI, NC, SPI_SCK);
bgrissom 1:256d7a2f8391 96
bgrissom 2:a57a5501152c 97 if (gSpiPtr == NULL) {
bgrissom 2:a57a5501152c 98 printf("ERROR: Could not allocate SPI\n");
bgrissom 2:a57a5501152c 99 return ERROR;
bgrissom 2:a57a5501152c 100 }
bgrissom 1:256d7a2f8391 101
bgrissom 2:a57a5501152c 102 // Note: Polarity and phase are both 0 for the TC62D723FNG
bgrissom 2:a57a5501152c 103 // For a graphical reminder on polarity and phase, visit:
bgrissom 2:a57a5501152c 104 // http://www.eetimes.com/document.asp?doc_id=1272534
bgrissom 2:a57a5501152c 105 gSpiPtr->format(16, 0);
bgrissom 2:a57a5501152c 106 gSpiPtr->frequency(1000000); // 1 MHz
bgrissom 2:a57a5501152c 107 //gSpiPtr->frequency(24000000); // 24 MHz
bgrissom 2:a57a5501152c 108 gSpiMode = true;
bgrissom 2:a57a5501152c 109 }
bgrissom 2:a57a5501152c 110 gSpiPtr->write(value);
bgrissom 2:a57a5501152c 111 return OK;
bgrissom 2:a57a5501152c 112 }
bgrissom 1:256d7a2f8391 113
bgrissom 0:b0f98b83cb07 114
bgrissom 0:b0f98b83cb07 115
bgrissom 2:a57a5501152c 116 void cmd_S1(void) {
bgrissom 2:a57a5501152c 117 int i = 0;
bgrissom 2:a57a5501152c 118 int j = 0;
bgrissom 2:a57a5501152c 119
bgrissom 2:a57a5501152c 120 if ( gSpiMode == true &&
bgrissom 2:a57a5501152c 121 gSpiPtr != NULL)
bgrissom 2:a57a5501152c 122 {
bgrissom 2:a57a5501152c 123 delete gSpiPtr;
bgrissom 2:a57a5501152c 124 gSpiPtr = NULL;
bgrissom 2:a57a5501152c 125 gSpiMode = false;
bgrissom 2:a57a5501152c 126 }
bgrissom 1:256d7a2f8391 127
bgrissom 2:a57a5501152c 128 DigitalOut bbSCK (D13); // bit bang clock
bgrissom 2:a57a5501152c 129 DigitalOut bbTRANS(D8); // bit bang TRANS (data) line
bgrissom 2:a57a5501152c 130
bgrissom 2:a57a5501152c 131 bbSCK = 0; // Start off/low
bgrissom 2:a57a5501152c 132 bbTRANS = 1; // Set high
bgrissom 2:a57a5501152c 133
bgrissom 2:a57a5501152c 134 // Loop 6 times = 3 clock cycles
bgrissom 2:a57a5501152c 135 for (j=0; j<6; j++) { // Always use an even number here!
bgrissom 2:a57a5501152c 136 // The order of these two lines matter!
bgrissom 2:a57a5501152c 137 i == 0 ? i = 1 : i = 0; // Toggle i
bgrissom 2:a57a5501152c 138 i == 0 ? bbSCK = 0 : bbSCK = 1; // Set SCK to the same value as i
bgrissom 0:b0f98b83cb07 139 }
bgrissom 2:a57a5501152c 140 bbTRANS = 0; // Set low
bgrissom 2:a57a5501152c 141 }
bgrissom 2:a57a5501152c 142
bgrissom 2:a57a5501152c 143
bgrissom 2:a57a5501152c 144