Anthem / Mbed 2 deprecated brad_Nucleo_spi_master

Test application for getting the Nucleo F0 30 board to work with Evan's prototype LED board.

Dependencies:   mbed

main.cpp@1:256d7a2f8391, 2014-07-07 (annotated)

Committer:
bgrissom
Date:
Mon Jul 07 23:39:59 2014 +0000
Revision:
1:256d7a2f8391
Parent:
0:b0f98b83cb07
Child:
2:a57a5501152c
This should be how the LED driver interface should work, but this current version won't run because it doesn't like me reconfiguring the SPI bus to use PA_9 as MOSI.  --Brad.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bgrissom 1:256d7a2f8391 1 #include "mbed.h"
bgrissom 1:256d7a2f8391 2
bgrissom 1:256d7a2f8391 3 int main() {
bgrissom 1:256d7a2f8391 4 // NOTE: 24MHz is half the 48MHz clock rate. The PWM registers
bgrissom 1:256d7a2f8391 5 // seem to only allow 24MHz at this point, so I'm matching
bgrissom 1:256d7a2f8391 6 // the SPI bus speed to be the same.
bgrissom 1:256d7a2f8391 7 //
bgrissom 1:256d7a2f8391 8 // 1/24MHz => 1/(24*10^6) => 41.6*10^-9 second period,
bgrissom 1:256d7a2f8391 9 // which means 41.6ns period and 20.8ns pulse width at
bgrissom 1:256d7a2f8391 10 // 50% duty cycle (which seems to be right for the SPI clock
bgrissom 1:256d7a2f8391 11 // line as well as a reasonable choice for the PWM line).
bgrissom 0:b0f98b83cb07 12
bgrissom 0:b0f98b83cb07 13
bgrissom 1:256d7a2f8391 14 /////////////////////////////////////////////////
bgrissom 1:256d7a2f8391 15 // SPI SETUP
bgrissom 1:256d7a2f8391 16 /////////////////////////////////////////////////
bgrissom 1:256d7a2f8391 17 // We are not using MISO, this is a one-way bus
bgrissom 1:256d7a2f8391 18 //SPI device(SPI_MOSI, NC, SPI_SCK);
bgrissom 0:b0f98b83cb07 19
bgrissom 1:256d7a2f8391 20 // Note: Polarity and phase are both 0 for the TC62D723FNG
bgrissom 1:256d7a2f8391 21 // For a graphical reminder on polarity and phase, visit:
bgrissom 1:256d7a2f8391 22 // http://www.eetimes.com/document.asp?doc_id=1272534
bgrissom 1:256d7a2f8391 23 //
bgrissom 1:256d7a2f8391 24 //device.format(16, 0);
bgrissom 1:256d7a2f8391 25 //device.frequency(24000000); // 24 MHz
bgrissom 1:256d7a2f8391 26 //device.frequency(1000000); // 1 MHz
bgrissom 1:256d7a2f8391 27 /////////////////////////////////////////////////
bgrissom 0:b0f98b83cb07 28
bgrissom 0:b0f98b83cb07 29
bgrissom 0:b0f98b83cb07 30
bgrissom 1:256d7a2f8391 31 /////////////////////////////////////////////////
bgrissom 1:256d7a2f8391 32 // PWMCLK
bgrissom 1:256d7a2f8391 33 /////////////////////////////////////////////////
bgrissom 1:256d7a2f8391 34 //PwmOut pinPWMCLK(D9); // For Nucleo board, not for Redgarden board
bgrissom 1:256d7a2f8391 35 //pinPWMCLK.write(0.5f); // Set to 50% duty cycle for testing
bgrissom 1:256d7a2f8391 36
bgrissom 1:256d7a2f8391 37
bgrissom 1:256d7a2f8391 38 /////////////////////////////////////////////////
bgrissom 1:256d7a2f8391 39 // OTHER / DEBUG
bgrissom 1:256d7a2f8391 40 /////////////////////////////////////////////////
bgrissom 1:256d7a2f8391 41 /////////////////////////////////////////////////
bgrissom 1:256d7a2f8391 42
bgrissom 1:256d7a2f8391 43
bgrissom 0:b0f98b83cb07 44
bgrissom 0:b0f98b83cb07 45
bgrissom 1:256d7a2f8391 46 printf("17:22\n");
bgrissom 1:256d7a2f8391 47 //int i = 0;
bgrissom 0:b0f98b83cb07 48 while(1) {
bgrissom 1:256d7a2f8391 49 wait_us(50);
bgrissom 1:256d7a2f8391 50
bgrissom 1:256d7a2f8391 51 // S0 Command: Needs only SCK and SIN (which are SPI_SCK and SPI_MOSI respectively)
bgrissom 1:256d7a2f8391 52 // This is because TRANS can be 0 for this command according to the datasheet
bgrissom 1:256d7a2f8391 53 SPI data(SPI_MOSI, NC, SPI_SCK);
bgrissom 1:256d7a2f8391 54 data.format(16, 0);
bgrissom 1:256d7a2f8391 55 data.frequency(1000000); // 1 MHz
bgrissom 1:256d7a2f8391 56 data.write(0xFF);
bgrissom 1:256d7a2f8391 57
bgrissom 1:256d7a2f8391 58 // S1 Command: TRANS / "LATCH"
bgrissom 1:256d7a2f8391 59 // The S1 command doesn't use SIN, but TRANS needs to be on for exactly
bgrissom 1:256d7a2f8391 60 // three clock pulses. The easiest way to do this is re-configuring
bgrissom 1:256d7a2f8391 61 // the SPI bus to use the TRANS line as MOSI and sending 0x07. If this
bgrissom 1:256d7a2f8391 62 // doesn't work, we need to bitbang it.
bgrissom 1:256d7a2f8391 63 SPI latch(PA_9, NC, SPI_SCK);
bgrissom 1:256d7a2f8391 64 latch.format(16, 0);
bgrissom 1:256d7a2f8391 65 latch.frequency(1000000); // 1 MHz
bgrissom 1:256d7a2f8391 66 latch.write(0x07); // Three clock pulses
bgrissom 0:b0f98b83cb07 67 }
bgrissom 0:b0f98b83cb07 68 }