Test application for getting the Nucleo F0 30 board to work with Evan's prototype LED board.
Dependencies: mbed
main.cpp@4:4eeacb39a417, 2014-08-05 (annotated)
- Committer:
- bgrissom
- Date:
- Tue Aug 05 23:11:15 2014 +0000
- Revision:
- 4:4eeacb39a417
- Parent:
- 3:6f12c437ab88
- Child:
- 5:9a662dec2ddb
This was what I demo'd for Evan a few weeks ago. We are about to make some changes to get it to work on a full 18x18 board.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bgrissom | 1:256d7a2f8391 | 1 | #include "mbed.h" |
bgrissom | 2:a57a5501152c | 2 | |
bgrissom | 2:a57a5501152c | 3 | #define OK (0) |
bgrissom | 2:a57a5501152c | 4 | #define ERROR (-1) |
bgrissom | 2:a57a5501152c | 5 | |
bgrissom | 2:a57a5501152c | 6 | // Forward Declarations |
bgrissom | 2:a57a5501152c | 7 | void pwmout_period_ns(pwmout_t* obj, int us); |
bgrissom | 2:a57a5501152c | 8 | int cmd_S0(uint16_t value); |
bgrissom | 2:a57a5501152c | 9 | void cmd_S1(void); |
bgrissom | 2:a57a5501152c | 10 | |
bgrissom | 3:6f12c437ab88 | 11 | // Globals |
bgrissom | 2:a57a5501152c | 12 | bool gSpiMode = false; |
bgrissom | 2:a57a5501152c | 13 | SPI* gSpiPtr = NULL; |
bgrissom | 3:6f12c437ab88 | 14 | DigitalOut gbbTRANS(D8); // Global bit bang TRANS (data) line |
bgrissom | 3:6f12c437ab88 | 15 | |
bgrissom | 2:a57a5501152c | 16 | |
bgrissom | 1:256d7a2f8391 | 17 | int main() { |
bgrissom | 1:256d7a2f8391 | 18 | // NOTE: 24MHz is half the 48MHz clock rate. The PWM registers |
bgrissom | 1:256d7a2f8391 | 19 | // seem to only allow 24MHz at this point, so I'm matching |
bgrissom | 1:256d7a2f8391 | 20 | // the SPI bus speed to be the same. |
bgrissom | 1:256d7a2f8391 | 21 | // |
bgrissom | 1:256d7a2f8391 | 22 | // 1/24MHz => 1/(24*10^6) => 41.6*10^-9 second period, |
bgrissom | 1:256d7a2f8391 | 23 | // which means 41.6ns period and 20.8ns pulse width at |
bgrissom | 1:256d7a2f8391 | 24 | // 50% duty cycle (which seems to be right for the SPI clock |
bgrissom | 1:256d7a2f8391 | 25 | // line as well as a reasonable choice for the PWM line). |
bgrissom | 0:b0f98b83cb07 | 26 | |
bgrissom | 3:6f12c437ab88 | 27 | // BAG ORIG: gbbTRANS = 1; // Start with TRANS high. It acts like a SPI slave select |
bgrissom | 3:6f12c437ab88 | 28 | // that is active-low. |
bgrissom | 3:6f12c437ab88 | 29 | gbbTRANS = 0; |
bgrissom | 0:b0f98b83cb07 | 30 | |
bgrissom | 3:6f12c437ab88 | 31 | // PWMCLK |
bgrissom | 2:a57a5501152c | 32 | pwmout_t outs; |
bgrissom | 2:a57a5501152c | 33 | pwmout_init(&outs, D9); |
bgrissom | 3:6f12c437ab88 | 34 | pwmout_period_ns(&outs, 2); // 24 MHz (not very clean on the scope) |
bgrissom | 4:4eeacb39a417 | 35 | // pwmout_period_ns(&outs, 40); // 1.2 MHz on the scope |
bgrissom | 2:a57a5501152c | 36 | pwmout_write(&outs, 0.5f); |
bgrissom | 2:a57a5501152c | 37 | |
bgrissom | 2:a57a5501152c | 38 | int ret = OK; // Return value |
bgrissom | 2:a57a5501152c | 39 | int i = 0; |
bgrissom | 2:a57a5501152c | 40 | |
bgrissom | 4:4eeacb39a417 | 41 | printf("17:10\n"); |
bgrissom | 2:a57a5501152c | 42 | |
bgrissom | 2:a57a5501152c | 43 | while (1) { |
bgrissom | 2:a57a5501152c | 44 | for (i=0; i<16; i++) { |
bgrissom | 4:4eeacb39a417 | 45 | ret = cmd_S0(0xFFFF); |
bgrissom | 3:6f12c437ab88 | 46 | // ORIG: ret = cmd_S0(0xFFFF); |
bgrissom | 2:a57a5501152c | 47 | if (ret != OK) { |
bgrissom | 2:a57a5501152c | 48 | printf("ERROR cmd_S0()\n"); |
bgrissom | 2:a57a5501152c | 49 | return ERROR; |
bgrissom | 2:a57a5501152c | 50 | } |
bgrissom | 2:a57a5501152c | 51 | } |
bgrissom | 2:a57a5501152c | 52 | cmd_S1(); |
bgrissom | 2:a57a5501152c | 53 | } |
bgrissom | 2:a57a5501152c | 54 | } |
bgrissom | 0:b0f98b83cb07 | 55 | |
bgrissom | 2:a57a5501152c | 56 | |
bgrissom | 0:b0f98b83cb07 | 57 | |
bgrissom | 2:a57a5501152c | 58 | // S0 Command: |
bgrissom | 2:a57a5501152c | 59 | // Needs only SCK and SIN (which are SPI_SCK and SPI_MOSI respectively). |
bgrissom | 2:a57a5501152c | 60 | // This is because TRANS can be 0 for this command according to the datasheet. |
bgrissom | 2:a57a5501152c | 61 | int cmd_S0(uint16_t value) { |
bgrissom | 2:a57a5501152c | 62 | // Command S0 and S1 share the same clock line, so we need to be |
bgrissom | 2:a57a5501152c | 63 | // careful which mode we are in. This avoids re-initializing these |
bgrissom | 2:a57a5501152c | 64 | // pins if we are already in SPI mode. |
bgrissom | 2:a57a5501152c | 65 | // WARNING: Re-initializing every time makes the MOSI line dirty and |
bgrissom | 2:a57a5501152c | 66 | // is wasteful for the CPU. |
bgrissom | 2:a57a5501152c | 67 | if ( gSpiMode == false && |
bgrissom | 2:a57a5501152c | 68 | gSpiPtr == NULL) |
bgrissom | 2:a57a5501152c | 69 | { |
bgrissom | 2:a57a5501152c | 70 | // We are not using MISO, this is a one-way bus |
bgrissom | 2:a57a5501152c | 71 | gSpiPtr = new SPI(SPI_MOSI, NC, SPI_SCK); |
bgrissom | 1:256d7a2f8391 | 72 | |
bgrissom | 2:a57a5501152c | 73 | if (gSpiPtr == NULL) { |
bgrissom | 2:a57a5501152c | 74 | printf("ERROR: Could not allocate SPI\n"); |
bgrissom | 2:a57a5501152c | 75 | return ERROR; |
bgrissom | 2:a57a5501152c | 76 | } |
bgrissom | 1:256d7a2f8391 | 77 | |
bgrissom | 2:a57a5501152c | 78 | // Note: Polarity and phase are both 0 for the TC62D723FNG |
bgrissom | 2:a57a5501152c | 79 | // For a graphical reminder on polarity and phase, visit: |
bgrissom | 2:a57a5501152c | 80 | // http://www.eetimes.com/document.asp?doc_id=1272534 |
bgrissom | 2:a57a5501152c | 81 | gSpiPtr->format(16, 0); |
bgrissom | 4:4eeacb39a417 | 82 | // gSpiPtr->frequency(1000000); // 1.5 MHz on the scope |
bgrissom | 3:6f12c437ab88 | 83 | gSpiPtr->frequency(24000000); // 24 MHz |
bgrissom | 2:a57a5501152c | 84 | gSpiMode = true; |
bgrissom | 2:a57a5501152c | 85 | } |
bgrissom | 3:6f12c437ab88 | 86 | gbbTRANS = 0; // Like an SPI slave select |
bgrissom | 2:a57a5501152c | 87 | gSpiPtr->write(value); |
bgrissom | 3:6f12c437ab88 | 88 | gbbTRANS = 1; // Like an SPI slave select |
bgrissom | 4:4eeacb39a417 | 89 | // LONGTERM OPTIMIZATION: Evan suggests setting it |
bgrissom | 4:4eeacb39a417 | 90 | // wait_us(1); |
bgrissom | 4:4eeacb39a417 | 91 | // gbbTRANS = 0; // Set back low |
bgrissom | 2:a57a5501152c | 92 | return OK; |
bgrissom | 2:a57a5501152c | 93 | } |
bgrissom | 1:256d7a2f8391 | 94 | |
bgrissom | 0:b0f98b83cb07 | 95 | |
bgrissom | 0:b0f98b83cb07 | 96 | |
bgrissom | 2:a57a5501152c | 97 | void cmd_S1(void) { |
bgrissom | 2:a57a5501152c | 98 | int i = 0; |
bgrissom | 2:a57a5501152c | 99 | int j = 0; |
bgrissom | 2:a57a5501152c | 100 | |
bgrissom | 3:6f12c437ab88 | 101 | gbbTRANS = 0; // FIXME |
bgrissom | 3:6f12c437ab88 | 102 | |
bgrissom | 2:a57a5501152c | 103 | if ( gSpiMode == true && |
bgrissom | 2:a57a5501152c | 104 | gSpiPtr != NULL) |
bgrissom | 2:a57a5501152c | 105 | { |
bgrissom | 2:a57a5501152c | 106 | delete gSpiPtr; |
bgrissom | 2:a57a5501152c | 107 | gSpiPtr = NULL; |
bgrissom | 2:a57a5501152c | 108 | gSpiMode = false; |
bgrissom | 2:a57a5501152c | 109 | } |
bgrissom | 1:256d7a2f8391 | 110 | |
bgrissom | 2:a57a5501152c | 111 | DigitalOut bbSCK (D13); // bit bang clock |
bgrissom | 2:a57a5501152c | 112 | |
bgrissom | 3:6f12c437ab88 | 113 | bbSCK = 0; // Start off/low |
bgrissom | 3:6f12c437ab88 | 114 | gbbTRANS = 1; // Set high |
bgrissom | 2:a57a5501152c | 115 | |
bgrissom | 2:a57a5501152c | 116 | // Loop 6 times = 3 clock cycles |
bgrissom | 2:a57a5501152c | 117 | for (j=0; j<6; j++) { // Always use an even number here! |
bgrissom | 2:a57a5501152c | 118 | // The order of these two lines matter! |
bgrissom | 2:a57a5501152c | 119 | i == 0 ? i = 1 : i = 0; // Toggle i |
bgrissom | 2:a57a5501152c | 120 | i == 0 ? bbSCK = 0 : bbSCK = 1; // Set SCK to the same value as i |
bgrissom | 0:b0f98b83cb07 | 121 | } |
bgrissom | 3:6f12c437ab88 | 122 | gbbTRANS = 0; // Set low |
bgrissom | 2:a57a5501152c | 123 | } |
bgrissom | 2:a57a5501152c | 124 | |
bgrissom | 2:a57a5501152c | 125 | |
bgrissom | 2:a57a5501152c | 126 | |
bgrissom | 3:6f12c437ab88 | 127 | // This code is based off: |
bgrissom | 3:6f12c437ab88 | 128 | // mbed/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pwmout_api.c pwmout_period_us() |
bgrissom | 3:6f12c437ab88 | 129 | void pwmout_period_ns(pwmout_t* obj, int us) { |
bgrissom | 3:6f12c437ab88 | 130 | TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); |
bgrissom | 3:6f12c437ab88 | 131 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; |
bgrissom | 3:6f12c437ab88 | 132 | float dc = pwmout_read(obj); |
bgrissom | 3:6f12c437ab88 | 133 | |
bgrissom | 3:6f12c437ab88 | 134 | TIM_Cmd(tim, DISABLE); |
bgrissom | 3:6f12c437ab88 | 135 | |
bgrissom | 3:6f12c437ab88 | 136 | obj->period = us; |
bgrissom | 3:6f12c437ab88 | 137 | |
bgrissom | 3:6f12c437ab88 | 138 | TIM_TimeBaseStructure.TIM_Period = obj->period - 1; |
bgrissom | 3:6f12c437ab88 | 139 | // Orig code: TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick |
bgrissom | 3:6f12c437ab88 | 140 | TIM_TimeBaseStructure.TIM_Prescaler = 0; // BAG 1 ns tick (?) |
bgrissom | 3:6f12c437ab88 | 141 | TIM_TimeBaseStructure.TIM_ClockDivision = 0; |
bgrissom | 3:6f12c437ab88 | 142 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; |
bgrissom | 3:6f12c437ab88 | 143 | TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure); |
bgrissom | 3:6f12c437ab88 | 144 | |
bgrissom | 3:6f12c437ab88 | 145 | // Set duty cycle again |
bgrissom | 3:6f12c437ab88 | 146 | pwmout_write(obj, dc); |
bgrissom | 3:6f12c437ab88 | 147 | |
bgrissom | 3:6f12c437ab88 | 148 | TIM_ARRPreloadConfig(tim, ENABLE); |
bgrissom | 3:6f12c437ab88 | 149 | |
bgrissom | 3:6f12c437ab88 | 150 | TIM_Cmd(tim, ENABLE); |
bgrissom | 3:6f12c437ab88 | 151 | } |