lpcterm2 - semihost server example program

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Norimasa Okamoto / Mbed 2 deprecated lpcterm2

semihost server example program

Dependencies: SWD mbed USBLocalFileSystem BaseDAP USBDAP

/media/uploads/va009039/kl46z-lpc800-360x480.jpg

	LPCXpresso LPC11U68	LPCXpresso LPC1549	FRDM-KL46Z	EA LPC4088 QSB app-board	LPC1768 app-board	LPC810	LPC1114FN28
	server	server	server	server	server	client	client
SWDIO	D12	D12	D12	p25	p21	p4(P0_2)	p12
SWCLK	D10	D10	D10	p26	p22	p3(P0_3)	p3
nRESET *option	D6	D6	D6	p34	p30	p1(P0_5)	p23
GND	GND	GND	GND	p1	p1	p7	p22
3.3V	P3V3	P3V3	P3V3	p44	p40	p6	p21
flash write	SW2(P0_1)	SW3(P1_9)	SW1	p14 joystick center	p14 joystick center

client example:

Import program lpc810-semihost_helloworld

semihost client example program

Target2.cpp@6:5da6ad51a18f, 2013-09-23 (annotated)

Committer:: va009039
Date:: Mon Sep 23 00:31:45 2013 +0000
Revision:: 6:5da6ad51a18f
Parent:: 5:2774358f5e4f
Child:: 7:acfd2dbff157

validate the address of the breakpoint.

Who changed what in which revision?

User	Revision	Line number	New contents of line
va009039	6:5da6ad51a18f	1	// Target2.cpp 2013/9/17
va009039	0:27d35fa263b5	2	#include "Target2.h"
va009039	0:27d35fa263b5	3	#include "mydebug.h"
va009039	0:27d35fa263b5	4
va009039	3:d7a7cde0bfb8	5	#define SYSMEMREMAP 0x40048000
va009039	3:d7a7cde0bfb8	6
va009039	2:32e9437348ad	7	#define CoreDebug_BASE (0xE000EDF0UL)
va009039	2:32e9437348ad	8	#define DHCSR (CoreDebug_BASE+0)
va009039	2:32e9437348ad	9	#define DCRSR (CoreDebug_BASE+4)
va009039	2:32e9437348ad	10	#define DCRDR (CoreDebug_BASE+8)
va009039	2:32e9437348ad	11	#define DEMCR (CoreDebug_BASE+12)
va009039	2:32e9437348ad	12
va009039	2:32e9437348ad	13	#define NVIC_AIRCR 0xE000ED0C
va009039	0:27d35fa263b5	14
va009039	4:5e4107edcbdb	15	// FPB (breakpoint)
va009039	4:5e4107edcbdb	16	#define FP_CTRL (0xE0002000)
va009039	4:5e4107edcbdb	17	#define FP_CTRL_KEY (1 << 1)
va009039	4:5e4107edcbdb	18	#define FP_COMP0 (0xE0002008)
va009039	4:5e4107edcbdb	19
va009039	5:2774358f5e4f	20	Target2::Target2(PinName swdio, PinName swclk, PinName reset)
va009039	5:2774358f5e4f	21	: _swd(swdio, swclk, reset)
va009039	0:27d35fa263b5	22	{
va009039	0:27d35fa263b5	23	r0.setup(this, 0);
va009039	0:27d35fa263b5	24	r1.setup(this, 1);
va009039	0:27d35fa263b5	25	r2.setup(this, 2);
va009039	0:27d35fa263b5	26	r3.setup(this, 3);
va009039	0:27d35fa263b5	27	r4.setup(this, 4);
va009039	0:27d35fa263b5	28	r5.setup(this, 5);
va009039	0:27d35fa263b5	29	r6.setup(this, 6);
va009039	0:27d35fa263b5	30	r7.setup(this, 7);
va009039	0:27d35fa263b5	31	r8.setup(this, 8);
va009039	0:27d35fa263b5	32	r9.setup(this, 9);
va009039	0:27d35fa263b5	33	r10.setup(this, 10);
va009039	0:27d35fa263b5	34	r11.setup(this, 11);
va009039	0:27d35fa263b5	35	r12.setup(this, 12);
va009039	0:27d35fa263b5	36	sp.setup(this, 13);
va009039	0:27d35fa263b5	37	lr.setup(this, 14);
va009039	0:27d35fa263b5	38	pc.setup(this, 15);
va009039	0:27d35fa263b5	39	xpsr.setup(this, 16);
va009039	0:27d35fa263b5	40	}
va009039	0:27d35fa263b5	41
va009039	0:27d35fa263b5	42	bool Target2::setup()
va009039	0:27d35fa263b5	43	{
va009039	0:27d35fa263b5	44	_swd.Setup();
va009039	5:2774358f5e4f	45	JTAG2SWD();
va009039	0:27d35fa263b5	46
va009039	0:27d35fa263b5	47	uint32_t data;
va009039	0:27d35fa263b5	48	uint8_t ack = _swd.Transfer(DP_IDCODE, &data);
va009039	0:27d35fa263b5	49	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	50	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	51	return false;
va009039	0:27d35fa263b5	52	}
va009039	3:d7a7cde0bfb8	53	idcode = data;
va009039	3:d7a7cde0bfb8	54	//TEST_ASSERT(data == 0x0bb11477);
va009039	0:27d35fa263b5	55
va009039	0:27d35fa263b5	56	Abort();
va009039	0:27d35fa263b5	57
va009039	0:27d35fa263b5	58	data = 0x0;
va009039	0:27d35fa263b5	59	ack = _swd.Transfer(DP_SELECT, &data);
va009039	0:27d35fa263b5	60	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	61	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	62	return false;
va009039	0:27d35fa263b5	63	}
va009039	0:27d35fa263b5	64
va009039	0:27d35fa263b5	65	ack = _swd.Transfer(DP_RDBUFF, &data);
va009039	0:27d35fa263b5	66	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	67	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	68	return false;
va009039	0:27d35fa263b5	69	}
va009039	0:27d35fa263b5	70
va009039	0:27d35fa263b5	71	data = CSYSPWRUPREQ \| CDBGPWRUPREQ;
va009039	0:27d35fa263b5	72	ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039	0:27d35fa263b5	73	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	74	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	75	return false;
va009039	0:27d35fa263b5	76	}
va009039	0:27d35fa263b5	77
va009039	0:27d35fa263b5	78	ack = _swd.Transfer(DP_RDBUFF, &data);
va009039	0:27d35fa263b5	79	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	80	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	81	return false;
va009039	0:27d35fa263b5	82	}
va009039	0:27d35fa263b5	83
va009039	0:27d35fa263b5	84	ack = _swd.Transfer(DP_CTRL_STAT_R, &data);
va009039	0:27d35fa263b5	85	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	86	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	87	return false;
va009039	0:27d35fa263b5	88	}
va009039	0:27d35fa263b5	89	TEST_ASSERT(data == 0xf0000040);
va009039	0:27d35fa263b5	90
va009039	0:27d35fa263b5	91	data = CSYSPWRUPREQ \| CDBGPWRUPREQ \| 0x04000000;
va009039	0:27d35fa263b5	92	ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039	0:27d35fa263b5	93	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	94	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	95	return false;
va009039	0:27d35fa263b5	96	}
va009039	0:27d35fa263b5	97
va009039	0:27d35fa263b5	98	ack = _swd.Transfer(DP_RDBUFF, &data);
va009039	0:27d35fa263b5	99	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	100	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	101	return false;
va009039	0:27d35fa263b5	102	}
va009039	0:27d35fa263b5	103
va009039	0:27d35fa263b5	104	data = CSYSPWRUPREQ \| CDBGPWRUPREQ \| MASKLANE;
va009039	0:27d35fa263b5	105	ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039	0:27d35fa263b5	106	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	107	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	108	return false;
va009039	0:27d35fa263b5	109	}
va009039	0:27d35fa263b5	110
va009039	0:27d35fa263b5	111	ack = _swd.Transfer(DP_RDBUFF, &data);
va009039	0:27d35fa263b5	112	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	113	if (ack != SWD_OK) {
va009039	0:27d35fa263b5	114	return false;
va009039	0:27d35fa263b5	115	}
va009039	0:27d35fa263b5	116	return true;
va009039	0:27d35fa263b5	117	}
va009039	0:27d35fa263b5	118
va009039	6:5da6ad51a18f	119	void Target2::SWJClock(uint32_t clock_hz)
va009039	6:5da6ad51a18f	120	{
va009039	6:5da6ad51a18f	121	_swd.SWJClock(clock_hz);
va009039	6:5da6ad51a18f	122	}
va009039	6:5da6ad51a18f	123
va009039	5:2774358f5e4f	124	void Target2::JTAG2SWD()
va009039	5:2774358f5e4f	125	{
va009039	5:2774358f5e4f	126	const uint8_t data1[] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff};
va009039	5:2774358f5e4f	127	const uint8_t data2[] = {0x9e,0xe7};
va009039	5:2774358f5e4f	128	const uint8_t data3[] = {0x00};
va009039	5:2774358f5e4f	129	_swd.SWJSequence(sizeof(data1)*8, data1);
va009039	5:2774358f5e4f	130	_swd.SWJSequence(sizeof(data2)*8, data2);
va009039	5:2774358f5e4f	131	_swd.SWJSequence(sizeof(data1)*8, data1);
va009039	5:2774358f5e4f	132	_swd.SWJSequence(sizeof(data3)*8, data3);
va009039	5:2774358f5e4f	133	}
va009039	5:2774358f5e4f	134
va009039	3:d7a7cde0bfb8	135	void Target2::HardwareReset()
va009039	0:27d35fa263b5	136	{
va009039	3:d7a7cde0bfb8	137	_swd.SWJPins(0x00, 0x80); // nReset off
va009039	3:d7a7cde0bfb8	138	_swd.SWJPins(0x80, 0x80); // nReset on
va009039	3:d7a7cde0bfb8	139	}
va009039	3:d7a7cde0bfb8	140
va009039	3:d7a7cde0bfb8	141	void Target2::SoftwareReset()
va009039	3:d7a7cde0bfb8	142	{
va009039	3:d7a7cde0bfb8	143	writeMemory(NVIC_AIRCR, 0x05fa0004);
va009039	0:27d35fa263b5	144	}
va009039	0:27d35fa263b5	145
va009039	0:27d35fa263b5	146	uint32_t Target2::readMemory(uint32_t addr)
va009039	0:27d35fa263b5	147	{
va009039	0:27d35fa263b5	148	_setaddr(addr);
va009039	0:27d35fa263b5	149
va009039	0:27d35fa263b5	150	uint32_t data;
va009039	0:27d35fa263b5	151	uint8_t ack = _swd.Transfer(AP_DRW_R, &data); // dummy read
va009039	0:27d35fa263b5	152	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	153
va009039	0:27d35fa263b5	154	ack = _swd.Transfer(DP_RDBUFF, &data);
va009039	0:27d35fa263b5	155	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	156	return data;
va009039	0:27d35fa263b5	157	}
va009039	0:27d35fa263b5	158
va009039	0:27d35fa263b5	159	void Target2::readMemory(uint32_t addr, uint32_t* data, int count)
va009039	0:27d35fa263b5	160	{
va009039	0:27d35fa263b5	161	if (count == 0) {
va009039	0:27d35fa263b5	162	return;
va009039	0:27d35fa263b5	163	}
va009039	0:27d35fa263b5	164
va009039	0:27d35fa263b5	165	_setaddr(addr);
va009039	0:27d35fa263b5	166
va009039	0:27d35fa263b5	167	uint8_t ack = _swd.Transfer(AP_DRW_R, NULL); // dummy read
va009039	0:27d35fa263b5	168	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	169
va009039	0:27d35fa263b5	170	for(int i = 0; i < count-1; i++) {
va009039	0:27d35fa263b5	171	ack = _swd.Transfer(AP_DRW_R, data++);
va009039	0:27d35fa263b5	172	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	173	}
va009039	0:27d35fa263b5	174	ack = _swd.Transfer(DP_RDBUFF, data);
va009039	0:27d35fa263b5	175	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	176	}
va009039	0:27d35fa263b5	177
va009039	0:27d35fa263b5	178	void Target2::writeMemory(uint32_t addr, uint32_t data)
va009039	0:27d35fa263b5	179	{
va009039	0:27d35fa263b5	180	writeMemory(addr, &data, 1);
va009039	0:27d35fa263b5	181	}
va009039	0:27d35fa263b5	182
va009039	0:27d35fa263b5	183	void Target2::writeMemory(uint32_t addr, uint32_t* data, int count)
va009039	0:27d35fa263b5	184	{
va009039	0:27d35fa263b5	185	_setaddr(addr);
va009039	0:27d35fa263b5	186
va009039	0:27d35fa263b5	187	while(count-- > 0) {
va009039	0:27d35fa263b5	188	uint8_t ack = _swd.Transfer(AP_DRW_W, data);
va009039	0:27d35fa263b5	189	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	190	data++;
va009039	0:27d35fa263b5	191	}
va009039	0:27d35fa263b5	192	}
va009039	0:27d35fa263b5	193
va009039	1:eb30547ba84d	194	uint8_t Target2::readMemory8(uint32_t addr)
va009039	1:eb30547ba84d	195	{
va009039	1:eb30547ba84d	196	_setaddr8(addr);
va009039	1:eb30547ba84d	197
va009039	1:eb30547ba84d	198	uint32_t data32;
va009039	1:eb30547ba84d	199	uint8_t ack = _swd.Transfer(AP_DRW_R, &data32); // dummy read
va009039	1:eb30547ba84d	200	TEST_ASSERT(ack == SWD_OK);
va009039	1:eb30547ba84d	201
va009039	1:eb30547ba84d	202	ack = _swd.Transfer(DP_RDBUFF, &data32);
va009039	1:eb30547ba84d	203	TEST_ASSERT(ack == SWD_OK);
va009039	1:eb30547ba84d	204	return (data32 >> ((addr & 0x03) << 3)) & 0xff;
va009039	1:eb30547ba84d	205	}
va009039	1:eb30547ba84d	206
va009039	1:eb30547ba84d	207	void Target2::writeMemory8(uint32_t addr, uint8_t data)
va009039	1:eb30547ba84d	208	{
va009039	1:eb30547ba84d	209	_setaddr8(addr);
va009039	1:eb30547ba84d	210
va009039	1:eb30547ba84d	211	uint32_t data32 = data;
va009039	1:eb30547ba84d	212	data32 <<= ((addr & 0x03) << 3);
va009039	1:eb30547ba84d	213	uint8_t ack = _swd.Transfer(AP_DRW_W, &data32);
va009039	1:eb30547ba84d	214	TEST_ASSERT(ack == SWD_OK);
va009039	1:eb30547ba84d	215	}
va009039	1:eb30547ba84d	216
va009039	0:27d35fa263b5	217	void Target2::_setaddr(uint32_t addr)
va009039	0:27d35fa263b5	218	{
va009039	0:27d35fa263b5	219	uint32_t ctl = CSW_VALUE\|CSW_SIZE32;
va009039	0:27d35fa263b5	220	uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039	0:27d35fa263b5	221	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	222
va009039	0:27d35fa263b5	223	ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039	0:27d35fa263b5	224	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	225
va009039	0:27d35fa263b5	226	ack = _swd.Transfer(AP_TAR, &addr);
va009039	0:27d35fa263b5	227	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	228
va009039	0:27d35fa263b5	229	ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039	0:27d35fa263b5	230	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	231	}
va009039	0:27d35fa263b5	232
va009039	1:eb30547ba84d	233	void Target2::_setaddr8(uint32_t addr)
va009039	1:eb30547ba84d	234	{
va009039	1:eb30547ba84d	235	uint32_t ctl = CSW_VALUE\|CSW_SIZE8;
va009039	1:eb30547ba84d	236	uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039	1:eb30547ba84d	237	TEST_ASSERT(ack == SWD_OK);
va009039	1:eb30547ba84d	238
va009039	1:eb30547ba84d	239	ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039	1:eb30547ba84d	240	TEST_ASSERT(ack == SWD_OK);
va009039	1:eb30547ba84d	241
va009039	1:eb30547ba84d	242	ack = _swd.Transfer(AP_TAR, &addr);
va009039	1:eb30547ba84d	243	TEST_ASSERT(ack == SWD_OK);
va009039	1:eb30547ba84d	244
va009039	1:eb30547ba84d	245	ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039	1:eb30547ba84d	246	TEST_ASSERT(ack == SWD_OK);
va009039	1:eb30547ba84d	247	}
va009039	1:eb30547ba84d	248
va009039	0:27d35fa263b5	249	void Target2::Abort()
va009039	0:27d35fa263b5	250	{
va009039	0:27d35fa263b5	251	uint32_t data = 0x1e;
va009039	0:27d35fa263b5	252	uint8_t ack = _swd.Transfer(DP_ABORT, &data);
va009039	0:27d35fa263b5	253	TEST_ASSERT(ack == SWD_OK);
va009039	0:27d35fa263b5	254	}
va009039	0:27d35fa263b5	255
va009039	0:27d35fa263b5	256	int Target2::getStatus()
va009039	0:27d35fa263b5	257	{
va009039	0:27d35fa263b5	258	return readMemory(DHCSR) & 6 ? TARGET_HALTED : TARGET_RUNNING;
va009039	0:27d35fa263b5	259	}
va009039	0:27d35fa263b5	260
va009039	0:27d35fa263b5	261	bool Target2::wait_status(int status, int timeout_ms)
va009039	0:27d35fa263b5	262	{
va009039	0:27d35fa263b5	263	Timer t;
va009039	0:27d35fa263b5	264	t.reset();
va009039	0:27d35fa263b5	265	t.start();
va009039	0:27d35fa263b5	266	while(t.read_ms() < timeout_ms) {
va009039	0:27d35fa263b5	267	if (getStatus() == status) {
va009039	0:27d35fa263b5	268	return true;
va009039	0:27d35fa263b5	269	}
va009039	0:27d35fa263b5	270	}
va009039	0:27d35fa263b5	271	return false;
va009039	0:27d35fa263b5	272	}
va009039	0:27d35fa263b5	273
va009039	4:5e4107edcbdb	274	bool Target2::prog_status()
va009039	4:5e4107edcbdb	275	{
va009039	4:5e4107edcbdb	276	writeMemory(DEMCR, 1);
va009039	4:5e4107edcbdb	277	int status = getStatus();
va009039	4:5e4107edcbdb	278	TEST_ASSERT(status == TARGET_HALTED);
va009039	4:5e4107edcbdb	279	if (status == TARGET_RUNNING) {
va009039	4:5e4107edcbdb	280	halt();
va009039	4:5e4107edcbdb	281	}
va009039	4:5e4107edcbdb	282	bool st = wait_status(TARGET_HALTED);
va009039	4:5e4107edcbdb	283	TEST_ASSERT(st == true);
va009039	4:5e4107edcbdb	284	writeMemory(DEMCR, 0);
va009039	4:5e4107edcbdb	285	writeMemory(SYSMEMREMAP, 2); // user flash page
va009039	4:5e4107edcbdb	286	uint32_t reset_handler = readMemory(4);
va009039	6:5da6ad51a18f	287	if (setBreakpoint0(reset_handler)) {
va009039	6:5da6ad51a18f	288	writeMemory(NVIC_AIRCR, 0x05fa0004); // SYSRESETREQ software reset
va009039	6:5da6ad51a18f	289	st = wait_status(TARGET_HALTED);
va009039	6:5da6ad51a18f	290	TEST_ASSERT(st == true);
va009039	6:5da6ad51a18f	291	TEST_ASSERT((reset_handler&0xfffffffe) == pc);
va009039	6:5da6ad51a18f	292	removeBreakpoint0(0);
va009039	6:5da6ad51a18f	293	}
va009039	4:5e4107edcbdb	294	return true;
va009039	4:5e4107edcbdb	295	}
va009039	4:5e4107edcbdb	296
va009039	6:5da6ad51a18f	297	bool Target2::setBreakpoint0(uint32_t addr)
va009039	4:5e4107edcbdb	298	{
va009039	6:5da6ad51a18f	299	if ((addr&1) == 0 \|\| addr >= 0x20000000) {
va009039	6:5da6ad51a18f	300	return false;
va009039	6:5da6ad51a18f	301	}
va009039	6:5da6ad51a18f	302	uint32_t data = (addr&0x1ffffffc) \| 0xc0000001;
va009039	6:5da6ad51a18f	303	if (addr&0x00000002) {
va009039	6:5da6ad51a18f	304	data \|= 0x80000000;
va009039	4:5e4107edcbdb	305	} else {
va009039	6:5da6ad51a18f	306	data \|= 0x40000000;
va009039	4:5e4107edcbdb	307	}
va009039	6:5da6ad51a18f	308	writeMemory(FP_COMP0, data); // set breakpoint
va009039	6:5da6ad51a18f	309	writeMemory(FP_CTRL, 3); // enable FPB
va009039	6:5da6ad51a18f	310	return true;
va009039	6:5da6ad51a18f	311	}
va009039	6:5da6ad51a18f	312
va009039	6:5da6ad51a18f	313	void Target2::removeBreakpoint0(uint32_t addr)
va009039	6:5da6ad51a18f	314	{
va009039	6:5da6ad51a18f	315	writeMemory(FP_COMP0, 0); // breakpoint clear
va009039	6:5da6ad51a18f	316	writeMemory(FP_CTRL, 2); // desable FPB
va009039	4:5e4107edcbdb	317	}
va009039	4:5e4107edcbdb	318
va009039	0:27d35fa263b5	319	void Target2::halt()
va009039	0:27d35fa263b5	320	{
va009039	0:27d35fa263b5	321	writeMemory(DHCSR, 0xa05f0003);
va009039	0:27d35fa263b5	322	}
va009039	0:27d35fa263b5	323
va009039	0:27d35fa263b5	324	void Target2::resume()
va009039	0:27d35fa263b5	325	{
va009039	0:27d35fa263b5	326	writeMemory(DHCSR, 0xa05f0001);
va009039	0:27d35fa263b5	327	}
va009039	0:27d35fa263b5	328
va009039	1:eb30547ba84d	329	void Target2::step()
va009039	1:eb30547ba84d	330	{
va009039	1:eb30547ba84d	331	writeMemory(DHCSR, 0xa05f0005);
va009039	1:eb30547ba84d	332	}
va009039	1:eb30547ba84d	333
va009039	0:27d35fa263b5	334	uint32_t CoreReg::read()
va009039	0:27d35fa263b5	335	{
va009039	0:27d35fa263b5	336	_target->writeMemory(DCRSR, _reg);
va009039	0:27d35fa263b5	337	return _target->readMemory(DCRDR);
va009039	0:27d35fa263b5	338	}
va009039	0:27d35fa263b5	339
va009039	0:27d35fa263b5	340	void CoreReg::write(uint32_t value)
va009039	0:27d35fa263b5	341	{
va009039	0:27d35fa263b5	342	_target->writeMemory(DCRDR, value);
va009039	0:27d35fa263b5	343	_target->writeMemory(DCRSR, _reg\|0x10000);
va009039	0:27d35fa263b5	344	}
va009039	0:27d35fa263b5	345
va009039	0:27d35fa263b5	346	void CoreReg::setup(Target2* target, uint8_t reg)
va009039	0:27d35fa263b5	347	{
va009039	0:27d35fa263b5	348	_target = target;
va009039	0:27d35fa263b5	349	_reg = reg;
va009039	0:27d35fa263b5	350	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	01 Sep 2013
Imports:	26
Forks:	0
Commits:	19
Dependents:	0
Dependencies:	5
Followers:	3

The code in this repository is Apache licensed.

Import programlpc810-semihost_helloworld

Target2.cpp@6:5da6ad51a18f, 2013-09-23 (annotated)

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Import program lpc810-semihost_helloworld