semihost server example program

Dependencies:   SWD mbed USBLocalFileSystem BaseDAP USBDAP

/media/uploads/va009039/kl46z-lpc800-360x480.jpg

LPCXpresso
LPC11U68
LPCXpresso
LPC1549
FRDM-KL46ZEA LPC4088 QSB
app-board
LPC1768
app-board
LPC810LPC1114FN28
serverserverserverserverserverclientclient
SWDIOD12D12D12p25p21p4(P0_2)p12
SWCLKD10D10D10p26p22p3(P0_3)p3
nRESET
*option
D6D6D6p34p30p1(P0_5)p23
GNDGNDGNDGNDp1p1p7p22
3.3VP3V3P3V3P3V3p44p40p6p21
flash writeSW2(P0_1)SW3(P1_9)SW1p14
joystick
center
p14
joystick
center

client example:

Import programlpc810-semihost_helloworld

semihost client example program

Committer:
va009039
Date:
Sun Sep 08 14:13:15 2013 +0000
Revision:
3:d7a7cde0bfb8
Parent:
2:32e9437348ad
Child:
4:5e4107edcbdb
add softwarereset(),flash.init()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 3:d7a7cde0bfb8 1 // Target2.cpp 2013/9/8
va009039 0:27d35fa263b5 2 #include "Target2.h"
va009039 0:27d35fa263b5 3 #include "mydebug.h"
va009039 0:27d35fa263b5 4
va009039 3:d7a7cde0bfb8 5 #define SYSMEMREMAP 0x40048000
va009039 3:d7a7cde0bfb8 6
va009039 2:32e9437348ad 7 #define CoreDebug_BASE (0xE000EDF0UL)
va009039 2:32e9437348ad 8 #define DHCSR (CoreDebug_BASE+0)
va009039 2:32e9437348ad 9 #define DCRSR (CoreDebug_BASE+4)
va009039 2:32e9437348ad 10 #define DCRDR (CoreDebug_BASE+8)
va009039 2:32e9437348ad 11 #define DEMCR (CoreDebug_BASE+12)
va009039 2:32e9437348ad 12
va009039 2:32e9437348ad 13 #define NVIC_AIRCR 0xE000ED0C
va009039 0:27d35fa263b5 14
va009039 0:27d35fa263b5 15 Target2::Target2(PinName swdio, PinName swclk, PinName reset, Serial* usbpc)
va009039 0:27d35fa263b5 16 : _swd(swdio, swclk, reset), _pc(usbpc)
va009039 0:27d35fa263b5 17 {
va009039 0:27d35fa263b5 18 r0.setup(this, 0);
va009039 0:27d35fa263b5 19 r1.setup(this, 1);
va009039 0:27d35fa263b5 20 r2.setup(this, 2);
va009039 0:27d35fa263b5 21 r3.setup(this, 3);
va009039 0:27d35fa263b5 22 r4.setup(this, 4);
va009039 0:27d35fa263b5 23 r5.setup(this, 5);
va009039 0:27d35fa263b5 24 r6.setup(this, 6);
va009039 0:27d35fa263b5 25 r7.setup(this, 7);
va009039 0:27d35fa263b5 26 r8.setup(this, 8);
va009039 0:27d35fa263b5 27 r9.setup(this, 9);
va009039 0:27d35fa263b5 28 r10.setup(this, 10);
va009039 0:27d35fa263b5 29 r11.setup(this, 11);
va009039 0:27d35fa263b5 30 r12.setup(this, 12);
va009039 0:27d35fa263b5 31 sp.setup(this, 13);
va009039 0:27d35fa263b5 32 lr.setup(this, 14);
va009039 0:27d35fa263b5 33 pc.setup(this, 15);
va009039 0:27d35fa263b5 34 xpsr.setup(this, 16);
va009039 0:27d35fa263b5 35 }
va009039 0:27d35fa263b5 36
va009039 0:27d35fa263b5 37 bool Target2::setup()
va009039 0:27d35fa263b5 38 {
va009039 0:27d35fa263b5 39 _swd.Setup();
va009039 0:27d35fa263b5 40 _swd.JTAG2SWD();
va009039 0:27d35fa263b5 41
va009039 0:27d35fa263b5 42 uint32_t data;
va009039 0:27d35fa263b5 43 uint8_t ack = _swd.Transfer(DP_IDCODE, &data);
va009039 0:27d35fa263b5 44 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 45 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 46 return false;
va009039 0:27d35fa263b5 47 }
va009039 3:d7a7cde0bfb8 48 idcode = data;
va009039 3:d7a7cde0bfb8 49 //TEST_ASSERT(data == 0x0bb11477);
va009039 0:27d35fa263b5 50
va009039 0:27d35fa263b5 51 Abort();
va009039 0:27d35fa263b5 52
va009039 0:27d35fa263b5 53 data = 0x0;
va009039 0:27d35fa263b5 54 ack = _swd.Transfer(DP_SELECT, &data);
va009039 0:27d35fa263b5 55 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 56 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 57 return false;
va009039 0:27d35fa263b5 58 }
va009039 0:27d35fa263b5 59
va009039 0:27d35fa263b5 60 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 61 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 62 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 63 return false;
va009039 0:27d35fa263b5 64 }
va009039 0:27d35fa263b5 65
va009039 0:27d35fa263b5 66 data = CSYSPWRUPREQ | CDBGPWRUPREQ;
va009039 0:27d35fa263b5 67 TEST_ASSERT(data == 0x50000000);
va009039 0:27d35fa263b5 68 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 69 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 70 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 71 return false;
va009039 0:27d35fa263b5 72 }
va009039 0:27d35fa263b5 73
va009039 0:27d35fa263b5 74 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 75 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 76 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 77 return false;
va009039 0:27d35fa263b5 78 }
va009039 0:27d35fa263b5 79
va009039 0:27d35fa263b5 80 ack = _swd.Transfer(DP_CTRL_STAT_R, &data);
va009039 0:27d35fa263b5 81 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 82 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 83 return false;
va009039 0:27d35fa263b5 84 }
va009039 0:27d35fa263b5 85 TEST_ASSERT(data == 0xf0000040);
va009039 0:27d35fa263b5 86
va009039 0:27d35fa263b5 87 data = CSYSPWRUPREQ | CDBGPWRUPREQ | 0x04000000;
va009039 0:27d35fa263b5 88 TEST_ASSERT(data == 0x54000000);
va009039 0:27d35fa263b5 89 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 90 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 91 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 92 return false;
va009039 0:27d35fa263b5 93 }
va009039 0:27d35fa263b5 94
va009039 0:27d35fa263b5 95 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 96 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 97 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 98 return false;
va009039 0:27d35fa263b5 99 }
va009039 0:27d35fa263b5 100
va009039 0:27d35fa263b5 101 data = CSYSPWRUPREQ | CDBGPWRUPREQ | MASKLANE;
va009039 0:27d35fa263b5 102 TEST_ASSERT(data == 0x50000f00);
va009039 0:27d35fa263b5 103 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 104 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 105 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 106 return false;
va009039 0:27d35fa263b5 107 }
va009039 0:27d35fa263b5 108
va009039 0:27d35fa263b5 109 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 110 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 111 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 112 return false;
va009039 0:27d35fa263b5 113 }
va009039 0:27d35fa263b5 114 return true;
va009039 0:27d35fa263b5 115 }
va009039 0:27d35fa263b5 116
va009039 3:d7a7cde0bfb8 117 void Target2::HardwareReset()
va009039 0:27d35fa263b5 118 {
va009039 3:d7a7cde0bfb8 119 _swd.SWJPins(0x00, 0x80); // nReset off
va009039 3:d7a7cde0bfb8 120 _swd.SWJPins(0x80, 0x80); // nReset on
va009039 3:d7a7cde0bfb8 121 }
va009039 3:d7a7cde0bfb8 122
va009039 3:d7a7cde0bfb8 123 void Target2::SoftwareReset()
va009039 3:d7a7cde0bfb8 124 {
va009039 3:d7a7cde0bfb8 125 writeMemory(NVIC_AIRCR, 0x05fa0004);
va009039 0:27d35fa263b5 126 }
va009039 0:27d35fa263b5 127
va009039 0:27d35fa263b5 128 uint32_t Target2::readMemory(uint32_t addr)
va009039 0:27d35fa263b5 129 {
va009039 0:27d35fa263b5 130 _setaddr(addr);
va009039 0:27d35fa263b5 131
va009039 0:27d35fa263b5 132 uint32_t data;
va009039 0:27d35fa263b5 133 uint8_t ack = _swd.Transfer(AP_DRW_R, &data); // dummy read
va009039 0:27d35fa263b5 134 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 135
va009039 0:27d35fa263b5 136 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 137 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 138 return data;
va009039 0:27d35fa263b5 139 }
va009039 0:27d35fa263b5 140
va009039 0:27d35fa263b5 141 void Target2::readMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 142 {
va009039 0:27d35fa263b5 143 if (count == 0) {
va009039 0:27d35fa263b5 144 return;
va009039 0:27d35fa263b5 145 }
va009039 0:27d35fa263b5 146
va009039 0:27d35fa263b5 147 _setaddr(addr);
va009039 0:27d35fa263b5 148
va009039 0:27d35fa263b5 149 uint8_t ack = _swd.Transfer(AP_DRW_R, NULL); // dummy read
va009039 0:27d35fa263b5 150 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 151
va009039 0:27d35fa263b5 152 for(int i = 0; i < count-1; i++) {
va009039 0:27d35fa263b5 153 ack = _swd.Transfer(AP_DRW_R, data++);
va009039 0:27d35fa263b5 154 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 155 }
va009039 0:27d35fa263b5 156 ack = _swd.Transfer(DP_RDBUFF, data);
va009039 0:27d35fa263b5 157 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 158 }
va009039 0:27d35fa263b5 159
va009039 0:27d35fa263b5 160 void Target2::writeMemory(uint32_t addr, uint32_t data)
va009039 0:27d35fa263b5 161 {
va009039 0:27d35fa263b5 162 writeMemory(addr, &data, 1);
va009039 0:27d35fa263b5 163 }
va009039 0:27d35fa263b5 164
va009039 0:27d35fa263b5 165 void Target2::writeMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 166 {
va009039 0:27d35fa263b5 167 _setaddr(addr);
va009039 0:27d35fa263b5 168
va009039 0:27d35fa263b5 169 while(count-- > 0) {
va009039 0:27d35fa263b5 170 uint8_t ack = _swd.Transfer(AP_DRW_W, data);
va009039 0:27d35fa263b5 171 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 172 data++;
va009039 0:27d35fa263b5 173 }
va009039 0:27d35fa263b5 174 }
va009039 0:27d35fa263b5 175
va009039 1:eb30547ba84d 176 uint8_t Target2::readMemory8(uint32_t addr)
va009039 1:eb30547ba84d 177 {
va009039 1:eb30547ba84d 178 _setaddr8(addr);
va009039 1:eb30547ba84d 179
va009039 1:eb30547ba84d 180 uint32_t data32;
va009039 1:eb30547ba84d 181 uint8_t ack = _swd.Transfer(AP_DRW_R, &data32); // dummy read
va009039 1:eb30547ba84d 182 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 183
va009039 1:eb30547ba84d 184 ack = _swd.Transfer(DP_RDBUFF, &data32);
va009039 1:eb30547ba84d 185 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 186 return (data32 >> ((addr & 0x03) << 3)) & 0xff;
va009039 1:eb30547ba84d 187 }
va009039 1:eb30547ba84d 188
va009039 1:eb30547ba84d 189 void Target2::writeMemory8(uint32_t addr, uint8_t data)
va009039 1:eb30547ba84d 190 {
va009039 1:eb30547ba84d 191 _setaddr8(addr);
va009039 1:eb30547ba84d 192
va009039 1:eb30547ba84d 193 uint32_t data32 = data;
va009039 1:eb30547ba84d 194 data32 <<= ((addr & 0x03) << 3);
va009039 1:eb30547ba84d 195 uint8_t ack = _swd.Transfer(AP_DRW_W, &data32);
va009039 1:eb30547ba84d 196 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 197 }
va009039 1:eb30547ba84d 198
va009039 0:27d35fa263b5 199 void Target2::_setaddr(uint32_t addr)
va009039 0:27d35fa263b5 200 {
va009039 0:27d35fa263b5 201 uint32_t ctl = CSW_VALUE|CSW_SIZE32;
va009039 0:27d35fa263b5 202 uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039 0:27d35fa263b5 203 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 204
va009039 0:27d35fa263b5 205 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 206 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 207
va009039 0:27d35fa263b5 208 ack = _swd.Transfer(AP_TAR, &addr);
va009039 0:27d35fa263b5 209 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 210
va009039 0:27d35fa263b5 211 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 212 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 213 }
va009039 0:27d35fa263b5 214
va009039 1:eb30547ba84d 215 void Target2::_setaddr8(uint32_t addr)
va009039 1:eb30547ba84d 216 {
va009039 1:eb30547ba84d 217 uint32_t ctl = CSW_VALUE|CSW_SIZE8;
va009039 1:eb30547ba84d 218 uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039 1:eb30547ba84d 219 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 220
va009039 1:eb30547ba84d 221 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 222 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 223
va009039 1:eb30547ba84d 224 ack = _swd.Transfer(AP_TAR, &addr);
va009039 1:eb30547ba84d 225 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 226
va009039 1:eb30547ba84d 227 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 228 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 229 }
va009039 1:eb30547ba84d 230
va009039 0:27d35fa263b5 231 void Target2::Abort()
va009039 0:27d35fa263b5 232 {
va009039 0:27d35fa263b5 233 uint32_t data = 0x1e;
va009039 0:27d35fa263b5 234 uint8_t ack = _swd.Transfer(DP_ABORT, &data);
va009039 0:27d35fa263b5 235 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 236 }
va009039 0:27d35fa263b5 237
va009039 0:27d35fa263b5 238 int Target2::getStatus()
va009039 0:27d35fa263b5 239 {
va009039 0:27d35fa263b5 240 return readMemory(DHCSR) & 6 ? TARGET_HALTED : TARGET_RUNNING;
va009039 0:27d35fa263b5 241 }
va009039 0:27d35fa263b5 242
va009039 0:27d35fa263b5 243 bool Target2::wait_status(int status, int timeout_ms)
va009039 0:27d35fa263b5 244 {
va009039 0:27d35fa263b5 245 Timer t;
va009039 0:27d35fa263b5 246 t.reset();
va009039 0:27d35fa263b5 247 t.start();
va009039 0:27d35fa263b5 248 while(t.read_ms() < timeout_ms) {
va009039 0:27d35fa263b5 249 if (getStatus() == status) {
va009039 0:27d35fa263b5 250 return true;
va009039 0:27d35fa263b5 251 }
va009039 0:27d35fa263b5 252 }
va009039 0:27d35fa263b5 253 return false;
va009039 0:27d35fa263b5 254 }
va009039 0:27d35fa263b5 255
va009039 0:27d35fa263b5 256 void Target2::halt()
va009039 0:27d35fa263b5 257 {
va009039 0:27d35fa263b5 258 writeMemory(DHCSR, 0xa05f0003);
va009039 0:27d35fa263b5 259 }
va009039 0:27d35fa263b5 260
va009039 0:27d35fa263b5 261 void Target2::resume()
va009039 0:27d35fa263b5 262 {
va009039 0:27d35fa263b5 263 writeMemory(DHCSR, 0xa05f0001);
va009039 0:27d35fa263b5 264 }
va009039 0:27d35fa263b5 265
va009039 1:eb30547ba84d 266 void Target2::step()
va009039 1:eb30547ba84d 267 {
va009039 1:eb30547ba84d 268 writeMemory(DHCSR, 0xa05f0005);
va009039 1:eb30547ba84d 269 }
va009039 1:eb30547ba84d 270
va009039 0:27d35fa263b5 271 uint32_t CoreReg::read()
va009039 0:27d35fa263b5 272 {
va009039 0:27d35fa263b5 273 _target->writeMemory(DCRSR, _reg);
va009039 0:27d35fa263b5 274 return _target->readMemory(DCRDR);
va009039 0:27d35fa263b5 275 }
va009039 0:27d35fa263b5 276
va009039 0:27d35fa263b5 277 void CoreReg::write(uint32_t value)
va009039 0:27d35fa263b5 278 {
va009039 0:27d35fa263b5 279 _target->writeMemory(DCRDR, value);
va009039 0:27d35fa263b5 280 _target->writeMemory(DCRSR, _reg|0x10000);
va009039 0:27d35fa263b5 281 }
va009039 0:27d35fa263b5 282
va009039 0:27d35fa263b5 283 void CoreReg::setup(Target2* target, uint8_t reg)
va009039 0:27d35fa263b5 284 {
va009039 0:27d35fa263b5 285 _target = target;
va009039 0:27d35fa263b5 286 _reg = reg;
va009039 0:27d35fa263b5 287 }