Norimasa Okamoto / Mbed 2 deprecated lpcterm2

semihost server example program

Dependencies:   SWD mbed USBLocalFileSystem BaseDAP USBDAP

/media/uploads/va009039/kl46z-lpc800-360x480.jpg

LPCXpresso
LPC11U68		LPCXpresso
LPC1549		FRDM-KL46ZEA LPC4088 QSB
app-board		LPC1768
app-board		LPC810LPC1114FN28
serverserverserverserverserverclientclient
SWDIOD12D12D12p25p21p4(P0_2)p12
SWCLKD10D10D10p26p22p3(P0_3)p3
nRESET
*option		D6D6D6p34p30p1(P0_5)p23
GNDGNDGNDGNDp1p1p7p22
3.3VP3V3P3V3P3V3p44p40p6p21
flash writeSW2(P0_1)SW3(P1_9)SW1p14
joystick
center		p14
joystick
center

client example:

Import programlpc810-semihost_helloworld

semihost client example program

Last commit 20 Feb 2014 by Norimasa Okamoto

Target2.cpp@2:32e9437348ad, 2013-09-05 (annotated)

Committer:
va009039
Date:
Thu Sep 05 09:34:12 2013 +0000
Revision:
2:32e9437348ad
Parent:
1:eb30547ba84d
Child:
3:d7a7cde0bfb8
bug fix sys_writec,sys_exit not resume.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 2:32e9437348ad 1 // Target2.cpp 2013/9/5
va009039 0:27d35fa263b5 2 #include "Target2.h"
va009039 0:27d35fa263b5 3 #include "mydebug.h"
va009039 0:27d35fa263b5 4
va009039 2:32e9437348ad 5 #define CoreDebug_BASE (0xE000EDF0UL)
va009039 2:32e9437348ad 6 #define DHCSR (CoreDebug_BASE+0)
va009039 2:32e9437348ad 7 #define DCRSR (CoreDebug_BASE+4)
va009039 2:32e9437348ad 8 #define DCRDR (CoreDebug_BASE+8)
va009039 2:32e9437348ad 9 #define DEMCR (CoreDebug_BASE+12)
va009039 2:32e9437348ad 10
va009039 2:32e9437348ad 11 #define NVIC_AIRCR 0xE000ED0C
va009039 0:27d35fa263b5 12
va009039 0:27d35fa263b5 13 Target2::Target2(PinName swdio, PinName swclk, PinName reset, Serial* usbpc)
va009039 0:27d35fa263b5 14 : _swd(swdio, swclk, reset), _pc(usbpc)
va009039 0:27d35fa263b5 15 {
va009039 0:27d35fa263b5 16 r0.setup(this, 0);
va009039 0:27d35fa263b5 17 r1.setup(this, 1);
va009039 0:27d35fa263b5 18 r2.setup(this, 2);
va009039 0:27d35fa263b5 19 r3.setup(this, 3);
va009039 0:27d35fa263b5 20 r4.setup(this, 4);
va009039 0:27d35fa263b5 21 r5.setup(this, 5);
va009039 0:27d35fa263b5 22 r6.setup(this, 6);
va009039 0:27d35fa263b5 23 r7.setup(this, 7);
va009039 0:27d35fa263b5 24 r8.setup(this, 8);
va009039 0:27d35fa263b5 25 r9.setup(this, 9);
va009039 0:27d35fa263b5 26 r10.setup(this, 10);
va009039 0:27d35fa263b5 27 r11.setup(this, 11);
va009039 0:27d35fa263b5 28 r12.setup(this, 12);
va009039 0:27d35fa263b5 29 sp.setup(this, 13);
va009039 0:27d35fa263b5 30 lr.setup(this, 14);
va009039 0:27d35fa263b5 31 pc.setup(this, 15);
va009039 0:27d35fa263b5 32 xpsr.setup(this, 16);
va009039 0:27d35fa263b5 33 }
va009039 0:27d35fa263b5 34
va009039 0:27d35fa263b5 35 bool Target2::setup()
va009039 0:27d35fa263b5 36 {
va009039 0:27d35fa263b5 37 _swd.Setup();
va009039 0:27d35fa263b5 38 _swd.JTAG2SWD();
va009039 0:27d35fa263b5 39
va009039 0:27d35fa263b5 40 uint32_t data;
va009039 0:27d35fa263b5 41 uint8_t ack = _swd.Transfer(DP_IDCODE, &data);
va009039 0:27d35fa263b5 42 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 43 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 44 return false;
va009039 0:27d35fa263b5 45 }
va009039 0:27d35fa263b5 46 TEST_ASSERT(data == 0x0bb11477);
va009039 0:27d35fa263b5 47
va009039 0:27d35fa263b5 48 Abort();
va009039 0:27d35fa263b5 49
va009039 0:27d35fa263b5 50 data = 0x0;
va009039 0:27d35fa263b5 51 ack = _swd.Transfer(DP_SELECT, &data);
va009039 0:27d35fa263b5 52 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 53 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 54 return false;
va009039 0:27d35fa263b5 55 }
va009039 0:27d35fa263b5 56
va009039 0:27d35fa263b5 57 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 58 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 59 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 60 return false;
va009039 0:27d35fa263b5 61 }
va009039 0:27d35fa263b5 62
va009039 0:27d35fa263b5 63 data = CSYSPWRUPREQ | CDBGPWRUPREQ;
va009039 0:27d35fa263b5 64 TEST_ASSERT(data == 0x50000000);
va009039 0:27d35fa263b5 65 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 66 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 67 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 68 return false;
va009039 0:27d35fa263b5 69 }
va009039 0:27d35fa263b5 70
va009039 0:27d35fa263b5 71 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 72 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 73 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 74 return false;
va009039 0:27d35fa263b5 75 }
va009039 0:27d35fa263b5 76
va009039 0:27d35fa263b5 77 ack = _swd.Transfer(DP_CTRL_STAT_R, &data);
va009039 0:27d35fa263b5 78 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 79 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 80 return false;
va009039 0:27d35fa263b5 81 }
va009039 0:27d35fa263b5 82 TEST_ASSERT(data == 0xf0000040);
va009039 0:27d35fa263b5 83
va009039 0:27d35fa263b5 84 data = CSYSPWRUPREQ | CDBGPWRUPREQ | 0x04000000;
va009039 0:27d35fa263b5 85 TEST_ASSERT(data == 0x54000000);
va009039 0:27d35fa263b5 86 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 87 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 88 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 89 return false;
va009039 0:27d35fa263b5 90 }
va009039 0:27d35fa263b5 91
va009039 0:27d35fa263b5 92 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 93 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 94 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 95 return false;
va009039 0:27d35fa263b5 96 }
va009039 0:27d35fa263b5 97
va009039 0:27d35fa263b5 98 data = CSYSPWRUPREQ | CDBGPWRUPREQ | MASKLANE;
va009039 0:27d35fa263b5 99 TEST_ASSERT(data == 0x50000f00);
va009039 0:27d35fa263b5 100 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 101 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 102 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 103 return false;
va009039 0:27d35fa263b5 104 }
va009039 0:27d35fa263b5 105
va009039 0:27d35fa263b5 106 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 107 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 108 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 109 return false;
va009039 0:27d35fa263b5 110 }
va009039 0:27d35fa263b5 111 return true;
va009039 0:27d35fa263b5 112 }
va009039 0:27d35fa263b5 113
va009039 0:27d35fa263b5 114 void Target2::Reset()
va009039 0:27d35fa263b5 115 {
va009039 0:27d35fa263b5 116 _swd.reset();
va009039 0:27d35fa263b5 117 }
va009039 0:27d35fa263b5 118
va009039 0:27d35fa263b5 119 uint32_t Target2::readMemory(uint32_t addr)
va009039 0:27d35fa263b5 120 {
va009039 0:27d35fa263b5 121 _setaddr(addr);
va009039 0:27d35fa263b5 122
va009039 0:27d35fa263b5 123 uint32_t data;
va009039 0:27d35fa263b5 124 uint8_t ack = _swd.Transfer(AP_DRW_R, &data); // dummy read
va009039 0:27d35fa263b5 125 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 126
va009039 0:27d35fa263b5 127 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 128 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 129 return data;
va009039 0:27d35fa263b5 130 }
va009039 0:27d35fa263b5 131
va009039 0:27d35fa263b5 132 void Target2::readMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 133 {
va009039 0:27d35fa263b5 134 if (count == 0) {
va009039 0:27d35fa263b5 135 return;
va009039 0:27d35fa263b5 136 }
va009039 0:27d35fa263b5 137
va009039 0:27d35fa263b5 138 _setaddr(addr);
va009039 0:27d35fa263b5 139
va009039 0:27d35fa263b5 140 uint8_t ack = _swd.Transfer(AP_DRW_R, NULL); // dummy read
va009039 0:27d35fa263b5 141 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 142
va009039 0:27d35fa263b5 143 for(int i = 0; i < count-1; i++) {
va009039 0:27d35fa263b5 144 ack = _swd.Transfer(AP_DRW_R, data++);
va009039 0:27d35fa263b5 145 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 146 }
va009039 0:27d35fa263b5 147 ack = _swd.Transfer(DP_RDBUFF, data);
va009039 0:27d35fa263b5 148 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 149 }
va009039 0:27d35fa263b5 150
va009039 0:27d35fa263b5 151 void Target2::writeMemory(uint32_t addr, uint32_t data)
va009039 0:27d35fa263b5 152 {
va009039 0:27d35fa263b5 153 writeMemory(addr, &data, 1);
va009039 0:27d35fa263b5 154 }
va009039 0:27d35fa263b5 155
va009039 0:27d35fa263b5 156 void Target2::writeMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 157 {
va009039 0:27d35fa263b5 158 _setaddr(addr);
va009039 0:27d35fa263b5 159
va009039 0:27d35fa263b5 160 while(count-- > 0) {
va009039 0:27d35fa263b5 161 uint8_t ack = _swd.Transfer(AP_DRW_W, data);
va009039 0:27d35fa263b5 162 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 163 data++;
va009039 0:27d35fa263b5 164 }
va009039 0:27d35fa263b5 165 }
va009039 0:27d35fa263b5 166
va009039 1:eb30547ba84d 167 uint8_t Target2::readMemory8(uint32_t addr)
va009039 1:eb30547ba84d 168 {
va009039 1:eb30547ba84d 169 _setaddr8(addr);
va009039 1:eb30547ba84d 170
va009039 1:eb30547ba84d 171 uint32_t data32;
va009039 1:eb30547ba84d 172 uint8_t ack = _swd.Transfer(AP_DRW_R, &data32); // dummy read
va009039 1:eb30547ba84d 173 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 174
va009039 1:eb30547ba84d 175 ack = _swd.Transfer(DP_RDBUFF, &data32);
va009039 1:eb30547ba84d 176 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 177 return (data32 >> ((addr & 0x03) << 3)) & 0xff;
va009039 1:eb30547ba84d 178 }
va009039 1:eb30547ba84d 179
va009039 1:eb30547ba84d 180 void Target2::writeMemory8(uint32_t addr, uint8_t data)
va009039 1:eb30547ba84d 181 {
va009039 1:eb30547ba84d 182 _setaddr8(addr);
va009039 1:eb30547ba84d 183
va009039 1:eb30547ba84d 184 uint32_t data32 = data;
va009039 1:eb30547ba84d 185 data32 <<= ((addr & 0x03) << 3);
va009039 1:eb30547ba84d 186 uint8_t ack = _swd.Transfer(AP_DRW_W, &data32);
va009039 1:eb30547ba84d 187 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 188 }
va009039 1:eb30547ba84d 189
va009039 0:27d35fa263b5 190 void Target2::_setaddr(uint32_t addr)
va009039 0:27d35fa263b5 191 {
va009039 0:27d35fa263b5 192 uint32_t ctl = CSW_VALUE|CSW_SIZE32;
va009039 0:27d35fa263b5 193 TEST_ASSERT(ctl == 0x23000052);
va009039 0:27d35fa263b5 194 uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039 0:27d35fa263b5 195 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 196
va009039 0:27d35fa263b5 197 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 198 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 199
va009039 0:27d35fa263b5 200 ack = _swd.Transfer(AP_TAR, &addr);
va009039 0:27d35fa263b5 201 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 202
va009039 0:27d35fa263b5 203 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 204 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 205 }
va009039 0:27d35fa263b5 206
va009039 1:eb30547ba84d 207 void Target2::_setaddr8(uint32_t addr)
va009039 1:eb30547ba84d 208 {
va009039 1:eb30547ba84d 209 uint32_t ctl = CSW_VALUE|CSW_SIZE8;
va009039 1:eb30547ba84d 210 TEST_ASSERT(ctl == 0x23000050);
va009039 1:eb30547ba84d 211 uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039 1:eb30547ba84d 212 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 213
va009039 1:eb30547ba84d 214 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 215 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 216
va009039 1:eb30547ba84d 217 ack = _swd.Transfer(AP_TAR, &addr);
va009039 1:eb30547ba84d 218 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 219
va009039 1:eb30547ba84d 220 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 221 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 222 }
va009039 1:eb30547ba84d 223
va009039 0:27d35fa263b5 224 void Target2::Abort()
va009039 0:27d35fa263b5 225 {
va009039 0:27d35fa263b5 226 uint32_t data = 0x1e;
va009039 0:27d35fa263b5 227 uint8_t ack = _swd.Transfer(DP_ABORT, &data);
va009039 0:27d35fa263b5 228 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 229 }
va009039 0:27d35fa263b5 230
va009039 0:27d35fa263b5 231 int Target2::getStatus()
va009039 0:27d35fa263b5 232 {
va009039 0:27d35fa263b5 233 return readMemory(DHCSR) & 6 ? TARGET_HALTED : TARGET_RUNNING;
va009039 0:27d35fa263b5 234 }
va009039 0:27d35fa263b5 235
va009039 0:27d35fa263b5 236 bool Target2::wait_status(int status, int timeout_ms)
va009039 0:27d35fa263b5 237 {
va009039 0:27d35fa263b5 238 Timer t;
va009039 0:27d35fa263b5 239 t.reset();
va009039 0:27d35fa263b5 240 t.start();
va009039 0:27d35fa263b5 241 while(t.read_ms() < timeout_ms) {
va009039 0:27d35fa263b5 242 if (getStatus() == status) {
va009039 0:27d35fa263b5 243 return true;
va009039 0:27d35fa263b5 244 }
va009039 0:27d35fa263b5 245 }
va009039 0:27d35fa263b5 246 return false;
va009039 0:27d35fa263b5 247 }
va009039 0:27d35fa263b5 248
va009039 0:27d35fa263b5 249 void Target2::halt()
va009039 0:27d35fa263b5 250 {
va009039 0:27d35fa263b5 251 writeMemory(DHCSR, 0xa05f0003);
va009039 0:27d35fa263b5 252 }
va009039 0:27d35fa263b5 253
va009039 0:27d35fa263b5 254 void Target2::resume()
va009039 0:27d35fa263b5 255 {
va009039 0:27d35fa263b5 256 writeMemory(DHCSR, 0xa05f0001);
va009039 0:27d35fa263b5 257 }
va009039 0:27d35fa263b5 258
va009039 1:eb30547ba84d 259 void Target2::step()
va009039 1:eb30547ba84d 260 {
va009039 1:eb30547ba84d 261 writeMemory(DHCSR, 0xa05f0005);
va009039 1:eb30547ba84d 262 }
va009039 1:eb30547ba84d 263
va009039 0:27d35fa263b5 264 uint32_t CoreReg::read()
va009039 0:27d35fa263b5 265 {
va009039 0:27d35fa263b5 266 _target->writeMemory(DCRSR, _reg);
va009039 0:27d35fa263b5 267 return _target->readMemory(DCRDR);
va009039 0:27d35fa263b5 268 }
va009039 0:27d35fa263b5 269
va009039 0:27d35fa263b5 270 void CoreReg::write(uint32_t value)
va009039 0:27d35fa263b5 271 {
va009039 0:27d35fa263b5 272 _target->writeMemory(DCRDR, value);
va009039 0:27d35fa263b5 273 _target->writeMemory(DCRSR, _reg|0x10000);
va009039 0:27d35fa263b5 274 }
va009039 0:27d35fa263b5 275
va009039 0:27d35fa263b5 276 void CoreReg::setup(Target2* target, uint8_t reg)
va009039 0:27d35fa263b5 277 {
va009039 0:27d35fa263b5 278 _target = target;
va009039 0:27d35fa263b5 279 _reg = reg;
va009039 0:27d35fa263b5 280 }