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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Parent:
149:1fb5f62b92bd 
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30
mbed_official 146:f64d43ff0c18 31 #include "fsl_dspi_hal.h"
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 /*******************************************************************************
mbed_official 146:f64d43ff0c18 34 * Definitions
mbed_official 146:f64d43ff0c18 35 ******************************************************************************/
mbed_official 146:f64d43ff0c18 36
mbed_official 146:f64d43ff0c18 37 /*******************************************************************************
mbed_official 324:406fd2029f23 38 * Variables
mbed_official 324:406fd2029f23 39 ******************************************************************************/
mbed_official 324:406fd2029f23 40
mbed_official 324:406fd2029f23 41 /*******************************************************************************
mbed_official 146:f64d43ff0c18 42 * Code
mbed_official 146:f64d43ff0c18 43 ******************************************************************************/
mbed_official 146:f64d43ff0c18 44
mbed_official 146:f64d43ff0c18 45 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 46 *
mbed_official 324:406fd2029f23 47 * Function Name : DSPI_HAL_Init
mbed_official 146:f64d43ff0c18 48 * Description : Restore DSPI to reset configuration.
mbed_official 146:f64d43ff0c18 49 * This function basically resets all of the DSPI registers to their default setting including
mbed_official 146:f64d43ff0c18 50 * disabling the module.
mbed_official 146:f64d43ff0c18 51 *
mbed_official 146:f64d43ff0c18 52 *END**************************************************************************/
mbed_official 324:406fd2029f23 53 void DSPI_HAL_Init(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 54 {
mbed_official 146:f64d43ff0c18 55 /* first, make sure the module is enabled to allow writes to certain registers*/
mbed_official 324:406fd2029f23 56 DSPI_HAL_Enable(baseAddr);
mbed_official 146:f64d43ff0c18 57
mbed_official 146:f64d43ff0c18 58 /* Halt all transfers*/
mbed_official 324:406fd2029f23 59 DSPI_HAL_StopTransfer(baseAddr);
mbed_official 146:f64d43ff0c18 60
mbed_official 146:f64d43ff0c18 61 /* set the registers to their default states*/
mbed_official 146:f64d43ff0c18 62 /* clear the status bits (write-1-to-clear)*/
mbed_official 324:406fd2029f23 63 HW_SPI_SR_WR(baseAddr, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF |
mbed_official 324:406fd2029f23 64 BM_SPI_SR_TFFF | BM_SPI_SR_RFOF | BM_SPI_SR_RFDF);
mbed_official 324:406fd2029f23 65 HW_SPI_TCR_WR(baseAddr, 0);
mbed_official 324:406fd2029f23 66 HW_SPI_CTARn_WR(baseAddr, 0, 0x78000000); /* CTAR0*/
mbed_official 324:406fd2029f23 67 HW_SPI_CTARn_WR(baseAddr, 1, 0x78000000); /* CTAR1*/
mbed_official 324:406fd2029f23 68 HW_SPI_RSER_WR(baseAddr, 0);
mbed_official 324:406fd2029f23 69
mbed_official 324:406fd2029f23 70 /* Clear out PUSHR register. Since DSPI is halted, nothing should be transmitted. Be
mbed_official 324:406fd2029f23 71 * sure the flush the FIFOs afterwards
mbed_official 324:406fd2029f23 72 */
mbed_official 324:406fd2029f23 73 HW_SPI_PUSHR_WR(baseAddr, 0);
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /* flush the fifos*/
mbed_official 324:406fd2029f23 76 DSPI_HAL_SetFlushFifoCmd(baseAddr, true, true);
mbed_official 324:406fd2029f23 77
mbed_official 324:406fd2029f23 78 /* Now set MCR to default value, which disables module: set MDIS and HALT, clear other bits */
mbed_official 324:406fd2029f23 79 HW_SPI_MCR_WR(baseAddr, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT);
mbed_official 146:f64d43ff0c18 80 }
mbed_official 146:f64d43ff0c18 81
mbed_official 146:f64d43ff0c18 82 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 83 *
mbed_official 324:406fd2029f23 84 * Function Name : DSPI_HAL_SetBaudRate
mbed_official 146:f64d43ff0c18 85 * Description : Set the DSPI baud rate in bits per second.
mbed_official 146:f64d43ff0c18 86 * This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest
mbed_official 146:f64d43ff0c18 87 * possible baud rate without exceeding the desired baud rate, and will return the calculated
mbed_official 146:f64d43ff0c18 88 * baud rate in bits-per-second. It requires that the caller also provide the frequency of the
mbed_official 146:f64d43ff0c18 89 * module source clock (in Hz).
mbed_official 146:f64d43ff0c18 90 *
mbed_official 146:f64d43ff0c18 91 *END**************************************************************************/
mbed_official 324:406fd2029f23 92 uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 93 uint32_t bitsPerSec, uint32_t sourceClockInHz)
mbed_official 146:f64d43ff0c18 94 {
mbed_official 146:f64d43ff0c18 95 /* for master mode configuration, if slave mode detected, return 0*/
mbed_official 324:406fd2029f23 96 if (!DSPI_HAL_IsMaster(baseAddr))
mbed_official 146:f64d43ff0c18 97 {
mbed_official 146:f64d43ff0c18 98 return 0;
mbed_official 146:f64d43ff0c18 99 }
mbed_official 146:f64d43ff0c18 100
mbed_official 146:f64d43ff0c18 101 uint32_t prescaler, bestPrescaler;
mbed_official 146:f64d43ff0c18 102 uint32_t scaler, bestScaler;
mbed_official 146:f64d43ff0c18 103 uint32_t dbr, bestDbr;
mbed_official 146:f64d43ff0c18 104 uint32_t realBaudrate, bestBaudrate;
mbed_official 146:f64d43ff0c18 105 uint32_t diff, min_diff;
mbed_official 146:f64d43ff0c18 106 uint32_t baudrate = bitsPerSec;
mbed_official 146:f64d43ff0c18 107
mbed_official 146:f64d43ff0c18 108 /* find combination of prescaler and scaler resulting in baudrate closest to the */
mbed_official 146:f64d43ff0c18 109 /* requested value */
mbed_official 146:f64d43ff0c18 110 min_diff = 0xFFFFFFFFU;
mbed_official 146:f64d43ff0c18 111 bestPrescaler = 0;
mbed_official 146:f64d43ff0c18 112 bestScaler = 0;
mbed_official 146:f64d43ff0c18 113 bestDbr = 1;
mbed_official 146:f64d43ff0c18 114 bestBaudrate = 0; /* required to avoid compilation warning */
mbed_official 146:f64d43ff0c18 115
mbed_official 146:f64d43ff0c18 116 /* In all for loops, if min_diff = 0, the exit for loop*/
mbed_official 146:f64d43ff0c18 117 for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
mbed_official 146:f64d43ff0c18 118 {
mbed_official 146:f64d43ff0c18 119 for (scaler = 0; (scaler < 16) && min_diff; scaler++)
mbed_official 146:f64d43ff0c18 120 {
mbed_official 146:f64d43ff0c18 121 for (dbr = 1; (dbr < 3) && min_diff; dbr++)
mbed_official 146:f64d43ff0c18 122 {
mbed_official 146:f64d43ff0c18 123 realBaudrate = ((sourceClockInHz * dbr) /
mbed_official 146:f64d43ff0c18 124 (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler])));
mbed_official 146:f64d43ff0c18 125
mbed_official 146:f64d43ff0c18 126 /* calculate the baud rate difference based on the conditional statement*/
mbed_official 146:f64d43ff0c18 127 /* that states that the calculated baud rate must not exceed the desired baud rate*/
mbed_official 146:f64d43ff0c18 128 if (baudrate >= realBaudrate)
mbed_official 146:f64d43ff0c18 129 {
mbed_official 146:f64d43ff0c18 130 diff = baudrate-realBaudrate;
mbed_official 146:f64d43ff0c18 131 if (min_diff > diff)
mbed_official 146:f64d43ff0c18 132 {
mbed_official 146:f64d43ff0c18 133 /* a better match found */
mbed_official 146:f64d43ff0c18 134 min_diff = diff;
mbed_official 146:f64d43ff0c18 135 bestPrescaler = prescaler;
mbed_official 146:f64d43ff0c18 136 bestScaler = scaler;
mbed_official 146:f64d43ff0c18 137 bestBaudrate = realBaudrate;
mbed_official 146:f64d43ff0c18 138 bestDbr = dbr;
mbed_official 146:f64d43ff0c18 139 }
mbed_official 146:f64d43ff0c18 140 }
mbed_official 146:f64d43ff0c18 141 }
mbed_official 146:f64d43ff0c18 142 }
mbed_official 146:f64d43ff0c18 143 }
mbed_official 146:f64d43ff0c18 144
mbed_official 146:f64d43ff0c18 145 /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
mbed_official 324:406fd2029f23 146 BW_SPI_CTARn_DBR(baseAddr, whichCtar, (bestDbr - 1));
mbed_official 324:406fd2029f23 147 BW_SPI_CTARn_PBR(baseAddr, whichCtar, bestPrescaler);
mbed_official 324:406fd2029f23 148 BW_SPI_CTARn_BR(baseAddr, whichCtar, bestScaler);
mbed_official 146:f64d43ff0c18 149
mbed_official 146:f64d43ff0c18 150 /* return the actual calculated baud rate*/
mbed_official 146:f64d43ff0c18 151 return bestBaudrate;
mbed_official 146:f64d43ff0c18 152 }
mbed_official 146:f64d43ff0c18 153
mbed_official 146:f64d43ff0c18 154 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 155 *
mbed_official 324:406fd2029f23 156 * Function Name : DSPI_HAL_SetBaudDivisors
mbed_official 146:f64d43ff0c18 157 * Description : Configure the baud rate divisors manually.
mbed_official 146:f64d43ff0c18 158 * This function allows the caller to manually set the baud rate divisors in the event that
mbed_official 324:406fd2029f23 159 * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
mbed_official 146:f64d43ff0c18 160 *
mbed_official 146:f64d43ff0c18 161 *END**************************************************************************/
mbed_official 324:406fd2029f23 162 void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr,
mbed_official 324:406fd2029f23 163 dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 164 const dspi_baud_rate_divisors_t * divisors)
mbed_official 146:f64d43ff0c18 165 {
mbed_official 146:f64d43ff0c18 166 /* these settings are only relevant in master mode*/
mbed_official 324:406fd2029f23 167 if (DSPI_HAL_IsMaster(baseAddr))
mbed_official 146:f64d43ff0c18 168 {
mbed_official 324:406fd2029f23 169 BW_SPI_CTARn_DBR(baseAddr, whichCtar, divisors->doubleBaudRate);
mbed_official 324:406fd2029f23 170 BW_SPI_CTARn_PBR(baseAddr, whichCtar, divisors->prescaleDivisor);
mbed_official 324:406fd2029f23 171 BW_SPI_CTARn_BR(baseAddr, whichCtar, divisors->baudRateDivisor);
mbed_official 146:f64d43ff0c18 172 }
mbed_official 146:f64d43ff0c18 173 }
mbed_official 146:f64d43ff0c18 174
mbed_official 146:f64d43ff0c18 175 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 176 *
mbed_official 324:406fd2029f23 177 * Function Name : DSPI_HAL_SetPcsPolarityMode
mbed_official 146:f64d43ff0c18 178 * Description : Configure DSPI peripheral chip select polarity.
mbed_official 146:f64d43ff0c18 179 * This function will take in the desired peripheral chip select (PCS) and it's
mbed_official 146:f64d43ff0c18 180 * corresponding desired polarity and will configure the PCS signal to operate with the
mbed_official 146:f64d43ff0c18 181 * desired characteristic.
mbed_official 146:f64d43ff0c18 182 *
mbed_official 146:f64d43ff0c18 183 *END**************************************************************************/
mbed_official 324:406fd2029f23 184 void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs,
mbed_official 324:406fd2029f23 185 dspi_pcs_polarity_config_t activeLowOrHigh)
mbed_official 146:f64d43ff0c18 186 {
mbed_official 146:f64d43ff0c18 187 uint32_t temp;
mbed_official 146:f64d43ff0c18 188
mbed_official 324:406fd2029f23 189 temp = BR_SPI_MCR_PCSIS(baseAddr);
mbed_official 146:f64d43ff0c18 190
mbed_official 146:f64d43ff0c18 191 if (activeLowOrHigh == kDspiPcs_ActiveLow)
mbed_official 146:f64d43ff0c18 192 {
mbed_official 146:f64d43ff0c18 193 temp |= pcs;
mbed_official 146:f64d43ff0c18 194 }
mbed_official 146:f64d43ff0c18 195 else /* kDspiPcsPolarity_ActiveHigh*/
mbed_official 146:f64d43ff0c18 196 {
mbed_official 146:f64d43ff0c18 197 temp &= ~(unsigned)pcs;
mbed_official 146:f64d43ff0c18 198 }
mbed_official 146:f64d43ff0c18 199
mbed_official 324:406fd2029f23 200 BW_SPI_MCR_PCSIS(baseAddr, temp);
mbed_official 146:f64d43ff0c18 201 }
mbed_official 146:f64d43ff0c18 202
mbed_official 146:f64d43ff0c18 203
mbed_official 146:f64d43ff0c18 204 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 205 *
mbed_official 324:406fd2029f23 206 * Function Name : DSPI_HAL_SetFifoCmd
mbed_official 324:406fd2029f23 207 * Description : Enables (or disables) the DSPI FIFOs.
mbed_official 146:f64d43ff0c18 208 * This function with allow the caller to disable/enable the TX and RX FIFOs (independently).
mbed_official 324:406fd2029f23 209 * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
mbed_official 324:406fd2029f23 210 * configuration. To enable, the caller must pass in a logic 1 (true).
mbed_official 146:f64d43ff0c18 211 *
mbed_official 146:f64d43ff0c18 212 *END**************************************************************************/
mbed_official 324:406fd2029f23 213 void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo)
mbed_official 146:f64d43ff0c18 214 {
mbed_official 146:f64d43ff0c18 215 /* first see if MDIS is set or cleared */
mbed_official 324:406fd2029f23 216 uint32_t isMdisSet = BR_SPI_MCR_MDIS(baseAddr);
mbed_official 146:f64d43ff0c18 217
mbed_official 146:f64d43ff0c18 218 if (isMdisSet)
mbed_official 146:f64d43ff0c18 219 {
mbed_official 324:406fd2029f23 220 /* clear the MDIS bit (enable DSPI) to allow us to write to the fifo disables */
mbed_official 324:406fd2029f23 221 DSPI_HAL_Enable(baseAddr);
mbed_official 146:f64d43ff0c18 222 }
mbed_official 146:f64d43ff0c18 223
mbed_official 324:406fd2029f23 224 /* Note, the bit definition is "disable FIFO", so a "1" would disable. If user wants to enable
mbed_official 324:406fd2029f23 225 * the FIFOs, they pass in true, which we must logically negate (turn to false) to enable the
mbed_official 324:406fd2029f23 226 * FIFO
mbed_official 324:406fd2029f23 227 */
mbed_official 324:406fd2029f23 228 BW_SPI_MCR_DIS_TXF(baseAddr, ~(enableTxFifo == true));
mbed_official 324:406fd2029f23 229 BW_SPI_MCR_DIS_RXF(baseAddr, ~(enableRxFifo == true));
mbed_official 146:f64d43ff0c18 230
mbed_official 324:406fd2029f23 231 /* set MDIS (disable DSPI) if it was set to begin with */
mbed_official 146:f64d43ff0c18 232 if (isMdisSet)
mbed_official 146:f64d43ff0c18 233 {
mbed_official 324:406fd2029f23 234 DSPI_HAL_Disable(baseAddr);
mbed_official 146:f64d43ff0c18 235 }
mbed_official 146:f64d43ff0c18 236 }
mbed_official 146:f64d43ff0c18 237
mbed_official 146:f64d43ff0c18 238 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 239 *
mbed_official 324:406fd2029f23 240 * Function Name : DSPI_HAL_SetFlushFifoCmd
mbed_official 146:f64d43ff0c18 241 * Description : Flush DSPI fifos.
mbed_official 146:f64d43ff0c18 242 *
mbed_official 146:f64d43ff0c18 243 *END**************************************************************************/
mbed_official 324:406fd2029f23 244 void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo)
mbed_official 146:f64d43ff0c18 245 {
mbed_official 324:406fd2029f23 246 BW_SPI_MCR_CLR_TXF(baseAddr, (enableFlushTxFifo == true));
mbed_official 324:406fd2029f23 247 BW_SPI_MCR_CLR_RXF(baseAddr, (enableFlushRxFifo == true));
mbed_official 146:f64d43ff0c18 248 }
mbed_official 146:f64d43ff0c18 249
mbed_official 146:f64d43ff0c18 250 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 251 *
mbed_official 324:406fd2029f23 252 * Function Name : DSPI_HAL_SetDataFormat
mbed_official 146:f64d43ff0c18 253 * Description : Configure the data format for a particular CTAR.
mbed_official 146:f64d43ff0c18 254 * This function configures the bits-per-frame, polarity, phase, and shift direction for a
mbed_official 146:f64d43ff0c18 255 * particular CTAR. An example use case is as follows:
mbed_official 146:f64d43ff0c18 256 * dspi_data_format_config_t dataFormat;
mbed_official 146:f64d43ff0c18 257 * dataFormat.bitsPerFrame = 16;
mbed_official 146:f64d43ff0c18 258 * dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
mbed_official 146:f64d43ff0c18 259 * dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
mbed_official 146:f64d43ff0c18 260 * dataFormat.direction = kDspiMsbFirst;
mbed_official 324:406fd2029f23 261 * DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &dataFormat);
mbed_official 146:f64d43ff0c18 262 *
mbed_official 146:f64d43ff0c18 263 *END**************************************************************************/
mbed_official 324:406fd2029f23 264 dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr,
mbed_official 324:406fd2029f23 265 dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 266 const dspi_data_format_config_t * config)
mbed_official 146:f64d43ff0c18 267 {
mbed_official 146:f64d43ff0c18 268 /* check bits-per-frame value to make sure it it within the proper range*/
mbed_official 146:f64d43ff0c18 269 /* in either master or slave mode*/
mbed_official 146:f64d43ff0c18 270 if ((config->bitsPerFrame < 4) ||
mbed_official 324:406fd2029f23 271 ((config->bitsPerFrame > 16) && (HW_SPI_MCR(baseAddr).B.MSTR == 1)) ||
mbed_official 324:406fd2029f23 272 ((config->bitsPerFrame > 32) && (HW_SPI_MCR(baseAddr).B.MSTR == 0)))
mbed_official 146:f64d43ff0c18 273 {
mbed_official 146:f64d43ff0c18 274 return kStatus_DSPI_InvalidBitCount;
mbed_official 146:f64d43ff0c18 275 }
mbed_official 146:f64d43ff0c18 276
mbed_official 146:f64d43ff0c18 277 /* for master mode configuration*/
mbed_official 324:406fd2029f23 278 if (DSPI_HAL_IsMaster(baseAddr))
mbed_official 146:f64d43ff0c18 279 {
mbed_official 324:406fd2029f23 280 BW_SPI_CTARn_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
mbed_official 324:406fd2029f23 281 BW_SPI_CTARn_CPOL(baseAddr, whichCtar, config->clkPolarity);
mbed_official 324:406fd2029f23 282 BW_SPI_CTARn_CPHA(baseAddr, whichCtar, config->clkPhase);
mbed_official 324:406fd2029f23 283 BW_SPI_CTARn_LSBFE(baseAddr, whichCtar, config->direction);
mbed_official 146:f64d43ff0c18 284 }
mbed_official 146:f64d43ff0c18 285 else /* for slave mode configuration*/
mbed_official 146:f64d43ff0c18 286 {
mbed_official 324:406fd2029f23 287 BW_SPI_CTARn_SLAVE_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
mbed_official 324:406fd2029f23 288 BW_SPI_CTARn_SLAVE_CPOL(baseAddr, whichCtar, config->clkPolarity);
mbed_official 324:406fd2029f23 289 BW_SPI_CTARn_SLAVE_CPHA(baseAddr, whichCtar, config->clkPhase);
mbed_official 146:f64d43ff0c18 290 }
mbed_official 146:f64d43ff0c18 291 return kStatus_DSPI_Success;
mbed_official 146:f64d43ff0c18 292 }
mbed_official 146:f64d43ff0c18 293
mbed_official 146:f64d43ff0c18 294 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 295 *
mbed_official 324:406fd2029f23 296 * Function Name : DSPI_HAL_SetDelay
mbed_official 324:406fd2029f23 297 * Description : Manually configures the delay prescaler and scaler for a particular CTAR.
mbed_official 324:406fd2029f23 298 * This function configures the:
mbed_official 324:406fd2029f23 299 * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
mbed_official 324:406fd2029f23 300 * After SCK delay pre-scalar (PASC) and scalar (ASC),
mbed_official 324:406fd2029f23 301 * Delay after transfer pre-scalar (PDT)and scalar (DT).
mbed_official 146:f64d43ff0c18 302 *
mbed_official 324:406fd2029f23 303 * These delay names are available in type dspi_delay_type_t.
mbed_official 324:406fd2029f23 304 *
mbed_official 324:406fd2029f23 305 * The user passes which delay they want to configure along with the prescaler and scaler value.
mbed_official 324:406fd2029f23 306 * This basically allows the user to directly set the prescaler/scaler values if they have
mbed_official 324:406fd2029f23 307 * pre-calculated them or if they simply wish to manually increment either value.
mbed_official 146:f64d43ff0c18 308 *END**************************************************************************/
mbed_official 324:406fd2029f23 309 void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
mbed_official 324:406fd2029f23 310 uint32_t scaler, dspi_delay_type_t whichDelay)
mbed_official 146:f64d43ff0c18 311 {
mbed_official 146:f64d43ff0c18 312 /* these settings are only relevant in master mode*/
mbed_official 324:406fd2029f23 313 if (DSPI_HAL_IsMaster(baseAddr))
mbed_official 146:f64d43ff0c18 314 {
mbed_official 324:406fd2029f23 315 if (whichDelay == kDspiPcsToSck)
mbed_official 324:406fd2029f23 316 {
mbed_official 324:406fd2029f23 317 BW_SPI_CTARn_PCSSCK(baseAddr, whichCtar, prescaler);
mbed_official 324:406fd2029f23 318 BW_SPI_CTARn_CSSCK(baseAddr, whichCtar, scaler);
mbed_official 324:406fd2029f23 319 }
mbed_official 324:406fd2029f23 320
mbed_official 324:406fd2029f23 321 if (whichDelay == kDspiLastSckToPcs)
mbed_official 324:406fd2029f23 322 {
mbed_official 324:406fd2029f23 323 BW_SPI_CTARn_PASC(baseAddr, whichCtar, prescaler);
mbed_official 324:406fd2029f23 324 BW_SPI_CTARn_ASC(baseAddr, whichCtar, scaler);
mbed_official 324:406fd2029f23 325 }
mbed_official 324:406fd2029f23 326
mbed_official 324:406fd2029f23 327 if (whichDelay == kDspiAfterTransfer)
mbed_official 324:406fd2029f23 328 {
mbed_official 324:406fd2029f23 329 BW_SPI_CTARn_PDT(baseAddr, whichCtar, prescaler);
mbed_official 324:406fd2029f23 330 BW_SPI_CTARn_DT(baseAddr, whichCtar, scaler);
mbed_official 324:406fd2029f23 331 }
mbed_official 146:f64d43ff0c18 332 }
mbed_official 146:f64d43ff0c18 333 }
mbed_official 146:f64d43ff0c18 334
mbed_official 146:f64d43ff0c18 335 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 336 *
mbed_official 324:406fd2029f23 337 * Function Name : DSPI_HAL_CalculateDelay
mbed_official 324:406fd2029f23 338 * Description : Calculates the delay prescaler and scaler based on desired delay input in
mbed_official 324:406fd2029f23 339 * nano-seconds.
mbed_official 324:406fd2029f23 340 *
mbed_official 324:406fd2029f23 341 * This function calculates the values for:
mbed_official 324:406fd2029f23 342 * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
mbed_official 324:406fd2029f23 343 * After SCK delay pre-scalar (PASC) and scalar (ASC), or
mbed_official 324:406fd2029f23 344 * Delay after transfer pre-scalar (PDT)and scalar (DT).
mbed_official 324:406fd2029f23 345 *
mbed_official 324:406fd2029f23 346 * These delay names are available in type dspi_delay_type_t.
mbed_official 324:406fd2029f23 347 *
mbed_official 324:406fd2029f23 348 * The user passes which delay they want to configure along with the desired delay value in
mbed_official 324:406fd2029f23 349 * nano-seconds. The function will calculate the values needed for the prescaler and scaler and
mbed_official 324:406fd2029f23 350 * will return the actual calculated delay as an exact delay match may not be acheivable. In this
mbed_official 324:406fd2029f23 351 * case, the closest match will be calculated without going below the desired delay value input.
mbed_official 324:406fd2029f23 352 * It is possible to input a very large delay value that exceeds the capability of the part, in
mbed_official 324:406fd2029f23 353 * which case the maximum supported delay will be returned. It will be up to the higher level
mbed_official 324:406fd2029f23 354 * peripheral driver to alert the user of an out of range delay input.
mbed_official 324:406fd2029f23 355 *END**************************************************************************/
mbed_official 324:406fd2029f23 356 uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 357 dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
mbed_official 324:406fd2029f23 358 uint32_t delayInNanoSec)
mbed_official 324:406fd2029f23 359 {
mbed_official 324:406fd2029f23 360 /* for master mode configuration, if slave mode detected, return 0*/
mbed_official 324:406fd2029f23 361 if (!DSPI_HAL_IsMaster(baseAddr))
mbed_official 324:406fd2029f23 362 {
mbed_official 324:406fd2029f23 363 return 0;
mbed_official 324:406fd2029f23 364 }
mbed_official 324:406fd2029f23 365
mbed_official 324:406fd2029f23 366 uint32_t prescaler, bestPrescaler;
mbed_official 324:406fd2029f23 367 uint32_t scaler, bestScaler;
mbed_official 324:406fd2029f23 368 uint32_t realDelay, bestDelay;
mbed_official 324:406fd2029f23 369 uint32_t diff, min_diff;
mbed_official 324:406fd2029f23 370 uint32_t initialDelayNanoSec;
mbed_official 324:406fd2029f23 371
mbed_official 324:406fd2029f23 372 /* find combination of prescaler and scaler resulting in the delay closest to the
mbed_official 324:406fd2029f23 373 * requested value
mbed_official 324:406fd2029f23 374 */
mbed_official 324:406fd2029f23 375 min_diff = 0xFFFFFFFFU;
mbed_official 324:406fd2029f23 376 /* Initialize prescaler and scaler to their max values to generate the max delay */
mbed_official 324:406fd2029f23 377 bestPrescaler = 0x3;
mbed_official 324:406fd2029f23 378 bestScaler = 0xF;
mbed_official 324:406fd2029f23 379 bestDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[bestPrescaler] *
mbed_official 324:406fd2029f23 380 s_delayScaler[bestScaler];
mbed_official 324:406fd2029f23 381
mbed_official 324:406fd2029f23 382 /* First calculate the initial, default delay */
mbed_official 324:406fd2029f23 383 initialDelayNanoSec = 1000000000/sourceClockInHz * 2;
mbed_official 324:406fd2029f23 384
mbed_official 324:406fd2029f23 385 /* If the initial, default delay is already greater than the desired delay, then
mbed_official 324:406fd2029f23 386 * set the delays to their initial value (0) and return the delay. In other words,
mbed_official 324:406fd2029f23 387 * there is no way to decrease the delay value further.
mbed_official 324:406fd2029f23 388 */
mbed_official 324:406fd2029f23 389 if (initialDelayNanoSec >= delayInNanoSec)
mbed_official 324:406fd2029f23 390 {
mbed_official 324:406fd2029f23 391 DSPI_HAL_SetDelay(baseAddr, whichCtar, 0, 0, whichDelay);
mbed_official 324:406fd2029f23 392 return initialDelayNanoSec;
mbed_official 324:406fd2029f23 393 }
mbed_official 324:406fd2029f23 394
mbed_official 324:406fd2029f23 395
mbed_official 324:406fd2029f23 396 /* In all for loops, if min_diff = 0, the exit for loop*/
mbed_official 324:406fd2029f23 397 for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
mbed_official 324:406fd2029f23 398 {
mbed_official 324:406fd2029f23 399 for (scaler = 0; (scaler < 16) && min_diff; scaler++)
mbed_official 324:406fd2029f23 400 {
mbed_official 324:406fd2029f23 401 realDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[prescaler] *
mbed_official 324:406fd2029f23 402 s_delayScaler[scaler];
mbed_official 324:406fd2029f23 403
mbed_official 324:406fd2029f23 404 /* calculate the delay difference based on the conditional statement
mbed_official 324:406fd2029f23 405 * that states that the calculated delay must not be less then the desired delay
mbed_official 324:406fd2029f23 406 */
mbed_official 324:406fd2029f23 407 if (realDelay >= delayInNanoSec)
mbed_official 324:406fd2029f23 408 {
mbed_official 324:406fd2029f23 409 diff = realDelay-delayInNanoSec;
mbed_official 324:406fd2029f23 410 if (min_diff > diff)
mbed_official 324:406fd2029f23 411 {
mbed_official 324:406fd2029f23 412 /* a better match found */
mbed_official 324:406fd2029f23 413 min_diff = diff;
mbed_official 324:406fd2029f23 414 bestPrescaler = prescaler;
mbed_official 324:406fd2029f23 415 bestScaler = scaler;
mbed_official 324:406fd2029f23 416 bestDelay = realDelay;
mbed_official 324:406fd2029f23 417 }
mbed_official 324:406fd2029f23 418 }
mbed_official 324:406fd2029f23 419 }
mbed_official 324:406fd2029f23 420 }
mbed_official 324:406fd2029f23 421
mbed_official 324:406fd2029f23 422 /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
mbed_official 324:406fd2029f23 423 DSPI_HAL_SetDelay(baseAddr, whichCtar, bestPrescaler, bestScaler, whichDelay);
mbed_official 324:406fd2029f23 424
mbed_official 324:406fd2029f23 425 /* return the actual calculated baud rate*/
mbed_official 324:406fd2029f23 426 return bestDelay;
mbed_official 324:406fd2029f23 427 }
mbed_official 324:406fd2029f23 428
mbed_official 324:406fd2029f23 429
mbed_official 324:406fd2029f23 430 /*FUNCTION**********************************************************************
mbed_official 324:406fd2029f23 431 *
mbed_official 324:406fd2029f23 432 * Function Name : DSPI_HAL_SetTxFifoFillDmaIntMode
mbed_official 324:406fd2029f23 433 * Description : Configures the DSPI Tx FIFO Fill request to generate DMA or interrupt requests.
mbed_official 324:406fd2029f23 434 * This function configures the DSPI Tx FIFO Fill flag to generate either
mbed_official 324:406fd2029f23 435 * an interrupt or DMA request. The user passes in which request they'd like to generate
mbed_official 324:406fd2029f23 436 * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
mbed_official 324:406fd2029f23 437 * Note, when disabling the request, the request type is don't care.
mbed_official 324:406fd2029f23 438 *
mbed_official 324:406fd2029f23 439 * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
mbed_official 324:406fd2029f23 440 * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
mbed_official 324:406fd2029f23 441 * DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
mbed_official 146:f64d43ff0c18 442 *
mbed_official 146:f64d43ff0c18 443 *END**************************************************************************/
mbed_official 324:406fd2029f23 444 void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
mbed_official 146:f64d43ff0c18 445 {
mbed_official 324:406fd2029f23 446 BW_SPI_RSER_TFFF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */
mbed_official 324:406fd2029f23 447 BW_SPI_RSER_TFFF_RE(baseAddr, (enable == true)); /* Enable or disable the request */
mbed_official 146:f64d43ff0c18 448 }
mbed_official 146:f64d43ff0c18 449
mbed_official 146:f64d43ff0c18 450 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 451 *
mbed_official 324:406fd2029f23 452 * Function Name : DSPI_HAL_SetRxFifoDrainDmaIntMode
mbed_official 324:406fd2029f23 453 * Description : Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
mbed_official 324:406fd2029f23 454 * This function configures the DSPI Rx FIFO Drain flag to generate either
mbed_official 324:406fd2029f23 455 * an interrupt or DMA request. The user passes in which request they'd like to generate
mbed_official 324:406fd2029f23 456 * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
mbed_official 324:406fd2029f23 457 * Note, when disabling the request, the request type is don't care.
mbed_official 146:f64d43ff0c18 458 *
mbed_official 324:406fd2029f23 459 * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
mbed_official 324:406fd2029f23 460 * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
mbed_official 324:406fd2029f23 461 * DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
mbed_official 146:f64d43ff0c18 462 *
mbed_official 146:f64d43ff0c18 463 *END**************************************************************************/
mbed_official 324:406fd2029f23 464 void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
mbed_official 324:406fd2029f23 465 {
mbed_official 324:406fd2029f23 466 BW_SPI_RSER_RFDF_DIRS(baseAddr, mode); /* Configure as DMA or interrupt */
mbed_official 324:406fd2029f23 467 BW_SPI_RSER_RFDF_RE(baseAddr, (enable == true)); /* Enable or disable the request */
mbed_official 324:406fd2029f23 468 }
mbed_official 324:406fd2029f23 469
mbed_official 324:406fd2029f23 470
mbed_official 324:406fd2029f23 471 /*FUNCTION**********************************************************************
mbed_official 324:406fd2029f23 472 *
mbed_official 324:406fd2029f23 473 * Function Name : DSPI_HAL_SetIntMode
mbed_official 324:406fd2029f23 474 * Description : Configure DSPI interrupts.
mbed_official 324:406fd2029f23 475 * This function configures the various interrupt sources of the DSPI. The parameters are
mbed_official 324:406fd2029f23 476 * baseAddr, interrupt source, and enable/disable setting.
mbed_official 324:406fd2029f23 477 * The interrupt source is a typedef enum whose value is the bit position of the
mbed_official 324:406fd2029f23 478 * interrupt source setting within the RSER register. In the DSPI, all interrupt
mbed_official 324:406fd2029f23 479 * configuration settings are in one register. The typedef enum equates each
mbed_official 324:406fd2029f23 480 * interrupt source to the bit position defined in the device header file.
mbed_official 324:406fd2029f23 481 * The function uses these bit positions in its algorithm to enable/disable the
mbed_official 324:406fd2029f23 482 * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
mbed_official 324:406fd2029f23 483 * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
mbed_official 324:406fd2029f23 484 * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
mbed_official 324:406fd2029f23 485 * these requests can generate either an interrupt or DMA request.
mbed_official 324:406fd2029f23 486 *
mbed_official 324:406fd2029f23 487 * DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case
mbed_official 324:406fd2029f23 488 *
mbed_official 324:406fd2029f23 489 *END**************************************************************************/
mbed_official 324:406fd2029f23 490 void DSPI_HAL_SetIntMode(uint32_t baseAddr,
mbed_official 146:f64d43ff0c18 491 dspi_status_and_interrupt_request_t interruptSrc,
mbed_official 146:f64d43ff0c18 492 bool enable)
mbed_official 146:f64d43ff0c18 493 {
mbed_official 146:f64d43ff0c18 494 uint32_t temp;
mbed_official 146:f64d43ff0c18 495
mbed_official 324:406fd2029f23 496 temp = (HW_SPI_RSER_RD(baseAddr) & ~(0x1U << interruptSrc)) |
mbed_official 324:406fd2029f23 497 ((uint32_t)enable << interruptSrc);
mbed_official 324:406fd2029f23 498 HW_SPI_RSER_WR(baseAddr, temp);
mbed_official 146:f64d43ff0c18 499 }
mbed_official 146:f64d43ff0c18 500
mbed_official 146:f64d43ff0c18 501 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 502 *
mbed_official 324:406fd2029f23 503 * Function Name : DSPI_HAL_GetFifoData
mbed_official 146:f64d43ff0c18 504 * Description : Read fifo registers for debug purposes.
mbed_official 146:f64d43ff0c18 505 *
mbed_official 146:f64d43ff0c18 506 *END**************************************************************************/
mbed_official 324:406fd2029f23 507 uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry)
mbed_official 146:f64d43ff0c18 508 {
mbed_official 146:f64d43ff0c18 509 if (whichFifo == kDspiTxFifo)
mbed_official 146:f64d43ff0c18 510 {
mbed_official 324:406fd2029f23 511 return HW_SPI_TXFRn_RD(baseAddr, whichFifoEntry);
mbed_official 146:f64d43ff0c18 512 }
mbed_official 146:f64d43ff0c18 513 else
mbed_official 146:f64d43ff0c18 514 {
mbed_official 324:406fd2029f23 515 return HW_SPI_RXFRn_RD(baseAddr, whichFifoEntry);
mbed_official 146:f64d43ff0c18 516 }
mbed_official 146:f64d43ff0c18 517 }
mbed_official 146:f64d43ff0c18 518
mbed_official 146:f64d43ff0c18 519 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 520 *
mbed_official 324:406fd2029f23 521 * Function Name : DSPI_HAL_WriteDataMastermode
mbed_official 146:f64d43ff0c18 522 * Description : Write data into the data buffer, master mode.
mbed_official 146:f64d43ff0c18 523 * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
mbed_official 146:f64d43ff0c18 524 * provides characteristics of the data being sent such as: optional continuous chip select
mbed_official 146:f64d43ff0c18 525 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
mbed_official 146:f64d43ff0c18 526 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
mbed_official 146:f64d43ff0c18 527 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
mbed_official 146:f64d43ff0c18 528 * sending the first frame of a data packet). An example use case is as follows:
mbed_official 146:f64d43ff0c18 529 * dspi_command_config_t commandConfig;
mbed_official 146:f64d43ff0c18 530 * commandConfig.isChipSelectContinuous = true;
mbed_official 146:f64d43ff0c18 531 * commandConfig.whichCtar = kDspiCtar0;
mbed_official 146:f64d43ff0c18 532 * commandConfig.whichPcs = kDspiPcs1;
mbed_official 146:f64d43ff0c18 533 * commandConfig.clearTransferCount = false;
mbed_official 146:f64d43ff0c18 534 * commandConfig.isEndOfQueue = false;
mbed_official 324:406fd2029f23 535 * DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
mbed_official 146:f64d43ff0c18 536 *
mbed_official 146:f64d43ff0c18 537 *END**************************************************************************/
mbed_official 324:406fd2029f23 538 void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr,
mbed_official 324:406fd2029f23 539 dspi_command_config_t * command,
mbed_official 324:406fd2029f23 540 uint16_t data)
mbed_official 146:f64d43ff0c18 541 {
mbed_official 146:f64d43ff0c18 542 uint32_t temp;
mbed_official 146:f64d43ff0c18 543
mbed_official 324:406fd2029f23 544 /* First, build up the 32-bit word then write it to the PUSHR */
mbed_official 146:f64d43ff0c18 545 temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
mbed_official 146:f64d43ff0c18 546 BF_SPI_PUSHR_CTAS(command->whichCtar) |
mbed_official 146:f64d43ff0c18 547 BF_SPI_PUSHR_PCS(command->whichPcs) |
mbed_official 146:f64d43ff0c18 548 BF_SPI_PUSHR_EOQ(command->isEndOfQueue) |
mbed_official 146:f64d43ff0c18 549 BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
mbed_official 146:f64d43ff0c18 550 BF_SPI_PUSHR_TXDATA(data);
mbed_official 146:f64d43ff0c18 551
mbed_official 324:406fd2029f23 552 HW_SPI_PUSHR_WR(baseAddr, temp);
mbed_official 324:406fd2029f23 553 }
mbed_official 324:406fd2029f23 554
mbed_official 324:406fd2029f23 555 /*FUNCTION**********************************************************************
mbed_official 324:406fd2029f23 556 *
mbed_official 324:406fd2029f23 557 * Function Name : DSPI_HAL_WriteDataMastermode
mbed_official 324:406fd2029f23 558 * Description : Write data into the data buffer, master mode and waits till complete to return.
mbed_official 324:406fd2029f23 559 * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
mbed_official 324:406fd2029f23 560 * provides characteristics of the data being sent such as: optional continuous chip select
mbed_official 324:406fd2029f23 561 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
mbed_official 324:406fd2029f23 562 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
mbed_official 324:406fd2029f23 563 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
mbed_official 324:406fd2029f23 564 * sending the first frame of a data packet). An example use case is as follows:
mbed_official 324:406fd2029f23 565 * dspi_command_config_t commandConfig;
mbed_official 324:406fd2029f23 566 * commandConfig.isChipSelectContinuous = true;
mbed_official 324:406fd2029f23 567 * commandConfig.whichCtar = kDspiCtar0;
mbed_official 324:406fd2029f23 568 * commandConfig.whichPcs = kDspiPcs1;
mbed_official 324:406fd2029f23 569 * commandConfig.clearTransferCount = false;
mbed_official 324:406fd2029f23 570 * commandConfig.isEndOfQueue = false;
mbed_official 324:406fd2029f23 571 * DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
mbed_official 324:406fd2029f23 572 *
mbed_official 324:406fd2029f23 573 * Note that this function will not return until after the transmit is complete. Also note that
mbed_official 324:406fd2029f23 574 * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
mbed_official 324:406fd2029f23 575 * Since the SPI is a synchronous protocol, receive data will be available when transmit completes.
mbed_official 324:406fd2029f23 576 *
mbed_official 324:406fd2029f23 577 *END**************************************************************************/
mbed_official 324:406fd2029f23 578 void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr,
mbed_official 324:406fd2029f23 579 dspi_command_config_t * command,
mbed_official 324:406fd2029f23 580 uint16_t data)
mbed_official 324:406fd2029f23 581 {
mbed_official 324:406fd2029f23 582 uint32_t temp;
mbed_official 324:406fd2029f23 583
mbed_official 324:406fd2029f23 584 /* First, clear Transmit Complete Flag (TCF) */
mbed_official 324:406fd2029f23 585 BW_SPI_SR_TCF(baseAddr, 1);
mbed_official 324:406fd2029f23 586
mbed_official 324:406fd2029f23 587 /* First, build up the 32-bit word then write it to the PUSHR */
mbed_official 324:406fd2029f23 588 temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
mbed_official 324:406fd2029f23 589 BF_SPI_PUSHR_CTAS(command->whichCtar) |
mbed_official 324:406fd2029f23 590 BF_SPI_PUSHR_PCS(command->whichPcs) |
mbed_official 324:406fd2029f23 591 BF_SPI_PUSHR_EOQ(command->isEndOfQueue) |
mbed_official 324:406fd2029f23 592 BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
mbed_official 324:406fd2029f23 593 BF_SPI_PUSHR_TXDATA(data);
mbed_official 324:406fd2029f23 594
mbed_official 324:406fd2029f23 595 HW_SPI_PUSHR_WR(baseAddr, temp);
mbed_official 324:406fd2029f23 596
mbed_official 324:406fd2029f23 597 /* Wait till TCF sets */
mbed_official 324:406fd2029f23 598 while(BR_SPI_SR_TCF(baseAddr) == 0) { }
mbed_official 146:f64d43ff0c18 599 }
mbed_official 146:f64d43ff0c18 600
mbed_official 146:f64d43ff0c18 601 /*******************************************************************************
mbed_official 146:f64d43ff0c18 602 * EOF
mbed_official 146:f64d43ff0c18 603 ******************************************************************************/
mbed_official 146:f64d43ff0c18 604