Matt Lloyd
/
DMA_UART_example
Example of UART-DMA transfers taken form the npx cmsis driver libary
Revision 0:7480abd3b63b, committed 2010-09-30
- Comitter:
- dpslwk
- Date:
- Thu Sep 30 20:13:24 2010 +0000
- Commit message:
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/debug_frmwrk.c Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,305 @@ +/***********************************************************************//** + * @file debug_frmwrk.c + * @brief Contains some utilities that used for debugging through UART + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + *---------------------------------------------------------------------------- + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ + +#include "debug_frmwrk.h" +#include "lpc17xx_pinsel.h" + +/* If this source file built with example, the LPC17xx FW library configuration + * file in each example directory ("lpc17xx_libcfg.h") must be included, + * otherwise the default FW library configuration file must be included instead + */ +#ifdef __BUILD_WITH_EXAMPLE__ +#include "lpc17xx_libcfg.h" +#else +#include "lpc17xx_libcfg_default.h" +#endif /* __BUILD_WITH_EXAMPLE__ */ + +#ifdef _DBGFWK +/* Debug framework */ + +void (*_db_msg)(LPC_UART_TypeDef *UARTx, const void *s); +void (*_db_msg_)(LPC_UART_TypeDef *UARTx, const void *s); +void (*_db_char)(LPC_UART_TypeDef *UARTx, uint8_t ch); +void (*_db_dec)(LPC_UART_TypeDef *UARTx, uint8_t decn); +void (*_db_dec_16)(LPC_UART_TypeDef *UARTx, uint16_t decn); +void (*_db_dec_32)(LPC_UART_TypeDef *UARTx, uint32_t decn); +void (*_db_hex)(LPC_UART_TypeDef *UARTx, uint8_t hexn); +void (*_db_hex_16)(LPC_UART_TypeDef *UARTx, uint16_t hexn); +void (*_db_hex_32)(LPC_UART_TypeDef *UARTx, uint32_t hexn); +uint8_t (*_db_get_char)(LPC_UART_TypeDef *UARTx); + + +/*********************************************************************//** + * @brief Puts a character to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] ch Character to put + * @return None + **********************************************************************/ +void UARTPutChar (LPC_UART_TypeDef *UARTx, uint8_t ch) +{ + UART_Send(UARTx, &ch, 1, BLOCKING); +} + + +/*********************************************************************//** + * @brief Get a character to UART port + * @param[in] UARTx Pointer to UART peripheral + * @return character value that returned + **********************************************************************/ +uint8_t UARTGetChar (LPC_UART_TypeDef *UARTx) +{ + uint8_t tmp = 0; + UART_Receive(UARTx, &tmp, 1, BLOCKING); + return(tmp); +} + + +/*********************************************************************//** + * @brief Puts a string to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] str string to put + * @return None + **********************************************************************/ +void UARTPuts(LPC_UART_TypeDef *UARTx, const void *str) +{ + uint8_t *s = (uint8_t *) str; + + while (*s) + { + UARTPutChar(UARTx, *s++); + } +} + + +/*********************************************************************//** + * @brief Puts a string to UART port and print new line + * @param[in] UARTx Pointer to UART peripheral + * @param[in] str String to put + * @return None + **********************************************************************/ +void UARTPuts_(LPC_UART_TypeDef *UARTx, const void *str) +{ + UARTPuts (UARTx, str); + UARTPuts (UARTx, "\n\r"); +} + + +/*********************************************************************//** + * @brief Puts a decimal number to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] decnum Decimal number (8-bit long) + * @return None + **********************************************************************/ +void UARTPutDec(LPC_UART_TypeDef *UARTx, uint8_t decnum) +{ + uint8_t c1=decnum%10; + uint8_t c2=(decnum/10)%10; + uint8_t c3=(decnum/100)%10; + UARTPutChar(UARTx, '0'+c3); + UARTPutChar(UARTx, '0'+c2); + UARTPutChar(UARTx, '0'+c1); +} + +/*********************************************************************//** + * @brief Puts a decimal number to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] decnum Decimal number (8-bit long) + * @return None + **********************************************************************/ +void UARTPutDec16(LPC_UART_TypeDef *UARTx, uint16_t decnum) +{ + uint8_t c1=decnum%10; + uint8_t c2=(decnum/10)%10; + uint8_t c3=(decnum/100)%10; + uint8_t c4=(decnum/1000)%10; + uint8_t c5=(decnum/10000)%10; + UARTPutChar(UARTx, '0'+c5); + UARTPutChar(UARTx, '0'+c4); + UARTPutChar(UARTx, '0'+c3); + UARTPutChar(UARTx, '0'+c2); + UARTPutChar(UARTx, '0'+c1); +} + +/*********************************************************************//** + * @brief Puts a decimal number to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] decnum Decimal number (8-bit long) + * @return None + **********************************************************************/ +void UARTPutDec32(LPC_UART_TypeDef *UARTx, uint32_t decnum) +{ + uint8_t c1=decnum%10; + uint8_t c2=(decnum/10)%10; + uint8_t c3=(decnum/100)%10; + uint8_t c4=(decnum/1000)%10; + uint8_t c5=(decnum/10000)%10; + uint8_t c6=(decnum/100000)%10; + uint8_t c7=(decnum/1000000)%10; + uint8_t c8=(decnum/10000000)%10; + uint8_t c9=(decnum/100000000)%10; + uint8_t c10=(decnum/100000000)%10; + UARTPutChar(UARTx, '0'+c10); + UARTPutChar(UARTx, '0'+c9); + UARTPutChar(UARTx, '0'+c8); + UARTPutChar(UARTx, '0'+c7); + UARTPutChar(UARTx, '0'+c6); + UARTPutChar(UARTx, '0'+c5); + UARTPutChar(UARTx, '0'+c4); + UARTPutChar(UARTx, '0'+c3); + UARTPutChar(UARTx, '0'+c2); + UARTPutChar(UARTx, '0'+c1); +} + +/*********************************************************************//** + * @brief Puts a hex number to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] hexnum Hex number (8-bit long) + * @return None + **********************************************************************/ +void UARTPutHex (LPC_UART_TypeDef *UARTx, uint8_t hexnum) +{ + uint8_t nibble, i; + + UARTPuts(UARTx, "0x"); + i = 1; + do { + nibble = (hexnum >> (4*i)) & 0x0F; + UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble)); + } while (i--); +} + + +/*********************************************************************//** + * @brief Puts a hex number to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] hexnum Hex number (16-bit long) + * @return None + **********************************************************************/ +void UARTPutHex16 (LPC_UART_TypeDef *UARTx, uint16_t hexnum) +{ + uint8_t nibble, i; + + UARTPuts(UARTx, "0x"); + i = 3; + do { + nibble = (hexnum >> (4*i)) & 0x0F; + UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble)); + } while (i--); +} + +/*********************************************************************//** + * @brief Puts a hex number to UART port + * @param[in] UARTx Pointer to UART peripheral + * @param[in] hexnum Hex number (32-bit long) + * @return None + **********************************************************************/ +void UARTPutHex32 (LPC_UART_TypeDef *UARTx, uint32_t hexnum) +{ + uint8_t nibble, i; + + UARTPuts(UARTx, "0x"); + i = 7; + do { + nibble = (hexnum >> (4*i)) & 0x0F; + UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble)); + } while (i--); +} + +///*********************************************************************//** +// * @brief print function that supports format as same as printf() +// * function of <stdio.h> library +// * @param[in] None +// * @return None +// **********************************************************************/ +//void _printf (const char *format, ...) +//{ +// static char buffer[512 + 1]; +// va_list vArgs; +// char *tmp; +// va_start(vArgs, format); +// vsprintf((char *)buffer, (char const *)format, vArgs); +// va_end(vArgs); +// +// _DBG(buffer); +//} + +/*********************************************************************//** + * @brief Initialize Debug frame work through initializing UART port + * @param[in] None + * @return None + **********************************************************************/ +void debug_frmwrk_init(void) +{ + UART_CFG_Type UARTConfigStruct; + PINSEL_CFG_Type PinCfg; + +#if (USED_UART_DEBUG_PORT==0) + /* + * Initialize UART0 pin connect + */ + PinCfg.Funcnum = 1; + PinCfg.OpenDrain = 0; + PinCfg.Pinmode = 0; + PinCfg.Pinnum = 2; + PinCfg.Portnum = 0; + PINSEL_ConfigPin(&PinCfg); + PinCfg.Pinnum = 3; + PINSEL_ConfigPin(&PinCfg); +#elif #if (USED_UART_DEBUG_PORT==1) + /* + * Initialize UART1 pin connect + */ + PinCfg.Funcnum = 1; + PinCfg.OpenDrain = 0; + PinCfg.Pinmode = 0; + PinCfg.Pinnum = 15; + PinCfg.Portnum = 0; + PINSEL_ConfigPin(&PinCfg); + PinCfg.Pinnum = 16; + PINSEL_ConfigPin(&PinCfg); +#endif + + /* Initialize UART Configuration parameter structure to default state: + * Baudrate = 9600bps + * 8 data bit + * 1 Stop bit + * None parity + */ + UART_ConfigStructInit(&UARTConfigStruct); + // Re-configure baudrate to 115200bps + UARTConfigStruct.Baud_rate = 115200; + + // Initialize DEBUG_UART_PORT peripheral with given to corresponding parameter + UART_Init((LPC_UART_TypeDef *)DEBUG_UART_PORT, &UARTConfigStruct); + + // Enable UART Transmit + UART_TxCmd((LPC_UART_TypeDef *)DEBUG_UART_PORT, ENABLE); + + _db_msg = UARTPuts; + _db_msg_ = UARTPuts_; + _db_char = UARTPutChar; + _db_hex = UARTPutHex; + _db_hex_16 = UARTPutHex16; + _db_hex_32 = UARTPutHex32; + _db_dec = UARTPutDec; + _db_dec_16 = UARTPutDec16; + _db_dec_32 = UARTPutDec32; + _db_get_char = UARTGetChar; +} +#endif /*_DBGFWK */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/debug_frmwrk.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,69 @@ +/***********************************************************************//** + * @file debug_frmwrk.h + * @brief Contains some utilities that used for debugging through UART + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + *---------------------------------------------------------------------------- + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ + +#ifndef DEBUG_FRMWRK_H_ +#define DEBUG_FRMWRK_H_ + +//#include <stdarg.h> +#include "lpc17xx_uart.h" + +#define USED_UART_DEBUG_PORT 0 + +#if (USED_UART_DEBUG_PORT==0) +#define DEBUG_UART_PORT LPC_UART0 +#elif (USED_UART_DEBUG_PORT==1) +#define DEBUG_UART_PORT LPC_UART1 +#endif + +#define _DBG(x) _db_msg(DEBUG_UART_PORT, x) +#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x) +#define _DBC(x) _db_char(DEBUG_UART_PORT, x) +#define _DBD(x) _db_dec(DEBUG_UART_PORT, x) +#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x) +#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x) +#define _DBH(x) _db_hex(DEBUG_UART_PORT, x) +#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x) +#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x) +#define _DG _db_get_char(DEBUG_UART_PORT) +//void _printf (const char *format, ...); + +extern void (*_db_msg)(LPC_UART_TypeDef *UARTx, const void *s); +extern void (*_db_msg_)(LPC_UART_TypeDef *UARTx, const void *s); +extern void (*_db_char)(LPC_UART_TypeDef *UARTx, uint8_t ch); +extern void (*_db_dec)(LPC_UART_TypeDef *UARTx, uint8_t decn); +extern void (*_db_dec_16)(LPC_UART_TypeDef *UARTx, uint16_t decn); +extern void (*_db_dec_32)(LPC_UART_TypeDef *UARTx, uint32_t decn); +extern void (*_db_hex)(LPC_UART_TypeDef *UARTx, uint8_t hexn); +extern void (*_db_hex_16)(LPC_UART_TypeDef *UARTx, uint16_t hexn); +extern void (*_db_hex_32)(LPC_UART_TypeDef *UARTx, uint32_t hexn); +extern uint8_t (*_db_get_char)(LPC_UART_TypeDef *UARTx); + +void UARTPutChar (LPC_UART_TypeDef *UARTx, uint8_t ch); +void UARTPuts(LPC_UART_TypeDef *UARTx, const void *str); +void UARTPuts_(LPC_UART_TypeDef *UARTx, const void *str); +void UARTPutDec(LPC_UART_TypeDef *UARTx, uint8_t decnum); +void UARTPutDec16(LPC_UART_TypeDef *UARTx, uint16_t decnum); +void UARTPutDec32(LPC_UART_TypeDef *UARTx, uint32_t decnum); +void UARTPutHex (LPC_UART_TypeDef *UARTx, uint8_t hexnum); +void UARTPutHex16 (LPC_UART_TypeDef *UARTx, uint16_t hexnum); +void UARTPutHex32 (LPC_UART_TypeDef *UARTx, uint32_t hexnum); +uint8_t UARTGetChar (LPC_UART_TypeDef *UARTx); +void debug_frmwrk_init(void); + +#endif /* DEBUG_FRMWRK_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_clkpwr.c Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,338 @@ +/***********************************************************************//** + * @file lpc17xx_clkpwr.c + * @brief Contains all functions support for Clock and Power Control + * firmware library on LPC17xx + * @version 3.0 + * @date 18. June. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @addtogroup CLKPWR + * @{ + */ + +/* Includes ------------------------------------------------------------------- */ +#include "lpc17xx_clkpwr.h" + + +/* Public Functions ----------------------------------------------------------- */ +/** @addtogroup CLKPWR_Public_Functions + * @{ + */ + +/*********************************************************************//** + * @brief Set value of each Peripheral Clock Selection + * @param[in] ClkType Peripheral Clock Selection of each type, + * should be one of the following: + * - CLKPWR_PCLKSEL_WDT : WDT + - CLKPWR_PCLKSEL_TIMER0 : Timer 0 + - CLKPWR_PCLKSEL_TIMER1 : Timer 1 + - CLKPWR_PCLKSEL_UART0 : UART 0 + - CLKPWR_PCLKSEL_UART1 : UART 1 + - CLKPWR_PCLKSEL_PWM1 : PWM 1 + - CLKPWR_PCLKSEL_I2C0 : I2C 0 + - CLKPWR_PCLKSEL_SPI : SPI + - CLKPWR_PCLKSEL_SSP1 : SSP 1 + - CLKPWR_PCLKSEL_DAC : DAC + - CLKPWR_PCLKSEL_ADC : ADC + - CLKPWR_PCLKSEL_CAN1 : CAN 1 + - CLKPWR_PCLKSEL_CAN2 : CAN 2 + - CLKPWR_PCLKSEL_ACF : ACF + - CLKPWR_PCLKSEL_QEI : QEI + - CLKPWR_PCLKSEL_PCB : PCB + - CLKPWR_PCLKSEL_I2C1 : I2C 1 + - CLKPWR_PCLKSEL_SSP0 : SSP 0 + - CLKPWR_PCLKSEL_TIMER2 : Timer 2 + - CLKPWR_PCLKSEL_TIMER3 : Timer 3 + - CLKPWR_PCLKSEL_UART2 : UART 2 + - CLKPWR_PCLKSEL_UART3 : UART 3 + - CLKPWR_PCLKSEL_I2C2 : I2C 2 + - CLKPWR_PCLKSEL_I2S : I2S + - CLKPWR_PCLKSEL_RIT : RIT + - CLKPWR_PCLKSEL_SYSCON : SYSCON + - CLKPWR_PCLKSEL_MC : MC + + * @param[in] DivVal Value of divider, should be: + * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4 + * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1 + * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2 + * + * @return none + **********************************************************************/ +void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal) +{ + uint32_t bitpos; + + bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32); + + /* PCLKSEL0 selected */ + if (ClkType < 32) + { + /* Clear two bit at bit position */ + LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos))); + + /* Set two selected bit */ + LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); + } + /* PCLKSEL1 selected */ + else + { + /* Clear two bit at bit position */ + LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos)); + + /* Set two selected bit */ + LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); + } +} + + +/*********************************************************************//** + * @brief Get current value of each Peripheral Clock Selection + * @param[in] ClkType Peripheral Clock Selection of each type, + * should be one of the following: + * - CLKPWR_PCLKSEL_WDT : WDT + - CLKPWR_PCLKSEL_TIMER0 : Timer 0 + - CLKPWR_PCLKSEL_TIMER1 : Timer 1 + - CLKPWR_PCLKSEL_UART0 : UART 0 + - CLKPWR_PCLKSEL_UART1 : UART 1 + - CLKPWR_PCLKSEL_PWM1 : PWM 1 + - CLKPWR_PCLKSEL_I2C0 : I2C 0 + - CLKPWR_PCLKSEL_SPI : SPI + - CLKPWR_PCLKSEL_SSP1 : SSP 1 + - CLKPWR_PCLKSEL_DAC : DAC + - CLKPWR_PCLKSEL_ADC : ADC + - CLKPWR_PCLKSEL_CAN1 : CAN 1 + - CLKPWR_PCLKSEL_CAN2 : CAN 2 + - CLKPWR_PCLKSEL_ACF : ACF + - CLKPWR_PCLKSEL_QEI : QEI + - CLKPWR_PCLKSEL_PCB : PCB + - CLKPWR_PCLKSEL_I2C1 : I2C 1 + - CLKPWR_PCLKSEL_SSP0 : SSP 0 + - CLKPWR_PCLKSEL_TIMER2 : Timer 2 + - CLKPWR_PCLKSEL_TIMER3 : Timer 3 + - CLKPWR_PCLKSEL_UART2 : UART 2 + - CLKPWR_PCLKSEL_UART3 : UART 3 + - CLKPWR_PCLKSEL_I2C2 : I2C 2 + - CLKPWR_PCLKSEL_I2S : I2S + - CLKPWR_PCLKSEL_RIT : RIT + - CLKPWR_PCLKSEL_SYSCON : SYSCON + - CLKPWR_PCLKSEL_MC : MC + + * @return Value of Selected Peripheral Clock Selection + **********************************************************************/ +uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType) +{ + uint32_t bitpos, retval; + + if (ClkType < 32) + { + bitpos = ClkType; + retval = LPC_SC->PCLKSEL0; + } + else + { + bitpos = ClkType - 32; + retval = LPC_SC->PCLKSEL1; + } + + retval = CLKPWR_PCLKSEL_GET(bitpos, retval); + return retval; +} + + + +/*********************************************************************//** + * @brief Get current value of each Peripheral Clock + * @param[in] ClkType Peripheral Clock Selection of each type, + * should be one of the following: + * - CLKPWR_PCLKSEL_WDT : WDT + - CLKPWR_PCLKSEL_TIMER0 : Timer 0 + - CLKPWR_PCLKSEL_TIMER1 : Timer 1 + - CLKPWR_PCLKSEL_UART0 : UART 0 + - CLKPWR_PCLKSEL_UART1 : UART 1 + - CLKPWR_PCLKSEL_PWM1 : PWM 1 + - CLKPWR_PCLKSEL_I2C0 : I2C 0 + - CLKPWR_PCLKSEL_SPI : SPI + - CLKPWR_PCLKSEL_SSP1 : SSP 1 + - CLKPWR_PCLKSEL_DAC : DAC + - CLKPWR_PCLKSEL_ADC : ADC + - CLKPWR_PCLKSEL_CAN1 : CAN 1 + - CLKPWR_PCLKSEL_CAN2 : CAN 2 + - CLKPWR_PCLKSEL_ACF : ACF + - CLKPWR_PCLKSEL_QEI : QEI + - CLKPWR_PCLKSEL_PCB : PCB + - CLKPWR_PCLKSEL_I2C1 : I2C 1 + - CLKPWR_PCLKSEL_SSP0 : SSP 0 + - CLKPWR_PCLKSEL_TIMER2 : Timer 2 + - CLKPWR_PCLKSEL_TIMER3 : Timer 3 + - CLKPWR_PCLKSEL_UART2 : UART 2 + - CLKPWR_PCLKSEL_UART3 : UART 3 + - CLKPWR_PCLKSEL_I2C2 : I2C 2 + - CLKPWR_PCLKSEL_I2S : I2S + - CLKPWR_PCLKSEL_RIT : RIT + - CLKPWR_PCLKSEL_SYSCON : SYSCON + - CLKPWR_PCLKSEL_MC : MC + + * @return Value of Selected Peripheral Clock + **********************************************************************/ +uint32_t CLKPWR_GetPCLK (uint32_t ClkType) +{ + uint32_t retval, div; + + retval = SystemCoreClock; + div = CLKPWR_GetPCLKSEL(ClkType); + + switch (div) + { + case 0: + div = 4; + break; + + case 1: + div = 1; + break; + + case 2: + div = 2; + break; + + case 3: + div = 8; + break; + } + retval /= div; + + return retval; +} + + + +/*********************************************************************//** + * @brief Configure power supply for each peripheral according to NewState + * @param[in] PPType Type of peripheral used to enable power, + * should be one of the following: + * - CLKPWR_PCONP_PCTIM0 : Timer 0 + - CLKPWR_PCONP_PCTIM1 : Timer 1 + - CLKPWR_PCONP_PCUART0 : UART 0 + - CLKPWR_PCONP_PCUART1 : UART 1 + - CLKPWR_PCONP_PCPWM1 : PWM 1 + - CLKPWR_PCONP_PCI2C0 : I2C 0 + - CLKPWR_PCONP_PCSPI : SPI + - CLKPWR_PCONP_PCRTC : RTC + - CLKPWR_PCONP_PCSSP1 : SSP 1 + - CLKPWR_PCONP_PCAD : ADC + - CLKPWR_PCONP_PCAN1 : CAN 1 + - CLKPWR_PCONP_PCAN2 : CAN 2 + - CLKPWR_PCONP_PCGPIO : GPIO + - CLKPWR_PCONP_PCRIT : RIT + - CLKPWR_PCONP_PCMC : MC + - CLKPWR_PCONP_PCQEI : QEI + - CLKPWR_PCONP_PCI2C1 : I2C 1 + - CLKPWR_PCONP_PCSSP0 : SSP 0 + - CLKPWR_PCONP_PCTIM2 : Timer 2 + - CLKPWR_PCONP_PCTIM3 : Timer 3 + - CLKPWR_PCONP_PCUART2 : UART 2 + - CLKPWR_PCONP_PCUART3 : UART 3 + - CLKPWR_PCONP_PCI2C2 : I2C 2 + - CLKPWR_PCONP_PCI2S : I2S + - CLKPWR_PCONP_PCGPDMA : GPDMA + - CLKPWR_PCONP_PCENET : Ethernet + - CLKPWR_PCONP_PCUSB : USB + * + * @param[in] NewState New state of Peripheral Power, should be: + * - ENABLE : Enable power for this peripheral + * - DISABLE : Disable power for this peripheral + * + * @return none + **********************************************************************/ +void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK; + } + else if (NewState == DISABLE) + { + LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK; + } +} + + +/*********************************************************************//** + * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None + **********************************************************************/ +void CLKPWR_Sleep(void) +{ + LPC_SC->PCON = 0x00; + /* Sleep Mode*/ + __WFI(); +} + + +/*********************************************************************//** + * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None + **********************************************************************/ +void CLKPWR_DeepSleep(void) +{ + /* Deep-Sleep Mode, set SLEEPDEEP bit */ + SCB->SCR = 0x4; + LPC_SC->PCON = 0x8; + /* Deep Sleep Mode*/ + __WFI(); +} + + +/*********************************************************************//** + * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None + **********************************************************************/ +void CLKPWR_PowerDown(void) +{ + /* Deep-Sleep Mode, set SLEEPDEEP bit */ + SCB->SCR = 0x4; + LPC_SC->PCON = 0x09; + /* Power Down Mode*/ + __WFI(); +} + + +/*********************************************************************//** + * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None + **********************************************************************/ +void CLKPWR_DeepPowerDown(void) +{ + /* Deep-Sleep Mode, set SLEEPDEEP bit */ + SCB->SCR = 0x4; + LPC_SC->PCON = 0x03; + /* Deep Power Down Mode*/ + __WFI(); +} + +/** + * @} + */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_clkpwr.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,394 @@ +/***********************************************************************//** + * @file lpc17xx_clkpwr.h + * @brief Contains all macro definitions and function prototypes + * support for Clock and Power Control firmware library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup CLKPWR CLKPWR + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_CLKPWR_H_ +#define LPC17XX_CLKPWR_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros + * @{ + */ + +/********************************************************************** + * Peripheral Clock Selection Definitions + **********************************************************************/ +/** Peripheral clock divider bit position for WDT */ +#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) +/** Peripheral clock divider bit position for TIMER0 */ +#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) +/** Peripheral clock divider bit position for TIMER1 */ +#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) +/** Peripheral clock divider bit position for UART0 */ +#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) +/** Peripheral clock divider bit position for UART1 */ +#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) +/** Peripheral clock divider bit position for PWM1 */ +#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) +/** Peripheral clock divider bit position for I2C0 */ +#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) +/** Peripheral clock divider bit position for SPI */ +#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) +/** Peripheral clock divider bit position for SSP1 */ +#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) +/** Peripheral clock divider bit position for DAC */ +#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) +/** Peripheral clock divider bit position for ADC */ +#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) +/** Peripheral clock divider bit position for CAN1 */ +#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) +/** Peripheral clock divider bit position for CAN2 */ +#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) +/** Peripheral clock divider bit position for ACF */ +#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) +/** Peripheral clock divider bit position for QEI */ +#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) +/** Peripheral clock divider bit position for PCB */ +#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) +/** Peripheral clock divider bit position for I2C1 */ +#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) +/** Peripheral clock divider bit position for SSP0 */ +#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) +/** Peripheral clock divider bit position for TIMER2 */ +#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) +/** Peripheral clock divider bit position for TIMER3 */ +#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) +/** Peripheral clock divider bit position for UART2 */ +#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) +/** Peripheral clock divider bit position for UART3 */ +#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) +/** Peripheral clock divider bit position for I2C2 */ +#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) +/** Peripheral clock divider bit position for I2S */ +#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) +/** Peripheral clock divider bit position for RIT */ +#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) +/** Peripheral clock divider bit position for SYSCON */ +#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) +/** Peripheral clock divider bit position for MC */ +#define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) + +/** Macro for Peripheral Clock Selection register bit values + * Note: When CCLK_DIV_8, Peripheral�s clock is selected to + * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering + * when �11�selects PCLK_xyz = CCLK/6 */ +/* Peripheral clock divider is set to 4 from CCLK */ +#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) +/** Peripheral clock divider is the same with CCLK */ +#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) +/** Peripheral clock divider is set to 2 from CCLK */ +#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) + + +/******************************************************************** +* Power Control for Peripherals Definitions +**********************************************************************/ +/** Timer/Counter 0 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) +/* Timer/Counter 1 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) +/** UART0 power/clock control bit */ +#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) +/** UART1 power/clock control bit */ +#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) +/** PWM1 power/clock control bit */ +#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) +/** The I2C0 interface power/clock control bit */ +#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) +/** The SPI interface power/clock control bit */ +#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) +/** The RTC power/clock control bit */ +#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) +/** The SSP1 interface power/clock control bit */ +#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) +/** A/D converter 0 (ADC0) power/clock control bit */ +#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) +/** CAN Controller 1 power/clock control bit */ +#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) +/** CAN Controller 2 power/clock control bit */ +#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) +/** GPIO power/clock control bit */ +#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) +/** Repetitive Interrupt Timer power/clock control bit */ +#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) +/** Motor Control PWM */ +#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) +/** Quadrature Encoder Interface power/clock control bit */ +#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) +/** The I2C1 interface power/clock control bit */ +#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) +/** The SSP0 interface power/clock control bit */ +#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) +/** Timer 2 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) +/** Timer 3 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) +/** UART 2 power/clock control bit */ +#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) +/** UART 3 power/clock control bit */ +#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) +/** I2C interface 2 power/clock control bit */ +#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) +/** I2S interface power/clock control bit*/ +#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) +/** GP DMA function power/clock control bit*/ +#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) +/** Ethernet block power/clock control bit*/ +#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) +/** USB interface power/clock control bit*/ +#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) + + +/** + * @} + */ +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros + * @{ + */ + +/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/*********************************************************************//** + * Macro defines for Clock Source Select Register + **********************************************************************/ +/** Internal RC oscillator */ +#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) +/** Main oscillator */ +#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) +/** RTC oscillator */ +#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) +/** Clock source selection bit mask */ +#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) + +/*********************************************************************//** + * Macro defines for Clock Output Configuration Register + **********************************************************************/ +/* Clock Output Configuration register definition */ +/** Selects the CPU clock as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) +/** Selects the main oscillator as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) +/** Selects the Internal RC oscillator as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) +/** Selects the USB clock as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) +/** Selects the RTC oscillator as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) +/** Integer value to divide the output clock by, minus one */ +#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) +/** CLKOUT enable control */ +#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) +/** CLKOUT activity indication */ +#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) +/** Clock source selection bit mask */ +#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) + +/*********************************************************************//** + * Macro defines for PPL0 Control Register + **********************************************************************/ +/** PLL 0 control enable */ +#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) +/** PLL 0 control connect */ +#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) +/** PLL 0 control bit mask */ +#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) + +/*********************************************************************//** + * Macro defines for PPL0 Configuration Register + **********************************************************************/ +/** PLL 0 Configuration MSEL field */ +#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) +/** PLL 0 Configuration NSEL field */ +#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) +/** PLL 0 Configuration bit mask */ +#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) + + +/*********************************************************************//** + * Macro defines for PPL0 Status Register + **********************************************************************/ +/** PLL 0 MSEL value */ +#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) +/** PLL NSEL get value */ +#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) +/** PLL status enable bit */ +#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) +/** PLL status Connect bit */ +#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) +/** PLL status lock */ +#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) + +/*********************************************************************//** + * Macro defines for PPL0 Feed Register + **********************************************************************/ +/** PLL0 Feed bit mask */ +#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) + +/*********************************************************************//** + * Macro defines for PLL1 Control Register + **********************************************************************/ +/** USB PLL control enable */ +#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) +/** USB PLL control connect */ +#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) +/** USB PLL control bit mask */ +#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) + +/*********************************************************************//** + * Macro defines for PLL1 Configuration Register + **********************************************************************/ +/** USB PLL MSEL set value */ +#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) +/** USB PLL PSEL set value */ +#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) +/** USB PLL configuration bit mask */ +#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) + +/*********************************************************************//** + * Macro defines for PLL1 Status Register + **********************************************************************/ +/** USB PLL MSEL get value */ +#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) +/** USB PLL PSEL get value */ +#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) +/** USB PLL status enable bit */ +#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) +/** USB PLL status Connect bit */ +#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) +/** USB PLL status lock */ +#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) + +/*********************************************************************//** + * Macro defines for PLL1 Feed Register + **********************************************************************/ +/** PLL1 Feed bit mask */ +#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) + +/*********************************************************************//** + * Macro defines for CPU Clock Configuration Register + **********************************************************************/ +/** CPU Clock configuration bit mask */ +#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) + +/*********************************************************************//** + * Macro defines for USB Clock Configuration Register + **********************************************************************/ +/** USB Clock Configuration bit mask */ +#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) + +/*********************************************************************//** + * Macro defines for IRC Trim Register + **********************************************************************/ +/** IRC Trim bit mask */ +#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) + +/*********************************************************************//** + * Macro defines for Peripheral Clock Selection Register 0 and 1 + **********************************************************************/ +/** Peripheral Clock Selection 0 mask bit */ +#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) +/** Peripheral Clock Selection 1 mask bit */ +#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) +/** Macro to set peripheral clock of each type + * p: position of two bits that hold divider of peripheral clock + * n: value of divider of peripheral clock to be set */ +#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) +/** Macro to mask peripheral clock of each type */ +#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) +/** Macro to get peripheral clock of each type */ +#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) + +/*********************************************************************//** + * Macro defines for Power Mode Control Register + **********************************************************************/ +/** Power mode control bit 0 */ +#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) +/** Power mode control bit 1 */ +#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) +/** Brown-Out Reduced Power Mode */ +#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) +/** Brown-Out Global Disable */ +#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) +/** Brown Out Reset Disable */ +#define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) +/** Sleep Mode entry flag */ +#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) +/** Deep Sleep entry flag */ +#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) +/** Power-down entry flag */ +#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) +/** Deep Power-down entry flag */ +#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) + +/*********************************************************************//** + * Macro defines for Power Control for Peripheral Register + **********************************************************************/ +/** Power Control for Peripherals bit mask */ +#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions + * @{ + */ + +void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); +uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); +uint32_t CLKPWR_GetPCLK (uint32_t ClkType); +void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); +void CLKPWR_Sleep(void); +void CLKPWR_DeepSleep(void); +void CLKPWR_PowerDown(void); +void CLKPWR_DeepPowerDown(void); + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LPC17XX_CLKPWR_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_gpdma.c Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,450 @@ +/***********************************************************************//** + * @file lpc17xx_gpdma.c + * @brief Contains all functions support for GPDMA firmware library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @addtogroup GPDMA + * @{ + */ + +/* Includes ------------------------------------------------------------------- */ +#include "lpc17xx_gpdma.h" +#include "lpc17xx_clkpwr.h" + +/* If this source file built with example, the LPC17xx FW library configuration + * file in each example directory ("lpc17xx_libcfg.h") must be included, + * otherwise the default FW library configuration file must be included instead + */ +#ifdef __BUILD_WITH_EXAMPLE__ +#include "lpc17xx_libcfg.h" +#else +#include "lpc17xx_libcfg_default.h" +#endif /* __BUILD_WITH_EXAMPLE__ */ + +#ifdef _GPDMA + + +/* Private Variables ---------------------------------------------------------- */ +/** @defgroup GPDMA_Private_Variables GPDMA Private Variables + * @{ + */ + +/** + * @brief Lookup Table of Connection Type matched with + * Peripheral Data (FIFO) register base address + */ +#ifdef __IAR_SYSTEMS_ICC__ +volatile const void *GPDMA_LUTPerAddr[] = { + (&LPC_SSP0->DR), // SSP0 Tx + (&LPC_SSP0->DR), // SSP0 Rx + (&LPC_SSP1->DR), // SSP1 Tx + (&LPC_SSP1->DR), // SSP1 Rx + (&LPC_ADC->ADGDR), // ADC + (&LPC_I2S->I2STXFIFO), // I2S Tx + (&LPC_I2S->I2SRXFIFO), // I2S Rx + (&LPC_DAC->DACR), // DAC + (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx + (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx + (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx + (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx + (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx + (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx + (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx + (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx + (&LPC_TIM0->MR0), // MAT0.0 + (&LPC_TIM0->MR1), // MAT0.1 + (&LPC_TIM1->MR0), // MAT1.0 + (&LPC_TIM1->MR1), // MAT1.1 + (&LPC_TIM2->MR0), // MAT2.0 + (&LPC_TIM2->MR1), // MAT2.1 + (&LPC_TIM3->MR0), // MAT3.0 + (&LPC_TIM3->MR1), // MAT3.1 +}; +#else +const uint32_t GPDMA_LUTPerAddr[] = { + ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx + ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx + ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx + ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx + ((uint32_t)&LPC_ADC->ADGDR), // ADC + ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx + ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx + ((uint32_t)&LPC_DAC->DACR), // DAC + ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx + ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx + ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx + ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx + ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx + ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx + ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx + ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx + ((uint32_t)&LPC_TIM0->MR0), // MAT0.0 + ((uint32_t)&LPC_TIM0->MR1), // MAT0.1 + ((uint32_t)&LPC_TIM1->MR0), // MAT1.0 + ((uint32_t)&LPC_TIM1->MR1), // MAT1.1 + ((uint32_t)&LPC_TIM2->MR0), // MAT2.0 + ((uint32_t)&LPC_TIM2->MR1), // MAT2.1 + ((uint32_t)&LPC_TIM3->MR0), // MAT3.0 + ((uint32_t)&LPC_TIM3->MR1), // MAT3.1 +}; +#endif +/** + * @brief Lookup Table of GPDMA Channel Number matched with + * GPDMA channel pointer + */ +const LPC_GPDMACH_TypeDef *pGPDMACh[8] = { + LPC_GPDMACH0, // GPDMA Channel 0 + LPC_GPDMACH1, // GPDMA Channel 1 + LPC_GPDMACH2, // GPDMA Channel 2 + LPC_GPDMACH3, // GPDMA Channel 3 + LPC_GPDMACH4, // GPDMA Channel 4 + LPC_GPDMACH5, // GPDMA Channel 5 + LPC_GPDMACH6, // GPDMA Channel 6 + LPC_GPDMACH7, // GPDMA Channel 7 +}; +/** + * @brief Optimized Peripheral Source and Destination burst size + */ +const uint8_t GPDMA_LUTPerBurst[] = { + GPDMA_BSIZE_4, // SSP0 Tx + GPDMA_BSIZE_4, // SSP0 Rx + GPDMA_BSIZE_4, // SSP1 Tx + GPDMA_BSIZE_4, // SSP1 Rx + GPDMA_BSIZE_4, // ADC + GPDMA_BSIZE_32, // I2S channel 0 + GPDMA_BSIZE_32, // I2S channel 1 + GPDMA_BSIZE_1, // DAC + GPDMA_BSIZE_1, // UART0 Tx + GPDMA_BSIZE_1, // UART0 Rx + GPDMA_BSIZE_1, // UART1 Tx + GPDMA_BSIZE_1, // UART1 Rx + GPDMA_BSIZE_1, // UART2 Tx + GPDMA_BSIZE_1, // UART2 Rx + GPDMA_BSIZE_1, // UART3 Tx + GPDMA_BSIZE_1, // UART3 Rx + GPDMA_BSIZE_1, // MAT0.0 + GPDMA_BSIZE_1, // MAT0.1 + GPDMA_BSIZE_1, // MAT1.0 + GPDMA_BSIZE_1, // MAT1.1 + GPDMA_BSIZE_1, // MAT2.0 + GPDMA_BSIZE_1, // MAT2.1 + GPDMA_BSIZE_1, // MAT3.0 + GPDMA_BSIZE_1, // MAT3.1 +}; +/** + * @brief Optimized Peripheral Source and Destination transfer width + */ +const uint8_t GPDMA_LUTPerWid[] = { + GPDMA_WIDTH_BYTE, // SSP0 Tx + GPDMA_WIDTH_BYTE, // SSP0 Rx + GPDMA_WIDTH_BYTE, // SSP1 Tx + GPDMA_WIDTH_BYTE, // SSP1 Rx + GPDMA_WIDTH_WORD, // ADC + GPDMA_WIDTH_WORD, // I2S channel 0 + GPDMA_WIDTH_WORD, // I2S channel 1 + GPDMA_WIDTH_BYTE, // DAC + GPDMA_WIDTH_BYTE, // UART0 Tx + GPDMA_WIDTH_BYTE, // UART0 Rx + GPDMA_WIDTH_BYTE, // UART1 Tx + GPDMA_WIDTH_BYTE, // UART1 Rx + GPDMA_WIDTH_BYTE, // UART2 Tx + GPDMA_WIDTH_BYTE, // UART2 Rx + GPDMA_WIDTH_BYTE, // UART3 Tx + GPDMA_WIDTH_BYTE, // UART3 Rx + GPDMA_WIDTH_WORD, // MAT0.0 + GPDMA_WIDTH_WORD, // MAT0.1 + GPDMA_WIDTH_WORD, // MAT1.0 + GPDMA_WIDTH_WORD, // MAT1.1 + GPDMA_WIDTH_WORD, // MAT2.0 + GPDMA_WIDTH_WORD, // MAT2.1 + GPDMA_WIDTH_WORD, // MAT3.0 + GPDMA_WIDTH_WORD, // MAT3.1 +}; + +/** + * @} + */ + +/* Public Functions ----------------------------------------------------------- */ +/** @addtogroup GPDMA_Public_Functions + * @{ + */ + +/********************************************************************//** + * @brief Initialize GPDMA controller + * @param None + * @return None + *********************************************************************/ +void GPDMA_Init(void) +{ + /* Enable GPDMA clock */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE); + + // Reset all channel configuration register + LPC_GPDMACH0->DMACCConfig = 0; + LPC_GPDMACH1->DMACCConfig = 0; + LPC_GPDMACH2->DMACCConfig = 0; + LPC_GPDMACH3->DMACCConfig = 0; + LPC_GPDMACH4->DMACCConfig = 0; + LPC_GPDMACH5->DMACCConfig = 0; + LPC_GPDMACH6->DMACCConfig = 0; + LPC_GPDMACH7->DMACCConfig = 0; + + /* Clear all DMA interrupt and error flag */ + LPC_GPDMA->DMACIntTCClear = 0xFF; + LPC_GPDMA->DMACIntErrClr = 0xFF; +} + +/********************************************************************//** + * @brief Setup GPDMA channel peripheral according to the specified + * parameters in the GPDMAChannelConfig. + * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type + * structure that contains the configuration + * information for the specified GPDMA channel peripheral. + * @return ERROR if selected channel is enabled before + * or SUCCESS if channel is configured successfully + *********************************************************************/ +Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig) +{ + LPC_GPDMACH_TypeDef *pDMAch; + uint32_t tmp1, tmp2; + + if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) { + // This channel is enabled, return ERROR, need to release this channel first + return ERROR; + } + + // Get Channel pointer + pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum]; + + // Reset the Interrupt status + LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum); + LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum); + + // Clear DMA configure + pDMAch->DMACCControl = 0x00; + pDMAch->DMACCConfig = 0x00; + + /* Assign Linker List Item value */ + pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI; + + /* Set value to Channel Control Registers */ + switch (GPDMAChannelConfig->TransferType) + { + // Memory to memory + case GPDMA_TRANSFERTYPE_M2M: + // Assign physical source and destination address + pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; + pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; + pDMAch->DMACCControl + = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \ + | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \ + | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \ + | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \ + | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \ + | GPDMA_DMACCxControl_SI \ + | GPDMA_DMACCxControl_DI \ + | GPDMA_DMACCxControl_I; + break; + // Memory to peripheral + case GPDMA_TRANSFERTYPE_M2P: + // Assign physical source + pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; + // Assign peripheral destination address + pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; + pDMAch->DMACCControl + = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ + | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ + | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ + | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ + | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ + | GPDMA_DMACCxControl_SI \ + | GPDMA_DMACCxControl_I; + break; + // Peripheral to memory + case GPDMA_TRANSFERTYPE_P2M: + // Assign peripheral source address + pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; + // Assign memory destination address + pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; + pDMAch->DMACCControl + = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ + | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ + | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ + | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ + | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ + | GPDMA_DMACCxControl_DI \ + | GPDMA_DMACCxControl_I; + break; + // Peripheral to peripheral + case GPDMA_TRANSFERTYPE_P2P: + // Assign peripheral source address + pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; + // Assign peripheral destination address + pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; + pDMAch->DMACCControl + = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ + | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ + | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ + | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ + | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ + | GPDMA_DMACCxControl_I; + break; + // Do not support any more transfer type, return ERROR + default: + return ERROR; + } + + /* Re-Configure DMA Request Select for source peripheral */ + if (GPDMAChannelConfig->SrcConn > 15) + { + LPC_SC->RESERVED9 |= (1<<(GPDMAChannelConfig->SrcConn - 16)); + } else { + LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->SrcConn - 8)); + } + + /* Re-Configure DMA Request Select for Destination peripheral */ + if (GPDMAChannelConfig->DstConn > 15) + { + LPC_SC->RESERVED9 |= (1<<(GPDMAChannelConfig->DstConn - 16)); + } else { + LPC_SC->RESERVED9 &= ~(1<<(GPDMAChannelConfig->DstConn - 8)); + } + + /* Enable DMA channels, little endian */ + LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E; + while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E)); + + // Calculate absolute value for Connection number + tmp1 = GPDMAChannelConfig->SrcConn; + tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1); + tmp2 = GPDMAChannelConfig->DstConn; + tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2); + + // Configure DMA Channel, enable Error Counter and Terminate counter + pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \ + | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \ + | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \ + | GPDMA_DMACCxConfig_DestPeripheral(tmp2); + + return SUCCESS; +} + + +/*********************************************************************//** + * @brief Enable/Disable DMA channel + * @param[in] channelNum GPDMA channel, should be in range from 0 to 7 + * @param[in] NewState New State of this command, should be: + * - ENABLE. + * - DISABLE. + * @return None + **********************************************************************/ +void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState) +{ + LPC_GPDMACH_TypeDef *pDMAch; + + // Get Channel pointer + pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum]; + + if (NewState == ENABLE) { + pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E; + } else { + pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E; + } +} +/*********************************************************************//** + * @brief Check if corresponding channel does have an active interrupt + * request or not + * @param[in] type type of status, should be: + * - GPDMA_STAT_INT: GPDMA Interrupt Status + * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status + * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status + * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status + * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status + * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status + * @param[in] channel GPDMA channel, should be in range from 0 to 7 + * @return IntStatus status of DMA channel interrupt after masking + * Should be: + * - SET: the corresponding channel has no active interrupt request + * - RESET: the corresponding channel does have an active interrupt request + **********************************************************************/ +IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel) +{ + CHECK_PARAM(PARAM_GPDMA_STAT(type)); + CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); + + switch (type) + { + case GPDMA_STAT_INT: //check status of DMA channel interrupts + if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel))) + return SET; + return RESET; + case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA + if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel)) + return SET; + return RESET; + case GPDMA_STAT_INTERR: //check interrupt status for DMA channels + if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel)) + return SET; + return RESET; + case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels + if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel)) + return SET; + return RESET; + case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels + if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel)) + return SET; + return RESET; + default: //check enable status for DMA channels + if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel)) + return SET; + return RESET; + } +} + +/*********************************************************************//** + * @brief Clear one or more interrupt requests on DMA channels + * @param[in] type type of interrupt request, should be: + * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear + * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear + * @param[in] channel GPDMA channel, should be in range from 0 to 7 + * @return None + **********************************************************************/ +void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel) +{ + CHECK_PARAM(PARAM_GPDMA_STATCLR(type)); + CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); + + if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel + LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel); + else // clear the error interrupt request + LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel); +} + +/** + * @} + */ + +#endif /* _GPDMA */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_gpdma.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,417 @@ +/***********************************************************************//** + * @file lpc17xx_gpdma.h + * @brief Contains all macro definitions and function prototypes + * support for GPDMA firmware library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup GPDMA GPDMA + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_GPDMA_H_ +#define LPC17XX_GPDMA_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup GPDMA_Public_Macros GPDMA Public Macros + * @{ + */ + +/** DMA Connection number definitions */ +#define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */ +#define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */ +#define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */ +#define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */ +#define GPDMA_CONN_ADC ((4UL)) /**< ADC */ +#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */ +#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */ +#define GPDMA_CONN_DAC ((7UL)) /**< DAC */ +#define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */ +#define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */ +#define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */ +#define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */ +#define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */ +#define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */ +#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */ +#define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */ +#define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */ +#define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */ +#define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */ +#define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */ +#define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */ +#define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */ +#define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */ +#define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */ + +/** GPDMA Transfer type definitions */ +#define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */ +#define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */ +#define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */ +#define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */ + +/** Burst size in Source and Destination definitions */ +#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */ +#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */ +#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */ +#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */ +#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */ +#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */ +#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */ +#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */ + +/** Width in Source transfer width and Destination transfer width definitions */ +#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */ +#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */ +#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */ + +/** DMA Request Select Mode definitions */ +#define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */ +#define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */ + +/** + * @} + */ + + +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup GPDMA_Private_Macros GPDMA Private Macros + * @{ + */ + +/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/*********************************************************************//** + * Macro defines for DMA Interrupt Status register + **********************************************************************/ +#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACIntStat_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Interrupt Terminal Count Request Status register + **********************************************************************/ +#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACIntTCStat_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Interrupt Terminal Count Request Clear register + **********************************************************************/ +#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACIntTCClear_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Interrupt Error Status register + **********************************************************************/ +#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACIntErrStat_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Interrupt Error Clear register + **********************************************************************/ +#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACIntErrClr_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Raw Interrupt Terminal Count Status register + **********************************************************************/ +#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Raw Error Interrupt Status register + **********************************************************************/ +#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Enabled Channel register + **********************************************************************/ +#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF)) +#define GPDMA_DMACEnbldChns_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Software Burst Request register + **********************************************************************/ +#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF)) +#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF)) + +/*********************************************************************//** + * Macro defines for DMA Software Single Request register + **********************************************************************/ +#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF)) +#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF)) + +/*********************************************************************//** + * Macro defines for DMA Software Last Burst Request register + **********************************************************************/ +#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF)) +#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF)) + +/*********************************************************************//** + * Macro defines for DMA Software Last Single Request register + **********************************************************************/ +#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF)) +#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF)) + +/*********************************************************************//** + * Macro defines for DMA Configuration register + **********************************************************************/ +#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/ +#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/ +#define GPDMA_DMACConfig_BITMASK ((0x03)) + +/*********************************************************************//** + * Macro defines for DMA Synchronization register + **********************************************************************/ +#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF)) +#define GPDMA_DMACSync_BITMASK ((0xFFFF)) + +/*********************************************************************//** + * Macro defines for DMA Request Select register + **********************************************************************/ +#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF)) +#define GPDMA_DMAReqSel_BITMASK ((0xFF)) + +/*********************************************************************//** + * Macro defines for DMA Channel Linked List Item registers + **********************************************************************/ +/** DMA Channel Linked List Item registers bit mask*/ +#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC)) + +/*********************************************************************//** + * Macro defines for DMA channel control registers + **********************************************************************/ +#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/ +#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/ +#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/ +#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/ +#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/ +#define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/ +#define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/ +#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/ +#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/ +#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/ +#define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */ +/** DMA channel control registers bit mask */ +#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF)) + +/*********************************************************************//** + * Macro defines for DMA Channel Configuration registers + **********************************************************************/ +#define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/ +#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/ +#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/ +#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/ +#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/ +#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/ +#define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/ +#define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/ +#define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/ +/** DMA Channel Configuration registers bit mask */ +#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF)) + +/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ +/* Macros check GPDMA channel */ +#define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7)) + +/* Macros check GPDMA connection type */ +#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \ +|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \ +|| (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \ +|| (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \ +|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \ +|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \ +|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \ +|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \ +|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \ +|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \ +|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \ +|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1)) + +/* Macros check GPDMA burst size type */ +#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \ +|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \ +|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \ +|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256)) + +/* Macros check GPDMA width type */ +#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \ +|| (n==GPDMA_WIDTH_WORD)) + +/* Macros check GPDMA status type */ +#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \ +|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \ +|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH)) + +/* Macros check GPDMA transfer type */ +#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \ +||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P)) + +/* Macros check GPDMA state clear type */ +#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR)) + +/* Macros check GPDMA request select type */ +#define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER)) +/** + * @} + */ + + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup GPDMA_Public_Types GPDMA Public Types + * @{ + */ + +/** + * @brief GPDMA Status enumeration + */ +typedef enum { + GPDMA_STAT_INT, /**< GPDMA Interrupt Status */ + GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */ + GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */ + GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */ + GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */ + GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */ +} GPDMA_Status_Type; + +/** + * @brief GPDMA Interrupt clear status enumeration + */ +typedef enum{ + GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */ + GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */ +}GPDMA_StateClear_Type; + +/** + * @brief GPDMA Channel configuration structure type definition + */ +typedef struct { + uint32_t ChannelNum; /**< DMA channel number, should be in + range from 0 to 7. + Note: DMA channel 0 has the highest priority + and DMA channel 7 the lowest priority. + */ + uint32_t TransferSize; /**< Length/Size of transfer */ + uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */ + uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as + GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */ + uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as + GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */ + uint32_t TransferType; /**< Transfer Type, should be one of the following: + - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control + - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control + - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control + - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control + */ + uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as + GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of + following: + - GPDMA_CONN_SSP0_Tx: SSP0, Tx + - GPDMA_CONN_SSP0_Rx: SSP0, Rx + - GPDMA_CONN_SSP1_Tx: SSP1, Tx + - GPDMA_CONN_SSP1_Rx: SSP1, Rx + - GPDMA_CONN_ADC: ADC + - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 + - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 + - GPDMA_CONN_DAC: DAC + - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 + - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 + - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 + - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 + - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 + - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 + - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 + - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 + */ + uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as + GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of + following: + - GPDMA_CONN_SSP0_Tx: SSP0, Tx + - GPDMA_CONN_SSP0_Rx: SSP0, Rx + - GPDMA_CONN_SSP1_Tx: SSP1, Tx + - GPDMA_CONN_SSP1_Rx: SSP1, Rx + - GPDMA_CONN_ADC: ADC + - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 + - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 + - GPDMA_CONN_DAC: DAC + - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 + - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 + - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 + - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 + - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 + - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 + - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 + - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 + */ + uint32_t DMALLI; /**< Linker List Item structure data address + if there's no Linker List, set as '0' + */ +} GPDMA_Channel_CFG_Type; + +/** + * @brief GPDMA Linker List Item structure type definition + */ +typedef struct { + uint32_t SrcAddr; /**< Source Address */ + uint32_t DstAddr; /**< Destination address */ + uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */ + uint32_t Control; /**< GPDMA Control of this LLI */ +} GPDMA_LLI_Type; + + +/** + * @} + */ + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup GPDMA_Public_Functions GPDMA Public Functions + * @{ + */ + +void GPDMA_Init(void); +//Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs); +Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig); +IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel); +void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel); +void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState); +//void GPDMA_IntHandler(void); + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LPC17XX_GPDMA_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_libcfg.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,148 @@ +/***********************************************************************//** + * @file lpc17xx_libcfg.h + * @purpose Library configuration file + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +#ifndef LPC17XX_LIBCFG_H_ +#define LPC17XX_LIBCFG_H_ + +#include "lpc_types.h" + + +/************************** DEBUG MODE DEFINITIONS *********************************/ +/* Un-comment the line below to compile the library in DEBUG mode, this will expanse + the "CHECK_PARAM" macro in the FW library code */ + +#define DEBUG + + +/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/ + +/* Comment the line below to disable the specific peripheral inclusion */ + +/* DEBUG_FRAMWORK ------------------------------ */ +#define _DBGFWK + +/* GPIO ------------------------------- */ +//#define _GPIO + +/* EXTI ------------------------------- */ +//#define _EXTI + +/* UART ------------------------------- */ +#define _UART +#define _UART0 +//#define _UART1 +//#define _UART2 +//#define _UART3 + +/* SPI ------------------------------- */ +//#define _SPI + +/* SSP ------------------------------- */ +//#define _SSP +//#define _SSP0 +//#define _SSP1 + +/* SYSTICK --------------------------- */ +//#define _SYSTICK + +/* I2C ------------------------------- */ +//#define _I2C +//#define _I2C0 +//#define _I2C1 +//#define _I2C2 + +/* TIMER ------------------------------- */ +//#define _TIM + +/* WDT ------------------------------- */ +//#define _WDT + + +/* GPDMA ------------------------------- */ +//#define _GPDMA + + +/* DAC ------------------------------- */ +//#define _DAC + +/* DAC ------------------------------- */ +//#define _ADC + + +/* PWM ------------------------------- */ +//#define _PWM +//#define _PWM1 + +/* RTC ------------------------------- */ +//#define _RTC + +/* I2S ------------------------------- */ +//#define _I2S + +/* USB device ------------------------------- */ +//#define _USBDEV +//#define _USB_DMA + +/* QEI ------------------------------- */ +//#define _QEI + +/* MCPWM ------------------------------- */ +//#define _MCPWM + +/* CAN--------------------------------*/ +//#define _CAN + +/* RIT ------------------------------- */ +//#define _RIT + +/* EMAC ------------------------------ */ +//#define _EMAC + + +/* GPDMA ------------------------------- */ +#define _GPDMA + + +/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/ + +#ifdef DEBUG +/******************************************************************************* +* @brief The CHECK_PARAM macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* @param[in] expr - If expr is false, it calls check_failed() function +* which reports the name of the source file and the source +* line number of the call that failed. +* - If expr is true, it returns no value. +* @return None +*******************************************************************************/ +#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define CHECK_PARAM(expr) +#endif /* DEBUG */ + + + +/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/ + +#ifdef DEBUG +void check_failed(uint8_t *file, uint32_t line); +#endif + + +#endif /* LPC17XX_LIBCFG_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_libcfg_default.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,170 @@ +/***********************************************************************//** + * @file lpc17xx_libcfg_default.h + * @brief Default Library configuration header file + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Library Configuration group ----------------------------------------------------------- */ +/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_LIBCFG_DEFAULT_H_ +#define LPC17XX_LIBCFG_DEFAULT_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "lpc_types.h" + + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros + * @{ + */ + +/************************** DEBUG MODE DEFINITIONS *********************************/ +/* Un-comment the line below to compile the library in DEBUG mode, this will expanse + the "CHECK_PARAM" macro in the FW library code */ + +#define DEBUG + + +/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/ +/* Comment the line below to disable the specific peripheral inclusion */ + +/* DEBUG_FRAMWORK ------------------------------ */ +#define _DBGFWK + +/* GPIO ------------------------------- */ +#define _GPIO + +/* EXTI ------------------------------- */ +#define _EXTI + +/* UART ------------------------------- */ +#define _UART +#define _UART0 +#define _UART1 +#define _UART2 +#define _UART3 + +/* SPI ------------------------------- */ +#define _SPI + +/* SYSTICK --------------------------- */ +#define _SYSTICK + +/* SSP ------------------------------- */ +#define _SSP +#define _SSP0 +#define _SSP1 + + +/* I2C ------------------------------- */ +#define _I2C +#define _I2C0 +#define _I2C1 +#define _I2C2 + +/* TIMER ------------------------------- */ +#define _TIM + +/* WDT ------------------------------- */ +#define _WDT + + +/* GPDMA ------------------------------- */ +#define _GPDMA + + +/* DAC ------------------------------- */ +#define _DAC + +/* DAC ------------------------------- */ +#define _ADC + + +/* PWM ------------------------------- */ +#define _PWM +#define _PWM1 + +/* RTC ------------------------------- */ +#define _RTC + +/* I2S ------------------------------- */ +#define _I2S + +/* USB device ------------------------------- */ +#define _USBDEV +#define _USB_DMA + +/* QEI ------------------------------- */ +#define _QEI + +/* MCPWM ------------------------------- */ +#define _MCPWM + +/* CAN--------------------------------*/ +#define _CAN + +/* RIT ------------------------------- */ +#define _RIT + +/* EMAC ------------------------------ */ +#define _EMAC + +/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/ + +#ifdef DEBUG +/******************************************************************************* +* @brief The CHECK_PARAM macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* @param[in] expr - If expr is false, it calls check_failed() function +* which reports the name of the source file and the source +* line number of the call that failed. +* - If expr is true, it returns no value. +* @return None +*******************************************************************************/ +#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define CHECK_PARAM(expr) +#endif /* DEBUG */ + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions + * @{ + */ + +#ifdef DEBUG +void check_failed(uint8_t *file, uint32_t line); +#endif + +/** + * @} + */ + +#endif /* LPC17XX_LIBCFG_DEFAULT_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_pinsel.c Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,306 @@ +/***********************************************************************//** + * @file lpc17xx_pinsel.c + * @brief Contains all functions support for Pin connect block firmware + * library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @addtogroup PINSEL + * @{ + */ + +/* Includes ------------------------------------------------------------------- */ +#include "lpc17xx_pinsel.h" + +/* Public Functions ----------------------------------------------------------- */ + +static void set_PinFunc ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum); +static void set_ResistorMode ( uint8_t portnum, uint8_t pinnum, uint8_t modenum); +static void set_OpenDrainMode( uint8_t portnum, uint8_t pinnum, uint8_t modenum); + +/*********************************************************************//** + * @brief Setup the pin selection function + * @param[in] portnum PORT number, + * should be one of the following: + * - PINSEL_PORT_0 : Port 0 + * - PINSEL_PORT_1 : Port 1 + * - PINSEL_PORT_2 : Port 2 + * - PINSEL_PORT_3 : Port 3 + * + * @param[in] pinnum Pin number, + * should be one of the following: + - PINSEL_PIN_0 : Pin 0 + - PINSEL_PIN_1 : Pin 1 + - PINSEL_PIN_2 : Pin 2 + - PINSEL_PIN_3 : Pin 3 + - PINSEL_PIN_4 : Pin 4 + - PINSEL_PIN_5 : Pin 5 + - PINSEL_PIN_6 : Pin 6 + - PINSEL_PIN_7 : Pin 7 + - PINSEL_PIN_8 : Pin 8 + - PINSEL_PIN_9 : Pin 9 + - PINSEL_PIN_10 : Pin 10 + - PINSEL_PIN_11 : Pin 11 + - PINSEL_PIN_12 : Pin 12 + - PINSEL_PIN_13 : Pin 13 + - PINSEL_PIN_14 : Pin 14 + - PINSEL_PIN_15 : Pin 15 + - PINSEL_PIN_16 : Pin 16 + - PINSEL_PIN_17 : Pin 17 + - PINSEL_PIN_18 : Pin 18 + - PINSEL_PIN_19 : Pin 19 + - PINSEL_PIN_20 : Pin 20 + - PINSEL_PIN_21 : Pin 21 + - PINSEL_PIN_22 : Pin 22 + - PINSEL_PIN_23 : Pin 23 + - PINSEL_PIN_24 : Pin 24 + - PINSEL_PIN_25 : Pin 25 + - PINSEL_PIN_26 : Pin 26 + - PINSEL_PIN_27 : Pin 27 + - PINSEL_PIN_28 : Pin 28 + - PINSEL_PIN_29 : Pin 29 + - PINSEL_PIN_30 : Pin 30 + - PINSEL_PIN_31 : Pin 31 + + * @param[in] funcnum Function number, + * should be one of the following: + * - PINSEL_FUNC_0 : default function + * - PINSEL_FUNC_1 : first alternate function + * - PINSEL_FUNC_2 : second alternate function + * - PINSEL_FUNC_3 : third alternate function + * + * @return None + **********************************************************************/ +static void set_PinFunc ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum) +{ + uint32_t pinnum_t = pinnum; + uint32_t pinselreg_idx = 2 * portnum; + uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINSEL0; + + if (pinnum_t >= 16) { + pinnum_t -= 16; + pinselreg_idx++; + } + *(uint32_t *)(pPinCon + pinselreg_idx) &= ~(0x03UL << (pinnum_t * 2)); + *(uint32_t *)(pPinCon + pinselreg_idx) |= ((uint32_t)funcnum) << (pinnum_t * 2); +} + +/*********************************************************************//** + * @brief Setup resistor mode for each pin + * @param[in] portnum PORT number, + * should be one of the following: + * - PINSEL_PORT_0 : Port 0 + * - PINSEL_PORT_1 : Port 1 + * - PINSEL_PORT_2 : Port 2 + * - PINSEL_PORT_3 : Port 3 + * @param[in] pinnum Pin number, + * should be one of the following: + - PINSEL_PIN_0 : Pin 0 + - PINSEL_PIN_1 : Pin 1 + - PINSEL_PIN_2 : Pin 2 + - PINSEL_PIN_3 : Pin 3 + - PINSEL_PIN_4 : Pin 4 + - PINSEL_PIN_5 : Pin 5 + - PINSEL_PIN_6 : Pin 6 + - PINSEL_PIN_7 : Pin 7 + - PINSEL_PIN_8 : Pin 8 + - PINSEL_PIN_9 : Pin 9 + - PINSEL_PIN_10 : Pin 10 + - PINSEL_PIN_11 : Pin 11 + - PINSEL_PIN_12 : Pin 12 + - PINSEL_PIN_13 : Pin 13 + - PINSEL_PIN_14 : Pin 14 + - PINSEL_PIN_15 : Pin 15 + - PINSEL_PIN_16 : Pin 16 + - PINSEL_PIN_17 : Pin 17 + - PINSEL_PIN_18 : Pin 18 + - PINSEL_PIN_19 : Pin 19 + - PINSEL_PIN_20 : Pin 20 + - PINSEL_PIN_21 : Pin 21 + - PINSEL_PIN_22 : Pin 22 + - PINSEL_PIN_23 : Pin 23 + - PINSEL_PIN_24 : Pin 24 + - PINSEL_PIN_25 : Pin 25 + - PINSEL_PIN_26 : Pin 26 + - PINSEL_PIN_27 : Pin 27 + - PINSEL_PIN_28 : Pin 28 + - PINSEL_PIN_29 : Pin 29 + - PINSEL_PIN_30 : Pin 30 + - PINSEL_PIN_31 : Pin 31 + + * @param[in] modenum: Mode number, + * should be one of the following: + - PINSEL_PINMODE_PULLUP : Internal pull-up resistor + - PINSEL_PINMODE_TRISTATE : Tri-state + - PINSEL_PINMODE_PULLDOWN : Internal pull-down resistor + + * @return None + **********************************************************************/ +void set_ResistorMode ( uint8_t portnum, uint8_t pinnum, uint8_t modenum) +{ + uint32_t pinnum_t = pinnum; + uint32_t pinmodereg_idx = 2 * portnum; + uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINMODE0; + + if (pinnum_t >= 16) { + pinnum_t -= 16; + pinmodereg_idx++ ; + } + + *(uint32_t *)(pPinCon + pinmodereg_idx) &= ~(0x03UL << (pinnum_t * 2)); + *(uint32_t *)(pPinCon + pinmodereg_idx) |= ((uint32_t)modenum) << (pinnum_t * 2); +} + +/*********************************************************************//** + * @brief Setup Open drain mode for each pin + * @param[in] portnum PORT number, + * should be one of the following: + * - PINSEL_PORT_0 : Port 0 + * - PINSEL_PORT_1 : Port 1 + * - PINSEL_PORT_2 : Port 2 + * - PINSEL_PORT_3 : Port 3 + * + * @param[in] pinnum Pin number, + * should be one of the following: + - PINSEL_PIN_0 : Pin 0 + - PINSEL_PIN_1 : Pin 1 + - PINSEL_PIN_2 : Pin 2 + - PINSEL_PIN_3 : Pin 3 + - PINSEL_PIN_4 : Pin 4 + - PINSEL_PIN_5 : Pin 5 + - PINSEL_PIN_6 : Pin 6 + - PINSEL_PIN_7 : Pin 7 + - PINSEL_PIN_8 : Pin 8 + - PINSEL_PIN_9 : Pin 9 + - PINSEL_PIN_10 : Pin 10 + - PINSEL_PIN_11 : Pin 11 + - PINSEL_PIN_12 : Pin 12 + - PINSEL_PIN_13 : Pin 13 + - PINSEL_PIN_14 : Pin 14 + - PINSEL_PIN_15 : Pin 15 + - PINSEL_PIN_16 : Pin 16 + - PINSEL_PIN_17 : Pin 17 + - PINSEL_PIN_18 : Pin 18 + - PINSEL_PIN_19 : Pin 19 + - PINSEL_PIN_20 : Pin 20 + - PINSEL_PIN_21 : Pin 21 + - PINSEL_PIN_22 : Pin 22 + - PINSEL_PIN_23 : Pin 23 + - PINSEL_PIN_24 : Pin 24 + - PINSEL_PIN_25 : Pin 25 + - PINSEL_PIN_26 : Pin 26 + - PINSEL_PIN_27 : Pin 27 + - PINSEL_PIN_28 : Pin 28 + - PINSEL_PIN_29 : Pin 29 + - PINSEL_PIN_30 : Pin 30 + - PINSEL_PIN_31 : Pin 31 + + * @param[in] modenum Open drain mode number, + * should be one of the following: + * - PINSEL_PINMODE_NORMAL : Pin is in the normal (not open drain) mode + * - PINSEL_PINMODE_OPENDRAIN : Pin is in the open drain mode + * + * @return None + **********************************************************************/ +void set_OpenDrainMode( uint8_t portnum, uint8_t pinnum, uint8_t modenum) +{ + uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINMODE_OD0; + + if (modenum == PINSEL_PINMODE_OPENDRAIN){ + *(uint32_t *)(pPinCon + portnum) |= (0x01UL << pinnum); + } else { + *(uint32_t *)(pPinCon + portnum) &= ~(0x01UL << pinnum); + } +} + +/* End of Public Functions ---------------------------------------------------- */ + +/* Public Functions ----------------------------------------------------------- */ +/** @addtogroup PINSEL_Public_Functions + * @{ + */ +/*********************************************************************//** + * @brief Configure trace function + * @param[in] NewState State of the Trace function configuration, + * should be one of the following: + * - ENABLE : Enable Trace Function + * - DISABLE : Disable Trace Function + * + * @return None + **********************************************************************/ +void PINSEL_ConfigTraceFunc(FunctionalState NewState) +{ + if (NewState == ENABLE) { + LPC_PINCON->PINSEL10 |= (0x01UL << 3); + } else if (NewState == DISABLE) { + LPC_PINCON->PINSEL10 &= ~(0x01UL << 3); + } +} + +/*********************************************************************//** + * @brief Setup I2C0 pins + * @param[in] i2cPinMode I2C pin mode, + * should be one of the following: + * - PINSEL_I2C_Normal_Mode : The standard drive mode + * - PINSEL_I2C_Fast_Mode : Fast Mode Plus drive mode + * + * @param[in] filterSlewRateEnable should be: + * - ENABLE: Enable filter and slew rate. + * - DISABLE: Disable filter and slew rate. + * + * @return None + **********************************************************************/ +void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable) +{ + uint32_t regVal = 0; + + if (i2cPinMode == PINSEL_I2C_Fast_Mode){ + regVal = PINSEL_I2CPADCFG_SCLDRV0 | PINSEL_I2CPADCFG_SDADRV0; + } + + if (filterSlewRateEnable == DISABLE){ + regVal = PINSEL_I2CPADCFG_SCLI2C0 | PINSEL_I2CPADCFG_SDAI2C0; + } + LPC_PINCON->I2CPADCFG = regVal; +} + + +/*********************************************************************//** + * @brief Configure Pin corresponding to specified parameters passed + * in the PinCfg + * @param[in] PinCfg Pointer to a PINSEL_CFG_Type structure + * that contains the configuration information for the + * specified pin. + * @return None + **********************************************************************/ +void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg) +{ + set_PinFunc(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->Funcnum); + set_ResistorMode(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->Pinmode); + set_OpenDrainMode(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->OpenDrain); +} + + +/** + * @} + */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_pinsel.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,191 @@ +/***********************************************************************//** + * @file lpc17xx_pinsel.h + * @brief Contains all macro definitions and function prototypes + * support for Pin connect block firmware library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup PINSEL PINSEL + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_PINSEL_H_ +#define LPC17XX_PINSEL_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup PINSEL_Public_Macros PINSEL Public Macros + * @{ + */ + +/*********************************************************************//** + *!< Macros define for PORT Selection + ***********************************************************************/ +#define PINSEL_PORT_0 ((0)) /**< PORT 0*/ +#define PINSEL_PORT_1 ((1)) /**< PORT 1*/ +#define PINSEL_PORT_2 ((2)) /**< PORT 2*/ +#define PINSEL_PORT_3 ((3)) /**< PORT 3*/ +#define PINSEL_PORT_4 ((4)) /**< PORT 4*/ + +/*********************************************************************** + * Macros define for Pin Function selection + **********************************************************************/ +#define PINSEL_FUNC_0 ((0)) /**< default function*/ +#define PINSEL_FUNC_1 ((1)) /**< first alternate function*/ +#define PINSEL_FUNC_2 ((2)) /**< second alternate function*/ +#define PINSEL_FUNC_3 ((3)) /**< third or reserved alternate function*/ + +/*********************************************************************** + * Macros define for Pin Number of Port + **********************************************************************/ +#define PINSEL_PIN_0 ((0)) /**< Pin 0 */ +#define PINSEL_PIN_1 ((1)) /**< Pin 1 */ +#define PINSEL_PIN_2 ((2)) /**< Pin 2 */ +#define PINSEL_PIN_3 ((3)) /**< Pin 3 */ +#define PINSEL_PIN_4 ((4)) /**< Pin 4 */ +#define PINSEL_PIN_5 ((5)) /**< Pin 5 */ +#define PINSEL_PIN_6 ((6)) /**< Pin 6 */ +#define PINSEL_PIN_7 ((7)) /**< Pin 7 */ +#define PINSEL_PIN_8 ((8)) /**< Pin 8 */ +#define PINSEL_PIN_9 ((9)) /**< Pin 9 */ +#define PINSEL_PIN_10 ((10)) /**< Pin 10 */ +#define PINSEL_PIN_11 ((11)) /**< Pin 11 */ +#define PINSEL_PIN_12 ((12)) /**< Pin 12 */ +#define PINSEL_PIN_13 ((13)) /**< Pin 13 */ +#define PINSEL_PIN_14 ((14)) /**< Pin 14 */ +#define PINSEL_PIN_15 ((15)) /**< Pin 15 */ +#define PINSEL_PIN_16 ((16)) /**< Pin 16 */ +#define PINSEL_PIN_17 ((17)) /**< Pin 17 */ +#define PINSEL_PIN_18 ((18)) /**< Pin 18 */ +#define PINSEL_PIN_19 ((19)) /**< Pin 19 */ +#define PINSEL_PIN_20 ((20)) /**< Pin 20 */ +#define PINSEL_PIN_21 ((21)) /**< Pin 21 */ +#define PINSEL_PIN_22 ((22)) /**< Pin 22 */ +#define PINSEL_PIN_23 ((23)) /**< Pin 23 */ +#define PINSEL_PIN_24 ((24)) /**< Pin 24 */ +#define PINSEL_PIN_25 ((25)) /**< Pin 25 */ +#define PINSEL_PIN_26 ((26)) /**< Pin 26 */ +#define PINSEL_PIN_27 ((27)) /**< Pin 27 */ +#define PINSEL_PIN_28 ((28)) /**< Pin 28 */ +#define PINSEL_PIN_29 ((29)) /**< Pin 29 */ +#define PINSEL_PIN_30 ((30)) /**< Pin 30 */ +#define PINSEL_PIN_31 ((31)) /**< Pin 31 */ + +/*********************************************************************** + * Macros define for Pin mode + **********************************************************************/ +#define PINSEL_PINMODE_PULLUP ((0)) /**< Internal pull-up resistor*/ +#define PINSEL_PINMODE_TRISTATE ((2)) /**< Tri-state */ +#define PINSEL_PINMODE_PULLDOWN ((3)) /**< Internal pull-down resistor */ + +/*********************************************************************** + * Macros define for Pin mode (normal/open drain) + **********************************************************************/ +#define PINSEL_PINMODE_NORMAL ((0)) /**< Pin is in the normal (not open drain) mode.*/ +#define PINSEL_PINMODE_OPENDRAIN ((1)) /**< Pin is in the open drain mode */ + +/*********************************************************************** + * Macros define for I2C mode + ***********************************************************************/ +#define PINSEL_I2C_Normal_Mode ((0)) /**< The standard drive mode */ +#define PINSEL_I2C_Fast_Mode ((1)) /**< Fast Mode Plus drive mode */ + +/** + * @} + */ + +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup PINSEL_Private_Macros PINSEL Private Macros + * @{ + */ + +/* Pin selection define */ +/* I2C Pin Configuration register bit description */ +#define PINSEL_I2CPADCFG_SDADRV0 _BIT(0) /**< Drive mode control for the SDA0 pin, P0.27 */ +#define PINSEL_I2CPADCFG_SDAI2C0 _BIT(1) /**< I2C mode control for the SDA0 pin, P0.27 */ +#define PINSEL_I2CPADCFG_SCLDRV0 _BIT(2) /**< Drive mode control for the SCL0 pin, P0.28 */ +#define PINSEL_I2CPADCFG_SCLI2C0 _BIT(3) /**< I2C mode control for the SCL0 pin, P0.28 */ + +/** + * @} + */ + + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup PINSEL_Public_Types PINSEL Public Types + * @{ + */ + +/** @brief Pin configuration structure */ +typedef struct +{ + uint8_t Portnum; /**< Port Number, should be PINSEL_PORT_x, + where x should be in range from 0 to 4 */ + uint8_t Pinnum; /**< Pin Number, should be PINSEL_PIN_x, + where x should be in range from 0 to 31 */ + uint8_t Funcnum; /**< Function Number, should be PINSEL_FUNC_x, + where x should be in range from 0 to 3 */ + uint8_t Pinmode; /**< Pin Mode, should be: + - PINSEL_PINMODE_PULLUP: Internal pull-up resistor + - PINSEL_PINMODE_TRISTATE: Tri-state + - PINSEL_PINMODE_PULLDOWN: Internal pull-down resistor */ + uint8_t OpenDrain; /**< OpenDrain mode, should be: + - PINSEL_PINMODE_NORMAL: Pin is in the normal (not open drain) mode + - PINSEL_PINMODE_OPENDRAIN: Pin is in the open drain mode */ +} PINSEL_CFG_Type; + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup PINSEL_Public_Functions PINSEL Public Functions + * @{ + */ + +void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg); +void PINSEL_ConfigTraceFunc (FunctionalState NewState); +void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable); + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LPC17XX_PINSEL_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_uart.c Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,1366 @@ +/***********************************************************************//** + * @file lpc17xx_uart.c + * @brief Contains all functions support for UART firmware library on LPC17xx + * @version 3.0 + * @date 18. June. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @addtogroup UART + * @{ + */ + +/* Includes ------------------------------------------------------------------- */ +#include "lpc17xx_uart.h" +#include "lpc17xx_clkpwr.h" + +/* If this source file built with example, the LPC17xx FW library configuration + * file in each example directory ("lpc17xx_libcfg.h") must be included, + * otherwise the default FW library configuration file must be included instead + */ +#ifdef __BUILD_WITH_EXAMPLE__ +#include "lpc17xx_libcfg.h" +#else +#include "lpc17xx_libcfg_default.h" +#endif /* __BUILD_WITH_EXAMPLE__ */ + + +#ifdef _UART + +/* Private Functions ---------------------------------------------------------- */ + +static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate); + + +/*********************************************************************//** + * @brief Determines best dividers to get a target clock rate + * @param[in] UARTx Pointer to selected UART peripheral, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] baudrate Desired UART baud rate. + * @return Error status, could be: + * - SUCCESS + * - ERROR + **********************************************************************/ +static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate) +{ + Status errorStatus = ERROR; + + uint32_t uClk = 0; + uint32_t calcBaudrate = 0; + uint32_t temp = 0; + + uint32_t mulFracDiv, dividerAddFracDiv; + uint32_t diviser = 0 ; + uint32_t mulFracDivOptimal = 1; + uint32_t dividerAddOptimal = 0; + uint32_t diviserOptimal = 0; + + uint32_t relativeError = 0; + uint32_t relativeOptimalError = 100000; + + /* get UART block clock */ + if (UARTx == (LPC_UART_TypeDef *)LPC_UART0) + { + uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART0); + } + else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1) + { + uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART1); + } + else if (UARTx == LPC_UART2) + { + uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART2); + } + else if (UARTx == LPC_UART3) + { + uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART3); + } + + + uClk = uClk >> 4; /* div by 16 */ + /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers + * The formula is : + * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) + * It involves floating point calculations. That's the reason the formulae are adjusted with + * Multiply and divide method.*/ + /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: + * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */ + for (mulFracDiv = 1 ; mulFracDiv <= 15 ;mulFracDiv++) + { + for (dividerAddFracDiv = 0 ; dividerAddFracDiv <= 15 ;dividerAddFracDiv++) + { + temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv)); + + diviser = temp / baudrate; + if ((temp % baudrate) > (baudrate / 2)) + diviser++; + + if (diviser > 2 && diviser < 65536) + { + calcBaudrate = temp / diviser; + + if (calcBaudrate <= baudrate) + relativeError = baudrate - calcBaudrate; + else + relativeError = calcBaudrate - baudrate; + + if ((relativeError < relativeOptimalError)) + { + mulFracDivOptimal = mulFracDiv ; + dividerAddOptimal = dividerAddFracDiv; + diviserOptimal = diviser; + relativeOptimalError = relativeError; + if (relativeError == 0) + break; + } + } /* End of if */ + } /* end of inner for loop */ + if (relativeError == 0) + break; + } /* end of outer for loop */ + + if (relativeOptimalError < ((baudrate * UART_ACCEPTED_BAUDRATE_ERROR)/100)) + { + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; + ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal); + ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal); + /* Then reset DLAB bit */ + ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; + ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \ + | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK; + } + else + { + UARTx->LCR |= UART_LCR_DLAB_EN; + UARTx->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal); + UARTx->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal); + /* Then reset DLAB bit */ + UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; + UARTx->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \ + | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK; + } + errorStatus = SUCCESS; + } + + return errorStatus; +} + +/* End of Private Functions ---------------------------------------------------- */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @addtogroup UART_Public_Functions + * @{ + */ +/* UART Init/DeInit functions -------------------------------------------------*/ +/********************************************************************//** + * @brief Initializes the UARTx peripheral according to the specified + * parameters in the UART_ConfigStruct. + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure +* that contains the configuration information for the +* specified UART peripheral. + * @return None + *********************************************************************/ +void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct) +{ + uint32_t tmp; + + // For debug mode + CHECK_PARAM(PARAM_UARTx(UARTx)); + CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits)); + CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits)); + CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity)); + +#ifdef _UART0 + if(UARTx == (LPC_UART_TypeDef *)LPC_UART0) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE); + } +#endif + +#ifdef _UART1 + if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE); + } +#endif + +#ifdef _UART2 + if(UARTx == LPC_UART2) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE); + } +#endif + +#ifdef _UART3 + if(UARTx == LPC_UART3) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE); + } +#endif + + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + /* FIFOs are empty */ + ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN \ + | UART_FCR_RX_RS | UART_FCR_TX_RS); + // Disable FIFO + ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = 0; + + // Dummy reading + while (((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_RDR) + { + tmp = ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR; + } + + ((LPC_UART1_TypeDef *)UARTx)->TER = UART_TER_TXEN; + // Wait for current transmit complete + while (!(((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_THRE)); + // Disable Tx + ((LPC_UART1_TypeDef *)UARTx)->TER = 0; + + // Disable interrupt + ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER = 0; + // Set LCR to default state + ((LPC_UART1_TypeDef *)UARTx)->LCR = 0; + // Set ACR to default state + ((LPC_UART1_TypeDef *)UARTx)->ACR = 0; + // Set Modem Control to default state + ((LPC_UART1_TypeDef *)UARTx)->MCR = 0; + // Set RS485 control to default state + ((LPC_UART1_TypeDef *)UARTx)->RS485CTRL = 0; + // Set RS485 delay timer to default state + ((LPC_UART1_TypeDef *)UARTx)->RS485DLY = 0; + // Set RS485 addr match to default state + ((LPC_UART1_TypeDef *)UARTx)->ADRMATCH = 0; + //Dummy Reading to Clear Status + tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR; + tmp = ((LPC_UART1_TypeDef *)UARTx)->LSR; + } + else + { + /* FIFOs are empty */ + UARTx->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); + // Disable FIFO + UARTx->/*IIFCR.*/FCR = 0; + + // Dummy reading + while (UARTx->LSR & UART_LSR_RDR) + { + tmp = UARTx->/*RBTHDLR.*/RBR; + } + + UARTx->TER = UART_TER_TXEN; + // Wait for current transmit complete + while (!(UARTx->LSR & UART_LSR_THRE)); + // Disable Tx + UARTx->TER = 0; + + // Disable interrupt + UARTx->/*DLIER.*/IER = 0; + // Set LCR to default state + UARTx->LCR = 0; + // Set ACR to default state + UARTx->ACR = 0; + // Dummy reading + tmp = UARTx->LSR; + } + + if (UARTx == LPC_UART3) + { + // Set IrDA to default state + UARTx->ICR = 0; + } + + // Set Line Control register ---------------------------- + + uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate)); + + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \ + & UART_LCR_BITMASK; + } + else + { + tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK; + } + + switch (UART_ConfigStruct->Databits){ + case UART_DATABIT_5: + tmp |= UART_LCR_WLEN5; + break; + case UART_DATABIT_6: + tmp |= UART_LCR_WLEN6; + break; + case UART_DATABIT_7: + tmp |= UART_LCR_WLEN7; + break; + case UART_DATABIT_8: + default: + tmp |= UART_LCR_WLEN8; + break; + } + + if (UART_ConfigStruct->Parity == UART_PARITY_NONE) + { + // Do nothing... + } + else + { + tmp |= UART_LCR_PARITY_EN; + switch (UART_ConfigStruct->Parity) + { + case UART_PARITY_ODD: + tmp |= UART_LCR_PARITY_ODD; + break; + + case UART_PARITY_EVEN: + tmp |= UART_LCR_PARITY_EVEN; + break; + + case UART_PARITY_SP_1: + tmp |= UART_LCR_PARITY_F_1; + break; + + case UART_PARITY_SP_0: + tmp |= UART_LCR_PARITY_F_0; + break; + default: + break; + } + } + + switch (UART_ConfigStruct->Stopbits){ + case UART_STOPBIT_2: + tmp |= UART_LCR_STOPBIT_SEL; + break; + case UART_STOPBIT_1: + default: + // Do no thing + break; + } + + + // Write back to LCR, configure FIFO and Disable Tx + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); + } + else + { + UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); + } +} + +/*********************************************************************//** + * @brief De-initializes the UARTx peripheral registers to their + * default reset values. + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return None + **********************************************************************/ +void UART_DeInit(LPC_UART_TypeDef* UARTx) +{ + // For debug mode + CHECK_PARAM(PARAM_UARTx(UARTx)); + + UART_TxCmd(UARTx, DISABLE); + +#ifdef _UART0 + if (UARTx == (LPC_UART_TypeDef *)LPC_UART0) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE); + } +#endif + +#ifdef _UART1 + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE); + } +#endif + +#ifdef _UART2 + if (UARTx == LPC_UART2) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE); + } +#endif + +#ifdef _UART3 + if (UARTx == LPC_UART3) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE); + } +#endif +} + +/*****************************************************************************//** +* @brief Fills each UART_InitStruct member with its default value: +* - 9600 bps +* - 8-bit data +* - 1 Stopbit +* - None Parity +* @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure +* which will be initialized. +* @return None +*******************************************************************************/ +void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct) +{ + UART_InitStruct->Baud_rate = 9600; + UART_InitStruct->Databits = UART_DATABIT_8; + UART_InitStruct->Parity = UART_PARITY_NONE; + UART_InitStruct->Stopbits = UART_STOPBIT_1; +} + +/* UART Send/Recieve functions -------------------------------------------------*/ +/*********************************************************************//** + * @brief Transmit a single data through UART peripheral + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] Data Data to transmit (must be 8-bit long) + * @return None + **********************************************************************/ +void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data) +{ + CHECK_PARAM(PARAM_UARTx(UARTx)); + + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT; + } + else + { + UARTx->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT; + } + +} + + +/*********************************************************************//** + * @brief Receive a single data from UART peripheral + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return Data received + **********************************************************************/ +uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx) +{ + CHECK_PARAM(PARAM_UARTx(UARTx)); + + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + return (((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT); + } + else + { + return (UARTx->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT); + } +} + +/*********************************************************************//** + * @brief Send a block of data via UART peripheral + * @param[in] UARTx Selected UART peripheral used to send data, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] txbuf Pointer to Transmit buffer + * @param[in] buflen Length of Transmit buffer + * @param[in] flag Flag used in UART transfer, should be + * NONE_BLOCKING or BLOCKING + * @return Number of bytes sent. + * + * Note: when using UART in BLOCKING mode, a time-out condition is used + * via defined symbol UART_BLOCKING_TIMEOUT. + **********************************************************************/ +uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, + uint32_t buflen, TRANSFER_BLOCK_Type flag) +{ + uint32_t bToSend, bSent, timeOut, fifo_cnt; + uint8_t *pChar = txbuf; + + bToSend = buflen; + + // blocking mode + if (flag == BLOCKING) { + bSent = 0; + while (bToSend){ + timeOut = UART_BLOCKING_TIMEOUT; + // Wait for THR empty with timeout + while (!(UARTx->LSR & UART_LSR_THRE)) { + if (timeOut == 0) break; + timeOut--; + } + // Time out! + if(timeOut == 0) break; + fifo_cnt = UART_TX_FIFO_SIZE; + while (fifo_cnt && bToSend){ + UART_SendByte(UARTx, (*pChar++)); + fifo_cnt--; + bToSend--; + bSent++; + } + } + } + // None blocking mode + else { + bSent = 0; + while (bToSend) { + if (!(UARTx->LSR & UART_LSR_THRE)){ + break; + } + fifo_cnt = UART_TX_FIFO_SIZE; + while (fifo_cnt && bToSend) { + UART_SendByte(UARTx, (*pChar++)); + bToSend--; + fifo_cnt--; + bSent++; + } + } + } + return bSent; +} + +/*********************************************************************//** + * @brief Receive a block of data via UART peripheral + * @param[in] UARTx Selected UART peripheral used to send data, + * should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[out] rxbuf Pointer to Received buffer + * @param[in] buflen Length of Received buffer + * @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING + + * @return Number of bytes received + * + * Note: when using UART in BLOCKING mode, a time-out condition is used + * via defined symbol UART_BLOCKING_TIMEOUT. + **********************************************************************/ +uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ + uint32_t buflen, TRANSFER_BLOCK_Type flag) +{ + uint32_t bToRecv, bRecv, timeOut; + uint8_t *pChar = rxbuf; + + bToRecv = buflen; + + // Blocking mode + if (flag == BLOCKING) { + bRecv = 0; + while (bToRecv){ + timeOut = UART_BLOCKING_TIMEOUT; + while (!(UARTx->LSR & UART_LSR_RDR)){ + if (timeOut == 0) break; + timeOut--; + } + // Time out! + if(timeOut == 0) break; + // Get data from the buffer + (*pChar++) = UART_ReceiveByte(UARTx); + bToRecv--; + bRecv++; + } + } + // None blocking mode + else { + bRecv = 0; + while (bToRecv) { + if (!(UARTx->LSR & UART_LSR_RDR)) { + break; + } else { + (*pChar++) = UART_ReceiveByte(UARTx); + bRecv++; + bToRecv--; + } + } + } + return bRecv; +} + +/*********************************************************************//** + * @brief Force BREAK character on UART line, output pin UARTx TXD is + forced to logic 0. + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return None + **********************************************************************/ +void UART_ForceBreak(LPC_UART_TypeDef* UARTx) +{ + CHECK_PARAM(PARAM_UARTx(UARTx)); + + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN; + } + else + { + UARTx->LCR |= UART_LCR_BREAK_EN; + } +} + + +/********************************************************************//** + * @brief Enable or disable specified UART interrupt. + * @param[in] UARTx UART peripheral selected, should be + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] UARTIntCfg Specifies the interrupt flag, + * should be one of the following: + - UART_INTCFG_RBR : RBR Interrupt enable + - UART_INTCFG_THRE : THR Interrupt enable + - UART_INTCFG_RLS : RX line status interrupt enable + - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only) + - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only) + - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt + - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt + * @param[in] NewState New state of specified UART interrupt type, + * should be: + * - ENALBE: Enable this UART interrupt type. +* - DISALBE: Disable this UART interrupt type. + * @return None + *********************************************************************/ +void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState) +{ + uint32_t tmp = 0; + + CHECK_PARAM(PARAM_UARTx(UARTx)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); + + switch(UARTIntCfg){ + case UART_INTCFG_RBR: + tmp = UART_IER_RBRINT_EN; + break; + case UART_INTCFG_THRE: + tmp = UART_IER_THREINT_EN; + break; + case UART_INTCFG_RLS: + tmp = UART_IER_RLSINT_EN; + break; + case UART1_INTCFG_MS: + tmp = UART1_IER_MSINT_EN; + break; + case UART1_INTCFG_CTS: + tmp = UART1_IER_CTSINT_EN; + break; + case UART_INTCFG_ABEO: + tmp = UART_IER_ABEOINT_EN; + break; + case UART_INTCFG_ABTO: + tmp = UART_IER_ABTOINT_EN; + break; + } + + if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) + { + CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) || (PARAM_UART1_INTCFG(UARTIntCfg))); + } + else + { + CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg)); + } + + if (NewState == ENABLE) + { + if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER |= tmp; + } + else + { + UARTx->/*DLIER.*/IER |= tmp; + } + } + else + { + if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK; + } + else + { + UARTx->/*DLIER.*/IER &= (~tmp) & UART_IER_BITMASK; + } + } +} + + +/********************************************************************//** + * @brief Get current value of Line Status register in UART peripheral. + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return Current value of Line Status register in UART peripheral. + * Note: The return value of this function must be ANDed with each member in + * UART_LS_Type enumeration to determine current flag status + * corresponding to each Line status type. Because some flags in + * Line Status register will be cleared after reading, the next reading + * Line Status register could not be correct. So this function used to + * read Line status register in one time only, then the return value + * used to check all flags. + *********************************************************************/ +uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx) +{ + CHECK_PARAM(PARAM_UARTx(UARTx)); + + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK); + } + else + { + return ((UARTx->LSR) & UART_LSR_BITMASK); + } +} + +/********************************************************************//** + * @brief Get Interrupt Identification value + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return Current value of UART UIIR register in UART peripheral. + *********************************************************************/ +uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx) +{ + CHECK_PARAM(PARAM_UARTx(UARTx)); + return (UARTx->IIR & 0x03CF); +} + +/*********************************************************************//** + * @brief Check whether if UART is busy or not + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return RESET if UART is not busy, otherwise return SET. + **********************************************************************/ +FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx) +{ + if (UARTx->LSR & UART_LSR_TEMT){ + return RESET; + } else { + return SET; + } +} + + +/*********************************************************************//** + * @brief Configure FIFO function on selected UART peripheral + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that + * contains specified information about FIFO configuration + * @return none + **********************************************************************/ +void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg) +{ + uint8_t tmp = 0; + + CHECK_PARAM(PARAM_UARTx(UARTx)); + CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf)); + + tmp |= UART_FCR_FIFO_EN; + switch (FIFOCfg->FIFO_Level){ + case UART_FIFO_TRGLEV0: + tmp |= UART_FCR_TRG_LEV0; + break; + case UART_FIFO_TRGLEV1: + tmp |= UART_FCR_TRG_LEV1; + break; + case UART_FIFO_TRGLEV2: + tmp |= UART_FCR_TRG_LEV2; + break; + case UART_FIFO_TRGLEV3: + default: + tmp |= UART_FCR_TRG_LEV3; + break; + } + + if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) + { + tmp |= UART_FCR_TX_RS; + } + if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) + { + tmp |= UART_FCR_RX_RS; + } + if (FIFOCfg->FIFO_DMAMode == ENABLE) + { + tmp |= UART_FCR_DMAMODE_SEL; + } + + + //write to FIFO control register + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK; + } + else + { + UARTx->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK; + } +} + +/*****************************************************************************//** +* @brief Fills each UART_FIFOInitStruct member with its default value: +* - FIFO_DMAMode = DISABLE +* - FIFO_Level = UART_FIFO_TRGLEV0 +* - FIFO_ResetRxBuf = ENABLE +* - FIFO_ResetTxBuf = ENABLE +* - FIFO_State = ENABLE + +* @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure +* which will be initialized. +* @return None +*******************************************************************************/ +void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct) +{ + UART_FIFOInitStruct->FIFO_DMAMode = DISABLE; + UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0; + UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE; + UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE; +} + + +/*********************************************************************//** + * @brief Start/Stop Auto Baudrate activity + * @param[in] UARTx UART peripheral selected, should be + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that + * contains specified information about UART + * auto baudrate configuration + * @param[in] NewState New State of Auto baudrate activity, should be: + * - ENABLE: Start this activity + * - DISABLE: Stop this activity + * Note: Auto-baudrate mode enable bit will be cleared once this mode + * completed. + * @return none + **********************************************************************/ +void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ + FunctionalState NewState) +{ + uint32_t tmp; + + CHECK_PARAM(PARAM_UARTx(UARTx)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); + + tmp = 0; + if (NewState == ENABLE) { + if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){ + tmp |= UART_ACR_MODE; + } + if (ABConfigStruct->AutoRestart == ENABLE){ + tmp |= UART_ACR_AUTO_RESTART; + } + } + + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + if (NewState == ENABLE) + { + // Clear DLL and DLM value + ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; + ((LPC_UART1_TypeDef *)UARTx)->DLL = 0; + ((LPC_UART1_TypeDef *)UARTx)->DLM = 0; + ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN; + // FDR value must be reset to default value + ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10; + ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp; + } + else + { + ((LPC_UART1_TypeDef *)UARTx)->ACR = 0; + } + } + else + { + if (NewState == ENABLE) + { + // Clear DLL and DLM value + UARTx->LCR |= UART_LCR_DLAB_EN; + UARTx->DLL = 0; + UARTx->DLM = 0; + UARTx->LCR &= ~UART_LCR_DLAB_EN; + // FDR value must be reset to default value + UARTx->FDR = 0x10; + UARTx->ACR = UART_ACR_START | tmp; + } + else + { + UARTx->ACR = 0; + } + } +} + +/*********************************************************************//** + * @brief Clear Autobaud Interrupt Pending + * @param[in] UARTx UART peripheral selected, should be + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] ABIntType type of auto-baud interrupt, should be: + * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt + * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt + * @return none + **********************************************************************/ +void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType) +{ + CHECK_PARAM(PARAM_UARTx(UARTx)); + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + UARTx->ACR |= ABIntType; + } + else + UARTx->ACR |= ABIntType; +} + +/*********************************************************************//** + * @brief Enable/Disable transmission on UART TxD pin + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] NewState New State of Tx transmission function, should be: + * - ENABLE: Enable this function + - DISABLE: Disable this function + * @return none + **********************************************************************/ +void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState) +{ + CHECK_PARAM(PARAM_UARTx(UARTx)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); + + if (NewState == ENABLE) + { + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN; + } + else + { + UARTx->TER |= UART_TER_TXEN; + } + } + else + { + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; + } + else + { + UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; + } + } +} + +/* UART IrDA functions ---------------------------------------------------*/ + +#ifdef _UART3 + +/*********************************************************************//** + * @brief Enable or disable inverting serial input function of IrDA + * on UART peripheral. + * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) + * @param[in] NewState New state of inverting serial input, should be: + * - ENABLE: Enable this function. + * - DISABLE: Disable this function. + * @return none + **********************************************************************/ +void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState) +{ + CHECK_PARAM(PARAM_UART_IrDA(UARTx)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->ICR |= UART_ICR_IRDAINV; + } + else if (NewState == DISABLE) + { + UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK; + } +} + + +/*********************************************************************//** + * @brief Enable or disable IrDA function on UART peripheral. + * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) + * @param[in] NewState New state of IrDA function, should be: + * - ENABLE: Enable this function. + * - DISABLE: Disable this function. + * @return none + **********************************************************************/ +void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState) +{ + CHECK_PARAM(PARAM_UART_IrDA(UARTx)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->ICR |= UART_ICR_IRDAEN; + } + else + { + UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK; + } +} + + +/*********************************************************************//** + * @brief Configure Pulse divider for IrDA function on UART peripheral. + * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) + * @param[in] PulseDiv Pulse Divider value from Peripheral clock, + * should be one of the following: + - UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk + - UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk + - UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk + - UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk + - UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk + - UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk + - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk + - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk + + * @return none + **********************************************************************/ +void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv) +{ + uint32_t tmp, tmp1; + CHECK_PARAM(PARAM_UART_IrDA(UARTx)); + CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv)); + + tmp1 = UART_ICR_PULSEDIV(PulseDiv); + tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7)); + tmp |= tmp1 | UART_ICR_FIXPULSE_EN; + UARTx->ICR = tmp & UART_ICR_BITMASK; +} + +#endif + + +/* UART1 FullModem function ---------------------------------------------*/ + +#ifdef _UART1 + +/*********************************************************************//** + * @brief Force pin DTR/RTS corresponding to given state (Full modem mode) + * @param[in] UARTx LPC_UART1 (only) + * @param[in] Pin Pin that NewState will be applied to, should be: + * - UART1_MODEM_PIN_DTR: DTR pin. + * - UART1_MODEM_PIN_RTS: RTS pin. + * @param[in] NewState New State of DTR/RTS pin, should be: + * - INACTIVE: Force the pin to inactive signal. + - ACTIVE: Force the pin to active signal. + * @return none + **********************************************************************/ +void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ + UART1_SignalState NewState) +{ + uint8_t tmp = 0; + + CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); + CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin)); + CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState)); + + switch (Pin){ + case UART1_MODEM_PIN_DTR: + tmp = UART1_MCR_DTR_CTRL; + break; + case UART1_MODEM_PIN_RTS: + tmp = UART1_MCR_RTS_CTRL; + break; + default: + break; + } + + if (NewState == ACTIVE){ + UARTx->MCR |= tmp; + } else { + UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; + } +} + + +/*********************************************************************//** + * @brief Configure Full Modem mode for UART peripheral + * @param[in] UARTx LPC_UART1 (only) + * @param[in] Mode Full Modem mode, should be: + * - UART1_MODEM_MODE_LOOPBACK: Loop back mode. + * - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode. + * - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode. + * @param[in] NewState New State of this mode, should be: + * - ENABLE: Enable this mode. + - DISABLE: Disable this mode. + * @return none + **********************************************************************/ +void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ + FunctionalState NewState) +{ + uint8_t tmp = 0; + + CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); + CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); + + switch(Mode){ + case UART1_MODEM_MODE_LOOPBACK: + tmp = UART1_MCR_LOOPB_EN; + break; + case UART1_MODEM_MODE_AUTO_RTS: + tmp = UART1_MCR_AUTO_RTS_EN; + break; + case UART1_MODEM_MODE_AUTO_CTS: + tmp = UART1_MCR_AUTO_CTS_EN; + break; + default: + break; + } + + if (NewState == ENABLE) + { + UARTx->MCR |= tmp; + } + else + { + UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; + } +} + + +/*********************************************************************//** + * @brief Get current status of modem status register + * @param[in] UARTx LPC_UART1 (only) + * @return Current value of modem status register + * Note: The return value of this function must be ANDed with each member + * UART_MODEM_STAT_type enumeration to determine current flag status + * corresponding to each modem flag status. Because some flags in + * modem status register will be cleared after reading, the next reading + * modem register could not be correct. So this function used to + * read modem status register in one time only, then the return value + * used to check all flags. + **********************************************************************/ +uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx) +{ + CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); + return ((UARTx->MSR) & UART1_MSR_BITMASK); +} + + +/* UART RS485 functions --------------------------------------------------------------*/ + +/*********************************************************************//** + * @brief Configure UART peripheral in RS485 mode according to the specified +* parameters in the RS485ConfigStruct. + * @param[in] UARTx LPC_UART1 (only) + * @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure +* that contains the configuration information for specified UART +* in RS485 mode. + * @return None + **********************************************************************/ +void UART_RS485Config(LPC_UART1_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct) +{ + uint32_t tmp; + + CHECK_PARAM(PARAM_UART1_MODEM(UARTx)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State)); + CHECK_PARAM(PARAM_UART1_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue)); + CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level)); + CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin)); + CHECK_PARAM(PARAM_UART1_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State)); + CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State)); + + tmp = 0; + // If Auto Direction Control is enabled - This function is used in Master mode + if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE) + { + tmp |= UART1_RS485CTRL_DCTRL_EN; + + // Set polar + if (RS485ConfigStruct->DirCtrlPol_Level == SET) + { + tmp |= UART1_RS485CTRL_OINV_1; + } + + // Set pin according to + if (RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR) + { + tmp |= UART1_RS485CTRL_SEL_DTR; + } + + // Fill delay time + UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK; + } + + // MultiDrop mode is enable + if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE) + { + tmp |= UART1_RS485CTRL_NMM_EN; + } + + // Auto Address Detect function + if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE) + { + tmp |= UART1_RS485CTRL_AADEN; + // Fill Match Address + UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK; + } + + + // Receiver is disable + if (RS485ConfigStruct->Rx_State == DISABLE) + { + tmp |= UART1_RS485CTRL_RX_DIS; + } + + // write back to RS485 control register + UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK; + + // Enable Parity function and leave parity in stick '0' parity as default + UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN); +} + +/*********************************************************************//** + * @brief Enable/Disable receiver in RS485 module in UART1 + * @param[in] UARTx LPC_UART1 (only) + * @param[in] NewState New State of command, should be: + * - ENABLE: Enable this function. + * - DISABLE: Disable this function. + * @return None + **********************************************************************/ +void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE){ + UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS; + } else { + UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS; + } +} + +/*********************************************************************//** + * @brief Send data on RS485 bus with specified parity stick value (9-bit mode). + * @param[in] UARTx LPC_UART1 (only) + * @param[in] pDatFrm Pointer to data frame. + * @param[in] size Size of data. + * @param[in] ParityStick Parity Stick value, should be 0 or 1. + * @return None + **********************************************************************/ +uint32_t UART_RS485Send(LPC_UART1_TypeDef *UARTx, uint8_t *pDatFrm, \ + uint32_t size, uint8_t ParityStick) +{ + uint8_t tmp, save; + uint32_t cnt; + + if (ParityStick){ + save = tmp = UARTx->LCR & UART_LCR_BITMASK; + tmp &= ~(UART_LCR_PARITY_EVEN); + UARTx->LCR = tmp; + cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); + while (!(UARTx->LSR & UART_LSR_TEMT)); + UARTx->LCR = save; + } else { + cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); + while (!(UARTx->LSR & UART_LSR_TEMT)); + } + return cnt; +} + +/*********************************************************************//** + * @brief Send Slave address frames on RS485 bus. + * @param[in] UARTx LPC_UART1 (only) + * @param[in] SlvAddr Slave Address. + * @return None + **********************************************************************/ +void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr) +{ + UART_RS485Send(UARTx, &SlvAddr, 1, 1); +} + +/*********************************************************************//** + * @brief Send Data frames on RS485 bus. + * @param[in] UARTx LPC_UART1 (only) + * @param[in] pData Pointer to data to be sent. + * @param[in] size Size of data frame to be sent. + * @return None + **********************************************************************/ +uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size) +{ + return (UART_RS485Send(UARTx, pData, size, 0)); +} + +#endif /* _UART1 */ + +#endif /* _UART */ + +/** + * @} + */ + +/** + * @} + */ +/* --------------------------------- End Of File ------------------------------ */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc17xx_uart.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,644 @@ +/***********************************************************************//** + * @file lpc17xx_uart.h + * @brief Contains all macro definitions and function prototypes + * support for UART firmware library on LPC17xx + * @version 3.0 + * @date 18. June. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup UART UART + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef __LPC17XX_UART_H +#define __LPC17XX_UART_H + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup UART_Public_Macros UART Public Macros + * @{ + */ + +/** UART time-out definitions in case of using Read() and Write function + * with Blocking Flag mode + */ +#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) + +/** + * @} + */ + +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + +/* Accepted Error baud rate value (in percent unit) */ +#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ + + +/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/*********************************************************************//** + * Macro defines for Macro defines for UARTn Receiver Buffer Register + **********************************************************************/ +#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */ + +/*********************************************************************//** + * Macro defines for Macro defines for UARTn Transmit Holding Register + **********************************************************************/ +#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */ + +/*********************************************************************//** + * Macro defines for Macro defines for UARTn Divisor Latch LSB register + **********************************************************************/ +#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */ +#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UARTn Divisor Latch MSB register + **********************************************************************/ +#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */ +#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART interrupt enable register + **********************************************************************/ +#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/ +#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/ +#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/ +#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */ +#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */ +#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */ +#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */ +#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */ +#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART interrupt identification register + **********************************************************************/ +#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */ +#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/ +#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/ +#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/ +#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/ +#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/ +#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */ +#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */ +#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */ +#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */ +#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART FIFO control register + **********************************************************************/ +#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */ +#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */ +#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */ +#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */ +#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */ +#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */ +#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */ +#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */ +#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */ +#define UART_TX_FIFO_SIZE (16) + +/*********************************************************************//** + * Macro defines for Macro defines for UART line control register + **********************************************************************/ +#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */ +#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */ +#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */ +#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */ +#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */ +#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */ +#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */ +#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */ +#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */ +#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */ +#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */ +#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */ +#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART1 Modem Control Register + **********************************************************************/ +#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */ +#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */ +#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */ +#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */ +#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */ +#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART line status register + **********************************************************************/ +#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/ +#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/ +#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/ +#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/ +#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/ +#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/ +#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/ +#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/ +#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART Modem (UART1 only) status register + **********************************************************************/ +#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */ +#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */ +#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */ +#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */ +#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */ +#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */ +#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */ +#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */ +#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART Scratch Pad Register + **********************************************************************/ +#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART Auto baudrate control register + **********************************************************************/ +#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */ +#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */ +#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */ +#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */ +#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */ +#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART IrDA control register + **********************************************************************/ +#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */ +#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */ +#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */ +#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */ +#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART Fractional divider register + **********************************************************************/ +#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */ +#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */ +#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART Tx Enable register + **********************************************************************/ +#define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */ +#define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART1 RS485 Control register + **********************************************************************/ +#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) + is disabled */ +#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */ +#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */ +#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled + (bit DCTRL = 1), pin DTR is used for direction control */ +#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */ +#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction + control signal on the RTS (or DTR) pin. The direction control pin + will be driven to logic "1" when the transmitter has data to be sent */ +#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART1 RS-485 Address Match register + **********************************************************************/ +#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART1 RS-485 Delay value register + **********************************************************************/ +/* Macro defines for UART1 RS-485 Delay value register */ +#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ + +/*********************************************************************//** + * Macro defines for Macro defines for UART FIFO Level register + **********************************************************************/ +#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */ +#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */ +#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */ + + +/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ + +/** Macro to check the input UART_DATABIT parameters */ +#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\ +|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8)) + +/** Macro to check the input UART_STOPBIT parameters */ +#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2)) + +/** Macro to check the input UART_PARITY parameters */ +#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \ +|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \ +|| (parity==UART_PARITY_SP_0)) + +/** Macro to check the input UART_FIFO parameters */ +#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \ +|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \ +|| (fifo==UART_FIFO_TRGLEV3)) + +/** Macro to check the input UART_INTCFG parameters */ +#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \ +|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \ +|| (IntCfg==UART_INTCFG_ABTO)) + +/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */ +#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS)) + +/** Macro to check the input UART_AUTOBAUD_MODE parameters */ +#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1)) + +/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */ +#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \ + (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO)) + +/** Macro to check the input UART_IrDA_PULSEDIV parameters */ +#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \ +|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \ +|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \ +|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256)) + +/* Macro to check the input UART1_SignalState parameters */ +#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE)) + +/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */ +#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS)) + +/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */ +#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \ +|| (x==UART1_MODEM_MODE_AUTO_CTS)) + +/** Macro to check the direction control pin type */ +#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR)) + +/* Macro to determine if it is valid UART port number */ +#define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \ +|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \ +|| (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \ +|| (((uint32_t *)x)==((uint32_t *)LPC_UART3))) +#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3)) +#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1)) + +/** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */ +#define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF)) + +/** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */ +#define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF)) + +/** + * @} + */ + + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ + +/** + * @brief UART Databit type definitions + */ +typedef enum { + UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ + UART_DATABIT_6, /*!< UART 6 bit data mode */ + UART_DATABIT_7, /*!< UART 7 bit data mode */ + UART_DATABIT_8 /*!< UART 8 bit data mode */ +} UART_DATABIT_Type; + +/** + * @brief UART Stop bit type definitions + */ +typedef enum { + UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ + UART_STOPBIT_2, /*!< UART Two Stop Bits Select */ +} UART_STOPBIT_Type; + +/** + * @brief UART Parity type definitions + */ +typedef enum { + UART_PARITY_NONE = 0, /*!< No parity */ + UART_PARITY_ODD, /*!< Odd parity */ + UART_PARITY_EVEN, /*!< Even parity */ + UART_PARITY_SP_1, /*!< Forced "1" stick parity */ + UART_PARITY_SP_0 /*!< Forced "0" stick parity */ +} UART_PARITY_Type; + +/** + * @brief FIFO Level type definitions + */ +typedef enum { + UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ + UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ + UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ + UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ +} UART_FITO_LEVEL_Type; + +/********************************************************************//** +* @brief UART Interrupt Type definitions +**********************************************************************/ +typedef enum { + UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ + UART_INTCFG_THRE, /*!< THR Interrupt enable*/ + UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ + UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ + UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ + UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ + UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ +} UART_INT_Type; + +/** + * @brief UART Line Status Type definition + */ +typedef enum { + UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/ + UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/ + UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/ + UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/ + UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/ + UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/ + UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/ + UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/ +} UART_LS_Type; + +/** + * @brief UART Auto-baudrate mode type definition + */ +typedef enum { + UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */ + UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */ +} UART_AB_MODE_Type; + +/** + * @brief Auto Baudrate mode configuration type definition + */ +typedef struct { + UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */ + FunctionalState AutoRestart; /**< Auto Restart state */ +} UART_AB_CFG_Type; + +/** + * @brief UART End of Auto-baudrate type definition + */ +typedef enum { + UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */ + UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */ +}UART_ABEO_Type; + +/** + * UART IrDA Control type Definition + */ +typedef enum { + UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ + UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ + UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ + UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ + UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ + UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ + UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ + UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk + - Configures the pulse when FixPulseEn = 1 */ +} UART_IrDA_PULSE_Type; + +/********************************************************************//** +* @brief UART1 Full modem - Signal states definition +**********************************************************************/ +typedef enum { + INACTIVE = 0, /* In-active state */ + ACTIVE = !INACTIVE /* Active state */ +}UART1_SignalState; + +/** + * @brief UART modem status type definition + */ +typedef enum { + UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */ + UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */ + UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */ + UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */ + UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */ + UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */ + UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */ + UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */ +} UART_MODEM_STAT_type; + +/** + * @brief Modem output pin type definition + */ +typedef enum { + UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */ + UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */ +} UART_MODEM_PIN_Type; + +/** + * @brief UART Modem mode type definition + */ +typedef enum { + UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */ + UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */ + UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */ +} UART_MODEM_MODE_Type; + +/** + * @brief UART Direction Control Pin type definition + */ +typedef enum { + UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */ + UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */ +} UART_RS485_DIRCTRL_PIN_Type; + +/********************************************************************//** +* @brief UART Configuration Structure definition +**********************************************************************/ +typedef struct { + uint32_t Baud_rate; /**< UART baud rate */ + UART_PARITY_Type Parity; /**< Parity selection, should be: + - UART_PARITY_NONE: No parity + - UART_PARITY_ODD: Odd parity + - UART_PARITY_EVEN: Even parity + - UART_PARITY_SP_1: Forced "1" stick parity + - UART_PARITY_SP_0: Forced "0" stick parity + */ + UART_DATABIT_Type Databits; /**< Number of data bits, should be: + - UART_DATABIT_5: UART 5 bit data mode + - UART_DATABIT_6: UART 6 bit data mode + - UART_DATABIT_7: UART 7 bit data mode + - UART_DATABIT_8: UART 8 bit data mode + */ + UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be: + - UART_STOPBIT_1: UART 1 Stop Bits Select + - UART_STOPBIT_2: UART 2 Stop Bits Select + */ +} UART_CFG_Type; + +/********************************************************************//** +* @brief UART FIFO Configuration Structure definition +**********************************************************************/ + +typedef struct { + FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be: + - ENABLE: Reset Rx FIFO in UART + - DISABLE: Do not reset Rx FIFO in UART + */ + FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be: + - ENABLE: Reset Tx FIFO in UART + - DISABLE: Do not reset Tx FIFO in UART + */ + FunctionalState FIFO_DMAMode; /**< DMA mode, should be: + - ENABLE: Enable DMA mode in UART + - DISABLE: Disable DMA mode in UART + */ + UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be: + - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character + - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character + - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character + - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character + */ +} UART_FIFO_CFG_Type; + +/********************************************************************//** +* @brief UART1 Full modem - RS485 Control configuration type +**********************************************************************/ +typedef struct { + FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State: + - ENABLE: Enable this function. + - DISABLE: Disable this function. */ + FunctionalState Rx_State; /*!< Receiver State: + - ENABLE: Enable Receiver. + - DISABLE: Disable Receiver. */ + FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state: + - ENABLE: ENABLE this function. + - DISABLE: Disable this function. */ + FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State: + - ENABLE: Enable this function. + - DISABLE: Disable this function. */ + UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state: + - UART1_RS485_DIRCTRL_RTS: + pin RTS is used for direction control. + - UART1_RS485_DIRCTRL_DTR: + pin DTR is used for direction control. */ + SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on + the RTS (or DTR) pin: + - RESET: The direction control pin will be driven + to logic "0" when the transmitter has data to be sent. + - SET: The direction control pin will be driven + to logic "1" when the transmitter has data to be sent. */ + uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */ + uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */ +} UART1_RS485_CTRLCFG_Type; + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup UART_Public_Functions UART Public Functions + * @{ + */ +/* UART Init/DeInit functions --------------------------------------------------*/ +void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct); +void UART_DeInit(LPC_UART_TypeDef* UARTx); +void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct); + +/* UART Send/Receive functions -------------------------------------------------*/ +void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data); +uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx); +uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, + uint32_t buflen, TRANSFER_BLOCK_Type flag); +uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ + uint32_t buflen, TRANSFER_BLOCK_Type flag); + +/* UART FIFO functions ----------------------------------------------------------*/ +void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg); +void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct); + +/* UART get information functions -----------------------------------------------*/ +uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx); +uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx); + +/* UART operate functions -------------------------------------------------------*/ +void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \ + FunctionalState NewState); +void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState); +FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx); +void UART_ForceBreak(LPC_UART_TypeDef* UARTx); + +/* UART Auto-baud functions -----------------------------------------------------*/ +void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType); +void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ + FunctionalState NewState); + +/* UART1 FullModem functions ----------------------------------------------------*/ +void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ + UART1_SignalState NewState); +void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ + FunctionalState NewState); +uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx); + +/* UART RS485 functions ----------------------------------------------------------*/ +void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \ + UART1_RS485_CTRLCFG_Type *RS485ConfigStruct); +void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState); +void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr); +uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size); + +/* UART IrDA functions-------------------------------------------------------------*/ +void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); +void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); +void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv); +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __LPC17XX_UART_H */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lpc_types.h Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,196 @@ +/***********************************************************************//** + * @file lpc_types.h + * @brief Contains the NXP ABL typedefs for C standard types. + * It is intended to be used in ISO C conforming development + * environments and checks for this insofar as it is possible + * to do so. + * @version 1.0 + * @date 27 Jul. 2008 + * @author wellsk + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Type group ----------------------------------------------------------- */ +/** @defgroup LPC_Types LPC_Types + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC_TYPES_H +#define LPC_TYPES_H + +/* Includes ------------------------------------------------------------------- */ +#include <stdint.h> + + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup LPC_Types_Public_Types LPC_Types Public Types + * @{ + */ + +/** + * @brief Boolean Type definition + */ +typedef enum {FALSE = 0, TRUE = !FALSE} Bool; + +/** + * @brief Flag Status and Interrupt Flag Status type definition + */ +typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; +#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET)) + +/** + * @brief Functional State Definition + */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE)) + +/** + * @ Status type definition + */ +typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; + + +/** + * Read/Write transfer type mode (Block or non-block) + */ +typedef enum +{ + NONE_BLOCKING = 0, /**< None Blocking type */ + BLOCKING, /**< Blocking type */ +} TRANSFER_BLOCK_Type; + + +/** Pointer to Function returning Void (any number of parameters) */ +typedef void (*PFV)(); + +/** Pointer to Function returning int32_t (any number of parameters) */ +typedef int32_t(*PFI)(); + +/** + * @} + */ + + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros + * @{ + */ + +/* _BIT(n) sets the bit at position "n" + * _BIT(n) is intended to be used in "OR" and "AND" expressions: + * e.g., "(_BIT(3) | _BIT(7))". + */ +#undef _BIT +/* Set bit macro */ +#define _BIT(n) (1<<n) + +/* _SBF(f,v) sets the bit field starting at position "f" to value "v". + * _SBF(f,v) is intended to be used in "OR" and "AND" expressions: + * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)" + */ +#undef _SBF +/* Set bit field macro */ +#define _SBF(f,v) (v<<f) + +/* _BITMASK constructs a symbol with 'field_width' least significant + * bits set. + * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF + * The symbol is intended to be used to limit the bit field width + * thusly: + * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32. + * If "any_expression" results in a value that is larger than can be + * contained in 'x' bits, the bits above 'x - 1' are masked off. When + * used with the _SBF example above, the example would be written: + * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) + * This ensures that the value written to a_reg is no wider than + * 16 bits, and makes the code easier to read and understand. + */ +#undef _BITMASK +/* Bitmask creation macro */ +#define _BITMASK(field_width) ( _BIT(field_width) - 1) + +/* NULL pointer */ +#ifndef NULL +#define NULL ((void*) 0) +#endif + +/* Number of elements in an array */ +#define NELEMENTS(array) (sizeof (array) / sizeof (array[0])) + +/* Static data/function define */ +#define STATIC static +/* External data/function define */ +#define EXTERN extern + +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/** + * @} + */ + + +/* Old Type Definition compatibility ------------------------------------------ */ +/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types + * @{ + */ + +/** SMA type for character type */ +typedef char CHAR; + +/** SMA type for 8 bit unsigned value */ +typedef uint8_t UNS_8; + +/** SMA type for 8 bit signed value */ +typedef int8_t INT_8; + +/** SMA type for 16 bit unsigned value */ +typedef uint16_t UNS_16; + +/** SMA type for 16 bit signed value */ +typedef int16_t INT_16; + +/** SMA type for 32 bit unsigned value */ +typedef uint32_t UNS_32; + +/** SMA type for 32 bit signed value */ +typedef int32_t INT_32; + +/** SMA type for 64 bit signed value */ +typedef int64_t INT_64; + +/** SMA type for 64 bit unsigned value */ +typedef uint64_t UNS_64; + +/** 32 bit boolean type */ +typedef Bool BOOL_32; + +/** 16 bit boolean type */ +typedef Bool BOOL_16; + +/** 8 bit boolean type */ +typedef Bool BOOL_8; + +/** + * @} + */ + + +#endif /* LPC_TYPES_H */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/mbed/builds/e2ac27c8e93e
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/uart_dma_test.c Thu Sep 30 20:13:24 2010 +0000 @@ -0,0 +1,359 @@ +/***********************************************************************//** + * tweaked by dps.lwk to work with mbed's online complier + * 30/09/2010 + **********************************************************************/ + +/***********************************************************************//** + * @file uart_dma_test.c + * @purpose This example describes how to using UART in DMA mode + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + *--------------------------------------------------------------------- + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ +#include "lpc17xx_uart.h" +#include "lpc17xx_libcfg.h" +#include "lpc17xx_gpdma.h" +#include "lpc17xx_pinsel.h" + +/* Example group ----------------------------------------------------------- */ +/** @defgroup UART_DMA DMA + * @ingroup UART_Examples + * @{ + */ + +/************************** PRIVATE DEFINITIONS *************************/ +/* Receive buffer size */ +#define RX_BUF_SIZE 0x80 // ***LWK*** uped buffer to 128bytes + +/************************** PRIVATE VARIABLES *************************/ +uint8_t menu1[] = +"Hello NXP Semiconductors \n\r" +"UART interrupt mode demo using ring buffer \n\r\t " +"MCU LPC17xx - ARM Cortex-M3 \n\r\t " +"UART0 - 9600bps \n\r" +" This is a long string. It transferred in to DMA memory and transmit through Tx line \n\r" +" on UART0 peripheral. To use UART with DMA mode, FIFO function must be enabled \n\r"; + +uint8_t menu3[] = "UART demo terminated!\n"; + +// Receive buffer +__IO uint8_t rx_buf[RX_BUF_SIZE]; + +// Terminal Counter flag for Channel 0 +__IO uint32_t Channel0_TC; + +// Error Counter flag for Channel 0 +__IO uint32_t Channel0_Err; + +// Terminal Counter flag for Channel 1 +__IO uint32_t Channel1_TC; + +// Error Counter flag for Channel 1 +__IO uint32_t Channel1_Err; + + +/************************** PRIVATE FUNCTIONS *************************/ +extern "C" void DMA_IRQHandler (void); // ***LWK*** mbed requires IRQHandeler to be extern "C" + +void print_menu(void); + +/*----------------- INTERRUPT SERVICE ROUTINES --------------------------*/ +/*********************************************************************//** + * @brief GPDMA interrupt handler sub-routine + * @param[in] None + * @return None + **********************************************************************/ +void DMA_IRQHandler (void) +{ + + + uint32_t tmp; + // Scan interrupt pending + for (tmp = 0; tmp <= 7; tmp++) { + if (GPDMA_IntGetStatus(GPDMA_STAT_INT, tmp)){ + // Check counter terminal status + if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, tmp)){ + // Clear terminate counter Interrupt pending + GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, tmp); + + switch (tmp){ + case 0: + Channel0_TC++; + GPDMA_ChannelCmd(0, DISABLE); + break; + case 1: + Channel1_TC++; + GPDMA_ChannelCmd(1, DISABLE); + break; + default: + break; + } + + } + // Check error terminal status + if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, tmp)){ + // Clear error counter Interrupt pending + GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, tmp); + switch (tmp){ + case 0: + Channel0_Err++; + GPDMA_ChannelCmd(0, DISABLE); + break; + case 1: + Channel1_Err++; + GPDMA_ChannelCmd(1, DISABLE); + break; + default: + break; + } + } + } + } +} + +/*-------------------------MAIN FUNCTION------------------------------*/ +/*********************************************************************//** + * @brief c_entry: Main UART program body + * @param[in] None + * @return int + **********************************************************************/ +int c_entry(void) +{ + uint8_t *rx_char; + uint32_t idx; + // UART Configuration structure variable + UART_CFG_Type UARTConfigStruct; + // UART FIFO configuration Struct variable + UART_FIFO_CFG_Type UARTFIFOConfigStruct; + GPDMA_Channel_CFG_Type GPDMACfg; + // Pin configuration for UART0 + PINSEL_CFG_Type PinCfg; + + // ***LWK*** setup pins for debug leds + LPC_GPIO1->FIODIR |= 0xb40000; + LPC_GPIO1->FIOMASK = 0xff4bffff; + + /* + * Initialize UART0 pin connect + */ + PinCfg.Funcnum = 1; + PinCfg.OpenDrain = 0; + PinCfg.Pinmode = 0; + PinCfg.Pinnum = 2; + PinCfg.Portnum = 0; + PINSEL_ConfigPin(&PinCfg); + PinCfg.Pinnum = 3; + PINSEL_ConfigPin(&PinCfg); + + /* Initialize UART Configuration parameter structure to default state: + * Baudrate = 9600bps + * 8 data bit + * 1 Stop bit + * None parity + */ + UART_ConfigStructInit(&UARTConfigStruct); + + // Initialize UART0 peripheral with given to corresponding parameter + UART_Init((LPC_UART_TypeDef *)LPC_UART0, &UARTConfigStruct); + + + /* Initialize FIFOConfigStruct to default state: + * - FIFO_DMAMode = DISABLE + * - FIFO_Level = UART_FIFO_TRGLEV0 + * - FIFO_ResetRxBuf = ENABLE + * - FIFO_ResetTxBuf = ENABLE + * - FIFO_State = ENABLE + */ + UART_FIFOConfigStructInit(&UARTFIFOConfigStruct); + + // Enable DMA mode in UART + UARTFIFOConfigStruct.FIFO_DMAMode = ENABLE; + + // Initialize FIFO for UART0 peripheral + UART_FIFOConfig((LPC_UART_TypeDef *)LPC_UART0, &UARTFIFOConfigStruct); + + // Enable UART Transmit + UART_TxCmd((LPC_UART_TypeDef *)LPC_UART0, ENABLE); + + + /* GPDMA Interrupt configuration section ------------------------------------------------- */ + + /* Initialize GPDMA controller */ + GPDMA_Init(); + + + /* Setting GPDMA interrupt */ + // Disable interrupt for DMA + NVIC_DisableIRQ (DMA_IRQn); + /* preemption = 1, sub-priority = 1 */ + NVIC_SetPriority(DMA_IRQn, ((0x01<<3)|0x01)); + + + // Setup GPDMA channel -------------------------------- + // channel 0 + GPDMACfg.ChannelNum = 0; + // Source memory + GPDMACfg.SrcMemAddr = (uint32_t) &menu1; + // Destination memory - don't care + GPDMACfg.DstMemAddr = 0; + // Transfer size + GPDMACfg.TransferSize = sizeof(menu1); + // Transfer width - don't care + GPDMACfg.TransferWidth = 0; + // Transfer type + GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_M2P; + // Source connection - don't care + GPDMACfg.SrcConn = 0; + // Destination connection + GPDMACfg.DstConn = GPDMA_CONN_UART0_Tx; + // Linker List Item - unused + GPDMACfg.DMALLI = 0; + // Setup channel with given parameter + GPDMA_Setup(&GPDMACfg); + + // Setup GPDMA channel -------------------------------- + // channel 1 + GPDMACfg.ChannelNum = 1; + // Source memory - don't care + GPDMACfg.SrcMemAddr = 0; + // Destination memory + GPDMACfg.DstMemAddr = (uint32_t) &rx_buf; + // Transfer size + GPDMACfg.TransferSize = sizeof(rx_buf); + // Transfer width - don't care + GPDMACfg.TransferWidth = 0; + // Transfer type + GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_P2M; + // Source connection + GPDMACfg.SrcConn = GPDMA_CONN_UART0_Rx; + // Destination connection - don't care + GPDMACfg.DstConn = 0; + // Linker List Item - unused + GPDMACfg.DMALLI = 0; + GPDMA_Setup(&GPDMACfg); + + /* Reset terminal counter */ + Channel0_TC = 0; + /* Reset Error counter */ + Channel0_Err = 0; + + // Enable interrupt for DMA + NVIC_EnableIRQ (DMA_IRQn); + + // ***LWK*** First debug LED1 on + LPC_GPIO1->FIOSET = (1<<18); + + // Enable GPDMA channel 0 + GPDMA_ChannelCmd(0, ENABLE); + // Make sure GPDMA channel 1 is disabled + GPDMA_ChannelCmd(1, DISABLE); + + // ***LWK*** DEBUG LED 2 on + LPC_GPIO1->FIOSET = (1<<20); + + + /* Wait for GPDMA on UART0 Tx processing complete */ + while ((Channel0_TC == 0) && (Channel0_Err == 0)); // ***LWK*** got stuck here!!! untill i found out the IRQHandeler needed extern "C" + + // ***LWK** LED 1 off + LPC_GPIO1->FIOCLR = (1<<18); + + LPC_GPIO1->FIOCLR = (11<<20); + // Main loop - echos back to the terminal + while (1) + { + //***LWK*** debug LED + + LPC_GPIO1->FIOSET = (1<<21); //***LWK*** led 3 in while + + /* Reset terminal counter */ + Channel1_TC = 0; + /* Reset Error counter */ + Channel1_Err = 0; + + // Setup channel with given parameter + GPDMA_Setup(&GPDMACfg); + + // Enable GPDMA channel 1 + GPDMA_ChannelCmd(1, ENABLE); + + // Clear Rx buffer using DMA + for (idx = 0; idx < RX_BUF_SIZE; idx++){ + rx_buf[idx] = 0; + } + + + + // now, start receive character using GPDMA + rx_char = (uint8_t *) &rx_buf; + while ((Channel1_TC == 0) && (Channel1_Err == 0)){ + // Check whether if there's any character received, then print it back + if (*rx_char != 0) + { + UART_Send((LPC_UART_TypeDef *)LPC_UART0, rx_char, 1, BLOCKING); + + //***LWK*** debug LED + // LPC_GPIO1->FIOSET = (1<<21); + rx_char++; + } + } + + //***LWK*** debug LED out of while eithe tc or err + LPC_GPIO1->FIOSET = (1<<23); + + } + + //***LWK*** debug LED + // LPC_GPIO1->FIOSET = (1<<23); + + // DeInitialize UART0 peripheral + UART_DeInit((LPC_UART_TypeDef *)LPC_UART0); + + /* Loop forever */ + while(1); + return 1; +} + +/* With ARM and GHS toolsets, the entry point is main() - this will + allow the linker to generate wrapper code to setup stacks, allocate + heap area, and initialize and copy code and data segments. For GNU + toolsets, the entry point is through __start() in the crt0_gnu.asm + file, and that startup code will setup stacks and data */ +int main(void) +{ + return c_entry(); +} + + +#ifdef DEBUG +/******************************************************************************* +* @brief Reports the name of the source file and the source line number +* where the CHECK_PARAM error has occurred. +* @param[in] file Pointer to the source file name +* @param[in] line assert_param error line source number +* @return None +*******************************************************************************/ +void check_failed(uint8_t *file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while(1); +} +#endif + +/* + * @} + */