Matt Lloyd
Example of UART-DMA transfers taken form the npx cmsis driver libary
lpc17xx_uart.h@0:7480abd3b63b, 2010-09-30 (annotated)
- Committer:
- dpslwk
- Date:
- Thu Sep 30 20:13:24 2010 +0000
- Revision:
- 0:7480abd3b63b
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| dpslwk | 0:7480abd3b63b | 1 | /***********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 2 | * @file lpc17xx_uart.h |
| dpslwk | 0:7480abd3b63b | 3 | * @brief Contains all macro definitions and function prototypes |
| dpslwk | 0:7480abd3b63b | 4 | * support for UART firmware library on LPC17xx |
| dpslwk | 0:7480abd3b63b | 5 | * @version 3.0 |
| dpslwk | 0:7480abd3b63b | 6 | * @date 18. June. 2010 |
| dpslwk | 0:7480abd3b63b | 7 | * @author NXP MCU SW Application Team |
| dpslwk | 0:7480abd3b63b | 8 | ************************************************************************** |
| dpslwk | 0:7480abd3b63b | 9 | * Software that is described herein is for illustrative purposes only |
| dpslwk | 0:7480abd3b63b | 10 | * which provides customers with programming information regarding the |
| dpslwk | 0:7480abd3b63b | 11 | * products. This software is supplied "AS IS" without any warranties. |
| dpslwk | 0:7480abd3b63b | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| dpslwk | 0:7480abd3b63b | 13 | * use of the software, conveys no license or title under any patent, |
| dpslwk | 0:7480abd3b63b | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| dpslwk | 0:7480abd3b63b | 15 | * reserves the right to make changes in the software without |
| dpslwk | 0:7480abd3b63b | 16 | * notification. NXP Semiconductors also make no representation or |
| dpslwk | 0:7480abd3b63b | 17 | * warranty that such application will be suitable for the specified |
| dpslwk | 0:7480abd3b63b | 18 | * use without further testing or modification. |
| dpslwk | 0:7480abd3b63b | 19 | **************************************************************************/ |
| dpslwk | 0:7480abd3b63b | 20 | |
| dpslwk | 0:7480abd3b63b | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| dpslwk | 0:7480abd3b63b | 22 | /** @defgroup UART UART |
| dpslwk | 0:7480abd3b63b | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| dpslwk | 0:7480abd3b63b | 24 | * @{ |
| dpslwk | 0:7480abd3b63b | 25 | */ |
| dpslwk | 0:7480abd3b63b | 26 | |
| dpslwk | 0:7480abd3b63b | 27 | #ifndef __LPC17XX_UART_H |
| dpslwk | 0:7480abd3b63b | 28 | #define __LPC17XX_UART_H |
| dpslwk | 0:7480abd3b63b | 29 | |
| dpslwk | 0:7480abd3b63b | 30 | /* Includes ------------------------------------------------------------------- */ |
| dpslwk | 0:7480abd3b63b | 31 | #include "LPC17xx.h" |
| dpslwk | 0:7480abd3b63b | 32 | #include "lpc_types.h" |
| dpslwk | 0:7480abd3b63b | 33 | |
| dpslwk | 0:7480abd3b63b | 34 | |
| dpslwk | 0:7480abd3b63b | 35 | #ifdef __cplusplus |
| dpslwk | 0:7480abd3b63b | 36 | extern "C" |
| dpslwk | 0:7480abd3b63b | 37 | { |
| dpslwk | 0:7480abd3b63b | 38 | #endif |
| dpslwk | 0:7480abd3b63b | 39 | |
| dpslwk | 0:7480abd3b63b | 40 | /* Public Macros -------------------------------------------------------------- */ |
| dpslwk | 0:7480abd3b63b | 41 | /** @defgroup UART_Public_Macros UART Public Macros |
| dpslwk | 0:7480abd3b63b | 42 | * @{ |
| dpslwk | 0:7480abd3b63b | 43 | */ |
| dpslwk | 0:7480abd3b63b | 44 | |
| dpslwk | 0:7480abd3b63b | 45 | /** UART time-out definitions in case of using Read() and Write function |
| dpslwk | 0:7480abd3b63b | 46 | * with Blocking Flag mode |
| dpslwk | 0:7480abd3b63b | 47 | */ |
| dpslwk | 0:7480abd3b63b | 48 | #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) |
| dpslwk | 0:7480abd3b63b | 49 | |
| dpslwk | 0:7480abd3b63b | 50 | /** |
| dpslwk | 0:7480abd3b63b | 51 | * @} |
| dpslwk | 0:7480abd3b63b | 52 | */ |
| dpslwk | 0:7480abd3b63b | 53 | |
| dpslwk | 0:7480abd3b63b | 54 | /* Private Macros ------------------------------------------------------------- */ |
| dpslwk | 0:7480abd3b63b | 55 | /** @defgroup UART_Private_Macros UART Private Macros |
| dpslwk | 0:7480abd3b63b | 56 | * @{ |
| dpslwk | 0:7480abd3b63b | 57 | */ |
| dpslwk | 0:7480abd3b63b | 58 | |
| dpslwk | 0:7480abd3b63b | 59 | /* Accepted Error baud rate value (in percent unit) */ |
| dpslwk | 0:7480abd3b63b | 60 | #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ |
| dpslwk | 0:7480abd3b63b | 61 | |
| dpslwk | 0:7480abd3b63b | 62 | |
| dpslwk | 0:7480abd3b63b | 63 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| dpslwk | 0:7480abd3b63b | 64 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 65 | * Macro defines for Macro defines for UARTn Receiver Buffer Register |
| dpslwk | 0:7480abd3b63b | 66 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 67 | #define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */ |
| dpslwk | 0:7480abd3b63b | 68 | |
| dpslwk | 0:7480abd3b63b | 69 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 70 | * Macro defines for Macro defines for UARTn Transmit Holding Register |
| dpslwk | 0:7480abd3b63b | 71 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 72 | #define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */ |
| dpslwk | 0:7480abd3b63b | 73 | |
| dpslwk | 0:7480abd3b63b | 74 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 75 | * Macro defines for Macro defines for UARTn Divisor Latch LSB register |
| dpslwk | 0:7480abd3b63b | 76 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 77 | #define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */ |
| dpslwk | 0:7480abd3b63b | 78 | #define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */ |
| dpslwk | 0:7480abd3b63b | 79 | |
| dpslwk | 0:7480abd3b63b | 80 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 81 | * Macro defines for Macro defines for UARTn Divisor Latch MSB register |
| dpslwk | 0:7480abd3b63b | 82 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 83 | #define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */ |
| dpslwk | 0:7480abd3b63b | 84 | #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */ |
| dpslwk | 0:7480abd3b63b | 85 | |
| dpslwk | 0:7480abd3b63b | 86 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 87 | * Macro defines for Macro defines for UART interrupt enable register |
| dpslwk | 0:7480abd3b63b | 88 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 89 | #define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/ |
| dpslwk | 0:7480abd3b63b | 90 | #define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/ |
| dpslwk | 0:7480abd3b63b | 91 | #define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/ |
| dpslwk | 0:7480abd3b63b | 92 | #define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */ |
| dpslwk | 0:7480abd3b63b | 93 | #define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */ |
| dpslwk | 0:7480abd3b63b | 94 | #define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */ |
| dpslwk | 0:7480abd3b63b | 95 | #define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */ |
| dpslwk | 0:7480abd3b63b | 96 | #define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */ |
| dpslwk | 0:7480abd3b63b | 97 | #define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */ |
| dpslwk | 0:7480abd3b63b | 98 | |
| dpslwk | 0:7480abd3b63b | 99 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 100 | * Macro defines for Macro defines for UART interrupt identification register |
| dpslwk | 0:7480abd3b63b | 101 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 102 | #define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */ |
| dpslwk | 0:7480abd3b63b | 103 | #define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/ |
| dpslwk | 0:7480abd3b63b | 104 | #define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/ |
| dpslwk | 0:7480abd3b63b | 105 | #define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/ |
| dpslwk | 0:7480abd3b63b | 106 | #define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/ |
| dpslwk | 0:7480abd3b63b | 107 | #define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/ |
| dpslwk | 0:7480abd3b63b | 108 | #define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */ |
| dpslwk | 0:7480abd3b63b | 109 | #define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */ |
| dpslwk | 0:7480abd3b63b | 110 | #define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */ |
| dpslwk | 0:7480abd3b63b | 111 | #define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */ |
| dpslwk | 0:7480abd3b63b | 112 | #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */ |
| dpslwk | 0:7480abd3b63b | 113 | |
| dpslwk | 0:7480abd3b63b | 114 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 115 | * Macro defines for Macro defines for UART FIFO control register |
| dpslwk | 0:7480abd3b63b | 116 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 117 | #define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */ |
| dpslwk | 0:7480abd3b63b | 118 | #define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */ |
| dpslwk | 0:7480abd3b63b | 119 | #define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */ |
| dpslwk | 0:7480abd3b63b | 120 | #define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */ |
| dpslwk | 0:7480abd3b63b | 121 | #define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */ |
| dpslwk | 0:7480abd3b63b | 122 | #define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */ |
| dpslwk | 0:7480abd3b63b | 123 | #define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */ |
| dpslwk | 0:7480abd3b63b | 124 | #define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */ |
| dpslwk | 0:7480abd3b63b | 125 | #define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */ |
| dpslwk | 0:7480abd3b63b | 126 | #define UART_TX_FIFO_SIZE (16) |
| dpslwk | 0:7480abd3b63b | 127 | |
| dpslwk | 0:7480abd3b63b | 128 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 129 | * Macro defines for Macro defines for UART line control register |
| dpslwk | 0:7480abd3b63b | 130 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 131 | #define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 132 | #define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 133 | #define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 134 | #define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 135 | #define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */ |
| dpslwk | 0:7480abd3b63b | 136 | #define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */ |
| dpslwk | 0:7480abd3b63b | 137 | #define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */ |
| dpslwk | 0:7480abd3b63b | 138 | #define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */ |
| dpslwk | 0:7480abd3b63b | 139 | #define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */ |
| dpslwk | 0:7480abd3b63b | 140 | #define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */ |
| dpslwk | 0:7480abd3b63b | 141 | #define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */ |
| dpslwk | 0:7480abd3b63b | 142 | #define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */ |
| dpslwk | 0:7480abd3b63b | 143 | #define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */ |
| dpslwk | 0:7480abd3b63b | 144 | |
| dpslwk | 0:7480abd3b63b | 145 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 146 | * Macro defines for Macro defines for UART1 Modem Control Register |
| dpslwk | 0:7480abd3b63b | 147 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 148 | #define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */ |
| dpslwk | 0:7480abd3b63b | 149 | #define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */ |
| dpslwk | 0:7480abd3b63b | 150 | #define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */ |
| dpslwk | 0:7480abd3b63b | 151 | #define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */ |
| dpslwk | 0:7480abd3b63b | 152 | #define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */ |
| dpslwk | 0:7480abd3b63b | 153 | #define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */ |
| dpslwk | 0:7480abd3b63b | 154 | |
| dpslwk | 0:7480abd3b63b | 155 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 156 | * Macro defines for Macro defines for UART line status register |
| dpslwk | 0:7480abd3b63b | 157 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 158 | #define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/ |
| dpslwk | 0:7480abd3b63b | 159 | #define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/ |
| dpslwk | 0:7480abd3b63b | 160 | #define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/ |
| dpslwk | 0:7480abd3b63b | 161 | #define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/ |
| dpslwk | 0:7480abd3b63b | 162 | #define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/ |
| dpslwk | 0:7480abd3b63b | 163 | #define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/ |
| dpslwk | 0:7480abd3b63b | 164 | #define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/ |
| dpslwk | 0:7480abd3b63b | 165 | #define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/ |
| dpslwk | 0:7480abd3b63b | 166 | #define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */ |
| dpslwk | 0:7480abd3b63b | 167 | |
| dpslwk | 0:7480abd3b63b | 168 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 169 | * Macro defines for Macro defines for UART Modem (UART1 only) status register |
| dpslwk | 0:7480abd3b63b | 170 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 171 | #define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */ |
| dpslwk | 0:7480abd3b63b | 172 | #define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */ |
| dpslwk | 0:7480abd3b63b | 173 | #define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */ |
| dpslwk | 0:7480abd3b63b | 174 | #define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */ |
| dpslwk | 0:7480abd3b63b | 175 | #define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */ |
| dpslwk | 0:7480abd3b63b | 176 | #define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */ |
| dpslwk | 0:7480abd3b63b | 177 | #define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */ |
| dpslwk | 0:7480abd3b63b | 178 | #define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */ |
| dpslwk | 0:7480abd3b63b | 179 | #define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */ |
| dpslwk | 0:7480abd3b63b | 180 | |
| dpslwk | 0:7480abd3b63b | 181 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 182 | * Macro defines for Macro defines for UART Scratch Pad Register |
| dpslwk | 0:7480abd3b63b | 183 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 184 | #define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */ |
| dpslwk | 0:7480abd3b63b | 185 | |
| dpslwk | 0:7480abd3b63b | 186 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 187 | * Macro defines for Macro defines for UART Auto baudrate control register |
| dpslwk | 0:7480abd3b63b | 188 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 189 | #define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */ |
| dpslwk | 0:7480abd3b63b | 190 | #define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */ |
| dpslwk | 0:7480abd3b63b | 191 | #define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */ |
| dpslwk | 0:7480abd3b63b | 192 | #define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */ |
| dpslwk | 0:7480abd3b63b | 193 | #define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */ |
| dpslwk | 0:7480abd3b63b | 194 | #define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */ |
| dpslwk | 0:7480abd3b63b | 195 | |
| dpslwk | 0:7480abd3b63b | 196 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 197 | * Macro defines for Macro defines for UART IrDA control register |
| dpslwk | 0:7480abd3b63b | 198 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 199 | #define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */ |
| dpslwk | 0:7480abd3b63b | 200 | #define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */ |
| dpslwk | 0:7480abd3b63b | 201 | #define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */ |
| dpslwk | 0:7480abd3b63b | 202 | #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 203 | #define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */ |
| dpslwk | 0:7480abd3b63b | 204 | |
| dpslwk | 0:7480abd3b63b | 205 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 206 | * Macro defines for Macro defines for UART Fractional divider register |
| dpslwk | 0:7480abd3b63b | 207 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 208 | #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */ |
| dpslwk | 0:7480abd3b63b | 209 | #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */ |
| dpslwk | 0:7480abd3b63b | 210 | #define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */ |
| dpslwk | 0:7480abd3b63b | 211 | |
| dpslwk | 0:7480abd3b63b | 212 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 213 | * Macro defines for Macro defines for UART Tx Enable register |
| dpslwk | 0:7480abd3b63b | 214 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 215 | #define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */ |
| dpslwk | 0:7480abd3b63b | 216 | #define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */ |
| dpslwk | 0:7480abd3b63b | 217 | |
| dpslwk | 0:7480abd3b63b | 218 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 219 | * Macro defines for Macro defines for UART1 RS485 Control register |
| dpslwk | 0:7480abd3b63b | 220 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 221 | #define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) |
| dpslwk | 0:7480abd3b63b | 222 | is disabled */ |
| dpslwk | 0:7480abd3b63b | 223 | #define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */ |
| dpslwk | 0:7480abd3b63b | 224 | #define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */ |
| dpslwk | 0:7480abd3b63b | 225 | #define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled |
| dpslwk | 0:7480abd3b63b | 226 | (bit DCTRL = 1), pin DTR is used for direction control */ |
| dpslwk | 0:7480abd3b63b | 227 | #define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */ |
| dpslwk | 0:7480abd3b63b | 228 | #define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction |
| dpslwk | 0:7480abd3b63b | 229 | control signal on the RTS (or DTR) pin. The direction control pin |
| dpslwk | 0:7480abd3b63b | 230 | will be driven to logic "1" when the transmitter has data to be sent */ |
| dpslwk | 0:7480abd3b63b | 231 | #define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */ |
| dpslwk | 0:7480abd3b63b | 232 | |
| dpslwk | 0:7480abd3b63b | 233 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 234 | * Macro defines for Macro defines for UART1 RS-485 Address Match register |
| dpslwk | 0:7480abd3b63b | 235 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 236 | #define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ |
| dpslwk | 0:7480abd3b63b | 237 | |
| dpslwk | 0:7480abd3b63b | 238 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 239 | * Macro defines for Macro defines for UART1 RS-485 Delay value register |
| dpslwk | 0:7480abd3b63b | 240 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 241 | /* Macro defines for UART1 RS-485 Delay value register */ |
| dpslwk | 0:7480abd3b63b | 242 | #define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ |
| dpslwk | 0:7480abd3b63b | 243 | |
| dpslwk | 0:7480abd3b63b | 244 | /*********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 245 | * Macro defines for Macro defines for UART FIFO Level register |
| dpslwk | 0:7480abd3b63b | 246 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 247 | #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */ |
| dpslwk | 0:7480abd3b63b | 248 | #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */ |
| dpslwk | 0:7480abd3b63b | 249 | #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */ |
| dpslwk | 0:7480abd3b63b | 250 | |
| dpslwk | 0:7480abd3b63b | 251 | |
| dpslwk | 0:7480abd3b63b | 252 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
| dpslwk | 0:7480abd3b63b | 253 | |
| dpslwk | 0:7480abd3b63b | 254 | /** Macro to check the input UART_DATABIT parameters */ |
| dpslwk | 0:7480abd3b63b | 255 | #define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\ |
| dpslwk | 0:7480abd3b63b | 256 | || (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8)) |
| dpslwk | 0:7480abd3b63b | 257 | |
| dpslwk | 0:7480abd3b63b | 258 | /** Macro to check the input UART_STOPBIT parameters */ |
| dpslwk | 0:7480abd3b63b | 259 | #define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2)) |
| dpslwk | 0:7480abd3b63b | 260 | |
| dpslwk | 0:7480abd3b63b | 261 | /** Macro to check the input UART_PARITY parameters */ |
| dpslwk | 0:7480abd3b63b | 262 | #define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \ |
| dpslwk | 0:7480abd3b63b | 263 | || (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \ |
| dpslwk | 0:7480abd3b63b | 264 | || (parity==UART_PARITY_SP_0)) |
| dpslwk | 0:7480abd3b63b | 265 | |
| dpslwk | 0:7480abd3b63b | 266 | /** Macro to check the input UART_FIFO parameters */ |
| dpslwk | 0:7480abd3b63b | 267 | #define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \ |
| dpslwk | 0:7480abd3b63b | 268 | || (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \ |
| dpslwk | 0:7480abd3b63b | 269 | || (fifo==UART_FIFO_TRGLEV3)) |
| dpslwk | 0:7480abd3b63b | 270 | |
| dpslwk | 0:7480abd3b63b | 271 | /** Macro to check the input UART_INTCFG parameters */ |
| dpslwk | 0:7480abd3b63b | 272 | #define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \ |
| dpslwk | 0:7480abd3b63b | 273 | || (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \ |
| dpslwk | 0:7480abd3b63b | 274 | || (IntCfg==UART_INTCFG_ABTO)) |
| dpslwk | 0:7480abd3b63b | 275 | |
| dpslwk | 0:7480abd3b63b | 276 | /** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */ |
| dpslwk | 0:7480abd3b63b | 277 | #define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS)) |
| dpslwk | 0:7480abd3b63b | 278 | |
| dpslwk | 0:7480abd3b63b | 279 | /** Macro to check the input UART_AUTOBAUD_MODE parameters */ |
| dpslwk | 0:7480abd3b63b | 280 | #define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1)) |
| dpslwk | 0:7480abd3b63b | 281 | |
| dpslwk | 0:7480abd3b63b | 282 | /** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */ |
| dpslwk | 0:7480abd3b63b | 283 | #define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \ |
| dpslwk | 0:7480abd3b63b | 284 | (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO)) |
| dpslwk | 0:7480abd3b63b | 285 | |
| dpslwk | 0:7480abd3b63b | 286 | /** Macro to check the input UART_IrDA_PULSEDIV parameters */ |
| dpslwk | 0:7480abd3b63b | 287 | #define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \ |
| dpslwk | 0:7480abd3b63b | 288 | || (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \ |
| dpslwk | 0:7480abd3b63b | 289 | || (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \ |
| dpslwk | 0:7480abd3b63b | 290 | || (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256)) |
| dpslwk | 0:7480abd3b63b | 291 | |
| dpslwk | 0:7480abd3b63b | 292 | /* Macro to check the input UART1_SignalState parameters */ |
| dpslwk | 0:7480abd3b63b | 293 | #define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE)) |
| dpslwk | 0:7480abd3b63b | 294 | |
| dpslwk | 0:7480abd3b63b | 295 | /** Macro to check the input PARAM_UART1_MODEM_PIN parameters */ |
| dpslwk | 0:7480abd3b63b | 296 | #define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS)) |
| dpslwk | 0:7480abd3b63b | 297 | |
| dpslwk | 0:7480abd3b63b | 298 | /** Macro to check the input PARAM_UART1_MODEM_MODE parameters */ |
| dpslwk | 0:7480abd3b63b | 299 | #define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \ |
| dpslwk | 0:7480abd3b63b | 300 | || (x==UART1_MODEM_MODE_AUTO_CTS)) |
| dpslwk | 0:7480abd3b63b | 301 | |
| dpslwk | 0:7480abd3b63b | 302 | /** Macro to check the direction control pin type */ |
| dpslwk | 0:7480abd3b63b | 303 | #define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR)) |
| dpslwk | 0:7480abd3b63b | 304 | |
| dpslwk | 0:7480abd3b63b | 305 | /* Macro to determine if it is valid UART port number */ |
| dpslwk | 0:7480abd3b63b | 306 | #define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \ |
| dpslwk | 0:7480abd3b63b | 307 | || (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \ |
| dpslwk | 0:7480abd3b63b | 308 | || (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \ |
| dpslwk | 0:7480abd3b63b | 309 | || (((uint32_t *)x)==((uint32_t *)LPC_UART3))) |
| dpslwk | 0:7480abd3b63b | 310 | #define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3)) |
| dpslwk | 0:7480abd3b63b | 311 | #define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1)) |
| dpslwk | 0:7480abd3b63b | 312 | |
| dpslwk | 0:7480abd3b63b | 313 | /** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */ |
| dpslwk | 0:7480abd3b63b | 314 | #define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF)) |
| dpslwk | 0:7480abd3b63b | 315 | |
| dpslwk | 0:7480abd3b63b | 316 | /** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */ |
| dpslwk | 0:7480abd3b63b | 317 | #define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF)) |
| dpslwk | 0:7480abd3b63b | 318 | |
| dpslwk | 0:7480abd3b63b | 319 | /** |
| dpslwk | 0:7480abd3b63b | 320 | * @} |
| dpslwk | 0:7480abd3b63b | 321 | */ |
| dpslwk | 0:7480abd3b63b | 322 | |
| dpslwk | 0:7480abd3b63b | 323 | |
| dpslwk | 0:7480abd3b63b | 324 | /* Public Types --------------------------------------------------------------- */ |
| dpslwk | 0:7480abd3b63b | 325 | /** @defgroup UART_Public_Types UART Public Types |
| dpslwk | 0:7480abd3b63b | 326 | * @{ |
| dpslwk | 0:7480abd3b63b | 327 | */ |
| dpslwk | 0:7480abd3b63b | 328 | |
| dpslwk | 0:7480abd3b63b | 329 | /** |
| dpslwk | 0:7480abd3b63b | 330 | * @brief UART Databit type definitions |
| dpslwk | 0:7480abd3b63b | 331 | */ |
| dpslwk | 0:7480abd3b63b | 332 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 333 | UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 334 | UART_DATABIT_6, /*!< UART 6 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 335 | UART_DATABIT_7, /*!< UART 7 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 336 | UART_DATABIT_8 /*!< UART 8 bit data mode */ |
| dpslwk | 0:7480abd3b63b | 337 | } UART_DATABIT_Type; |
| dpslwk | 0:7480abd3b63b | 338 | |
| dpslwk | 0:7480abd3b63b | 339 | /** |
| dpslwk | 0:7480abd3b63b | 340 | * @brief UART Stop bit type definitions |
| dpslwk | 0:7480abd3b63b | 341 | */ |
| dpslwk | 0:7480abd3b63b | 342 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 343 | UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ |
| dpslwk | 0:7480abd3b63b | 344 | UART_STOPBIT_2, /*!< UART Two Stop Bits Select */ |
| dpslwk | 0:7480abd3b63b | 345 | } UART_STOPBIT_Type; |
| dpslwk | 0:7480abd3b63b | 346 | |
| dpslwk | 0:7480abd3b63b | 347 | /** |
| dpslwk | 0:7480abd3b63b | 348 | * @brief UART Parity type definitions |
| dpslwk | 0:7480abd3b63b | 349 | */ |
| dpslwk | 0:7480abd3b63b | 350 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 351 | UART_PARITY_NONE = 0, /*!< No parity */ |
| dpslwk | 0:7480abd3b63b | 352 | UART_PARITY_ODD, /*!< Odd parity */ |
| dpslwk | 0:7480abd3b63b | 353 | UART_PARITY_EVEN, /*!< Even parity */ |
| dpslwk | 0:7480abd3b63b | 354 | UART_PARITY_SP_1, /*!< Forced "1" stick parity */ |
| dpslwk | 0:7480abd3b63b | 355 | UART_PARITY_SP_0 /*!< Forced "0" stick parity */ |
| dpslwk | 0:7480abd3b63b | 356 | } UART_PARITY_Type; |
| dpslwk | 0:7480abd3b63b | 357 | |
| dpslwk | 0:7480abd3b63b | 358 | /** |
| dpslwk | 0:7480abd3b63b | 359 | * @brief FIFO Level type definitions |
| dpslwk | 0:7480abd3b63b | 360 | */ |
| dpslwk | 0:7480abd3b63b | 361 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 362 | UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ |
| dpslwk | 0:7480abd3b63b | 363 | UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ |
| dpslwk | 0:7480abd3b63b | 364 | UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ |
| dpslwk | 0:7480abd3b63b | 365 | UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ |
| dpslwk | 0:7480abd3b63b | 366 | } UART_FITO_LEVEL_Type; |
| dpslwk | 0:7480abd3b63b | 367 | |
| dpslwk | 0:7480abd3b63b | 368 | /********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 369 | * @brief UART Interrupt Type definitions |
| dpslwk | 0:7480abd3b63b | 370 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 371 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 372 | UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ |
| dpslwk | 0:7480abd3b63b | 373 | UART_INTCFG_THRE, /*!< THR Interrupt enable*/ |
| dpslwk | 0:7480abd3b63b | 374 | UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ |
| dpslwk | 0:7480abd3b63b | 375 | UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ |
| dpslwk | 0:7480abd3b63b | 376 | UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ |
| dpslwk | 0:7480abd3b63b | 377 | UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ |
| dpslwk | 0:7480abd3b63b | 378 | UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ |
| dpslwk | 0:7480abd3b63b | 379 | } UART_INT_Type; |
| dpslwk | 0:7480abd3b63b | 380 | |
| dpslwk | 0:7480abd3b63b | 381 | /** |
| dpslwk | 0:7480abd3b63b | 382 | * @brief UART Line Status Type definition |
| dpslwk | 0:7480abd3b63b | 383 | */ |
| dpslwk | 0:7480abd3b63b | 384 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 385 | UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/ |
| dpslwk | 0:7480abd3b63b | 386 | UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/ |
| dpslwk | 0:7480abd3b63b | 387 | UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/ |
| dpslwk | 0:7480abd3b63b | 388 | UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/ |
| dpslwk | 0:7480abd3b63b | 389 | UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/ |
| dpslwk | 0:7480abd3b63b | 390 | UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/ |
| dpslwk | 0:7480abd3b63b | 391 | UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/ |
| dpslwk | 0:7480abd3b63b | 392 | UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/ |
| dpslwk | 0:7480abd3b63b | 393 | } UART_LS_Type; |
| dpslwk | 0:7480abd3b63b | 394 | |
| dpslwk | 0:7480abd3b63b | 395 | /** |
| dpslwk | 0:7480abd3b63b | 396 | * @brief UART Auto-baudrate mode type definition |
| dpslwk | 0:7480abd3b63b | 397 | */ |
| dpslwk | 0:7480abd3b63b | 398 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 399 | UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */ |
| dpslwk | 0:7480abd3b63b | 400 | UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */ |
| dpslwk | 0:7480abd3b63b | 401 | } UART_AB_MODE_Type; |
| dpslwk | 0:7480abd3b63b | 402 | |
| dpslwk | 0:7480abd3b63b | 403 | /** |
| dpslwk | 0:7480abd3b63b | 404 | * @brief Auto Baudrate mode configuration type definition |
| dpslwk | 0:7480abd3b63b | 405 | */ |
| dpslwk | 0:7480abd3b63b | 406 | typedef struct { |
| dpslwk | 0:7480abd3b63b | 407 | UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */ |
| dpslwk | 0:7480abd3b63b | 408 | FunctionalState AutoRestart; /**< Auto Restart state */ |
| dpslwk | 0:7480abd3b63b | 409 | } UART_AB_CFG_Type; |
| dpslwk | 0:7480abd3b63b | 410 | |
| dpslwk | 0:7480abd3b63b | 411 | /** |
| dpslwk | 0:7480abd3b63b | 412 | * @brief UART End of Auto-baudrate type definition |
| dpslwk | 0:7480abd3b63b | 413 | */ |
| dpslwk | 0:7480abd3b63b | 414 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 415 | UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */ |
| dpslwk | 0:7480abd3b63b | 416 | UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */ |
| dpslwk | 0:7480abd3b63b | 417 | }UART_ABEO_Type; |
| dpslwk | 0:7480abd3b63b | 418 | |
| dpslwk | 0:7480abd3b63b | 419 | /** |
| dpslwk | 0:7480abd3b63b | 420 | * UART IrDA Control type Definition |
| dpslwk | 0:7480abd3b63b | 421 | */ |
| dpslwk | 0:7480abd3b63b | 422 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 423 | UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk |
| dpslwk | 0:7480abd3b63b | 424 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 425 | UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk |
| dpslwk | 0:7480abd3b63b | 426 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 427 | UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk |
| dpslwk | 0:7480abd3b63b | 428 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 429 | UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk |
| dpslwk | 0:7480abd3b63b | 430 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 431 | UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk |
| dpslwk | 0:7480abd3b63b | 432 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 433 | UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk |
| dpslwk | 0:7480abd3b63b | 434 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 435 | UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk |
| dpslwk | 0:7480abd3b63b | 436 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 437 | UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk |
| dpslwk | 0:7480abd3b63b | 438 | - Configures the pulse when FixPulseEn = 1 */ |
| dpslwk | 0:7480abd3b63b | 439 | } UART_IrDA_PULSE_Type; |
| dpslwk | 0:7480abd3b63b | 440 | |
| dpslwk | 0:7480abd3b63b | 441 | /********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 442 | * @brief UART1 Full modem - Signal states definition |
| dpslwk | 0:7480abd3b63b | 443 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 444 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 445 | INACTIVE = 0, /* In-active state */ |
| dpslwk | 0:7480abd3b63b | 446 | ACTIVE = !INACTIVE /* Active state */ |
| dpslwk | 0:7480abd3b63b | 447 | }UART1_SignalState; |
| dpslwk | 0:7480abd3b63b | 448 | |
| dpslwk | 0:7480abd3b63b | 449 | /** |
| dpslwk | 0:7480abd3b63b | 450 | * @brief UART modem status type definition |
| dpslwk | 0:7480abd3b63b | 451 | */ |
| dpslwk | 0:7480abd3b63b | 452 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 453 | UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */ |
| dpslwk | 0:7480abd3b63b | 454 | UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */ |
| dpslwk | 0:7480abd3b63b | 455 | UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */ |
| dpslwk | 0:7480abd3b63b | 456 | UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */ |
| dpslwk | 0:7480abd3b63b | 457 | UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */ |
| dpslwk | 0:7480abd3b63b | 458 | UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */ |
| dpslwk | 0:7480abd3b63b | 459 | UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */ |
| dpslwk | 0:7480abd3b63b | 460 | UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */ |
| dpslwk | 0:7480abd3b63b | 461 | } UART_MODEM_STAT_type; |
| dpslwk | 0:7480abd3b63b | 462 | |
| dpslwk | 0:7480abd3b63b | 463 | /** |
| dpslwk | 0:7480abd3b63b | 464 | * @brief Modem output pin type definition |
| dpslwk | 0:7480abd3b63b | 465 | */ |
| dpslwk | 0:7480abd3b63b | 466 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 467 | UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */ |
| dpslwk | 0:7480abd3b63b | 468 | UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */ |
| dpslwk | 0:7480abd3b63b | 469 | } UART_MODEM_PIN_Type; |
| dpslwk | 0:7480abd3b63b | 470 | |
| dpslwk | 0:7480abd3b63b | 471 | /** |
| dpslwk | 0:7480abd3b63b | 472 | * @brief UART Modem mode type definition |
| dpslwk | 0:7480abd3b63b | 473 | */ |
| dpslwk | 0:7480abd3b63b | 474 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 475 | UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */ |
| dpslwk | 0:7480abd3b63b | 476 | UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */ |
| dpslwk | 0:7480abd3b63b | 477 | UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */ |
| dpslwk | 0:7480abd3b63b | 478 | } UART_MODEM_MODE_Type; |
| dpslwk | 0:7480abd3b63b | 479 | |
| dpslwk | 0:7480abd3b63b | 480 | /** |
| dpslwk | 0:7480abd3b63b | 481 | * @brief UART Direction Control Pin type definition |
| dpslwk | 0:7480abd3b63b | 482 | */ |
| dpslwk | 0:7480abd3b63b | 483 | typedef enum { |
| dpslwk | 0:7480abd3b63b | 484 | UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */ |
| dpslwk | 0:7480abd3b63b | 485 | UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */ |
| dpslwk | 0:7480abd3b63b | 486 | } UART_RS485_DIRCTRL_PIN_Type; |
| dpslwk | 0:7480abd3b63b | 487 | |
| dpslwk | 0:7480abd3b63b | 488 | /********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 489 | * @brief UART Configuration Structure definition |
| dpslwk | 0:7480abd3b63b | 490 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 491 | typedef struct { |
| dpslwk | 0:7480abd3b63b | 492 | uint32_t Baud_rate; /**< UART baud rate */ |
| dpslwk | 0:7480abd3b63b | 493 | UART_PARITY_Type Parity; /**< Parity selection, should be: |
| dpslwk | 0:7480abd3b63b | 494 | - UART_PARITY_NONE: No parity |
| dpslwk | 0:7480abd3b63b | 495 | - UART_PARITY_ODD: Odd parity |
| dpslwk | 0:7480abd3b63b | 496 | - UART_PARITY_EVEN: Even parity |
| dpslwk | 0:7480abd3b63b | 497 | - UART_PARITY_SP_1: Forced "1" stick parity |
| dpslwk | 0:7480abd3b63b | 498 | - UART_PARITY_SP_0: Forced "0" stick parity |
| dpslwk | 0:7480abd3b63b | 499 | */ |
| dpslwk | 0:7480abd3b63b | 500 | UART_DATABIT_Type Databits; /**< Number of data bits, should be: |
| dpslwk | 0:7480abd3b63b | 501 | - UART_DATABIT_5: UART 5 bit data mode |
| dpslwk | 0:7480abd3b63b | 502 | - UART_DATABIT_6: UART 6 bit data mode |
| dpslwk | 0:7480abd3b63b | 503 | - UART_DATABIT_7: UART 7 bit data mode |
| dpslwk | 0:7480abd3b63b | 504 | - UART_DATABIT_8: UART 8 bit data mode |
| dpslwk | 0:7480abd3b63b | 505 | */ |
| dpslwk | 0:7480abd3b63b | 506 | UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be: |
| dpslwk | 0:7480abd3b63b | 507 | - UART_STOPBIT_1: UART 1 Stop Bits Select |
| dpslwk | 0:7480abd3b63b | 508 | - UART_STOPBIT_2: UART 2 Stop Bits Select |
| dpslwk | 0:7480abd3b63b | 509 | */ |
| dpslwk | 0:7480abd3b63b | 510 | } UART_CFG_Type; |
| dpslwk | 0:7480abd3b63b | 511 | |
| dpslwk | 0:7480abd3b63b | 512 | /********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 513 | * @brief UART FIFO Configuration Structure definition |
| dpslwk | 0:7480abd3b63b | 514 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 515 | |
| dpslwk | 0:7480abd3b63b | 516 | typedef struct { |
| dpslwk | 0:7480abd3b63b | 517 | FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be: |
| dpslwk | 0:7480abd3b63b | 518 | - ENABLE: Reset Rx FIFO in UART |
| dpslwk | 0:7480abd3b63b | 519 | - DISABLE: Do not reset Rx FIFO in UART |
| dpslwk | 0:7480abd3b63b | 520 | */ |
| dpslwk | 0:7480abd3b63b | 521 | FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be: |
| dpslwk | 0:7480abd3b63b | 522 | - ENABLE: Reset Tx FIFO in UART |
| dpslwk | 0:7480abd3b63b | 523 | - DISABLE: Do not reset Tx FIFO in UART |
| dpslwk | 0:7480abd3b63b | 524 | */ |
| dpslwk | 0:7480abd3b63b | 525 | FunctionalState FIFO_DMAMode; /**< DMA mode, should be: |
| dpslwk | 0:7480abd3b63b | 526 | - ENABLE: Enable DMA mode in UART |
| dpslwk | 0:7480abd3b63b | 527 | - DISABLE: Disable DMA mode in UART |
| dpslwk | 0:7480abd3b63b | 528 | */ |
| dpslwk | 0:7480abd3b63b | 529 | UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be: |
| dpslwk | 0:7480abd3b63b | 530 | - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character |
| dpslwk | 0:7480abd3b63b | 531 | - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character |
| dpslwk | 0:7480abd3b63b | 532 | - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character |
| dpslwk | 0:7480abd3b63b | 533 | - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character |
| dpslwk | 0:7480abd3b63b | 534 | */ |
| dpslwk | 0:7480abd3b63b | 535 | } UART_FIFO_CFG_Type; |
| dpslwk | 0:7480abd3b63b | 536 | |
| dpslwk | 0:7480abd3b63b | 537 | /********************************************************************//** |
| dpslwk | 0:7480abd3b63b | 538 | * @brief UART1 Full modem - RS485 Control configuration type |
| dpslwk | 0:7480abd3b63b | 539 | **********************************************************************/ |
| dpslwk | 0:7480abd3b63b | 540 | typedef struct { |
| dpslwk | 0:7480abd3b63b | 541 | FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State: |
| dpslwk | 0:7480abd3b63b | 542 | - ENABLE: Enable this function. |
| dpslwk | 0:7480abd3b63b | 543 | - DISABLE: Disable this function. */ |
| dpslwk | 0:7480abd3b63b | 544 | FunctionalState Rx_State; /*!< Receiver State: |
| dpslwk | 0:7480abd3b63b | 545 | - ENABLE: Enable Receiver. |
| dpslwk | 0:7480abd3b63b | 546 | - DISABLE: Disable Receiver. */ |
| dpslwk | 0:7480abd3b63b | 547 | FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state: |
| dpslwk | 0:7480abd3b63b | 548 | - ENABLE: ENABLE this function. |
| dpslwk | 0:7480abd3b63b | 549 | - DISABLE: Disable this function. */ |
| dpslwk | 0:7480abd3b63b | 550 | FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State: |
| dpslwk | 0:7480abd3b63b | 551 | - ENABLE: Enable this function. |
| dpslwk | 0:7480abd3b63b | 552 | - DISABLE: Disable this function. */ |
| dpslwk | 0:7480abd3b63b | 553 | UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state: |
| dpslwk | 0:7480abd3b63b | 554 | - UART1_RS485_DIRCTRL_RTS: |
| dpslwk | 0:7480abd3b63b | 555 | pin RTS is used for direction control. |
| dpslwk | 0:7480abd3b63b | 556 | - UART1_RS485_DIRCTRL_DTR: |
| dpslwk | 0:7480abd3b63b | 557 | pin DTR is used for direction control. */ |
| dpslwk | 0:7480abd3b63b | 558 | SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on |
| dpslwk | 0:7480abd3b63b | 559 | the RTS (or DTR) pin: |
| dpslwk | 0:7480abd3b63b | 560 | - RESET: The direction control pin will be driven |
| dpslwk | 0:7480abd3b63b | 561 | to logic "0" when the transmitter has data to be sent. |
| dpslwk | 0:7480abd3b63b | 562 | - SET: The direction control pin will be driven |
| dpslwk | 0:7480abd3b63b | 563 | to logic "1" when the transmitter has data to be sent. */ |
| dpslwk | 0:7480abd3b63b | 564 | uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */ |
| dpslwk | 0:7480abd3b63b | 565 | uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */ |
| dpslwk | 0:7480abd3b63b | 566 | } UART1_RS485_CTRLCFG_Type; |
| dpslwk | 0:7480abd3b63b | 567 | |
| dpslwk | 0:7480abd3b63b | 568 | /** |
| dpslwk | 0:7480abd3b63b | 569 | * @} |
| dpslwk | 0:7480abd3b63b | 570 | */ |
| dpslwk | 0:7480abd3b63b | 571 | |
| dpslwk | 0:7480abd3b63b | 572 | |
| dpslwk | 0:7480abd3b63b | 573 | /* Public Functions ----------------------------------------------------------- */ |
| dpslwk | 0:7480abd3b63b | 574 | /** @defgroup UART_Public_Functions UART Public Functions |
| dpslwk | 0:7480abd3b63b | 575 | * @{ |
| dpslwk | 0:7480abd3b63b | 576 | */ |
| dpslwk | 0:7480abd3b63b | 577 | /* UART Init/DeInit functions --------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 578 | void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct); |
| dpslwk | 0:7480abd3b63b | 579 | void UART_DeInit(LPC_UART_TypeDef* UARTx); |
| dpslwk | 0:7480abd3b63b | 580 | void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct); |
| dpslwk | 0:7480abd3b63b | 581 | |
| dpslwk | 0:7480abd3b63b | 582 | /* UART Send/Receive functions -------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 583 | void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data); |
| dpslwk | 0:7480abd3b63b | 584 | uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx); |
| dpslwk | 0:7480abd3b63b | 585 | uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, |
| dpslwk | 0:7480abd3b63b | 586 | uint32_t buflen, TRANSFER_BLOCK_Type flag); |
| dpslwk | 0:7480abd3b63b | 587 | uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ |
| dpslwk | 0:7480abd3b63b | 588 | uint32_t buflen, TRANSFER_BLOCK_Type flag); |
| dpslwk | 0:7480abd3b63b | 589 | |
| dpslwk | 0:7480abd3b63b | 590 | /* UART FIFO functions ----------------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 591 | void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg); |
| dpslwk | 0:7480abd3b63b | 592 | void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct); |
| dpslwk | 0:7480abd3b63b | 593 | |
| dpslwk | 0:7480abd3b63b | 594 | /* UART get information functions -----------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 595 | uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx); |
| dpslwk | 0:7480abd3b63b | 596 | uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx); |
| dpslwk | 0:7480abd3b63b | 597 | |
| dpslwk | 0:7480abd3b63b | 598 | /* UART operate functions -------------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 599 | void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \ |
| dpslwk | 0:7480abd3b63b | 600 | FunctionalState NewState); |
| dpslwk | 0:7480abd3b63b | 601 | void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState); |
| dpslwk | 0:7480abd3b63b | 602 | FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx); |
| dpslwk | 0:7480abd3b63b | 603 | void UART_ForceBreak(LPC_UART_TypeDef* UARTx); |
| dpslwk | 0:7480abd3b63b | 604 | |
| dpslwk | 0:7480abd3b63b | 605 | /* UART Auto-baud functions -----------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 606 | void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType); |
| dpslwk | 0:7480abd3b63b | 607 | void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ |
| dpslwk | 0:7480abd3b63b | 608 | FunctionalState NewState); |
| dpslwk | 0:7480abd3b63b | 609 | |
| dpslwk | 0:7480abd3b63b | 610 | /* UART1 FullModem functions ----------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 611 | void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ |
| dpslwk | 0:7480abd3b63b | 612 | UART1_SignalState NewState); |
| dpslwk | 0:7480abd3b63b | 613 | void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ |
| dpslwk | 0:7480abd3b63b | 614 | FunctionalState NewState); |
| dpslwk | 0:7480abd3b63b | 615 | uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx); |
| dpslwk | 0:7480abd3b63b | 616 | |
| dpslwk | 0:7480abd3b63b | 617 | /* UART RS485 functions ----------------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 618 | void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \ |
| dpslwk | 0:7480abd3b63b | 619 | UART1_RS485_CTRLCFG_Type *RS485ConfigStruct); |
| dpslwk | 0:7480abd3b63b | 620 | void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState); |
| dpslwk | 0:7480abd3b63b | 621 | void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr); |
| dpslwk | 0:7480abd3b63b | 622 | uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size); |
| dpslwk | 0:7480abd3b63b | 623 | |
| dpslwk | 0:7480abd3b63b | 624 | /* UART IrDA functions-------------------------------------------------------------*/ |
| dpslwk | 0:7480abd3b63b | 625 | void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); |
| dpslwk | 0:7480abd3b63b | 626 | void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); |
| dpslwk | 0:7480abd3b63b | 627 | void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv); |
| dpslwk | 0:7480abd3b63b | 628 | /** |
| dpslwk | 0:7480abd3b63b | 629 | * @} |
| dpslwk | 0:7480abd3b63b | 630 | */ |
| dpslwk | 0:7480abd3b63b | 631 | |
| dpslwk | 0:7480abd3b63b | 632 | |
| dpslwk | 0:7480abd3b63b | 633 | #ifdef __cplusplus |
| dpslwk | 0:7480abd3b63b | 634 | } |
| dpslwk | 0:7480abd3b63b | 635 | #endif |
| dpslwk | 0:7480abd3b63b | 636 | |
| dpslwk | 0:7480abd3b63b | 637 | |
| dpslwk | 0:7480abd3b63b | 638 | #endif /* __LPC17XX_UART_H */ |
| dpslwk | 0:7480abd3b63b | 639 | |
| dpslwk | 0:7480abd3b63b | 640 | /** |
| dpslwk | 0:7480abd3b63b | 641 | * @} |
| dpslwk | 0:7480abd3b63b | 642 | */ |
| dpslwk | 0:7480abd3b63b | 643 | |
| dpslwk | 0:7480abd3b63b | 644 | /* --------------------------------- End Of File ------------------------------ */ |