DMA_UART_example - Example of UART-DMA transfers taken form the npx …

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Matt Lloyd / Mbed 2 deprecated DMA_UART_example

Example of UART-DMA transfers taken form the npx cmsis driver libary

lpc17xx_clkpwr.h@0:7480abd3b63b, 2010-09-30 (annotated)

Committer:: dpslwk
Date:: Thu Sep 30 20:13:24 2010 +0000
Revision:: 0:7480abd3b63b

Who changed what in which revision?

User	Revision	Line number	New contents of line
dpslwk	0:7480abd3b63b	1	/*********************************************************************//
dpslwk	0:7480abd3b63b	2	* @file lpc17xx_clkpwr.h
dpslwk	0:7480abd3b63b	3	* @brief Contains all macro definitions and function prototypes
dpslwk	0:7480abd3b63b	4	* support for Clock and Power Control firmware library on LPC17xx
dpslwk	0:7480abd3b63b	5	* @version 2.0
dpslwk	0:7480abd3b63b	6	* @date 21. May. 2010
dpslwk	0:7480abd3b63b	7	* @author NXP MCU SW Application Team
dpslwk	0:7480abd3b63b	8	**************************************************************************
dpslwk	0:7480abd3b63b	9	* Software that is described herein is for illustrative purposes only
dpslwk	0:7480abd3b63b	10	* which provides customers with programming information regarding the
dpslwk	0:7480abd3b63b	11	* products. This software is supplied "AS IS" without any warranties.
dpslwk	0:7480abd3b63b	12	* NXP Semiconductors assumes no responsibility or liability for the
dpslwk	0:7480abd3b63b	13	* use of the software, conveys no license or title under any patent,
dpslwk	0:7480abd3b63b	14	* copyright, or mask work right to the product. NXP Semiconductors
dpslwk	0:7480abd3b63b	15	* reserves the right to make changes in the software without
dpslwk	0:7480abd3b63b	16	* notification. NXP Semiconductors also make no representation or
dpslwk	0:7480abd3b63b	17	* warranty that such application will be suitable for the specified
dpslwk	0:7480abd3b63b	18	* use without further testing or modification.
dpslwk	0:7480abd3b63b	19	**************************************************************************/
dpslwk	0:7480abd3b63b	20
dpslwk	0:7480abd3b63b	21	/* Peripheral group ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	22	/** @defgroup CLKPWR CLKPWR
dpslwk	0:7480abd3b63b	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
dpslwk	0:7480abd3b63b	24	* @{
dpslwk	0:7480abd3b63b	25	*/
dpslwk	0:7480abd3b63b	26
dpslwk	0:7480abd3b63b	27	#ifndef LPC17XX_CLKPWR_H_
dpslwk	0:7480abd3b63b	28	#define LPC17XX_CLKPWR_H_
dpslwk	0:7480abd3b63b	29
dpslwk	0:7480abd3b63b	30	/* Includes ------------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	31	#include "LPC17xx.h"
dpslwk	0:7480abd3b63b	32	#include "lpc_types.h"
dpslwk	0:7480abd3b63b	33
dpslwk	0:7480abd3b63b	34	#ifdef __cplusplus
dpslwk	0:7480abd3b63b	35	extern "C"
dpslwk	0:7480abd3b63b	36	{
dpslwk	0:7480abd3b63b	37	#endif
dpslwk	0:7480abd3b63b	38
dpslwk	0:7480abd3b63b	39	/* Public Macros -------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	40	/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
dpslwk	0:7480abd3b63b	41	* @{
dpslwk	0:7480abd3b63b	42	*/
dpslwk	0:7480abd3b63b	43
dpslwk	0:7480abd3b63b	44	/**********************************************************************
dpslwk	0:7480abd3b63b	45	* Peripheral Clock Selection Definitions
dpslwk	0:7480abd3b63b	46	**********************************************************************/
dpslwk	0:7480abd3b63b	47	/** Peripheral clock divider bit position for WDT */
dpslwk	0:7480abd3b63b	48	#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
dpslwk	0:7480abd3b63b	49	/** Peripheral clock divider bit position for TIMER0 */
dpslwk	0:7480abd3b63b	50	#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
dpslwk	0:7480abd3b63b	51	/** Peripheral clock divider bit position for TIMER1 */
dpslwk	0:7480abd3b63b	52	#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
dpslwk	0:7480abd3b63b	53	/** Peripheral clock divider bit position for UART0 */
dpslwk	0:7480abd3b63b	54	#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
dpslwk	0:7480abd3b63b	55	/** Peripheral clock divider bit position for UART1 */
dpslwk	0:7480abd3b63b	56	#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
dpslwk	0:7480abd3b63b	57	/** Peripheral clock divider bit position for PWM1 */
dpslwk	0:7480abd3b63b	58	#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
dpslwk	0:7480abd3b63b	59	/** Peripheral clock divider bit position for I2C0 */
dpslwk	0:7480abd3b63b	60	#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
dpslwk	0:7480abd3b63b	61	/** Peripheral clock divider bit position for SPI */
dpslwk	0:7480abd3b63b	62	#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
dpslwk	0:7480abd3b63b	63	/** Peripheral clock divider bit position for SSP1 */
dpslwk	0:7480abd3b63b	64	#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
dpslwk	0:7480abd3b63b	65	/** Peripheral clock divider bit position for DAC */
dpslwk	0:7480abd3b63b	66	#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
dpslwk	0:7480abd3b63b	67	/** Peripheral clock divider bit position for ADC */
dpslwk	0:7480abd3b63b	68	#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
dpslwk	0:7480abd3b63b	69	/** Peripheral clock divider bit position for CAN1 */
dpslwk	0:7480abd3b63b	70	#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
dpslwk	0:7480abd3b63b	71	/** Peripheral clock divider bit position for CAN2 */
dpslwk	0:7480abd3b63b	72	#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
dpslwk	0:7480abd3b63b	73	/** Peripheral clock divider bit position for ACF */
dpslwk	0:7480abd3b63b	74	#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
dpslwk	0:7480abd3b63b	75	/** Peripheral clock divider bit position for QEI */
dpslwk	0:7480abd3b63b	76	#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
dpslwk	0:7480abd3b63b	77	/** Peripheral clock divider bit position for PCB */
dpslwk	0:7480abd3b63b	78	#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
dpslwk	0:7480abd3b63b	79	/** Peripheral clock divider bit position for I2C1 */
dpslwk	0:7480abd3b63b	80	#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
dpslwk	0:7480abd3b63b	81	/** Peripheral clock divider bit position for SSP0 */
dpslwk	0:7480abd3b63b	82	#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
dpslwk	0:7480abd3b63b	83	/** Peripheral clock divider bit position for TIMER2 */
dpslwk	0:7480abd3b63b	84	#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
dpslwk	0:7480abd3b63b	85	/** Peripheral clock divider bit position for TIMER3 */
dpslwk	0:7480abd3b63b	86	#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
dpslwk	0:7480abd3b63b	87	/** Peripheral clock divider bit position for UART2 */
dpslwk	0:7480abd3b63b	88	#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
dpslwk	0:7480abd3b63b	89	/** Peripheral clock divider bit position for UART3 */
dpslwk	0:7480abd3b63b	90	#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
dpslwk	0:7480abd3b63b	91	/** Peripheral clock divider bit position for I2C2 */
dpslwk	0:7480abd3b63b	92	#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
dpslwk	0:7480abd3b63b	93	/** Peripheral clock divider bit position for I2S */
dpslwk	0:7480abd3b63b	94	#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
dpslwk	0:7480abd3b63b	95	/** Peripheral clock divider bit position for RIT */
dpslwk	0:7480abd3b63b	96	#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
dpslwk	0:7480abd3b63b	97	/** Peripheral clock divider bit position for SYSCON */
dpslwk	0:7480abd3b63b	98	#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
dpslwk	0:7480abd3b63b	99	/** Peripheral clock divider bit position for MC */
dpslwk	0:7480abd3b63b	100	#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
dpslwk	0:7480abd3b63b	101
dpslwk	0:7480abd3b63b	102	/** Macro for Peripheral Clock Selection register bit values
dpslwk	0:7480abd3b63b	103	* Note: When CCLK_DIV_8, Peripheral�s clock is selected to
dpslwk	0:7480abd3b63b	104	* PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
dpslwk	0:7480abd3b63b	105	* when �11�selects PCLK_xyz = CCLK/6 */
dpslwk	0:7480abd3b63b	106	/* Peripheral clock divider is set to 4 from CCLK */
dpslwk	0:7480abd3b63b	107	#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
dpslwk	0:7480abd3b63b	108	/** Peripheral clock divider is the same with CCLK */
dpslwk	0:7480abd3b63b	109	#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
dpslwk	0:7480abd3b63b	110	/** Peripheral clock divider is set to 2 from CCLK */
dpslwk	0:7480abd3b63b	111	#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
dpslwk	0:7480abd3b63b	112
dpslwk	0:7480abd3b63b	113
dpslwk	0:7480abd3b63b	114	/********************************************************************
dpslwk	0:7480abd3b63b	115	* Power Control for Peripherals Definitions
dpslwk	0:7480abd3b63b	116	**********************************************************************/
dpslwk	0:7480abd3b63b	117	/** Timer/Counter 0 power/clock control bit */
dpslwk	0:7480abd3b63b	118	#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
dpslwk	0:7480abd3b63b	119	/* Timer/Counter 1 power/clock control bit */
dpslwk	0:7480abd3b63b	120	#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
dpslwk	0:7480abd3b63b	121	/** UART0 power/clock control bit */
dpslwk	0:7480abd3b63b	122	#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
dpslwk	0:7480abd3b63b	123	/** UART1 power/clock control bit */
dpslwk	0:7480abd3b63b	124	#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
dpslwk	0:7480abd3b63b	125	/** PWM1 power/clock control bit */
dpslwk	0:7480abd3b63b	126	#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
dpslwk	0:7480abd3b63b	127	/** The I2C0 interface power/clock control bit */
dpslwk	0:7480abd3b63b	128	#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
dpslwk	0:7480abd3b63b	129	/** The SPI interface power/clock control bit */
dpslwk	0:7480abd3b63b	130	#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
dpslwk	0:7480abd3b63b	131	/** The RTC power/clock control bit */
dpslwk	0:7480abd3b63b	132	#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
dpslwk	0:7480abd3b63b	133	/** The SSP1 interface power/clock control bit */
dpslwk	0:7480abd3b63b	134	#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
dpslwk	0:7480abd3b63b	135	/** A/D converter 0 (ADC0) power/clock control bit */
dpslwk	0:7480abd3b63b	136	#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
dpslwk	0:7480abd3b63b	137	/** CAN Controller 1 power/clock control bit */
dpslwk	0:7480abd3b63b	138	#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
dpslwk	0:7480abd3b63b	139	/** CAN Controller 2 power/clock control bit */
dpslwk	0:7480abd3b63b	140	#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
dpslwk	0:7480abd3b63b	141	/** GPIO power/clock control bit */
dpslwk	0:7480abd3b63b	142	#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
dpslwk	0:7480abd3b63b	143	/** Repetitive Interrupt Timer power/clock control bit */
dpslwk	0:7480abd3b63b	144	#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
dpslwk	0:7480abd3b63b	145	/** Motor Control PWM */
dpslwk	0:7480abd3b63b	146	#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
dpslwk	0:7480abd3b63b	147	/** Quadrature Encoder Interface power/clock control bit */
dpslwk	0:7480abd3b63b	148	#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
dpslwk	0:7480abd3b63b	149	/** The I2C1 interface power/clock control bit */
dpslwk	0:7480abd3b63b	150	#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
dpslwk	0:7480abd3b63b	151	/** The SSP0 interface power/clock control bit */
dpslwk	0:7480abd3b63b	152	#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
dpslwk	0:7480abd3b63b	153	/** Timer 2 power/clock control bit */
dpslwk	0:7480abd3b63b	154	#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
dpslwk	0:7480abd3b63b	155	/** Timer 3 power/clock control bit */
dpslwk	0:7480abd3b63b	156	#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
dpslwk	0:7480abd3b63b	157	/** UART 2 power/clock control bit */
dpslwk	0:7480abd3b63b	158	#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
dpslwk	0:7480abd3b63b	159	/** UART 3 power/clock control bit */
dpslwk	0:7480abd3b63b	160	#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
dpslwk	0:7480abd3b63b	161	/** I2C interface 2 power/clock control bit */
dpslwk	0:7480abd3b63b	162	#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
dpslwk	0:7480abd3b63b	163	/** I2S interface power/clock control bit*/
dpslwk	0:7480abd3b63b	164	#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
dpslwk	0:7480abd3b63b	165	/** GP DMA function power/clock control bit*/
dpslwk	0:7480abd3b63b	166	#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
dpslwk	0:7480abd3b63b	167	/** Ethernet block power/clock control bit*/
dpslwk	0:7480abd3b63b	168	#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
dpslwk	0:7480abd3b63b	169	/** USB interface power/clock control bit*/
dpslwk	0:7480abd3b63b	170	#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
dpslwk	0:7480abd3b63b	171
dpslwk	0:7480abd3b63b	172
dpslwk	0:7480abd3b63b	173	/**
dpslwk	0:7480abd3b63b	174	* @}
dpslwk	0:7480abd3b63b	175	*/
dpslwk	0:7480abd3b63b	176	/* Private Macros ------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	177	/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
dpslwk	0:7480abd3b63b	178	* @{
dpslwk	0:7480abd3b63b	179	*/
dpslwk	0:7480abd3b63b	180
dpslwk	0:7480abd3b63b	181	/* --------------------- BIT DEFINITIONS -------------------------------------- */
dpslwk	0:7480abd3b63b	182	/*******************************************************************//
dpslwk	0:7480abd3b63b	183	* Macro defines for Clock Source Select Register
dpslwk	0:7480abd3b63b	184	**********************************************************************/
dpslwk	0:7480abd3b63b	185	/** Internal RC oscillator */
dpslwk	0:7480abd3b63b	186	#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
dpslwk	0:7480abd3b63b	187	/** Main oscillator */
dpslwk	0:7480abd3b63b	188	#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
dpslwk	0:7480abd3b63b	189	/** RTC oscillator */
dpslwk	0:7480abd3b63b	190	#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
dpslwk	0:7480abd3b63b	191	/** Clock source selection bit mask */
dpslwk	0:7480abd3b63b	192	#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
dpslwk	0:7480abd3b63b	193
dpslwk	0:7480abd3b63b	194	/*******************************************************************//
dpslwk	0:7480abd3b63b	195	* Macro defines for Clock Output Configuration Register
dpslwk	0:7480abd3b63b	196	**********************************************************************/
dpslwk	0:7480abd3b63b	197	/* Clock Output Configuration register definition */
dpslwk	0:7480abd3b63b	198	/** Selects the CPU clock as the CLKOUT source */
dpslwk	0:7480abd3b63b	199	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
dpslwk	0:7480abd3b63b	200	/** Selects the main oscillator as the CLKOUT source */
dpslwk	0:7480abd3b63b	201	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
dpslwk	0:7480abd3b63b	202	/** Selects the Internal RC oscillator as the CLKOUT source */
dpslwk	0:7480abd3b63b	203	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
dpslwk	0:7480abd3b63b	204	/** Selects the USB clock as the CLKOUT source */
dpslwk	0:7480abd3b63b	205	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
dpslwk	0:7480abd3b63b	206	/** Selects the RTC oscillator as the CLKOUT source */
dpslwk	0:7480abd3b63b	207	#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
dpslwk	0:7480abd3b63b	208	/** Integer value to divide the output clock by, minus one */
dpslwk	0:7480abd3b63b	209	#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
dpslwk	0:7480abd3b63b	210	/** CLKOUT enable control */
dpslwk	0:7480abd3b63b	211	#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
dpslwk	0:7480abd3b63b	212	/** CLKOUT activity indication */
dpslwk	0:7480abd3b63b	213	#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
dpslwk	0:7480abd3b63b	214	/** Clock source selection bit mask */
dpslwk	0:7480abd3b63b	215	#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
dpslwk	0:7480abd3b63b	216
dpslwk	0:7480abd3b63b	217	/*******************************************************************//
dpslwk	0:7480abd3b63b	218	* Macro defines for PPL0 Control Register
dpslwk	0:7480abd3b63b	219	**********************************************************************/
dpslwk	0:7480abd3b63b	220	/** PLL 0 control enable */
dpslwk	0:7480abd3b63b	221	#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
dpslwk	0:7480abd3b63b	222	/** PLL 0 control connect */
dpslwk	0:7480abd3b63b	223	#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
dpslwk	0:7480abd3b63b	224	/** PLL 0 control bit mask */
dpslwk	0:7480abd3b63b	225	#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
dpslwk	0:7480abd3b63b	226
dpslwk	0:7480abd3b63b	227	/*******************************************************************//
dpslwk	0:7480abd3b63b	228	* Macro defines for PPL0 Configuration Register
dpslwk	0:7480abd3b63b	229	**********************************************************************/
dpslwk	0:7480abd3b63b	230	/** PLL 0 Configuration MSEL field */
dpslwk	0:7480abd3b63b	231	#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
dpslwk	0:7480abd3b63b	232	/** PLL 0 Configuration NSEL field */
dpslwk	0:7480abd3b63b	233	#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
dpslwk	0:7480abd3b63b	234	/** PLL 0 Configuration bit mask */
dpslwk	0:7480abd3b63b	235	#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
dpslwk	0:7480abd3b63b	236
dpslwk	0:7480abd3b63b	237
dpslwk	0:7480abd3b63b	238	/*******************************************************************//
dpslwk	0:7480abd3b63b	239	* Macro defines for PPL0 Status Register
dpslwk	0:7480abd3b63b	240	**********************************************************************/
dpslwk	0:7480abd3b63b	241	/** PLL 0 MSEL value */
dpslwk	0:7480abd3b63b	242	#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
dpslwk	0:7480abd3b63b	243	/** PLL NSEL get value */
dpslwk	0:7480abd3b63b	244	#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
dpslwk	0:7480abd3b63b	245	/** PLL status enable bit */
dpslwk	0:7480abd3b63b	246	#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
dpslwk	0:7480abd3b63b	247	/** PLL status Connect bit */
dpslwk	0:7480abd3b63b	248	#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
dpslwk	0:7480abd3b63b	249	/** PLL status lock */
dpslwk	0:7480abd3b63b	250	#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
dpslwk	0:7480abd3b63b	251
dpslwk	0:7480abd3b63b	252	/*******************************************************************//
dpslwk	0:7480abd3b63b	253	* Macro defines for PPL0 Feed Register
dpslwk	0:7480abd3b63b	254	**********************************************************************/
dpslwk	0:7480abd3b63b	255	/** PLL0 Feed bit mask */
dpslwk	0:7480abd3b63b	256	#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
dpslwk	0:7480abd3b63b	257
dpslwk	0:7480abd3b63b	258	/*******************************************************************//
dpslwk	0:7480abd3b63b	259	* Macro defines for PLL1 Control Register
dpslwk	0:7480abd3b63b	260	**********************************************************************/
dpslwk	0:7480abd3b63b	261	/** USB PLL control enable */
dpslwk	0:7480abd3b63b	262	#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
dpslwk	0:7480abd3b63b	263	/** USB PLL control connect */
dpslwk	0:7480abd3b63b	264	#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
dpslwk	0:7480abd3b63b	265	/** USB PLL control bit mask */
dpslwk	0:7480abd3b63b	266	#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
dpslwk	0:7480abd3b63b	267
dpslwk	0:7480abd3b63b	268	/*******************************************************************//
dpslwk	0:7480abd3b63b	269	* Macro defines for PLL1 Configuration Register
dpslwk	0:7480abd3b63b	270	**********************************************************************/
dpslwk	0:7480abd3b63b	271	/** USB PLL MSEL set value */
dpslwk	0:7480abd3b63b	272	#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
dpslwk	0:7480abd3b63b	273	/** USB PLL PSEL set value */
dpslwk	0:7480abd3b63b	274	#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
dpslwk	0:7480abd3b63b	275	/** USB PLL configuration bit mask */
dpslwk	0:7480abd3b63b	276	#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
dpslwk	0:7480abd3b63b	277
dpslwk	0:7480abd3b63b	278	/*******************************************************************//
dpslwk	0:7480abd3b63b	279	* Macro defines for PLL1 Status Register
dpslwk	0:7480abd3b63b	280	**********************************************************************/
dpslwk	0:7480abd3b63b	281	/** USB PLL MSEL get value */
dpslwk	0:7480abd3b63b	282	#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
dpslwk	0:7480abd3b63b	283	/** USB PLL PSEL get value */
dpslwk	0:7480abd3b63b	284	#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
dpslwk	0:7480abd3b63b	285	/** USB PLL status enable bit */
dpslwk	0:7480abd3b63b	286	#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
dpslwk	0:7480abd3b63b	287	/** USB PLL status Connect bit */
dpslwk	0:7480abd3b63b	288	#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
dpslwk	0:7480abd3b63b	289	/** USB PLL status lock */
dpslwk	0:7480abd3b63b	290	#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
dpslwk	0:7480abd3b63b	291
dpslwk	0:7480abd3b63b	292	/*******************************************************************//
dpslwk	0:7480abd3b63b	293	* Macro defines for PLL1 Feed Register
dpslwk	0:7480abd3b63b	294	**********************************************************************/
dpslwk	0:7480abd3b63b	295	/** PLL1 Feed bit mask */
dpslwk	0:7480abd3b63b	296	#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
dpslwk	0:7480abd3b63b	297
dpslwk	0:7480abd3b63b	298	/*******************************************************************//
dpslwk	0:7480abd3b63b	299	* Macro defines for CPU Clock Configuration Register
dpslwk	0:7480abd3b63b	300	**********************************************************************/
dpslwk	0:7480abd3b63b	301	/** CPU Clock configuration bit mask */
dpslwk	0:7480abd3b63b	302	#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
dpslwk	0:7480abd3b63b	303
dpslwk	0:7480abd3b63b	304	/*******************************************************************//
dpslwk	0:7480abd3b63b	305	* Macro defines for USB Clock Configuration Register
dpslwk	0:7480abd3b63b	306	**********************************************************************/
dpslwk	0:7480abd3b63b	307	/** USB Clock Configuration bit mask */
dpslwk	0:7480abd3b63b	308	#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
dpslwk	0:7480abd3b63b	309
dpslwk	0:7480abd3b63b	310	/*******************************************************************//
dpslwk	0:7480abd3b63b	311	* Macro defines for IRC Trim Register
dpslwk	0:7480abd3b63b	312	**********************************************************************/
dpslwk	0:7480abd3b63b	313	/** IRC Trim bit mask */
dpslwk	0:7480abd3b63b	314	#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
dpslwk	0:7480abd3b63b	315
dpslwk	0:7480abd3b63b	316	/*******************************************************************//
dpslwk	0:7480abd3b63b	317	* Macro defines for Peripheral Clock Selection Register 0 and 1
dpslwk	0:7480abd3b63b	318	**********************************************************************/
dpslwk	0:7480abd3b63b	319	/** Peripheral Clock Selection 0 mask bit */
dpslwk	0:7480abd3b63b	320	#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
dpslwk	0:7480abd3b63b	321	/** Peripheral Clock Selection 1 mask bit */
dpslwk	0:7480abd3b63b	322	#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
dpslwk	0:7480abd3b63b	323	/** Macro to set peripheral clock of each type
dpslwk	0:7480abd3b63b	324	* p: position of two bits that hold divider of peripheral clock
dpslwk	0:7480abd3b63b	325	* n: value of divider of peripheral clock to be set */
dpslwk	0:7480abd3b63b	326	#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
dpslwk	0:7480abd3b63b	327	/** Macro to mask peripheral clock of each type */
dpslwk	0:7480abd3b63b	328	#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
dpslwk	0:7480abd3b63b	329	/** Macro to get peripheral clock of each type */
dpslwk	0:7480abd3b63b	330	#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
dpslwk	0:7480abd3b63b	331
dpslwk	0:7480abd3b63b	332	/*******************************************************************//
dpslwk	0:7480abd3b63b	333	* Macro defines for Power Mode Control Register
dpslwk	0:7480abd3b63b	334	**********************************************************************/
dpslwk	0:7480abd3b63b	335	/** Power mode control bit 0 */
dpslwk	0:7480abd3b63b	336	#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
dpslwk	0:7480abd3b63b	337	/** Power mode control bit 1 */
dpslwk	0:7480abd3b63b	338	#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
dpslwk	0:7480abd3b63b	339	/** Brown-Out Reduced Power Mode */
dpslwk	0:7480abd3b63b	340	#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
dpslwk	0:7480abd3b63b	341	/** Brown-Out Global Disable */
dpslwk	0:7480abd3b63b	342	#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
dpslwk	0:7480abd3b63b	343	/** Brown Out Reset Disable */
dpslwk	0:7480abd3b63b	344	#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
dpslwk	0:7480abd3b63b	345	/** Sleep Mode entry flag */
dpslwk	0:7480abd3b63b	346	#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
dpslwk	0:7480abd3b63b	347	/** Deep Sleep entry flag */
dpslwk	0:7480abd3b63b	348	#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
dpslwk	0:7480abd3b63b	349	/** Power-down entry flag */
dpslwk	0:7480abd3b63b	350	#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
dpslwk	0:7480abd3b63b	351	/** Deep Power-down entry flag */
dpslwk	0:7480abd3b63b	352	#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
dpslwk	0:7480abd3b63b	353
dpslwk	0:7480abd3b63b	354	/*******************************************************************//
dpslwk	0:7480abd3b63b	355	* Macro defines for Power Control for Peripheral Register
dpslwk	0:7480abd3b63b	356	**********************************************************************/
dpslwk	0:7480abd3b63b	357	/** Power Control for Peripherals bit mask */
dpslwk	0:7480abd3b63b	358	#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
dpslwk	0:7480abd3b63b	359
dpslwk	0:7480abd3b63b	360	/**
dpslwk	0:7480abd3b63b	361	* @}
dpslwk	0:7480abd3b63b	362	*/
dpslwk	0:7480abd3b63b	363
dpslwk	0:7480abd3b63b	364
dpslwk	0:7480abd3b63b	365	/* Public Functions ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	366	/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
dpslwk	0:7480abd3b63b	367	* @{
dpslwk	0:7480abd3b63b	368	*/
dpslwk	0:7480abd3b63b	369
dpslwk	0:7480abd3b63b	370	void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
dpslwk	0:7480abd3b63b	371	uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
dpslwk	0:7480abd3b63b	372	uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
dpslwk	0:7480abd3b63b	373	void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
dpslwk	0:7480abd3b63b	374	void CLKPWR_Sleep(void);
dpslwk	0:7480abd3b63b	375	void CLKPWR_DeepSleep(void);
dpslwk	0:7480abd3b63b	376	void CLKPWR_PowerDown(void);
dpslwk	0:7480abd3b63b	377	void CLKPWR_DeepPowerDown(void);
dpslwk	0:7480abd3b63b	378
dpslwk	0:7480abd3b63b	379	/**
dpslwk	0:7480abd3b63b	380	* @}
dpslwk	0:7480abd3b63b	381	*/
dpslwk	0:7480abd3b63b	382
dpslwk	0:7480abd3b63b	383
dpslwk	0:7480abd3b63b	384	#ifdef __cplusplus
dpslwk	0:7480abd3b63b	385	}
dpslwk	0:7480abd3b63b	386	#endif
dpslwk	0:7480abd3b63b	387
dpslwk	0:7480abd3b63b	388	#endif /* LPC17XX_CLKPWR_H_ */
dpslwk	0:7480abd3b63b	389
dpslwk	0:7480abd3b63b	390	/**
dpslwk	0:7480abd3b63b	391	* @}
dpslwk	0:7480abd3b63b	392	*/
dpslwk	0:7480abd3b63b	393
dpslwk	0:7480abd3b63b	394	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	30 Sep 2010
Imports:	234
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	6

lpc17xx_clkpwr.h@0:7480abd3b63b, 2010-09-30 (annotated)

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