DMA_UART_example - Example of UART-DMA transfers taken form the npx …

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Matt Lloyd / Mbed 2 deprecated DMA_UART_example

Example of UART-DMA transfers taken form the npx cmsis driver libary

lpc17xx_uart.c@0:7480abd3b63b, 2010-09-30 (annotated)

Committer:: dpslwk
Date:: Thu Sep 30 20:13:24 2010 +0000
Revision:: 0:7480abd3b63b

Who changed what in which revision?

User	Revision	Line number	New contents of line
dpslwk	0:7480abd3b63b	1	/*********************************************************************//
dpslwk	0:7480abd3b63b	2	* @file lpc17xx_uart.c
dpslwk	0:7480abd3b63b	3	* @brief Contains all functions support for UART firmware library on LPC17xx
dpslwk	0:7480abd3b63b	4	* @version 3.0
dpslwk	0:7480abd3b63b	5	* @date 18. June. 2010
dpslwk	0:7480abd3b63b	6	* @author NXP MCU SW Application Team
dpslwk	0:7480abd3b63b	7	**************************************************************************
dpslwk	0:7480abd3b63b	8	* Software that is described herein is for illustrative purposes only
dpslwk	0:7480abd3b63b	9	* which provides customers with programming information regarding the
dpslwk	0:7480abd3b63b	10	* products. This software is supplied "AS IS" without any warranties.
dpslwk	0:7480abd3b63b	11	* NXP Semiconductors assumes no responsibility or liability for the
dpslwk	0:7480abd3b63b	12	* use of the software, conveys no license or title under any patent,
dpslwk	0:7480abd3b63b	13	* copyright, or mask work right to the product. NXP Semiconductors
dpslwk	0:7480abd3b63b	14	* reserves the right to make changes in the software without
dpslwk	0:7480abd3b63b	15	* notification. NXP Semiconductors also make no representation or
dpslwk	0:7480abd3b63b	16	* warranty that such application will be suitable for the specified
dpslwk	0:7480abd3b63b	17	* use without further testing or modification.
dpslwk	0:7480abd3b63b	18	**********************************************************************/
dpslwk	0:7480abd3b63b	19
dpslwk	0:7480abd3b63b	20	/* Peripheral group ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	21	/** @addtogroup UART
dpslwk	0:7480abd3b63b	22	* @{
dpslwk	0:7480abd3b63b	23	*/
dpslwk	0:7480abd3b63b	24
dpslwk	0:7480abd3b63b	25	/* Includes ------------------------------------------------------------------- */
dpslwk	0:7480abd3b63b	26	#include "lpc17xx_uart.h"
dpslwk	0:7480abd3b63b	27	#include "lpc17xx_clkpwr.h"
dpslwk	0:7480abd3b63b	28
dpslwk	0:7480abd3b63b	29	/* If this source file built with example, the LPC17xx FW library configuration
dpslwk	0:7480abd3b63b	30	* file in each example directory ("lpc17xx_libcfg.h") must be included,
dpslwk	0:7480abd3b63b	31	* otherwise the default FW library configuration file must be included instead
dpslwk	0:7480abd3b63b	32	*/
dpslwk	0:7480abd3b63b	33	#ifdef __BUILD_WITH_EXAMPLE__
dpslwk	0:7480abd3b63b	34	#include "lpc17xx_libcfg.h"
dpslwk	0:7480abd3b63b	35	#else
dpslwk	0:7480abd3b63b	36	#include "lpc17xx_libcfg_default.h"
dpslwk	0:7480abd3b63b	37	#endif /* __BUILD_WITH_EXAMPLE__ */
dpslwk	0:7480abd3b63b	38
dpslwk	0:7480abd3b63b	39
dpslwk	0:7480abd3b63b	40	#ifdef _UART
dpslwk	0:7480abd3b63b	41
dpslwk	0:7480abd3b63b	42	/* Private Functions ---------------------------------------------------------- */
dpslwk	0:7480abd3b63b	43
dpslwk	0:7480abd3b63b	44	static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate);
dpslwk	0:7480abd3b63b	45
dpslwk	0:7480abd3b63b	46
dpslwk	0:7480abd3b63b	47	/*******************************************************************//
dpslwk	0:7480abd3b63b	48	* @brief Determines best dividers to get a target clock rate
dpslwk	0:7480abd3b63b	49	* @param[in] UARTx Pointer to selected UART peripheral, should be:
dpslwk	0:7480abd3b63b	50	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	51	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	52	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	53	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	54	* @param[in] baudrate Desired UART baud rate.
dpslwk	0:7480abd3b63b	55	* @return Error status, could be:
dpslwk	0:7480abd3b63b	56	* - SUCCESS
dpslwk	0:7480abd3b63b	57	* - ERROR
dpslwk	0:7480abd3b63b	58	**********************************************************************/
dpslwk	0:7480abd3b63b	59	static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
dpslwk	0:7480abd3b63b	60	{
dpslwk	0:7480abd3b63b	61	Status errorStatus = ERROR;
dpslwk	0:7480abd3b63b	62
dpslwk	0:7480abd3b63b	63	uint32_t uClk = 0;
dpslwk	0:7480abd3b63b	64	uint32_t calcBaudrate = 0;
dpslwk	0:7480abd3b63b	65	uint32_t temp = 0;
dpslwk	0:7480abd3b63b	66
dpslwk	0:7480abd3b63b	67	uint32_t mulFracDiv, dividerAddFracDiv;
dpslwk	0:7480abd3b63b	68	uint32_t diviser = 0 ;
dpslwk	0:7480abd3b63b	69	uint32_t mulFracDivOptimal = 1;
dpslwk	0:7480abd3b63b	70	uint32_t dividerAddOptimal = 0;
dpslwk	0:7480abd3b63b	71	uint32_t diviserOptimal = 0;
dpslwk	0:7480abd3b63b	72
dpslwk	0:7480abd3b63b	73	uint32_t relativeError = 0;
dpslwk	0:7480abd3b63b	74	uint32_t relativeOptimalError = 100000;
dpslwk	0:7480abd3b63b	75
dpslwk	0:7480abd3b63b	76	/* get UART block clock */
dpslwk	0:7480abd3b63b	77	if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
dpslwk	0:7480abd3b63b	78	{
dpslwk	0:7480abd3b63b	79	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART0);
dpslwk	0:7480abd3b63b	80	}
dpslwk	0:7480abd3b63b	81	else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1)
dpslwk	0:7480abd3b63b	82	{
dpslwk	0:7480abd3b63b	83	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART1);
dpslwk	0:7480abd3b63b	84	}
dpslwk	0:7480abd3b63b	85	else if (UARTx == LPC_UART2)
dpslwk	0:7480abd3b63b	86	{
dpslwk	0:7480abd3b63b	87	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART2);
dpslwk	0:7480abd3b63b	88	}
dpslwk	0:7480abd3b63b	89	else if (UARTx == LPC_UART3)
dpslwk	0:7480abd3b63b	90	{
dpslwk	0:7480abd3b63b	91	uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART3);
dpslwk	0:7480abd3b63b	92	}
dpslwk	0:7480abd3b63b	93
dpslwk	0:7480abd3b63b	94
dpslwk	0:7480abd3b63b	95	uClk = uClk >> 4; /* div by 16 */
dpslwk	0:7480abd3b63b	96	/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
dpslwk	0:7480abd3b63b	97	* The formula is :
dpslwk	0:7480abd3b63b	98	* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
dpslwk	0:7480abd3b63b	99	* It involves floating point calculations. That's the reason the formulae are adjusted with
dpslwk	0:7480abd3b63b	100	* Multiply and divide method.*/
dpslwk	0:7480abd3b63b	101	/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
dpslwk	0:7480abd3b63b	102	* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
dpslwk	0:7480abd3b63b	103	for (mulFracDiv = 1 ; mulFracDiv <= 15 ;mulFracDiv++)
dpslwk	0:7480abd3b63b	104	{
dpslwk	0:7480abd3b63b	105	for (dividerAddFracDiv = 0 ; dividerAddFracDiv <= 15 ;dividerAddFracDiv++)
dpslwk	0:7480abd3b63b	106	{
dpslwk	0:7480abd3b63b	107	temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
dpslwk	0:7480abd3b63b	108
dpslwk	0:7480abd3b63b	109	diviser = temp / baudrate;
dpslwk	0:7480abd3b63b	110	if ((temp % baudrate) > (baudrate / 2))
dpslwk	0:7480abd3b63b	111	diviser++;
dpslwk	0:7480abd3b63b	112
dpslwk	0:7480abd3b63b	113	if (diviser > 2 && diviser < 65536)
dpslwk	0:7480abd3b63b	114	{
dpslwk	0:7480abd3b63b	115	calcBaudrate = temp / diviser;
dpslwk	0:7480abd3b63b	116
dpslwk	0:7480abd3b63b	117	if (calcBaudrate <= baudrate)
dpslwk	0:7480abd3b63b	118	relativeError = baudrate - calcBaudrate;
dpslwk	0:7480abd3b63b	119	else
dpslwk	0:7480abd3b63b	120	relativeError = calcBaudrate - baudrate;
dpslwk	0:7480abd3b63b	121
dpslwk	0:7480abd3b63b	122	if ((relativeError < relativeOptimalError))
dpslwk	0:7480abd3b63b	123	{
dpslwk	0:7480abd3b63b	124	mulFracDivOptimal = mulFracDiv ;
dpslwk	0:7480abd3b63b	125	dividerAddOptimal = dividerAddFracDiv;
dpslwk	0:7480abd3b63b	126	diviserOptimal = diviser;
dpslwk	0:7480abd3b63b	127	relativeOptimalError = relativeError;
dpslwk	0:7480abd3b63b	128	if (relativeError == 0)
dpslwk	0:7480abd3b63b	129	break;
dpslwk	0:7480abd3b63b	130	}
dpslwk	0:7480abd3b63b	131	} /* End of if */
dpslwk	0:7480abd3b63b	132	} /* end of inner for loop */
dpslwk	0:7480abd3b63b	133	if (relativeError == 0)
dpslwk	0:7480abd3b63b	134	break;
dpslwk	0:7480abd3b63b	135	} /* end of outer for loop */
dpslwk	0:7480abd3b63b	136
dpslwk	0:7480abd3b63b	137	if (relativeOptimalError < ((baudrate * UART_ACCEPTED_BAUDRATE_ERROR)/100))
dpslwk	0:7480abd3b63b	138	{
dpslwk	0:7480abd3b63b	139	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	140	{
dpslwk	0:7480abd3b63b	141	((LPC_UART1_TypeDef *)UARTx)->LCR \|= UART_LCR_DLAB_EN;
dpslwk	0:7480abd3b63b	142	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal);
dpslwk	0:7480abd3b63b	143	((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal);
dpslwk	0:7480abd3b63b	144	/* Then reset DLAB bit */
dpslwk	0:7480abd3b63b	145	((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
dpslwk	0:7480abd3b63b	146	((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
dpslwk	0:7480abd3b63b	147	\| UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
dpslwk	0:7480abd3b63b	148	}
dpslwk	0:7480abd3b63b	149	else
dpslwk	0:7480abd3b63b	150	{
dpslwk	0:7480abd3b63b	151	UARTx->LCR \|= UART_LCR_DLAB_EN;
dpslwk	0:7480abd3b63b	152	UARTx->/DLIER./DLM = UART_LOAD_DLM(diviserOptimal);
dpslwk	0:7480abd3b63b	153	UARTx->/RBTHDLR./DLL = UART_LOAD_DLL(diviserOptimal);
dpslwk	0:7480abd3b63b	154	/* Then reset DLAB bit */
dpslwk	0:7480abd3b63b	155	UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
dpslwk	0:7480abd3b63b	156	UARTx->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
dpslwk	0:7480abd3b63b	157	\| UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
dpslwk	0:7480abd3b63b	158	}
dpslwk	0:7480abd3b63b	159	errorStatus = SUCCESS;
dpslwk	0:7480abd3b63b	160	}
dpslwk	0:7480abd3b63b	161
dpslwk	0:7480abd3b63b	162	return errorStatus;
dpslwk	0:7480abd3b63b	163	}
dpslwk	0:7480abd3b63b	164
dpslwk	0:7480abd3b63b	165	/* End of Private Functions ---------------------------------------------------- */
dpslwk	0:7480abd3b63b	166
dpslwk	0:7480abd3b63b	167
dpslwk	0:7480abd3b63b	168	/* Public Functions ----------------------------------------------------------- */
dpslwk	0:7480abd3b63b	169	/** @addtogroup UART_Public_Functions
dpslwk	0:7480abd3b63b	170	* @{
dpslwk	0:7480abd3b63b	171	*/
dpslwk	0:7480abd3b63b	172	/* UART Init/DeInit functions -------------------------------------------------*/
dpslwk	0:7480abd3b63b	173	/******************************************************************//
dpslwk	0:7480abd3b63b	174	* @brief Initializes the UARTx peripheral according to the specified
dpslwk	0:7480abd3b63b	175	* parameters in the UART_ConfigStruct.
dpslwk	0:7480abd3b63b	176	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	177	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	178	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	179	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	180	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	181	* @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure
dpslwk	0:7480abd3b63b	182	* that contains the configuration information for the
dpslwk	0:7480abd3b63b	183	* specified UART peripheral.
dpslwk	0:7480abd3b63b	184	* @return None
dpslwk	0:7480abd3b63b	185	*********************************************************************/
dpslwk	0:7480abd3b63b	186	void UART_Init(LPC_UART_TypeDef UARTx, UART_CFG_Type UART_ConfigStruct)
dpslwk	0:7480abd3b63b	187	{
dpslwk	0:7480abd3b63b	188	uint32_t tmp;
dpslwk	0:7480abd3b63b	189
dpslwk	0:7480abd3b63b	190	// For debug mode
dpslwk	0:7480abd3b63b	191	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	192	CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits));
dpslwk	0:7480abd3b63b	193	CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits));
dpslwk	0:7480abd3b63b	194	CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity));
dpslwk	0:7480abd3b63b	195
dpslwk	0:7480abd3b63b	196	#ifdef _UART0
dpslwk	0:7480abd3b63b	197	if(UARTx == (LPC_UART_TypeDef *)LPC_UART0)
dpslwk	0:7480abd3b63b	198	{
dpslwk	0:7480abd3b63b	199	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	200	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
dpslwk	0:7480abd3b63b	201	}
dpslwk	0:7480abd3b63b	202	#endif
dpslwk	0:7480abd3b63b	203
dpslwk	0:7480abd3b63b	204	#ifdef _UART1
dpslwk	0:7480abd3b63b	205	if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	206	{
dpslwk	0:7480abd3b63b	207	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	208	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
dpslwk	0:7480abd3b63b	209	}
dpslwk	0:7480abd3b63b	210	#endif
dpslwk	0:7480abd3b63b	211
dpslwk	0:7480abd3b63b	212	#ifdef _UART2
dpslwk	0:7480abd3b63b	213	if(UARTx == LPC_UART2)
dpslwk	0:7480abd3b63b	214	{
dpslwk	0:7480abd3b63b	215	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	216	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
dpslwk	0:7480abd3b63b	217	}
dpslwk	0:7480abd3b63b	218	#endif
dpslwk	0:7480abd3b63b	219
dpslwk	0:7480abd3b63b	220	#ifdef _UART3
dpslwk	0:7480abd3b63b	221	if(UARTx == LPC_UART3)
dpslwk	0:7480abd3b63b	222	{
dpslwk	0:7480abd3b63b	223	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	224	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
dpslwk	0:7480abd3b63b	225	}
dpslwk	0:7480abd3b63b	226	#endif
dpslwk	0:7480abd3b63b	227
dpslwk	0:7480abd3b63b	228	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	229	{
dpslwk	0:7480abd3b63b	230	/* FIFOs are empty */
dpslwk	0:7480abd3b63b	231	((LPC_UART1_TypeDef )UARTx)->/IIFCR.*/FCR = ( UART_FCR_FIFO_EN \
dpslwk	0:7480abd3b63b	232	\| UART_FCR_RX_RS \| UART_FCR_TX_RS);
dpslwk	0:7480abd3b63b	233	// Disable FIFO
dpslwk	0:7480abd3b63b	234	((LPC_UART1_TypeDef )UARTx)->/IIFCR.*/FCR = 0;
dpslwk	0:7480abd3b63b	235
dpslwk	0:7480abd3b63b	236	// Dummy reading
dpslwk	0:7480abd3b63b	237	while (((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_RDR)
dpslwk	0:7480abd3b63b	238	{
dpslwk	0:7480abd3b63b	239	tmp = ((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/RBR;
dpslwk	0:7480abd3b63b	240	}
dpslwk	0:7480abd3b63b	241
dpslwk	0:7480abd3b63b	242	((LPC_UART1_TypeDef *)UARTx)->TER = UART_TER_TXEN;
dpslwk	0:7480abd3b63b	243	// Wait for current transmit complete
dpslwk	0:7480abd3b63b	244	while (!(((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_THRE));
dpslwk	0:7480abd3b63b	245	// Disable Tx
dpslwk	0:7480abd3b63b	246	((LPC_UART1_TypeDef *)UARTx)->TER = 0;
dpslwk	0:7480abd3b63b	247
dpslwk	0:7480abd3b63b	248	// Disable interrupt
dpslwk	0:7480abd3b63b	249	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/IER = 0;
dpslwk	0:7480abd3b63b	250	// Set LCR to default state
dpslwk	0:7480abd3b63b	251	((LPC_UART1_TypeDef *)UARTx)->LCR = 0;
dpslwk	0:7480abd3b63b	252	// Set ACR to default state
dpslwk	0:7480abd3b63b	253	((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
dpslwk	0:7480abd3b63b	254	// Set Modem Control to default state
dpslwk	0:7480abd3b63b	255	((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
dpslwk	0:7480abd3b63b	256	// Set RS485 control to default state
dpslwk	0:7480abd3b63b	257	((LPC_UART1_TypeDef *)UARTx)->RS485CTRL = 0;
dpslwk	0:7480abd3b63b	258	// Set RS485 delay timer to default state
dpslwk	0:7480abd3b63b	259	((LPC_UART1_TypeDef *)UARTx)->RS485DLY = 0;
dpslwk	0:7480abd3b63b	260	// Set RS485 addr match to default state
dpslwk	0:7480abd3b63b	261	((LPC_UART1_TypeDef *)UARTx)->ADRMATCH = 0;
dpslwk	0:7480abd3b63b	262	//Dummy Reading to Clear Status
dpslwk	0:7480abd3b63b	263	tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
dpslwk	0:7480abd3b63b	264	tmp = ((LPC_UART1_TypeDef *)UARTx)->LSR;
dpslwk	0:7480abd3b63b	265	}
dpslwk	0:7480abd3b63b	266	else
dpslwk	0:7480abd3b63b	267	{
dpslwk	0:7480abd3b63b	268	/* FIFOs are empty */
dpslwk	0:7480abd3b63b	269	UARTx->/IIFCR./FCR = ( UART_FCR_FIFO_EN \| UART_FCR_RX_RS \| UART_FCR_TX_RS);
dpslwk	0:7480abd3b63b	270	// Disable FIFO
dpslwk	0:7480abd3b63b	271	UARTx->/IIFCR./FCR = 0;
dpslwk	0:7480abd3b63b	272
dpslwk	0:7480abd3b63b	273	// Dummy reading
dpslwk	0:7480abd3b63b	274	while (UARTx->LSR & UART_LSR_RDR)
dpslwk	0:7480abd3b63b	275	{
dpslwk	0:7480abd3b63b	276	tmp = UARTx->/RBTHDLR./RBR;
dpslwk	0:7480abd3b63b	277	}
dpslwk	0:7480abd3b63b	278
dpslwk	0:7480abd3b63b	279	UARTx->TER = UART_TER_TXEN;
dpslwk	0:7480abd3b63b	280	// Wait for current transmit complete
dpslwk	0:7480abd3b63b	281	while (!(UARTx->LSR & UART_LSR_THRE));
dpslwk	0:7480abd3b63b	282	// Disable Tx
dpslwk	0:7480abd3b63b	283	UARTx->TER = 0;
dpslwk	0:7480abd3b63b	284
dpslwk	0:7480abd3b63b	285	// Disable interrupt
dpslwk	0:7480abd3b63b	286	UARTx->/DLIER./IER = 0;
dpslwk	0:7480abd3b63b	287	// Set LCR to default state
dpslwk	0:7480abd3b63b	288	UARTx->LCR = 0;
dpslwk	0:7480abd3b63b	289	// Set ACR to default state
dpslwk	0:7480abd3b63b	290	UARTx->ACR = 0;
dpslwk	0:7480abd3b63b	291	// Dummy reading
dpslwk	0:7480abd3b63b	292	tmp = UARTx->LSR;
dpslwk	0:7480abd3b63b	293	}
dpslwk	0:7480abd3b63b	294
dpslwk	0:7480abd3b63b	295	if (UARTx == LPC_UART3)
dpslwk	0:7480abd3b63b	296	{
dpslwk	0:7480abd3b63b	297	// Set IrDA to default state
dpslwk	0:7480abd3b63b	298	UARTx->ICR = 0;
dpslwk	0:7480abd3b63b	299	}
dpslwk	0:7480abd3b63b	300
dpslwk	0:7480abd3b63b	301	// Set Line Control register ----------------------------
dpslwk	0:7480abd3b63b	302
dpslwk	0:7480abd3b63b	303	uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
dpslwk	0:7480abd3b63b	304
dpslwk	0:7480abd3b63b	305	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	306	{
dpslwk	0:7480abd3b63b	307	tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN \| UART_LCR_BREAK_EN)) \
dpslwk	0:7480abd3b63b	308	& UART_LCR_BITMASK;
dpslwk	0:7480abd3b63b	309	}
dpslwk	0:7480abd3b63b	310	else
dpslwk	0:7480abd3b63b	311	{
dpslwk	0:7480abd3b63b	312	tmp = (UARTx->LCR & (UART_LCR_DLAB_EN \| UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
dpslwk	0:7480abd3b63b	313	}
dpslwk	0:7480abd3b63b	314
dpslwk	0:7480abd3b63b	315	switch (UART_ConfigStruct->Databits){
dpslwk	0:7480abd3b63b	316	case UART_DATABIT_5:
dpslwk	0:7480abd3b63b	317	tmp \|= UART_LCR_WLEN5;
dpslwk	0:7480abd3b63b	318	break;
dpslwk	0:7480abd3b63b	319	case UART_DATABIT_6:
dpslwk	0:7480abd3b63b	320	tmp \|= UART_LCR_WLEN6;
dpslwk	0:7480abd3b63b	321	break;
dpslwk	0:7480abd3b63b	322	case UART_DATABIT_7:
dpslwk	0:7480abd3b63b	323	tmp \|= UART_LCR_WLEN7;
dpslwk	0:7480abd3b63b	324	break;
dpslwk	0:7480abd3b63b	325	case UART_DATABIT_8:
dpslwk	0:7480abd3b63b	326	default:
dpslwk	0:7480abd3b63b	327	tmp \|= UART_LCR_WLEN8;
dpslwk	0:7480abd3b63b	328	break;
dpslwk	0:7480abd3b63b	329	}
dpslwk	0:7480abd3b63b	330
dpslwk	0:7480abd3b63b	331	if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
dpslwk	0:7480abd3b63b	332	{
dpslwk	0:7480abd3b63b	333	// Do nothing...
dpslwk	0:7480abd3b63b	334	}
dpslwk	0:7480abd3b63b	335	else
dpslwk	0:7480abd3b63b	336	{
dpslwk	0:7480abd3b63b	337	tmp \|= UART_LCR_PARITY_EN;
dpslwk	0:7480abd3b63b	338	switch (UART_ConfigStruct->Parity)
dpslwk	0:7480abd3b63b	339	{
dpslwk	0:7480abd3b63b	340	case UART_PARITY_ODD:
dpslwk	0:7480abd3b63b	341	tmp \|= UART_LCR_PARITY_ODD;
dpslwk	0:7480abd3b63b	342	break;
dpslwk	0:7480abd3b63b	343
dpslwk	0:7480abd3b63b	344	case UART_PARITY_EVEN:
dpslwk	0:7480abd3b63b	345	tmp \|= UART_LCR_PARITY_EVEN;
dpslwk	0:7480abd3b63b	346	break;
dpslwk	0:7480abd3b63b	347
dpslwk	0:7480abd3b63b	348	case UART_PARITY_SP_1:
dpslwk	0:7480abd3b63b	349	tmp \|= UART_LCR_PARITY_F_1;
dpslwk	0:7480abd3b63b	350	break;
dpslwk	0:7480abd3b63b	351
dpslwk	0:7480abd3b63b	352	case UART_PARITY_SP_0:
dpslwk	0:7480abd3b63b	353	tmp \|= UART_LCR_PARITY_F_0;
dpslwk	0:7480abd3b63b	354	break;
dpslwk	0:7480abd3b63b	355	default:
dpslwk	0:7480abd3b63b	356	break;
dpslwk	0:7480abd3b63b	357	}
dpslwk	0:7480abd3b63b	358	}
dpslwk	0:7480abd3b63b	359
dpslwk	0:7480abd3b63b	360	switch (UART_ConfigStruct->Stopbits){
dpslwk	0:7480abd3b63b	361	case UART_STOPBIT_2:
dpslwk	0:7480abd3b63b	362	tmp \|= UART_LCR_STOPBIT_SEL;
dpslwk	0:7480abd3b63b	363	break;
dpslwk	0:7480abd3b63b	364	case UART_STOPBIT_1:
dpslwk	0:7480abd3b63b	365	default:
dpslwk	0:7480abd3b63b	366	// Do no thing
dpslwk	0:7480abd3b63b	367	break;
dpslwk	0:7480abd3b63b	368	}
dpslwk	0:7480abd3b63b	369
dpslwk	0:7480abd3b63b	370
dpslwk	0:7480abd3b63b	371	// Write back to LCR, configure FIFO and Disable Tx
dpslwk	0:7480abd3b63b	372	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	373	{
dpslwk	0:7480abd3b63b	374	((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
dpslwk	0:7480abd3b63b	375	}
dpslwk	0:7480abd3b63b	376	else
dpslwk	0:7480abd3b63b	377	{
dpslwk	0:7480abd3b63b	378	UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
dpslwk	0:7480abd3b63b	379	}
dpslwk	0:7480abd3b63b	380	}
dpslwk	0:7480abd3b63b	381
dpslwk	0:7480abd3b63b	382	/*******************************************************************//
dpslwk	0:7480abd3b63b	383	* @brief De-initializes the UARTx peripheral registers to their
dpslwk	0:7480abd3b63b	384	* default reset values.
dpslwk	0:7480abd3b63b	385	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	386	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	387	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	388	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	389	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	390	* @return None
dpslwk	0:7480abd3b63b	391	**********************************************************************/
dpslwk	0:7480abd3b63b	392	void UART_DeInit(LPC_UART_TypeDef* UARTx)
dpslwk	0:7480abd3b63b	393	{
dpslwk	0:7480abd3b63b	394	// For debug mode
dpslwk	0:7480abd3b63b	395	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	396
dpslwk	0:7480abd3b63b	397	UART_TxCmd(UARTx, DISABLE);
dpslwk	0:7480abd3b63b	398
dpslwk	0:7480abd3b63b	399	#ifdef _UART0
dpslwk	0:7480abd3b63b	400	if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
dpslwk	0:7480abd3b63b	401	{
dpslwk	0:7480abd3b63b	402	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	403	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
dpslwk	0:7480abd3b63b	404	}
dpslwk	0:7480abd3b63b	405	#endif
dpslwk	0:7480abd3b63b	406
dpslwk	0:7480abd3b63b	407	#ifdef _UART1
dpslwk	0:7480abd3b63b	408	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	409	{
dpslwk	0:7480abd3b63b	410	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	411	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
dpslwk	0:7480abd3b63b	412	}
dpslwk	0:7480abd3b63b	413	#endif
dpslwk	0:7480abd3b63b	414
dpslwk	0:7480abd3b63b	415	#ifdef _UART2
dpslwk	0:7480abd3b63b	416	if (UARTx == LPC_UART2)
dpslwk	0:7480abd3b63b	417	{
dpslwk	0:7480abd3b63b	418	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	419	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
dpslwk	0:7480abd3b63b	420	}
dpslwk	0:7480abd3b63b	421	#endif
dpslwk	0:7480abd3b63b	422
dpslwk	0:7480abd3b63b	423	#ifdef _UART3
dpslwk	0:7480abd3b63b	424	if (UARTx == LPC_UART3)
dpslwk	0:7480abd3b63b	425	{
dpslwk	0:7480abd3b63b	426	/* Set up clock and power for UART module */
dpslwk	0:7480abd3b63b	427	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
dpslwk	0:7480abd3b63b	428	}
dpslwk	0:7480abd3b63b	429	#endif
dpslwk	0:7480abd3b63b	430	}
dpslwk	0:7480abd3b63b	431
dpslwk	0:7480abd3b63b	432	/***************************************************************************//
dpslwk	0:7480abd3b63b	433	* @brief Fills each UART_InitStruct member with its default value:
dpslwk	0:7480abd3b63b	434	* - 9600 bps
dpslwk	0:7480abd3b63b	435	* - 8-bit data
dpslwk	0:7480abd3b63b	436	* - 1 Stopbit
dpslwk	0:7480abd3b63b	437	* - None Parity
dpslwk	0:7480abd3b63b	438	* @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure
dpslwk	0:7480abd3b63b	439	* which will be initialized.
dpslwk	0:7480abd3b63b	440	* @return None
dpslwk	0:7480abd3b63b	441	*******************************************************************************/
dpslwk	0:7480abd3b63b	442	void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
dpslwk	0:7480abd3b63b	443	{
dpslwk	0:7480abd3b63b	444	UART_InitStruct->Baud_rate = 9600;
dpslwk	0:7480abd3b63b	445	UART_InitStruct->Databits = UART_DATABIT_8;
dpslwk	0:7480abd3b63b	446	UART_InitStruct->Parity = UART_PARITY_NONE;
dpslwk	0:7480abd3b63b	447	UART_InitStruct->Stopbits = UART_STOPBIT_1;
dpslwk	0:7480abd3b63b	448	}
dpslwk	0:7480abd3b63b	449
dpslwk	0:7480abd3b63b	450	/* UART Send/Recieve functions -------------------------------------------------*/
dpslwk	0:7480abd3b63b	451	/*******************************************************************//
dpslwk	0:7480abd3b63b	452	* @brief Transmit a single data through UART peripheral
dpslwk	0:7480abd3b63b	453	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	454	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	455	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	456	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	457	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	458	* @param[in] Data Data to transmit (must be 8-bit long)
dpslwk	0:7480abd3b63b	459	* @return None
dpslwk	0:7480abd3b63b	460	**********************************************************************/
dpslwk	0:7480abd3b63b	461	void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data)
dpslwk	0:7480abd3b63b	462	{
dpslwk	0:7480abd3b63b	463	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	464
dpslwk	0:7480abd3b63b	465	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	466	{
dpslwk	0:7480abd3b63b	467	((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
dpslwk	0:7480abd3b63b	468	}
dpslwk	0:7480abd3b63b	469	else
dpslwk	0:7480abd3b63b	470	{
dpslwk	0:7480abd3b63b	471	UARTx->/RBTHDLR./THR = Data & UART_THR_MASKBIT;
dpslwk	0:7480abd3b63b	472	}
dpslwk	0:7480abd3b63b	473
dpslwk	0:7480abd3b63b	474	}
dpslwk	0:7480abd3b63b	475
dpslwk	0:7480abd3b63b	476
dpslwk	0:7480abd3b63b	477	/*******************************************************************//
dpslwk	0:7480abd3b63b	478	* @brief Receive a single data from UART peripheral
dpslwk	0:7480abd3b63b	479	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	480	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	481	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	482	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	483	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	484	* @return Data received
dpslwk	0:7480abd3b63b	485	**********************************************************************/
dpslwk	0:7480abd3b63b	486	uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx)
dpslwk	0:7480abd3b63b	487	{
dpslwk	0:7480abd3b63b	488	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	489
dpslwk	0:7480abd3b63b	490	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	491	{
dpslwk	0:7480abd3b63b	492	return (((LPC_UART1_TypeDef )UARTx)->/RBTHDLR.*/RBR & UART_RBR_MASKBIT);
dpslwk	0:7480abd3b63b	493	}
dpslwk	0:7480abd3b63b	494	else
dpslwk	0:7480abd3b63b	495	{
dpslwk	0:7480abd3b63b	496	return (UARTx->/RBTHDLR./RBR & UART_RBR_MASKBIT);
dpslwk	0:7480abd3b63b	497	}
dpslwk	0:7480abd3b63b	498	}
dpslwk	0:7480abd3b63b	499
dpslwk	0:7480abd3b63b	500	/*******************************************************************//
dpslwk	0:7480abd3b63b	501	* @brief Send a block of data via UART peripheral
dpslwk	0:7480abd3b63b	502	* @param[in] UARTx Selected UART peripheral used to send data, should be:
dpslwk	0:7480abd3b63b	503	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	504	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	505	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	506	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	507	* @param[in] txbuf Pointer to Transmit buffer
dpslwk	0:7480abd3b63b	508	* @param[in] buflen Length of Transmit buffer
dpslwk	0:7480abd3b63b	509	* @param[in] flag Flag used in UART transfer, should be
dpslwk	0:7480abd3b63b	510	* NONE_BLOCKING or BLOCKING
dpslwk	0:7480abd3b63b	511	* @return Number of bytes sent.
dpslwk	0:7480abd3b63b	512	*
dpslwk	0:7480abd3b63b	513	* Note: when using UART in BLOCKING mode, a time-out condition is used
dpslwk	0:7480abd3b63b	514	* via defined symbol UART_BLOCKING_TIMEOUT.
dpslwk	0:7480abd3b63b	515	**********************************************************************/
dpslwk	0:7480abd3b63b	516	uint32_t UART_Send(LPC_UART_TypeDef UARTx, uint8_t txbuf,
dpslwk	0:7480abd3b63b	517	uint32_t buflen, TRANSFER_BLOCK_Type flag)
dpslwk	0:7480abd3b63b	518	{
dpslwk	0:7480abd3b63b	519	uint32_t bToSend, bSent, timeOut, fifo_cnt;
dpslwk	0:7480abd3b63b	520	uint8_t *pChar = txbuf;
dpslwk	0:7480abd3b63b	521
dpslwk	0:7480abd3b63b	522	bToSend = buflen;
dpslwk	0:7480abd3b63b	523
dpslwk	0:7480abd3b63b	524	// blocking mode
dpslwk	0:7480abd3b63b	525	if (flag == BLOCKING) {
dpslwk	0:7480abd3b63b	526	bSent = 0;
dpslwk	0:7480abd3b63b	527	while (bToSend){
dpslwk	0:7480abd3b63b	528	timeOut = UART_BLOCKING_TIMEOUT;
dpslwk	0:7480abd3b63b	529	// Wait for THR empty with timeout
dpslwk	0:7480abd3b63b	530	while (!(UARTx->LSR & UART_LSR_THRE)) {
dpslwk	0:7480abd3b63b	531	if (timeOut == 0) break;
dpslwk	0:7480abd3b63b	532	timeOut--;
dpslwk	0:7480abd3b63b	533	}
dpslwk	0:7480abd3b63b	534	// Time out!
dpslwk	0:7480abd3b63b	535	if(timeOut == 0) break;
dpslwk	0:7480abd3b63b	536	fifo_cnt = UART_TX_FIFO_SIZE;
dpslwk	0:7480abd3b63b	537	while (fifo_cnt && bToSend){
dpslwk	0:7480abd3b63b	538	UART_SendByte(UARTx, (*pChar++));
dpslwk	0:7480abd3b63b	539	fifo_cnt--;
dpslwk	0:7480abd3b63b	540	bToSend--;
dpslwk	0:7480abd3b63b	541	bSent++;
dpslwk	0:7480abd3b63b	542	}
dpslwk	0:7480abd3b63b	543	}
dpslwk	0:7480abd3b63b	544	}
dpslwk	0:7480abd3b63b	545	// None blocking mode
dpslwk	0:7480abd3b63b	546	else {
dpslwk	0:7480abd3b63b	547	bSent = 0;
dpslwk	0:7480abd3b63b	548	while (bToSend) {
dpslwk	0:7480abd3b63b	549	if (!(UARTx->LSR & UART_LSR_THRE)){
dpslwk	0:7480abd3b63b	550	break;
dpslwk	0:7480abd3b63b	551	}
dpslwk	0:7480abd3b63b	552	fifo_cnt = UART_TX_FIFO_SIZE;
dpslwk	0:7480abd3b63b	553	while (fifo_cnt && bToSend) {
dpslwk	0:7480abd3b63b	554	UART_SendByte(UARTx, (*pChar++));
dpslwk	0:7480abd3b63b	555	bToSend--;
dpslwk	0:7480abd3b63b	556	fifo_cnt--;
dpslwk	0:7480abd3b63b	557	bSent++;
dpslwk	0:7480abd3b63b	558	}
dpslwk	0:7480abd3b63b	559	}
dpslwk	0:7480abd3b63b	560	}
dpslwk	0:7480abd3b63b	561	return bSent;
dpslwk	0:7480abd3b63b	562	}
dpslwk	0:7480abd3b63b	563
dpslwk	0:7480abd3b63b	564	/*******************************************************************//
dpslwk	0:7480abd3b63b	565	* @brief Receive a block of data via UART peripheral
dpslwk	0:7480abd3b63b	566	* @param[in] UARTx Selected UART peripheral used to send data,
dpslwk	0:7480abd3b63b	567	* should be:
dpslwk	0:7480abd3b63b	568	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	569	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	570	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	571	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	572	* @param[out] rxbuf Pointer to Received buffer
dpslwk	0:7480abd3b63b	573	* @param[in] buflen Length of Received buffer
dpslwk	0:7480abd3b63b	574	* @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING
dpslwk	0:7480abd3b63b	575
dpslwk	0:7480abd3b63b	576	* @return Number of bytes received
dpslwk	0:7480abd3b63b	577	*
dpslwk	0:7480abd3b63b	578	* Note: when using UART in BLOCKING mode, a time-out condition is used
dpslwk	0:7480abd3b63b	579	* via defined symbol UART_BLOCKING_TIMEOUT.
dpslwk	0:7480abd3b63b	580	**********************************************************************/
dpslwk	0:7480abd3b63b	581	uint32_t UART_Receive(LPC_UART_TypeDef UARTx, uint8_t rxbuf, \
dpslwk	0:7480abd3b63b	582	uint32_t buflen, TRANSFER_BLOCK_Type flag)
dpslwk	0:7480abd3b63b	583	{
dpslwk	0:7480abd3b63b	584	uint32_t bToRecv, bRecv, timeOut;
dpslwk	0:7480abd3b63b	585	uint8_t *pChar = rxbuf;
dpslwk	0:7480abd3b63b	586
dpslwk	0:7480abd3b63b	587	bToRecv = buflen;
dpslwk	0:7480abd3b63b	588
dpslwk	0:7480abd3b63b	589	// Blocking mode
dpslwk	0:7480abd3b63b	590	if (flag == BLOCKING) {
dpslwk	0:7480abd3b63b	591	bRecv = 0;
dpslwk	0:7480abd3b63b	592	while (bToRecv){
dpslwk	0:7480abd3b63b	593	timeOut = UART_BLOCKING_TIMEOUT;
dpslwk	0:7480abd3b63b	594	while (!(UARTx->LSR & UART_LSR_RDR)){
dpslwk	0:7480abd3b63b	595	if (timeOut == 0) break;
dpslwk	0:7480abd3b63b	596	timeOut--;
dpslwk	0:7480abd3b63b	597	}
dpslwk	0:7480abd3b63b	598	// Time out!
dpslwk	0:7480abd3b63b	599	if(timeOut == 0) break;
dpslwk	0:7480abd3b63b	600	// Get data from the buffer
dpslwk	0:7480abd3b63b	601	(*pChar++) = UART_ReceiveByte(UARTx);
dpslwk	0:7480abd3b63b	602	bToRecv--;
dpslwk	0:7480abd3b63b	603	bRecv++;
dpslwk	0:7480abd3b63b	604	}
dpslwk	0:7480abd3b63b	605	}
dpslwk	0:7480abd3b63b	606	// None blocking mode
dpslwk	0:7480abd3b63b	607	else {
dpslwk	0:7480abd3b63b	608	bRecv = 0;
dpslwk	0:7480abd3b63b	609	while (bToRecv) {
dpslwk	0:7480abd3b63b	610	if (!(UARTx->LSR & UART_LSR_RDR)) {
dpslwk	0:7480abd3b63b	611	break;
dpslwk	0:7480abd3b63b	612	} else {
dpslwk	0:7480abd3b63b	613	(*pChar++) = UART_ReceiveByte(UARTx);
dpslwk	0:7480abd3b63b	614	bRecv++;
dpslwk	0:7480abd3b63b	615	bToRecv--;
dpslwk	0:7480abd3b63b	616	}
dpslwk	0:7480abd3b63b	617	}
dpslwk	0:7480abd3b63b	618	}
dpslwk	0:7480abd3b63b	619	return bRecv;
dpslwk	0:7480abd3b63b	620	}
dpslwk	0:7480abd3b63b	621
dpslwk	0:7480abd3b63b	622	/*******************************************************************//
dpslwk	0:7480abd3b63b	623	* @brief Force BREAK character on UART line, output pin UARTx TXD is
dpslwk	0:7480abd3b63b	624	forced to logic 0.
dpslwk	0:7480abd3b63b	625	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	626	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	627	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	628	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	629	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	630	* @return None
dpslwk	0:7480abd3b63b	631	**********************************************************************/
dpslwk	0:7480abd3b63b	632	void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
dpslwk	0:7480abd3b63b	633	{
dpslwk	0:7480abd3b63b	634	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	635
dpslwk	0:7480abd3b63b	636	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	637	{
dpslwk	0:7480abd3b63b	638	((LPC_UART1_TypeDef *)UARTx)->LCR \|= UART_LCR_BREAK_EN;
dpslwk	0:7480abd3b63b	639	}
dpslwk	0:7480abd3b63b	640	else
dpslwk	0:7480abd3b63b	641	{
dpslwk	0:7480abd3b63b	642	UARTx->LCR \|= UART_LCR_BREAK_EN;
dpslwk	0:7480abd3b63b	643	}
dpslwk	0:7480abd3b63b	644	}
dpslwk	0:7480abd3b63b	645
dpslwk	0:7480abd3b63b	646
dpslwk	0:7480abd3b63b	647	/******************************************************************//
dpslwk	0:7480abd3b63b	648	* @brief Enable or disable specified UART interrupt.
dpslwk	0:7480abd3b63b	649	* @param[in] UARTx UART peripheral selected, should be
dpslwk	0:7480abd3b63b	650	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	651	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	652	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	653	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	654	* @param[in] UARTIntCfg Specifies the interrupt flag,
dpslwk	0:7480abd3b63b	655	* should be one of the following:
dpslwk	0:7480abd3b63b	656	- UART_INTCFG_RBR : RBR Interrupt enable
dpslwk	0:7480abd3b63b	657	- UART_INTCFG_THRE : THR Interrupt enable
dpslwk	0:7480abd3b63b	658	- UART_INTCFG_RLS : RX line status interrupt enable
dpslwk	0:7480abd3b63b	659	- UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)
dpslwk	0:7480abd3b63b	660	- UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)
dpslwk	0:7480abd3b63b	661	- UART_INTCFG_ABEO : Enables the end of auto-baud interrupt
dpslwk	0:7480abd3b63b	662	- UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt
dpslwk	0:7480abd3b63b	663	* @param[in] NewState New state of specified UART interrupt type,
dpslwk	0:7480abd3b63b	664	* should be:
dpslwk	0:7480abd3b63b	665	* - ENALBE: Enable this UART interrupt type.
dpslwk	0:7480abd3b63b	666	* - DISALBE: Disable this UART interrupt type.
dpslwk	0:7480abd3b63b	667	* @return None
dpslwk	0:7480abd3b63b	668	*********************************************************************/
dpslwk	0:7480abd3b63b	669	void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
dpslwk	0:7480abd3b63b	670	{
dpslwk	0:7480abd3b63b	671	uint32_t tmp = 0;
dpslwk	0:7480abd3b63b	672
dpslwk	0:7480abd3b63b	673	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	674	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
dpslwk	0:7480abd3b63b	675
dpslwk	0:7480abd3b63b	676	switch(UARTIntCfg){
dpslwk	0:7480abd3b63b	677	case UART_INTCFG_RBR:
dpslwk	0:7480abd3b63b	678	tmp = UART_IER_RBRINT_EN;
dpslwk	0:7480abd3b63b	679	break;
dpslwk	0:7480abd3b63b	680	case UART_INTCFG_THRE:
dpslwk	0:7480abd3b63b	681	tmp = UART_IER_THREINT_EN;
dpslwk	0:7480abd3b63b	682	break;
dpslwk	0:7480abd3b63b	683	case UART_INTCFG_RLS:
dpslwk	0:7480abd3b63b	684	tmp = UART_IER_RLSINT_EN;
dpslwk	0:7480abd3b63b	685	break;
dpslwk	0:7480abd3b63b	686	case UART1_INTCFG_MS:
dpslwk	0:7480abd3b63b	687	tmp = UART1_IER_MSINT_EN;
dpslwk	0:7480abd3b63b	688	break;
dpslwk	0:7480abd3b63b	689	case UART1_INTCFG_CTS:
dpslwk	0:7480abd3b63b	690	tmp = UART1_IER_CTSINT_EN;
dpslwk	0:7480abd3b63b	691	break;
dpslwk	0:7480abd3b63b	692	case UART_INTCFG_ABEO:
dpslwk	0:7480abd3b63b	693	tmp = UART_IER_ABEOINT_EN;
dpslwk	0:7480abd3b63b	694	break;
dpslwk	0:7480abd3b63b	695	case UART_INTCFG_ABTO:
dpslwk	0:7480abd3b63b	696	tmp = UART_IER_ABTOINT_EN;
dpslwk	0:7480abd3b63b	697	break;
dpslwk	0:7480abd3b63b	698	}
dpslwk	0:7480abd3b63b	699
dpslwk	0:7480abd3b63b	700	if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
dpslwk	0:7480abd3b63b	701	{
dpslwk	0:7480abd3b63b	702	CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) \|\| (PARAM_UART1_INTCFG(UARTIntCfg)));
dpslwk	0:7480abd3b63b	703	}
dpslwk	0:7480abd3b63b	704	else
dpslwk	0:7480abd3b63b	705	{
dpslwk	0:7480abd3b63b	706	CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg));
dpslwk	0:7480abd3b63b	707	}
dpslwk	0:7480abd3b63b	708
dpslwk	0:7480abd3b63b	709	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	710	{
dpslwk	0:7480abd3b63b	711	if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
dpslwk	0:7480abd3b63b	712	{
dpslwk	0:7480abd3b63b	713	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/IER \|= tmp;
dpslwk	0:7480abd3b63b	714	}
dpslwk	0:7480abd3b63b	715	else
dpslwk	0:7480abd3b63b	716	{
dpslwk	0:7480abd3b63b	717	UARTx->/DLIER./IER \|= tmp;
dpslwk	0:7480abd3b63b	718	}
dpslwk	0:7480abd3b63b	719	}
dpslwk	0:7480abd3b63b	720	else
dpslwk	0:7480abd3b63b	721	{
dpslwk	0:7480abd3b63b	722	if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
dpslwk	0:7480abd3b63b	723	{
dpslwk	0:7480abd3b63b	724	((LPC_UART1_TypeDef )UARTx)->/DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK;
dpslwk	0:7480abd3b63b	725	}
dpslwk	0:7480abd3b63b	726	else
dpslwk	0:7480abd3b63b	727	{
dpslwk	0:7480abd3b63b	728	UARTx->/DLIER./IER &= (~tmp) & UART_IER_BITMASK;
dpslwk	0:7480abd3b63b	729	}
dpslwk	0:7480abd3b63b	730	}
dpslwk	0:7480abd3b63b	731	}
dpslwk	0:7480abd3b63b	732
dpslwk	0:7480abd3b63b	733
dpslwk	0:7480abd3b63b	734	/******************************************************************//
dpslwk	0:7480abd3b63b	735	* @brief Get current value of Line Status register in UART peripheral.
dpslwk	0:7480abd3b63b	736	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	737	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	738	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	739	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	740	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	741	* @return Current value of Line Status register in UART peripheral.
dpslwk	0:7480abd3b63b	742	* Note: The return value of this function must be ANDed with each member in
dpslwk	0:7480abd3b63b	743	* UART_LS_Type enumeration to determine current flag status
dpslwk	0:7480abd3b63b	744	* corresponding to each Line status type. Because some flags in
dpslwk	0:7480abd3b63b	745	* Line Status register will be cleared after reading, the next reading
dpslwk	0:7480abd3b63b	746	* Line Status register could not be correct. So this function used to
dpslwk	0:7480abd3b63b	747	* read Line status register in one time only, then the return value
dpslwk	0:7480abd3b63b	748	* used to check all flags.
dpslwk	0:7480abd3b63b	749	*********************************************************************/
dpslwk	0:7480abd3b63b	750	uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
dpslwk	0:7480abd3b63b	751	{
dpslwk	0:7480abd3b63b	752	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	753
dpslwk	0:7480abd3b63b	754	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	755	{
dpslwk	0:7480abd3b63b	756	return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
dpslwk	0:7480abd3b63b	757	}
dpslwk	0:7480abd3b63b	758	else
dpslwk	0:7480abd3b63b	759	{
dpslwk	0:7480abd3b63b	760	return ((UARTx->LSR) & UART_LSR_BITMASK);
dpslwk	0:7480abd3b63b	761	}
dpslwk	0:7480abd3b63b	762	}
dpslwk	0:7480abd3b63b	763
dpslwk	0:7480abd3b63b	764	/******************************************************************//
dpslwk	0:7480abd3b63b	765	* @brief Get Interrupt Identification value
dpslwk	0:7480abd3b63b	766	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	767	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	768	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	769	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	770	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	771	* @return Current value of UART UIIR register in UART peripheral.
dpslwk	0:7480abd3b63b	772	*********************************************************************/
dpslwk	0:7480abd3b63b	773	uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx)
dpslwk	0:7480abd3b63b	774	{
dpslwk	0:7480abd3b63b	775	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	776	return (UARTx->IIR & 0x03CF);
dpslwk	0:7480abd3b63b	777	}
dpslwk	0:7480abd3b63b	778
dpslwk	0:7480abd3b63b	779	/*******************************************************************//
dpslwk	0:7480abd3b63b	780	* @brief Check whether if UART is busy or not
dpslwk	0:7480abd3b63b	781	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	782	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	783	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	784	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	785	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	786	* @return RESET if UART is not busy, otherwise return SET.
dpslwk	0:7480abd3b63b	787	**********************************************************************/
dpslwk	0:7480abd3b63b	788	FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
dpslwk	0:7480abd3b63b	789	{
dpslwk	0:7480abd3b63b	790	if (UARTx->LSR & UART_LSR_TEMT){
dpslwk	0:7480abd3b63b	791	return RESET;
dpslwk	0:7480abd3b63b	792	} else {
dpslwk	0:7480abd3b63b	793	return SET;
dpslwk	0:7480abd3b63b	794	}
dpslwk	0:7480abd3b63b	795	}
dpslwk	0:7480abd3b63b	796
dpslwk	0:7480abd3b63b	797
dpslwk	0:7480abd3b63b	798	/*******************************************************************//
dpslwk	0:7480abd3b63b	799	* @brief Configure FIFO function on selected UART peripheral
dpslwk	0:7480abd3b63b	800	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	801	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	802	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	803	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	804	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	805	* @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that
dpslwk	0:7480abd3b63b	806	* contains specified information about FIFO configuration
dpslwk	0:7480abd3b63b	807	* @return none
dpslwk	0:7480abd3b63b	808	**********************************************************************/
dpslwk	0:7480abd3b63b	809	void UART_FIFOConfig(LPC_UART_TypeDef UARTx, UART_FIFO_CFG_Type FIFOCfg)
dpslwk	0:7480abd3b63b	810	{
dpslwk	0:7480abd3b63b	811	uint8_t tmp = 0;
dpslwk	0:7480abd3b63b	812
dpslwk	0:7480abd3b63b	813	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	814	CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level));
dpslwk	0:7480abd3b63b	815	CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode));
dpslwk	0:7480abd3b63b	816	CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf));
dpslwk	0:7480abd3b63b	817	CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf));
dpslwk	0:7480abd3b63b	818
dpslwk	0:7480abd3b63b	819	tmp \|= UART_FCR_FIFO_EN;
dpslwk	0:7480abd3b63b	820	switch (FIFOCfg->FIFO_Level){
dpslwk	0:7480abd3b63b	821	case UART_FIFO_TRGLEV0:
dpslwk	0:7480abd3b63b	822	tmp \|= UART_FCR_TRG_LEV0;
dpslwk	0:7480abd3b63b	823	break;
dpslwk	0:7480abd3b63b	824	case UART_FIFO_TRGLEV1:
dpslwk	0:7480abd3b63b	825	tmp \|= UART_FCR_TRG_LEV1;
dpslwk	0:7480abd3b63b	826	break;
dpslwk	0:7480abd3b63b	827	case UART_FIFO_TRGLEV2:
dpslwk	0:7480abd3b63b	828	tmp \|= UART_FCR_TRG_LEV2;
dpslwk	0:7480abd3b63b	829	break;
dpslwk	0:7480abd3b63b	830	case UART_FIFO_TRGLEV3:
dpslwk	0:7480abd3b63b	831	default:
dpslwk	0:7480abd3b63b	832	tmp \|= UART_FCR_TRG_LEV3;
dpslwk	0:7480abd3b63b	833	break;
dpslwk	0:7480abd3b63b	834	}
dpslwk	0:7480abd3b63b	835
dpslwk	0:7480abd3b63b	836	if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
dpslwk	0:7480abd3b63b	837	{
dpslwk	0:7480abd3b63b	838	tmp \|= UART_FCR_TX_RS;
dpslwk	0:7480abd3b63b	839	}
dpslwk	0:7480abd3b63b	840	if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
dpslwk	0:7480abd3b63b	841	{
dpslwk	0:7480abd3b63b	842	tmp \|= UART_FCR_RX_RS;
dpslwk	0:7480abd3b63b	843	}
dpslwk	0:7480abd3b63b	844	if (FIFOCfg->FIFO_DMAMode == ENABLE)
dpslwk	0:7480abd3b63b	845	{
dpslwk	0:7480abd3b63b	846	tmp \|= UART_FCR_DMAMODE_SEL;
dpslwk	0:7480abd3b63b	847	}
dpslwk	0:7480abd3b63b	848
dpslwk	0:7480abd3b63b	849
dpslwk	0:7480abd3b63b	850	//write to FIFO control register
dpslwk	0:7480abd3b63b	851	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	852	{
dpslwk	0:7480abd3b63b	853	((LPC_UART1_TypeDef )UARTx)->/IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
dpslwk	0:7480abd3b63b	854	}
dpslwk	0:7480abd3b63b	855	else
dpslwk	0:7480abd3b63b	856	{
dpslwk	0:7480abd3b63b	857	UARTx->/IIFCR./FCR = tmp & UART_FCR_BITMASK;
dpslwk	0:7480abd3b63b	858	}
dpslwk	0:7480abd3b63b	859	}
dpslwk	0:7480abd3b63b	860
dpslwk	0:7480abd3b63b	861	/***************************************************************************//
dpslwk	0:7480abd3b63b	862	* @brief Fills each UART_FIFOInitStruct member with its default value:
dpslwk	0:7480abd3b63b	863	* - FIFO_DMAMode = DISABLE
dpslwk	0:7480abd3b63b	864	* - FIFO_Level = UART_FIFO_TRGLEV0
dpslwk	0:7480abd3b63b	865	* - FIFO_ResetRxBuf = ENABLE
dpslwk	0:7480abd3b63b	866	* - FIFO_ResetTxBuf = ENABLE
dpslwk	0:7480abd3b63b	867	* - FIFO_State = ENABLE
dpslwk	0:7480abd3b63b	868
dpslwk	0:7480abd3b63b	869	* @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
dpslwk	0:7480abd3b63b	870	* which will be initialized.
dpslwk	0:7480abd3b63b	871	* @return None
dpslwk	0:7480abd3b63b	872	*******************************************************************************/
dpslwk	0:7480abd3b63b	873	void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
dpslwk	0:7480abd3b63b	874	{
dpslwk	0:7480abd3b63b	875	UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
dpslwk	0:7480abd3b63b	876	UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
dpslwk	0:7480abd3b63b	877	UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
dpslwk	0:7480abd3b63b	878	UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
dpslwk	0:7480abd3b63b	879	}
dpslwk	0:7480abd3b63b	880
dpslwk	0:7480abd3b63b	881
dpslwk	0:7480abd3b63b	882	/*******************************************************************//
dpslwk	0:7480abd3b63b	883	* @brief Start/Stop Auto Baudrate activity
dpslwk	0:7480abd3b63b	884	* @param[in] UARTx UART peripheral selected, should be
dpslwk	0:7480abd3b63b	885	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	886	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	887	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	888	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	889	* @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that
dpslwk	0:7480abd3b63b	890	* contains specified information about UART
dpslwk	0:7480abd3b63b	891	* auto baudrate configuration
dpslwk	0:7480abd3b63b	892	* @param[in] NewState New State of Auto baudrate activity, should be:
dpslwk	0:7480abd3b63b	893	* - ENABLE: Start this activity
dpslwk	0:7480abd3b63b	894	* - DISABLE: Stop this activity
dpslwk	0:7480abd3b63b	895	* Note: Auto-baudrate mode enable bit will be cleared once this mode
dpslwk	0:7480abd3b63b	896	* completed.
dpslwk	0:7480abd3b63b	897	* @return none
dpslwk	0:7480abd3b63b	898	**********************************************************************/
dpslwk	0:7480abd3b63b	899	void UART_ABCmd(LPC_UART_TypeDef UARTx, UART_AB_CFG_Type ABConfigStruct, \
dpslwk	0:7480abd3b63b	900	FunctionalState NewState)
dpslwk	0:7480abd3b63b	901	{
dpslwk	0:7480abd3b63b	902	uint32_t tmp;
dpslwk	0:7480abd3b63b	903
dpslwk	0:7480abd3b63b	904	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	905	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
dpslwk	0:7480abd3b63b	906
dpslwk	0:7480abd3b63b	907	tmp = 0;
dpslwk	0:7480abd3b63b	908	if (NewState == ENABLE) {
dpslwk	0:7480abd3b63b	909	if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){
dpslwk	0:7480abd3b63b	910	tmp \|= UART_ACR_MODE;
dpslwk	0:7480abd3b63b	911	}
dpslwk	0:7480abd3b63b	912	if (ABConfigStruct->AutoRestart == ENABLE){
dpslwk	0:7480abd3b63b	913	tmp \|= UART_ACR_AUTO_RESTART;
dpslwk	0:7480abd3b63b	914	}
dpslwk	0:7480abd3b63b	915	}
dpslwk	0:7480abd3b63b	916
dpslwk	0:7480abd3b63b	917	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	918	{
dpslwk	0:7480abd3b63b	919	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	920	{
dpslwk	0:7480abd3b63b	921	// Clear DLL and DLM value
dpslwk	0:7480abd3b63b	922	((LPC_UART1_TypeDef *)UARTx)->LCR \|= UART_LCR_DLAB_EN;
dpslwk	0:7480abd3b63b	923	((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
dpslwk	0:7480abd3b63b	924	((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
dpslwk	0:7480abd3b63b	925	((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
dpslwk	0:7480abd3b63b	926	// FDR value must be reset to default value
dpslwk	0:7480abd3b63b	927	((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
dpslwk	0:7480abd3b63b	928	((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START \| tmp;
dpslwk	0:7480abd3b63b	929	}
dpslwk	0:7480abd3b63b	930	else
dpslwk	0:7480abd3b63b	931	{
dpslwk	0:7480abd3b63b	932	((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
dpslwk	0:7480abd3b63b	933	}
dpslwk	0:7480abd3b63b	934	}
dpslwk	0:7480abd3b63b	935	else
dpslwk	0:7480abd3b63b	936	{
dpslwk	0:7480abd3b63b	937	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	938	{
dpslwk	0:7480abd3b63b	939	// Clear DLL and DLM value
dpslwk	0:7480abd3b63b	940	UARTx->LCR \|= UART_LCR_DLAB_EN;
dpslwk	0:7480abd3b63b	941	UARTx->DLL = 0;
dpslwk	0:7480abd3b63b	942	UARTx->DLM = 0;
dpslwk	0:7480abd3b63b	943	UARTx->LCR &= ~UART_LCR_DLAB_EN;
dpslwk	0:7480abd3b63b	944	// FDR value must be reset to default value
dpslwk	0:7480abd3b63b	945	UARTx->FDR = 0x10;
dpslwk	0:7480abd3b63b	946	UARTx->ACR = UART_ACR_START \| tmp;
dpslwk	0:7480abd3b63b	947	}
dpslwk	0:7480abd3b63b	948	else
dpslwk	0:7480abd3b63b	949	{
dpslwk	0:7480abd3b63b	950	UARTx->ACR = 0;
dpslwk	0:7480abd3b63b	951	}
dpslwk	0:7480abd3b63b	952	}
dpslwk	0:7480abd3b63b	953	}
dpslwk	0:7480abd3b63b	954
dpslwk	0:7480abd3b63b	955	/*******************************************************************//
dpslwk	0:7480abd3b63b	956	* @brief Clear Autobaud Interrupt Pending
dpslwk	0:7480abd3b63b	957	* @param[in] UARTx UART peripheral selected, should be
dpslwk	0:7480abd3b63b	958	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	959	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	960	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	961	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	962	* @param[in] ABIntType type of auto-baud interrupt, should be:
dpslwk	0:7480abd3b63b	963	* - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
dpslwk	0:7480abd3b63b	964	* - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
dpslwk	0:7480abd3b63b	965	* @return none
dpslwk	0:7480abd3b63b	966	**********************************************************************/
dpslwk	0:7480abd3b63b	967	void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType)
dpslwk	0:7480abd3b63b	968	{
dpslwk	0:7480abd3b63b	969	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	970	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	971	{
dpslwk	0:7480abd3b63b	972	UARTx->ACR \|= ABIntType;
dpslwk	0:7480abd3b63b	973	}
dpslwk	0:7480abd3b63b	974	else
dpslwk	0:7480abd3b63b	975	UARTx->ACR \|= ABIntType;
dpslwk	0:7480abd3b63b	976	}
dpslwk	0:7480abd3b63b	977
dpslwk	0:7480abd3b63b	978	/*******************************************************************//
dpslwk	0:7480abd3b63b	979	* @brief Enable/Disable transmission on UART TxD pin
dpslwk	0:7480abd3b63b	980	* @param[in] UARTx UART peripheral selected, should be:
dpslwk	0:7480abd3b63b	981	* - LPC_UART0: UART0 peripheral
dpslwk	0:7480abd3b63b	982	* - LPC_UART1: UART1 peripheral
dpslwk	0:7480abd3b63b	983	* - LPC_UART2: UART2 peripheral
dpslwk	0:7480abd3b63b	984	* - LPC_UART3: UART3 peripheral
dpslwk	0:7480abd3b63b	985	* @param[in] NewState New State of Tx transmission function, should be:
dpslwk	0:7480abd3b63b	986	* - ENABLE: Enable this function
dpslwk	0:7480abd3b63b	987	- DISABLE: Disable this function
dpslwk	0:7480abd3b63b	988	* @return none
dpslwk	0:7480abd3b63b	989	**********************************************************************/
dpslwk	0:7480abd3b63b	990	void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
dpslwk	0:7480abd3b63b	991	{
dpslwk	0:7480abd3b63b	992	CHECK_PARAM(PARAM_UARTx(UARTx));
dpslwk	0:7480abd3b63b	993	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
dpslwk	0:7480abd3b63b	994
dpslwk	0:7480abd3b63b	995	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	996	{
dpslwk	0:7480abd3b63b	997	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	998	{
dpslwk	0:7480abd3b63b	999	((LPC_UART1_TypeDef *)UARTx)->TER \|= UART_TER_TXEN;
dpslwk	0:7480abd3b63b	1000	}
dpslwk	0:7480abd3b63b	1001	else
dpslwk	0:7480abd3b63b	1002	{
dpslwk	0:7480abd3b63b	1003	UARTx->TER \|= UART_TER_TXEN;
dpslwk	0:7480abd3b63b	1004	}
dpslwk	0:7480abd3b63b	1005	}
dpslwk	0:7480abd3b63b	1006	else
dpslwk	0:7480abd3b63b	1007	{
dpslwk	0:7480abd3b63b	1008	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
dpslwk	0:7480abd3b63b	1009	{
dpslwk	0:7480abd3b63b	1010	((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
dpslwk	0:7480abd3b63b	1011	}
dpslwk	0:7480abd3b63b	1012	else
dpslwk	0:7480abd3b63b	1013	{
dpslwk	0:7480abd3b63b	1014	UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
dpslwk	0:7480abd3b63b	1015	}
dpslwk	0:7480abd3b63b	1016	}
dpslwk	0:7480abd3b63b	1017	}
dpslwk	0:7480abd3b63b	1018
dpslwk	0:7480abd3b63b	1019	/* UART IrDA functions ---------------------------------------------------*/
dpslwk	0:7480abd3b63b	1020
dpslwk	0:7480abd3b63b	1021	#ifdef _UART3
dpslwk	0:7480abd3b63b	1022
dpslwk	0:7480abd3b63b	1023	/*******************************************************************//
dpslwk	0:7480abd3b63b	1024	* @brief Enable or disable inverting serial input function of IrDA
dpslwk	0:7480abd3b63b	1025	* on UART peripheral.
dpslwk	0:7480abd3b63b	1026	* @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
dpslwk	0:7480abd3b63b	1027	* @param[in] NewState New state of inverting serial input, should be:
dpslwk	0:7480abd3b63b	1028	* - ENABLE: Enable this function.
dpslwk	0:7480abd3b63b	1029	* - DISABLE: Disable this function.
dpslwk	0:7480abd3b63b	1030	* @return none
dpslwk	0:7480abd3b63b	1031	**********************************************************************/
dpslwk	0:7480abd3b63b	1032	void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
dpslwk	0:7480abd3b63b	1033	{
dpslwk	0:7480abd3b63b	1034	CHECK_PARAM(PARAM_UART_IrDA(UARTx));
dpslwk	0:7480abd3b63b	1035	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
dpslwk	0:7480abd3b63b	1036
dpslwk	0:7480abd3b63b	1037	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	1038	{
dpslwk	0:7480abd3b63b	1039	UARTx->ICR \|= UART_ICR_IRDAINV;
dpslwk	0:7480abd3b63b	1040	}
dpslwk	0:7480abd3b63b	1041	else if (NewState == DISABLE)
dpslwk	0:7480abd3b63b	1042	{
dpslwk	0:7480abd3b63b	1043	UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
dpslwk	0:7480abd3b63b	1044	}
dpslwk	0:7480abd3b63b	1045	}
dpslwk	0:7480abd3b63b	1046
dpslwk	0:7480abd3b63b	1047
dpslwk	0:7480abd3b63b	1048	/*******************************************************************//
dpslwk	0:7480abd3b63b	1049	* @brief Enable or disable IrDA function on UART peripheral.
dpslwk	0:7480abd3b63b	1050	* @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
dpslwk	0:7480abd3b63b	1051	* @param[in] NewState New state of IrDA function, should be:
dpslwk	0:7480abd3b63b	1052	* - ENABLE: Enable this function.
dpslwk	0:7480abd3b63b	1053	* - DISABLE: Disable this function.
dpslwk	0:7480abd3b63b	1054	* @return none
dpslwk	0:7480abd3b63b	1055	**********************************************************************/
dpslwk	0:7480abd3b63b	1056	void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
dpslwk	0:7480abd3b63b	1057	{
dpslwk	0:7480abd3b63b	1058	CHECK_PARAM(PARAM_UART_IrDA(UARTx));
dpslwk	0:7480abd3b63b	1059	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
dpslwk	0:7480abd3b63b	1060
dpslwk	0:7480abd3b63b	1061	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	1062	{
dpslwk	0:7480abd3b63b	1063	UARTx->ICR \|= UART_ICR_IRDAEN;
dpslwk	0:7480abd3b63b	1064	}
dpslwk	0:7480abd3b63b	1065	else
dpslwk	0:7480abd3b63b	1066	{
dpslwk	0:7480abd3b63b	1067	UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
dpslwk	0:7480abd3b63b	1068	}
dpslwk	0:7480abd3b63b	1069	}
dpslwk	0:7480abd3b63b	1070
dpslwk	0:7480abd3b63b	1071
dpslwk	0:7480abd3b63b	1072	/*******************************************************************//
dpslwk	0:7480abd3b63b	1073	* @brief Configure Pulse divider for IrDA function on UART peripheral.
dpslwk	0:7480abd3b63b	1074	* @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
dpslwk	0:7480abd3b63b	1075	* @param[in] PulseDiv Pulse Divider value from Peripheral clock,
dpslwk	0:7480abd3b63b	1076	* should be one of the following:
dpslwk	0:7480abd3b63b	1077	- UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk
dpslwk	0:7480abd3b63b	1078	- UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk
dpslwk	0:7480abd3b63b	1079	- UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk
dpslwk	0:7480abd3b63b	1080	- UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk
dpslwk	0:7480abd3b63b	1081	- UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk
dpslwk	0:7480abd3b63b	1082	- UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk
dpslwk	0:7480abd3b63b	1083	- UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
dpslwk	0:7480abd3b63b	1084	- UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
dpslwk	0:7480abd3b63b	1085
dpslwk	0:7480abd3b63b	1086	* @return none
dpslwk	0:7480abd3b63b	1087	**********************************************************************/
dpslwk	0:7480abd3b63b	1088	void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
dpslwk	0:7480abd3b63b	1089	{
dpslwk	0:7480abd3b63b	1090	uint32_t tmp, tmp1;
dpslwk	0:7480abd3b63b	1091	CHECK_PARAM(PARAM_UART_IrDA(UARTx));
dpslwk	0:7480abd3b63b	1092	CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv));
dpslwk	0:7480abd3b63b	1093
dpslwk	0:7480abd3b63b	1094	tmp1 = UART_ICR_PULSEDIV(PulseDiv);
dpslwk	0:7480abd3b63b	1095	tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7));
dpslwk	0:7480abd3b63b	1096	tmp \|= tmp1 \| UART_ICR_FIXPULSE_EN;
dpslwk	0:7480abd3b63b	1097	UARTx->ICR = tmp & UART_ICR_BITMASK;
dpslwk	0:7480abd3b63b	1098	}
dpslwk	0:7480abd3b63b	1099
dpslwk	0:7480abd3b63b	1100	#endif
dpslwk	0:7480abd3b63b	1101
dpslwk	0:7480abd3b63b	1102
dpslwk	0:7480abd3b63b	1103	/* UART1 FullModem function ---------------------------------------------*/
dpslwk	0:7480abd3b63b	1104
dpslwk	0:7480abd3b63b	1105	#ifdef _UART1
dpslwk	0:7480abd3b63b	1106
dpslwk	0:7480abd3b63b	1107	/*******************************************************************//
dpslwk	0:7480abd3b63b	1108	* @brief Force pin DTR/RTS corresponding to given state (Full modem mode)
dpslwk	0:7480abd3b63b	1109	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1110	* @param[in] Pin Pin that NewState will be applied to, should be:
dpslwk	0:7480abd3b63b	1111	* - UART1_MODEM_PIN_DTR: DTR pin.
dpslwk	0:7480abd3b63b	1112	* - UART1_MODEM_PIN_RTS: RTS pin.
dpslwk	0:7480abd3b63b	1113	* @param[in] NewState New State of DTR/RTS pin, should be:
dpslwk	0:7480abd3b63b	1114	* - INACTIVE: Force the pin to inactive signal.
dpslwk	0:7480abd3b63b	1115	- ACTIVE: Force the pin to active signal.
dpslwk	0:7480abd3b63b	1116	* @return none
dpslwk	0:7480abd3b63b	1117	**********************************************************************/
dpslwk	0:7480abd3b63b	1118	void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
dpslwk	0:7480abd3b63b	1119	UART1_SignalState NewState)
dpslwk	0:7480abd3b63b	1120	{
dpslwk	0:7480abd3b63b	1121	uint8_t tmp = 0;
dpslwk	0:7480abd3b63b	1122
dpslwk	0:7480abd3b63b	1123	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
dpslwk	0:7480abd3b63b	1124	CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin));
dpslwk	0:7480abd3b63b	1125	CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState));
dpslwk	0:7480abd3b63b	1126
dpslwk	0:7480abd3b63b	1127	switch (Pin){
dpslwk	0:7480abd3b63b	1128	case UART1_MODEM_PIN_DTR:
dpslwk	0:7480abd3b63b	1129	tmp = UART1_MCR_DTR_CTRL;
dpslwk	0:7480abd3b63b	1130	break;
dpslwk	0:7480abd3b63b	1131	case UART1_MODEM_PIN_RTS:
dpslwk	0:7480abd3b63b	1132	tmp = UART1_MCR_RTS_CTRL;
dpslwk	0:7480abd3b63b	1133	break;
dpslwk	0:7480abd3b63b	1134	default:
dpslwk	0:7480abd3b63b	1135	break;
dpslwk	0:7480abd3b63b	1136	}
dpslwk	0:7480abd3b63b	1137
dpslwk	0:7480abd3b63b	1138	if (NewState == ACTIVE){
dpslwk	0:7480abd3b63b	1139	UARTx->MCR \|= tmp;
dpslwk	0:7480abd3b63b	1140	} else {
dpslwk	0:7480abd3b63b	1141	UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
dpslwk	0:7480abd3b63b	1142	}
dpslwk	0:7480abd3b63b	1143	}
dpslwk	0:7480abd3b63b	1144
dpslwk	0:7480abd3b63b	1145
dpslwk	0:7480abd3b63b	1146	/*******************************************************************//
dpslwk	0:7480abd3b63b	1147	* @brief Configure Full Modem mode for UART peripheral
dpslwk	0:7480abd3b63b	1148	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1149	* @param[in] Mode Full Modem mode, should be:
dpslwk	0:7480abd3b63b	1150	* - UART1_MODEM_MODE_LOOPBACK: Loop back mode.
dpslwk	0:7480abd3b63b	1151	* - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
dpslwk	0:7480abd3b63b	1152	* - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
dpslwk	0:7480abd3b63b	1153	* @param[in] NewState New State of this mode, should be:
dpslwk	0:7480abd3b63b	1154	* - ENABLE: Enable this mode.
dpslwk	0:7480abd3b63b	1155	- DISABLE: Disable this mode.
dpslwk	0:7480abd3b63b	1156	* @return none
dpslwk	0:7480abd3b63b	1157	**********************************************************************/
dpslwk	0:7480abd3b63b	1158	void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
dpslwk	0:7480abd3b63b	1159	FunctionalState NewState)
dpslwk	0:7480abd3b63b	1160	{
dpslwk	0:7480abd3b63b	1161	uint8_t tmp = 0;
dpslwk	0:7480abd3b63b	1162
dpslwk	0:7480abd3b63b	1163	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
dpslwk	0:7480abd3b63b	1164	CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode));
dpslwk	0:7480abd3b63b	1165	CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
dpslwk	0:7480abd3b63b	1166
dpslwk	0:7480abd3b63b	1167	switch(Mode){
dpslwk	0:7480abd3b63b	1168	case UART1_MODEM_MODE_LOOPBACK:
dpslwk	0:7480abd3b63b	1169	tmp = UART1_MCR_LOOPB_EN;
dpslwk	0:7480abd3b63b	1170	break;
dpslwk	0:7480abd3b63b	1171	case UART1_MODEM_MODE_AUTO_RTS:
dpslwk	0:7480abd3b63b	1172	tmp = UART1_MCR_AUTO_RTS_EN;
dpslwk	0:7480abd3b63b	1173	break;
dpslwk	0:7480abd3b63b	1174	case UART1_MODEM_MODE_AUTO_CTS:
dpslwk	0:7480abd3b63b	1175	tmp = UART1_MCR_AUTO_CTS_EN;
dpslwk	0:7480abd3b63b	1176	break;
dpslwk	0:7480abd3b63b	1177	default:
dpslwk	0:7480abd3b63b	1178	break;
dpslwk	0:7480abd3b63b	1179	}
dpslwk	0:7480abd3b63b	1180
dpslwk	0:7480abd3b63b	1181	if (NewState == ENABLE)
dpslwk	0:7480abd3b63b	1182	{
dpslwk	0:7480abd3b63b	1183	UARTx->MCR \|= tmp;
dpslwk	0:7480abd3b63b	1184	}
dpslwk	0:7480abd3b63b	1185	else
dpslwk	0:7480abd3b63b	1186	{
dpslwk	0:7480abd3b63b	1187	UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
dpslwk	0:7480abd3b63b	1188	}
dpslwk	0:7480abd3b63b	1189	}
dpslwk	0:7480abd3b63b	1190
dpslwk	0:7480abd3b63b	1191
dpslwk	0:7480abd3b63b	1192	/*******************************************************************//
dpslwk	0:7480abd3b63b	1193	* @brief Get current status of modem status register
dpslwk	0:7480abd3b63b	1194	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1195	* @return Current value of modem status register
dpslwk	0:7480abd3b63b	1196	* Note: The return value of this function must be ANDed with each member
dpslwk	0:7480abd3b63b	1197	* UART_MODEM_STAT_type enumeration to determine current flag status
dpslwk	0:7480abd3b63b	1198	* corresponding to each modem flag status. Because some flags in
dpslwk	0:7480abd3b63b	1199	* modem status register will be cleared after reading, the next reading
dpslwk	0:7480abd3b63b	1200	* modem register could not be correct. So this function used to
dpslwk	0:7480abd3b63b	1201	* read modem status register in one time only, then the return value
dpslwk	0:7480abd3b63b	1202	* used to check all flags.
dpslwk	0:7480abd3b63b	1203	**********************************************************************/
dpslwk	0:7480abd3b63b	1204	uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
dpslwk	0:7480abd3b63b	1205	{
dpslwk	0:7480abd3b63b	1206	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
dpslwk	0:7480abd3b63b	1207	return ((UARTx->MSR) & UART1_MSR_BITMASK);
dpslwk	0:7480abd3b63b	1208	}
dpslwk	0:7480abd3b63b	1209
dpslwk	0:7480abd3b63b	1210
dpslwk	0:7480abd3b63b	1211	/* UART RS485 functions --------------------------------------------------------------*/
dpslwk	0:7480abd3b63b	1212
dpslwk	0:7480abd3b63b	1213	/*******************************************************************//
dpslwk	0:7480abd3b63b	1214	* @brief Configure UART peripheral in RS485 mode according to the specified
dpslwk	0:7480abd3b63b	1215	* parameters in the RS485ConfigStruct.
dpslwk	0:7480abd3b63b	1216	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1217	* @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
dpslwk	0:7480abd3b63b	1218	* that contains the configuration information for specified UART
dpslwk	0:7480abd3b63b	1219	* in RS485 mode.
dpslwk	0:7480abd3b63b	1220	* @return None
dpslwk	0:7480abd3b63b	1221	**********************************************************************/
dpslwk	0:7480abd3b63b	1222	void UART_RS485Config(LPC_UART1_TypeDef UARTx, UART1_RS485_CTRLCFG_Type RS485ConfigStruct)
dpslwk	0:7480abd3b63b	1223	{
dpslwk	0:7480abd3b63b	1224	uint32_t tmp;
dpslwk	0:7480abd3b63b	1225
dpslwk	0:7480abd3b63b	1226	CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
dpslwk	0:7480abd3b63b	1227	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State));
dpslwk	0:7480abd3b63b	1228	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State));
dpslwk	0:7480abd3b63b	1229	CHECK_PARAM(PARAM_UART1_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue));
dpslwk	0:7480abd3b63b	1230	CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level));
dpslwk	0:7480abd3b63b	1231	CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin));
dpslwk	0:7480abd3b63b	1232	CHECK_PARAM(PARAM_UART1_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue));
dpslwk	0:7480abd3b63b	1233	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State));
dpslwk	0:7480abd3b63b	1234	CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State));
dpslwk	0:7480abd3b63b	1235
dpslwk	0:7480abd3b63b	1236	tmp = 0;
dpslwk	0:7480abd3b63b	1237	// If Auto Direction Control is enabled - This function is used in Master mode
dpslwk	0:7480abd3b63b	1238	if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
dpslwk	0:7480abd3b63b	1239	{
dpslwk	0:7480abd3b63b	1240	tmp \|= UART1_RS485CTRL_DCTRL_EN;
dpslwk	0:7480abd3b63b	1241
dpslwk	0:7480abd3b63b	1242	// Set polar
dpslwk	0:7480abd3b63b	1243	if (RS485ConfigStruct->DirCtrlPol_Level == SET)
dpslwk	0:7480abd3b63b	1244	{
dpslwk	0:7480abd3b63b	1245	tmp \|= UART1_RS485CTRL_OINV_1;
dpslwk	0:7480abd3b63b	1246	}
dpslwk	0:7480abd3b63b	1247
dpslwk	0:7480abd3b63b	1248	// Set pin according to
dpslwk	0:7480abd3b63b	1249	if (RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
dpslwk	0:7480abd3b63b	1250	{
dpslwk	0:7480abd3b63b	1251	tmp \|= UART1_RS485CTRL_SEL_DTR;
dpslwk	0:7480abd3b63b	1252	}
dpslwk	0:7480abd3b63b	1253
dpslwk	0:7480abd3b63b	1254	// Fill delay time
dpslwk	0:7480abd3b63b	1255	UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
dpslwk	0:7480abd3b63b	1256	}
dpslwk	0:7480abd3b63b	1257
dpslwk	0:7480abd3b63b	1258	// MultiDrop mode is enable
dpslwk	0:7480abd3b63b	1259	if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
dpslwk	0:7480abd3b63b	1260	{
dpslwk	0:7480abd3b63b	1261	tmp \|= UART1_RS485CTRL_NMM_EN;
dpslwk	0:7480abd3b63b	1262	}
dpslwk	0:7480abd3b63b	1263
dpslwk	0:7480abd3b63b	1264	// Auto Address Detect function
dpslwk	0:7480abd3b63b	1265	if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
dpslwk	0:7480abd3b63b	1266	{
dpslwk	0:7480abd3b63b	1267	tmp \|= UART1_RS485CTRL_AADEN;
dpslwk	0:7480abd3b63b	1268	// Fill Match Address
dpslwk	0:7480abd3b63b	1269	UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
dpslwk	0:7480abd3b63b	1270	}
dpslwk	0:7480abd3b63b	1271
dpslwk	0:7480abd3b63b	1272
dpslwk	0:7480abd3b63b	1273	// Receiver is disable
dpslwk	0:7480abd3b63b	1274	if (RS485ConfigStruct->Rx_State == DISABLE)
dpslwk	0:7480abd3b63b	1275	{
dpslwk	0:7480abd3b63b	1276	tmp \|= UART1_RS485CTRL_RX_DIS;
dpslwk	0:7480abd3b63b	1277	}
dpslwk	0:7480abd3b63b	1278
dpslwk	0:7480abd3b63b	1279	// write back to RS485 control register
dpslwk	0:7480abd3b63b	1280	UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
dpslwk	0:7480abd3b63b	1281
dpslwk	0:7480abd3b63b	1282	// Enable Parity function and leave parity in stick '0' parity as default
dpslwk	0:7480abd3b63b	1283	UARTx->LCR \|= (UART_LCR_PARITY_F_0 \| UART_LCR_PARITY_EN);
dpslwk	0:7480abd3b63b	1284	}
dpslwk	0:7480abd3b63b	1285
dpslwk	0:7480abd3b63b	1286	/*******************************************************************//
dpslwk	0:7480abd3b63b	1287	* @brief Enable/Disable receiver in RS485 module in UART1
dpslwk	0:7480abd3b63b	1288	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1289	* @param[in] NewState New State of command, should be:
dpslwk	0:7480abd3b63b	1290	* - ENABLE: Enable this function.
dpslwk	0:7480abd3b63b	1291	* - DISABLE: Disable this function.
dpslwk	0:7480abd3b63b	1292	* @return None
dpslwk	0:7480abd3b63b	1293	**********************************************************************/
dpslwk	0:7480abd3b63b	1294	void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState)
dpslwk	0:7480abd3b63b	1295	{
dpslwk	0:7480abd3b63b	1296	if (NewState == ENABLE){
dpslwk	0:7480abd3b63b	1297	UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
dpslwk	0:7480abd3b63b	1298	} else {
dpslwk	0:7480abd3b63b	1299	UARTx->RS485CTRL \|= UART1_RS485CTRL_RX_DIS;
dpslwk	0:7480abd3b63b	1300	}
dpslwk	0:7480abd3b63b	1301	}
dpslwk	0:7480abd3b63b	1302
dpslwk	0:7480abd3b63b	1303	/*******************************************************************//
dpslwk	0:7480abd3b63b	1304	* @brief Send data on RS485 bus with specified parity stick value (9-bit mode).
dpslwk	0:7480abd3b63b	1305	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1306	* @param[in] pDatFrm Pointer to data frame.
dpslwk	0:7480abd3b63b	1307	* @param[in] size Size of data.
dpslwk	0:7480abd3b63b	1308	* @param[in] ParityStick Parity Stick value, should be 0 or 1.
dpslwk	0:7480abd3b63b	1309	* @return None
dpslwk	0:7480abd3b63b	1310	**********************************************************************/
dpslwk	0:7480abd3b63b	1311	uint32_t UART_RS485Send(LPC_UART1_TypeDef UARTx, uint8_t pDatFrm, \
dpslwk	0:7480abd3b63b	1312	uint32_t size, uint8_t ParityStick)
dpslwk	0:7480abd3b63b	1313	{
dpslwk	0:7480abd3b63b	1314	uint8_t tmp, save;
dpslwk	0:7480abd3b63b	1315	uint32_t cnt;
dpslwk	0:7480abd3b63b	1316
dpslwk	0:7480abd3b63b	1317	if (ParityStick){
dpslwk	0:7480abd3b63b	1318	save = tmp = UARTx->LCR & UART_LCR_BITMASK;
dpslwk	0:7480abd3b63b	1319	tmp &= ~(UART_LCR_PARITY_EVEN);
dpslwk	0:7480abd3b63b	1320	UARTx->LCR = tmp;
dpslwk	0:7480abd3b63b	1321	cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
dpslwk	0:7480abd3b63b	1322	while (!(UARTx->LSR & UART_LSR_TEMT));
dpslwk	0:7480abd3b63b	1323	UARTx->LCR = save;
dpslwk	0:7480abd3b63b	1324	} else {
dpslwk	0:7480abd3b63b	1325	cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
dpslwk	0:7480abd3b63b	1326	while (!(UARTx->LSR & UART_LSR_TEMT));
dpslwk	0:7480abd3b63b	1327	}
dpslwk	0:7480abd3b63b	1328	return cnt;
dpslwk	0:7480abd3b63b	1329	}
dpslwk	0:7480abd3b63b	1330
dpslwk	0:7480abd3b63b	1331	/*******************************************************************//
dpslwk	0:7480abd3b63b	1332	* @brief Send Slave address frames on RS485 bus.
dpslwk	0:7480abd3b63b	1333	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1334	* @param[in] SlvAddr Slave Address.
dpslwk	0:7480abd3b63b	1335	* @return None
dpslwk	0:7480abd3b63b	1336	**********************************************************************/
dpslwk	0:7480abd3b63b	1337	void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr)
dpslwk	0:7480abd3b63b	1338	{
dpslwk	0:7480abd3b63b	1339	UART_RS485Send(UARTx, &SlvAddr, 1, 1);
dpslwk	0:7480abd3b63b	1340	}
dpslwk	0:7480abd3b63b	1341
dpslwk	0:7480abd3b63b	1342	/*******************************************************************//
dpslwk	0:7480abd3b63b	1343	* @brief Send Data frames on RS485 bus.
dpslwk	0:7480abd3b63b	1344	* @param[in] UARTx LPC_UART1 (only)
dpslwk	0:7480abd3b63b	1345	* @param[in] pData Pointer to data to be sent.
dpslwk	0:7480abd3b63b	1346	* @param[in] size Size of data frame to be sent.
dpslwk	0:7480abd3b63b	1347	* @return None
dpslwk	0:7480abd3b63b	1348	**********************************************************************/
dpslwk	0:7480abd3b63b	1349	uint32_t UART_RS485SendData(LPC_UART1_TypeDef UARTx, uint8_t pData, uint32_t size)
dpslwk	0:7480abd3b63b	1350	{
dpslwk	0:7480abd3b63b	1351	return (UART_RS485Send(UARTx, pData, size, 0));
dpslwk	0:7480abd3b63b	1352	}
dpslwk	0:7480abd3b63b	1353
dpslwk	0:7480abd3b63b	1354	#endif /* _UART1 */
dpslwk	0:7480abd3b63b	1355
dpslwk	0:7480abd3b63b	1356	#endif /* _UART */
dpslwk	0:7480abd3b63b	1357
dpslwk	0:7480abd3b63b	1358	/**
dpslwk	0:7480abd3b63b	1359	* @}
dpslwk	0:7480abd3b63b	1360	*/
dpslwk	0:7480abd3b63b	1361
dpslwk	0:7480abd3b63b	1362	/**
dpslwk	0:7480abd3b63b	1363	* @}
dpslwk	0:7480abd3b63b	1364	*/
dpslwk	0:7480abd3b63b	1365	/* --------------------------------- End Of File ------------------------------ */
dpslwk	0:7480abd3b63b	1366

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	30 Sep 2010
Imports:	234
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	6

lpc17xx_uart.c@0:7480abd3b63b, 2010-09-30 (annotated)

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