Julien Kern / mbed

mbed library

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_pit.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pit.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_PIT_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_PIT_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 PIT
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Periodic Interrupt Timer
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_PIT_MCR - PIT Module Control Register
bogdanm 82:6473597d706e 33 * - HW_PIT_LDVALn - Timer Load Value Register
bogdanm 82:6473597d706e 34 * - HW_PIT_CVALn - Current Timer Value Register
bogdanm 82:6473597d706e 35 * - HW_PIT_TCTRLn - Timer Control Register
bogdanm 82:6473597d706e 36 * - HW_PIT_TFLGn - Timer Flag Register
bogdanm 82:6473597d706e 37 *
bogdanm 82:6473597d706e 38 * - hw_pit_t - Struct containing all module registers.
bogdanm 82:6473597d706e 39 */
bogdanm 82:6473597d706e 40
bogdanm 82:6473597d706e 41 //! @name Module base addresses
bogdanm 82:6473597d706e 42 //@{
bogdanm 82:6473597d706e 43 #ifndef REGS_PIT_BASE
bogdanm 82:6473597d706e 44 #define HW_PIT_INSTANCE_COUNT (1U) //!< Number of instances of the PIT module.
bogdanm 82:6473597d706e 45 #define REGS_PIT_BASE (0x40037000U) //!< Base address for PIT.
bogdanm 82:6473597d706e 46 #endif
bogdanm 82:6473597d706e 47 //@}
bogdanm 82:6473597d706e 48
bogdanm 82:6473597d706e 49 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 50 // HW_PIT_MCR - PIT Module Control Register
bogdanm 82:6473597d706e 51 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 52
bogdanm 82:6473597d706e 53 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 54 /*!
bogdanm 82:6473597d706e 55 * @brief HW_PIT_MCR - PIT Module Control Register (RW)
bogdanm 82:6473597d706e 56 *
bogdanm 82:6473597d706e 57 * Reset value: 0x00000006U
bogdanm 82:6473597d706e 58 *
bogdanm 82:6473597d706e 59 * This register enables or disables the PIT timer clocks and controls the
bogdanm 82:6473597d706e 60 * timers when the PIT enters the Debug mode.
bogdanm 82:6473597d706e 61 */
bogdanm 82:6473597d706e 62 typedef union _hw_pit_mcr
bogdanm 82:6473597d706e 63 {
bogdanm 82:6473597d706e 64 uint32_t U;
bogdanm 82:6473597d706e 65 struct _hw_pit_mcr_bitfields
bogdanm 82:6473597d706e 66 {
bogdanm 82:6473597d706e 67 uint32_t FRZ : 1; //!< [0] Freeze
bogdanm 82:6473597d706e 68 uint32_t MDIS : 1; //!< [1] Module Disable - (PIT section)
bogdanm 82:6473597d706e 69 uint32_t RESERVED0 : 30; //!< [31:2]
bogdanm 82:6473597d706e 70 } B;
bogdanm 82:6473597d706e 71 } hw_pit_mcr_t;
bogdanm 82:6473597d706e 72 #endif
bogdanm 82:6473597d706e 73
bogdanm 82:6473597d706e 74 /*!
bogdanm 82:6473597d706e 75 * @name Constants and macros for entire PIT_MCR register
bogdanm 82:6473597d706e 76 */
bogdanm 82:6473597d706e 77 //@{
bogdanm 82:6473597d706e 78 #define HW_PIT_MCR_ADDR (REGS_PIT_BASE + 0x0U)
bogdanm 82:6473597d706e 79
bogdanm 82:6473597d706e 80 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 81 #define HW_PIT_MCR (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR)
bogdanm 82:6473597d706e 82 #define HW_PIT_MCR_RD() (HW_PIT_MCR.U)
bogdanm 82:6473597d706e 83 #define HW_PIT_MCR_WR(v) (HW_PIT_MCR.U = (v))
bogdanm 82:6473597d706e 84 #define HW_PIT_MCR_SET(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() | (v)))
bogdanm 82:6473597d706e 85 #define HW_PIT_MCR_CLR(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() & ~(v)))
bogdanm 82:6473597d706e 86 #define HW_PIT_MCR_TOG(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() ^ (v)))
bogdanm 82:6473597d706e 87 #endif
bogdanm 82:6473597d706e 88 //@}
bogdanm 82:6473597d706e 89
bogdanm 82:6473597d706e 90 /*
bogdanm 82:6473597d706e 91 * Constants & macros for individual PIT_MCR bitfields
bogdanm 82:6473597d706e 92 */
bogdanm 82:6473597d706e 93
bogdanm 82:6473597d706e 94 /*!
bogdanm 82:6473597d706e 95 * @name Register PIT_MCR, field FRZ[0] (RW)
bogdanm 82:6473597d706e 96 *
bogdanm 82:6473597d706e 97 * Allows the timers to be stopped when the device enters the Debug mode.
bogdanm 82:6473597d706e 98 *
bogdanm 82:6473597d706e 99 * Values:
bogdanm 82:6473597d706e 100 * - 0 - Timers continue to run in Debug mode.
bogdanm 82:6473597d706e 101 * - 1 - Timers are stopped in Debug mode.
bogdanm 82:6473597d706e 102 */
bogdanm 82:6473597d706e 103 //@{
bogdanm 82:6473597d706e 104 #define BP_PIT_MCR_FRZ (0U) //!< Bit position for PIT_MCR_FRZ.
bogdanm 82:6473597d706e 105 #define BM_PIT_MCR_FRZ (0x00000001U) //!< Bit mask for PIT_MCR_FRZ.
bogdanm 82:6473597d706e 106 #define BS_PIT_MCR_FRZ (1U) //!< Bit field size in bits for PIT_MCR_FRZ.
bogdanm 82:6473597d706e 107
bogdanm 82:6473597d706e 108 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 109 //! @brief Read current value of the PIT_MCR_FRZ field.
bogdanm 82:6473597d706e 110 #define BR_PIT_MCR_FRZ (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ))
bogdanm 82:6473597d706e 111 #endif
bogdanm 82:6473597d706e 112
bogdanm 82:6473597d706e 113 //! @brief Format value for bitfield PIT_MCR_FRZ.
bogdanm 82:6473597d706e 114 #define BF_PIT_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_FRZ), uint32_t) & BM_PIT_MCR_FRZ)
bogdanm 82:6473597d706e 115
bogdanm 82:6473597d706e 116 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 117 //! @brief Set the FRZ field to a new value.
bogdanm 82:6473597d706e 118 #define BW_PIT_MCR_FRZ(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ) = (v))
bogdanm 82:6473597d706e 119 #endif
bogdanm 82:6473597d706e 120 //@}
bogdanm 82:6473597d706e 121
bogdanm 82:6473597d706e 122 /*!
bogdanm 82:6473597d706e 123 * @name Register PIT_MCR, field MDIS[1] (RW)
bogdanm 82:6473597d706e 124 *
bogdanm 82:6473597d706e 125 * Disables the standard timers. This field must be enabled before any other
bogdanm 82:6473597d706e 126 * setup is done.
bogdanm 82:6473597d706e 127 *
bogdanm 82:6473597d706e 128 * Values:
bogdanm 82:6473597d706e 129 * - 0 - Clock for standard PIT timers is enabled.
bogdanm 82:6473597d706e 130 * - 1 - Clock for standard PIT timers is disabled.
bogdanm 82:6473597d706e 131 */
bogdanm 82:6473597d706e 132 //@{
bogdanm 82:6473597d706e 133 #define BP_PIT_MCR_MDIS (1U) //!< Bit position for PIT_MCR_MDIS.
bogdanm 82:6473597d706e 134 #define BM_PIT_MCR_MDIS (0x00000002U) //!< Bit mask for PIT_MCR_MDIS.
bogdanm 82:6473597d706e 135 #define BS_PIT_MCR_MDIS (1U) //!< Bit field size in bits for PIT_MCR_MDIS.
bogdanm 82:6473597d706e 136
bogdanm 82:6473597d706e 137 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 138 //! @brief Read current value of the PIT_MCR_MDIS field.
bogdanm 82:6473597d706e 139 #define BR_PIT_MCR_MDIS (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS))
bogdanm 82:6473597d706e 140 #endif
bogdanm 82:6473597d706e 141
bogdanm 82:6473597d706e 142 //! @brief Format value for bitfield PIT_MCR_MDIS.
bogdanm 82:6473597d706e 143 #define BF_PIT_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_MDIS), uint32_t) & BM_PIT_MCR_MDIS)
bogdanm 82:6473597d706e 144
bogdanm 82:6473597d706e 145 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 146 //! @brief Set the MDIS field to a new value.
bogdanm 82:6473597d706e 147 #define BW_PIT_MCR_MDIS(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS) = (v))
bogdanm 82:6473597d706e 148 #endif
bogdanm 82:6473597d706e 149 //@}
bogdanm 82:6473597d706e 150
bogdanm 82:6473597d706e 151 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 152 // HW_PIT_LDVALn - Timer Load Value Register
bogdanm 82:6473597d706e 153 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 154
bogdanm 82:6473597d706e 155 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 156 /*!
bogdanm 82:6473597d706e 157 * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
bogdanm 82:6473597d706e 158 *
bogdanm 82:6473597d706e 159 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 160 *
bogdanm 82:6473597d706e 161 * These registers select the timeout period for the timer interrupts.
bogdanm 82:6473597d706e 162 */
bogdanm 82:6473597d706e 163 typedef union _hw_pit_ldvaln
bogdanm 82:6473597d706e 164 {
bogdanm 82:6473597d706e 165 uint32_t U;
bogdanm 82:6473597d706e 166 struct _hw_pit_ldvaln_bitfields
bogdanm 82:6473597d706e 167 {
bogdanm 82:6473597d706e 168 uint32_t TSV : 32; //!< [31:0] Timer Start Value
bogdanm 82:6473597d706e 169 } B;
bogdanm 82:6473597d706e 170 } hw_pit_ldvaln_t;
bogdanm 82:6473597d706e 171 #endif
bogdanm 82:6473597d706e 172
bogdanm 82:6473597d706e 173 /*!
bogdanm 82:6473597d706e 174 * @name Constants and macros for entire PIT_LDVALn register
bogdanm 82:6473597d706e 175 */
bogdanm 82:6473597d706e 176 //@{
bogdanm 82:6473597d706e 177 #define HW_PIT_LDVALn_COUNT (4U)
bogdanm 82:6473597d706e 178
bogdanm 82:6473597d706e 179 #define HW_PIT_LDVALn_ADDR(n) (REGS_PIT_BASE + 0x100U + (0x10U * n))
bogdanm 82:6473597d706e 180
bogdanm 82:6473597d706e 181 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 182 #define HW_PIT_LDVALn(n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(n))
bogdanm 82:6473597d706e 183 #define HW_PIT_LDVALn_RD(n) (HW_PIT_LDVALn(n).U)
bogdanm 82:6473597d706e 184 #define HW_PIT_LDVALn_WR(n, v) (HW_PIT_LDVALn(n).U = (v))
bogdanm 82:6473597d706e 185 #define HW_PIT_LDVALn_SET(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) | (v)))
bogdanm 82:6473597d706e 186 #define HW_PIT_LDVALn_CLR(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 187 #define HW_PIT_LDVALn_TOG(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 188 #endif
bogdanm 82:6473597d706e 189 //@}
bogdanm 82:6473597d706e 190
bogdanm 82:6473597d706e 191 /*
bogdanm 82:6473597d706e 192 * Constants & macros for individual PIT_LDVALn bitfields
bogdanm 82:6473597d706e 193 */
bogdanm 82:6473597d706e 194
bogdanm 82:6473597d706e 195 /*!
bogdanm 82:6473597d706e 196 * @name Register PIT_LDVALn, field TSV[31:0] (RW)
bogdanm 82:6473597d706e 197 *
bogdanm 82:6473597d706e 198 * Sets the timer start value. The timer will count down until it reaches 0,
bogdanm 82:6473597d706e 199 * then it will generate an interrupt and load this register value again. Writing a
bogdanm 82:6473597d706e 200 * new value to this register will not restart the timer; instead the value will
bogdanm 82:6473597d706e 201 * be loaded after the timer expires. To abort the current cycle and start a
bogdanm 82:6473597d706e 202 * timer period with the new value, the timer must be disabled and enabled again.
bogdanm 82:6473597d706e 203 */
bogdanm 82:6473597d706e 204 //@{
bogdanm 82:6473597d706e 205 #define BP_PIT_LDVALn_TSV (0U) //!< Bit position for PIT_LDVALn_TSV.
bogdanm 82:6473597d706e 206 #define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) //!< Bit mask for PIT_LDVALn_TSV.
bogdanm 82:6473597d706e 207 #define BS_PIT_LDVALn_TSV (32U) //!< Bit field size in bits for PIT_LDVALn_TSV.
bogdanm 82:6473597d706e 208
bogdanm 82:6473597d706e 209 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 210 //! @brief Read current value of the PIT_LDVALn_TSV field.
bogdanm 82:6473597d706e 211 #define BR_PIT_LDVALn_TSV(n) (HW_PIT_LDVALn(n).U)
bogdanm 82:6473597d706e 212 #endif
bogdanm 82:6473597d706e 213
bogdanm 82:6473597d706e 214 //! @brief Format value for bitfield PIT_LDVALn_TSV.
bogdanm 82:6473597d706e 215 #define BF_PIT_LDVALn_TSV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_LDVALn_TSV), uint32_t) & BM_PIT_LDVALn_TSV)
bogdanm 82:6473597d706e 216
bogdanm 82:6473597d706e 217 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 218 //! @brief Set the TSV field to a new value.
bogdanm 82:6473597d706e 219 #define BW_PIT_LDVALn_TSV(n, v) (HW_PIT_LDVALn_WR(n, v))
bogdanm 82:6473597d706e 220 #endif
bogdanm 82:6473597d706e 221 //@}
bogdanm 82:6473597d706e 222 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 223 // HW_PIT_CVALn - Current Timer Value Register
bogdanm 82:6473597d706e 224 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 225
bogdanm 82:6473597d706e 226 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 227 /*!
bogdanm 82:6473597d706e 228 * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
bogdanm 82:6473597d706e 229 *
bogdanm 82:6473597d706e 230 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 231 *
bogdanm 82:6473597d706e 232 * These registers indicate the current timer position.
bogdanm 82:6473597d706e 233 */
bogdanm 82:6473597d706e 234 typedef union _hw_pit_cvaln
bogdanm 82:6473597d706e 235 {
bogdanm 82:6473597d706e 236 uint32_t U;
bogdanm 82:6473597d706e 237 struct _hw_pit_cvaln_bitfields
bogdanm 82:6473597d706e 238 {
bogdanm 82:6473597d706e 239 uint32_t TVL : 32; //!< [31:0] Current Timer Value
bogdanm 82:6473597d706e 240 } B;
bogdanm 82:6473597d706e 241 } hw_pit_cvaln_t;
bogdanm 82:6473597d706e 242 #endif
bogdanm 82:6473597d706e 243
bogdanm 82:6473597d706e 244 /*!
bogdanm 82:6473597d706e 245 * @name Constants and macros for entire PIT_CVALn register
bogdanm 82:6473597d706e 246 */
bogdanm 82:6473597d706e 247 //@{
bogdanm 82:6473597d706e 248 #define HW_PIT_CVALn_COUNT (4U)
bogdanm 82:6473597d706e 249
bogdanm 82:6473597d706e 250 #define HW_PIT_CVALn_ADDR(n) (REGS_PIT_BASE + 0x104U + (0x10U * n))
bogdanm 82:6473597d706e 251
bogdanm 82:6473597d706e 252 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 253 #define HW_PIT_CVALn(n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(n))
bogdanm 82:6473597d706e 254 #define HW_PIT_CVALn_RD(n) (HW_PIT_CVALn(n).U)
bogdanm 82:6473597d706e 255 #endif
bogdanm 82:6473597d706e 256 //@}
bogdanm 82:6473597d706e 257
bogdanm 82:6473597d706e 258 /*
bogdanm 82:6473597d706e 259 * Constants & macros for individual PIT_CVALn bitfields
bogdanm 82:6473597d706e 260 */
bogdanm 82:6473597d706e 261
bogdanm 82:6473597d706e 262 /*!
bogdanm 82:6473597d706e 263 * @name Register PIT_CVALn, field TVL[31:0] (RO)
bogdanm 82:6473597d706e 264 *
bogdanm 82:6473597d706e 265 * Represents the current timer value, if the timer is enabled. If the timer is
bogdanm 82:6473597d706e 266 * disabled, do not use this field as its value is unreliable. The timer uses a
bogdanm 82:6473597d706e 267 * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
bogdanm 82:6473597d706e 268 */
bogdanm 82:6473597d706e 269 //@{
bogdanm 82:6473597d706e 270 #define BP_PIT_CVALn_TVL (0U) //!< Bit position for PIT_CVALn_TVL.
bogdanm 82:6473597d706e 271 #define BM_PIT_CVALn_TVL (0xFFFFFFFFU) //!< Bit mask for PIT_CVALn_TVL.
bogdanm 82:6473597d706e 272 #define BS_PIT_CVALn_TVL (32U) //!< Bit field size in bits for PIT_CVALn_TVL.
bogdanm 82:6473597d706e 273
bogdanm 82:6473597d706e 274 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 275 //! @brief Read current value of the PIT_CVALn_TVL field.
bogdanm 82:6473597d706e 276 #define BR_PIT_CVALn_TVL(n) (HW_PIT_CVALn(n).U)
bogdanm 82:6473597d706e 277 #endif
bogdanm 82:6473597d706e 278 //@}
bogdanm 82:6473597d706e 279 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 280 // HW_PIT_TCTRLn - Timer Control Register
bogdanm 82:6473597d706e 281 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 282
bogdanm 82:6473597d706e 283 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 284 /*!
bogdanm 82:6473597d706e 285 * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
bogdanm 82:6473597d706e 286 *
bogdanm 82:6473597d706e 287 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 288 *
bogdanm 82:6473597d706e 289 * These registers contain the control bits for each timer.
bogdanm 82:6473597d706e 290 */
bogdanm 82:6473597d706e 291 typedef union _hw_pit_tctrln
bogdanm 82:6473597d706e 292 {
bogdanm 82:6473597d706e 293 uint32_t U;
bogdanm 82:6473597d706e 294 struct _hw_pit_tctrln_bitfields
bogdanm 82:6473597d706e 295 {
bogdanm 82:6473597d706e 296 uint32_t TEN : 1; //!< [0] Timer Enable
bogdanm 82:6473597d706e 297 uint32_t TIE : 1; //!< [1] Timer Interrupt Enable
bogdanm 82:6473597d706e 298 uint32_t CHN : 1; //!< [2] Chain Mode
bogdanm 82:6473597d706e 299 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 300 } B;
bogdanm 82:6473597d706e 301 } hw_pit_tctrln_t;
bogdanm 82:6473597d706e 302 #endif
bogdanm 82:6473597d706e 303
bogdanm 82:6473597d706e 304 /*!
bogdanm 82:6473597d706e 305 * @name Constants and macros for entire PIT_TCTRLn register
bogdanm 82:6473597d706e 306 */
bogdanm 82:6473597d706e 307 //@{
bogdanm 82:6473597d706e 308 #define HW_PIT_TCTRLn_COUNT (4U)
bogdanm 82:6473597d706e 309
bogdanm 82:6473597d706e 310 #define HW_PIT_TCTRLn_ADDR(n) (REGS_PIT_BASE + 0x108U + (0x10U * n))
bogdanm 82:6473597d706e 311
bogdanm 82:6473597d706e 312 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 313 #define HW_PIT_TCTRLn(n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(n))
bogdanm 82:6473597d706e 314 #define HW_PIT_TCTRLn_RD(n) (HW_PIT_TCTRLn(n).U)
bogdanm 82:6473597d706e 315 #define HW_PIT_TCTRLn_WR(n, v) (HW_PIT_TCTRLn(n).U = (v))
bogdanm 82:6473597d706e 316 #define HW_PIT_TCTRLn_SET(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) | (v)))
bogdanm 82:6473597d706e 317 #define HW_PIT_TCTRLn_CLR(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 318 #define HW_PIT_TCTRLn_TOG(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 319 #endif
bogdanm 82:6473597d706e 320 //@}
bogdanm 82:6473597d706e 321
bogdanm 82:6473597d706e 322 /*
bogdanm 82:6473597d706e 323 * Constants & macros for individual PIT_TCTRLn bitfields
bogdanm 82:6473597d706e 324 */
bogdanm 82:6473597d706e 325
bogdanm 82:6473597d706e 326 /*!
bogdanm 82:6473597d706e 327 * @name Register PIT_TCTRLn, field TEN[0] (RW)
bogdanm 82:6473597d706e 328 *
bogdanm 82:6473597d706e 329 * Enables or disables the timer.
bogdanm 82:6473597d706e 330 *
bogdanm 82:6473597d706e 331 * Values:
bogdanm 82:6473597d706e 332 * - 0 - Timer n is disabled.
bogdanm 82:6473597d706e 333 * - 1 - Timer n is enabled.
bogdanm 82:6473597d706e 334 */
bogdanm 82:6473597d706e 335 //@{
bogdanm 82:6473597d706e 336 #define BP_PIT_TCTRLn_TEN (0U) //!< Bit position for PIT_TCTRLn_TEN.
bogdanm 82:6473597d706e 337 #define BM_PIT_TCTRLn_TEN (0x00000001U) //!< Bit mask for PIT_TCTRLn_TEN.
bogdanm 82:6473597d706e 338 #define BS_PIT_TCTRLn_TEN (1U) //!< Bit field size in bits for PIT_TCTRLn_TEN.
bogdanm 82:6473597d706e 339
bogdanm 82:6473597d706e 340 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 341 //! @brief Read current value of the PIT_TCTRLn_TEN field.
bogdanm 82:6473597d706e 342 #define BR_PIT_TCTRLn_TEN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN))
bogdanm 82:6473597d706e 343 #endif
bogdanm 82:6473597d706e 344
bogdanm 82:6473597d706e 345 //! @brief Format value for bitfield PIT_TCTRLn_TEN.
bogdanm 82:6473597d706e 346 #define BF_PIT_TCTRLn_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TEN), uint32_t) & BM_PIT_TCTRLn_TEN)
bogdanm 82:6473597d706e 347
bogdanm 82:6473597d706e 348 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 349 //! @brief Set the TEN field to a new value.
bogdanm 82:6473597d706e 350 #define BW_PIT_TCTRLn_TEN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN) = (v))
bogdanm 82:6473597d706e 351 #endif
bogdanm 82:6473597d706e 352 //@}
bogdanm 82:6473597d706e 353
bogdanm 82:6473597d706e 354 /*!
bogdanm 82:6473597d706e 355 * @name Register PIT_TCTRLn, field TIE[1] (RW)
bogdanm 82:6473597d706e 356 *
bogdanm 82:6473597d706e 357 * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
bogdanm 82:6473597d706e 358 * will immediately cause an interrupt event. To avoid this, the associated
bogdanm 82:6473597d706e 359 * TFLGn[TIF] must be cleared first.
bogdanm 82:6473597d706e 360 *
bogdanm 82:6473597d706e 361 * Values:
bogdanm 82:6473597d706e 362 * - 0 - Interrupt requests from Timer n are disabled.
bogdanm 82:6473597d706e 363 * - 1 - Interrupt will be requested whenever TIF is set.
bogdanm 82:6473597d706e 364 */
bogdanm 82:6473597d706e 365 //@{
bogdanm 82:6473597d706e 366 #define BP_PIT_TCTRLn_TIE (1U) //!< Bit position for PIT_TCTRLn_TIE.
bogdanm 82:6473597d706e 367 #define BM_PIT_TCTRLn_TIE (0x00000002U) //!< Bit mask for PIT_TCTRLn_TIE.
bogdanm 82:6473597d706e 368 #define BS_PIT_TCTRLn_TIE (1U) //!< Bit field size in bits for PIT_TCTRLn_TIE.
bogdanm 82:6473597d706e 369
bogdanm 82:6473597d706e 370 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 371 //! @brief Read current value of the PIT_TCTRLn_TIE field.
bogdanm 82:6473597d706e 372 #define BR_PIT_TCTRLn_TIE(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE))
bogdanm 82:6473597d706e 373 #endif
bogdanm 82:6473597d706e 374
bogdanm 82:6473597d706e 375 //! @brief Format value for bitfield PIT_TCTRLn_TIE.
bogdanm 82:6473597d706e 376 #define BF_PIT_TCTRLn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TIE), uint32_t) & BM_PIT_TCTRLn_TIE)
bogdanm 82:6473597d706e 377
bogdanm 82:6473597d706e 378 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 379 //! @brief Set the TIE field to a new value.
bogdanm 82:6473597d706e 380 #define BW_PIT_TCTRLn_TIE(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE) = (v))
bogdanm 82:6473597d706e 381 #endif
bogdanm 82:6473597d706e 382 //@}
bogdanm 82:6473597d706e 383
bogdanm 82:6473597d706e 384 /*!
bogdanm 82:6473597d706e 385 * @name Register PIT_TCTRLn, field CHN[2] (RW)
bogdanm 82:6473597d706e 386 *
bogdanm 82:6473597d706e 387 * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
bogdanm 82:6473597d706e 388 * Timer 0 cannot be chained.
bogdanm 82:6473597d706e 389 *
bogdanm 82:6473597d706e 390 * Values:
bogdanm 82:6473597d706e 391 * - 0 - Timer is not chained.
bogdanm 82:6473597d706e 392 * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
bogdanm 82:6473597d706e 393 * field is set, Timer 2 is chained to Timer 1.
bogdanm 82:6473597d706e 394 */
bogdanm 82:6473597d706e 395 //@{
bogdanm 82:6473597d706e 396 #define BP_PIT_TCTRLn_CHN (2U) //!< Bit position for PIT_TCTRLn_CHN.
bogdanm 82:6473597d706e 397 #define BM_PIT_TCTRLn_CHN (0x00000004U) //!< Bit mask for PIT_TCTRLn_CHN.
bogdanm 82:6473597d706e 398 #define BS_PIT_TCTRLn_CHN (1U) //!< Bit field size in bits for PIT_TCTRLn_CHN.
bogdanm 82:6473597d706e 399
bogdanm 82:6473597d706e 400 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 401 //! @brief Read current value of the PIT_TCTRLn_CHN field.
bogdanm 82:6473597d706e 402 #define BR_PIT_TCTRLn_CHN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN))
bogdanm 82:6473597d706e 403 #endif
bogdanm 82:6473597d706e 404
bogdanm 82:6473597d706e 405 //! @brief Format value for bitfield PIT_TCTRLn_CHN.
bogdanm 82:6473597d706e 406 #define BF_PIT_TCTRLn_CHN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_CHN), uint32_t) & BM_PIT_TCTRLn_CHN)
bogdanm 82:6473597d706e 407
bogdanm 82:6473597d706e 408 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 409 //! @brief Set the CHN field to a new value.
bogdanm 82:6473597d706e 410 #define BW_PIT_TCTRLn_CHN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN) = (v))
bogdanm 82:6473597d706e 411 #endif
bogdanm 82:6473597d706e 412 //@}
bogdanm 82:6473597d706e 413 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 414 // HW_PIT_TFLGn - Timer Flag Register
bogdanm 82:6473597d706e 415 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 416
bogdanm 82:6473597d706e 417 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 418 /*!
bogdanm 82:6473597d706e 419 * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
bogdanm 82:6473597d706e 420 *
bogdanm 82:6473597d706e 421 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 422 *
bogdanm 82:6473597d706e 423 * These registers hold the PIT interrupt flags.
bogdanm 82:6473597d706e 424 */
bogdanm 82:6473597d706e 425 typedef union _hw_pit_tflgn
bogdanm 82:6473597d706e 426 {
bogdanm 82:6473597d706e 427 uint32_t U;
bogdanm 82:6473597d706e 428 struct _hw_pit_tflgn_bitfields
bogdanm 82:6473597d706e 429 {
bogdanm 82:6473597d706e 430 uint32_t TIF : 1; //!< [0] Timer Interrupt Flag
bogdanm 82:6473597d706e 431 uint32_t RESERVED0 : 31; //!< [31:1]
bogdanm 82:6473597d706e 432 } B;
bogdanm 82:6473597d706e 433 } hw_pit_tflgn_t;
bogdanm 82:6473597d706e 434 #endif
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 /*!
bogdanm 82:6473597d706e 437 * @name Constants and macros for entire PIT_TFLGn register
bogdanm 82:6473597d706e 438 */
bogdanm 82:6473597d706e 439 //@{
bogdanm 82:6473597d706e 440 #define HW_PIT_TFLGn_COUNT (4U)
bogdanm 82:6473597d706e 441
bogdanm 82:6473597d706e 442 #define HW_PIT_TFLGn_ADDR(n) (REGS_PIT_BASE + 0x10CU + (0x10U * n))
bogdanm 82:6473597d706e 443
bogdanm 82:6473597d706e 444 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 445 #define HW_PIT_TFLGn(n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(n))
bogdanm 82:6473597d706e 446 #define HW_PIT_TFLGn_RD(n) (HW_PIT_TFLGn(n).U)
bogdanm 82:6473597d706e 447 #define HW_PIT_TFLGn_WR(n, v) (HW_PIT_TFLGn(n).U = (v))
bogdanm 82:6473597d706e 448 #define HW_PIT_TFLGn_SET(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) | (v)))
bogdanm 82:6473597d706e 449 #define HW_PIT_TFLGn_CLR(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 450 #define HW_PIT_TFLGn_TOG(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 451 #endif
bogdanm 82:6473597d706e 452 //@}
bogdanm 82:6473597d706e 453
bogdanm 82:6473597d706e 454 /*
bogdanm 82:6473597d706e 455 * Constants & macros for individual PIT_TFLGn bitfields
bogdanm 82:6473597d706e 456 */
bogdanm 82:6473597d706e 457
bogdanm 82:6473597d706e 458 /*!
bogdanm 82:6473597d706e 459 * @name Register PIT_TFLGn, field TIF[0] (W1C)
bogdanm 82:6473597d706e 460 *
bogdanm 82:6473597d706e 461 * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
bogdanm 82:6473597d706e 462 * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
bogdanm 82:6473597d706e 463 * interrupt request.
bogdanm 82:6473597d706e 464 *
bogdanm 82:6473597d706e 465 * Values:
bogdanm 82:6473597d706e 466 * - 0 - Timeout has not yet occurred.
bogdanm 82:6473597d706e 467 * - 1 - Timeout has occurred.
bogdanm 82:6473597d706e 468 */
bogdanm 82:6473597d706e 469 //@{
bogdanm 82:6473597d706e 470 #define BP_PIT_TFLGn_TIF (0U) //!< Bit position for PIT_TFLGn_TIF.
bogdanm 82:6473597d706e 471 #define BM_PIT_TFLGn_TIF (0x00000001U) //!< Bit mask for PIT_TFLGn_TIF.
bogdanm 82:6473597d706e 472 #define BS_PIT_TFLGn_TIF (1U) //!< Bit field size in bits for PIT_TFLGn_TIF.
bogdanm 82:6473597d706e 473
bogdanm 82:6473597d706e 474 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 475 //! @brief Read current value of the PIT_TFLGn_TIF field.
bogdanm 82:6473597d706e 476 #define BR_PIT_TFLGn_TIF(n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF))
bogdanm 82:6473597d706e 477 #endif
bogdanm 82:6473597d706e 478
bogdanm 82:6473597d706e 479 //! @brief Format value for bitfield PIT_TFLGn_TIF.
bogdanm 82:6473597d706e 480 #define BF_PIT_TFLGn_TIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TFLGn_TIF), uint32_t) & BM_PIT_TFLGn_TIF)
bogdanm 82:6473597d706e 481
bogdanm 82:6473597d706e 482 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 483 //! @brief Set the TIF field to a new value.
bogdanm 82:6473597d706e 484 #define BW_PIT_TFLGn_TIF(n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF) = (v))
bogdanm 82:6473597d706e 485 #endif
bogdanm 82:6473597d706e 486 //@}
bogdanm 82:6473597d706e 487
bogdanm 82:6473597d706e 488 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 489 // hw_pit_t - module struct
bogdanm 82:6473597d706e 490 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 491 /*!
bogdanm 82:6473597d706e 492 * @brief All PIT module registers.
bogdanm 82:6473597d706e 493 */
bogdanm 82:6473597d706e 494 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 495 #pragma pack(1)
bogdanm 82:6473597d706e 496 typedef struct _hw_pit
bogdanm 82:6473597d706e 497 {
bogdanm 82:6473597d706e 498 __IO hw_pit_mcr_t MCR; //!< [0x0] PIT Module Control Register
bogdanm 82:6473597d706e 499 uint8_t _reserved0[252];
bogdanm 82:6473597d706e 500 struct {
bogdanm 82:6473597d706e 501 __IO hw_pit_ldvaln_t LDVALn; //!< [0x100] Timer Load Value Register
bogdanm 82:6473597d706e 502 __I hw_pit_cvaln_t CVALn; //!< [0x104] Current Timer Value Register
bogdanm 82:6473597d706e 503 __IO hw_pit_tctrln_t TCTRLn; //!< [0x108] Timer Control Register
bogdanm 82:6473597d706e 504 __IO hw_pit_tflgn_t TFLGn; //!< [0x10C] Timer Flag Register
bogdanm 82:6473597d706e 505 } CHANNEL[4];
bogdanm 82:6473597d706e 506 } hw_pit_t;
bogdanm 82:6473597d706e 507 #pragma pack()
bogdanm 82:6473597d706e 508
bogdanm 82:6473597d706e 509 //! @brief Macro to access all PIT registers.
bogdanm 82:6473597d706e 510 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 511 //! use the '&' operator, like <code>&HW_PIT</code>.
bogdanm 82:6473597d706e 512 #define HW_PIT (*(hw_pit_t *) REGS_PIT_BASE)
bogdanm 82:6473597d706e 513 #endif
bogdanm 82:6473597d706e 514
bogdanm 82:6473597d706e 515 #endif // __HW_PIT_REGISTERS_H__
bogdanm 82:6473597d706e 516 // v22/130726/0.9
bogdanm 82:6473597d706e 517 // EOF