mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c@591:474d026f7d79, 2015-07-15 (annotated)

Committer:
mbed_official
Date:
Wed Jul 15 08:15:08 2015 +0100
Revision:
591:474d026f7d79
Parent:
500:04797f1feae2
Child:
617:3b0e8f440867
Synchronized with git revision 9bb85c06785ef6791e8a6c4006a279857656c2b5



Full URL: https://github.com/mbedmicro/mbed/commit/9bb85c06785ef6791e8a6c4006a279857656c2b5/



mbed - Modified MBED_ASSERT to use error()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 17 #include "pwmout_api.h"
mbed_official 390:35c2c1cf29cd 18 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 19 #include "pinmap.h"
mbed_official 437:0b72c0f86db6 20 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 21 #include "cpg_iodefine.h"
mbed_official 390:35c2c1cf29cd 22 #include "pwm_iodefine.h"
mbed_official 390:35c2c1cf29cd 23
mbed_official 591:474d026f7d79 24 #define MTU2_PWM_NUM 22
mbed_official 591:474d026f7d79 25 #define MTU2_PWM_SIGNAL 2
mbed_official 591:474d026f7d79 26 #define MTU2_PWM_OFFSET 0x20
mbed_official 591:474d026f7d79 27
mbed_official 390:35c2c1cf29cd 28 // PORT ID, PWM ID, Pin function
mbed_official 390:35c2c1cf29cd 29 static const PinMap PinMap_PWM[] = {
mbed_official 591:474d026f7d79 30 {P2_1 , MTU2_PWM0_PIN , 6},
mbed_official 591:474d026f7d79 31 {P2_11 , MTU2_PWM1_PIN , 5},
mbed_official 591:474d026f7d79 32 {P3_8 , MTU2_PWM2_PIN , 6},
mbed_official 591:474d026f7d79 33 {P3_10 , MTU2_PWM3_PIN , 6},
mbed_official 591:474d026f7d79 34 {P4_0 , MTU2_PWM4_PIN , 2},
mbed_official 591:474d026f7d79 35 {P4_4 , MTU2_PWM5_PIN , 3},
mbed_official 591:474d026f7d79 36 {P4_6 , MTU2_PWM6_PIN , 3},
mbed_official 591:474d026f7d79 37 {P5_0 , MTU2_PWM7_PIN , 6},
mbed_official 591:474d026f7d79 38 {P5_3 , MTU2_PWM8_PIN , 6},
mbed_official 591:474d026f7d79 39 {P5_5 , MTU2_PWM9_PIN , 6},
mbed_official 591:474d026f7d79 40 {P7_2 , MTU2_PWM10_PIN , 7},
mbed_official 591:474d026f7d79 41 {P7_4 , MTU2_PWM11_PIN , 7},
mbed_official 591:474d026f7d79 42 {P7_6 , MTU2_PWM12_PIN , 7},
mbed_official 591:474d026f7d79 43 {P7_10 , MTU2_PWM13_PIN , 7},
mbed_official 591:474d026f7d79 44 {P7_12 , MTU2_PWM14_PIN , 7},
mbed_official 591:474d026f7d79 45 {P7_14 , MTU2_PWM15_PIN , 7},
mbed_official 591:474d026f7d79 46 {P8_8 , MTU2_PWM16_PIN , 5},
mbed_official 591:474d026f7d79 47 {P8_10 , MTU2_PWM17_PIN , 4},
mbed_official 591:474d026f7d79 48 {P8_12 , MTU2_PWM18_PIN , 4},
mbed_official 591:474d026f7d79 49 {P8_14 , MTU2_PWM19_PIN , 4},
mbed_official 591:474d026f7d79 50 {P11_0 , MTU2_PWM20_PIN , 2},
mbed_official 591:474d026f7d79 51 {P11_2 , MTU2_PWM21_PIN , 2},
mbed_official 591:474d026f7d79 52 {P4_4 , PWM0_PIN , 4},
mbed_official 591:474d026f7d79 53 {P3_2 , PWM1_PIN , 7},
mbed_official 591:474d026f7d79 54 {P4_6 , PWM2_PIN , 4},
mbed_official 591:474d026f7d79 55 {P4_7 , PWM3_PIN , 4},
mbed_official 591:474d026f7d79 56 {P8_14 , PWM4_PIN , 6},
mbed_official 591:474d026f7d79 57 {P8_15 , PWM5_PIN , 6},
mbed_official 591:474d026f7d79 58 {P8_13 , PWM6_PIN , 6},
mbed_official 591:474d026f7d79 59 {P8_11 , PWM7_PIN , 6},
mbed_official 591:474d026f7d79 60 {P8_8 , PWM8_PIN , 6},
mbed_official 591:474d026f7d79 61 {P10_0 , PWM9_PIN , 3},
mbed_official 591:474d026f7d79 62 {P8_12 , PWM10_PIN , 6},
mbed_official 591:474d026f7d79 63 {P8_9 , PWM11_PIN , 6},
mbed_official 591:474d026f7d79 64 {P8_10 , PWM12_PIN , 6},
mbed_official 591:474d026f7d79 65 {P4_5 , PWM13_PIN , 4},
mbed_official 591:474d026f7d79 66 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 67 };
mbed_official 390:35c2c1cf29cd 68
mbed_official 591:474d026f7d79 69 static const PWMType PORT[] = {
mbed_official 437:0b72c0f86db6 70 PWM2E, // PWM0_PIN
mbed_official 437:0b72c0f86db6 71 PWM2C, // PWM1_PIN
mbed_official 437:0b72c0f86db6 72 PWM2G, // PWM2_PIN
mbed_official 437:0b72c0f86db6 73 PWM2H, // PWM3_PIN
mbed_official 437:0b72c0f86db6 74 PWM1G, // PWM4_PIN
mbed_official 437:0b72c0f86db6 75 PWM1H, // PWM5_PIN
mbed_official 437:0b72c0f86db6 76 PWM1F, // PWM6_PIN
mbed_official 437:0b72c0f86db6 77 PWM1D, // PWM7_PIN
mbed_official 437:0b72c0f86db6 78 PWM1A, // PWM8_PIN
mbed_official 437:0b72c0f86db6 79 PWM2A, // PWM9_PIN
mbed_official 437:0b72c0f86db6 80 PWM1E, // PWM10_PIN
mbed_official 437:0b72c0f86db6 81 PWM1B, // PWM11_PIN
mbed_official 437:0b72c0f86db6 82 PWM1C, // PWM12_PIN
mbed_official 500:04797f1feae2 83 PWM2F, // PWM13_PIN
mbed_official 390:35c2c1cf29cd 84 };
mbed_official 390:35c2c1cf29cd 85
mbed_official 591:474d026f7d79 86 static const MTU2_PWMType MTU2_PORT[] = {
mbed_official 591:474d026f7d79 87 TIOC2A, // MTU2_PWM0_PIN
mbed_official 591:474d026f7d79 88 TIOC1A, // MTU2_PWM1_PIN
mbed_official 591:474d026f7d79 89 TIOC4A, // MTU2_PWM2_PIN
mbed_official 591:474d026f7d79 90 TIOC4C, // MTU2_PWM3_PIN
mbed_official 591:474d026f7d79 91 TIOC0A, // MTU2_PWM4_PIN
mbed_official 591:474d026f7d79 92 TIOC4A, // MTU2_PWM5_PIN
mbed_official 591:474d026f7d79 93 TIOC4C, // MTU2_PWM6_PIN
mbed_official 591:474d026f7d79 94 TIOC0A, // MTU2_PWM7_PIN
mbed_official 591:474d026f7d79 95 TIOC3C, // MTU2_PWM8_PIN
mbed_official 591:474d026f7d79 96 TIOC0C, // MTU2_PWM9_PIN
mbed_official 591:474d026f7d79 97 TIOC0C, // MTU2_PWM10_PIN
mbed_official 591:474d026f7d79 98 TIOC1A, // MTU2_PWM11_PIN
mbed_official 591:474d026f7d79 99 TIOC2A, // MTU2_PWM12_PIN
mbed_official 591:474d026f7d79 100 TIOC3C, // MTU2_PWM13_PIN
mbed_official 591:474d026f7d79 101 TIOC4A, // MTU2_PWM14_PIN
mbed_official 591:474d026f7d79 102 TIOC4C, // MTU2_PWM15_PIN
mbed_official 591:474d026f7d79 103 TIOC1A, // MTU2_PWM16_PIN
mbed_official 591:474d026f7d79 104 TIOC3A, // MTU2_PWM17_PIN
mbed_official 591:474d026f7d79 105 TIOC3C, // MTU2_PWM18_PIN
mbed_official 591:474d026f7d79 106 TIOC2A, // MTU2_PWM19_PIN
mbed_official 591:474d026f7d79 107 TIOC4A, // MTU2_PWM20_PIN
mbed_official 591:474d026f7d79 108 TIOC4C, // MTU2_PWM21_PIN
mbed_official 591:474d026f7d79 109 };
mbed_official 591:474d026f7d79 110
mbed_official 437:0b72c0f86db6 111 static __IO uint16_t *PWM_MATCH[] = {
mbed_official 437:0b72c0f86db6 112 &PWMPWBFR_2E, // PWM0_PIN
mbed_official 437:0b72c0f86db6 113 &PWMPWBFR_2C, // PWM1_PIN
mbed_official 437:0b72c0f86db6 114 &PWMPWBFR_2G, // PWM2_PIN
mbed_official 437:0b72c0f86db6 115 &PWMPWBFR_2G, // PWM3_PIN
mbed_official 437:0b72c0f86db6 116 &PWMPWBFR_1G, // PWM4_PIN
mbed_official 437:0b72c0f86db6 117 &PWMPWBFR_1G, // PWM5_PIN
mbed_official 437:0b72c0f86db6 118 &PWMPWBFR_1E, // PWM6_PIN
mbed_official 437:0b72c0f86db6 119 &PWMPWBFR_1C, // PWM7_PIN
mbed_official 437:0b72c0f86db6 120 &PWMPWBFR_1A, // PWM8_PIN
mbed_official 437:0b72c0f86db6 121 &PWMPWBFR_2A, // PWM9_PIN
mbed_official 437:0b72c0f86db6 122 &PWMPWBFR_1E, // PWM10_PIN
mbed_official 437:0b72c0f86db6 123 &PWMPWBFR_1A, // PWM11_PIN
mbed_official 437:0b72c0f86db6 124 &PWMPWBFR_1C, // PWM12_PIN
mbed_official 500:04797f1feae2 125 &PWMPWBFR_2E, // PWM13_PIN
mbed_official 437:0b72c0f86db6 126 };
mbed_official 390:35c2c1cf29cd 127
mbed_official 591:474d026f7d79 128 static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = {
mbed_official 591:474d026f7d79 129 { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM0_PIN
mbed_official 591:474d026f7d79 130 { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM1_PIN
mbed_official 591:474d026f7d79 131 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM2_PIN
mbed_official 591:474d026f7d79 132 { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM3_PIN
mbed_official 591:474d026f7d79 133 { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM4_PIN
mbed_official 591:474d026f7d79 134 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM5_PIN
mbed_official 591:474d026f7d79 135 { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM6_PIN
mbed_official 591:474d026f7d79 136 { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM7_PIN
mbed_official 591:474d026f7d79 137 { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM8_PIN
mbed_official 591:474d026f7d79 138 { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM9_PIN
mbed_official 591:474d026f7d79 139 { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM10_PIN
mbed_official 591:474d026f7d79 140 { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM11_PIN
mbed_official 591:474d026f7d79 141 { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM12_PIN
mbed_official 591:474d026f7d79 142 { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM13_PIN
mbed_official 591:474d026f7d79 143 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM14_PIN
mbed_official 591:474d026f7d79 144 { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM15_PIN
mbed_official 591:474d026f7d79 145 { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM16_PIN
mbed_official 591:474d026f7d79 146 { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM17_PIN
mbed_official 591:474d026f7d79 147 { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM18_PIN
mbed_official 591:474d026f7d79 148 { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM19_PIN
mbed_official 591:474d026f7d79 149 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM20_PIN
mbed_official 591:474d026f7d79 150 { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM21_PIN
mbed_official 591:474d026f7d79 151 };
mbed_official 591:474d026f7d79 152
mbed_official 591:474d026f7d79 153 static __IO uint8_t *TCR_MATCH[] = {
mbed_official 591:474d026f7d79 154 &MTU2TCR_0,
mbed_official 591:474d026f7d79 155 &MTU2TCR_1,
mbed_official 591:474d026f7d79 156 &MTU2TCR_2,
mbed_official 591:474d026f7d79 157 &MTU2TCR_3,
mbed_official 591:474d026f7d79 158 &MTU2TCR_4,
mbed_official 591:474d026f7d79 159 };
mbed_official 591:474d026f7d79 160
mbed_official 591:474d026f7d79 161 static __IO uint8_t *TIORH_MATCH[] = {
mbed_official 591:474d026f7d79 162 &MTU2TIORH_0,
mbed_official 591:474d026f7d79 163 &MTU2TIOR_1,
mbed_official 591:474d026f7d79 164 &MTU2TIOR_2,
mbed_official 591:474d026f7d79 165 &MTU2TIORH_3,
mbed_official 591:474d026f7d79 166 &MTU2TIORH_4,
mbed_official 591:474d026f7d79 167 };
mbed_official 591:474d026f7d79 168
mbed_official 591:474d026f7d79 169 static __IO uint8_t *TIORL_MATCH[] = {
mbed_official 591:474d026f7d79 170 &MTU2TIORL_0,
mbed_official 591:474d026f7d79 171 NULL,
mbed_official 591:474d026f7d79 172 NULL,
mbed_official 591:474d026f7d79 173 &MTU2TIORL_3,
mbed_official 591:474d026f7d79 174 &MTU2TIORL_4,
mbed_official 591:474d026f7d79 175 };
mbed_official 591:474d026f7d79 176
mbed_official 591:474d026f7d79 177 static __IO uint16_t *TGRA_MATCH[] = {
mbed_official 591:474d026f7d79 178 &MTU2TGRA_0,
mbed_official 591:474d026f7d79 179 &MTU2TGRA_1,
mbed_official 591:474d026f7d79 180 &MTU2TGRA_2,
mbed_official 591:474d026f7d79 181 &MTU2TGRA_3,
mbed_official 591:474d026f7d79 182 &MTU2TGRA_4,
mbed_official 591:474d026f7d79 183 };
mbed_official 591:474d026f7d79 184
mbed_official 591:474d026f7d79 185 static __IO uint16_t *TGRC_MATCH[] = {
mbed_official 591:474d026f7d79 186 &MTU2TGRC_0,
mbed_official 591:474d026f7d79 187 NULL,
mbed_official 591:474d026f7d79 188 NULL,
mbed_official 591:474d026f7d79 189 &MTU2TGRC_3,
mbed_official 591:474d026f7d79 190 &MTU2TGRC_4,
mbed_official 591:474d026f7d79 191 };
mbed_official 591:474d026f7d79 192
mbed_official 591:474d026f7d79 193 static __IO uint8_t *TMDR_MATCH[] = {
mbed_official 591:474d026f7d79 194 &MTU2TMDR_0,
mbed_official 591:474d026f7d79 195 &MTU2TMDR_1,
mbed_official 591:474d026f7d79 196 &MTU2TMDR_2,
mbed_official 591:474d026f7d79 197 &MTU2TMDR_3,
mbed_official 591:474d026f7d79 198 &MTU2TMDR_4,
mbed_official 591:474d026f7d79 199 };
mbed_official 591:474d026f7d79 200
mbed_official 591:474d026f7d79 201 static int MAX_PERIOD[] = {
mbed_official 591:474d026f7d79 202 125000,
mbed_official 591:474d026f7d79 203 503000,
mbed_official 591:474d026f7d79 204 2000000,
mbed_official 591:474d026f7d79 205 2000000,
mbed_official 591:474d026f7d79 206 2000000,
mbed_official 591:474d026f7d79 207 };
mbed_official 591:474d026f7d79 208
mbed_official 591:474d026f7d79 209 typedef enum {
mbed_official 591:474d026f7d79 210 MODE_PWM = 0,
mbed_official 591:474d026f7d79 211 MODE_MTU2
mbed_official 591:474d026f7d79 212 } PWMmode;
mbed_official 591:474d026f7d79 213
mbed_official 591:474d026f7d79 214 typedef enum {
mbed_official 591:474d026f7d79 215 MTU2_PULSE = 0,
mbed_official 591:474d026f7d79 216 MTU2_PERIOD
mbed_official 591:474d026f7d79 217 } MTU2Signal;
mbed_official 591:474d026f7d79 218
mbed_official 591:474d026f7d79 219 static int pwm_mode = MODE_PWM;
mbed_official 437:0b72c0f86db6 220 static uint16_t init_period_ch1 = 0;
mbed_official 437:0b72c0f86db6 221 static uint16_t init_period_ch2 = 0;
mbed_official 591:474d026f7d79 222 static uint16_t init_mtu2_period_ch[5] = {0};
mbed_official 441:d2c15dda23c1 223 static int32_t period_ch1 = 1;
mbed_official 441:d2c15dda23c1 224 static int32_t period_ch2 = 1;
mbed_official 591:474d026f7d79 225 static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
mbed_official 390:35c2c1cf29cd 226
mbed_official 390:35c2c1cf29cd 227 void pwmout_init(pwmout_t* obj, PinName pin) {
mbed_official 390:35c2c1cf29cd 228 // determine the channel
mbed_official 390:35c2c1cf29cd 229 PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
mbed_official 390:35c2c1cf29cd 230 MBED_ASSERT(pwm != (PWMName)NC);
mbed_official 390:35c2c1cf29cd 231
mbed_official 591:474d026f7d79 232 if (pwm >= MTU2_PWM_OFFSET) {
mbed_official 591:474d026f7d79 233 /* PWM by MTU2 */
mbed_official 591:474d026f7d79 234 int tmp_pwm;
mbed_official 591:474d026f7d79 235
mbed_official 591:474d026f7d79 236 pwm_mode = MODE_MTU2;
mbed_official 591:474d026f7d79 237 // power on
mbed_official 591:474d026f7d79 238 CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
mbed_official 591:474d026f7d79 239
mbed_official 591:474d026f7d79 240 obj->pwm = pwm;
mbed_official 591:474d026f7d79 241 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
mbed_official 591:474d026f7d79 242 if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
mbed_official 591:474d026f7d79 243 obj->ch = 4;
mbed_official 591:474d026f7d79 244 MTU2TOER |= 0x36;
mbed_official 591:474d026f7d79 245 } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
mbed_official 591:474d026f7d79 246 obj->ch = 3;
mbed_official 591:474d026f7d79 247 MTU2TOER |= 0x09;
mbed_official 591:474d026f7d79 248 } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
mbed_official 591:474d026f7d79 249 obj->ch = 2;
mbed_official 591:474d026f7d79 250 } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
mbed_official 591:474d026f7d79 251 obj->ch = 1;
mbed_official 591:474d026f7d79 252 } else {
mbed_official 591:474d026f7d79 253 obj->ch = 0;
mbed_official 591:474d026f7d79 254 }
mbed_official 591:474d026f7d79 255 // Wire pinout
mbed_official 591:474d026f7d79 256 pinmap_pinout(pin, PinMap_PWM);
mbed_official 591:474d026f7d79 257 // default duty 0.0f
mbed_official 591:474d026f7d79 258 pwmout_write(obj, 0);
mbed_official 591:474d026f7d79 259 if (init_mtu2_period_ch[obj->ch] == 0) {
mbed_official 591:474d026f7d79 260 // default period 1ms
mbed_official 591:474d026f7d79 261 pwmout_period_us(obj, 1000);
mbed_official 591:474d026f7d79 262 init_mtu2_period_ch[obj->ch] = 1;
mbed_official 591:474d026f7d79 263 }
mbed_official 437:0b72c0f86db6 264 } else {
mbed_official 591:474d026f7d79 265 /* PWM */
mbed_official 591:474d026f7d79 266 pwm_mode = MODE_PWM;
mbed_official 591:474d026f7d79 267 // power on
mbed_official 591:474d026f7d79 268 CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
mbed_official 437:0b72c0f86db6 269
mbed_official 591:474d026f7d79 270 obj->pwm = pwm;
mbed_official 591:474d026f7d79 271 if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
mbed_official 591:474d026f7d79 272 obj->ch = 2;
mbed_official 591:474d026f7d79 273 PWMPWPR_2_BYTE_L = 0x00;
mbed_official 591:474d026f7d79 274 } else {
mbed_official 591:474d026f7d79 275 obj->ch = 1;
mbed_official 591:474d026f7d79 276 PWMPWPR_1_BYTE_L = 0x00;
mbed_official 591:474d026f7d79 277 }
mbed_official 437:0b72c0f86db6 278
mbed_official 591:474d026f7d79 279 // Wire pinout
mbed_official 591:474d026f7d79 280 pinmap_pinout(pin, PinMap_PWM);
mbed_official 591:474d026f7d79 281
mbed_official 591:474d026f7d79 282 // default to 491us: standard for servos, and fine for e.g. brightness control
mbed_official 591:474d026f7d79 283 pwmout_write(obj, 0);
mbed_official 591:474d026f7d79 284 if ((obj->ch == 2) && (init_period_ch2 == 0)) {
mbed_official 591:474d026f7d79 285 pwmout_period_us(obj, 491);
mbed_official 591:474d026f7d79 286 init_period_ch2 = 1;
mbed_official 591:474d026f7d79 287 }
mbed_official 591:474d026f7d79 288 if ((obj->ch == 1) && (init_period_ch1 == 0)) {
mbed_official 591:474d026f7d79 289 pwmout_period_us(obj, 491);
mbed_official 591:474d026f7d79 290 init_period_ch1 = 1;
mbed_official 591:474d026f7d79 291 }
mbed_official 437:0b72c0f86db6 292 }
mbed_official 390:35c2c1cf29cd 293 }
mbed_official 390:35c2c1cf29cd 294
mbed_official 390:35c2c1cf29cd 295 void pwmout_free(pwmout_t* obj) {
mbed_official 437:0b72c0f86db6 296 pwmout_write(obj, 0);
mbed_official 390:35c2c1cf29cd 297 }
mbed_official 390:35c2c1cf29cd 298
mbed_official 390:35c2c1cf29cd 299 void pwmout_write(pwmout_t* obj, float value) {
mbed_official 437:0b72c0f86db6 300 uint32_t wk_cycle;
mbed_official 437:0b72c0f86db6 301 uint16_t v;
mbed_official 437:0b72c0f86db6 302
mbed_official 591:474d026f7d79 303 if (pwm_mode == MODE_MTU2) {
mbed_official 591:474d026f7d79 304 /* PWM by MTU2 */
mbed_official 591:474d026f7d79 305 int tmp_pwm;
mbed_official 591:474d026f7d79 306
mbed_official 591:474d026f7d79 307 if (value < 0.0f) {
mbed_official 591:474d026f7d79 308 value = 0.0f;
mbed_official 591:474d026f7d79 309 } else if (value > 1.0f) {
mbed_official 591:474d026f7d79 310 value = 1.0f;
mbed_official 591:474d026f7d79 311 } else {
mbed_official 591:474d026f7d79 312 // Do Nothing
mbed_official 591:474d026f7d79 313 }
mbed_official 591:474d026f7d79 314 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
mbed_official 591:474d026f7d79 315 wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
mbed_official 591:474d026f7d79 316 // set channel match to percentage
mbed_official 591:474d026f7d79 317 *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
mbed_official 437:0b72c0f86db6 318 } else {
mbed_official 591:474d026f7d79 319 /* PWM */
mbed_official 591:474d026f7d79 320 if (value < 0.0f) {
mbed_official 591:474d026f7d79 321 value = 0.0f;
mbed_official 591:474d026f7d79 322 } else if (value > 1.0f) {
mbed_official 591:474d026f7d79 323 value = 1.0f;
mbed_official 591:474d026f7d79 324 } else {
mbed_official 591:474d026f7d79 325 // Do Nothing
mbed_official 591:474d026f7d79 326 }
mbed_official 437:0b72c0f86db6 327
mbed_official 591:474d026f7d79 328 if (obj->ch == 2) {
mbed_official 591:474d026f7d79 329 wk_cycle = PWMPWCYR_2 & 0x03ff;
mbed_official 591:474d026f7d79 330 } else {
mbed_official 591:474d026f7d79 331 wk_cycle = PWMPWCYR_1 & 0x03ff;
mbed_official 591:474d026f7d79 332 }
mbed_official 591:474d026f7d79 333
mbed_official 591:474d026f7d79 334 // set channel match to percentage
mbed_official 591:474d026f7d79 335 v = (uint16_t)((float)wk_cycle * value);
mbed_official 591:474d026f7d79 336 *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
mbed_official 437:0b72c0f86db6 337 }
mbed_official 390:35c2c1cf29cd 338 }
mbed_official 390:35c2c1cf29cd 339
mbed_official 390:35c2c1cf29cd 340 float pwmout_read(pwmout_t* obj) {
mbed_official 437:0b72c0f86db6 341 uint32_t wk_cycle;
mbed_official 437:0b72c0f86db6 342 float value;
mbed_official 437:0b72c0f86db6 343
mbed_official 591:474d026f7d79 344 if (pwm_mode == MODE_MTU2) {
mbed_official 591:474d026f7d79 345 /* PWM by MTU2 */
mbed_official 591:474d026f7d79 346 uint32_t wk_pulse;
mbed_official 591:474d026f7d79 347 int tmp_pwm;
mbed_official 591:474d026f7d79 348
mbed_official 591:474d026f7d79 349 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
mbed_official 591:474d026f7d79 350 wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
mbed_official 591:474d026f7d79 351 wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
mbed_official 591:474d026f7d79 352 value = ((float)wk_pulse / (float)wk_cycle);
mbed_official 437:0b72c0f86db6 353 } else {
mbed_official 591:474d026f7d79 354 /* PWM */
mbed_official 591:474d026f7d79 355 if (obj->ch == 2) {
mbed_official 591:474d026f7d79 356 wk_cycle = PWMPWCYR_2 & 0x03ff;
mbed_official 591:474d026f7d79 357 } else {
mbed_official 591:474d026f7d79 358 wk_cycle = PWMPWCYR_1 & 0x03ff;
mbed_official 591:474d026f7d79 359 }
mbed_official 591:474d026f7d79 360 value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
mbed_official 437:0b72c0f86db6 361 }
mbed_official 437:0b72c0f86db6 362
mbed_official 437:0b72c0f86db6 363 return (value > 1.0f) ? (1.0f) : (value);
mbed_official 390:35c2c1cf29cd 364 }
mbed_official 390:35c2c1cf29cd 365
mbed_official 390:35c2c1cf29cd 366 void pwmout_period(pwmout_t* obj, float seconds) {
mbed_official 390:35c2c1cf29cd 367 pwmout_period_us(obj, seconds * 1000000.0f);
mbed_official 390:35c2c1cf29cd 368 }
mbed_official 390:35c2c1cf29cd 369
mbed_official 390:35c2c1cf29cd 370 void pwmout_period_ms(pwmout_t* obj, int ms) {
mbed_official 390:35c2c1cf29cd 371 pwmout_period_us(obj, ms * 1000);
mbed_official 390:35c2c1cf29cd 372 }
mbed_official 390:35c2c1cf29cd 373
mbed_official 437:0b72c0f86db6 374 static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
mbed_official 437:0b72c0f86db6 375 uint16_t wk_pwmpbfr;
mbed_official 437:0b72c0f86db6 376 float value;
mbed_official 437:0b72c0f86db6 377 uint16_t v;
mbed_official 437:0b72c0f86db6 378
mbed_official 437:0b72c0f86db6 379 wk_pwmpbfr = *p_pwmpbfr;
mbed_official 437:0b72c0f86db6 380 value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
mbed_official 437:0b72c0f86db6 381 v = (uint16_t)((float)new_cycle * value);
mbed_official 437:0b72c0f86db6 382 *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
mbed_official 437:0b72c0f86db6 383 }
mbed_official 437:0b72c0f86db6 384
mbed_official 591:474d026f7d79 385 static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
mbed_official 591:474d026f7d79 386 uint16_t wk_pwmpbfr;
mbed_official 591:474d026f7d79 387 float value;
mbed_official 591:474d026f7d79 388
mbed_official 591:474d026f7d79 389 wk_pwmpbfr = *p_pwmpbfr;
mbed_official 591:474d026f7d79 390 value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
mbed_official 591:474d026f7d79 391 *p_pwmpbfr = (uint16_t)((float)new_cycle * value);
mbed_official 591:474d026f7d79 392 }
mbed_official 591:474d026f7d79 393
mbed_official 390:35c2c1cf29cd 394 // Set the PWM period, keeping the duty cycle the same.
mbed_official 390:35c2c1cf29cd 395 void pwmout_period_us(pwmout_t* obj, int us) {
mbed_official 591:474d026f7d79 396 uint64_t wk_cycle_mtu2;
mbed_official 437:0b72c0f86db6 397 uint32_t pclk_base;
mbed_official 437:0b72c0f86db6 398 uint32_t wk_cycle;
mbed_official 591:474d026f7d79 399 uint32_t wk_cks = 0;
mbed_official 437:0b72c0f86db6 400 uint16_t wk_last_cycle;
mbed_official 591:474d026f7d79 401 int max_us = 0;
mbed_official 437:0b72c0f86db6 402
mbed_official 591:474d026f7d79 403 if (pwm_mode == MODE_MTU2) {
mbed_official 591:474d026f7d79 404 /* PWM by MTU2 */
mbed_official 591:474d026f7d79 405 int tmp_pwm;
mbed_official 591:474d026f7d79 406 uint16_t tmp_tgra;
mbed_official 591:474d026f7d79 407 uint16_t tmp_tgrc;
mbed_official 591:474d026f7d79 408 uint8_t tmp_tcr_up;
mbed_official 591:474d026f7d79 409 uint8_t tmp_tstr_sp;
mbed_official 591:474d026f7d79 410 uint8_t tmp_tstr_st;
mbed_official 591:474d026f7d79 411
mbed_official 591:474d026f7d79 412 max_us = MAX_PERIOD[obj->ch];
mbed_official 591:474d026f7d79 413 if (us > max_us) {
mbed_official 591:474d026f7d79 414 us = max_us;
mbed_official 591:474d026f7d79 415 } else if (us < 1) {
mbed_official 591:474d026f7d79 416 us = 1;
mbed_official 591:474d026f7d79 417 } else {
mbed_official 591:474d026f7d79 418 // Do Nothing
mbed_official 591:474d026f7d79 419 }
mbed_official 390:35c2c1cf29cd 420
mbed_official 591:474d026f7d79 421 if (RZ_A1_IsClockMode0() == false) {
mbed_official 591:474d026f7d79 422 pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
mbed_official 591:474d026f7d79 423 } else {
mbed_official 591:474d026f7d79 424 pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
mbed_official 591:474d026f7d79 425 }
mbed_official 437:0b72c0f86db6 426
mbed_official 591:474d026f7d79 427 wk_cycle_mtu2 = (uint64_t)pclk_base * us;
mbed_official 591:474d026f7d79 428 while (wk_cycle_mtu2 >= 65535000000) {
mbed_official 591:474d026f7d79 429 if ((obj->ch == 1) && (wk_cks == 3)) {
mbed_official 591:474d026f7d79 430 wk_cks+=2;
mbed_official 591:474d026f7d79 431 } else if ((obj->ch == 2) && (wk_cks == 3)) {
mbed_official 591:474d026f7d79 432 wk_cycle_mtu2 >>= 2;
mbed_official 591:474d026f7d79 433 wk_cks+=3;
mbed_official 591:474d026f7d79 434 }
mbed_official 591:474d026f7d79 435 wk_cycle_mtu2 >>= 2;
mbed_official 591:474d026f7d79 436 wk_cks++;
mbed_official 591:474d026f7d79 437 }
mbed_official 591:474d026f7d79 438 wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
mbed_official 591:474d026f7d79 439
mbed_official 591:474d026f7d79 440 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
mbed_official 591:474d026f7d79 441 if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
mbed_official 591:474d026f7d79 442 tmp_tcr_up = 0xC0;
mbed_official 591:474d026f7d79 443 } else {
mbed_official 591:474d026f7d79 444 tmp_tcr_up = 0x40;
mbed_official 591:474d026f7d79 445 }
mbed_official 591:474d026f7d79 446 if ((obj->ch == 4) || (obj->ch == 3)) {
mbed_official 591:474d026f7d79 447 tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
mbed_official 591:474d026f7d79 448 tmp_tstr_st = (1 << (obj->ch + 3));
mbed_official 591:474d026f7d79 449 } else {
mbed_official 591:474d026f7d79 450 tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
mbed_official 591:474d026f7d79 451 tmp_tstr_st = (1 << obj->ch);
mbed_official 591:474d026f7d79 452 }
mbed_official 591:474d026f7d79 453 // Counter Stop
mbed_official 591:474d026f7d79 454 MTU2TSTR &= tmp_tstr_sp;
mbed_official 591:474d026f7d79 455 wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
mbed_official 591:474d026f7d79 456 *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
mbed_official 591:474d026f7d79 457 *TIORH_MATCH[obj->ch] = 0x21;
mbed_official 591:474d026f7d79 458 if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
mbed_official 591:474d026f7d79 459 *TIORL_MATCH[obj->ch] = 0x21;
mbed_official 591:474d026f7d79 460 }
mbed_official 591:474d026f7d79 461 *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period
mbed_official 390:35c2c1cf29cd 462
mbed_official 591:474d026f7d79 463 // Set duty again(TGRA)
mbed_official 591:474d026f7d79 464 tmp_tgra = *TGRA_MATCH[obj->ch];
mbed_official 591:474d026f7d79 465 set_mtu2_duty_again(&tmp_tgra, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 466 if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
mbed_official 591:474d026f7d79 467 // Set duty again(TGRC)
mbed_official 591:474d026f7d79 468 tmp_tgrc = *TGRC_MATCH[obj->ch];
mbed_official 591:474d026f7d79 469 set_mtu2_duty_again(&tmp_tgrc, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 470 }
mbed_official 591:474d026f7d79 471 *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1
mbed_official 390:35c2c1cf29cd 472
mbed_official 437:0b72c0f86db6 473 // Counter Start
mbed_official 591:474d026f7d79 474 MTU2TSTR |= tmp_tstr_st;
mbed_official 441:d2c15dda23c1 475 // Save for future use
mbed_official 591:474d026f7d79 476 mtu2_period_ch[obj->ch] = us;
mbed_official 437:0b72c0f86db6 477 } else {
mbed_official 591:474d026f7d79 478 /* PWM */
mbed_official 591:474d026f7d79 479 if (us > 491) {
mbed_official 591:474d026f7d79 480 us = 491;
mbed_official 591:474d026f7d79 481 } else if (us < 1) {
mbed_official 591:474d026f7d79 482 us = 1;
mbed_official 591:474d026f7d79 483 } else {
mbed_official 591:474d026f7d79 484 // Do Nothing
mbed_official 591:474d026f7d79 485 }
mbed_official 591:474d026f7d79 486
mbed_official 591:474d026f7d79 487 if (RZ_A1_IsClockMode0() == false) {
mbed_official 591:474d026f7d79 488 pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
mbed_official 591:474d026f7d79 489 } else {
mbed_official 591:474d026f7d79 490 pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
mbed_official 591:474d026f7d79 491 }
mbed_official 591:474d026f7d79 492
mbed_official 591:474d026f7d79 493 wk_cycle = pclk_base * us;
mbed_official 591:474d026f7d79 494 while (wk_cycle >= 102350) {
mbed_official 591:474d026f7d79 495 wk_cycle >>= 1;
mbed_official 591:474d026f7d79 496 wk_cks++;
mbed_official 591:474d026f7d79 497 }
mbed_official 591:474d026f7d79 498 wk_cycle = (wk_cycle + 50) / 100;
mbed_official 390:35c2c1cf29cd 499
mbed_official 591:474d026f7d79 500 if (obj->ch == 2) {
mbed_official 591:474d026f7d79 501 wk_last_cycle = PWMPWCYR_2 & 0x03ff;
mbed_official 591:474d026f7d79 502 PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
mbed_official 591:474d026f7d79 503 PWMPWCYR_2 = (uint16_t)wk_cycle;
mbed_official 591:474d026f7d79 504
mbed_official 591:474d026f7d79 505 // Set duty again
mbed_official 591:474d026f7d79 506 set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 507 set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 508 set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 509 set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 510
mbed_official 591:474d026f7d79 511 // Counter Start
mbed_official 591:474d026f7d79 512 PWMPWCR_2_BYTE_L |= 0x08;
mbed_official 437:0b72c0f86db6 513
mbed_official 591:474d026f7d79 514 // Save for future use
mbed_official 591:474d026f7d79 515 period_ch2 = us;
mbed_official 591:474d026f7d79 516 } else {
mbed_official 591:474d026f7d79 517 wk_last_cycle = PWMPWCYR_1 & 0x03ff;
mbed_official 591:474d026f7d79 518 PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
mbed_official 591:474d026f7d79 519 PWMPWCYR_1 = (uint16_t)wk_cycle;
mbed_official 441:d2c15dda23c1 520
mbed_official 591:474d026f7d79 521 // Set duty again
mbed_official 591:474d026f7d79 522 set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 523 set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 524 set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 525 set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
mbed_official 591:474d026f7d79 526
mbed_official 591:474d026f7d79 527 // Counter Start
mbed_official 591:474d026f7d79 528 PWMPWCR_1_BYTE_L |= 0x08;
mbed_official 591:474d026f7d79 529
mbed_official 591:474d026f7d79 530 // Save for future use
mbed_official 591:474d026f7d79 531 period_ch1 = us;
mbed_official 591:474d026f7d79 532 }
mbed_official 437:0b72c0f86db6 533 }
mbed_official 390:35c2c1cf29cd 534 }
mbed_official 390:35c2c1cf29cd 535
mbed_official 390:35c2c1cf29cd 536 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
mbed_official 390:35c2c1cf29cd 537 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
mbed_official 390:35c2c1cf29cd 538 }
mbed_official 390:35c2c1cf29cd 539
mbed_official 390:35c2c1cf29cd 540 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
mbed_official 390:35c2c1cf29cd 541 pwmout_pulsewidth_us(obj, ms * 1000);
mbed_official 390:35c2c1cf29cd 542 }
mbed_official 390:35c2c1cf29cd 543
mbed_official 390:35c2c1cf29cd 544 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
mbed_official 441:d2c15dda23c1 545 float value = 0;
mbed_official 441:d2c15dda23c1 546
mbed_official 591:474d026f7d79 547 if (pwm_mode == MODE_MTU2) {
mbed_official 591:474d026f7d79 548 /* PWM by MTU2 */
mbed_official 591:474d026f7d79 549 if (mtu2_period_ch[obj->ch] != 0) {
mbed_official 591:474d026f7d79 550 value = (float)us / (float)mtu2_period_ch[obj->ch];
mbed_official 441:d2c15dda23c1 551 }
mbed_official 441:d2c15dda23c1 552 } else {
mbed_official 591:474d026f7d79 553 /* PWM */
mbed_official 591:474d026f7d79 554 if (obj->ch == 2) {
mbed_official 591:474d026f7d79 555 if (period_ch2 != 0) {
mbed_official 591:474d026f7d79 556 value = (float)us / (float)period_ch2;
mbed_official 591:474d026f7d79 557 }
mbed_official 591:474d026f7d79 558 } else {
mbed_official 591:474d026f7d79 559 if (period_ch1 != 0) {
mbed_official 591:474d026f7d79 560 value = (float)us / (float)period_ch1;
mbed_official 591:474d026f7d79 561 }
mbed_official 441:d2c15dda23c1 562 }
mbed_official 591:474d026f7d79 563
mbed_official 591:474d026f7d79 564 pwmout_write(obj, value);
mbed_official 441:d2c15dda23c1 565 }
mbed_official 390:35c2c1cf29cd 566 }