steven niu / Mbed 2 deprecated LP1768-lowpower_test

a test code to implement and test LP1768 power control mode

Dependencies:   mbed

This code implemented some LP1768 power mode : Sleep(), DeepSleep(), PowerDown(), DeepPowerDown(), BOGD_PowerDown(). It also has a test code to test these power modes and wakeup using watch dog. The wakeup part is based on Erik's code but add implementation for LP1768. As LP1768 has debug enabled in default, it cannot be waked up in DeepSleep mode. Therefore this code use WDC reset to wake up the chips from deep sleep. The test code also allow test the power under two clock frequency (96 MHz and 48MHz). Inspired by Paul and Michael Wang, I also tested the power reduction by power off PHY. The analysis could be found in http://mbed.org/users/steniu01/notebook/lp1768-power-mode-implementation-and-measurement-/#

PowerControl/EthernetPowerControl.h@2:15d9501bf5b3, 2014-08-02 (annotated)

Committer:
steniu01
Date:
Sat Aug 02 16:01:23 2014 +0000
Revision:
2:15d9501bf5b3
Parent:
1:571258908570 
a test code to test LP1768 power mode.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 0:5c4169623549 1 /* mbed PowerControl Library
steniu01 0:5c4169623549 2 * Copyright (c) 2010 Michael Wei
steniu01 0:5c4169623549 3 */
steniu01 0:5c4169623549 4
steniu01 0:5c4169623549 5 #ifndef MBED_POWERCONTROL_ETH_H
steniu01 0:5c4169623549 6 #define MBED_POWERCONTROL_ETH_H
steniu01 0:5c4169623549 7
steniu01 0:5c4169623549 8 #include "mbed.h"
steniu01 0:5c4169623549 9 #include "PowerControl.h"
steniu01 0:5c4169623549 10
steniu01 0:5c4169623549 11 #define PHY_REG_BMCR_POWERDOWN 0xB
steniu01 0:5c4169623549 12 #define PHY_REG_EDCR_ENABLE 0xF
steniu01 0:5c4169623549 13
steniu01 0:5c4169623549 14
steniu01 0:5c4169623549 15 void EMAC_Init();
steniu01 1:571258908570 16 unsigned short read_PHY (unsigned int PhyReg);
steniu01 1:571258908570 17 void write_PHY (unsigned int PhyReg, unsigned short Value);
steniu01 0:5c4169623549 18
steniu01 0:5c4169623549 19 void PHY_PowerDown(void);
steniu01 0:5c4169623549 20 void PHY_PowerUp(void);
steniu01 0:5c4169623549 21 void PHY_EnergyDetect_Enable(void);
steniu01 0:5c4169623549 22 void PHY_EnergyDetect_Disable(void);
steniu01 0:5c4169623549 23
steniu01 0:5c4169623549 24 //From NXP Sample Code .... Probably from KEIL sample code
steniu01 0:5c4169623549 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
steniu01 0:5c4169623549 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
steniu01 0:5c4169623549 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
steniu01 0:5c4169623549 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
steniu01 0:5c4169623549 29
steniu01 0:5c4169623549 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
steniu01 0:5c4169623549 31
steniu01 0:5c4169623549 32 /* EMAC variables located in 16K Ethernet SRAM */
steniu01 0:5c4169623549 33 #define RX_DESC_BASE 0x20080000
steniu01 0:5c4169623549 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
steniu01 0:5c4169623549 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
steniu01 0:5c4169623549 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
steniu01 0:5c4169623549 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
steniu01 0:5c4169623549 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
steniu01 0:5c4169623549 39
steniu01 0:5c4169623549 40 /* RX and TX descriptor and status definitions. */
steniu01 0:5c4169623549 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
steniu01 0:5c4169623549 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
steniu01 0:5c4169623549 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
steniu01 0:5c4169623549 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
steniu01 0:5c4169623549 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
steniu01 0:5c4169623549 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
steniu01 0:5c4169623549 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
steniu01 0:5c4169623549 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
steniu01 0:5c4169623549 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
steniu01 0:5c4169623549 50
steniu01 0:5c4169623549 51 /* MAC Configuration Register 1 */
steniu01 0:5c4169623549 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
steniu01 0:5c4169623549 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
steniu01 0:5c4169623549 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
steniu01 0:5c4169623549 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
steniu01 0:5c4169623549 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
steniu01 0:5c4169623549 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
steniu01 0:5c4169623549 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
steniu01 0:5c4169623549 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
steniu01 0:5c4169623549 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
steniu01 0:5c4169623549 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
steniu01 0:5c4169623549 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
steniu01 0:5c4169623549 63
steniu01 0:5c4169623549 64 /* MAC Configuration Register 2 */
steniu01 0:5c4169623549 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
steniu01 0:5c4169623549 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
steniu01 0:5c4169623549 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
steniu01 0:5c4169623549 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
steniu01 0:5c4169623549 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
steniu01 0:5c4169623549 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
steniu01 0:5c4169623549 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
steniu01 0:5c4169623549 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
steniu01 0:5c4169623549 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
steniu01 0:5c4169623549 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
steniu01 0:5c4169623549 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
steniu01 0:5c4169623549 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
steniu01 0:5c4169623549 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
steniu01 0:5c4169623549 78
steniu01 0:5c4169623549 79 /* Back-to-Back Inter-Packet-Gap Register */
steniu01 0:5c4169623549 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
steniu01 0:5c4169623549 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
steniu01 0:5c4169623549 82
steniu01 0:5c4169623549 83 /* Non Back-to-Back Inter-Packet-Gap Register */
steniu01 0:5c4169623549 84 #define IPGR_DEF 0x00000012 /* Recommended value */
steniu01 0:5c4169623549 85
steniu01 0:5c4169623549 86 /* Collision Window/Retry Register */
steniu01 0:5c4169623549 87 #define CLRT_DEF 0x0000370F /* Default value */
steniu01 0:5c4169623549 88
steniu01 0:5c4169623549 89 /* PHY Support Register */
steniu01 0:5c4169623549 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
steniu01 0:5c4169623549 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
steniu01 0:5c4169623549 92
steniu01 0:5c4169623549 93 /* Test Register */
steniu01 0:5c4169623549 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
steniu01 0:5c4169623549 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
steniu01 0:5c4169623549 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
steniu01 0:5c4169623549 97
steniu01 0:5c4169623549 98 /* MII Management Configuration Register */
steniu01 0:5c4169623549 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
steniu01 0:5c4169623549 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
steniu01 0:5c4169623549 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
steniu01 0:5c4169623549 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
steniu01 0:5c4169623549 103
steniu01 0:5c4169623549 104 /* MII Management Command Register */
steniu01 0:5c4169623549 105 #define MCMD_READ 0x00000001 /* MII Read */
steniu01 0:5c4169623549 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
steniu01 0:5c4169623549 107
steniu01 0:5c4169623549 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
steniu01 0:5c4169623549 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
steniu01 0:5c4169623549 110
steniu01 0:5c4169623549 111 /* MII Management Address Register */
steniu01 0:5c4169623549 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
steniu01 0:5c4169623549 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
steniu01 0:5c4169623549 114
steniu01 0:5c4169623549 115 /* MII Management Indicators Register */
steniu01 0:5c4169623549 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
steniu01 0:5c4169623549 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
steniu01 0:5c4169623549 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
steniu01 0:5c4169623549 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
steniu01 0:5c4169623549 120
steniu01 0:5c4169623549 121 /* Command Register */
steniu01 0:5c4169623549 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
steniu01 0:5c4169623549 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
steniu01 0:5c4169623549 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
steniu01 0:5c4169623549 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
steniu01 0:5c4169623549 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
steniu01 0:5c4169623549 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
steniu01 0:5c4169623549 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
steniu01 0:5c4169623549 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
steniu01 0:5c4169623549 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
steniu01 0:5c4169623549 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
steniu01 0:5c4169623549 132
steniu01 0:5c4169623549 133 /* Status Register */
steniu01 0:5c4169623549 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
steniu01 0:5c4169623549 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
steniu01 0:5c4169623549 136
steniu01 0:5c4169623549 137 /* Transmit Status Vector 0 Register */
steniu01 0:5c4169623549 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
steniu01 0:5c4169623549 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
steniu01 0:5c4169623549 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
steniu01 0:5c4169623549 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
steniu01 0:5c4169623549 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
steniu01 0:5c4169623549 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
steniu01 0:5c4169623549 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
steniu01 0:5c4169623549 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
steniu01 0:5c4169623549 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
steniu01 0:5c4169623549 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
steniu01 0:5c4169623549 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
steniu01 0:5c4169623549 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
steniu01 0:5c4169623549 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
steniu01 0:5c4169623549 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
steniu01 0:5c4169623549 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
steniu01 0:5c4169623549 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
steniu01 0:5c4169623549 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
steniu01 0:5c4169623549 155
steniu01 0:5c4169623549 156 /* Transmit Status Vector 1 Register */
steniu01 0:5c4169623549 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
steniu01 0:5c4169623549 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
steniu01 0:5c4169623549 159
steniu01 0:5c4169623549 160 /* Receive Status Vector Register */
steniu01 0:5c4169623549 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
steniu01 0:5c4169623549 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
steniu01 0:5c4169623549 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
steniu01 0:5c4169623549 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
steniu01 0:5c4169623549 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
steniu01 0:5c4169623549 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
steniu01 0:5c4169623549 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
steniu01 0:5c4169623549 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
steniu01 0:5c4169623549 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
steniu01 0:5c4169623549 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
steniu01 0:5c4169623549 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
steniu01 0:5c4169623549 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
steniu01 0:5c4169623549 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
steniu01 0:5c4169623549 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
steniu01 0:5c4169623549 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
steniu01 0:5c4169623549 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
steniu01 0:5c4169623549 177
steniu01 0:5c4169623549 178 /* Flow Control Counter Register */
steniu01 0:5c4169623549 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
steniu01 0:5c4169623549 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
steniu01 0:5c4169623549 181
steniu01 0:5c4169623549 182 /* Flow Control Status Register */
steniu01 0:5c4169623549 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
steniu01 0:5c4169623549 184
steniu01 0:5c4169623549 185 /* Receive Filter Control Register */
steniu01 0:5c4169623549 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
steniu01 0:5c4169623549 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
steniu01 0:5c4169623549 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
steniu01 0:5c4169623549 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
steniu01 0:5c4169623549 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
steniu01 0:5c4169623549 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
steniu01 0:5c4169623549 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
steniu01 0:5c4169623549 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
steniu01 0:5c4169623549 194
steniu01 0:5c4169623549 195 /* Receive Filter WoL Status/Clear Registers */
steniu01 0:5c4169623549 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
steniu01 0:5c4169623549 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
steniu01 0:5c4169623549 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
steniu01 0:5c4169623549 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
steniu01 0:5c4169623549 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
steniu01 0:5c4169623549 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
steniu01 0:5c4169623549 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
steniu01 0:5c4169623549 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
steniu01 0:5c4169623549 204
steniu01 0:5c4169623549 205 /* Interrupt Status/Enable/Clear/Set Registers */
steniu01 0:5c4169623549 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
steniu01 0:5c4169623549 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
steniu01 0:5c4169623549 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
steniu01 0:5c4169623549 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
steniu01 0:5c4169623549 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
steniu01 0:5c4169623549 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
steniu01 0:5c4169623549 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
steniu01 0:5c4169623549 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
steniu01 0:5c4169623549 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
steniu01 0:5c4169623549 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
steniu01 0:5c4169623549 216
steniu01 0:5c4169623549 217 /* Power Down Register */
steniu01 0:5c4169623549 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
steniu01 0:5c4169623549 219
steniu01 0:5c4169623549 220 /* RX Descriptor Control Word */
steniu01 0:5c4169623549 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
steniu01 0:5c4169623549 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
steniu01 0:5c4169623549 223
steniu01 0:5c4169623549 224 /* RX Status Hash CRC Word */
steniu01 0:5c4169623549 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
steniu01 0:5c4169623549 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
steniu01 0:5c4169623549 227
steniu01 0:5c4169623549 228 /* RX Status Information Word */
steniu01 0:5c4169623549 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
steniu01 0:5c4169623549 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
steniu01 0:5c4169623549 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
steniu01 0:5c4169623549 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
steniu01 0:5c4169623549 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
steniu01 0:5c4169623549 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
steniu01 0:5c4169623549 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
steniu01 0:5c4169623549 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
steniu01 0:5c4169623549 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
steniu01 0:5c4169623549 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
steniu01 0:5c4169623549 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
steniu01 0:5c4169623549 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
steniu01 0:5c4169623549 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
steniu01 0:5c4169623549 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
steniu01 0:5c4169623549 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
steniu01 0:5c4169623549 244
steniu01 0:5c4169623549 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
steniu01 0:5c4169623549 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
steniu01 0:5c4169623549 247
steniu01 0:5c4169623549 248 /* TX Descriptor Control Word */
steniu01 0:5c4169623549 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
steniu01 0:5c4169623549 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
steniu01 0:5c4169623549 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
steniu01 0:5c4169623549 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
steniu01 0:5c4169623549 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
steniu01 0:5c4169623549 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
steniu01 0:5c4169623549 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
steniu01 0:5c4169623549 256
steniu01 0:5c4169623549 257 /* TX Status Information Word */
steniu01 0:5c4169623549 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
steniu01 0:5c4169623549 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
steniu01 0:5c4169623549 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
steniu01 0:5c4169623549 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
steniu01 0:5c4169623549 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
steniu01 0:5c4169623549 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
steniu01 0:5c4169623549 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
steniu01 0:5c4169623549 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
steniu01 0:5c4169623549 266
steniu01 0:5c4169623549 267 /* DP83848C PHY Registers */
steniu01 0:5c4169623549 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
steniu01 0:5c4169623549 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
steniu01 0:5c4169623549 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
steniu01 0:5c4169623549 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
steniu01 0:5c4169623549 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
steniu01 0:5c4169623549 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
steniu01 0:5c4169623549 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
steniu01 0:5c4169623549 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
steniu01 0:5c4169623549 276
steniu01 0:5c4169623549 277 /* PHY Extended Registers */
steniu01 0:5c4169623549 278 #define PHY_REG_STS 0x10 /* Status Register */
steniu01 0:5c4169623549 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
steniu01 0:5c4169623549 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
steniu01 0:5c4169623549 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
steniu01 0:5c4169623549 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
steniu01 0:5c4169623549 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
steniu01 0:5c4169623549 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
steniu01 0:5c4169623549 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
steniu01 0:5c4169623549 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
steniu01 0:5c4169623549 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
steniu01 0:5c4169623549 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
steniu01 0:5c4169623549 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
steniu01 0:5c4169623549 290
steniu01 0:5c4169623549 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
steniu01 0:5c4169623549 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
steniu01 0:5c4169623549 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
steniu01 0:5c4169623549 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
steniu01 0:5c4169623549 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
steniu01 0:5c4169623549 296
steniu01 0:5c4169623549 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
steniu01 0:5c4169623549 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
steniu01 0:5c4169623549 299 #endif