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LPC1768/GCC_ARM/core_cmFunc.h@27:7110ebee3484, 2011-11-29 (annotated)

Committer:
emilmont
Date:
Tue Nov 29 14:59:27 2011 +0000
Revision:
27:7110ebee3484
Child:
33:5364839841bd
New Libraries 11.11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file core_cmFunc.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 27:7110ebee3484 4 * @version V2.01
emilmont 27:7110ebee3484 5 * @date 06. December 2010
emilmont 27:7110ebee3484 6 *
emilmont 27:7110ebee3484 7 * @note
emilmont 27:7110ebee3484 8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 9 *
emilmont 27:7110ebee3484 10 * @par
emilmont 27:7110ebee3484 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 27:7110ebee3484 12 * processor based microcontrollers. This file can be freely distributed
emilmont 27:7110ebee3484 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * @par
emilmont 27:7110ebee3484 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 21 *
emilmont 27:7110ebee3484 22 ******************************************************************************/
emilmont 27:7110ebee3484 23
emilmont 27:7110ebee3484 24 #ifndef __CORE_CMFUNC_H__
emilmont 27:7110ebee3484 25 #define __CORE_CMFUNC_H__
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27 /* ########################### Core Function Access ########################### */
emilmont 27:7110ebee3484 28 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 27:7110ebee3484 29 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 27:7110ebee3484 30 @{
emilmont 27:7110ebee3484 31 */
emilmont 27:7110ebee3484 32
emilmont 27:7110ebee3484 33 #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
emilmont 27:7110ebee3484 34 /* ARM armcc specific functions */
emilmont 27:7110ebee3484 35
emilmont 27:7110ebee3484 36 /* intrinsic void __enable_irq(); */
emilmont 27:7110ebee3484 37 /* intrinsic void __disable_irq(); */
emilmont 27:7110ebee3484 38
emilmont 27:7110ebee3484 39 /** \brief Get Control Register
emilmont 27:7110ebee3484 40
emilmont 27:7110ebee3484 41 This function returns the content of the Control Register.
emilmont 27:7110ebee3484 42
emilmont 27:7110ebee3484 43 \return Control Register value
emilmont 27:7110ebee3484 44 */
emilmont 27:7110ebee3484 45 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 46 extern uint32_t __get_CONTROL(void);
emilmont 27:7110ebee3484 47 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 48 static __INLINE uint32_t __get_CONTROL(void)
emilmont 27:7110ebee3484 49 {
emilmont 27:7110ebee3484 50 register uint32_t __regControl __ASM("control");
emilmont 27:7110ebee3484 51 return(__regControl);
emilmont 27:7110ebee3484 52 }
emilmont 27:7110ebee3484 53 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 54
emilmont 27:7110ebee3484 55
emilmont 27:7110ebee3484 56 /** \brief Set Control Register
emilmont 27:7110ebee3484 57
emilmont 27:7110ebee3484 58 This function writes the given value to the Control Register.
emilmont 27:7110ebee3484 59
emilmont 27:7110ebee3484 60 \param [in] control Control Register value to set
emilmont 27:7110ebee3484 61 */
emilmont 27:7110ebee3484 62 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 63 extern void __set_CONTROL(uint32_t control);
emilmont 27:7110ebee3484 64 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 65 static __INLINE void __set_CONTROL(uint32_t control)
emilmont 27:7110ebee3484 66 {
emilmont 27:7110ebee3484 67 register uint32_t __regControl __ASM("control");
emilmont 27:7110ebee3484 68 __regControl = control;
emilmont 27:7110ebee3484 69 }
emilmont 27:7110ebee3484 70 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 71
emilmont 27:7110ebee3484 72
emilmont 27:7110ebee3484 73 /** \brief Get ISPR Register
emilmont 27:7110ebee3484 74
emilmont 27:7110ebee3484 75 This function returns the content of the ISPR Register.
emilmont 27:7110ebee3484 76
emilmont 27:7110ebee3484 77 \return ISPR Register value
emilmont 27:7110ebee3484 78 */
emilmont 27:7110ebee3484 79 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 80 extern uint32_t __get_IPSR(void);
emilmont 27:7110ebee3484 81 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 82 static __INLINE uint32_t __get_IPSR(void)
emilmont 27:7110ebee3484 83 {
emilmont 27:7110ebee3484 84 register uint32_t __regIPSR __ASM("ipsr");
emilmont 27:7110ebee3484 85 return(__regIPSR);
emilmont 27:7110ebee3484 86 }
emilmont 27:7110ebee3484 87 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 88
emilmont 27:7110ebee3484 89
emilmont 27:7110ebee3484 90 /** \brief Get APSR Register
emilmont 27:7110ebee3484 91
emilmont 27:7110ebee3484 92 This function returns the content of the APSR Register.
emilmont 27:7110ebee3484 93
emilmont 27:7110ebee3484 94 \return APSR Register value
emilmont 27:7110ebee3484 95 */
emilmont 27:7110ebee3484 96 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 97 extern uint32_t __get_APSR(void);
emilmont 27:7110ebee3484 98 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 99 static __INLINE uint32_t __get_APSR(void)
emilmont 27:7110ebee3484 100 {
emilmont 27:7110ebee3484 101 register uint32_t __regAPSR __ASM("apsr");
emilmont 27:7110ebee3484 102 return(__regAPSR);
emilmont 27:7110ebee3484 103 }
emilmont 27:7110ebee3484 104 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 105
emilmont 27:7110ebee3484 106
emilmont 27:7110ebee3484 107 /** \brief Get xPSR Register
emilmont 27:7110ebee3484 108
emilmont 27:7110ebee3484 109 This function returns the content of the xPSR Register.
emilmont 27:7110ebee3484 110
emilmont 27:7110ebee3484 111 \return xPSR Register value
emilmont 27:7110ebee3484 112 */
emilmont 27:7110ebee3484 113 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 114 extern uint32_t __get_xPSR(void);
emilmont 27:7110ebee3484 115 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 116 static __INLINE uint32_t __get_xPSR(void)
emilmont 27:7110ebee3484 117 {
emilmont 27:7110ebee3484 118 register uint32_t __regXPSR __ASM("xpsr");
emilmont 27:7110ebee3484 119 return(__regXPSR);
emilmont 27:7110ebee3484 120 }
emilmont 27:7110ebee3484 121 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 122
emilmont 27:7110ebee3484 123
emilmont 27:7110ebee3484 124 /** \brief Get Process Stack Pointer
emilmont 27:7110ebee3484 125
emilmont 27:7110ebee3484 126 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 127
emilmont 27:7110ebee3484 128 \return PSP Register value
emilmont 27:7110ebee3484 129 */
emilmont 27:7110ebee3484 130 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 131 extern uint32_t __get_PSP(void);
emilmont 27:7110ebee3484 132 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 133 static __INLINE uint32_t __get_PSP(void)
emilmont 27:7110ebee3484 134 {
emilmont 27:7110ebee3484 135 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 27:7110ebee3484 136 return(__regProcessStackPointer);
emilmont 27:7110ebee3484 137 }
emilmont 27:7110ebee3484 138 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 139
emilmont 27:7110ebee3484 140
emilmont 27:7110ebee3484 141 /** \brief Set Process Stack Pointer
emilmont 27:7110ebee3484 142
emilmont 27:7110ebee3484 143 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 144
emilmont 27:7110ebee3484 145 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 27:7110ebee3484 146 */
emilmont 27:7110ebee3484 147 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 148 extern void __set_PSP(uint32_t topOfProcStack);
emilmont 27:7110ebee3484 149 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 150 static __INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 27:7110ebee3484 151 {
emilmont 27:7110ebee3484 152 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 27:7110ebee3484 153 __regProcessStackPointer = topOfProcStack;
emilmont 27:7110ebee3484 154 }
emilmont 27:7110ebee3484 155 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 156
emilmont 27:7110ebee3484 157
emilmont 27:7110ebee3484 158 /** \brief Get Main Stack Pointer
emilmont 27:7110ebee3484 159
emilmont 27:7110ebee3484 160 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 161
emilmont 27:7110ebee3484 162 \return MSP Register value
emilmont 27:7110ebee3484 163 */
emilmont 27:7110ebee3484 164 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 165 extern uint32_t __get_MSP(void);
emilmont 27:7110ebee3484 166 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 167 static __INLINE uint32_t __get_MSP(void)
emilmont 27:7110ebee3484 168 {
emilmont 27:7110ebee3484 169 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 27:7110ebee3484 170 return(__regMainStackPointer);
emilmont 27:7110ebee3484 171 }
emilmont 27:7110ebee3484 172 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 173
emilmont 27:7110ebee3484 174
emilmont 27:7110ebee3484 175 /** \brief Set Main Stack Pointer
emilmont 27:7110ebee3484 176
emilmont 27:7110ebee3484 177 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 178
emilmont 27:7110ebee3484 179 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 27:7110ebee3484 180 */
emilmont 27:7110ebee3484 181 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 182 extern void __set_MSP(uint32_t topOfMainStack);
emilmont 27:7110ebee3484 183 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 184 static __INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 27:7110ebee3484 185 {
emilmont 27:7110ebee3484 186 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 27:7110ebee3484 187 __regMainStackPointer = topOfMainStack;
emilmont 27:7110ebee3484 188 }
emilmont 27:7110ebee3484 189 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 190
emilmont 27:7110ebee3484 191
emilmont 27:7110ebee3484 192 /** \brief Get Priority Mask
emilmont 27:7110ebee3484 193
emilmont 27:7110ebee3484 194 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 27:7110ebee3484 195
emilmont 27:7110ebee3484 196 \return Priority Mask value
emilmont 27:7110ebee3484 197 */
emilmont 27:7110ebee3484 198 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 199 extern uint32_t __get_PRIMASK(void);
emilmont 27:7110ebee3484 200 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 201 static __INLINE uint32_t __get_PRIMASK(void)
emilmont 27:7110ebee3484 202 {
emilmont 27:7110ebee3484 203 register uint32_t __regPriMask __ASM("primask");
emilmont 27:7110ebee3484 204 return(__regPriMask);
emilmont 27:7110ebee3484 205 }
emilmont 27:7110ebee3484 206 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 207
emilmont 27:7110ebee3484 208
emilmont 27:7110ebee3484 209 /** \brief Set Priority Mask
emilmont 27:7110ebee3484 210
emilmont 27:7110ebee3484 211 This function assigns the given value to the Priority Mask Register.
emilmont 27:7110ebee3484 212
emilmont 27:7110ebee3484 213 \param [in] priMask Priority Mask
emilmont 27:7110ebee3484 214 */
emilmont 27:7110ebee3484 215 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 216 extern void __set_PRIMASK(uint32_t priMask);
emilmont 27:7110ebee3484 217 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 218 static __INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 27:7110ebee3484 219 {
emilmont 27:7110ebee3484 220 register uint32_t __regPriMask __ASM("primask");
emilmont 27:7110ebee3484 221 __regPriMask = (priMask);
emilmont 27:7110ebee3484 222 }
emilmont 27:7110ebee3484 223 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 224
emilmont 27:7110ebee3484 225
emilmont 27:7110ebee3484 226 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 227
emilmont 27:7110ebee3484 228 /** \brief Enable FIQ
emilmont 27:7110ebee3484 229
emilmont 27:7110ebee3484 230 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 27:7110ebee3484 231 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 232 */
emilmont 27:7110ebee3484 233 #define __enable_fault_irq __enable_fiq
emilmont 27:7110ebee3484 234
emilmont 27:7110ebee3484 235
emilmont 27:7110ebee3484 236 /** \brief Disable FIQ
emilmont 27:7110ebee3484 237
emilmont 27:7110ebee3484 238 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 27:7110ebee3484 239 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 240 */
emilmont 27:7110ebee3484 241 #define __disable_fault_irq __disable_fiq
emilmont 27:7110ebee3484 242
emilmont 27:7110ebee3484 243
emilmont 27:7110ebee3484 244 /** \brief Get Base Priority
emilmont 27:7110ebee3484 245
emilmont 27:7110ebee3484 246 This function returns the current value of the Base Priority register.
emilmont 27:7110ebee3484 247
emilmont 27:7110ebee3484 248 \return Base Priority register value
emilmont 27:7110ebee3484 249 */
emilmont 27:7110ebee3484 250 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 251 extern uint32_t __get_BASEPRI(void);
emilmont 27:7110ebee3484 252 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 253 static __INLINE uint32_t __get_BASEPRI(void)
emilmont 27:7110ebee3484 254 {
emilmont 27:7110ebee3484 255 register uint32_t __regBasePri __ASM("basepri");
emilmont 27:7110ebee3484 256 return(__regBasePri);
emilmont 27:7110ebee3484 257 }
emilmont 27:7110ebee3484 258 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 259
emilmont 27:7110ebee3484 260
emilmont 27:7110ebee3484 261 /** \brief Set Base Priority
emilmont 27:7110ebee3484 262
emilmont 27:7110ebee3484 263 This function assigns the given value to the Base Priority register.
emilmont 27:7110ebee3484 264
emilmont 27:7110ebee3484 265 \param [in] basePri Base Priority value to set
emilmont 27:7110ebee3484 266 */
emilmont 27:7110ebee3484 267 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 268 extern void __set_BASEPRI(uint32_t basePri);
emilmont 27:7110ebee3484 269 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 270 static __INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 27:7110ebee3484 271 {
emilmont 27:7110ebee3484 272 register uint32_t __regBasePri __ASM("basepri");
emilmont 27:7110ebee3484 273 __regBasePri = (basePri & 0xff);
emilmont 27:7110ebee3484 274 }
emilmont 27:7110ebee3484 275 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 276
emilmont 27:7110ebee3484 277
emilmont 27:7110ebee3484 278 /** \brief Get Fault Mask
emilmont 27:7110ebee3484 279
emilmont 27:7110ebee3484 280 This function returns the current value of the Fault Mask register.
emilmont 27:7110ebee3484 281
emilmont 27:7110ebee3484 282 \return Fault Mask register value
emilmont 27:7110ebee3484 283 */
emilmont 27:7110ebee3484 284 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 285 extern uint32_t __get_FAULTMASK(void);
emilmont 27:7110ebee3484 286 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 287 static __INLINE uint32_t __get_FAULTMASK(void)
emilmont 27:7110ebee3484 288 {
emilmont 27:7110ebee3484 289 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 27:7110ebee3484 290 return(__regFaultMask);
emilmont 27:7110ebee3484 291 }
emilmont 27:7110ebee3484 292 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 293
emilmont 27:7110ebee3484 294
emilmont 27:7110ebee3484 295 /** \brief Set Fault Mask
emilmont 27:7110ebee3484 296
emilmont 27:7110ebee3484 297 This function assigns the given value to the Fault Mask register.
emilmont 27:7110ebee3484 298
emilmont 27:7110ebee3484 299 \param [in] faultMask Fault Mask value to set
emilmont 27:7110ebee3484 300 */
emilmont 27:7110ebee3484 301 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 302 extern void __set_FAULTMASK(uint32_t faultMask);
emilmont 27:7110ebee3484 303 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 304 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 27:7110ebee3484 305 {
emilmont 27:7110ebee3484 306 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 27:7110ebee3484 307 __regFaultMask = (faultMask & 1);
emilmont 27:7110ebee3484 308 }
emilmont 27:7110ebee3484 309 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 310
emilmont 27:7110ebee3484 311 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 312
emilmont 27:7110ebee3484 313
emilmont 27:7110ebee3484 314 #if (__CORTEX_M == 0x04)
emilmont 27:7110ebee3484 315
emilmont 27:7110ebee3484 316 /** \brief Get FPSCR
emilmont 27:7110ebee3484 317
emilmont 27:7110ebee3484 318 This function returns the current value of the Floating Point Status/Control register.
emilmont 27:7110ebee3484 319
emilmont 27:7110ebee3484 320 \return Floating Point Status/Control register value
emilmont 27:7110ebee3484 321 */
emilmont 27:7110ebee3484 322 static __INLINE uint32_t __get_FPSCR(void)
emilmont 27:7110ebee3484 323 {
emilmont 27:7110ebee3484 324 #if (__FPU_PRESENT == 1)
emilmont 27:7110ebee3484 325 register uint32_t __regfpscr __ASM("fpscr");
emilmont 27:7110ebee3484 326 return(__regfpscr);
emilmont 27:7110ebee3484 327 #else
emilmont 27:7110ebee3484 328 return(0);
emilmont 27:7110ebee3484 329 #endif
emilmont 27:7110ebee3484 330 }
emilmont 27:7110ebee3484 331
emilmont 27:7110ebee3484 332
emilmont 27:7110ebee3484 333 /** \brief Set FPSCR
emilmont 27:7110ebee3484 334
emilmont 27:7110ebee3484 335 This function assigns the given value to the Floating Point Status/Control register.
emilmont 27:7110ebee3484 336
emilmont 27:7110ebee3484 337 \param [in] fpscr Floating Point Status/Control value to set
emilmont 27:7110ebee3484 338 */
emilmont 27:7110ebee3484 339 static __INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 27:7110ebee3484 340 {
emilmont 27:7110ebee3484 341 #if (__FPU_PRESENT == 1)
emilmont 27:7110ebee3484 342 register uint32_t __regfpscr __ASM("fpscr");
emilmont 27:7110ebee3484 343 __regfpscr = (fpscr);
emilmont 27:7110ebee3484 344 #endif
emilmont 27:7110ebee3484 345 }
emilmont 27:7110ebee3484 346
emilmont 27:7110ebee3484 347 #endif /* (__CORTEX_M == 0x04) */
emilmont 27:7110ebee3484 348
emilmont 27:7110ebee3484 349
emilmont 27:7110ebee3484 350 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
emilmont 27:7110ebee3484 351 /* IAR iccarm specific functions */
emilmont 27:7110ebee3484 352
emilmont 27:7110ebee3484 353 #if defined (__ICCARM__)
emilmont 27:7110ebee3484 354 #include <intrinsics.h> /* IAR Intrinsics */
emilmont 27:7110ebee3484 355 #endif
emilmont 27:7110ebee3484 356
emilmont 27:7110ebee3484 357 #pragma diag_suppress=Pe940
emilmont 27:7110ebee3484 358
emilmont 27:7110ebee3484 359 /** \brief Enable IRQ Interrupts
emilmont 27:7110ebee3484 360
emilmont 27:7110ebee3484 361 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 27:7110ebee3484 362 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 363 */
emilmont 27:7110ebee3484 364 #define __enable_irq __enable_interrupt
emilmont 27:7110ebee3484 365
emilmont 27:7110ebee3484 366
emilmont 27:7110ebee3484 367 /** \brief Disable IRQ Interrupts
emilmont 27:7110ebee3484 368
emilmont 27:7110ebee3484 369 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 27:7110ebee3484 370 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 371 */
emilmont 27:7110ebee3484 372 #define __disable_irq __disable_interrupt
emilmont 27:7110ebee3484 373
emilmont 27:7110ebee3484 374
emilmont 27:7110ebee3484 375 /* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
emilmont 27:7110ebee3484 376 /* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
emilmont 27:7110ebee3484 377
emilmont 27:7110ebee3484 378
emilmont 27:7110ebee3484 379 /** \brief Get ISPR Register
emilmont 27:7110ebee3484 380
emilmont 27:7110ebee3484 381 This function returns the content of the ISPR Register.
emilmont 27:7110ebee3484 382
emilmont 27:7110ebee3484 383 \return ISPR Register value
emilmont 27:7110ebee3484 384 */
emilmont 27:7110ebee3484 385 static uint32_t __get_IPSR(void)
emilmont 27:7110ebee3484 386 {
emilmont 27:7110ebee3484 387 __ASM("mrs r0, ipsr");
emilmont 27:7110ebee3484 388 }
emilmont 27:7110ebee3484 389
emilmont 27:7110ebee3484 390
emilmont 27:7110ebee3484 391 /** \brief Get APSR Register
emilmont 27:7110ebee3484 392
emilmont 27:7110ebee3484 393 This function returns the content of the APSR Register.
emilmont 27:7110ebee3484 394
emilmont 27:7110ebee3484 395 \return APSR Register value
emilmont 27:7110ebee3484 396 */
emilmont 27:7110ebee3484 397 static uint32_t __get_APSR(void)
emilmont 27:7110ebee3484 398 {
emilmont 27:7110ebee3484 399 __ASM("mrs r0, apsr");
emilmont 27:7110ebee3484 400 }
emilmont 27:7110ebee3484 401
emilmont 27:7110ebee3484 402
emilmont 27:7110ebee3484 403 /** \brief Get xPSR Register
emilmont 27:7110ebee3484 404
emilmont 27:7110ebee3484 405 This function returns the content of the xPSR Register.
emilmont 27:7110ebee3484 406
emilmont 27:7110ebee3484 407 \return xPSR Register value
emilmont 27:7110ebee3484 408 */
emilmont 27:7110ebee3484 409 static uint32_t __get_xPSR(void)
emilmont 27:7110ebee3484 410 {
emilmont 27:7110ebee3484 411 __ASM("mrs r0, psr"); // assembler does not know "xpsr"
emilmont 27:7110ebee3484 412 }
emilmont 27:7110ebee3484 413
emilmont 27:7110ebee3484 414
emilmont 27:7110ebee3484 415 /** \brief Get Process Stack Pointer
emilmont 27:7110ebee3484 416
emilmont 27:7110ebee3484 417 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 418
emilmont 27:7110ebee3484 419 \return PSP Register value
emilmont 27:7110ebee3484 420 */
emilmont 27:7110ebee3484 421 static uint32_t __get_PSP(void)
emilmont 27:7110ebee3484 422 {
emilmont 27:7110ebee3484 423 __ASM("mrs r0, psp");
emilmont 27:7110ebee3484 424 }
emilmont 27:7110ebee3484 425
emilmont 27:7110ebee3484 426
emilmont 27:7110ebee3484 427 /** \brief Set Process Stack Pointer
emilmont 27:7110ebee3484 428
emilmont 27:7110ebee3484 429 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 430
emilmont 27:7110ebee3484 431 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 27:7110ebee3484 432 */
emilmont 27:7110ebee3484 433 static void __set_PSP(uint32_t topOfProcStack)
emilmont 27:7110ebee3484 434 {
emilmont 27:7110ebee3484 435 __ASM("msr psp, r0");
emilmont 27:7110ebee3484 436 }
emilmont 27:7110ebee3484 437
emilmont 27:7110ebee3484 438
emilmont 27:7110ebee3484 439 /** \brief Get Main Stack Pointer
emilmont 27:7110ebee3484 440
emilmont 27:7110ebee3484 441 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 442
emilmont 27:7110ebee3484 443 \return MSP Register value
emilmont 27:7110ebee3484 444 */
emilmont 27:7110ebee3484 445 static uint32_t __get_MSP(void)
emilmont 27:7110ebee3484 446 {
emilmont 27:7110ebee3484 447 __ASM("mrs r0, msp");
emilmont 27:7110ebee3484 448 }
emilmont 27:7110ebee3484 449
emilmont 27:7110ebee3484 450
emilmont 27:7110ebee3484 451 /** \brief Set Main Stack Pointer
emilmont 27:7110ebee3484 452
emilmont 27:7110ebee3484 453 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 454
emilmont 27:7110ebee3484 455 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 27:7110ebee3484 456 */
emilmont 27:7110ebee3484 457 static void __set_MSP(uint32_t topOfMainStack)
emilmont 27:7110ebee3484 458 {
emilmont 27:7110ebee3484 459 __ASM("msr msp, r0");
emilmont 27:7110ebee3484 460 }
emilmont 27:7110ebee3484 461
emilmont 27:7110ebee3484 462
emilmont 27:7110ebee3484 463 /* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
emilmont 27:7110ebee3484 464 /* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
emilmont 27:7110ebee3484 465
emilmont 27:7110ebee3484 466
emilmont 27:7110ebee3484 467 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 468
emilmont 27:7110ebee3484 469 /** \brief Enable FIQ
emilmont 27:7110ebee3484 470
emilmont 27:7110ebee3484 471 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 27:7110ebee3484 472 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 473 */
emilmont 27:7110ebee3484 474 static __INLINE void __enable_fault_irq(void)
emilmont 27:7110ebee3484 475 {
emilmont 27:7110ebee3484 476 __ASM ("cpsie f");
emilmont 27:7110ebee3484 477 }
emilmont 27:7110ebee3484 478
emilmont 27:7110ebee3484 479
emilmont 27:7110ebee3484 480 /** \brief Disable FIQ
emilmont 27:7110ebee3484 481
emilmont 27:7110ebee3484 482 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 27:7110ebee3484 483 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 484 */
emilmont 27:7110ebee3484 485 static __INLINE void __disable_fault_irq(void)
emilmont 27:7110ebee3484 486 {
emilmont 27:7110ebee3484 487 __ASM ("cpsid f");
emilmont 27:7110ebee3484 488 }
emilmont 27:7110ebee3484 489
emilmont 27:7110ebee3484 490
emilmont 27:7110ebee3484 491 /* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
emilmont 27:7110ebee3484 492 /* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
emilmont 27:7110ebee3484 493 /* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
emilmont 27:7110ebee3484 494 /* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
emilmont 27:7110ebee3484 495
emilmont 27:7110ebee3484 496 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 497
emilmont 27:7110ebee3484 498
emilmont 27:7110ebee3484 499 #if (__CORTEX_M == 0x04)
emilmont 27:7110ebee3484 500
emilmont 27:7110ebee3484 501 /** \brief Get FPSCR
emilmont 27:7110ebee3484 502
emilmont 27:7110ebee3484 503 This function returns the current value of the Floating Point Status/Control register.
emilmont 27:7110ebee3484 504
emilmont 27:7110ebee3484 505 \return Floating Point Status/Control register value
emilmont 27:7110ebee3484 506 */
emilmont 27:7110ebee3484 507 static uint32_t __get_FPSCR(void)
emilmont 27:7110ebee3484 508 {
emilmont 27:7110ebee3484 509 #if (__FPU_PRESENT == 1)
emilmont 27:7110ebee3484 510 __ASM("vmrs r0, fpscr");
emilmont 27:7110ebee3484 511 #else
emilmont 27:7110ebee3484 512 return(0);
emilmont 27:7110ebee3484 513 #endif
emilmont 27:7110ebee3484 514 }
emilmont 27:7110ebee3484 515
emilmont 27:7110ebee3484 516
emilmont 27:7110ebee3484 517 /** \brief Set FPSCR
emilmont 27:7110ebee3484 518
emilmont 27:7110ebee3484 519 This function assigns the given value to the Floating Point Status/Control register.
emilmont 27:7110ebee3484 520
emilmont 27:7110ebee3484 521 \param [in] fpscr Floating Point Status/Control value to set
emilmont 27:7110ebee3484 522 */
emilmont 27:7110ebee3484 523 static void __set_FPSCR(uint32_t fpscr)
emilmont 27:7110ebee3484 524 {
emilmont 27:7110ebee3484 525 #if (__FPU_PRESENT == 1)
emilmont 27:7110ebee3484 526 __ASM("vmsr fpscr, r0");
emilmont 27:7110ebee3484 527 #endif
emilmont 27:7110ebee3484 528 }
emilmont 27:7110ebee3484 529
emilmont 27:7110ebee3484 530 #endif /* (__CORTEX_M == 0x04) */
emilmont 27:7110ebee3484 531
emilmont 27:7110ebee3484 532 #pragma diag_default=Pe940
emilmont 27:7110ebee3484 533
emilmont 27:7110ebee3484 534
emilmont 27:7110ebee3484 535 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
emilmont 27:7110ebee3484 536 /* GNU gcc specific functions */
emilmont 27:7110ebee3484 537
emilmont 27:7110ebee3484 538 /** \brief Enable IRQ Interrupts
emilmont 27:7110ebee3484 539
emilmont 27:7110ebee3484 540 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 27:7110ebee3484 541 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 542 */
emilmont 27:7110ebee3484 543 __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
emilmont 27:7110ebee3484 544 {
emilmont 27:7110ebee3484 545 __ASM volatile ("cpsie i");
emilmont 27:7110ebee3484 546 }
emilmont 27:7110ebee3484 547
emilmont 27:7110ebee3484 548
emilmont 27:7110ebee3484 549 /** \brief Disable IRQ Interrupts
emilmont 27:7110ebee3484 550
emilmont 27:7110ebee3484 551 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 27:7110ebee3484 552 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 553 */
emilmont 27:7110ebee3484 554 __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
emilmont 27:7110ebee3484 555 {
emilmont 27:7110ebee3484 556 __ASM volatile ("cpsid i");
emilmont 27:7110ebee3484 557 }
emilmont 27:7110ebee3484 558
emilmont 27:7110ebee3484 559
emilmont 27:7110ebee3484 560 /** \brief Get Control Register
emilmont 27:7110ebee3484 561
emilmont 27:7110ebee3484 562 This function returns the content of the Control Register.
emilmont 27:7110ebee3484 563
emilmont 27:7110ebee3484 564 \return Control Register value
emilmont 27:7110ebee3484 565 */
emilmont 27:7110ebee3484 566 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
emilmont 27:7110ebee3484 567 {
emilmont 27:7110ebee3484 568 uint32_t result;
emilmont 27:7110ebee3484 569
emilmont 27:7110ebee3484 570 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 27:7110ebee3484 571 return(result);
emilmont 27:7110ebee3484 572 }
emilmont 27:7110ebee3484 573
emilmont 27:7110ebee3484 574
emilmont 27:7110ebee3484 575 /** \brief Set Control Register
emilmont 27:7110ebee3484 576
emilmont 27:7110ebee3484 577 This function writes the given value to the Control Register.
emilmont 27:7110ebee3484 578
emilmont 27:7110ebee3484 579 \param [in] control Control Register value to set
emilmont 27:7110ebee3484 580 */
emilmont 27:7110ebee3484 581 __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
emilmont 27:7110ebee3484 582 {
emilmont 27:7110ebee3484 583 __ASM volatile ("MSR control, %0" : : "r" (control) );
emilmont 27:7110ebee3484 584 }
emilmont 27:7110ebee3484 585
emilmont 27:7110ebee3484 586
emilmont 27:7110ebee3484 587 /** \brief Get ISPR Register
emilmont 27:7110ebee3484 588
emilmont 27:7110ebee3484 589 This function returns the content of the ISPR Register.
emilmont 27:7110ebee3484 590
emilmont 27:7110ebee3484 591 \return ISPR Register value
emilmont 27:7110ebee3484 592 */
emilmont 27:7110ebee3484 593 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
emilmont 27:7110ebee3484 594 {
emilmont 27:7110ebee3484 595 uint32_t result;
emilmont 27:7110ebee3484 596
emilmont 27:7110ebee3484 597 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 27:7110ebee3484 598 return(result);
emilmont 27:7110ebee3484 599 }
emilmont 27:7110ebee3484 600
emilmont 27:7110ebee3484 601
emilmont 27:7110ebee3484 602 /** \brief Get APSR Register
emilmont 27:7110ebee3484 603
emilmont 27:7110ebee3484 604 This function returns the content of the APSR Register.
emilmont 27:7110ebee3484 605
emilmont 27:7110ebee3484 606 \return APSR Register value
emilmont 27:7110ebee3484 607 */
emilmont 27:7110ebee3484 608 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
emilmont 27:7110ebee3484 609 {
emilmont 27:7110ebee3484 610 uint32_t result;
emilmont 27:7110ebee3484 611
emilmont 27:7110ebee3484 612 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 27:7110ebee3484 613 return(result);
emilmont 27:7110ebee3484 614 }
emilmont 27:7110ebee3484 615
emilmont 27:7110ebee3484 616
emilmont 27:7110ebee3484 617 /** \brief Get xPSR Register
emilmont 27:7110ebee3484 618
emilmont 27:7110ebee3484 619 This function returns the content of the xPSR Register.
emilmont 27:7110ebee3484 620
emilmont 27:7110ebee3484 621 \return xPSR Register value
emilmont 27:7110ebee3484 622 */
emilmont 27:7110ebee3484 623 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
emilmont 27:7110ebee3484 624 {
emilmont 27:7110ebee3484 625 uint32_t result;
emilmont 27:7110ebee3484 626
emilmont 27:7110ebee3484 627 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 27:7110ebee3484 628 return(result);
emilmont 27:7110ebee3484 629 }
emilmont 27:7110ebee3484 630
emilmont 27:7110ebee3484 631
emilmont 27:7110ebee3484 632 /** \brief Get Process Stack Pointer
emilmont 27:7110ebee3484 633
emilmont 27:7110ebee3484 634 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 635
emilmont 27:7110ebee3484 636 \return PSP Register value
emilmont 27:7110ebee3484 637 */
emilmont 27:7110ebee3484 638 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
emilmont 27:7110ebee3484 639 {
emilmont 27:7110ebee3484 640 register uint32_t result;
emilmont 27:7110ebee3484 641
emilmont 27:7110ebee3484 642 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 27:7110ebee3484 643 return(result);
emilmont 27:7110ebee3484 644 }
emilmont 27:7110ebee3484 645
emilmont 27:7110ebee3484 646
emilmont 27:7110ebee3484 647 /** \brief Set Process Stack Pointer
emilmont 27:7110ebee3484 648
emilmont 27:7110ebee3484 649 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 650
emilmont 27:7110ebee3484 651 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 27:7110ebee3484 652 */
emilmont 27:7110ebee3484 653 __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 27:7110ebee3484 654 {
emilmont 27:7110ebee3484 655 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
emilmont 27:7110ebee3484 656 }
emilmont 27:7110ebee3484 657
emilmont 27:7110ebee3484 658
emilmont 27:7110ebee3484 659 /** \brief Get Main Stack Pointer
emilmont 27:7110ebee3484 660
emilmont 27:7110ebee3484 661 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 662
emilmont 27:7110ebee3484 663 \return MSP Register value
emilmont 27:7110ebee3484 664 */
emilmont 27:7110ebee3484 665 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
emilmont 27:7110ebee3484 666 {
emilmont 27:7110ebee3484 667 register uint32_t result;
emilmont 27:7110ebee3484 668
emilmont 27:7110ebee3484 669 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 27:7110ebee3484 670 return(result);
emilmont 27:7110ebee3484 671 }
emilmont 27:7110ebee3484 672
emilmont 27:7110ebee3484 673
emilmont 27:7110ebee3484 674 /** \brief Set Main Stack Pointer
emilmont 27:7110ebee3484 675
emilmont 27:7110ebee3484 676 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 677
emilmont 27:7110ebee3484 678 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 27:7110ebee3484 679 */
emilmont 27:7110ebee3484 680 __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 27:7110ebee3484 681 {
emilmont 27:7110ebee3484 682 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
emilmont 27:7110ebee3484 683 }
emilmont 27:7110ebee3484 684
emilmont 27:7110ebee3484 685
emilmont 27:7110ebee3484 686 /** \brief Get Priority Mask
emilmont 27:7110ebee3484 687
emilmont 27:7110ebee3484 688 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 27:7110ebee3484 689
emilmont 27:7110ebee3484 690 \return Priority Mask value
emilmont 27:7110ebee3484 691 */
emilmont 27:7110ebee3484 692 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
emilmont 27:7110ebee3484 693 {
emilmont 27:7110ebee3484 694 uint32_t result;
emilmont 27:7110ebee3484 695
emilmont 27:7110ebee3484 696 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 27:7110ebee3484 697 return(result);
emilmont 27:7110ebee3484 698 }
emilmont 27:7110ebee3484 699
emilmont 27:7110ebee3484 700
emilmont 27:7110ebee3484 701 /** \brief Set Priority Mask
emilmont 27:7110ebee3484 702
emilmont 27:7110ebee3484 703 This function assigns the given value to the Priority Mask Register.
emilmont 27:7110ebee3484 704
emilmont 27:7110ebee3484 705 \param [in] priMask Priority Mask
emilmont 27:7110ebee3484 706 */
emilmont 27:7110ebee3484 707 __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 27:7110ebee3484 708 {
emilmont 27:7110ebee3484 709 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
emilmont 27:7110ebee3484 710 }
emilmont 27:7110ebee3484 711
emilmont 27:7110ebee3484 712
emilmont 27:7110ebee3484 713 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 714
emilmont 27:7110ebee3484 715 /** \brief Enable FIQ
emilmont 27:7110ebee3484 716
emilmont 27:7110ebee3484 717 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 27:7110ebee3484 718 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 719 */
emilmont 27:7110ebee3484 720 __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
emilmont 27:7110ebee3484 721 {
emilmont 27:7110ebee3484 722 __ASM volatile ("cpsie f");
emilmont 27:7110ebee3484 723 }
emilmont 27:7110ebee3484 724
emilmont 27:7110ebee3484 725
emilmont 27:7110ebee3484 726 /** \brief Disable FIQ
emilmont 27:7110ebee3484 727
emilmont 27:7110ebee3484 728 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 27:7110ebee3484 729 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 730 */
emilmont 27:7110ebee3484 731 __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
emilmont 27:7110ebee3484 732 {
emilmont 27:7110ebee3484 733 __ASM volatile ("cpsid f");
emilmont 27:7110ebee3484 734 }
emilmont 27:7110ebee3484 735
emilmont 27:7110ebee3484 736
emilmont 27:7110ebee3484 737 /** \brief Get Base Priority
emilmont 27:7110ebee3484 738
emilmont 27:7110ebee3484 739 This function returns the current value of the Base Priority register.
emilmont 27:7110ebee3484 740
emilmont 27:7110ebee3484 741 \return Base Priority register value
emilmont 27:7110ebee3484 742 */
emilmont 27:7110ebee3484 743 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
emilmont 27:7110ebee3484 744 {
emilmont 27:7110ebee3484 745 uint32_t result;
emilmont 27:7110ebee3484 746
emilmont 27:7110ebee3484 747 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 27:7110ebee3484 748 return(result);
emilmont 27:7110ebee3484 749 }
emilmont 27:7110ebee3484 750
emilmont 27:7110ebee3484 751
emilmont 27:7110ebee3484 752 /** \brief Set Base Priority
emilmont 27:7110ebee3484 753
emilmont 27:7110ebee3484 754 This function assigns the given value to the Base Priority register.
emilmont 27:7110ebee3484 755
emilmont 27:7110ebee3484 756 \param [in] basePri Base Priority value to set
emilmont 27:7110ebee3484 757 */
emilmont 27:7110ebee3484 758 __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
emilmont 27:7110ebee3484 759 {
emilmont 27:7110ebee3484 760 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
emilmont 27:7110ebee3484 761 }
emilmont 27:7110ebee3484 762
emilmont 27:7110ebee3484 763
emilmont 27:7110ebee3484 764 /** \brief Get Fault Mask
emilmont 27:7110ebee3484 765
emilmont 27:7110ebee3484 766 This function returns the current value of the Fault Mask register.
emilmont 27:7110ebee3484 767
emilmont 27:7110ebee3484 768 \return Fault Mask register value
emilmont 27:7110ebee3484 769 */
emilmont 27:7110ebee3484 770 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
emilmont 27:7110ebee3484 771 {
emilmont 27:7110ebee3484 772 uint32_t result;
emilmont 27:7110ebee3484 773
emilmont 27:7110ebee3484 774 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 27:7110ebee3484 775 return(result);
emilmont 27:7110ebee3484 776 }
emilmont 27:7110ebee3484 777
emilmont 27:7110ebee3484 778
emilmont 27:7110ebee3484 779 /** \brief Set Fault Mask
emilmont 27:7110ebee3484 780
emilmont 27:7110ebee3484 781 This function assigns the given value to the Fault Mask register.
emilmont 27:7110ebee3484 782
emilmont 27:7110ebee3484 783 \param [in] faultMask Fault Mask value to set
emilmont 27:7110ebee3484 784 */
emilmont 27:7110ebee3484 785 __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 27:7110ebee3484 786 {
emilmont 27:7110ebee3484 787 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
emilmont 27:7110ebee3484 788 }
emilmont 27:7110ebee3484 789
emilmont 27:7110ebee3484 790 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 791
emilmont 27:7110ebee3484 792
emilmont 27:7110ebee3484 793 #if (__CORTEX_M == 0x04)
emilmont 27:7110ebee3484 794
emilmont 27:7110ebee3484 795 /** \brief Get FPSCR
emilmont 27:7110ebee3484 796
emilmont 27:7110ebee3484 797 This function returns the current value of the Floating Point Status/Control register.
emilmont 27:7110ebee3484 798
emilmont 27:7110ebee3484 799 \return Floating Point Status/Control register value
emilmont 27:7110ebee3484 800 */
emilmont 27:7110ebee3484 801 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
emilmont 27:7110ebee3484 802 {
emilmont 27:7110ebee3484 803 #if (__FPU_PRESENT == 1)
emilmont 27:7110ebee3484 804 uint32_t result;
emilmont 27:7110ebee3484 805
emilmont 27:7110ebee3484 806 __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
emilmont 27:7110ebee3484 807 return(result);
emilmont 27:7110ebee3484 808 #else
emilmont 27:7110ebee3484 809 return(0);
emilmont 27:7110ebee3484 810 #endif
emilmont 27:7110ebee3484 811 }
emilmont 27:7110ebee3484 812
emilmont 27:7110ebee3484 813
emilmont 27:7110ebee3484 814 /** \brief Set FPSCR
emilmont 27:7110ebee3484 815
emilmont 27:7110ebee3484 816 This function assigns the given value to the Floating Point Status/Control register.
emilmont 27:7110ebee3484 817
emilmont 27:7110ebee3484 818 \param [in] fpscr Floating Point Status/Control value to set
emilmont 27:7110ebee3484 819 */
emilmont 27:7110ebee3484 820 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 27:7110ebee3484 821 {
emilmont 27:7110ebee3484 822 #if (__FPU_PRESENT == 1)
emilmont 27:7110ebee3484 823 __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
emilmont 27:7110ebee3484 824 #endif
emilmont 27:7110ebee3484 825 }
emilmont 27:7110ebee3484 826
emilmont 27:7110ebee3484 827 #endif /* (__CORTEX_M == 0x04) */
emilmont 27:7110ebee3484 828
emilmont 27:7110ebee3484 829
emilmont 27:7110ebee3484 830 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
emilmont 27:7110ebee3484 831 /* TASKING carm specific functions */
emilmont 27:7110ebee3484 832
emilmont 27:7110ebee3484 833 /*
emilmont 27:7110ebee3484 834 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 27:7110ebee3484 835 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 27:7110ebee3484 836 * Including the CMSIS ones.
emilmont 27:7110ebee3484 837 */
emilmont 27:7110ebee3484 838
emilmont 27:7110ebee3484 839 #endif
emilmont 27:7110ebee3484 840
emilmont 27:7110ebee3484 841 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 27:7110ebee3484 842
emilmont 27:7110ebee3484 843
emilmont 27:7110ebee3484 844 #endif /* __CORE_CMFUNC_H__ */