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LPC1768/GCC_ARM/core_cmFunc.h@33:5364839841bd, 2012-01-10 (annotated)

Committer:
emilmont
Date:
Tue Jan 10 12:00:50 2012 +0000
Revision:
33:5364839841bd
Parent:
27:7110ebee3484 
[10 January 2012] CAN::attach template. CMSIS updates.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file core_cmFunc.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 33:5364839841bd 4 * @version V3.00
emilmont 33:5364839841bd 5 * @date 09. December 2011
emilmont 27:7110ebee3484 6 *
emilmont 27:7110ebee3484 7 * @note
emilmont 33:5364839841bd 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 9 *
emilmont 27:7110ebee3484 10 * @par
emilmont 27:7110ebee3484 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 27:7110ebee3484 12 * processor based microcontrollers. This file can be freely distributed
emilmont 27:7110ebee3484 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * @par
emilmont 27:7110ebee3484 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 21 *
emilmont 27:7110ebee3484 22 ******************************************************************************/
emilmont 27:7110ebee3484 23
emilmont 33:5364839841bd 24 #ifndef __CORE_CMFUNC_H
emilmont 33:5364839841bd 25 #define __CORE_CMFUNC_H
emilmont 33:5364839841bd 26
emilmont 27:7110ebee3484 27
emilmont 27:7110ebee3484 28 /* ########################### Core Function Access ########################### */
emilmont 27:7110ebee3484 29 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 27:7110ebee3484 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 27:7110ebee3484 31 @{
emilmont 27:7110ebee3484 32 */
emilmont 27:7110ebee3484 33
emilmont 33:5364839841bd 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 27:7110ebee3484 35 /* ARM armcc specific functions */
emilmont 27:7110ebee3484 36
emilmont 33:5364839841bd 37 #if (__ARMCC_VERSION < 400677)
emilmont 33:5364839841bd 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 33:5364839841bd 39 #endif
emilmont 33:5364839841bd 40
emilmont 27:7110ebee3484 41 /* intrinsic void __enable_irq(); */
emilmont 27:7110ebee3484 42 /* intrinsic void __disable_irq(); */
emilmont 27:7110ebee3484 43
emilmont 27:7110ebee3484 44 /** \brief Get Control Register
emilmont 27:7110ebee3484 45
emilmont 27:7110ebee3484 46 This function returns the content of the Control Register.
emilmont 27:7110ebee3484 47
emilmont 27:7110ebee3484 48 \return Control Register value
emilmont 27:7110ebee3484 49 */
emilmont 27:7110ebee3484 50 static __INLINE uint32_t __get_CONTROL(void)
emilmont 27:7110ebee3484 51 {
emilmont 27:7110ebee3484 52 register uint32_t __regControl __ASM("control");
emilmont 27:7110ebee3484 53 return(__regControl);
emilmont 27:7110ebee3484 54 }
emilmont 27:7110ebee3484 55
emilmont 27:7110ebee3484 56
emilmont 27:7110ebee3484 57 /** \brief Set Control Register
emilmont 27:7110ebee3484 58
emilmont 27:7110ebee3484 59 This function writes the given value to the Control Register.
emilmont 27:7110ebee3484 60
emilmont 27:7110ebee3484 61 \param [in] control Control Register value to set
emilmont 27:7110ebee3484 62 */
emilmont 27:7110ebee3484 63 static __INLINE void __set_CONTROL(uint32_t control)
emilmont 27:7110ebee3484 64 {
emilmont 27:7110ebee3484 65 register uint32_t __regControl __ASM("control");
emilmont 27:7110ebee3484 66 __regControl = control;
emilmont 27:7110ebee3484 67 }
emilmont 27:7110ebee3484 68
emilmont 27:7110ebee3484 69
emilmont 33:5364839841bd 70 /** \brief Get IPSR Register
emilmont 27:7110ebee3484 71
emilmont 33:5364839841bd 72 This function returns the content of the IPSR Register.
emilmont 33:5364839841bd 73
emilmont 33:5364839841bd 74 \return IPSR Register value
emilmont 27:7110ebee3484 75 */
emilmont 27:7110ebee3484 76 static __INLINE uint32_t __get_IPSR(void)
emilmont 27:7110ebee3484 77 {
emilmont 27:7110ebee3484 78 register uint32_t __regIPSR __ASM("ipsr");
emilmont 27:7110ebee3484 79 return(__regIPSR);
emilmont 27:7110ebee3484 80 }
emilmont 27:7110ebee3484 81
emilmont 27:7110ebee3484 82
emilmont 27:7110ebee3484 83 /** \brief Get APSR Register
emilmont 27:7110ebee3484 84
emilmont 27:7110ebee3484 85 This function returns the content of the APSR Register.
emilmont 27:7110ebee3484 86
emilmont 27:7110ebee3484 87 \return APSR Register value
emilmont 27:7110ebee3484 88 */
emilmont 27:7110ebee3484 89 static __INLINE uint32_t __get_APSR(void)
emilmont 27:7110ebee3484 90 {
emilmont 27:7110ebee3484 91 register uint32_t __regAPSR __ASM("apsr");
emilmont 27:7110ebee3484 92 return(__regAPSR);
emilmont 27:7110ebee3484 93 }
emilmont 27:7110ebee3484 94
emilmont 27:7110ebee3484 95
emilmont 27:7110ebee3484 96 /** \brief Get xPSR Register
emilmont 27:7110ebee3484 97
emilmont 27:7110ebee3484 98 This function returns the content of the xPSR Register.
emilmont 27:7110ebee3484 99
emilmont 27:7110ebee3484 100 \return xPSR Register value
emilmont 27:7110ebee3484 101 */
emilmont 27:7110ebee3484 102 static __INLINE uint32_t __get_xPSR(void)
emilmont 27:7110ebee3484 103 {
emilmont 27:7110ebee3484 104 register uint32_t __regXPSR __ASM("xpsr");
emilmont 27:7110ebee3484 105 return(__regXPSR);
emilmont 27:7110ebee3484 106 }
emilmont 27:7110ebee3484 107
emilmont 27:7110ebee3484 108
emilmont 27:7110ebee3484 109 /** \brief Get Process Stack Pointer
emilmont 27:7110ebee3484 110
emilmont 27:7110ebee3484 111 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 112
emilmont 27:7110ebee3484 113 \return PSP Register value
emilmont 27:7110ebee3484 114 */
emilmont 27:7110ebee3484 115 static __INLINE uint32_t __get_PSP(void)
emilmont 27:7110ebee3484 116 {
emilmont 27:7110ebee3484 117 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 27:7110ebee3484 118 return(__regProcessStackPointer);
emilmont 27:7110ebee3484 119 }
emilmont 27:7110ebee3484 120
emilmont 27:7110ebee3484 121
emilmont 27:7110ebee3484 122 /** \brief Set Process Stack Pointer
emilmont 27:7110ebee3484 123
emilmont 27:7110ebee3484 124 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 125
emilmont 27:7110ebee3484 126 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 27:7110ebee3484 127 */
emilmont 27:7110ebee3484 128 static __INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 27:7110ebee3484 129 {
emilmont 27:7110ebee3484 130 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 27:7110ebee3484 131 __regProcessStackPointer = topOfProcStack;
emilmont 27:7110ebee3484 132 }
emilmont 27:7110ebee3484 133
emilmont 27:7110ebee3484 134
emilmont 27:7110ebee3484 135 /** \brief Get Main Stack Pointer
emilmont 27:7110ebee3484 136
emilmont 27:7110ebee3484 137 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 138
emilmont 27:7110ebee3484 139 \return MSP Register value
emilmont 27:7110ebee3484 140 */
emilmont 27:7110ebee3484 141 static __INLINE uint32_t __get_MSP(void)
emilmont 27:7110ebee3484 142 {
emilmont 27:7110ebee3484 143 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 27:7110ebee3484 144 return(__regMainStackPointer);
emilmont 27:7110ebee3484 145 }
emilmont 27:7110ebee3484 146
emilmont 27:7110ebee3484 147
emilmont 27:7110ebee3484 148 /** \brief Set Main Stack Pointer
emilmont 27:7110ebee3484 149
emilmont 27:7110ebee3484 150 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 151
emilmont 27:7110ebee3484 152 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 27:7110ebee3484 153 */
emilmont 27:7110ebee3484 154 static __INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 27:7110ebee3484 155 {
emilmont 27:7110ebee3484 156 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 27:7110ebee3484 157 __regMainStackPointer = topOfMainStack;
emilmont 27:7110ebee3484 158 }
emilmont 27:7110ebee3484 159
emilmont 27:7110ebee3484 160
emilmont 27:7110ebee3484 161 /** \brief Get Priority Mask
emilmont 27:7110ebee3484 162
emilmont 27:7110ebee3484 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 27:7110ebee3484 164
emilmont 27:7110ebee3484 165 \return Priority Mask value
emilmont 27:7110ebee3484 166 */
emilmont 27:7110ebee3484 167 static __INLINE uint32_t __get_PRIMASK(void)
emilmont 27:7110ebee3484 168 {
emilmont 27:7110ebee3484 169 register uint32_t __regPriMask __ASM("primask");
emilmont 27:7110ebee3484 170 return(__regPriMask);
emilmont 27:7110ebee3484 171 }
emilmont 27:7110ebee3484 172
emilmont 27:7110ebee3484 173
emilmont 27:7110ebee3484 174 /** \brief Set Priority Mask
emilmont 27:7110ebee3484 175
emilmont 27:7110ebee3484 176 This function assigns the given value to the Priority Mask Register.
emilmont 27:7110ebee3484 177
emilmont 27:7110ebee3484 178 \param [in] priMask Priority Mask
emilmont 27:7110ebee3484 179 */
emilmont 27:7110ebee3484 180 static __INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 27:7110ebee3484 181 {
emilmont 27:7110ebee3484 182 register uint32_t __regPriMask __ASM("primask");
emilmont 27:7110ebee3484 183 __regPriMask = (priMask);
emilmont 27:7110ebee3484 184 }
emilmont 27:7110ebee3484 185
emilmont 27:7110ebee3484 186
emilmont 27:7110ebee3484 187 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 188
emilmont 27:7110ebee3484 189 /** \brief Enable FIQ
emilmont 27:7110ebee3484 190
emilmont 27:7110ebee3484 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 27:7110ebee3484 192 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 193 */
emilmont 27:7110ebee3484 194 #define __enable_fault_irq __enable_fiq
emilmont 27:7110ebee3484 195
emilmont 27:7110ebee3484 196
emilmont 27:7110ebee3484 197 /** \brief Disable FIQ
emilmont 27:7110ebee3484 198
emilmont 27:7110ebee3484 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 27:7110ebee3484 200 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 201 */
emilmont 27:7110ebee3484 202 #define __disable_fault_irq __disable_fiq
emilmont 27:7110ebee3484 203
emilmont 27:7110ebee3484 204
emilmont 27:7110ebee3484 205 /** \brief Get Base Priority
emilmont 27:7110ebee3484 206
emilmont 27:7110ebee3484 207 This function returns the current value of the Base Priority register.
emilmont 27:7110ebee3484 208
emilmont 27:7110ebee3484 209 \return Base Priority register value
emilmont 27:7110ebee3484 210 */
emilmont 27:7110ebee3484 211 static __INLINE uint32_t __get_BASEPRI(void)
emilmont 27:7110ebee3484 212 {
emilmont 27:7110ebee3484 213 register uint32_t __regBasePri __ASM("basepri");
emilmont 27:7110ebee3484 214 return(__regBasePri);
emilmont 27:7110ebee3484 215 }
emilmont 27:7110ebee3484 216
emilmont 27:7110ebee3484 217
emilmont 27:7110ebee3484 218 /** \brief Set Base Priority
emilmont 27:7110ebee3484 219
emilmont 27:7110ebee3484 220 This function assigns the given value to the Base Priority register.
emilmont 27:7110ebee3484 221
emilmont 27:7110ebee3484 222 \param [in] basePri Base Priority value to set
emilmont 27:7110ebee3484 223 */
emilmont 27:7110ebee3484 224 static __INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 27:7110ebee3484 225 {
emilmont 27:7110ebee3484 226 register uint32_t __regBasePri __ASM("basepri");
emilmont 27:7110ebee3484 227 __regBasePri = (basePri & 0xff);
emilmont 27:7110ebee3484 228 }
emilmont 27:7110ebee3484 229
emilmont 27:7110ebee3484 230
emilmont 27:7110ebee3484 231 /** \brief Get Fault Mask
emilmont 27:7110ebee3484 232
emilmont 27:7110ebee3484 233 This function returns the current value of the Fault Mask register.
emilmont 27:7110ebee3484 234
emilmont 27:7110ebee3484 235 \return Fault Mask register value
emilmont 27:7110ebee3484 236 */
emilmont 27:7110ebee3484 237 static __INLINE uint32_t __get_FAULTMASK(void)
emilmont 27:7110ebee3484 238 {
emilmont 27:7110ebee3484 239 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 27:7110ebee3484 240 return(__regFaultMask);
emilmont 27:7110ebee3484 241 }
emilmont 27:7110ebee3484 242
emilmont 27:7110ebee3484 243
emilmont 27:7110ebee3484 244 /** \brief Set Fault Mask
emilmont 27:7110ebee3484 245
emilmont 27:7110ebee3484 246 This function assigns the given value to the Fault Mask register.
emilmont 27:7110ebee3484 247
emilmont 27:7110ebee3484 248 \param [in] faultMask Fault Mask value to set
emilmont 27:7110ebee3484 249 */
emilmont 27:7110ebee3484 250 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 27:7110ebee3484 251 {
emilmont 27:7110ebee3484 252 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 33:5364839841bd 253 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 27:7110ebee3484 254 }
emilmont 27:7110ebee3484 255
emilmont 27:7110ebee3484 256 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 257
emilmont 27:7110ebee3484 258
emilmont 27:7110ebee3484 259 #if (__CORTEX_M == 0x04)
emilmont 27:7110ebee3484 260
emilmont 27:7110ebee3484 261 /** \brief Get FPSCR
emilmont 27:7110ebee3484 262
emilmont 27:7110ebee3484 263 This function returns the current value of the Floating Point Status/Control register.
emilmont 27:7110ebee3484 264
emilmont 27:7110ebee3484 265 \return Floating Point Status/Control register value
emilmont 27:7110ebee3484 266 */
emilmont 27:7110ebee3484 267 static __INLINE uint32_t __get_FPSCR(void)
emilmont 27:7110ebee3484 268 {
emilmont 33:5364839841bd 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 27:7110ebee3484 270 register uint32_t __regfpscr __ASM("fpscr");
emilmont 27:7110ebee3484 271 return(__regfpscr);
emilmont 27:7110ebee3484 272 #else
emilmont 27:7110ebee3484 273 return(0);
emilmont 27:7110ebee3484 274 #endif
emilmont 27:7110ebee3484 275 }
emilmont 27:7110ebee3484 276
emilmont 27:7110ebee3484 277
emilmont 27:7110ebee3484 278 /** \brief Set FPSCR
emilmont 27:7110ebee3484 279
emilmont 27:7110ebee3484 280 This function assigns the given value to the Floating Point Status/Control register.
emilmont 27:7110ebee3484 281
emilmont 27:7110ebee3484 282 \param [in] fpscr Floating Point Status/Control value to set
emilmont 27:7110ebee3484 283 */
emilmont 27:7110ebee3484 284 static __INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 27:7110ebee3484 285 {
emilmont 33:5364839841bd 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 27:7110ebee3484 287 register uint32_t __regfpscr __ASM("fpscr");
emilmont 27:7110ebee3484 288 __regfpscr = (fpscr);
emilmont 27:7110ebee3484 289 #endif
emilmont 27:7110ebee3484 290 }
emilmont 27:7110ebee3484 291
emilmont 27:7110ebee3484 292 #endif /* (__CORTEX_M == 0x04) */
emilmont 27:7110ebee3484 293
emilmont 27:7110ebee3484 294
emilmont 33:5364839841bd 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 27:7110ebee3484 296 /* IAR iccarm specific functions */
emilmont 27:7110ebee3484 297
emilmont 33:5364839841bd 298 #include <cmsis_iar.h>
emilmont 27:7110ebee3484 299
emilmont 33:5364839841bd 300 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 27:7110ebee3484 301 /* GNU gcc specific functions */
emilmont 27:7110ebee3484 302
emilmont 27:7110ebee3484 303 /** \brief Enable IRQ Interrupts
emilmont 27:7110ebee3484 304
emilmont 27:7110ebee3484 305 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 27:7110ebee3484 306 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 307 */
emilmont 27:7110ebee3484 308 __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
emilmont 27:7110ebee3484 309 {
emilmont 27:7110ebee3484 310 __ASM volatile ("cpsie i");
emilmont 27:7110ebee3484 311 }
emilmont 27:7110ebee3484 312
emilmont 27:7110ebee3484 313
emilmont 27:7110ebee3484 314 /** \brief Disable IRQ Interrupts
emilmont 27:7110ebee3484 315
emilmont 27:7110ebee3484 316 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 27:7110ebee3484 317 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 318 */
emilmont 27:7110ebee3484 319 __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
emilmont 27:7110ebee3484 320 {
emilmont 27:7110ebee3484 321 __ASM volatile ("cpsid i");
emilmont 27:7110ebee3484 322 }
emilmont 27:7110ebee3484 323
emilmont 27:7110ebee3484 324
emilmont 27:7110ebee3484 325 /** \brief Get Control Register
emilmont 27:7110ebee3484 326
emilmont 27:7110ebee3484 327 This function returns the content of the Control Register.
emilmont 27:7110ebee3484 328
emilmont 27:7110ebee3484 329 \return Control Register value
emilmont 27:7110ebee3484 330 */
emilmont 27:7110ebee3484 331 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
emilmont 27:7110ebee3484 332 {
emilmont 27:7110ebee3484 333 uint32_t result;
emilmont 27:7110ebee3484 334
emilmont 27:7110ebee3484 335 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 27:7110ebee3484 336 return(result);
emilmont 27:7110ebee3484 337 }
emilmont 27:7110ebee3484 338
emilmont 27:7110ebee3484 339
emilmont 27:7110ebee3484 340 /** \brief Set Control Register
emilmont 27:7110ebee3484 341
emilmont 27:7110ebee3484 342 This function writes the given value to the Control Register.
emilmont 27:7110ebee3484 343
emilmont 27:7110ebee3484 344 \param [in] control Control Register value to set
emilmont 27:7110ebee3484 345 */
emilmont 27:7110ebee3484 346 __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
emilmont 27:7110ebee3484 347 {
emilmont 27:7110ebee3484 348 __ASM volatile ("MSR control, %0" : : "r" (control) );
emilmont 27:7110ebee3484 349 }
emilmont 27:7110ebee3484 350
emilmont 27:7110ebee3484 351
emilmont 33:5364839841bd 352 /** \brief Get IPSR Register
emilmont 27:7110ebee3484 353
emilmont 33:5364839841bd 354 This function returns the content of the IPSR Register.
emilmont 27:7110ebee3484 355
emilmont 33:5364839841bd 356 \return IPSR Register value
emilmont 27:7110ebee3484 357 */
emilmont 27:7110ebee3484 358 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
emilmont 27:7110ebee3484 359 {
emilmont 27:7110ebee3484 360 uint32_t result;
emilmont 27:7110ebee3484 361
emilmont 27:7110ebee3484 362 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 27:7110ebee3484 363 return(result);
emilmont 27:7110ebee3484 364 }
emilmont 27:7110ebee3484 365
emilmont 27:7110ebee3484 366
emilmont 27:7110ebee3484 367 /** \brief Get APSR Register
emilmont 27:7110ebee3484 368
emilmont 27:7110ebee3484 369 This function returns the content of the APSR Register.
emilmont 27:7110ebee3484 370
emilmont 27:7110ebee3484 371 \return APSR Register value
emilmont 27:7110ebee3484 372 */
emilmont 27:7110ebee3484 373 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
emilmont 27:7110ebee3484 374 {
emilmont 27:7110ebee3484 375 uint32_t result;
emilmont 27:7110ebee3484 376
emilmont 27:7110ebee3484 377 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 27:7110ebee3484 378 return(result);
emilmont 27:7110ebee3484 379 }
emilmont 27:7110ebee3484 380
emilmont 27:7110ebee3484 381
emilmont 27:7110ebee3484 382 /** \brief Get xPSR Register
emilmont 27:7110ebee3484 383
emilmont 27:7110ebee3484 384 This function returns the content of the xPSR Register.
emilmont 27:7110ebee3484 385
emilmont 27:7110ebee3484 386 \return xPSR Register value
emilmont 27:7110ebee3484 387 */
emilmont 27:7110ebee3484 388 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
emilmont 27:7110ebee3484 389 {
emilmont 27:7110ebee3484 390 uint32_t result;
emilmont 27:7110ebee3484 391
emilmont 27:7110ebee3484 392 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 27:7110ebee3484 393 return(result);
emilmont 27:7110ebee3484 394 }
emilmont 27:7110ebee3484 395
emilmont 27:7110ebee3484 396
emilmont 27:7110ebee3484 397 /** \brief Get Process Stack Pointer
emilmont 27:7110ebee3484 398
emilmont 27:7110ebee3484 399 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 400
emilmont 27:7110ebee3484 401 \return PSP Register value
emilmont 27:7110ebee3484 402 */
emilmont 27:7110ebee3484 403 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
emilmont 27:7110ebee3484 404 {
emilmont 27:7110ebee3484 405 register uint32_t result;
emilmont 27:7110ebee3484 406
emilmont 27:7110ebee3484 407 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 27:7110ebee3484 408 return(result);
emilmont 27:7110ebee3484 409 }
emilmont 27:7110ebee3484 410
emilmont 27:7110ebee3484 411
emilmont 27:7110ebee3484 412 /** \brief Set Process Stack Pointer
emilmont 27:7110ebee3484 413
emilmont 27:7110ebee3484 414 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 27:7110ebee3484 415
emilmont 27:7110ebee3484 416 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 27:7110ebee3484 417 */
emilmont 27:7110ebee3484 418 __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 27:7110ebee3484 419 {
emilmont 27:7110ebee3484 420 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
emilmont 27:7110ebee3484 421 }
emilmont 27:7110ebee3484 422
emilmont 27:7110ebee3484 423
emilmont 27:7110ebee3484 424 /** \brief Get Main Stack Pointer
emilmont 27:7110ebee3484 425
emilmont 27:7110ebee3484 426 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 427
emilmont 27:7110ebee3484 428 \return MSP Register value
emilmont 27:7110ebee3484 429 */
emilmont 27:7110ebee3484 430 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
emilmont 27:7110ebee3484 431 {
emilmont 27:7110ebee3484 432 register uint32_t result;
emilmont 27:7110ebee3484 433
emilmont 27:7110ebee3484 434 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 27:7110ebee3484 435 return(result);
emilmont 27:7110ebee3484 436 }
emilmont 27:7110ebee3484 437
emilmont 27:7110ebee3484 438
emilmont 27:7110ebee3484 439 /** \brief Set Main Stack Pointer
emilmont 27:7110ebee3484 440
emilmont 27:7110ebee3484 441 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 27:7110ebee3484 442
emilmont 27:7110ebee3484 443 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 27:7110ebee3484 444 */
emilmont 27:7110ebee3484 445 __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 27:7110ebee3484 446 {
emilmont 27:7110ebee3484 447 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
emilmont 27:7110ebee3484 448 }
emilmont 27:7110ebee3484 449
emilmont 27:7110ebee3484 450
emilmont 27:7110ebee3484 451 /** \brief Get Priority Mask
emilmont 27:7110ebee3484 452
emilmont 27:7110ebee3484 453 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 27:7110ebee3484 454
emilmont 27:7110ebee3484 455 \return Priority Mask value
emilmont 27:7110ebee3484 456 */
emilmont 27:7110ebee3484 457 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
emilmont 27:7110ebee3484 458 {
emilmont 27:7110ebee3484 459 uint32_t result;
emilmont 27:7110ebee3484 460
emilmont 27:7110ebee3484 461 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 27:7110ebee3484 462 return(result);
emilmont 27:7110ebee3484 463 }
emilmont 27:7110ebee3484 464
emilmont 27:7110ebee3484 465
emilmont 27:7110ebee3484 466 /** \brief Set Priority Mask
emilmont 27:7110ebee3484 467
emilmont 27:7110ebee3484 468 This function assigns the given value to the Priority Mask Register.
emilmont 27:7110ebee3484 469
emilmont 27:7110ebee3484 470 \param [in] priMask Priority Mask
emilmont 27:7110ebee3484 471 */
emilmont 27:7110ebee3484 472 __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 27:7110ebee3484 473 {
emilmont 27:7110ebee3484 474 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
emilmont 27:7110ebee3484 475 }
emilmont 27:7110ebee3484 476
emilmont 27:7110ebee3484 477
emilmont 27:7110ebee3484 478 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 479
emilmont 27:7110ebee3484 480 /** \brief Enable FIQ
emilmont 27:7110ebee3484 481
emilmont 27:7110ebee3484 482 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 27:7110ebee3484 483 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 484 */
emilmont 27:7110ebee3484 485 __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
emilmont 27:7110ebee3484 486 {
emilmont 27:7110ebee3484 487 __ASM volatile ("cpsie f");
emilmont 27:7110ebee3484 488 }
emilmont 27:7110ebee3484 489
emilmont 27:7110ebee3484 490
emilmont 27:7110ebee3484 491 /** \brief Disable FIQ
emilmont 27:7110ebee3484 492
emilmont 27:7110ebee3484 493 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 27:7110ebee3484 494 Can only be executed in Privileged modes.
emilmont 27:7110ebee3484 495 */
emilmont 27:7110ebee3484 496 __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
emilmont 27:7110ebee3484 497 {
emilmont 27:7110ebee3484 498 __ASM volatile ("cpsid f");
emilmont 27:7110ebee3484 499 }
emilmont 27:7110ebee3484 500
emilmont 27:7110ebee3484 501
emilmont 27:7110ebee3484 502 /** \brief Get Base Priority
emilmont 27:7110ebee3484 503
emilmont 27:7110ebee3484 504 This function returns the current value of the Base Priority register.
emilmont 27:7110ebee3484 505
emilmont 27:7110ebee3484 506 \return Base Priority register value
emilmont 27:7110ebee3484 507 */
emilmont 27:7110ebee3484 508 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
emilmont 27:7110ebee3484 509 {
emilmont 27:7110ebee3484 510 uint32_t result;
emilmont 27:7110ebee3484 511
emilmont 27:7110ebee3484 512 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 27:7110ebee3484 513 return(result);
emilmont 27:7110ebee3484 514 }
emilmont 27:7110ebee3484 515
emilmont 27:7110ebee3484 516
emilmont 27:7110ebee3484 517 /** \brief Set Base Priority
emilmont 27:7110ebee3484 518
emilmont 27:7110ebee3484 519 This function assigns the given value to the Base Priority register.
emilmont 27:7110ebee3484 520
emilmont 27:7110ebee3484 521 \param [in] basePri Base Priority value to set
emilmont 27:7110ebee3484 522 */
emilmont 27:7110ebee3484 523 __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
emilmont 27:7110ebee3484 524 {
emilmont 27:7110ebee3484 525 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
emilmont 27:7110ebee3484 526 }
emilmont 27:7110ebee3484 527
emilmont 27:7110ebee3484 528
emilmont 27:7110ebee3484 529 /** \brief Get Fault Mask
emilmont 27:7110ebee3484 530
emilmont 27:7110ebee3484 531 This function returns the current value of the Fault Mask register.
emilmont 27:7110ebee3484 532
emilmont 27:7110ebee3484 533 \return Fault Mask register value
emilmont 27:7110ebee3484 534 */
emilmont 27:7110ebee3484 535 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
emilmont 27:7110ebee3484 536 {
emilmont 27:7110ebee3484 537 uint32_t result;
emilmont 27:7110ebee3484 538
emilmont 27:7110ebee3484 539 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 27:7110ebee3484 540 return(result);
emilmont 27:7110ebee3484 541 }
emilmont 27:7110ebee3484 542
emilmont 27:7110ebee3484 543
emilmont 27:7110ebee3484 544 /** \brief Set Fault Mask
emilmont 27:7110ebee3484 545
emilmont 27:7110ebee3484 546 This function assigns the given value to the Fault Mask register.
emilmont 27:7110ebee3484 547
emilmont 27:7110ebee3484 548 \param [in] faultMask Fault Mask value to set
emilmont 27:7110ebee3484 549 */
emilmont 27:7110ebee3484 550 __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 27:7110ebee3484 551 {
emilmont 27:7110ebee3484 552 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
emilmont 27:7110ebee3484 553 }
emilmont 27:7110ebee3484 554
emilmont 27:7110ebee3484 555 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 556
emilmont 27:7110ebee3484 557
emilmont 27:7110ebee3484 558 #if (__CORTEX_M == 0x04)
emilmont 27:7110ebee3484 559
emilmont 27:7110ebee3484 560 /** \brief Get FPSCR
emilmont 27:7110ebee3484 561
emilmont 27:7110ebee3484 562 This function returns the current value of the Floating Point Status/Control register.
emilmont 27:7110ebee3484 563
emilmont 27:7110ebee3484 564 \return Floating Point Status/Control register value
emilmont 27:7110ebee3484 565 */
emilmont 27:7110ebee3484 566 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
emilmont 27:7110ebee3484 567 {
emilmont 33:5364839841bd 568 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 27:7110ebee3484 569 uint32_t result;
emilmont 27:7110ebee3484 570
emilmont 33:5364839841bd 571 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 27:7110ebee3484 572 return(result);
emilmont 27:7110ebee3484 573 #else
emilmont 27:7110ebee3484 574 return(0);
emilmont 27:7110ebee3484 575 #endif
emilmont 27:7110ebee3484 576 }
emilmont 27:7110ebee3484 577
emilmont 27:7110ebee3484 578
emilmont 27:7110ebee3484 579 /** \brief Set FPSCR
emilmont 27:7110ebee3484 580
emilmont 27:7110ebee3484 581 This function assigns the given value to the Floating Point Status/Control register.
emilmont 27:7110ebee3484 582
emilmont 27:7110ebee3484 583 \param [in] fpscr Floating Point Status/Control value to set
emilmont 27:7110ebee3484 584 */
emilmont 27:7110ebee3484 585 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 27:7110ebee3484 586 {
emilmont 33:5364839841bd 587 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 33:5364839841bd 588 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
emilmont 27:7110ebee3484 589 #endif
emilmont 27:7110ebee3484 590 }
emilmont 27:7110ebee3484 591
emilmont 27:7110ebee3484 592 #endif /* (__CORTEX_M == 0x04) */
emilmont 27:7110ebee3484 593
emilmont 27:7110ebee3484 594
emilmont 33:5364839841bd 595 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 27:7110ebee3484 596 /* TASKING carm specific functions */
emilmont 27:7110ebee3484 597
emilmont 27:7110ebee3484 598 /*
emilmont 27:7110ebee3484 599 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 27:7110ebee3484 600 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 27:7110ebee3484 601 * Including the CMSIS ones.
emilmont 27:7110ebee3484 602 */
emilmont 27:7110ebee3484 603
emilmont 27:7110ebee3484 604 #endif
emilmont 27:7110ebee3484 605
emilmont 27:7110ebee3484 606 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 27:7110ebee3484 607
emilmont 27:7110ebee3484 608
emilmont 33:5364839841bd 609 #endif /* __CORE_CMFUNC_H */