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TARGET_NRF51822/nrf_soc.h@80:8e73be2a2ac1, 2014-02-21 (annotated)

Committer:
emilmont
Date:
Fri Feb 21 12:21:39 2014 +0000
Revision:
80:8e73be2a2ac1
First alpha release for the NRF51822 target (to be tested in the online IDE)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved.
emilmont 80:8e73be2a2ac1 2 *
emilmont 80:8e73be2a2ac1 3 * The information contained herein is confidential property of Nordic Semiconductor. The use,
emilmont 80:8e73be2a2ac1 4 * copying, transfer or disclosure of such information is prohibited except by express written
emilmont 80:8e73be2a2ac1 5 * agreement with Nordic Semiconductor.
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 */
emilmont 80:8e73be2a2ac1 8
emilmont 80:8e73be2a2ac1 9 /**
emilmont 80:8e73be2a2ac1 10 @defgroup nrf_soc_api SoC Library API
emilmont 80:8e73be2a2ac1 11 @{
emilmont 80:8e73be2a2ac1 12
emilmont 80:8e73be2a2ac1 13 @brief APIs for the SoC library.
emilmont 80:8e73be2a2ac1 14
emilmont 80:8e73be2a2ac1 15 */
emilmont 80:8e73be2a2ac1 16
emilmont 80:8e73be2a2ac1 17 #ifndef NRF_SOC_H__
emilmont 80:8e73be2a2ac1 18 #define NRF_SOC_H__
emilmont 80:8e73be2a2ac1 19
emilmont 80:8e73be2a2ac1 20 #include <stdint.h>
emilmont 80:8e73be2a2ac1 21 #include <stdbool.h>
emilmont 80:8e73be2a2ac1 22 #include "nrf_svc.h"
emilmont 80:8e73be2a2ac1 23 #include "nrf51.h"
emilmont 80:8e73be2a2ac1 24 #include "nrf51_bitfields.h"
emilmont 80:8e73be2a2ac1 25 #include "nrf_error_soc.h"
emilmont 80:8e73be2a2ac1 26
emilmont 80:8e73be2a2ac1 27 /** @addtogroup NRF_SOC_DEFINES Defines
emilmont 80:8e73be2a2ac1 28 * @{ */
emilmont 80:8e73be2a2ac1 29
emilmont 80:8e73be2a2ac1 30 /**@brief The number of the lowest SVC number reserved for the SoC library. */
emilmont 80:8e73be2a2ac1 31 #define SOC_SVC_BASE 0x20
emilmont 80:8e73be2a2ac1 32
emilmont 80:8e73be2a2ac1 33 /**@brief Guranteed time for application to process radio inactive notification. */
emilmont 80:8e73be2a2ac1 34 #define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62)
emilmont 80:8e73be2a2ac1 35
emilmont 80:8e73be2a2ac1 36 #define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */
emilmont 80:8e73be2a2ac1 37 #define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */
emilmont 80:8e73be2a2ac1 38 #define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */
emilmont 80:8e73be2a2ac1 39
emilmont 80:8e73be2a2ac1 40 #define SD_EVT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
emilmont 80:8e73be2a2ac1 41 #define SD_EVT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
emilmont 80:8e73be2a2ac1 42 #define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */
emilmont 80:8e73be2a2ac1 43 #define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. */
emilmont 80:8e73be2a2ac1 44
emilmont 80:8e73be2a2ac1 45 /** @} */
emilmont 80:8e73be2a2ac1 46
emilmont 80:8e73be2a2ac1 47 /** @addtogroup NRF_SOC_TYPES Types
emilmont 80:8e73be2a2ac1 48 * @{ */
emilmont 80:8e73be2a2ac1 49
emilmont 80:8e73be2a2ac1 50 /**@brief The SVC numbers used by the SVC functions in the SoC library. */
emilmont 80:8e73be2a2ac1 51 enum NRF_SOC_SVCS
emilmont 80:8e73be2a2ac1 52 {
emilmont 80:8e73be2a2ac1 53 SD_MUTEX_NEW = SOC_SVC_BASE,
emilmont 80:8e73be2a2ac1 54 SD_MUTEX_ACQUIRE,
emilmont 80:8e73be2a2ac1 55 SD_MUTEX_RELEASE,
emilmont 80:8e73be2a2ac1 56 SD_NVIC_ENABLEIRQ,
emilmont 80:8e73be2a2ac1 57 SD_NVIC_DISABLEIRQ,
emilmont 80:8e73be2a2ac1 58 SD_NVIC_GETPENDINGIRQ,
emilmont 80:8e73be2a2ac1 59 SD_NVIC_SETPENDINGIRQ,
emilmont 80:8e73be2a2ac1 60 SD_NVIC_CLEARPENDINGIRQ,
emilmont 80:8e73be2a2ac1 61 SD_NVIC_SETPRIORITY,
emilmont 80:8e73be2a2ac1 62 SD_NVIC_GETPRIORITY,
emilmont 80:8e73be2a2ac1 63 SD_NVIC_SYSTEMRESET,
emilmont 80:8e73be2a2ac1 64 SD_NVIC_CRITICAL_REGION_ENTER,
emilmont 80:8e73be2a2ac1 65 SD_NVIC_CRITICAL_REGION_EXIT,
emilmont 80:8e73be2a2ac1 66 SD_RAND_APPLICATION_POOL_CAPACITY,
emilmont 80:8e73be2a2ac1 67 SD_RAND_APPLICATION_BYTES_AVAILABLE,
emilmont 80:8e73be2a2ac1 68 SD_RAND_APPLICATION_GET_VECTOR,
emilmont 80:8e73be2a2ac1 69 SD_POWER_MODE_SET,
emilmont 80:8e73be2a2ac1 70 SD_POWER_SYSTEM_OFF,
emilmont 80:8e73be2a2ac1 71 SD_POWER_RESET_REASON_GET,
emilmont 80:8e73be2a2ac1 72 SD_POWER_RESET_REASON_CLR,
emilmont 80:8e73be2a2ac1 73 SD_POWER_POF_ENABLE,
emilmont 80:8e73be2a2ac1 74 SD_POWER_POF_THRESHOLD_SET,
emilmont 80:8e73be2a2ac1 75 SD_POWER_RAMON_SET,
emilmont 80:8e73be2a2ac1 76 SD_POWER_RAMON_CLR,
emilmont 80:8e73be2a2ac1 77 SD_POWER_RAMON_GET,
emilmont 80:8e73be2a2ac1 78 SD_POWER_GPREGRET_SET,
emilmont 80:8e73be2a2ac1 79 SD_POWER_GPREGRET_CLR,
emilmont 80:8e73be2a2ac1 80 SD_POWER_GPREGRET_GET,
emilmont 80:8e73be2a2ac1 81 SD_POWER_DCDC_MODE_SET,
emilmont 80:8e73be2a2ac1 82 SD_APP_EVT_WAIT,
emilmont 80:8e73be2a2ac1 83 SD_CLOCK_HFCLK_REQUEST,
emilmont 80:8e73be2a2ac1 84 SD_CLOCK_HFCLK_RELEASE,
emilmont 80:8e73be2a2ac1 85 SD_CLOCK_HFCLK_IS_RUNNING,
emilmont 80:8e73be2a2ac1 86 SD_PPI_CHANNEL_ENABLE_GET,
emilmont 80:8e73be2a2ac1 87 SD_PPI_CHANNEL_ENABLE_SET,
emilmont 80:8e73be2a2ac1 88 SD_PPI_CHANNEL_ENABLE_CLR,
emilmont 80:8e73be2a2ac1 89 SD_PPI_CHANNEL_ASSIGN,
emilmont 80:8e73be2a2ac1 90 SD_PPI_GROUP_TASK_ENABLE,
emilmont 80:8e73be2a2ac1 91 SD_PPI_GROUP_TASK_DISABLE,
emilmont 80:8e73be2a2ac1 92 SD_PPI_GROUP_ASSIGN,
emilmont 80:8e73be2a2ac1 93 SD_PPI_GROUP_GET,
emilmont 80:8e73be2a2ac1 94 SD_RADIO_NOTIFICATION_CFG_SET,
emilmont 80:8e73be2a2ac1 95 SD_ECB_BLOCK_ENCRYPT,
emilmont 80:8e73be2a2ac1 96 SD_RESERVED1,
emilmont 80:8e73be2a2ac1 97 SD_RESERVED2,
emilmont 80:8e73be2a2ac1 98 SD_RESERVED3,
emilmont 80:8e73be2a2ac1 99 SD_EVT_GET,
emilmont 80:8e73be2a2ac1 100 SD_TEMP_GET,
emilmont 80:8e73be2a2ac1 101 SD_FLASH_ERASE_PAGE,
emilmont 80:8e73be2a2ac1 102 SD_FLASH_WRITE,
emilmont 80:8e73be2a2ac1 103 SD_FLASH_PROTECT,
emilmont 80:8e73be2a2ac1 104 SVC_SOC_LAST
emilmont 80:8e73be2a2ac1 105 };
emilmont 80:8e73be2a2ac1 106
emilmont 80:8e73be2a2ac1 107 /**@brief Possible values of a ::nrf_mutex_t. */
emilmont 80:8e73be2a2ac1 108 enum NRF_MUTEX_VALUES
emilmont 80:8e73be2a2ac1 109 {
emilmont 80:8e73be2a2ac1 110 NRF_MUTEX_FREE,
emilmont 80:8e73be2a2ac1 111 NRF_MUTEX_TAKEN
emilmont 80:8e73be2a2ac1 112 };
emilmont 80:8e73be2a2ac1 113
emilmont 80:8e73be2a2ac1 114 /**@brief Possible values of ::nrf_app_irq_priority_t. */
emilmont 80:8e73be2a2ac1 115 enum NRF_APP_PRIORITIES
emilmont 80:8e73be2a2ac1 116 {
emilmont 80:8e73be2a2ac1 117 NRF_APP_PRIORITY_HIGH = 1,
emilmont 80:8e73be2a2ac1 118 NRF_APP_PRIORITY_LOW = 3
emilmont 80:8e73be2a2ac1 119 };
emilmont 80:8e73be2a2ac1 120
emilmont 80:8e73be2a2ac1 121 /**@brief Possible values of ::nrf_power_mode_t. */
emilmont 80:8e73be2a2ac1 122 enum NRF_POWER_MODES
emilmont 80:8e73be2a2ac1 123 {
emilmont 80:8e73be2a2ac1 124 NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */
emilmont 80:8e73be2a2ac1 125 NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */
emilmont 80:8e73be2a2ac1 126 };
emilmont 80:8e73be2a2ac1 127
emilmont 80:8e73be2a2ac1 128
emilmont 80:8e73be2a2ac1 129 /**@brief Possible values of ::nrf_power_failure_threshold_t */
emilmont 80:8e73be2a2ac1 130 enum NRF_POWER_THRESHOLDS
emilmont 80:8e73be2a2ac1 131 {
emilmont 80:8e73be2a2ac1 132 NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */
emilmont 80:8e73be2a2ac1 133 NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */
emilmont 80:8e73be2a2ac1 134 NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */
emilmont 80:8e73be2a2ac1 135 NRF_POWER_THRESHOLD_V27 /**< 2.7 Volts power failure threshold. */
emilmont 80:8e73be2a2ac1 136 };
emilmont 80:8e73be2a2ac1 137
emilmont 80:8e73be2a2ac1 138
emilmont 80:8e73be2a2ac1 139 /**@brief Possible values of ::nrf_power_dcdc_mode_t. */
emilmont 80:8e73be2a2ac1 140 enum NRF_POWER_DCDC_MODES
emilmont 80:8e73be2a2ac1 141 {
emilmont 80:8e73be2a2ac1 142 NRF_POWER_DCDC_MODE_OFF, /**< The DCDC is always off. */
emilmont 80:8e73be2a2ac1 143 NRF_POWER_DCDC_MODE_ON, /**< The DCDC is always on. */
emilmont 80:8e73be2a2ac1 144 NRF_POWER_DCDC_MODE_AUTOMATIC /**< The DCDC is automatically managed. */
emilmont 80:8e73be2a2ac1 145 };
emilmont 80:8e73be2a2ac1 146
emilmont 80:8e73be2a2ac1 147 /**@brief Possible values of ::nrf_radio_notification_distance_t. */
emilmont 80:8e73be2a2ac1 148 enum NRF_RADIO_NOTIFICATION_DISTANCES
emilmont 80:8e73be2a2ac1 149 {
emilmont 80:8e73be2a2ac1 150 NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */
emilmont 80:8e73be2a2ac1 151 NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */
emilmont 80:8e73be2a2ac1 152 NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */
emilmont 80:8e73be2a2ac1 153 NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */
emilmont 80:8e73be2a2ac1 154 NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */
emilmont 80:8e73be2a2ac1 155 NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */
emilmont 80:8e73be2a2ac1 156 NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */
emilmont 80:8e73be2a2ac1 157 };
emilmont 80:8e73be2a2ac1 158
emilmont 80:8e73be2a2ac1 159
emilmont 80:8e73be2a2ac1 160 /**@brief Possible values of ::nrf_radio_notification_type_t. */
emilmont 80:8e73be2a2ac1 161 enum NRF_RADIO_NOTIFICATION_TYPES
emilmont 80:8e73be2a2ac1 162 {
emilmont 80:8e73be2a2ac1 163 NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */
emilmont 80:8e73be2a2ac1 164 NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */
emilmont 80:8e73be2a2ac1 165 NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */
emilmont 80:8e73be2a2ac1 166 NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */
emilmont 80:8e73be2a2ac1 167 };
emilmont 80:8e73be2a2ac1 168
emilmont 80:8e73be2a2ac1 169 /**@brief SoC Events. */
emilmont 80:8e73be2a2ac1 170 enum NRF_SOC_EVTS
emilmont 80:8e73be2a2ac1 171 {
emilmont 80:8e73be2a2ac1 172 NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */
emilmont 80:8e73be2a2ac1 173 NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */
emilmont 80:8e73be2a2ac1 174 NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */
emilmont 80:8e73be2a2ac1 175 NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */
emilmont 80:8e73be2a2ac1 176 NRF_EVT_RESERVED1,
emilmont 80:8e73be2a2ac1 177 NRF_EVT_RESERVED2,
emilmont 80:8e73be2a2ac1 178 NRF_EVT_RESERVED3,
emilmont 80:8e73be2a2ac1 179 NRF_EVT_RESERVED4,
emilmont 80:8e73be2a2ac1 180 NRF_EVT_RESERVED5,
emilmont 80:8e73be2a2ac1 181 NRF_EVT_NUMBER_OF_EVTS
emilmont 80:8e73be2a2ac1 182 };
emilmont 80:8e73be2a2ac1 183
emilmont 80:8e73be2a2ac1 184 /** @} */
emilmont 80:8e73be2a2ac1 185
emilmont 80:8e73be2a2ac1 186 /** @addtogroup NRF_SOC_TYPES Types
emilmont 80:8e73be2a2ac1 187 * @{ */
emilmont 80:8e73be2a2ac1 188
emilmont 80:8e73be2a2ac1 189 /**@brief Represents a mutex for use with the nrf_mutex functions.
emilmont 80:8e73be2a2ac1 190 * @note Accessing the value directly is not safe, use the mutex functions!
emilmont 80:8e73be2a2ac1 191 */
emilmont 80:8e73be2a2ac1 192 typedef volatile uint8_t nrf_mutex_t;
emilmont 80:8e73be2a2ac1 193
emilmont 80:8e73be2a2ac1 194 /**@brief The interrupt priorities available to the application while the softdevice is active. */
emilmont 80:8e73be2a2ac1 195 typedef uint8_t nrf_app_irq_priority_t;
emilmont 80:8e73be2a2ac1 196
emilmont 80:8e73be2a2ac1 197 /**@brief Represents a power mode, used in power mode functions */
emilmont 80:8e73be2a2ac1 198 typedef uint8_t nrf_power_mode_t;
emilmont 80:8e73be2a2ac1 199
emilmont 80:8e73be2a2ac1 200 /**@brief Represents a power failure threshold value. */
emilmont 80:8e73be2a2ac1 201 typedef uint8_t nrf_power_failure_threshold_t;
emilmont 80:8e73be2a2ac1 202
emilmont 80:8e73be2a2ac1 203 /**@brief Represents a DCDC mode value. */
emilmont 80:8e73be2a2ac1 204 typedef uint32_t nrf_power_dcdc_mode_t;
emilmont 80:8e73be2a2ac1 205
emilmont 80:8e73be2a2ac1 206 /**@brief Radio notification distances. */
emilmont 80:8e73be2a2ac1 207 typedef uint8_t nrf_radio_notification_distance_t;
emilmont 80:8e73be2a2ac1 208
emilmont 80:8e73be2a2ac1 209 /**@brief Radio notification types. */
emilmont 80:8e73be2a2ac1 210 typedef uint8_t nrf_radio_notification_type_t;
emilmont 80:8e73be2a2ac1 211
emilmont 80:8e73be2a2ac1 212
emilmont 80:8e73be2a2ac1 213 /**@brief AES ECB data structure */
emilmont 80:8e73be2a2ac1 214 typedef struct
emilmont 80:8e73be2a2ac1 215 {
emilmont 80:8e73be2a2ac1 216 uint8_t key[SOC_ECB_KEY_LENGTH]; /**< Encryption key. */
emilmont 80:8e73be2a2ac1 217 uint8_t cleartext[SOC_ECB_CLEARTEXT_LENGTH]; /**< Clear Text data. */
emilmont 80:8e73be2a2ac1 218 uint8_t ciphertext[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Cipher Text data. */
emilmont 80:8e73be2a2ac1 219 } nrf_ecb_hal_data_t;
emilmont 80:8e73be2a2ac1 220
emilmont 80:8e73be2a2ac1 221 /** @} */
emilmont 80:8e73be2a2ac1 222
emilmont 80:8e73be2a2ac1 223 /** @addtogroup NRF_SOC_FUNCTIONS Functions
emilmont 80:8e73be2a2ac1 224 * @{ */
emilmont 80:8e73be2a2ac1 225
emilmont 80:8e73be2a2ac1 226 /**@brief Initialize a mutex.
emilmont 80:8e73be2a2ac1 227 *
emilmont 80:8e73be2a2ac1 228 * @param[in] p_mutex Pointer to the mutex to initialize.
emilmont 80:8e73be2a2ac1 229 *
emilmont 80:8e73be2a2ac1 230 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 231 */
emilmont 80:8e73be2a2ac1 232 SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex));
emilmont 80:8e73be2a2ac1 233
emilmont 80:8e73be2a2ac1 234 /**@brief Attempt to acquire a mutex.
emilmont 80:8e73be2a2ac1 235 *
emilmont 80:8e73be2a2ac1 236 * @param[in] p_mutex Pointer to the mutex to acquire.
emilmont 80:8e73be2a2ac1 237 *
emilmont 80:8e73be2a2ac1 238 * @retval ::NRF_SUCCESS The mutex was successfully acquired.
emilmont 80:8e73be2a2ac1 239 * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired.
emilmont 80:8e73be2a2ac1 240 */
emilmont 80:8e73be2a2ac1 241 SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex));
emilmont 80:8e73be2a2ac1 242
emilmont 80:8e73be2a2ac1 243 /**@brief Release a mutex.
emilmont 80:8e73be2a2ac1 244 *
emilmont 80:8e73be2a2ac1 245 * @param[in] p_mutex Pointer to the mutex to release.
emilmont 80:8e73be2a2ac1 246 *
emilmont 80:8e73be2a2ac1 247 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 248 */
emilmont 80:8e73be2a2ac1 249 SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex));
emilmont 80:8e73be2a2ac1 250
emilmont 80:8e73be2a2ac1 251 /**@brief Enable External Interrupt.
emilmont 80:8e73be2a2ac1 252 * @note Corresponds to NVIC_EnableIRQ in CMSIS.
emilmont 80:8e73be2a2ac1 253 *
emilmont 80:8e73be2a2ac1 254 * @pre{IRQn is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 255 *
emilmont 80:8e73be2a2ac1 256 * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS.
emilmont 80:8e73be2a2ac1 257 *
emilmont 80:8e73be2a2ac1 258 * @retval ::NRF_SUCCESS The interrupt was enabled.
emilmont 80:8e73be2a2ac1 259 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
emilmont 80:8e73be2a2ac1 260 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application.
emilmont 80:8e73be2a2ac1 261 */
emilmont 80:8e73be2a2ac1 262 SVCALL(SD_NVIC_ENABLEIRQ, uint32_t, sd_nvic_EnableIRQ(IRQn_Type IRQn));
emilmont 80:8e73be2a2ac1 263
emilmont 80:8e73be2a2ac1 264 /**@brief Disable External Interrupt.
emilmont 80:8e73be2a2ac1 265 * @note Corresponds to NVIC_DisableIRQ in CMSIS.
emilmont 80:8e73be2a2ac1 266 *
emilmont 80:8e73be2a2ac1 267 * @pre{IRQn is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 268 *
emilmont 80:8e73be2a2ac1 269 * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS
emilmont 80:8e73be2a2ac1 270 *
emilmont 80:8e73be2a2ac1 271 * @retval ::NRF_SUCCESS The interrupt was disabled.
emilmont 80:8e73be2a2ac1 272 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
emilmont 80:8e73be2a2ac1 273 */
emilmont 80:8e73be2a2ac1 274 SVCALL(SD_NVIC_DISABLEIRQ, uint32_t, sd_nvic_DisableIRQ(IRQn_Type IRQn));
emilmont 80:8e73be2a2ac1 275
emilmont 80:8e73be2a2ac1 276 /**@brief Get Pending Interrupt.
emilmont 80:8e73be2a2ac1 277 * @note Corresponds to NVIC_GetPendingIRQ in CMSIS.
emilmont 80:8e73be2a2ac1 278 *
emilmont 80:8e73be2a2ac1 279 * @pre{IRQn is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 280 *
emilmont 80:8e73be2a2ac1 281 * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS.
emilmont 80:8e73be2a2ac1 282 * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ.
emilmont 80:8e73be2a2ac1 283 *
emilmont 80:8e73be2a2ac1 284 * @retval ::NRF_SUCCESS The interrupt is available for the application.
emilmont 80:8e73be2a2ac1 285 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
emilmont 80:8e73be2a2ac1 286 */
emilmont 80:8e73be2a2ac1 287 SVCALL(SD_NVIC_GETPENDINGIRQ, uint32_t, sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq));
emilmont 80:8e73be2a2ac1 288
emilmont 80:8e73be2a2ac1 289 /**@brief Set Pending Interrupt.
emilmont 80:8e73be2a2ac1 290 * @note Corresponds to NVIC_SetPendingIRQ in CMSIS.
emilmont 80:8e73be2a2ac1 291 *
emilmont 80:8e73be2a2ac1 292 * @pre{IRQn is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 293 *
emilmont 80:8e73be2a2ac1 294 * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS.
emilmont 80:8e73be2a2ac1 295 *
emilmont 80:8e73be2a2ac1 296 * @retval ::NRF_SUCCESS The interrupt is set pending.
emilmont 80:8e73be2a2ac1 297 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
emilmont 80:8e73be2a2ac1 298 */
emilmont 80:8e73be2a2ac1 299 SVCALL(SD_NVIC_SETPENDINGIRQ, uint32_t, sd_nvic_SetPendingIRQ(IRQn_Type IRQn));
emilmont 80:8e73be2a2ac1 300
emilmont 80:8e73be2a2ac1 301 /**@brief Clear Pending Interrupt.
emilmont 80:8e73be2a2ac1 302 * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS.
emilmont 80:8e73be2a2ac1 303 *
emilmont 80:8e73be2a2ac1 304 * @pre{IRQn is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 305 *
emilmont 80:8e73be2a2ac1 306 * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS.
emilmont 80:8e73be2a2ac1 307 *
emilmont 80:8e73be2a2ac1 308 * @retval ::NRF_SUCCESS The interrupt pending flag is cleared.
emilmont 80:8e73be2a2ac1 309 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
emilmont 80:8e73be2a2ac1 310 */
emilmont 80:8e73be2a2ac1 311 SVCALL(SD_NVIC_CLEARPENDINGIRQ, uint32_t, sd_nvic_ClearPendingIRQ(IRQn_Type IRQn));
emilmont 80:8e73be2a2ac1 312
emilmont 80:8e73be2a2ac1 313 /**@brief Set Interrupt Priority.
emilmont 80:8e73be2a2ac1 314 * @note Corresponds to NVIC_SetPriority in CMSIS.
emilmont 80:8e73be2a2ac1 315 *
emilmont 80:8e73be2a2ac1 316 * @pre{IRQn is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 317 * @pre{priority is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 318 *
emilmont 80:8e73be2a2ac1 319 * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS.
emilmont 80:8e73be2a2ac1 320 * @param[in] priority A valid IRQ priority for use by the application.
emilmont 80:8e73be2a2ac1 321 *
emilmont 80:8e73be2a2ac1 322 * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application.
emilmont 80:8e73be2a2ac1 323 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
emilmont 80:8e73be2a2ac1 324 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application.
emilmont 80:8e73be2a2ac1 325 */
emilmont 80:8e73be2a2ac1 326 SVCALL(SD_NVIC_SETPRIORITY, uint32_t, sd_nvic_SetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t priority));
emilmont 80:8e73be2a2ac1 327
emilmont 80:8e73be2a2ac1 328 /**@brief Get Interrupt Priority.
emilmont 80:8e73be2a2ac1 329 * @note Corresponds to NVIC_GetPriority in CMSIS.
emilmont 80:8e73be2a2ac1 330 *
emilmont 80:8e73be2a2ac1 331 * @pre{IRQn is valid and not reserved by the stack}
emilmont 80:8e73be2a2ac1 332 *
emilmont 80:8e73be2a2ac1 333 * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS.
emilmont 80:8e73be2a2ac1 334 * @param[out] p_priority Return value from NVIC_GetPriority.
emilmont 80:8e73be2a2ac1 335 *
emilmont 80:8e73be2a2ac1 336 * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority.
emilmont 80:8e73be2a2ac1 337 * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application.
emilmont 80:8e73be2a2ac1 338 */
emilmont 80:8e73be2a2ac1 339 SVCALL(SD_NVIC_GETPRIORITY, uint32_t, sd_nvic_GetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t * p_priority));
emilmont 80:8e73be2a2ac1 340
emilmont 80:8e73be2a2ac1 341 /**@brief System Reset.
emilmont 80:8e73be2a2ac1 342 * @note Corresponds to NVIC_SystemReset in CMSIS.
emilmont 80:8e73be2a2ac1 343 *
emilmont 80:8e73be2a2ac1 344 * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN
emilmont 80:8e73be2a2ac1 345 */
emilmont 80:8e73be2a2ac1 346 SVCALL(SD_NVIC_SYSTEMRESET, uint32_t, sd_nvic_SystemReset(void));
emilmont 80:8e73be2a2ac1 347
emilmont 80:8e73be2a2ac1 348 /**@brief Enters critical region.
emilmont 80:8e73be2a2ac1 349 *
emilmont 80:8e73be2a2ac1 350 * @post Application interrupts will be disabled.
emilmont 80:8e73be2a2ac1 351 * @sa sd_nvic_critical_region_exit
emilmont 80:8e73be2a2ac1 352 *
emilmont 80:8e73be2a2ac1 353 * @param[out] p_is_nested_critical_region 1: If in a nested critical region.
emilmont 80:8e73be2a2ac1 354 * 0: Otherwise.
emilmont 80:8e73be2a2ac1 355 *
emilmont 80:8e73be2a2ac1 356 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 357 */
emilmont 80:8e73be2a2ac1 358 SVCALL(SD_NVIC_CRITICAL_REGION_ENTER, uint32_t, sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region));
emilmont 80:8e73be2a2ac1 359
emilmont 80:8e73be2a2ac1 360 /**@brief Exit critical region.
emilmont 80:8e73be2a2ac1 361 *
emilmont 80:8e73be2a2ac1 362 * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter.
emilmont 80:8e73be2a2ac1 363 * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called.
emilmont 80:8e73be2a2ac1 364 *
emilmont 80:8e73be2a2ac1 365 * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter.
emilmont 80:8e73be2a2ac1 366 *
emilmont 80:8e73be2a2ac1 367 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 368 */
emilmont 80:8e73be2a2ac1 369 SVCALL(SD_NVIC_CRITICAL_REGION_EXIT, uint32_t, sd_nvic_critical_region_exit(uint8_t is_nested_critical_region));
emilmont 80:8e73be2a2ac1 370
emilmont 80:8e73be2a2ac1 371 /**@brief Query the capacity of the application random pool.
emilmont 80:8e73be2a2ac1 372 *
emilmont 80:8e73be2a2ac1 373 * @param[out] p_pool_capacity The capacity of the pool.
emilmont 80:8e73be2a2ac1 374 *
emilmont 80:8e73be2a2ac1 375 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 376 */
emilmont 80:8e73be2a2ac1 377 SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity));
emilmont 80:8e73be2a2ac1 378
emilmont 80:8e73be2a2ac1 379 /**@brief Get number of random bytes available to the application.
emilmont 80:8e73be2a2ac1 380 *
emilmont 80:8e73be2a2ac1 381 * @param[out] p_bytes_available The number of bytes currently available in the pool.
emilmont 80:8e73be2a2ac1 382 *
emilmont 80:8e73be2a2ac1 383 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 384 */
emilmont 80:8e73be2a2ac1 385 SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available));
emilmont 80:8e73be2a2ac1 386
emilmont 80:8e73be2a2ac1 387 /**@brief Get random bytes from the application pool.
emilmont 80:8e73be2a2ac1 388
emilmont 80:8e73be2a2ac1 389 @param[out] p_buff Pointer to unit8_t buffer for storing the bytes.
emilmont 80:8e73be2a2ac1 390 @param[in] length Number of bytes to take from pool and place in p_buff.
emilmont 80:8e73be2a2ac1 391
emilmont 80:8e73be2a2ac1 392 @retval ::NRF_SUCCESS The requested bytes were written to p_buff.
emilmont 80:8e73be2a2ac1 393 @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available.
emilmont 80:8e73be2a2ac1 394 */
emilmont 80:8e73be2a2ac1 395 SVCALL(SD_RAND_APPLICATION_GET_VECTOR, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length));
emilmont 80:8e73be2a2ac1 396
emilmont 80:8e73be2a2ac1 397 /**@brief Gets the reset reason register.
emilmont 80:8e73be2a2ac1 398 *
emilmont 80:8e73be2a2ac1 399 * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register.
emilmont 80:8e73be2a2ac1 400 *
emilmont 80:8e73be2a2ac1 401 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 402 */
emilmont 80:8e73be2a2ac1 403 SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason));
emilmont 80:8e73be2a2ac1 404
emilmont 80:8e73be2a2ac1 405 /**@brief Clears the bits of the reset reason register.
emilmont 80:8e73be2a2ac1 406 *
emilmont 80:8e73be2a2ac1 407 * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register.
emilmont 80:8e73be2a2ac1 408 *
emilmont 80:8e73be2a2ac1 409 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 410 */
emilmont 80:8e73be2a2ac1 411 SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk));
emilmont 80:8e73be2a2ac1 412
emilmont 80:8e73be2a2ac1 413 /**@brief Sets the power mode when in CPU sleep.
emilmont 80:8e73be2a2ac1 414 *
emilmont 80:8e73be2a2ac1 415 * @param[in] power_mode The power mode to use when in CPU sleep. @sa sd_app_evt_wait
emilmont 80:8e73be2a2ac1 416 *
emilmont 80:8e73be2a2ac1 417 * @retval ::NRF_SUCCESS The power mode was set.
emilmont 80:8e73be2a2ac1 418 * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown.
emilmont 80:8e73be2a2ac1 419 */
emilmont 80:8e73be2a2ac1 420 SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(nrf_power_mode_t power_mode));
emilmont 80:8e73be2a2ac1 421
emilmont 80:8e73be2a2ac1 422 /**@brief Puts the chip in System OFF mode.
emilmont 80:8e73be2a2ac1 423 *
emilmont 80:8e73be2a2ac1 424 * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN
emilmont 80:8e73be2a2ac1 425 */
emilmont 80:8e73be2a2ac1 426 SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void));
emilmont 80:8e73be2a2ac1 427
emilmont 80:8e73be2a2ac1 428 /**@brief Enables or disables the power-fail comparator.
emilmont 80:8e73be2a2ac1 429 *
emilmont 80:8e73be2a2ac1 430 * Enabling this will give a softdevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs.
emilmont 80:8e73be2a2ac1 431 * The event can be retrieved with sd_evt_get();
emilmont 80:8e73be2a2ac1 432 *
emilmont 80:8e73be2a2ac1 433 * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled.
emilmont 80:8e73be2a2ac1 434 *
emilmont 80:8e73be2a2ac1 435 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 436 */
emilmont 80:8e73be2a2ac1 437 SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable));
emilmont 80:8e73be2a2ac1 438
emilmont 80:8e73be2a2ac1 439 /**@brief Sets the power-fail threshold value.
emilmont 80:8e73be2a2ac1 440 *
emilmont 80:8e73be2a2ac1 441 * @param[in] threshold The power-fail threshold value to use.
emilmont 80:8e73be2a2ac1 442 *
emilmont 80:8e73be2a2ac1 443 * @retval ::NRF_SUCCESS The power failure threshold was set.
emilmont 80:8e73be2a2ac1 444 * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown.
emilmont 80:8e73be2a2ac1 445 */
emilmont 80:8e73be2a2ac1 446 SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(nrf_power_failure_threshold_t threshold));
emilmont 80:8e73be2a2ac1 447
emilmont 80:8e73be2a2ac1 448 /**@brief Sets bits in the NRF_POWER->RAMON register.
emilmont 80:8e73be2a2ac1 449 *
emilmont 80:8e73be2a2ac1 450 * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register.
emilmont 80:8e73be2a2ac1 451 *
emilmont 80:8e73be2a2ac1 452 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 453 */
emilmont 80:8e73be2a2ac1 454 SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon));
emilmont 80:8e73be2a2ac1 455
emilmont 80:8e73be2a2ac1 456 /** @brief Clears bits in the NRF_POWER->RAMON register.
emilmont 80:8e73be2a2ac1 457 *
emilmont 80:8e73be2a2ac1 458 * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register.
emilmont 80:8e73be2a2ac1 459 *
emilmont 80:8e73be2a2ac1 460 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 461 */
emilmont 80:8e73be2a2ac1 462 SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon));
emilmont 80:8e73be2a2ac1 463
emilmont 80:8e73be2a2ac1 464 /**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks.
emilmont 80:8e73be2a2ac1 465 *
emilmont 80:8e73be2a2ac1 466 * @param[out] p_ramon Content of NRF_POWER->RAMON register.
emilmont 80:8e73be2a2ac1 467 *
emilmont 80:8e73be2a2ac1 468 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 469 */
emilmont 80:8e73be2a2ac1 470 SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon));
emilmont 80:8e73be2a2ac1 471
emilmont 80:8e73be2a2ac1 472 /**@brief Set bits in the NRF_POWER->GPREGRET register.
emilmont 80:8e73be2a2ac1 473 *
emilmont 80:8e73be2a2ac1 474 * @param[in] gpregret_msk Bits to be set in the GPREGRET register.
emilmont 80:8e73be2a2ac1 475 *
emilmont 80:8e73be2a2ac1 476 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 477 */
emilmont 80:8e73be2a2ac1 478 SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_msk));
emilmont 80:8e73be2a2ac1 479
emilmont 80:8e73be2a2ac1 480 /**@brief Clear bits in the NRF_POWER->GPREGRET register.
emilmont 80:8e73be2a2ac1 481 *
emilmont 80:8e73be2a2ac1 482 * @param[in] gpregret_msk Bits to be clear in the GPREGRET register.
emilmont 80:8e73be2a2ac1 483 *
emilmont 80:8e73be2a2ac1 484 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 485 */
emilmont 80:8e73be2a2ac1 486 SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_msk));
emilmont 80:8e73be2a2ac1 487
emilmont 80:8e73be2a2ac1 488 /**@brief Get contents of the NRF_POWER->GPREGRET register.
emilmont 80:8e73be2a2ac1 489 *
emilmont 80:8e73be2a2ac1 490 * @param[out] p_gpregret Contents of the GPREGRET register.
emilmont 80:8e73be2a2ac1 491 *
emilmont 80:8e73be2a2ac1 492 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 493 */
emilmont 80:8e73be2a2ac1 494 SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t *p_gpregret));
emilmont 80:8e73be2a2ac1 495
emilmont 80:8e73be2a2ac1 496 /**@brief Sets the DCDC mode.
emilmont 80:8e73be2a2ac1 497 *
emilmont 80:8e73be2a2ac1 498 * Depending on the internal state of the SoftDevice, the mode change may not happen immediately.
emilmont 80:8e73be2a2ac1 499 * The DCDC mode switch will be blocked when occurring in close proximity to radio transmissions. When
emilmont 80:8e73be2a2ac1 500 * the radio transmission is done, the last mode will be used.
emilmont 80:8e73be2a2ac1 501 *
emilmont 80:8e73be2a2ac1 502 * @param[in] dcdc_mode The mode of the DCDC.
emilmont 80:8e73be2a2ac1 503 *
emilmont 80:8e73be2a2ac1 504 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 505 * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid.
emilmont 80:8e73be2a2ac1 506 */
emilmont 80:8e73be2a2ac1 507 SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(nrf_power_dcdc_mode_t dcdc_mode));
emilmont 80:8e73be2a2ac1 508
emilmont 80:8e73be2a2ac1 509 /**@brief Request the high frequency crystal oscillator.
emilmont 80:8e73be2a2ac1 510 *
emilmont 80:8e73be2a2ac1 511 * Will start the high frequency crystal oscillator, the startup time of the crystal varies
emilmont 80:8e73be2a2ac1 512 * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started.
emilmont 80:8e73be2a2ac1 513 *
emilmont 80:8e73be2a2ac1 514 * @see sd_clock_hfclk_is_running
emilmont 80:8e73be2a2ac1 515 * @see sd_clock_hfclk_release
emilmont 80:8e73be2a2ac1 516 *
emilmont 80:8e73be2a2ac1 517 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 518 */
emilmont 80:8e73be2a2ac1 519 SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void));
emilmont 80:8e73be2a2ac1 520
emilmont 80:8e73be2a2ac1 521 /**@brief Releases the high frequency crystal oscillator.
emilmont 80:8e73be2a2ac1 522 *
emilmont 80:8e73be2a2ac1 523 * Will stop the high frequency crystal oscillator, this happens immediately.
emilmont 80:8e73be2a2ac1 524 *
emilmont 80:8e73be2a2ac1 525 * @see sd_clock_hfclk_is_running
emilmont 80:8e73be2a2ac1 526 * @see sd_clock_hfclk_request
emilmont 80:8e73be2a2ac1 527 *
emilmont 80:8e73be2a2ac1 528 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 529 */
emilmont 80:8e73be2a2ac1 530 SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void));
emilmont 80:8e73be2a2ac1 531
emilmont 80:8e73be2a2ac1 532 /**@brief Checks if the high frequency crystal oscillator is running.
emilmont 80:8e73be2a2ac1 533 *
emilmont 80:8e73be2a2ac1 534 * @see sd_clock_hfclk_request
emilmont 80:8e73be2a2ac1 535 * @see sd_clock_hfclk_release
emilmont 80:8e73be2a2ac1 536 *
emilmont 80:8e73be2a2ac1 537 * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not.
emilmont 80:8e73be2a2ac1 538 *
emilmont 80:8e73be2a2ac1 539 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 540 */
emilmont 80:8e73be2a2ac1 541 SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running));
emilmont 80:8e73be2a2ac1 542
emilmont 80:8e73be2a2ac1 543 /**@brief Waits for an application event.
emilmont 80:8e73be2a2ac1 544 *
emilmont 80:8e73be2a2ac1 545 * An application event is either an application interrupt or a pended interrupt when the
emilmont 80:8e73be2a2ac1 546 * interrupt is disabled. When the interrupt is enabled it will be taken immediately since
emilmont 80:8e73be2a2ac1 547 * this function will wait in thread mode, then the execution will return in the application's
emilmont 80:8e73be2a2ac1 548 * main thread. When an interrupt is disabled and gets pended it will return to the application's
emilmont 80:8e73be2a2ac1 549 * thread main. The application must ensure that the pended flag is cleared using
emilmont 80:8e73be2a2ac1 550 * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for
emilmont 80:8e73be2a2ac1 551 * disabled interrupts, as the interrupt handler will clear the pending flag automatically for
emilmont 80:8e73be2a2ac1 552 * enabled interrupts.
emilmont 80:8e73be2a2ac1 553 *
emilmont 80:8e73be2a2ac1 554 * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0
emilmont 80:8e73be2a2ac1 555 * System Control Register (SCR). @sa CMSIS_SCB
emilmont 80:8e73be2a2ac1 556 *
emilmont 80:8e73be2a2ac1 557 * @note If an application interrupt has happened since the last time sd_app_evt_wait was
emilmont 80:8e73be2a2ac1 558 * called this function will return immediately and not go to sleep. This is to avoid race
emilmont 80:8e73be2a2ac1 559 * conditions that can occur when a flag is updated in the interrupt handler and processed
emilmont 80:8e73be2a2ac1 560 * in the main loop.
emilmont 80:8e73be2a2ac1 561 *
emilmont 80:8e73be2a2ac1 562 * @post An application interrupt has happened or a interrupt pending flag is set.
emilmont 80:8e73be2a2ac1 563 *
emilmont 80:8e73be2a2ac1 564 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 565 */
emilmont 80:8e73be2a2ac1 566 SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void));
emilmont 80:8e73be2a2ac1 567
emilmont 80:8e73be2a2ac1 568 /**@brief Get PPI channel enable register contents.
emilmont 80:8e73be2a2ac1 569 *
emilmont 80:8e73be2a2ac1 570 * @param[out] p_channel_enable The contents of the PPI CHEN register.
emilmont 80:8e73be2a2ac1 571 *
emilmont 80:8e73be2a2ac1 572 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 573 */
emilmont 80:8e73be2a2ac1 574 SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable));
emilmont 80:8e73be2a2ac1 575
emilmont 80:8e73be2a2ac1 576 /**@brief Set PPI channel enable register.
emilmont 80:8e73be2a2ac1 577 *
emilmont 80:8e73be2a2ac1 578 * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register.
emilmont 80:8e73be2a2ac1 579 *
emilmont 80:8e73be2a2ac1 580 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 581 */
emilmont 80:8e73be2a2ac1 582 SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk));
emilmont 80:8e73be2a2ac1 583
emilmont 80:8e73be2a2ac1 584 /**@brief Clear PPI channel enable register.
emilmont 80:8e73be2a2ac1 585 *
emilmont 80:8e73be2a2ac1 586 * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register.
emilmont 80:8e73be2a2ac1 587 *
emilmont 80:8e73be2a2ac1 588 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 589 */
emilmont 80:8e73be2a2ac1 590 SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk));
emilmont 80:8e73be2a2ac1 591
emilmont 80:8e73be2a2ac1 592 /**@brief Assign endpoints to a PPI channel.
emilmont 80:8e73be2a2ac1 593 *
emilmont 80:8e73be2a2ac1 594 * @param[in] channel_num Number of the PPI channel to assign.
emilmont 80:8e73be2a2ac1 595 * @param[in] evt_endpoint Event endpoint of the PPI channel.
emilmont 80:8e73be2a2ac1 596 * @param[in] task_endpoint Task endpoint of the PPI channel.
emilmont 80:8e73be2a2ac1 597 *
emilmont 80:8e73be2a2ac1 598 * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid.
emilmont 80:8e73be2a2ac1 599 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 600 */
emilmont 80:8e73be2a2ac1 601 SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint));
emilmont 80:8e73be2a2ac1 602
emilmont 80:8e73be2a2ac1 603 /**@brief Task to enable a channel group.
emilmont 80:8e73be2a2ac1 604 *
emilmont 80:8e73be2a2ac1 605 * @param[in] group_num Number of the channel group.
emilmont 80:8e73be2a2ac1 606 *
emilmont 80:8e73be2a2ac1 607 * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid
emilmont 80:8e73be2a2ac1 608 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 609 */
emilmont 80:8e73be2a2ac1 610 SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num));
emilmont 80:8e73be2a2ac1 611
emilmont 80:8e73be2a2ac1 612 /**@brief Task to disable a channel group.
emilmont 80:8e73be2a2ac1 613 *
emilmont 80:8e73be2a2ac1 614 * @param[in] group_num Number of the PPI group.
emilmont 80:8e73be2a2ac1 615 *
emilmont 80:8e73be2a2ac1 616 * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
emilmont 80:8e73be2a2ac1 617 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 618 */
emilmont 80:8e73be2a2ac1 619 SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num));
emilmont 80:8e73be2a2ac1 620
emilmont 80:8e73be2a2ac1 621 /**@brief Assign PPI channels to a channel group.
emilmont 80:8e73be2a2ac1 622 *
emilmont 80:8e73be2a2ac1 623 * @param[in] group_num Number of the channel group.
emilmont 80:8e73be2a2ac1 624 * @param[in] channel_msk Mask of the channels to assign to the group.
emilmont 80:8e73be2a2ac1 625 *
emilmont 80:8e73be2a2ac1 626 * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
emilmont 80:8e73be2a2ac1 627 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 628 */
emilmont 80:8e73be2a2ac1 629 SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk));
emilmont 80:8e73be2a2ac1 630
emilmont 80:8e73be2a2ac1 631 /**@brief Gets the PPI channels of a channel group.
emilmont 80:8e73be2a2ac1 632 *
emilmont 80:8e73be2a2ac1 633 * @param[in] group_num Number of the channel group.
emilmont 80:8e73be2a2ac1 634 * @param[out] p_channel_msk Mask of the channels assigned to the group.
emilmont 80:8e73be2a2ac1 635 *
emilmont 80:8e73be2a2ac1 636 * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
emilmont 80:8e73be2a2ac1 637 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 638 */
emilmont 80:8e73be2a2ac1 639 SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk));
emilmont 80:8e73be2a2ac1 640
emilmont 80:8e73be2a2ac1 641 /**@brief Configures the Radio Notification signal.
emilmont 80:8e73be2a2ac1 642 *
emilmont 80:8e73be2a2ac1 643 * @note
emilmont 80:8e73be2a2ac1 644 * - The notification signal latency depends on the interrupt priority settings of SWI used
emilmont 80:8e73be2a2ac1 645 * for notification signal.
emilmont 80:8e73be2a2ac1 646 * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice
emilmont 80:8e73be2a2ac1 647 * will interrupt the application to do Radio Event preparation.
emilmont 80:8e73be2a2ac1 648 * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have
emilmont 80:8e73be2a2ac1 649 * to shorten the connection events to have time for the Radio Notification signals.
emilmont 80:8e73be2a2ac1 650 *
emilmont 80:8e73be2a2ac1 651 * @param[in] type Type of notification signal.
emilmont 80:8e73be2a2ac1 652 * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio
emilmont 80:8e73be2a2ac1 653 * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is
emilmont 80:8e73be2a2ac1 654 * recommended (but not required) to be used with
emilmont 80:8e73be2a2ac1 655 * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE.
emilmont 80:8e73be2a2ac1 656 *
emilmont 80:8e73be2a2ac1 657 * @param[in] distance Distance between the notification signal and start of radio activity.
emilmont 80:8e73be2a2ac1 658 * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or
emilmont 80:8e73be2a2ac1 659 * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used.
emilmont 80:8e73be2a2ac1 660 *
emilmont 80:8e73be2a2ac1 661 * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid.
emilmont 80:8e73be2a2ac1 662 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 663 */
emilmont 80:8e73be2a2ac1 664 SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(nrf_radio_notification_type_t type, nrf_radio_notification_distance_t distance));
emilmont 80:8e73be2a2ac1 665
emilmont 80:8e73be2a2ac1 666 /**@brief Encrypts a block according to the specified parameters.
emilmont 80:8e73be2a2ac1 667 *
emilmont 80:8e73be2a2ac1 668 * 128-bit AES encryption.
emilmont 80:8e73be2a2ac1 669 *
emilmont 80:8e73be2a2ac1 670 * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input
emilmont 80:8e73be2a2ac1 671 * parameters and one output parameter).
emilmont 80:8e73be2a2ac1 672 *
emilmont 80:8e73be2a2ac1 673 * @retval ::NRF_SUCCESS
emilmont 80:8e73be2a2ac1 674 */
emilmont 80:8e73be2a2ac1 675 SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data));
emilmont 80:8e73be2a2ac1 676
emilmont 80:8e73be2a2ac1 677 /**@brief Gets any pending events generated by the SoC API.
emilmont 80:8e73be2a2ac1 678 *
emilmont 80:8e73be2a2ac1 679 * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned.
emilmont 80:8e73be2a2ac1 680 *
emilmont 80:8e73be2a2ac1 681 * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending.
emilmont 80:8e73be2a2ac1 682 *
emilmont 80:8e73be2a2ac1 683 * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter.
emilmont 80:8e73be2a2ac1 684 * @retval ::NRF_ERROR_NOT_FOUND No pending events.
emilmont 80:8e73be2a2ac1 685 */
emilmont 80:8e73be2a2ac1 686 SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id));
emilmont 80:8e73be2a2ac1 687
emilmont 80:8e73be2a2ac1 688 /**@brief Get the temperature measured on the chip
emilmont 80:8e73be2a2ac1 689 *
emilmont 80:8e73be2a2ac1 690 * This function will block until the temperature measurement is done.
emilmont 80:8e73be2a2ac1 691 * It takes around 50us from call to return.
emilmont 80:8e73be2a2ac1 692 *
emilmont 80:8e73be2a2ac1 693 * @note Pan #28 in PAN-028 v 1.6 "Negative measured values are not represented correctly" is corrected by this function.
emilmont 80:8e73be2a2ac1 694 *
emilmont 80:8e73be2a2ac1 695 * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees celsius.
emilmont 80:8e73be2a2ac1 696 *
emilmont 80:8e73be2a2ac1 697 * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp
emilmont 80:8e73be2a2ac1 698 */
emilmont 80:8e73be2a2ac1 699 SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp));
emilmont 80:8e73be2a2ac1 700
emilmont 80:8e73be2a2ac1 701 /**@brief Flash Write
emilmont 80:8e73be2a2ac1 702 *
emilmont 80:8e73be2a2ac1 703 * Commands to write a buffer to flash
emilmont 80:8e73be2a2ac1 704 *
emilmont 80:8e73be2a2ac1 705 * This call initiates the flash access command, and its completion will be communicated to the
emilmont 80:8e73be2a2ac1 706 * application with exactly one of the following events:
emilmont 80:8e73be2a2ac1 707 * - NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
emilmont 80:8e73be2a2ac1 708 * - NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started.
emilmont 80:8e73be2a2ac1 709 *
emilmont 80:8e73be2a2ac1 710 * @note
emilmont 80:8e73be2a2ac1 711 * - This call takes control over the radio and the CPU during flash erase and write to make sure that
emilmont 80:8e73be2a2ac1 712 * they will not interfere with the flash access. This means that all interrupts will be blocked
emilmont 80:8e73be2a2ac1 713 * for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
emilmont 80:8e73be2a2ac1 714 * and the command parameters).
emilmont 80:8e73be2a2ac1 715 *
emilmont 80:8e73be2a2ac1 716 *
emilmont 80:8e73be2a2ac1 717 * @param[in] p_dst Pointer to start of flash location to be written.
emilmont 80:8e73be2a2ac1 718 * @param[in] p_src Pointer to buffer with data to be written
emilmont 80:8e73be2a2ac1 719 * @param[in] size Number of 32-bit words to write. Maximum size is 256 32bit words.
emilmont 80:8e73be2a2ac1 720 *
emilmont 80:8e73be2a2ac1 721 * @retval ::NRF_ERROR_INVALID_ADDR Tried to write to a non existing flash address, or p_dst or p_src was unaligned.
emilmont 80:8e73be2a2ac1 722 * @retval ::NRF_ERROR_BUSY The previous command has not yet completed.
emilmont 80:8e73be2a2ac1 723 * @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or more than 256 words.
emilmont 80:8e73be2a2ac1 724 * @retval ::NRF_ERROR_FORBIDDEN Tried to write to or read from protected location.
emilmont 80:8e73be2a2ac1 725 * @retval ::NRF_SUCCESS The command was accepted.
emilmont 80:8e73be2a2ac1 726 */
emilmont 80:8e73be2a2ac1 727 SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * const p_dst, uint32_t const * const p_src, uint32_t size));
emilmont 80:8e73be2a2ac1 728
emilmont 80:8e73be2a2ac1 729
emilmont 80:8e73be2a2ac1 730 /**@brief Flash Erase page
emilmont 80:8e73be2a2ac1 731 *
emilmont 80:8e73be2a2ac1 732 * Commands to erase a flash page
emilmont 80:8e73be2a2ac1 733 *
emilmont 80:8e73be2a2ac1 734 * This call initiates the flash access command, and its completion will be communicated to the
emilmont 80:8e73be2a2ac1 735 * application with exactly one of the following events:
emilmont 80:8e73be2a2ac1 736 * - NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
emilmont 80:8e73be2a2ac1 737 * - NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started.
emilmont 80:8e73be2a2ac1 738 *
emilmont 80:8e73be2a2ac1 739 * @note
emilmont 80:8e73be2a2ac1 740 * - This call takes control over the radio and the CPU during flash erase and write to make sure that
emilmont 80:8e73be2a2ac1 741 * they will not interfere with the flash access. This means that all interrupts will be blocked
emilmont 80:8e73be2a2ac1 742 * for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
emilmont 80:8e73be2a2ac1 743 * and the command parameters).
emilmont 80:8e73be2a2ac1 744 *
emilmont 80:8e73be2a2ac1 745 *
emilmont 80:8e73be2a2ac1 746 * @param[in] page_number Pagenumber of the page to erase
emilmont 80:8e73be2a2ac1 747 * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error.
emilmont 80:8e73be2a2ac1 748 * @retval ::NRF_ERROR_INVALID_ADDR Tried to erase to a non existing flash page.
emilmont 80:8e73be2a2ac1 749 * @retval ::NRF_ERROR_BUSY The previous command has not yet completed.
emilmont 80:8e73be2a2ac1 750 * @retval ::NRF_ERROR_FORBIDDEN Tried to erase a protected page.
emilmont 80:8e73be2a2ac1 751 * @retval ::NRF_SUCCESS The command was accepted.
emilmont 80:8e73be2a2ac1 752 */
emilmont 80:8e73be2a2ac1 753 SVCALL(SD_FLASH_ERASE_PAGE, uint32_t, sd_flash_page_erase(uint32_t page_number));
emilmont 80:8e73be2a2ac1 754
emilmont 80:8e73be2a2ac1 755
emilmont 80:8e73be2a2ac1 756 /**@brief Flash Protection set
emilmont 80:8e73be2a2ac1 757 *
emilmont 80:8e73be2a2ac1 758 * Commands to set the flash protection registers PROTENSETx
emilmont 80:8e73be2a2ac1 759 *
emilmont 80:8e73be2a2ac1 760 * @note To read the values in PROTENSETx you can read them directly. They are only write-protected.
emilmont 80:8e73be2a2ac1 761 *
emilmont 80:8e73be2a2ac1 762 * @param[in] protenset0 Value to be written to PROTENSET0
emilmont 80:8e73be2a2ac1 763 * @param[in] protenset1 Value to be written to PROTENSET1
emilmont 80:8e73be2a2ac1 764 *
emilmont 80:8e73be2a2ac1 765 * @retval ::NRF_ERROR_FORBIDDEN Tried to protect the SoftDevice
emilmont 80:8e73be2a2ac1 766 * @retval ::NRF_SUCCESS Values successfully written to PROTENSETx
emilmont 80:8e73be2a2ac1 767 */
emilmont 80:8e73be2a2ac1 768 SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t protenset0, uint32_t protenset1));
emilmont 80:8e73be2a2ac1 769
emilmont 80:8e73be2a2ac1 770
emilmont 80:8e73be2a2ac1 771 /** @} */
emilmont 80:8e73be2a2ac1 772
emilmont 80:8e73be2a2ac1 773 #endif // NRF_SOC_H__
emilmont 80:8e73be2a2ac1 774
emilmont 80:8e73be2a2ac1 775 /**
emilmont 80:8e73be2a2ac1 776 @}
emilmont 80:8e73be2a2ac1 777 */