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Last commit 20 Feb 2019 by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h
- Revision:
- 613:bc40b8d2aec4
- Parent:
- 532:fe11edbda85c
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h Tue Aug 18 15:00:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h Thu Aug 20 10:45:13 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f407xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 + * @version V2.3.2 + * @date 26-June-2015 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. * * This file contains: @@ -937,16 +937,13 @@ #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ @@ -3556,11 +3553,15 @@ #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ -#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */ #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -3597,11 +3598,15 @@ #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ -#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */ #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -3638,11 +3643,15 @@ #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ -#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */ #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -3684,6 +3693,10 @@ #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -3720,11 +3733,15 @@ #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ -#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */ #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -3761,11 +3778,15 @@ #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ -#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */ #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -3802,11 +3823,15 @@ #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ -#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */ #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -3848,6 +3873,10 @@ #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ +#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ +#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ +#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ +#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ @@ -5120,7 +5149,6 @@ #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) -#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) @@ -5354,7 +5382,7 @@ /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) -#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) +#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /******************** Bits definition for RTC_WUTR register *****************/ #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
